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Abstract

Long-term reliability of semiconductors is a key concern for both emerging high reliability markets and continuous fabrication process innovation approaching the anticipated minimum of achievable gate length. Unexpected aging-induced failures are unacceptable in safety-critical products, and increasing variability in smaller transistors aggravates these risks. Prior research efforts to better monitor, characterize, and qualify semiconductor reliability are significant but still suffer from major limitations regarding uncertainty quantification, multiple aging mechanisms, and complex variability sources. Addressing these gaps, this research work contributes on-chip sensor designs for improved isolation of key aging mechanisms alongside novel physical modelling and predictive Bayesian experimental design approaches leveraging recent advances in probabilistic programming. The suite of on-chip sensors provide improved physical mechanism isolation and sophisticated read-out functionality over existing circuits in the literature, enabling fine-grained monitoring of semiconductor aging. All sensors are successfully implemented and evaluated using custom 12nm FinFET chip designs. The developed computational Bayesian modelling and experimental design components provide capabilities for separation of epistemic and aleatoric uncertainty in physical models, multi-level variability modelling, and a quantitative basis for accelerated life test optimization that accounts for engineering costs and risks. These features are not found in prior statistical frameworks for semiconductor reliability, uniquely allowing for accelerated test cost optimization, characterization of chip- and lot-level variability, and uncertainty-aware product lifespan predictions. This research is also, based on comprehensive literature review, one of the first applications of predictive computational Bayesian experimental design in any domain. The developed contributions act as robust components towards comprehensive high reliability monitoring and qualification strategies and help tackle growing variability concerns. Future work on useability, application demonstration, and feature enhancement provides a pathway for feasible regulation and in-field management, aiding global efforts to improve consumer protections for e-waste reduction and to ensure safety-critical product operation.