Applied Science, Faculty of
Electrical and Computer Engineering, Department of
DSpace
UBCV
Hill, Ian Robert McCluny
Doctor of Philosophy - PhD
University of British Columbia
Long-term reliability of semiconductors is a key concern for both emerging high reliability markets and continuous fabrication process innovation approaching the anticipated minimum of achievable gate length. Unexpected aging-induced failures are unacceptable in safety-critical products, and increasing variability in smaller transistors aggravates these risks. Prior research efforts to better monitor, characterize, and qualify semiconductor reliability are significant but still suffer from major limitations regarding uncertainty quantification, multiple aging mechanisms, and complex variability sources. Addressing these gaps, this research work contributes on-chip sensor designs for improved isolation of key aging mechanisms alongside novel physical modelling and predictive Bayesian experimental design approaches leveraging recent advances in probabilistic programming. The suite of on-chip sensors provide improved physical mechanism isolation and sophisticated read-out functionality over existing circuits in the literature, enabling fine-grained monitoring of semiconductor aging. All sensors are successfully implemented and evaluated using custom 12nm FinFET chip designs. The developed computational Bayesian modelling and experimental design components provide capabilities for separation of epistemic and aleatoric uncertainty in physical models, multi-level variability modelling, and a quantitative basis for accelerated life test optimization that accounts for engineering costs and risks. These features are not found in prior statistical frameworks for semiconductor reliability, uniquely allowing for accelerated test cost optimization, characterization of chip- and lot-level variability, and uncertainty-aware product lifespan predictions. This research is also, based on comprehensive literature review, one of the first applications of predictive computational Bayesian experimental design in any domain. The developed contributions act as robust components towards comprehensive high reliability monitoring and qualification strategies and help tackle growing variability concerns. Future work on useability, application demonstration, and feature enhancement provides a pathway for feasible regulation and in-field management, aiding global efforts to improve consumer protections for e-waste reduction and to ensure safety-critical product operation.
Long-Term Reliability Monitoring andQualification Strategies for IntegratedCircuitsbyIan Robert McCluny HillB.A.Sc., The University of Waterloo, 2020A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFDOCTOR OF PHILOSOPHYinThe Faculty of Graduate and Postdoctoral Studies(Electrical and Computer Engineering)THE UNIVERSITY OF BRITISH COLUMBIA(Vancouver)October 2025© Ian Robert McCluny Hill 2025The following individuals certify that they have read, and recommend to the Faculty ofGraduate and Postdoctoral Studies for acceptance, the dissertation entitled:Long-Term Reliability Monitoring and Qualification Strategies for Integrated Circuitssubmitted by Ian Robert McCluny Hill in partial fulfilment of the requirements forthe degree of Doctor of Philosophyin Electrical and Computer EngineeringExamining Committee:Andre´ Ivanov, Professor, Electrical and Computer Engineering, UBCSupervisorSudip Shekhar, Professor, Electrical and Computer Engineering, UBCSupervisory Committee MemberNatalia Nolde, Professor, Statistics, UBCUniversity ExaminerGuangrui Xia, Associate Professor, Materials Engineering, UBCUniversity ExaminerGeorges Gielen, Professor, Electrical Engineering, Katholieke Universiteit LeuvenExternal ExaminerAdditional Supervisory Committee Members:Prashant Nair, Assistant Professor, Electrical and Computer Engineering, UBCSupervisory Committee MemberiiAbstractLong-term reliability of semiconductors is a key concern for both emerging high reliabilitymarkets and continuous fabrication process innovation approaching the anticipated min-imum of achievable gate length. Unexpected aging-induced failures are unacceptable insafety-critical products, and increasing variability in smaller transistors aggravates theserisks. Prior research efforts to better monitor, characterize, and qualify semiconductorreliability are significant but still suffer from major limitations regarding uncertaintyquantification, multiple aging mechanisms, and complex variability sources. Addressingthese gaps, this research work contributes on-chip sensor designs for improved isolationof key aging mechanisms alongside novel physical modelling and predictive Bayesian ex-perimental design approaches leveraging recent advances in probabilistic programming.The suite of on-chip sensors provide improved physical mechanism isolation and so-phisticated read-out functionality over existing circuits in the literature, enabling fine-grained monitoring of semiconductor aging. All sensors are successfully implementedand evaluated using custom 12nm FinFET chip designs. The developed computationalBayesian modelling and experimental design components provide capabilities for sepa-ration of epistemic and aleatoric uncertainty in physical models, multi-level variabilitymodelling, and a quantitative basis for accelerated life test optimization that accounts forengineering costs and risks. These features are not found in prior statistical frameworksfor semiconductor reliability, uniquely allowing for accelerated test cost optimization,characterization of chip- and lot-level variability, and uncertainty-aware product lifes-pan predictions. This research is also, based on comprehensive literature review, one ofthe first applications of predictive computational Bayesian experimental design in anydomain.The developed contributions act as robust components towards comprehensive highreliability monitoring and qualification strategies and help tackle growing variability con-cerns. Future work on useability, application demonstration, and feature enhancementprovides a pathway for feasible regulation and in-field management, aiding global ef-forts to improve consumer protections for e-waste reduction and to ensure safety-criticalproduct operation.iiiLay SummaryWhile semiconductors are increasingly used to control safety-critical systems, transistorsare shrinking to where single atom defects significantly affect aging. Current industrialand research methods for evaluating reliability are not rigorous enough in quantifying theuncertainty of predictions or modelling complex sources of variability, risking unexpectedaging-induced failures in critical next-generation products. This research introduces sev-eral on-chip aging sensors that track the progression of different transistor defect forma-tion physics, a probabilistic physics modelling framework that carefully incorporates un-certainty and variability, and an experimental design approach for optimizing acceleratedstress tests to meet rigorous reliability requirements with consideration for engineeringcosts and risks. Custom semiconductor chips and emerging probabilistic programmingtechniques are used to implement the research contributions, which are then validatedthrough tests and detailed case studies. These contributions represent key componentstowards a comprehensive qualification strategy for ensuring safe long-term operation ofatomic-scale transistors in critical applications.ivPrefaceThe research effort presented in this dissertation, including problem identification, so-lution design, implementation, analysis, and evaluation is the sole work of the author,conducted while a member of the Ivanov SoC Lab, subject to the following exceptions:• An early literature review for the CMOS reliability survey paper [1] that first iden-tified several of the cited works (mainly in Ch. 1) was a joint effort by the IvanovSoC Lab. Additionally, Y. Elhagrasy assisted with finding relevant works for theelectromigration sensor literature review presented in Sec. 2.5. Presented analysisof the research in these cited works remains the sole work of the author.• Ivanov SoC Lab researchers contributed to several sections of the CMOS reliabilitysurvey paper [1] that were revised for Sec. 1.4 (P. Chanawala), Sec. 1.6.1 (Dr. A.Sheikholeslam), and Table 1.1 (P. Chanawala). All review, analysis, and contentin these sections has been significantly updated, improved, and revised in thisdissertation by the author, but the original versions were important precursors.• M. Rendo´n prepared Figs. 3.4 and 3.3 as part of his contribution to the inducedoffset sensor conference paper [2], used with permission.• Though the author was significantly involved in the direction, technical effort, re-sults analysis, and mentorship for the gate leakage sensor and associated TC2 chipdesign, the lead researcher for this project was Ivanov SoC Lab Master’s studentM. Rendo´n. Significant portions of Secs. 2.4, 3.1.5, 3.2, 3.3.4, and 3.4 are based onhis technical work on design, 12nm implementation, test system revision, results,and analysis of the gate leakage sensor. They also contain several figures preparedby him for a corresponding publication [3] (used with permission).All preparation and writing of this dissertation remains the sole work of the author.As indicated in the discussion on collaboration, significant portions of the conductedresearch work have been published previously in journals and conferences. All previouslypublished work presented in this dissertation has been significantly rewritten and inmany places improved upon to fit the long-form dissertation structure and to addressshortcomings that were identified after publication.vPreface• Secs. 1.3, 1.4, 1.5, and 1.6 are revised and updated from published versions in [1]:I. Hill, P. Chanawala, R. Singh, S. A. Sheikholeslam, and A. Ivanov, “CMOS reliabilityfrom past to future: A survey of requirements, trends, and prediction methods,” IEEETransactions on Device and Materials Reliability, vol. 22, no. 1, pp. 1–18, 2022.• The oscillator-based sensor design presented in Chs. 2 and 3 is published in [4]:I. Hill, M. Rendo´n, and A. Ivanov, “Enhanced wear-out sensor design in a 12nm processfor separable stress regime monitoring,” in 2024 IEEE 42nd VLSI Test Symposium (VTS),2024, pp. 1–7.• The induced offset sensor design presented in Chs. 2 and 3 is published in [2]:I. Hill, M. Rendo´n, and A. Ivanov, “A novel induced offset voltage sensor for separable wear-out mechanism characterization in a 12nm FinFET process,” in 2024 IEEE InternationalReliability Physics Symposium (IRPS), 2024, pp. 8A.4–1–8A.4–9.• The gate leakage sensor design presented in Chs. 2 and 3 is published in [3]:M. Rendo´n, I. Hill, and A. Ivanov, “Gate leakage current integration-based dielectric break-down monitor in a 12nm FinFET process,” in 2025 IEEE 43rd VLSI Test Symposium(VTS), 2025, pp. 1–7.• Excepting the parallel Brent minimization algorithm, Ch. 5 is published in [5]:I. Hill and A. Ivanov, “Gerabaldi: A temporal simulator for probabilistic IC degradationand failure processes,” in 2023 IEEE 41st VLSI Test Symposium (VTS), 2023, pp. 1–7.• Though this dissertation provides significantly more detail, discusses the design ofthe software library for inference, and includes an additional case study, significantportions of Ch. 4 and Ch. 6 are published in [6]:I. Hill and A. Ivanov, “Multilevel variability and epistemic uncertainty analysis of reliabilityphysics models through hierarchical probabilistic modelling,” in 2025 IEEE InternationalReliability Physics Symposium (IRPS), 2025, pp. 1–6.All figures taken directly from these publications are permitted for dissertation use andcan be easily identified by disclaimers and citations in accordance with IEEE copyrightpolicy. Updated and revised versions of figures from these publications also refer to thesource works. All research work presented in Part III is unpublished and has not yetbeen submitted to a journal or conference at time of submitting this dissertation forpublication, but the work is intended for future publication.No part of the content of this dissertation was generated using artificial intelligence.The extent to which large language models were leveraged as part of the conductedresearch work is limited to use as a search engine to find particular library features ofMatplotlib, JAX, NumPy, and LaTeX (all contributed code in the developed open-sourcesoftware libraries remains hand-written), as well as to find particular vocabulary that hadslipped out of the author’s mind.viTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiLay Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiiList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiiiList of Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviiiList of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xixGlossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiiAcknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxv1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Historical Context for Semiconductor Reliability Engineering . . . . . . . 21.2 Formal Definition and Facets of Reliability . . . . . . . . . . . . . . . . . 31.3 Consequences of Evolving Semiconductor Markets . . . . . . . . . . . . . 51.3.1 Safety-Critical Market Growth . . . . . . . . . . . . . . . . . . . . 51.3.2 Low Reliability Market Concerns . . . . . . . . . . . . . . . . . . 61.4 Overview of Key Semiconductor Wear-Out and Failure Mechanisms . . . 81.4.1 Transistor Wear-Out and Failure Mechanisms . . . . . . . . . . . 91.4.2 Interconnect Wear-Out and Failure Mechanisms . . . . . . . . . . 121.5 Incoming Technical Challenges . . . . . . . . . . . . . . . . . . . . . . . . 131.5.1 Increasing Variability at Atomic Scales . . . . . . . . . . . . . . . 161.5.2 Increasing System Complexity . . . . . . . . . . . . . . . . . . . . 17viiTable of Contents1.5.3 Heat Dissipation and Failure Modes in Vertical Integration . . . . 171.6 Industrial Long-Term Reliability Qualification Practices . . . . . . . . . . 181.6.1 Standardized Product Demonstration Tests . . . . . . . . . . . . . 181.6.2 Per-Mechanism Investigation Recommendations . . . . . . . . . . 201.7 Areas for Improvement in Long-Term Reliability . . . . . . . . . . . . . . 221.7.1 Physics-of-Failure Investigations . . . . . . . . . . . . . . . . . . . 221.7.2 Measurement and Monitoring Techniques . . . . . . . . . . . . . . 231.7.3 Data Analysis Methods . . . . . . . . . . . . . . . . . . . . . . . . 231.7.4 Data Collection Schemes . . . . . . . . . . . . . . . . . . . . . . . 241.8 Research Contributions and Scope . . . . . . . . . . . . . . . . . . . . . . 25I Separable Wear-Out Mechanism Monitoring via On-Chip Sensors 272 On-Chip Sensor Designs for Isolated Mechanism Monitoring . . . . . 282.1 Explicating Transistor Stress Regimes . . . . . . . . . . . . . . . . . . . . 292.2 Isolating BTI and HCI via Modified Ring Oscillators . . . . . . . . . . . 312.2.1 Related Sensor Designs in Prior Literature . . . . . . . . . . . . . 312.2.2 Topology and Principle of Operation . . . . . . . . . . . . . . . . 332.3 Isolating BTI and HCI via Differential Offset Voltage Amplification . . . 352.3.1 Related Sensor Designs in Prior Literature . . . . . . . . . . . . . 352.3.2 Topology and Principle of Operation . . . . . . . . . . . . . . . . 362.4 Gate Leakage Current Sensing for TDDB Risk Assessment . . . . . . . . 402.4.1 Related Sensor Designs in Prior Literature . . . . . . . . . . . . . 412.4.2 Topology and Principle of Operation . . . . . . . . . . . . . . . . 422.5 Staggered EM Failure Sensor for Degradation Milestones . . . . . . . . . 432.5.1 Related Sensor Designs in Prior Literature . . . . . . . . . . . . . 442.5.2 Topology and Principle of Operation . . . . . . . . . . . . . . . . 453 Sensor Implementation, Testing, and Evaluation . . . . . . . . . . . . . 473.1 Physical Layout in 12nm FinFET . . . . . . . . . . . . . . . . . . . . . . 493.1.1 Front End Design Considerations . . . . . . . . . . . . . . . . . . 493.1.2 Back End Design Considerations . . . . . . . . . . . . . . . . . . . 503.1.3 Oscillator-Based Sensor Layout . . . . . . . . . . . . . . . . . . . 503.1.4 Induced Offset Voltage Sensor Layout . . . . . . . . . . . . . . . . 513.1.5 Gate Leakage Sensor Layout . . . . . . . . . . . . . . . . . . . . . 533.1.6 Staggered EM Sensor Layout . . . . . . . . . . . . . . . . . . . . . 543.2 Automated Accelerated Life Test System . . . . . . . . . . . . . . . . . . 55viiiTable of Contents3.2.1 Test Chip Host Board . . . . . . . . . . . . . . . . . . . . . . . . . 573.2.2 Test Control Board . . . . . . . . . . . . . . . . . . . . . . . . . . 593.2.3 Test Control Firmware in the Rust Programming Language . . . . 603.2.4 Computer Driver and Data Storage . . . . . . . . . . . . . . . . . 643.3 Test and Evaluation of Implemented Sensor Designs . . . . . . . . . . . . 643.3.1 Conducted Accelerated Life Tests . . . . . . . . . . . . . . . . . . 643.3.2 Oscillator-Based Sensor Validation . . . . . . . . . . . . . . . . . . 653.3.3 Induced Offset Voltage Sensor Validation . . . . . . . . . . . . . . 703.3.4 Gate Leakage Sensor Validation . . . . . . . . . . . . . . . . . . . 723.3.5 Staggered EM Sensor Validation . . . . . . . . . . . . . . . . . . . 733.4 Comments on Long-Term Reliability in Scaled FinFET Process Nodes . . 743.5 Part I Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . . 77II Probabilistic Modelling and Computational Bayesian Inferencefor Semiconductor Lifespan Prediction . . . . . . . . . . . . . . . . . . . 794 Probabilistic Physics-of-Failure Modelling . . . . . . . . . . . . . . . . . 804.1 Existing Semiconductor Long-Term Reliability Data Analysis Approaches 814.1.1 Enhanced Frequentist Statistical Methods . . . . . . . . . . . . . 814.1.2 Machine Learning Limitations for Long-Term Reliability Prediction 824.1.3 Introduction to Bayesian Reliability Analysis . . . . . . . . . . . . 834.2 Structured Probabilistic Models . . . . . . . . . . . . . . . . . . . . . . . 854.3 Hierarchical Probabilistic Physics-of-Failure Models . . . . . . . . . . . . 864.4 Probability Distributions for Hyper-Latent Variables . . . . . . . . . . . . 924.5 Useful Hyper-Latent Variable Transformations . . . . . . . . . . . . . . . 944.6 Interpretable Uncertainty Quantification . . . . . . . . . . . . . . . . . . 964.7 Uncertainty-Aware Metrics for Specifying Product Lifespan . . . . . . . . 984.7.1 Lower Bound Quantile Credible Interval . . . . . . . . . . . . . . 994.7.2 Highest Density Quantile Credible Region . . . . . . . . . . . . . 1005 Generative Modelling for In-Depth Aging Simulations . . . . . . . . . 1025.1 Structure of the Simulation Software . . . . . . . . . . . . . . . . . . . . 1035.2 Time-Varying Stress Simulation Method . . . . . . . . . . . . . . . . . . 1055.3 Parallel Brent’s Minimization Method . . . . . . . . . . . . . . . . . . . . 1075.4 Demonstrative Generative Modelling Studies . . . . . . . . . . . . . . . . 1095.4.1 Threshold Voltage Degradation Variability . . . . . . . . . . . . . 1095.4.2 Individual Defect TDDB Model Sensitivity . . . . . . . . . . . . . 111ixTable of Contents6 Computational Bayesian Inference of Physics-of-Failure Models . . . 1146.1 Bayesian Inference Background . . . . . . . . . . . . . . . . . . . . . . . . 1146.1.1 Hierarchical Model Inference Challenges . . . . . . . . . . . . . . 1156.1.2 Historical Knowledge Incorporation via Priors . . . . . . . . . . . 1166.2 Computational Inference Algorithms and Considerations . . . . . . . . . 1176.2.1 The No U-Turn Sampler . . . . . . . . . . . . . . . . . . . . . . . 1186.2.2 Defining Models for Effective NUTS Inference . . . . . . . . . . . 1196.3 Software Framework for Model Construction and Inference . . . . . . . . 1206.3.1 Software Design for Non-Expert Useability . . . . . . . . . . . . . 1216.3.2 Defining the Developed SPM Architecture as a Program . . . . . 1236.4 Computational Inference Case Studies . . . . . . . . . . . . . . . . . . . . 1256.4.1 Characterizing Group Variability in Generic Failure Data . . . . . 1256.4.2 Inference on Real-World NBTI Data . . . . . . . . . . . . . . . . . 1276.4.3 Inference on Sparse TDDB Data . . . . . . . . . . . . . . . . . . . 1296.5 Part II Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . 132III Predictive Bayesian Experimental Design for Optimized Long-Term Reliability Qualification . . . . . . . . . . . . . . . . . . . . . . . . . 1347 Semiconductor Accelerated Life Test Design Optimization . . . . . . 1357.1 Prior Literature on Accelerated Life Test Design . . . . . . . . . . . . . . 1367.1.1 Formalized Design of Accelerated Life Tests . . . . . . . . . . . . 1377.1.2 Reliability Demonstration Tests and Cost Awareness . . . . . . . 1387.1.3 Bayesian Accelerated Life Test Design . . . . . . . . . . . . . . . . 1397.1.4 Situating the Developed Accelerated Life Test Design Framework 1417.2 Information Gain in Computational Bayesian Experimental Design . . . 1427.2.1 Auxiliary Information Gain Statistics . . . . . . . . . . . . . . . . 1437.2.2 Threshold Information Gain as a Risk Measure . . . . . . . . . . . 1447.2.3 Limitations of Information Gain in Arbitrary Model Contexts . . 1457.3 Predictive Inference Formulations for Test Utility . . . . . . . . . . . . . 1467.3.1 Uncertainty-Aware Lifespan Metrics as Predictive Utility Measures 1477.4 Description of the Developed Accelerated Life Test Design Framework . . 1498 Implementing Computational Predictive Bayesian Experimental De-sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528.1 Necessary Software Infrastructure for Implementation . . . . . . . . . . . 1528.1.1 Existing Bayesian Experimental Design Software . . . . . . . . . . 153xTable of Contents8.1.2 Custom Algorithm Design Approach . . . . . . . . . . . . . . . . 1548.2 Necessary Importance Sampling Results . . . . . . . . . . . . . . . . . . . 1558.2.1 Importance Sampling from the Target . . . . . . . . . . . . . . . . 1568.2.2 Uniform Importance Sampling . . . . . . . . . . . . . . . . . . . . 1568.2.3 Importance Sampling from the Prior . . . . . . . . . . . . . . . . 1578.3 Computational Predictive Bayesian Experimental Design Algorithm . . . 1588.3.1 Summary Statistic Estimation Using Importance Weights . . . . . 1618.4 Hierarchical Latent Marginalization Algorithm . . . . . . . . . . . . . . . 1628.4.1 Marginalization Algorithm Validation . . . . . . . . . . . . . . . . 1649 Towards Rigorous and Uncertainty-Aware Semiconductor Long-TermReliability Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1679.1 High Temperature Operating Life Test Utility Analysis . . . . . . . . . . 1689.2 Illustrative Electromigration Qualification Procedure . . . . . . . . . . . 1769.3 Optimized Characterization of Per-Mechanism Sensor Test Chip . . . . . 1839.4 Part III Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . 19110 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19310.1 Developing Comprehensive Monitoring and Qualification Strategies . . . 19510.2 Directions for Future Efforts . . . . . . . . . . . . . . . . . . . . . . . . . 198Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201AppendicesA Parallel Brent’s Minimization Method . . . . . . . . . . . . . . . . . . . 221A.1 Logarithmic Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221A.2 Parallel Brent Minimization Pseudocode . . . . . . . . . . . . . . . . . . 222B Log Domain Transformations . . . . . . . . . . . . . . . . . . . . . . . . . 226B.1 Working with Log Probabilities . . . . . . . . . . . . . . . . . . . . . . . 227B.2 Log Domain Model Formulations . . . . . . . . . . . . . . . . . . . . . . . 228xiList of Tables1.1 Semiconductor markets reliability overview, revised from [1]. . . . . . . . . 53.1 Degradation magnitude ratios across BTI and HCI mechanisms observedwith different implemented sensors, revised and combined from [4] and [2]. 744.1 Recommended distributions for specifying continuous hyper-latent vari-ables in semiconductor reliability models, revised from [6]. . . . . . . . . . 937.1 Component measures of test utility considered within the research scope. 1508.1 Comparison of existing software libraries for BED. . . . . . . . . . . . . . 1538.2 Relative difference of inferences made using the custom latent marginal-ization algorithm in comparison to the state of the art NUTS algorithmacross three test cases targeting models similar to those used in application.1659.1 Maximum utility measure designs out of the multiple temperature HTOLvariants and comparisons to base HTOL. . . . . . . . . . . . . . . . . . . 175xiiList of Figures1.1 Bathtub curve representation of product reliability, adapted from [7]. . . . 41.2 Carrier trapping due to atomic defects formed from bias temperature in-stability in nanowire FETs. © 2022 IEEE [1]. . . . . . . . . . . . . . . . 91.3 Visualization of GAAFET gate dielectric defect formation leading to SILCand TDDB. © 2025 IEEE [3]. . . . . . . . . . . . . . . . . . . . . . . . . 121.4 Depiction of electromigration micro and macro impacts. © 2022 IEEE [1]. 121.5 Prior and projected timeline of semiconductor innovations, updated from[1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.1 Achievable maximal stress regimes in CMOS transistors with referenceidentifiers. Drain-source symmetry is assumed and bulk terminals ne-glected, revised from [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302.2 Schematics of the eight variants within the proposed RO-based sensordesign. Shading corresponds to the stress regimes experienced by eachtransistor during stress-mode operation when en is high. Revised from [4]. 332.3 Schematic of the threshold voltage sensor differential offset amplifier topol-ogy with measure mode analog bias voltage labels. Revised from [2]. . . . 372.4 Higher-level schematic of the full proposed differential offset amplifier sen-sor design showing supporting circuitry required for operation, revisedfrom [2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402.5 Schematic of the SILC sensor gate leakage current extraction circuit. Theen signal goes high during stress and drops to a logic low to begin ameasurement. Revised from [3]. . . . . . . . . . . . . . . . . . . . . . . . . 422.6 Schematic of the staggered electromigration failure sensor. Interconnectfailure state is visualized as a normally-closed switch. . . . . . . . . . . . . 453.1 Top-level layout of the TC1 chip. The RO-based sensor instance groupsand EM sensor are seen in the middle-left region, with the induced offsetsensor instances all contained within the lower-middle isolated analog region. 48xiiiList of Figures3.2 Abstracted view of the introduced interwoven layout technique for the ROsensors. © 2024 IEEE [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.3 Abstract view of the induced offset sensor core layout. © 2024 IEEE [2] . 523.4 Simulated gain and back-calculation uncertainty for the induced offset volt-age sensor core across process variability corners. © 2024 IEEE [2] . . . 523.5 Abstract FinFET layout view illustrating the SILC sensor implementationwith current mirror layout matching, revised from [3]. . . . . . . . . . . . 533.6 Abstract layout view of a staggered electromigration failure test line. Largerinterconnect cross-sectional areas are used except in the indicated EM fail-ure line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.7 Top-down photograph of the two custom boards that compose the auto-mated ALT system hardware. Two TC2 chips are seen on the right. ©2025 IEEE [3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563.8 Structural block diagram of the automated test system showing the variousdesign components and interfaces. . . . . . . . . . . . . . . . . . . . . . . 573.9 Printed circuit board layout for the TC1 host board. Ground plane copperlayer is hidden for visual clarity. . . . . . . . . . . . . . . . . . . . . . . . . 583.10 Printed circuit board layout for the automated ALT system control board. 593.11 Firmware architecture for the automated stress test system following asuper loop design paradigm. Arrows with hue indicate control flow, blackarrows indicate data transactions. . . . . . . . . . . . . . . . . . . . . . . . 613.12 Initial and post-settling free-running frequencies of implemented sensorinstances compared to simulated ranges across worst-case process cornersindicated by the brown dotted intervals. © 2024 IEEE [4]. . . . . . . . . 663.13 Observed frequency degradation for all sensor instances of each variantalongside violin plots with quartiles to approximate the observed distribu-tion, revised from [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673.14 Frequency difference between two interwoven RO sensors throughout theevaluation test demonstrating exceptional matching. Absolute frequencyis shown in the upper inset. © 2024 IEEE [4]. . . . . . . . . . . . . . . . 693.15 Mean degradation curves across 20 duplicates for each of the four inducedoffset sensor stress regimes. © 2024 IEEE [2]. . . . . . . . . . . . . . . . 693.16 Offset sensor variants output voltage shift after 1000 and 1500 hours ofstress. High degradation variability is observed between instances, espe-cially following the severe ET stress phase. © 2024 IEEE [2]. . . . . . . . 70xivList of Figures3.17 Relative increase in voltage ramp rate of individual SILC ramp sensors,grouped by variant and with associated summary statistics. © 2025 IEEE[3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723.18 Failure times across chips for one of the interconnect lines within the stag-gered EM sensor. Predicted MTTF from foundry modelling is includedfor comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733.19 Significant deviations in sensor measurements observed between differentchips. © 2024 IEEE [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763.20 Correlated degradation with initial measured value observed in the SILCramp sensor. © 2025 IEEE [3]. . . . . . . . . . . . . . . . . . . . . . . . . 764.1 Introduction to graphical representations of SPMs using resistor thermalnoise to illustrate different variable and parameter types. . . . . . . . . . . 874.2 Direct mapping of Black’s equation for electromigration failure time to astructured probabilistic model, revised from [6]. . . . . . . . . . . . . . . . 874.3 Mapping of Black’s equation to an SPM with stochastic behaviours intro-duced to the model parameters and stress conditions. . . . . . . . . . . . . 894.4 Mapping of Black’s equation to an SPM with stochastic model parametersand hierarchical priors to separate variability and uncertainty within themodel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904.5 Mapping of Black’s equation to the developed SPM architecture for semi-conductor reliability analyses with multilevel variability and uncertaintyquantification. © 2025 IEEE [6] . . . . . . . . . . . . . . . . . . . . . . . 914.6 Illustration of using variable transformations to constrain the domains ofrandom variables while minimizing distortion of mean and variance. . . . 954.7 Comparison of proposed lifespan metrics to MTTF when working with abimodal failure distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . 1015.1 Abstract representation of the data class model in the simulation tool,with the workflow indicated via blue arrows. © 2023 IEEE [5]. . . . . . . 1035.2 Temporal degradation behaviour in each of the three tests for the currentand new simulated processes. Series show mean degradation, ±1 standarddeviation is represented by the filled region. Revised from [5]. . . . . . . . 1105.3 End-of-test HTOL and LTOL degradation for current and new simulatedfabrication processes. Increased variability in HCI temperature depen-dence produces test violations under LTOL conditions. Revised from [5]. . 111xvList of Figures5.4 Fitted Weibull distributions to right-censored TDDB failure data simu-lated using the demonstrative temporal model across different values forparameter α. © 2023 IEEE [5]. . . . . . . . . . . . . . . . . . . . . . . . 1126.1 Abstract structural diagram of the software for performing CBI and ex-perimental design with custom wear-out models. . . . . . . . . . . . . . . 1226.2 Hybrid graphical/functional representation of how wear-out models withinthe SPM architecture are formulated for HOPPL use in the custom infer-ence software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246.3 Conventional MLE fit of Weibull failure data exhibiting group-level vari-ability. The 95% confidence interval fails to bound individual lot failuredistributions. © 2025 IEEE [6]. . . . . . . . . . . . . . . . . . . . . . . . 1266.4 Prior and posterior predicted failure distributions of a Weibull modelwithin the SPM architecture, demonstrating effective characterization ofgroup-level variability behaviours. © 2025 IEEE [6]. . . . . . . . . . . . . 1276.5 Prior and posterior degradation curve distributions for the probabilisticNBTI model using experimental data from the contributed RO-based sen-sors for inference. © 2025 IEEE [6]. . . . . . . . . . . . . . . . . . . . . . 1286.6 Hyper-latent prior and posterior distributions for the NBTI model com-pared to show epistemic uncertainty reduction after inference. NumericHφ values are included to quantify the reductions. Revised from [6]. . . . 1296.7 Different inference approaches to learning from sparse TDDB data. Stochas-ticity of the data leads to high estimate variance in the MLE procedurethat is mitigated in Bayesian inference through prior information and mod-elling of uncertainty as to aleatoric variability. . . . . . . . . . . . . . . . . 1306.8 Lifespan metrics generated from the MLE fit and CBI on sparse TDDBdata. Different information regarding the likely true behaviour is conveyedby each metric and method. . . . . . . . . . . . . . . . . . . . . . . . . . . 1319.1 Graphical representation of the Arrhenius temperature acceleration modelwith pass/fail observations at the end of HTOL. A sigmoid function isused to introduce aleatoric uncertainty to the observations. . . . . . . . . 1699.2 Graphical representation of the Arrhenius temperature acceleration modelwith time dependence to obtain degradation observations at the end ofHTOL. Brent minimization is used to solve the inverse equation for timeto compute chip lifespan. . . . . . . . . . . . . . . . . . . . . . . . . . . . 170xviList of Figures9.3 Prior and posterior product lifespan predictions after a successful HTOLtest result is observed for fixed and slightly uncertain activation energywithin a probabilistic Arrhenius model, demonstrating overconfidence ofpredictions when assuming single values for wear-out model parameters. . 1719.4 Estimated test utility measures of HTOL variants where test duration ismodified, evaluated for both pass/fail state observation and parameterdegradation observation models. . . . . . . . . . . . . . . . . . . . . . . . 1739.5 Expected information gain estimates across the three-dimensional test de-sign space of multi-stress HTOL variants. The highest EIG of 2.524 natsis seen with sub-test temperatures [100°C, 125°C, 150°C]. . . . . . . . . . 1759.6 Graphical representation of the surrogate test line electromigration modelfor multi-voltage, test-to-failure ALT design and lifespan prediction. . . . 1799.7 Estimated utility measures of RPP and expected test time across the three-dimensional test design space for EM qualification. . . . . . . . . . . . . . 1809.8 Underlying “true” reliability distributions for each of the three simulatedEM models. The prior predictive and reliability requirement are includedfor context. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819.9 Posterior reliability distributions and metrics for each of the three simu-lated EM models in comparison to the required reliability and prior dis-tribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819.10 Simplified graphical representation of the four-mechanism PoF model usedto represent the TC1 chip wear-out sensors for the characterization study. 1859.11 Two-dimensional slice of the six-dimensional test design space showingestimated utility from the TC1 characterization BED analysis. All stressconditions for Board 1 and test duration for Board 2 are fixed in the plot. 1879.12 Prior and posterior hyper-latent variable distributions and interpretableentropy values for the four-mechanism degradation model of the TC1 12nmtest chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1889.13 Prior and posterior predictive lifespan distributions for PMOS sensors ina custom 12nm test chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1899.14 Posterior predicted Vth degradation after 10 years for PMOS transistorsunder DC BTI and HCI stress across varied field use conditions. . . . . . 19110.1 Rough steps recommended for developing application-specific LTR mon-itoring and qualification strategies using the developed research compo-nents. To which steps relevant organizations are expected to provide inputis included. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197xviiList of Algorithms1 Importance sampling based algorithm for performing predictive BED anal-ysis with arbitrary utility definitions. . . . . . . . . . . . . . . . . . . . . . 1592 Custom layered resampling algorithm used to marginalize across V tocompute p(y|x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633 Top-level enhanced Brent’s minimization procedure. . . . . . . . . . . . . 2234 Single internal iteration of enhanced Brent minimization. . . . . . . . . . 2245 Fit parabola to three points within Brent minimization. . . . . . . . . . . 2246 Determine distance to new point within Brent minimization. . . . . . . . 2257 Update the evaluation points within Brent minimization. . . . . . . . . . 225xviiiList of AbbreviationsAC Alternating currentADC Analog to digital converterAF Acceleration factor, used to extrapolate failure rates across test conditionsALT Accelerated life test, a high stress test used to quickly observe wear-outANOVA Analysis of variance, a statistical method for uncertainty analysisBED Bayesian experimental designBEoL Back end of line, higher mask layers in the semiconductor fabrication processBTI Bias temperature instability, a transistor degradation mechanismCBI Computational Bayesian inference, for problems without analytic solutionsCDF Cumulative distribution functionCMOS Complementary metal–oxide–semiconductor, an integration technologyCPU Central processing unitDAC Digital to analog converterDC Direct currentDoE Design of experimentsDUT Device under testEIG Expected information gain, here in units of natsEM Electromigration, an interconnect degradation and failure mechanismEUV Extreme ultraviolet, short wavelength light used to fabricate fine patternsFET Field effect transistorxixList of AbbreviationsFIT Failures in time, a constant failure rate metric of failures per billion hoursFOPPL First-order probabilistic programming languageGAAFET Gate-all-around field effect transistorHCI Hot carrier injection, a transistor degradation mechanismHDCR Highest density credible region, Bayesian summary statistic for a distributionHOPPL Higher-order probabilistic programming languageHTOL High temperature operating life, a reliability demonstration testI/O Input/outputIC Integrated circuitIEEE Institute of Electrical and Electronics EngineersIG Information gain, a measure of uncertainty reduction, here in units of natsIGPP Information gain pass probabilityIRDS International Roadmap for Devices and SystemIS Importance sampling, a random sampling method for numerical estimationJEDEC Joint Electron Device Engineering CouncilLBCI Lower bound credible interval, Bayesian summary statistic for a distributionLDDP Limiting density of discrete pointsLTOL Low temperature operating life, a reliability demonstration testLTR Long-term reliability, alternatively referred to as wear-out or agingMCMC Markov chain Monte Carlo, a guided/autocorrelated random sampling methodML Machine learningMLE Maximum likelihood estimation, a statistical fitting methodMTTF Mean time to failure, a metric specifying expected lifespan, here in hoursNUTS No U-turn sampler, a computational algorithm for Bayesian inferencexxList of AbbreviationsPoF Physics-of-failure, using specific physics knowledge in reliability analysesPPA Power, performance, and area, key objectives of semiconductor engineeringPVT Process, voltage, and temperature, key sources of semiconductor variabilityPWM Pulse width modulation, a digital signalling control techniqueRDT Reliability demonstration test, used to evidence acceptable product lifespanRO Ring oscillator, formed using an odd-numbered loop of invertersRPP Requirement pass probabilitySILC Stress-induced leakage current, a transistor degradation mechanismSLM Silicon lifecycle managementSMC Sequential Monte Carlo, using repeated resampling for numerical estimationSoC System on chip, a single die/chip containing various product features/unitsSPM Structured probabilistic model, a graph-based approach to stochastic modelsTC1 The first custom 12nm test chip designed as part of the conducted researchTC2 The second custom 12nm test chip designed as part of the conducted researchTDDB Time-dependent dielectric breakdown, a transistor failure mechanismTIG Threshold information gain, here in units of natsTSV Through-silicon via, a conductive channel bored through the silicon bulkTTF Time to failure, here in units of hoursUSB Universal serial bus, a digital signalling protocolVIG Variance of information gain, here in units of natsxxiGlossaryAleatoric uncertainty Inherent stochasticity of some system, model, or phenomenonthat results in unpredictable observations, even with complete knowledge of thesystem.Apparent activation energy The effective energy threshold, Eaa, beyond which somestochastic process occurs. Activation energy originates from atomic energy barriersin chemical reaction rates and crystalline defect formation, but it is treated as abroader empirical parameter in reliability prediction models. Commonly stated inunits of electron volts.Distribution tail Intuitively, the portion of some probability distribution function farfrom the most likely/central value(s). In long-term reliability engineering the char-acterization of the lower-valued/left tail of the lifespan distribution is of particularinterest to avoid early unexpected failures. Within the scope of this dissertation,left tails are generally defined as the portion of the probability distribution left ofsome particular lower-bound quantile that specifies the tolerable early failure ratefor a semiconductor market.Epistemic uncertainty Lack of perfect knowledge as to the behaviour of some sys-tem, model, or phenomenon that can be in theory be reduced through additionallearning.Experimental utility The value that some test provides towards a given objective.Can be exact once the test outcome is observed, but typically is an expectationover possible observations when the outcome is not yet known.Field use conditions The customer-observed set of values for physical stress param-eters that impact the process of aging for some device. These values for stressconditions often vary over time in real-world use scenarios.Frequentist inference An approach to statistical inference centred on the treatment oflatent/hidden parameters as single-valued/fixed while observed data is stochastic,implying certain methods for handling prior information and specifying uncertaintyxxiiGlossaryas to some latent parameter value. The majority of existing statistical methods inthe semiconductor engineering literature are frequentist in nature. Instead, thisdissertation generally instead uses Bayesian and/or predictive inference approachesin which observed test data is considered fixed while inferences regarding unknownquantities are probability distributions.Group variability Stochasticity where each device in some grouping shares some com-mon parameter shift, but the shifts vary between groups.Hierarchical model A probabilistic model in which some latent random variables arethemselves dependent on additional hyper-latent random variables. This results innested integrals and thus increased computational complexity.Hyper-latent variable A random variable that latent variables hierarchically dependupon. Within the contributed probabilistic modelling framework of this disserta-tion, hyper-latent variables specifically encode epistemic uncertainty.Latent variable A random variable representing the uncertainty of some hidden param-eter within a probabilistic model. Within the contributed probabilistic modellingframework of this dissertation, latent variables specifically encode aleatoric uncer-tainty.Long-term reliability characterization The engineering process of learning aboutand modelling the degradation and failure behaviours that determine product lifes-pan.Long-term reliability qualification The engineering process of evidencing sufficientproduct lifespan across a product population for sale in a target market.Multilevel variability Stochasticity resulting from both a combination of both indi-vidual and group-level sources, producing complex distributions of values acrossdevice populations.Multiple mechanisms Different physical wear-out phenomena with unique character-istics and potential interdependencies that jointly determine overall product-leveldegradation and failure.Natural units of information (nats) A quantitative unit of Shannon/information en-tropy based on calculation using the natural logarithm, with one nat correspondingto the information gleaned from observing an event with probability 1e . Alterna-tive units of bits/shannons or hartleys correspond to the same Shannon entropycalculated using base-2 or base-10 logarithms respectively.xxiiiGlossaryPosterior distribution Represents beliefs as to the spread of possible values for someunknown parameter after observing data and performing Bayesian inference givensome prior beliefs.Predictive experimental design The optimization of tests based on learning aboutquantities of interest predicted by a model rather than based on learning about themodel itself.Prior distribution Represents beliefs as to the spread of possible values for some un-known parameter before observing data and performing Bayesian inference. Notethat the name is specifically given with respect to future observations, as the priorprobability distribution may have been a result of inference on previously-observeddata.Probabilistic programming A programmatic approach to defining and evaluatingprobabilistic models that enables general statistical operations such as Bayesianinference to be performed computationally.Process yield For semiconductors, the percentage of manufactured chips that can beexpected to be functional/“good” out of the total fabricated population. It is acrucial metric of process maturity and potential for commercial success.Product lifespan Within the scope of this dissertation is defined as the length of timefor which a target percentage of a product population can be asserted to outlastbefore failing due to wear-out.Self-heating The process in which energy dissipated by a device itself elevates the localtemperature, thus increasing the experienced temperature stress.Stress conditions The set of values for physical stress parameters that impact theprocess of aging for some device, such as temperature, supply voltage, or humidity.Stress regime The configuration of terminal voltages for some electrical device thatdetermines which different wear-out mechanisms are induced in the device, and towhat degree.xxivAcknowledgementsFirst and foremost, the author would like to acknowledge his supervisor Dr. Andre´Ivanov for providing consistent and quality advice, critique, flexibility, and freedom forself-direction throughout the five years of work towards this dissertation. This essentialsupport made the journey of pursuing a doctorate degree both challenging and rewarding,and served to confirm that the choice to work under his supervision was an excellent one.Further valuable critique and suggestions were provided by the author’s committeemembers Dr. Sudip Shekhar and Dr. Prashant Nair, departmental examination chairDr. Shahriar Mirabbasi, external examiner Dr. Georges Gielen, and university examinersDr. Natalia Nolde and Dr. Guangrui Xia. The course instruction of Dr. Frank Woodwas crucial in obtaining the statistics and probabilistic programming knowledge neededto tackle the research problems addressed by this dissertation, CMC Microsystems pro-vided exceptional opportunities to fabricate custom chip designs, and the UBC E&CEengineering services staff was incredibly helpful in supporting the custom chip design andtest process. Additionally, other researchers within the Ivanov SoC Lab provided valu-able contributions and discussion, in particular Mateo Rendo´n who worked tirelessly onthe gate leakage sensor, second chip design, automated test system revision, and paperwriting efforts for the on-chip sensor designs.Finally, beyond academic and technical support, a Natural Sciences and EngineeringResearch Council of Canada (NSERC) doctoral research scholarship provided importantfinancial stability that allowed for focus on the research effort. This journey also wouldnot have been possible without the mental space afforded by the author’s parents, Jeniferand Simon Hill, and partner, Raina Fan, through the busiest months and most stressfulchallenges.xxvChapter 1IntroductionFrom formal logic verification to layout-aware circuit simulation to product floor-sweeping,the field of semiconductor engineering has developed a remarkable array of techniques toensure functional correctness in the face of the extraordinary difficulty of designing andmanufacturing some of the most complex devices ever created. With automated systemsincreasingly entrusted to handle safety-critical tasks, reliable operation of these complexintegrated products becomes paramount. For many aspects of product design and relia-bility, formal verification techniques, though often prohibitively challenging, can providefunctional guarantees to customers. Even with black box methods such as deep learning,where the physical meanings of individual parameters are complex and obscured, thereare motivated efforts to develop more formal verification strategies to aid deployment incritical applications [8]. For some aspects of engineering design, however, there existsfundamental and unavoidable epistemic uncertainty that frustrates any and all efforts toprovide verifiable operation. Possibly the most interesting and challenging example insemiconductors is the long-term reliability (LTR) aspect of product quality. If a productdesign includes novelty and is intended to last for any significant period of time, there isno way to directly test whether these novel aspects will operate reliably for the requiredlifetime within a realistic product development timeline. The reliability engineer’s jobis thus that of the forecaster, leveraging data collected within the restrictive windowavailable to them prior to product release to develop predictions that come as close aspossible to violating causality.Evaluation and improvement of semiconductor LTR is not only inherently uncertainand technically challenging, it is also a pressing issue. The IEEE International Roadmapfor Devices and Systems (IRDS) has identified growing risks to the continued innovation ofsemiconductor technologies resulting from reliability concerns, particularly related to highlevels of variability between individual devices and reduced thresholds for failure due toincreasing complexity and decreasing atomic scale in modern fabrication processes [9, 10].From an industrial perspective, chip design companies grapple with rapid developmenttimelines that minimize the time and resources available for quality testing efforts. Thepressures to balance time savings, high reliability, and technological innovation put severe11.1. Historical Context for Semiconductor Reliability Engineeringstrain on the capabilities of existing LTR qualification strategies. Standard methodsuse fixed-length test procedures that are inflexible to different product requirementsor development timelines, and their extrapolated lifespan predictions fail to effectivelycapture the degree of confidence that can be placed in product lifespan estimates forsafety-critical applications.This dissertation contributes the components necessary to build a starting foundationfor improved LTR qualification of semiconductors; strategies rigorous enough for growinghigh-reliability applications and further transistor scaling. Only feasible as a result ofmodern advancements in on-chip sensor design, computational Bayesian statistics, andcompute performance, the introduced sensors and statistical frameworks leverage state-of-the-art engineering methods and tools (including some novel enhancements developedwithin the research scope). This dissertation itself is segmented into three parts thathandle different research directions that converge to form the overall qualification foun-dation. Culminating case studies in Ch. 9 present complete examples of qualificationand characterization procedures leveraging the research contributions, embodying po-tential methods for industrial adaptation, while the remainder of this chapter providesimportant contextual background and explicit definitions of the research objectives andscope.1.1 Historical Context for Semiconductor ReliabilityEngineeringElectronics are not just a major driver for the development of reliability engineeringtechniques today, they also originated the modern conception of the field. Vacuum tubesduring the second world war had two conflicting properties: critical importance withinthe function of advanced military equipment, and extremely high rates of failure [11–14].Ongoing poor uptime and expensive repair costs of these systems necessitated a more for-mal approach to managing electronic components, spawning the framework and methodsof the 1957 Advisory Group on the Reliability of Electronic Equipment (AGREE) reportthat is commonly referenced as the start of a formal field of reliability engineering [15]. Afirst key contrast of the current definition from earlier work stems from the rise of massmanufacturing, in particular the relative uniformity between physical devices that can beachieved to allow for detailed reliability analyses to remain applicable to all instances of aproduct (thus making such analysis economical). Without the low variability afforded byfabrication techniques arising from the industrial revolution, there is little capability forcollective analysis of reliability for a given product. Another contrast worth highlighting21.2. Formal Definition and Facets of Reliabilityis the impact of advanced manufacturing on repairability and responsibility. Reliabilityhas been relevant and considered for millenia, from surface wear of roads to seismic re-sistance of houses, but the motivation to develop analysis and improvement techniquesincreases drastically once in-field repair is prohibitive and relatively few organized bodiesare capable of service. A sonar power amplifier in a submarine cannot be easily fixed orMacGyvered by her crew, and the providing company may be financially responsible forrepair or replacement if they promised some minimum lifespan to the customer to securea contract.The second historical event motivating the modern sophistication of reliability engi-neering is the development of integration technology. Simultaneous fabrication of manyindividual transistors on a single die with interconnection capability allowed for drasticscaling, reduced failure rates, and exceptional device uniformity. Advanced integrationintroduces a significant drawback of making individual device analysis and repair virtu-ally impossible, however. This leads to uniquely high demands on reliability; a singlefailed transistor cannot be repaired or replaced, thus for modern fabrication processes asingle failure in billions has the potential to consign the entire chip. Variability betweendevices also becomes significantly correlated as a byproduct; a small shift in fabricationconditions impacts all transistors on a die. Statistical analysis can be extremely chal-lenging in these cases where failures are dominated by extreme value stochastic eventsand potentially correlated across silicon wafers and production lots. This monolithic in-tegration approach separates semiconductors from most other products and exacerbatesreliability engineering challenges.Finally, it is valuable to highlight the ongoing process of miniaturization. The smallerelectronics get, the more quantum the physical degradation and failure mechanisms be-come. Nanometre transistors can experience quantization of degradation where everyatomic defect that forms can produce measurable parameter shifts [16], making physicalphenomena difficult to model and further aggravating aging variability in current fab-rication processes. Looking forward, new challenges (discussed at length in Sec. 1.5)will continue to drive innovation in the field and necessitate increasingly sophisticatedstatistical approaches to handle all of the challenges associated with the pursuit of atrillion-transistor chip [17].1.2 Formal Definition and Facets of ReliabilityJust as the word “reliability” was coined in reference to the consistently pleasant andempathetic character of a person [18], the engineering definition intends to capture the31.2. Formal Definition and Facets of Reliabilityconceptual idea of quality in relation to time. In the textbook Practical Reliability En-gineering, leveraged by the American Society for Quality (ASQ) for their certificationprogram, reliability is defined as “the probability that an item will perform a requiredfunction without failure under stated conditions for a stated period of time,” [19]. Froma product perspective, the required function is a complex set of features and qualities,and the stated conditions reference the stressors experienced. The stated period is oftenbroken into three idealized segments of a product’s lifespan based on failure cause andrate to form a “bathtub” curve as seen in Fig. 1.1, noting that in reality failure ratecurves are less simplistic and these segments can frequently overlap.Figure 1.1: Bathtub curve representation of product reliability, adapted from [7].The middle facet of the curve, operational life failures, are characterized by their fullystochastic nature. These arise from design flaws that present under random or atypicalevents such as extreme temperatures, rare untested system inputs, or radiation exposure.Reducing the rate of operational failures can be achieved through design and exposuretesting prior to product launch. Note that operational life failures occur during the othertwo time segments as well but are often dominated by the other causes of failure, andthat from a software perspective this is the only aspect of reliability.The early life facet of reliability is usually attributed to manufacturing defects such aslithography imprecision or weak wire bonds that cause a product to either be entirely non-functional or to age and fail rapidly after fabrication. With sound reliability engineeringthis segment of the curve should almost never be observed by customers since effectivescreening techniques such as burn-in testing induce these failures and enable defectiveparts to be discarded prior to sale.The final facet of semiconductor reliability, wear-out (also known as LTR or aging),arises from the natural degradation of nominal devices operating under stress. Eventu-41.3. Consequences of Evolving Semiconductor Marketsally all physical devices fail, and the point at which failure rates increase significantlydue to aging typically defines a product’s lifespan. As mentioned in the chapter open-ing, a critical feature of wear-out that makes it particularly challenging to address isthat it cannot be tested directly under expected in-field stress conditions unless devel-opment cycles are longer than the target lifespan. Such cases are extremely rare (theJames Webb space telescope is a notable exception due to development delays [20]), thuswear-out reliability must instead be forecast in advance of product release, retaining aninherent degree of uncertainty and so leading to unavoidable design risk. Wear-out hasalso historically been de-emphasized in the semiconductor industry thanks to rapid per-formance improvements in semiconductor fabrication processes and digital design thathave rendered consumer products obsolete before wear-out failures begin to appear (cur-rent and upcoming changes to this trend are discussed in the next section). Althoughthe work within this dissertation is restricted in scope to wear-out reliability, it is usefulto consider it in relation to the other two facets. Some manufacturing defects can berepresented as device parameter shifts that aggravate aging to an extreme degree, andthe artificial distinction between the severity of stress conditions that induce wear-outversus unexpected operational life failures has crucial ramifications in designing tests forwear-out prediction.1.3 Consequences of Evolving Semiconductor MarketsTable 1.1 provides a summary of typical lifespan, allowable failures-in-time (FIT) rates,and compound annual growth rate (CAGR) forecasts for major semiconductor marketsegments. Table data is based on several different sources [21–28].Table 1.1: Semiconductor markets reliability overview, revised from [1].Consumer Datacenter Communi-cationsAutomotive Aerospaceand MilitaryHealthcareTypicalLifespan4 3 20 15 20 10 yearsTolerableFIT<10 000 <1 000 <1 000 <1 <1 <10ProjectedCAGR7% 5% 6% 13% 8% 11.4%1.3.1 Safety-Critical Market GrowthHigh reliability semiconductor markets can be loosely defined as those requiring extremelylow failure rates (approximately a FIT below 10) due to safety critical function. All ofthe emerging high-reliability markets seen in Table 1.1 have strict reliability requirements51.3. Consequences of Evolving Semiconductor Marketsresulting from their high ethical responsibility to minimize failure risks, but they alsoshare high rates of projected growth over the next decade in comparison to less stringentmarkets. One potential cause for this growth is the increasing maturation of the semi-conductor and software industries. Technology adoption rates for critical applicationsare generally slow, and so the level of trust in these technologies may have taken time togrow to a point where autonomous systems are being entrusted to make functional deci-sions with high consequences of failure. There are a small number of established marketswhere autonomous systems are already commonly used for critical functions, such as intrain control systems, but extensive redundancy is used to ensure correct operation inthese applications. As safety critical systems become accessible to individual consumersand incorporate more intensive computations, such as machine vision algorithms for au-tonomous vehicles, such redundancy can become cost prohibitive and so strict individualpart reliability is instead prioritized. Regardless of the reasons, the observed growthtrends suggest that LTR will experience increased emphasis as high-reliability marketswith low tolerable failure rates and long expectations on product lifespan occupy a largershare of total semiconductor sales.Increased desire for regulation emerges as a byproduct of stringent requirements forhigh-reliability products. As an example, the automotive market has developed the AEC-Q100 specification to provide testable standards for semiconductor component reliabilitythat must be met by suppliers [29]. Such regulatory strategies for wear-out reliabilityare still in the early development stages, as evidenced by the AEC-Q100 statement that,“Typically a product qualification according to this document is not sufficient to release anew technology for manufacturing of automotive products. It is highly recommended toperform a technology qualification using knowledge based methodologies as prerequisiteto the product qualification.” Test requirements for semiconductor die fabrication relia-bility tests (AEC-Q100 Table 2, Test Group D [29]) are still non-existent as of the 2023edition, meaning customers are provided no evidence beyond the trust placed in semicon-ductor foundries as to the wear-out reliability of their vehicles. Significant opportunitiesfor research work into metrics and methods for effective wear-out reliability regulationstrategies that can quantify and minimize epistemic uncertainty exist as a result of thisneed for more effective regulation.1.3.2 Low Reliability Market ConcernsWear-out reliability is a unique concern in the purchasing decision process. The objectiveis not to find a part that will never experience wear-out failures, merely one that willnot experience failure within the desired useful life of the product. This is contrast to61.3. Consequences of Evolving Semiconductor Marketsthe other facets of reliability, in which any observed failures are considered design de-fects rather than a physical inevitability. A de-emphasis of wear-out reliability inverselyproportional to the product lifespan arises, thus short-lived products require little ef-fort to be dedicated to qualifying and improving wear-out reliability. Datacenter andtelecommunication markets contain large systems that are designed to tolerate isolatedfailures (e.g., a single device within a server or a single cell tower in a populated area canfail without significant impact), and so LTR is also de-emphasized in these cases whereit is more of a competitive selling point to reduce operational repair costs. There areunique issues in markets with large-scale systems, however, as isolated issues can oftenslip through unnoticed, leading to major challenges like silent data corruption that arecurrently incentivizing greater reliability investment for datacenter customers [30]. Con-sumer electronics most clearly display this trend of de-emphasis on reliability, however,especially in products where rapid innovation is prevalent (such as smartphones). Heredevices becoming technically obsolete from a features perspective long before wear-outfailures can be observed. Additionally, it is difficult for an individual consumer to gaugethe LTR of technically complex products when making purchasing decisions.For the consumer segment specifically (where reliability is most easily overlooked),it is reasonable to wonder whether allocating resources to address wear-out reliability isworthwhile, and in many cases it is not from an economical standpoint. There are threetrends worth considering, however, that may increase the number of consumer productsfor which increased LTR investment may occur in the near future. The first is observedincreases in length of ownership for key consumer products. In 2019, Apple acknowledgedthat iPhone sales have been affected by existing users choosing to replace their batteriesinstead of upgrade [31], and a similar trend can be observed in the automotive industrywhere the average age of light vehicles on U.S. roads continues to increase annually [32].The European Union’s right-to-repair legislation passed in 2021 increases financial bur-den in relation to these longer periods of ownership, requiring manufacturers to ensurea decade of supported repairs for their products [33]. The second trend is increasingconsumer interest in reliability and cost of ownership. This is evidenced by efforts suchas France’s “durability index”, first enforced in 2025, that scores certain categories ofelectronics based on criteria including reliability, ease of repair, and protection againstobsolescence; the index must be displayed at the point of sale to aid in consumer pur-chasing decisions [34]. Finally, with trending global concerns regarding emissions ande-waste production, increased emphasis on reliability is important to consider as part ofany feasible strategy to achieve environmental, social, and resource stability. The UnitedNations estimates that 62 million metric tons of e-waste were produced globally in 202271.4. Overview of Key Semiconductor Wear-Out and Failure Mechanisms[35], a staggering statistic that is directly dependent on length of product ownership.Additionally, many technologies for emissions reduction, such as electric vehicles, hingeon reliability (an electric Volvo C40 Recharge is less sustainable from a total emissionsperspective than the gas-powered equivalent until it exceeds 77 000 km cumulative driv-ing distance due to car battery manufacturing emissions [36]). These trends suggest thatLTR’s role in product success will grow in importance over time, even for markets wherewear-out qualification has historically been de-emphasized.1.4 Overview of Key Semiconductor Wear-Out andFailure MechanismsWithin the domain of semiconductor wear-out reliability there are multiple physical pro-cesses that occur over time and can lead to both gradual degradation of device parametersand sudden failure events. There are three known significant mechanisms within modernfield effect transistors (FETs) and three in interconnects that will be introduced as themost important to IC reliability. Many others exist, however, such as those related towire bonding, 3D integration, and through-silicon vias (TSVs) that may grow in impor-tance as fabrication processes continue to innovate. The evolution of these mechanismsas innovation occurs, in terms of their severity and exact underlying physical phenomena,is difficult to monitor due to the low prevalence of transparency in the semiconductorindustry. Only the foundries themselves have detailed data on LTR mechanisms in pro-duction processes (shared to chip designers through obfuscated simulation models withassociated non-disclosure agreements), and so establishing how the severity of aging ischanging alongside process innovation is a piecemeal effort. Following extensive survey,the broad conclusion is that existing literature is divided on how transistor scaling andarchitecture impacts key LTR mechanisms due to complexity and differences in foundryprocesses alongside the additional time dependence of reliability as a process matures[37–39]. There is general agreement that transistor variability and self-heating duringoperation is worsening in more advanced fabrication nodes, however, which impacts allLTR mechanisms [9, 40, 41]. The effects of self-heating are not discussed in detail toreduce the complexity of modelling temperature stress, suffice it to say that all LTRmechanisms exhibit temperature dependence and thus are impacted by heat generatedduring operation of the devices in which they arise [42]. This section will proceed tointroduce the key mechanisms affected, while more detailed discussion of variability andself-heating as significant upcoming LTR challenges is provided shortly in Sec. 1.5.81.4. Overview of Key Semiconductor Wear-Out and Failure Mechanisms1.4.1 Transistor Wear-Out and Failure MechanismsFor transistor mechanisms in particular the exact physical processes governing wear-outmechanisms are still not fully understood due to the extreme difficulty in characteriz-ing individual atomic defects and modelling the quantum processes that compose them.Although proposed physics and models exist [43, 44], the following descriptions will re-main at the phenomenological level of detail with general consensus. Bias temperatureinstability (BTI) occurs as a result of the electric field across the gate dielectric of atransistor providing potential energy for the formation of atomic defects in the gate di-electric materials. These defects can then trap charge carriers, as depicted in Fig. 1.2.The rapid and repeated trapping and detrapping of carriers by individual defects can beobserved as random telegraph noise (RTN), evidencing the increasing discretization ofdegradation where individual traps produce measurable shifts in transistor parameters[45]. The interface layers contain the majority of formed defects due to their less stablelattice structures; transitions between materials with different crystal structures leads tostrain and pollutant atom contamination (especially hydrogen) [46].Figure 1.2: Carrier trapping due to atomic defects formed from bias temperature insta-bility in nanowire FETs. © 2022 IEEE [1].Charges within the formed defects can reduce the efficiency of the gate dielectricand lead to increases in the transistor threshold voltage (Vth) magnitude. The result isdigital circuit slowdown and analog circuit parameter degradation. This process occursin both NMOS and PMOS transistors as PBTI and NBTI respectively. An importantfeature of many processes driven by atomic defect formation is that when stress is re-moved (or sometimes even reversed [47]) some of the defect state formation processesare reversible (and related to RTN detrapping), leading to a “recovery phase” that is91.4. Overview of Key Semiconductor Wear-Out and Failure Mechanismsparticularly noticeable with regards to BTI on short time scales. Assuming that a tran-sistor is not kept under permanent BTI stress this recovery can happen naturally duringtransistor switching and/or product downtime; though accounting for recovery is impor-tant during measurement to avoid pessimistic predictions, the permanent component ofBTI is assumed to be the primary consideration for in-field prediction in this dissertation[48]. Further assuming that the majority of BTI recovery is allowed to take place prior tomeasurements (supported by the used sensor design read-out schemes and experimentallyobserved lack of recovery in Part I of this work), its impact on the presented researchcontributions is small. Leaving recovery mostly out of scope within this dissertation, thehigh-level empirical Eq. 1.1 is used to model permanent threshold voltage shifts, ∆Vth,resulting from BTI following the recommendations of the industrial Joint Electron DeviceEngineering Council (JEDEC) Solid State Technology Association provided in JEP-122[49]. The pre-factor Ao, apparent activation energy Eaa, voltage exponent α, and timeexponent n are all latent parameters that must be determined for a given process, k isthe Boltzmann constant, while temperature T , gate voltage Vgs, and time t are stressparameters.∆Vth = AoeEaakT V αgs tn (1.1)Hot carrier injection (HCI) is similar to BTI in many ways, though the potential en-ergy is instead provided by energetic collisions of mobile charge carriers moving throughthe transistor channel (see Sec. 2.1 for a discussion of what voltage bias conditions induceBTI and HCI and to what degree). These collisions introduce defects and carriers to var-ious sites within the transistor, producing several sub-effects [50]. These formed defectstates can further increase Vth and also decrease carrier mobility (thus reducing the tran-sistor saturation current). For both n-HCI and p-HCI in NMOS and PMOS respectively,and depending on the fabrication process, HCI has the potential to worsen both withincreasing and decreasing temperature relative to field-use conditions. At low temper-atures less lattice scattering gives carriers lots of time to build up momentum betweencollisions, while at high temperatures carriers accelerate quickly and require less energyto induce defect states [51]. Due to their very similar impact on transistors, some studieshave observed that the BTI and HCI mechanisms can show interdependent effects wheretransistor degradation via one can affect future degradation via the other [52]. Modelsincorporating such interdependent effects are still absent, thus this dissertation retainsseparate models for the two mechanisms. Similar to BTI, complex physics-emulatingHCI models have been proposed [53] but are involved and full consensus is not reached.There is also no clear consensus on empirical models for HCI in short-channel transistors101.4. Overview of Key Semiconductor Wear-Out and Failure Mechanisms(the JEDEC suggested model contains no voltage or temperature dependence), but anacceptably well-reasoned one from P. Zhang et al. is adapted for the purpose of thisdissertation [54]. The empirical HCI model is shown in Eq. 1.2, where pre-factor Ao,voltage exponents u and v, time exponent α, and temperature dependence factor β arelatent parameters to determine, Tref is reference temperature 300K, then temperatureT , voltages Vgs and Vds, and time t are stress parameters.∆Vth = AoVugs Vvds tα+β(T−Tref ) (1.2)The final transistor wear-out mechanism of time dependent dielectric breakdown(TDDB), with its sub-mechanism of stress-induced leakage current (SILC), is drivenby defect formation throughout the gate dielectric that leads to increasing gate to chan-nel current magnitude Ig. The SILC phenomenon results from the quantum tunnelingof electrons through the gate dielectric, a process which increases in frequency as defectsform that reduce the required tunneling distances and increase the quantity of interme-diate sites available [55]. The gate current increases of SILC are observable but typicallynot significant enough to impact normal transistor operation, though they can be usedto track the progression of defect formation [56]. Once enough defects form in a local-ized chain the insulating dielectric can fail altogether and allow for conventional currentflow, often significant enough to render the transistor non-functional. This point of sud-den conductive failure is TDDB, and though some occurrences can be recovered throughstress removal or reversal to repair defects in the dielectric, the conductive channels areoften permanent and thus lead to TDDB being referred to as a “hard failure” mechanism.A visual explanation of TDDB is shown in Fig. 1.3.Empirical models for TDDB are abundant, and large-scale debate continues overwhich best follows the physics of modern process nodes. Case studies within this disser-tation will mainly adopt the power law model following a well-regarded 2013 comparativestudy by Croes et al. [57], but all presented analyses could be just as easily performedwith alternate empirical TDDB models and no argument for preferring one over anotheris made. The power law model form used neglects any possible parameter sensitivitiesto temperature and voltage but leverages temperature dependence introduced by Wu etal. [56] to define the time to failure (TTF) for a transistor. The model is represented inEq. 1.3, with to, n, a, and b as latent parameters to infer for a given fabrication process,then previously seen stress parameters of Vgs and T .TTF = toV−ngs eaT+ bT2 (1.3)111.4. Overview of Key Semiconductor Wear-Out and Failure MechanismsSUBSTRATEGATE OXIDEGATECHANNELSiO2VDDGNDPartially conductive path(SBD)Ohmic short (HBD)𝐼𝐺𝐿Figure 1.3: Visualization of GAAFET gate dielectric defect formation leading to SILCand TDDB. © 2025 IEEE [3].1.4.2 Interconnect Wear-Out and Failure MechanismsMoving from transistors, considered “front-end-of-line” elements of a fabricated chip, towhat are called back-end-of-line (BEoL), the most significant LTR mechanism is electro-migration (EM). As current flows through metallic interconnects, repeated collisions ofcharge carriers with the atomic lattice results in a net force on the metal that can pro-duce warping and movement within the interconnect [58]. The effects of this phenomenonare increasing electrical resistance over time and open circuit hard failures if sufficientvoiding occurs (empty pockets that grow as metal migration occurs). The phenomenonis depicted in Fig. 1.4.Figure 1.4: Depiction of electromigration micro and macro impacts. © 2022 IEEE [1].121.5. Incoming Technical ChallengesWorst case EM occurs under DC current stress due to continuous force in a singledirection, and it follows that the mechanism can be partially recovered through reversecurrent stress [47]. Although still occurring at the microscopic scale, BEoL mechanismsare more readily described by macroscopic physics and thus there is less uncertaintyand debate as to how best to physically model the phenomena. The accepted Black’sequation [59] shown in Eq. 1.4 will be used for EM in this dissertation, though upcomingprocesses are considering the adoption of rare earth metals, such as Co, Ru, or Mo,that exhibit extremely high EM resistance and could change models or mitigate themechanism in the future [60]. Latent parameters n and Eaa are the current scaling factorand apparent activation energy respectively, while J is the DC current density stress inthe wire dependent on the circuit and stress voltage and A is the cross-sectional area ofthe interconnect.TTF =AJneEaakT (1.4)Other BEoL mechanisms are not considered within case studies and so only a shortsummary of each is provided for completeness. Interconnects in ICs also exhibit warpingand movement due to stress migration, which results in similar impacts to chips aswith EM but instead arises from mechanical tensile stress due to thermal expansionand contraction [61]. The final interconnect mechanism is BEoL TDDB, which sharesmany features with conventional TDDB though instead occurs in the thicker insulatingdielectrics between interconnects and other fabricated structures. Less SILC is observeddue to increased thickness and reduced electric field magnitudes, however hard failuresstill present due to lower quality dielectrics used in BEoL fabrication and the potentialfor metal atoms within interconnects to migrate into the dielectric and produce defectsnot seen in transistor TDDB [62].1.5 Incoming Technical ChallengesThe constant pursuit of performance improvement and feature innovation within thesemiconductor industry results in a continuous race to keep up for reliability engineers.By the time at which in-field failures could feasibly be observed and used to verify pre-dictions as to LTR, multiple new process nodes will have been introduced with a varietyof changes to device geometry, materials, and manufacturing techniques that make directcorrespondence of reliability with the verified process infeasible. This is not to say thathistorical knowledge gleaned from the verification of older processes cannot provide sig-nificant value in the prediction of reliability for new technologies, to foreshadow methods131.5. Incoming Technical Challengesthat will first be introduced in Sec. 4.1.3, however all fabrication processes that providetechnical innovation will also unavoidably introduce epistemic uncertainty as to LTRperformance. The continuing rate of semiconductor process innovation is remarkableconsidering the complexities of semiconductor fabrication; foundries typically manageto operate on an average two to three year process development cycle. An overview ofhistorical and projected innovations in semiconductor fabrication is presented in the Fig.1.5 timeline.The approximate dates of historic innovations and predictions are a synthesis froma variety of sources [9, 10, 63–68]. Since this innovation is primarily driven by indus-try, many details are not disclosed in order to guard technological advancements, andmarketability can often take priority. Consequently, there are several caveats to theinformation shown in the timeline:• The minimum dimension labels commonly used to name foundry processes, suchas 5nm, do not correspond to the actual minimum gate length process dimensionin modern semiconductors. This is due to the increasing difficulty of further directscaling leading to numerous “equivalent improvement” strategies that allow forprocess performance to be marketed as equivalent to some direct minimum featuresize [9].• Additional foundries and technological advancements exist but only the most sig-nificant are listed for visual clarity, with focus primarily on the development ofprocesses and innovations for digital logic rather than power or analog deviceswhich would have their own unique timelines.• All IEEE IRDS forecasted technology changes and processes are merely predic-tions and should be treated as such, while company-specific information is oftenapproximate to the best available public knowledge.It is also important to define a few terms seen in the timeline. Techniques using“3D” refer to vertical integration technologies used to fit more circuitry into the sametwo-dimensional footprint. Tri-gate is an alternative name for FinFET-like transistors.Similarly, RibbonFET and nanosheet transistors are effectively GAAFETs. Future CFETdevices retain GAAFET-style architecture, but an NMOS and PMOS transistor are ableto be vertically stacked (this is partial 3D VLSI but transistor fabrication still startsfrom the silicon bulk, whereas “true” 3D VLSI implies additional CFETs can be stackedvertically). Extreme ultra-violet (EUV) lithography is the use of smaller wavelength lightto increase geometric precision at nanometre scales, where larger optical apertures areneeded to improve feature precision. Finally, backside power refers to the capability to141.5. Incoming Technical Challengesroute power delivery through the silicon wafer directly to transistors, freeing up significantspace for increased signal routing density in the conventional metal layers.Figure 1.5: Prior and projected timeline of semiconductor innovations, updated from [1].151.5. Incoming Technical ChallengesEach scaling step and novel fabrication technique introduced brings associated wear-out reliability risks, with potential for new mechanisms (such as with TSVs), modifica-tions in behaviour of existing mechanisms, and the discretization of degradation broughton by quantum effects at atomic scales [16]. The IRDS predictions for upcoming fabri-cation processes lead to several technical challenges worth discussing in greater detail.1.5.1 Increasing Variability at Atomic ScalesLikely the most pressing concern for semiconductor fabrication in terms of LTR is theincreasing rates of stochastic defects caused by fabrication variability, from etching to de-position to atomic contaminants [9]. Though the ideal objective is reduction of variabilityto a degree where stochastic failures never arise, and certainly semiconductor engineeringexcels in this pursuit, residual variability continues to be a major source of issues relatedto yield and non-uniform performance. Even in an imaginary scenario in which fabrica-tion variability was somehow entirely eliminated, once in the hands of customers eachchip is subjected to unique stressors, workloads, and environments. Long-term reliabilityis impacted by almost every one of the numerous sources of variability, from inherentdifferences in exact atomic composition between transistor devices, chips across a singlewafer, and production lots to external non-uniformity in voltage, temperature, humid-ity, and more. Characterization and modelling of these many sources of stochasticity isan important pre-requisite to reduction, enabling chip designers to account for randomvariations in circuit parameters to ensure sufficient performance across the probabilisticprocess distribution of chip performance, power consumption, and degradation.Unavoidable variability, also known as aleatoric uncertainty, is a critical considerationof the conducted research, and will be brought up frequently throughout the chapters tocome. Product lifespan predictions need to be made with consideration for variability inthe failure times of individual chips, thus overall product lifespan, especially when highreliability is required, is limited by the lower tail of the stochastic probability distributionof failure times. These extreme value “unlucky” failures are difficult to observe in testenvironments due to their rarity yet cause failures with increasing frequency as productionvolumes scale, contributing to problems such as silent data corruption in large-scalecompute infrastructure [30]. At atomic scales, these extreme value failures often onlyrequire a few individual atomic defects to form and are physically governed by quantumeffects. No noticeable degradation preludes failure, and they are thus extremely difficultto observe, predict, or mitigate.One last important factor is the potential for correlated random effects to result ingroup-level variability. All chips in a lot could experience the same stochastic shift if161.5. Incoming Technical Challengesa variability source is introduced at large scale, and can simultaneously be individuallyshifted if variability sources occur at the atomic scale, such as contaminants. The mostcomplex correlations are dependencies of per-device variability on group-level stochasticeffects. As an example, if gradual aging of an air filter in a production facility slightlyincreases the density of atomic contaminants over time (even if still below tolerable levels),variability between devices due to atomic contaminants could increase in later productionlots, leading to some devices with more potential sites for atomic defects to form andthus longer tails in the distribution of failure times. Better understanding and modellingof the complexities of variability sources will be crucial to achieving reasonable yield andLTR in upcoming fabrication processes.1.5.2 Increasing System ComplexityProjected increases in system complexity as 3D packaging and chiplet architectures areincreasingly adopted can also lead to system-level LTR concerns [69]. Though packag-ing is outside the technical scope of this dissertation, the overall reliability of multi-dieproducts is an important additional consideration when determining LTR requirementsfor individual chips. To meet a target product-level reliability requirement, the law oftotal probability necessitates that each individual die/chiplet within a packaged productis qualified to an even higher degree of reliability [70]. If interdependencies arise (e.g.,heat dissipation affecting adjacent chips) the situation becomes even more challengingto assess. The higher component reliability requirements needed to maintain equiva-lent system-level reliability further motivates the need for effective qualification strate-gies. Application of the research contributions of this dissertation to package-level LTRmechanisms, alongside variability and unique failure criteria across multiple independentchiplets simultaneously, would be a valuable avenue for future work to investigate.1.5.3 Heat Dissipation and Failure Modes in Vertical IntegrationFinally, self-heating and the potential for new degradation phenomena associated withdevice architecture changes are also crucial considerations for LTR in particular [64].These challenges are not directly addressed by the conducted research work, but arerelevant in terms of motivating consideration for a variety of field use conditions andtest designs. If self-heating impacts continue to increase in severity with the growthof vertical packaging and integration, the specifics of software workloads may play anincreasing role in LTR. A variety of field use stress conditions arise according to thevariety of workloads and so product LTR qualification will need to be conducted withrespect to worst case scenarios across multiple potential in-field use cases (rather than a171.6. Industrial Long-Term Reliability Qualification Practicessingle anticipated degree of stress). On top of exacerbating thermal dissipation issues,innovations such as backside power delivery and CFETs that are being introduced toenable vertical integration have significant potential to introduce new LTR mechanismsor worsen the severity of existing ones [71, 72]. It is therefore important to ensure thataccelerated testing methods can explicitly consider new and modified physical phenomenathat may produce failures under field use conditions.1.6 Industrial Long-Term Reliability QualificationPracticesGiven the daunting task of forecasting LTR for safety-critical applications in light of thecomplex and evolving set of wear-out and failure mechanisms that impact circuits in inno-vative fabrication processes, selecting tests and prediction techniques without specializedreliability engineering knowledge is extremely challenging. Building on the MIL-HDBK-217 and MIL-HDBK-781 (previously MIL-STD-781) series of documents that were de-veloped to provide some common guidance and minimum expected level of reliability inmilitary electronics in the mid to late 1900s [73, 74], JEDEC developed a set of standardsfor reliability qualification specifically geared towards semiconductor devices. Several arededicated to accelerated life tests (ALTs) [49, 75, 76]. The set of documents producedcomprises both specific test procedures and advice for evaluating individual failure mech-anisms and process shifts. Their widespread adoption has lead to a normative state insemiconductor LTR qualification. The brief discussion in this section will only focus onthe specific methods used in JEDEC semiconductor qualification, a more in-depth andgeneral review of traditional ALT strategy is provided by Collins et al. [77].1.6.1 Standardized Product Demonstration TestsThe most well-known and widely leveraged test within the JEDEC suite is the HighTemperature Operating Life (HTOL) test, described in JESD22-A108 [75]. Productsare subjected to elevated stress at 125°C and (optionally) up to 1.2x nominal supplyvoltage for 1000 hours. Failed chips out of three unique lots of 77 ICs each are totalledonce the test completes; typically an acceptance criteria of zero failures is used to claimsufficient system-level wear-out reliability for product release. This type of procedure isknown as a reliability demonstration test (RDT) [78]. The statistical basis for this claimof sufficiency assumes that the first failure occurs immediately after the test concludes,giving a failure rate of 1 per 1000 hours or a failures-in-time (FIT) metric of 1 000 000(failures per billion hours), which is then used as an upper bound to predict the rate181.6. Industrial Long-Term Reliability Qualification Practicesat field-use conditions. This is done via an acceleration factor (AF) computed usinga modified version of the Arrhenius relation, seen in Eq. 1.5 [49], a model which wasoriginally introduced by Svante Arrhenius in 1889 to model the effect of temperature onchemical reaction rates [79].AF =FITT1FITT2= e−Eaak( 1T1− 1T2) (1.5)Test and in-field temperatures, T1 and T2 respectively, coupled with an apparentactivation energy Eaa (historically 0.7eV) and the Boltzmann constant k compute atemperature acceleration factor, however the JEDEC standards also leverage the practiceto compute voltage acceleration factors. A typical lifespan prediction using this method,given zero HTOL failures, the 0.7eV figure, 125°C test temperature, and an in-fieldtemperature of 55°C gives an in-field lifespan of 8.865 years before the first wear-outfailure in an equivalent sample. The perspective on predictive confidence for this lifespanis that a test pass with the standard 231 samples implies that one can be 90% confidentthat in any accepted lot of fabricated chips at least 99% of in-field units can be expectedto outlive the computed lifespan [76]. This claim is based on the HTOL sample size,computed via the Poisson exponential binomial limit theorem for a 1% failure rate [80].There are additional tests set out by JEDEC beyond just HTOL, including Low Tem-perature Operating Life (LTOL), Temperature Cycling, and Temperature-Humidity-Biastests as examples. These are not as commonly cited as a basis for lifespan prediction, butare still important elements of the JEDEC reliability qualification approach. There arealso alternative but related approaches, such as measure-stress-measure tests [81], thatshare the same general principles. Many companies will also have internal tests and tech-niques developed behind intellectual property safeguards that are occasionally implied inpublished research and data; engagement with multiple industrial organizations helpedinform the research conducted towards this dissertation by providing some insight as tointernal procedures and statistical treatments.It is important to acknowledge the benefits of the JEDEC approach that led toindustry-wide acceptance:• The test specifications are simple from an execution perspective, which minimizescomplexity for engineers in test labs.• Industrial standardization provides a semblance of uniformity between competitors.• Acceptance criteria provide clear markers for claiming product market readiness.• The output predicted FIT is straightforward to comprehend.191.6. Industrial Long-Term Reliability Qualification PracticesThese benefits carry associated engineering limitations, however:• The fixed time investment of standard test procedures places hard lower limits onqualification times. A key motivation for the research work conducted towards thisdissertation is that often companies may want to save time or resources, but thesesimple fixed specifications leave no room for qualification customization accordingto unique product requirements or resource constraints.• Fixed lifetime predictions for a set of field-use conditions prevent competitive dif-ferentiation in terms of improved wear-out reliability. The JEDEC procedures aretoo rigid for use by a company looking to evidence improved wear-out reliabilityover competing products.• A single binary pass/fail criterion oversimplifies acceptability for high-reliability ap-plications which may require per-lot verification, risk profiling, or other approaches.It also permits manipulation strategies that can increase the likelihood of a testpass, such as favourable chip selection or selective reporting of successful attempts[82].• The FIT metric implies a constant failure rate, which makes little sense for theincreasing rates seen in the wear-out facet of the reliability bathtub curve. Thedistribution of failure rates arising from variability between devices, chips, andfabrication lots is also neglected.1.6.2 Per-Mechanism Investigation RecommendationsEven without noted limitations, product-level tests such as HTOL alone are insufficient toeffectively characterize wear-out. This is acknowledged by JEDEC, and their documentsprovide additional guidance (though not standardization) for investigation of individualwear-out mechanisms, including those discussed in Sec. 1.4. There are three specificassumptions of product-level tests in relation to individual mechanisms that are ofteninvalid, leading reliability engineering teams to investigate each mechanism in isolationto supplement the combined, or harmonized, degradation effects seen at the productlevel.1. Product-level acceleration factors assume that all mechanisms follow exponentialArrhenius relationships as temperatures change, and furthermore that the specificapparent activation energy Eaa used is the maximum across all mechanisms. Thereis a large body of research demonstrating different stress relationships across mech-anisms and the associated impacts on lifespan predictions. A few key studies are201.6. Industrial Long-Term Reliability Qualification Practicesprovided for reference [83–86]. One further complicating factor is the potential forinterdependencies between mechanisms [52], which can prevent isolated behavioursfrom directly corresponding to harmonized wear-out performance.2. At the extreme end of mechanism behaviour with respect to stress conditions arethose that require specific energy thresholds for activation, such as material meltingpoints or diode breakdown behaviours. Accelerated test designs must use stressconditions that activate the same set of physical phenomena that are observed in thefield for acceleration factors to be applicable. Any novel fabrication process incurssome risk and requires verifying that the same set of mechanisms are activatedunder field use and accelerated test conditions. This assumption is rarely checkedbut crucial, appearing as a disclaimer at the opening of JEDEC’s JESD-47 standard[76].3. For most products field use conditions are not fixed. Different customer segmentsand diverse use cases for the same chip design lead to a spectrum of voltages,temperatures, workloads, and use frequency. Prior work has demonstrated howclock frequency [84], asymmetric aging of memory cells [87, 88], and idle staterecovery behaviours [47, 89] all impact LTR and drastically complicate the use ofacceleration factors for lifespan prediction.The published per-mechanism investigation approach allows for unique accelerationof individual wear-out mechanisms. Established models (such as those adopted for thescope of this dissertation in Sec. 1.4) are fit to accelerated test data by determiningmaximum likelihood or minimum mean-squared error estimates for latent parameters,after which they can be used to predict the contributions of each mechanism to overallreliability. Unfortunately, the approach still relies on acceleration factors at the per-mechanism level through summation of individually predicted failure rates, which fails tofully resolve any of the above assumptions. Additionally, suggestions for how to collectdegradation data for specific mechanisms in isolation is very limited. Lab-oriented teststructures for isolated measurement of many mechanisms exist in the literature [90–92]and internal to companies; there are far fewer on-chip circuits available to enable isolatedmeasurement of mechanisms once a chip has been packaged. Extensive surveys of researchworks proposing on-chip sensors for isolated monitoring of various wear-out mechanismswill be discussed in Ch. 2. Limited options for chip design firms to obtain per-mechanismreliability data results in a dependence on lab data provided by foundries for simulationmodels.211.7. Areas for Improvement in Long-Term Reliability1.7 Areas for Improvement in Long-Term ReliabilityWith shortcomings of industrial semiconductor wear-out qualification methods and in-dustrial motivation resulting from the pressure to address reliability concerns in upcomingfabrication processes, numerous research avenues towards improving wear-out qualifica-tion strategies have been pursued in the recent literature. This section describes fourkey areas of research at different hierarchical levels to provide a map of the field of semi-conductor wear-out reliability research. The contributions of this dissertation are placedinto this context; surveys of literature relevant to each contribution will be presented inlater chapters just prior to the corresponding work.1.7.1 Physics-of-Failure InvestigationsAt the heart of LTR are the physics from which degradation and failures arise. Seminalresearch at this most intrinsic level led to the growth of physics-of-failure (PoF) relia-bility engineering, as described in Sec. 1.1, and its importance has not lessened since.Reliability improvements arising from PoF research stem from more effective models ofdegradation and failure mechanisms that capture behaviour across stress conditions, ac-count for recovery effects, and accurately characterize the types of atomic defects thatform to produce the aging behaviours seen in modern semiconductors. Examples of re-cent notable works within this domain include detailed investigations of activation energythresholds for defects that cause wear-out [93] and the investigation of mechanism modelsfor new materials that may see adoption in the future [94, 95]. Heat dissipation and me-chanical wear-out mechanisms are also particularly relevant for ensuring reliable verticalintegration technologies. Research into self-heating effects [96] and new failure mecha-nisms such as delamination resulting from through-silicon vias [97] within 3D structuresare also experiencing high levels of interest as a result.The PoF level of research is not a focus of this dissertation, as a major challengearising from the innovative nature of semiconductor engineering is that wear-out physicsare constantly changing and require restrictive access to upcoming fabrication processesand proposed future materials. Significant progress made on topics such as silicon diox-ide defect formation rates [98] can become less relevant as new dielectric materials likehalfnium oxide are introduced in their place [99]. This aspect of the rigorous LTR qual-ification problem is thus central but in a constant state of flux. The research towardsthis dissertation explicitly attempts to remain agnostic to any specific fabrication processand generalize to any possible future set of physical mechanisms (only leveraging specificPoF models for demonstrative purposes). Literature on PoF studies is not surveyed in221.7. Areas for Improvement in Long-Term Reliabilitydetail for this reason. The only potential exception is that contributions of this workin structured probabilistic modelling, presented in Sec. 4.3, introduce generic multilevelvariability modelling capabilities not found in existing literature. Future PoF studiescould benefit from incorporating multilevel variability effects to help address aggravatedvariability concerns in scaled semiconductor fabrication.1.7.2 Measurement and Monitoring TechniquesHypothetically, even if a perfect physical understanding of wear-out was achieved fora specific fabrication process, the integrated and inaccessible nature of the fabricateddevices means that exact applied stress conditions for each transistor and other on-chipelectronic device throughout a product’s life-cycle are subject to uncertainty. In practice,the physics are also subject to uncertainty, and so innovations in measurement and moni-toring techniques for wear-out mechanisms enable improved reliability testing proceduresto help develop better physics models. Contributions at this hardware measurement levelof research include both in-lab testing approaches and on-chip structures that allow forcontinued measurement after a die is packaged.In-lab test approaches have historically evolved alongside PoF research given thatthey are required to obtain experimental data on mechanism behaviour [100, 101]. On-chip circuitry for wear-out monitoring is a more recent research direction; for decades ringoscillators (ROs) were the primary on-chip structure used to track degradation despitenot originally being designed for this purpose [102]. The research work conducted doesnot address in-lab test approaches for PoF investigations, for similar reasons as to whyPoF research itself was excluded, but does contribute significant improvements to on-chip sensor designs for detailed characterization and in-field monitoring strategies. Theimproved wear-out sensor designs for monitoring individual wear-out mechanisms arepresented in Part I of this dissertation, with in-depth discussions of existing on-chiphardware measurement approaches in the literature found in Ch. 2.1.7.3 Data Analysis MethodsEven with novel designs for on-chip sensors that monitor how different physical degra-dation phenomena progress with time, the value of these observations is limited withouteffective methods to interpret that data and develop confident predictions of semicon-ductor product lifespan. In Sec. 1.6 concerns regarding a number of assumptions andshortcomings with existing standard approaches for lifespan prediction were raised. Forper-mechanism data in particular conventional analysis methods were seen to have sig-nificant limitations.231.7. Areas for Improvement in Long-Term ReliabilityResearch into alternative approaches to LTR data analysis is less prevalent in theliterature than efforts in the first two areas of research discussed, however the identifiedchallenges with current approaches have led to notable efforts towards improved predic-tion methods. Work in this area relies heavily on developments in statistical analysis,and are broadly grouped into three categories: i) frequentist statistical enhancements, ii)Bayesian statistical treatments, and iii) black-box approaches based on machine learningor similar tools. A survey of works in these categories are contained in Ch. 4, while thebroader Part II develops a novel probabilistic modelling structure to enable sophisticatedsimulation and analysis of wear-out data.1.7.4 Data Collection SchemesThe final highest level of wear-out research focuses on what specific data should becollected to best enable analysis. The first sub-division of this area was the initial primarytargeted problem within this dissertation, towards optimizing the design of wear-outqualification tests prior to product release. Following discussions with industry reliabilityengineers, the desire to reduce test costs without sacrificing predictive confidence wasstrongly emphasized, leading to questions on whether test durations could be reduced tosave on time costs. The initial phrasing of the question that directed this research workwas, “If the HTOL test time was halved, to 500 hours, what would be the impact to theconfidence of product lifespan predictions?”Literature on improved semiconductor qualification test design is more scarce thanfor the previously described areas of research, with only a few works identified in thepresented survey within Ch. 7. The broader surveyed domain of reliability engineeringstatistics does contain significant prior work on experimental design for ALTs, however,which is brought to specific semiconductor application through contributions of this dis-sertation in Bayesian experimental design for wear-out qualification in Part III.Lastly, it is worth discussing the emerging field of silicon lifecycle management (SLM)that is adapting general product lifecycle management strategies for the specific chal-lenges of integrated semiconductors. The questions of when, how, and what telemetrydata to collect is a major aspect this field hopes to address and could reasonably beconsidered as part of this research area on data collection schemes. Existing work islimited in this emerging field, but some SLM solutions are already providing significantcommercial value [103] and it is expected to be an important consideration for high-reliability markets in the future. Data collection optimization for SLM is not directlyaddressed in this dissertation given that LTR qualification is prerequisite to the scopeof SLM solutions, but future work to package the presented sensor designs from Part I241.8. Research Contributions and Scopeinto an abstracted peripheral for easily obtaining wear-out telemetry data is a key activeavenue for research. The wear-out qualification test optimization methodology presentedin Part III also has potential future applicability for in-field data collection schemes.1.8 Research Contributions and ScopeThe contributions of this research work can be divided into three general areas, eachof which is allocated a separate part within the dissertation. The parts are kept rela-tively self-contained to improve overall readability, each with their own relevant context,literature review, and a concluding discussion section. References to other sections ofthe dissertation are used to link the work into a coherent whole. Though the devel-oped research components in each part provide individual value, Part III significantlyleverages the components of the second to maximize value. Towards the end, the disser-tation provides several case studies that evidence how both the individual contributionsand their combined use provides novel capability and industrial value through rigorousqualification and characterization strategies that account for and directly model epis-temic uncertainty, aleatoric uncertainty, and the engineering costs and risks associatedwith ALTs. From a general scope perspective, it is important to note that although thepresented contributions have potential for application to other facets of reliability, theresearch scope targets LTR exclusively and does not consider the unique needs of earlyor operational life reliability. Additionally, only semiconductor chips themselves are con-sidered and thus all specific interposer, package, and board-level reliability topics are leftout of scope. Other minor scope limitations are present but specific to sub-topics and sowill only be mentioned where relevant.Part I contributes several on-chip hardware sensor designs for active monitoring ofindividual degradation and failure mechanisms:1. An enhanced RO-based sensor for separable measurement of PBTI, NBTI, n-HCI,and p-HCI.2. A novel induced offset voltage sensor for separable measurement of PBTI, NBTI,n-HCI, and p-HCI.3. A novel gate leakage current sensor for measuring SILC degradation as a proxy forTDDB failure risk.4. A novel staggered interconnect EM failure sensor for tracking wear-out progression.All designs are evaluated through physical 12nm FinFET process implementations, anddata collected as part of this successful evaluation enables some general commentary on251.8. Research Contributions and ScopeLTR mechanism behaviours in modern semiconductor fabrication. This commentary islimited to relative comparisons to maximize protection of foundry intellectual property.An ancillary contribution of an automated wear-out testing system, based on printedcircuit boards, is introduced to allow for low-cost execution of ALTs in small-scale labo-ratory environments.Part II constructs a framework for analysis and prediction of LTR based on a novelstructured probabilistic model architecture compatible with arbitrary PoF models. Aformulation for interpretable quantification of uncertainty in these models is contributedto aid in engineering use. The novel architecture is leveraged to contribute a generativesoftware tool for rapid temporal simulation of wear-out data exhibiting complex variabil-ity behaviours and multiple mechanisms. The simulator includes features to allow fornon-constant stress tests to be studied. The architecture is also key to a contributedanalysis software tool for engineers to perform Bayesian inference of semiconductor PoFmodels with the aforementioned variability and multiple mechanism attributes. Finally,definitions for two lifespan metrics are contributed to aid in analyzing predictions madeusing PoF models within the novel architecture, and several case studies evidence thenovel analysis capabilities of a framework containing these contributions in comparisonwith existing techniques.Part III leverages the modelling architecture from Part II within an experimentaldesign framework for optimizing ALTs. Measures of test value that consider engineeringrisk are contributed for use in experimental utility definitions. Further contributions tothe analysis software tool from Part II are made to allow engineers to conduct ALT designtasks for semiconductor PoF models using the modelling architecture. An algorithm forevaluating the value of ALT designs based on arbitrary definitions of utility is includedalongside an internal importance resampling algorithm for integrating out intermediaterandom variables in hierarchical probabilistic models. Comprehensive case studies arethen presented to evidence the capabilities of the various and combined contributions ofthis research to improve semiconductor LTR analysis, qualification, and characterization.A short concluding chapter summarizes the contributions of this dissertation and dis-cusses future directions for industrial adoption and research stemming from the work.The resulting sum of developed research components, in concert with existing literatureon PoF investigations, is sufficient to provide a starting foundation for the developmentof formal LTR qualification procedures with improved rigour regarding the epistemicuncertainty and complex sources of variability inherent to semiconductor product lifes-pan predictions. Potential impacts in supporting high reliability regulation, continuingsemiconductor technology innovation, and consumer protection measures are discussed.26Part ISeparable Wear-Out MechanismMonitoring via On-Chip Sensors27Chapter 2On-Chip Sensor Designs forIsolated Mechanism MonitoringIndividual characterization of wear-out mechanisms has historically been conducted throughin-lab measurement of dedicated test structures. This level of detailed access to the die isin most cases restricted to foundries, and so the foundries themselves are relied upon forthe majority of per-mechanism data. This reliance leads to third-party verifiability issuesthat were were first introduced in Secs. 1.3.1 and 1.6.2. Regulatory bodies do not havethe technical capabilities to verify reliability models provided by foundries, leading to thestate of automotive regulation where safety-critical standards are based purely on trustin the foundry that sets, “The data, test method, calculations and internal criteria...”[29] and need only make them available for review. Chip design firms, similarly, havelittle ability to investigate the effects of individual failure mechanisms on their productsbeyond the simulation models provided in process design kits from foundries.There are emerging capabilities that may allow both design firms and regulatorybodies to investigate individual wear-out mechanisms themselves, tailored to their specificmarkets or products and thus reducing the dependence on generalized foundry results.There have been significant research efforts since approximately 2007 [104, 105] intodeveloping dedicated on-chip sensors for monitoring wear-out phenomenon, both at theharmonized level and in terms of individual mechanisms. These differ from test structuresin that they can continue to be used during product tests after a chip has been packaged, afeature that is also synergistic with the growing technical capabilities for in-field telemetrydata collection. As more products are designed for internet connectivity and computeperformance improvements make individual device analysis feasible at scale, there isgrowing potential for in-field collection of reliability data from consenting customers.The vision of the semiconductor sub-field of SLM is to have various on-chip sensorsthat can be monitored throughout a product’s lifespan and used to monitor performancedegradation, root-cause failures, and schedule repairs or replacements [106]. Since 2007the number of wear-out reliability sensor designs has proliferated and topologies havebecome increasingly sophisticated, however there are still significant gaps and challenges282.1. Explicating Transistor Stress Regimeswith existing designs. One notable shortcoming is that the vast majority of sensors eithertrack harmonized degradation or BTI in isolation, while very few designs exist for TDDB,EM, and HCI.This chapter introduces background and designs for several novel and improved on-chip sensors that provide effective isolation for all four of the aforementioned key semicon-ductor LTR mechanisms to enable per-mechanism monitoring outside of foundry labora-tories for various use cases. Isolated measurement of all key mechanisms can help improvethe confidence of lifespan predictions under varied customer use conditions by avoidingassumptions of uniform behaviour across stress conditions introduced by product-levelacceleration factors and by providing more fine-grained test data that increases the quan-tity of useful information that can be extracted from any given ALT. Each sensor designis described in detail and novelty within the context of prior art is discussed, thoughgreater focus is placed on the sensors for isolated monitoring of BTI and HCI giventhat they were the original targeted mechanisms for monitoring within the scope of thisresearch work. All sensors are physically implemented in a 12nm FinFET process forexperimental validation, which is discussed in Ch. 3.2.1 Explicating Transistor Stress RegimesFor transistor wear-out mechanisms in particular, isolation of individual phenomena isdifficult since most voltage stress regime configurations induce multiple mechanisms. ForBTI and TDDB, any non-zero electric field across the gate dielectric produces someamount of stress, and similarly HCI is induced by any current flow through the transistorchannel. Maximum stress magnitudes are achieved by maximizing current flow and elec-tric field strength; these maximal stress regimes for both NMOS and PMOS transistorsare depicted in Fig. 2.1, with bulk terminal connections neglected given existing workshowing a low dependence of wear-out on body bias in modern fabrication processes [107].For stress regimes where the drain and source of the transistor are at the same po-tential, negligible current flow occurs and thus no HCI degradation. Additionally, whenthe gate potential is opposite that of both the source and drain, both BTI and TDDBstress are maximized as the electric field Ef in the dielectric is uniformly maximizedacross the channel. In contrast, when the drain and source have a potential difference(such as in the HC-N stress regime), current flow induces HCI, and though the electricfield magnitude within the dielectric is still maximized between the gate and one of thechannel terminals, the field magnitude is non-uniform and decreases across the lengthof the channel. The relative rates of BTI and TDDB degradation under uniform versus292.1. Explicating Transistor Stress RegimesFigure 2.1: Achievable maximal stress regimes in CMOS transistors with reference iden-tifiers. Drain-source symmetry is assumed and bulk terminals neglected, revised from [4].non-uniform dielectric fields are not well studied, but limited literature coming from aphysical modelling perspective supports an expected decrease in both BTI and TDDBdegradation under HCI stress due to a gradual reduction in dielectric field potential overthe channel region approaching the transistor drain (given the equipotential of the gateand drain terminals) [108]. Developing a detailed physical model is out of scope for thisdissertation, but pointing out a couple possible directions for modelling helps to buildan intuitive reasoning for the expected decrease in stress and corresponding degradationreduction. The non-uniformity could be simplistically modelled as a decrease in effec-tive dielectric area for TDDB (which is commonly modelled as following a Poisson-lawarea scaling relationship [109]), or by segmenting the channel length into smaller chunkswith approximately uniform potential field and considering TDDB and BTI separatelyfor each chunk (then integrating over the full length of the transistor). In any case,although an intuitive reduction in effective stress can be expected, the two mechanismswill still progress in these stress regimes at some reduced rate. This makes perfectlyisolated monitoring of the HCI mechanism infeasible as no stress regime exists havingnon-uniform drain and source voltages without some amount of electric field stress. Theproposed sensors for monitoring HCI are thus focused on isolating degradation underthe HCI stress regime from which the reduced contribution of the BTI mechanism cantheoretically be compensated for via a physical model following an approach such as thetwo potential directions discussed above.302.2. Isolating BTI and HCI via Modified Ring OscillatorsDegradation under reverse bias is typically seen to be negligible in the literature,thus rarely studied, and often the reverse bias regimes are considered to be recoverymechanisms where degradation induced by forward-bias aging can be partially reversed[47]. For this reason the proposed sensor designs for BTI and HCI assume that reverse-bias degradation does not significantly impact RO behaviour in comparison to forward-bias aging, but acknowledge that in future processes this assumption could be shown tofail, however unlikely. In such a process, isolating forward-bias BTI and HCI via on-chipsensors would likely be infeasible.2.2 Isolating BTI and HCI via Modified Ring OscillatorsThe first sensor design developed is closely aligned with the majority of existing ap-proaches in the literature. The class of sensors is based on tracking the free-runningfrequency of RO circuits, which decrease as degradation progresses. A basic RO consistsof an odd number of digital inverters connected in a loop, resulting in an astable cellthat continually oscillates. These circuits are ideal for monitoring wear-out in many ap-plications due to their simplicity, ease of on-chip measurement, and existing prevalence.Standard ROs are poorly suited for careful measurements as they experience harmonizeddegradation as a result of competing BTI and HCI mechanisms and their frequency isdependent on process, voltage, and temperature (PVT) conditions. An ideal wear-outsensor based on ROs modifies this structure to allow for separable monitoring of BTI andHCI degradation in NMOS and PMOS transistors (leading to the PBTI and n-HCI mech-anism subclasses in NMOS transistors and NBTI and p-HCI in PMOS) while minimizingthe impact of temperature and voltage fluctuations.2.2.1 Related Sensor Designs in Prior LiteratureExisting sensor designs based on ROs supplement the base digital inverter chain structurein various different ways. Extensive survey of existing RO-based wear-out sensors revealedthree broadly definable techniques that are used to classify the designs. The first identifiedclass does not induce degradation of the RO transistors themselves but instead limitscurrent flow to the RO stages through a transistor that is stressed to degrade in someparticular manner over time [110, 111]. Although these designs have the benefits ofsimplicity and minimal layout area overhead, the single degraded transistor and limitedcurrent flow can increase susceptibility to PVT variations. This drawback is mitigatedvia an additional reference transistor that allows for differential comparison in a designby Singh et al. [111], which makes it the most sophisticated prior sensor in the category.312.2. Isolating BTI and HCI via Modified Ring OscillatorsThe second class of designs rely on asymmetric structures to have the contributionof some wear-out mechanisms dominate the overall frequency degradation over others.One approach to achieve this through sizing transistors differently to create asymmetriccapacitive loads and drive strengths, thus minimizing degradation in either NMOS orPMOS versus the other [112–115]. Other techniques include the use of I/O transistorsinstead of asymmetric sizing or variable gate voltages to adjust stress magnitudes foreach transistor [116] [117]. The main drawback of these approaches is that they areineffective in cases where certain mechanisms dominate others (a situation frequentlyfound in the literature [37, 38]), effectively cancelling out the asymmetry and resultingin non-dominant overall degradation behaviours.Finally there are full isolation approaches that attempt to completely avoid stressregimes that induce certain mechanisms. The simplest case of this, and by far the mostcommon, is stress states with zero current flow, preventing any forward-bias HCI degra-dation from occurring. The resulting circuit only experiences BTI degradation, andfurthermore, techniques can isolate only NBTI or PBTI through zero-current schemesthat age all RO stages under identical voltage stress. In a standard inverter chain underDC conditions the node voltages are identical in every even-numbered stage and invertedin the odd ones, so pure NBTI or PBTI can be achieved by either using one RO tocontrol stress voltages in another [118], stressing a standard RO then bypassing everyother stage during measurement [112, 113, 119], separated voltage rails for odd and evenstages [120], the use of multi-input logic gates that introduce extra inputs to make allstage voltages identical [112, 113, 121], or through switching out some stressed stagesfor unstressed alternates during measurement [116]. A more involved but controllablemethod is to modify the RO stages themselves, such as stacking transistors to isolatethe core inverter pair [122, 123] or through biasing transistors to force input and outputnodes to specific voltages [47, 124].The proposed RO-based design follows the approach of using pull-up and pull-downbias transistors with passgates between stages to individually control node stress voltages,as seen in Guo and Stan’s and Tsai et al.’s topologies [47, 124]. The design improves overthese two previous works by introducing sensor variants to isolate the HCI stress regimesand by introducing variants with weak, complementary biasing transistors to reduce thepotential for degradation-induced capacitive increases in opposite type biasing transistorsfrom affecting overall wear-out behaviour.322.2. Isolating BTI and HCI via Modified Ring Oscillators2.2.2 Topology and Principle of OperationSingle RO stage schematics for all eight developed variants of the sensor design areshown in Fig. 2.2, with terminal names and intermediate node voltages during DC stressmode operation (which occurs when the en signal is high) labelled alongside shadingcorresponding to the stress regimes from Fig. 2.1 experienced by each transistor.Figure 2.2: Schematics of the eight variants within the proposed RO-based sensor design.Shading corresponds to the stress regimes experienced by each transistor during stress-mode operation when en is high. Revised from [4].332.2. Isolating BTI and HCI via Modified Ring OscillatorsThe standard BTI variants match the topology seen in Guo and Stan’s design [47].During measure mode operation (strs en is high) all Q5/Q6 biasing transistors are incutoff and the passgates formed by Q3 and Q4 at the end of each stage are opened, form-ing an RO with the Q1/Q2 central inverter transistors in each stage connected together.As transistor stress regimes are not controlled during measurement, measurement timesare minimized to ensure that this measure-mode aging has a minimal impact on overalldegradation. As an example, a second-long measurement taken every hour would lead toa 3599:1 stress-to-measure mode degradation profile ratio. The custom automated accel-erated test system described in Sec. 3.2, which still relies on slower off-chip measurementtechniques, uses a frequency measurement window of approximately 0.244ms and thusallows for a stress-to-measure ratio of 14745599:1.The complementary biasing variants are developed to address the concern that forward-bias stress in the Q5/Q6 pull-up and pull-down transistors, seen in the base variants, mayexperience capacitance degradation that could affect overall frequency degradation [125].As an example, consider a theoretical process that experiences no NBTI degradation butsignificant PBTI degradation. In such a process, the inverter in the base NBTI varianttopology would not degrade, however PBTI in the NMOS pull-down transistor could shiftthe load capacitance and thus the oscillator free-running frequency, yet be misattributedto NBTI degradation. In the complementary biasing variant, the PMOS pull-down tran-sistor is both of the same type as the stress PMOS inverter transistor and experiencesreverse-bias degradation during stress. The drawback of this topology is that biasingstrength is significantly reduced and so overvoltage is needed to obtain equivalent stressmagnitudes, particularly in the HCI variants. Though extreme situations such as the ex-ample are unlikely, complementary biasing variants can challenge assumptions regardingcapacitance degradation and dominance of specific wear-out mechanisms.With an odd number of sensor stages of a given variant connected, the output ofan arbitrary stage can be tapped for frequency measurement. This tap should imme-diately be buffered to minimize capacitive loading of the stage. Oscillation frequencyheavily depends on the number of stages in an oscillator and on layout-specific parasiticcapacitances. For sensor implementation, the stage count must be high enough to slowoscillations such that voltage levels can saturate between successive state changes in eachstage. Additionally, due to variability between transistors, a larger stage count reducesthe impact of device-to-device variability to better track average wear-out performance,though chip-to-chip and lot-to-lot variability will impact all stages uniformly and so can-not be neglected. There may be situations where multiple sensors are used to characterizevariability in which lower stage count is desirable.342.3. Isolating BTI and HCI via Differential Offset Voltage Amplification2.3 Isolating BTI and HCI via Differential Offset VoltageAmplificationOne drawback of wear-out sensors based on ROs is that they require a precise timingsource to be available for measurement. Sensors based on other approaches and circuittopologies exist, but many of these have the same limitation, such as aging sensors basedon phase-locked loops [126], timed delay lines [127], or metastability resolution time [128].Since BTI and HCI degradation can have more complex impacts on analog circuit designs(as opposed to mainly delay increases in digital logic), there is extra incentive to provideisolated monitoring of these two mechanisms for primarily analog chips. Purely analogsemiconductor devices are far less likely to have precise timing sources available, and sothe previously presented RO sensors are less well suited to such cases. This motivatedthe development of an analog sensor design that can be measured using DC techniquesthat are more likely to be available in or near analog ICs. This section presents a novelsensor to fill the niche based on characterizing the induced offset voltage of a differentialamplifier as degradation progresses.2.3.1 Related Sensor Designs in Prior LiteratureDespite the majority of existing sensors for BTI and HCI measurement requiring timing-based measurement to utilize, there are some prior art proposed designs that can beused in DC-only applications. Of nine approaches found through extensive survey, onlytwo were physically implemented, corresponding to the two earliest works. The first,fabricated in a 150nm process, is an aging threshold monitor that compares the drivestrength of two inverters with one being stronger but also degrading with time until itis unable to compete with the reference [129], while the second, in a 65nm process, tapsa voltage of concern in an analog circuit design and uses it to bias a common gate am-plifier such that the latter degrades at rate comparable to the former [130]. All sevenremaining proposed designs are based on simulation results alone and leverage a varietyof circuit design techniques. Mostafa et al. use “native” transistors in circuitry for HCIisolation [131], a device type for which very little reliability research exists, while Shahet al. leverage Darlington pairs to sense leakage currents in target circuits of interest[132]. Leakage current sensing can also be achieved in static memory cells [133]. Theremaining proposed designs directly look at Vth degradation through approaches such asdiode-connected Vth extraction circuits [134] or degradation of a transimpedance ampli-fier transfer function [135].352.3. Isolating BTI and HCI via Differential Offset Voltage AmplificationThe final two proposed designs most closely match the design philosophy of the novelsensor proposed in terms of leveraging a differential measurement approach with amplifi-cation that provides increased precision and good resilience to inherent PVT variability.A topology from Wan and Kerkhoff uses a pair of matched transistors with only oneexperiencing BTI stress while the other remains unstressed as a reference [136]. Mea-surements consist of using a digital to analog converter (DAC) to sweep the gate voltagewhile an analog to digital converter (ADC) monitors the drain voltage to plot out thetransistors current-voltage characteristic function. This approach provides insight intodegradation effects across the gate biasing range of the devices, but the two transistorsmust be measured subsequently instead of simultaneously, reducing PVT resistance, andsome of the supporting circuitry is only considered at an abstracted level. Additionaldevelopment would be required to provide topologies for these sub-circuits that either donot degrade significantly or do not influence measurements as they degrade. The finaldesign by Strong et al. also uses a differentially-aged matched transistor pair, but mea-surement is conducted through biasing the source voltages using a DAC while monitoringa comparator output to find the point at which the transistor pair is effectively matchedvia source voltage compensation for degradation [137]. This approach effectively accountsfor stress-induced degradation in key supporting (ancillary) transistors within the sensordesign, and is likely the best overall prior art design in the surveyed category. Bothof these differentially-aged transistor pair sensors are only designed for BTI mechanismisolation, however, and neither has been physically verified.The novel sensor topology proposed in this dissertation is, to the best of knowledge,the first to allow for isolation of both BTI and HCI stress regimes in both NMOS andPMOS transistors, the first to account for degradation in all supporting circuitry, andthe first to provide a direct differential output voltage that can be read out as a singleanalog voltage while negating localized PVT variability. Additionally, this is the first pro-posed sensor design in the class to be physically implemented in a non-planar fabricationprocess, the details and results of which will be discussed in Ch. 3.2.3.2 Topology and Principle of OperationThe methodological approach for the proposed DC measurement sensor for BTI and HCIisolation is to apply differential stress to the input pair of a pseudo-differential voltageamplifier to induce an amplifier offset voltage that increases proportional to Vth degra-dation. The effectiveness of this approach is evidenced by prior art that uses amplifieroffset voltage as a proxy for Vth degradation in schemes for measuring BTI without in-curring recovery [138]. This has the benefits of using a well-studied amplifier parameter362.3. Isolating BTI and HCI via Differential Offset Voltage Amplificationthat hardware engineers have existing familiarity with and excellent resilience to PVTvariability via differential design. The schematic for the NMOS variant of the sensorcore is shown in Fig. 2.3 containing the pseudo-differential offset amplifier and the stressvoltage control transistors. The PMOS input pair variant is the complementary mirror,only differing in terms of output polarity and slight differences in amplifier gain whichcan be compensated for during Vth back-calculations.Figure 2.3: Schematic of the threshold voltage sensor differential offset amplifier topologywith measure mode analog bias voltage labels. Revised from [2].Within the schematic, transistors Q1 and Q2 form the differential input pair. Instress mode (en = 0), transistors Q7 through Q14 in the inverters are used to set thedrain and source bias voltages to prevent wear-out in Q2 while placing Q1 into one ofthe desired stress regimes of interest from Fig. 2.1. Amplifier transistors Q3 through Q6are kept in cutoff during stress mode operation. Switching to measure mode operation(en = 1), all inverter transistors are in cutoff while Q5 and Q6 (designed with largertotal area) are maximally biased to pull the source nodes of the input pair to ground.A mid-range analog common mode input voltage Vcm and drain resistance bias voltageVdr are applied to Q1/Q2 and Q3/Q4 respectively to amplify the degradation-inducedoffset voltage between Q1 and Q2 to the differential output Vout. The DC operation372.3. Isolating BTI and HCI via Differential Offset Voltage Amplificationof the sensor isolates the output from any possible AC parameter degradation, and thedifferential measurement isolates the reading from instantaneous shifts in temperatureand input voltage, with only the amplifier gain remaining susceptible to PVT variability.The pseudo-differential amplifier topology provides worsened common mode rejectionversus a fully differential design, however this is of minimal importance since the amplifieris not used functionally; the input signal Vcm is a voltage reference that remains constant.The similarly worse power supply rejection of the pseudo-differential topology is worthnoting as a tradeoff of increasing the available output voltage range by avoiding a tailcurrent bias. By sizing transistors Q1 through Q4 and selecting Vcm and Vdr to provide abalanced combination of high gain and gain stability, the gain shift with variations can beminimized to ensure the difference between initial and degraded readings directly tracksthe shift in threshold voltage of Q1, ∆Vth (see Sec. 3.1.4 for gain simulations in the linearregion across process corners). Note that mechanisms such as HCI can also affect otherdevice parameters of Q1 such as saturation current [53]; these additional degradationeffects are only observed as part of an effective ∆Vth or may pass undetected.Although classical transistor models are inaccurate for modern fabrication processesand simulation models must be relied upon for precise characterization of amplifier gain, aclassical differential amplifier analysis following a standard textbook approach can providefunctional intuition as to sensor operation [139]. The proposed sensor differs from thecanonical differential amplifier and so five assumptions are needed for equivalent analysis,though all are validated by hand calculation and/or simulation:1. Transistor matching quality is sufficient for a single-sided amplifier analysis.2. Transistors Q5 and Q6 are sufficiently large with sufficient bias to treat their drainterminals as effective ground nodes for a standard pseudo-differential single-sideanalysis.3. Leakage currents of transistors Q7 through Q14 in cutoff during measure mode arenegligible in comparison to the drain current ID in transistors Q1 and Q2.4. The degradation-induced shift ∆Vth is reasonably small so that a small signal linearapproximation at the DC bias point can be used.5. Channel-length modulation parameter λ can capture the majority of non-ideal tran-sistor effects such that other complexities of scaled transistors can be neglected.Given these assumptions, the DC bias point for the single-sided amplifier analysis can bedetermined through a numeric convergence of the non-linear saturation current balancebetween transistors Q1 and Q3 as shown in Eq. 2.1. Effective transistor parameters kn,382.3. Isolating BTI and HCI via Differential Offset Voltage Amplificationkp, λn, and λp, in combination with the VDD, Vcm, and Vdr bias voltages and initial/freshthreshold voltages Vthn and Vthp are given to determine VD1 (and thus ID).kn(Vcm − Vthn)2(1 + λnVD1)= kp(VDD − Vdr − |Vthp|)2(1 + |λp|(VDD − VD1))(2.1)The resulting bias point gives small signal model parameters gm1, ro1 and ro3:gm1 =2IDVcm − Vthn , ro1 =1λnID, ro3 =1λpID(2.2)The small signal amplifier model gives the voltage gain, treating ∆Vth as a differentialinput voltage in Eq. 2.3.vd1 = −12gm1∆Vth(ro1||ro3) (2.3)The only remaining manipulation to obtain the full gain expression is to realize that∆Vth is only applied to a single input, thus the differential input is half the thresholdshift, giving:Vout∆Vth= −12gm1(ro1||ro3) (2.4)This final expression looks exactly like a pseudo-differential output amplifier with anoffset voltage that increases as wear-out progresses according to the stress regime appliedto Q1.To provide the control logic, bias voltages, and further output amplification for thedescribed sensor core, supporting circuitry is required as shown in Fig. 2.4. A separatesupply voltage GVdd is gated except during measurement, which, in combination withpassgates and leakage-based pull-down bias transistors placed in front of the additionaloutput amplifier inputs, prevents any degradation in the analog supporting circuitry fromoccurring regardless of the specific topologies used. Degradation of the digital circuitrythat is on during stress does not impact the amplifier according to assumption 3, statedpreviously, and the DC operation of the sensor design. The stress control multiplexinglogic provides four configurable digital signals (Vs7, Vs9, Vs11, and Vs13) that set the drainand source stress voltages for Q1 and Q2. Finally, analog multiplexing is used in the gatebias control block to propagate the Vcm and Vdr bias voltages to the sensor core duringmeasurement (alongside the configurable stress voltages Vs1 and Vs2 for the Q1 and Q2gates). The full sensor design thus applies an arbitrary maximal stress regime to sensor392.4. Gate Leakage Current Sensing for TDDB Risk AssessmentFigure 2.4: Higher-level schematic of the full proposed differential offset amplifier sensordesign showing supporting circuitry required for operation, revised from [2].core transistor Q1 to induce a threshold voltage shift that can be read out as an amplifiedoffset voltage, with the difference between initial and subsequent measurements allowingfor characterization of the transistor ∆Vth degradation over time. Note that the outputamplifier shown uses a single-ended output to match the implemented version that willbe described in Sec. 3.1.4, however a differential output would be preferable and wasonly avoided due to pin count limitations for off-chip measurement.2.4 Gate Leakage Current Sensing for TDDB RiskAssessmentTypical test structures for TDDB wear-out characterization use large gate dielectric areasto increase the probability that a failure occurs during some test [91]. Based on theassumption of Poisson area scaling, the time-dependent failure probability for a standardtransistor can then be estimated according to its gate area ratio to the test structuresused. To propose a sensor for evaluating TDDB failure risk without massive dielectric areaand with reduced variability, SILC is leveraged as a related mechanism where resulting402.4. Gate Leakage Current Sensing for TDDB Risk Assessmentgate current increases can be used to estimate TDDB-causing defect formation rates andthus the corresponding TDDB failure risk. In SILC, quantum tunneling is the primarysource of increasing gate current, meaning all formed defects contribute to the overallcurrent increase (proportional to their position and clustering within the gate dielectric)as opposed to only those in the classically conductive path that forms to produce a TDDBfailure. The sensor therefore gradually degrades as opposed to experiencing sudden failurewithout prior indication, and can be smaller given the sensitivity to each defect ratherthan just the final conductive chain.2.4.1 Related Sensor Designs in Prior LiteratureFar fewer prior designs exist for TDDB sensing than for BTI and HCI due to the suddenrandom nature of gate dielectric breakdown as opposed to the gradual degradation of Vthinduced by BTI and HCI. Survey revealed existing work that is grouped into three cate-gories based on how they overcome the challenge of single failure point observation. Someprior literature claims to monitor TDDB through incidental observation of breakdownfailures in non-specialized circuits [118, 140], however these contribute no TDDB-specificdesign considerations and are thus not discussed.The first design category tracks environmental conditions to compute accumulatedTDDB stress [141]. Mathematical models are relied upon to predict failure risk insteadof monitoring TDDB directly. The second category compares circuit delays dependenton SILC gate leakage against references in a manner similar to some of the RO-basedsensors seen in Sec. 2.2.1, such as using the gate leakage to limit voltage slew rate at theinput to a Schmitt trigger which is integrated into an RO [142]. The frequency of theoscillator increases with time as defect formation increases gate leakage. Two other priorworks exist in this category but are less well developed and not experimentally verified[140, 143]. None of these sensors account for additional frequency degradation due toBTI and HCI. The final category treats the gate dielectric as a time-varying resistorby subjecting a transistor to TDDB stress then using an applied voltage differential toinduce SILC leakage that is then measured by proxy. Keane et al. perform measurementby pre-charging a voltage differential then allowing the charge to dissipate through thestressed transistor dielectric [144], while Kumagai et al. instead use the leakage currentto gradually charge a capacitor [145]. In both these designs the stressed transistor’sgate voltage changes over the course of the measurement, resulting in non-constant gateleakage current. Deviations of tunneling current behaviour from an ideal resistor can thusresult in errors when back-calculating resistance. The final design by Bhatheja et al. doesprovide a constant measurement voltage via a current mirror measurement scheme [146].412.4. Gate Leakage Current Sensing for TDDB Risk AssessmentThe proposed sensor measures integrated charge on a capacitor as a proxy for thedirect gate leakage current, similar to Kumagai et al. but with additional benefits. Thegate voltage is held constant to ensure constant leakage current, and amplification reducesthe challenge of measuring the current. No external calibration procedure or biasing isneeded to back-calculate the gate dielectric leakage and overall circuit complexity isreduced relative to existing designs in the third category.2.4.2 Topology and Principle of OperationThe key challenge in measuring SILC is that the gate leakage current magnitude is ex-tremely small and cannot be measured directly. The proposed design overcomes thisthrough the use of a current mirror with amplification to provide a larger current ca-pable of charging a capacitor. Fig. 2.5 shows the schematic for the sensor, inspired byphotodiode read-out circuits and modified to allow for two mode stress-measure oper-ation. A PMOS sensor variant is also designed and is simply the complement of thepictured NMOS schematic. In stress mode, pull-down transistor Q6 identically biasesthe source and drain of the stressed device under test (DUT) transistor, Q1, placing itinto a maximal TDDB/BTI stress regime with a uniform electric field magnitude. Thisstressed transistor sizing is large to increase the total gate dielectric area in which defectformation occurs and thus a greater leakage current and probability of TDDB failure.Figure 2.5: Schematic of the SILC sensor gate leakage current extraction circuit. The ensignal goes high during stress and drops to a logic low to begin a measurement. Revisedfrom [3].422.5. Staggered EM Failure Sensor for Degradation MilestonesMeasurement consists of placing Q6 into cutoff, at which point the gate leakage cur-rent of Q1 establishes a gate bias point for Q2. This bias point is identically applied toQ4 to form a cascoded current mirror, with the channel area ratio k providing amplifica-tion of the leakage current. A crucial design consideration is that the channel and gatedielectric leakage currents in the other transistors could impact and even overshadowthe DUT dielectric current if not addressed. Gate leakage in these ancillary transistorsis minimized through the use of I/O transistors (indicated by grey dielectrics in Fig.2.5) within the fabrication process that have significantly thicker gate dielectric layers,greatly reducing electron tunneling currents, and use of increased sizing of DUT Q1 incomparison to these transistors. Channel leakage in Q6 and Q7 is minimized via tran-sistor stacking, reducing the voltage differential across the channel in each device withinthe stack.Measurement of the SILC leakage current is achieved using the capacitor and pull-up Q7 to bias the drain of Q4 to VDD prior to measurement, then Q7 placed in cutoff,allowing the current mirror to charge the capacitor over time. The drain voltage ofQ4 decreases according to Eq. 2.5, with a source follower output stage to isolate thedischarging node from any load resistance and capacitance, thus allowing for accurateDUT leakage current estimates to be calculated. The parameter k is the current mirroramplification, C capacitance, t time, Vout the source follower output, and Igate the DUTleakage current.Igate = kCdVoutdt(2.5)Note that the source follower output voltage ranges from VDD−|Vth| down to Gnd +Vth over which the voltage slope can be characterized. This computed current can be usedto estimate defect formation; an equation for this is not provided as SILC and TDDB riskmodels for defect types, potentials, and dielectric stackup are process-dependent and lackconsensus in the literature. Although Q6 and Q7 experience forward-bias aging duringstress mode operation, BTI and HCI in these transistors does not affect circuit outputbehaviour as they are both in cutoff during measurement.2.5 Staggered EM Failure Sensor for DegradationMilestonesThe first three proposed sensors cover all the known significant wear-out mechanisms inmodern transistors, which are of primary importance to monitor due to quantum effectsand the significance of single-atom defects that frustrate full physical understanding432.5. Staggered EM Failure Sensor for Degradation Milestonesand modelling. Although EM is well-characterized in comparison, making sensors lessimportant for improving physical understanding, it also makes EM valuable as a referencefor tracking in-field wear-out progression. If an EM failure is observed in an interconnectwith a known Vdd to current density relationship, the failure time can be used to estimatethe effective temperature and voltage stress experienced up to that point. A simple EMsensor to mark wear-out “milestones” was developed to benefit an overall SLM on-chipmonitoring solution.2.5.1 Related Sensor Designs in Prior LiteratureFew existing on-chip sensors for EM exist as a result of the reasonable physical under-standing of the mechanism. There are numerous works that develop effective in-lab teststructures for EM [147], and continued efforts are needed for new EM-susceptible struc-tures in advanced fabrication processes [92], however such topologies are not suitable forin-field use.Only four existing on-chip monitoring solutions for EM were identified through sur-vey. The first monitors interconnect resistivity rather than full line failures [148]. Bymeasuring the voltage drop across an interconnect segment with known current flow, theresistance can be determined through analog voltage measurements. The second designshares many qualities with the first but monitors resistivity in segments as opposed tothe full length of the line [149]. By tapping the line at multiple points and applying avoltage differential the interconnect acts like a voltage divider, providing a set of voltagereadings that can be used to track where resistivity is increasing along the line and byhow much. The third design compares the resistivity of a set of lines subjected to EMstress to an unstressed single reference line [150]. When the resistivity of the parallel setsurpasses the single line the sensor output switches logic levels. This design bridges thegap between precise resistivity monitoring versus only tracking full interconnect failures.The final design from Mayahinia et al. shares commonalities with the third sensor and isthe most similar to the design presented here [151]. Used to monitor the EM failure riskfor circuits of concern, the resistance of a test line is compared against a reference usingan amplifier to create failure thresholds. To provide multiple successive points of failurethat indicate wear-out progression, several lines with different current flow are placed,resulting in different sensor failure indication times.The proposed sensor design follows a similar approach to the final sensor designusing successive failures of binary state outputs, but with key differences: i) the sensorinterconnect lines do not correspond to any circuit of concern and are used as a standalonedesign for drop-in use, and ii) sensor complexity is greatly reduced in comparison to all442.5. Staggered EM Failure Sensor for Degradation Milestonesexisting designs, requiring no amplification, comparison, or analog voltage measurement.The drawback is that the topology is not capable of analog resistivity measurement, butthis is not as important towards the objective of marking wear-out milestones.2.5.2 Topology and Principle of OperationThe proposed staggered sensor design is based upon running an adjustable currentthrough an interconnect line to induce EM failure, using two transistors configured asresistors for current control and to enable a binary signal output. By adjusting transistorsizing across multiple lines, failures can be expected to occur at different points of interestthroughout a product’s lifetime and thus allow for specific milestones in a product’s use-ful life to be identified as a comparative reference for characterization of other wear-outmechanisms (subject to inherent EM variability). Multiple sensors with identical sizingcan also be implemented to characterize EM variability if desired. A schematic of theimplemented version of the proposed design is shown in Fig. 2.6, containing a total ofeight lines that are multiplexed to reduce the sensor to a single output.Figure 2.6: Schematic of the staggered electromigration failure sensor. Interconnectfailure state is visualized as a normally-closed switch.452.5. Staggered EM Failure Sensor for Degradation MilestonesEach sensor interconnect line is located between two transistors configured to actas constant resistors. The NMOS transistor is sized to be several times larger thanthe PMOS device to bias the intermediate voltage below the threshold for a logical lowvoltage. A tap is placed on the high-voltage end of the test line and fed to a digital invertersuch that once the line resistance increases and eventually acts as an open circuit due toEM, the voltage will transition to a logical high and flip the inverter output.The number of transistor fins (i.e., transistor area) determines the total current flow toinduce EM; relative transistor sizing of the NMOS and PMOS remains at a fixed ratio. Bykeeping the EM-sensitive interconnect segment width fixed, the effective current densitycan be increased or decreased to adjust the mean time to failure for each line. Thechoice of target failure times to size the transistors for across a sensor implementationwould depend on the application of interest. All selected currents should generally besignificantly above typical current density seen in a well-designed circuit layout if failuresare to be observed, however. As a design guideline, following Black’s equation (seeSec. 1.4), a linear spread of intended failure times corresponds to an inverse power-lawdistribution of current densities.46Chapter 3Sensor Implementation, Testing,and EvaluationTo evidence that the proposed sensor designs introduced in the previous chapter are suit-able for use in modern process nodes, implementation in a FinFET node was prioritizeddespite the larger relative design time investment required over older processes. This rel-ative difference primarily arises from increasing complexity in terms of transistor layouttechniques, high mask layer counts, and more stringent design rules that must be met.Although recent process nodes as of writing are adopting 2nm minimum feature sizes,GAAFETs, and channel Ge incorporation, sensors validated 12nm FinFET are demon-strated to be applicable to high-κ metal gate, non-planar processes that exhibit quantizeddegradation behaviour due to atomic-scale feature sizes. Considering that the majority ofexisting sensor designs are validated purely through simulation, and those that have beenfabricated have used less advanced fabrication nodes (aside from one RO-based sensorin 7nm FinFET [152]), the process was deemed to be more than acceptable for effectivevalidation of the proposed designs. To ensure foundry intellectual property protection, nodetailed process information is presented in this dissertation; all layout diagrams use ab-stracted block diagrams, exact layer stack-ups are not provided, and experimental resultswill be shown in arbitrary units since for the purposes of sensor validation the specificreliability of the process used is irrelevant. Some comments on the relative magnitudeof wear-out mechanisms observed in scaled CMOS are provided to evidence and furtherreliability trends presented in Sec. 1.5 and demonstrate the effectiveness of the proposedsensor designs in isolating individual mechanisms.The completed sensor implementations represent a massive time investment acrosstwo chip tape-outs, with engineering team sizes of only one and two for the first andsecond tape-outs respectively to complete the entire design process. The first customtest chip, designated TC1 and with layout shown in Fig. 3.1, contains implementationsof the RO-based sensor, induced offset voltage sensor, staggered EM sensor, and somestandard ROs for reference. The second, TC2, contains the TDDB leakage current sensor.47Chapter 3. Sensor Implementation, Testing, and EvaluationFigure 3.1: Top-level layout of the TC1 chip. The RO-based sensor instance groups andEM sensor are seen in the middle-left region, with the induced offset sensor instances allcontained within the lower-middle isolated analog region.Many design steps were required that will not be discussed within scope, such asthose to learn the 12nm FinFET process development kit, design ancillary circuitry re-quired to supply, control, provide electrostatic-protected I/O for the proposed sensors,conduct multitudes of rigorous design verification steps to ensure correctness and strictfoundry compliance, and bring up the packaged devices once received from the foundry.Additionally, the high complexity of chip design incurs significant risk, as any tiny flaw,such as one erroneous via overlap among millions in a power distribution network, hasthe potential to render the entire chip non-functional. Keeping technical overheads andrisks in mind when considering research implementations of hardware designs should beemphasized, and it is extremely fortunate that the chip designs presented in this chapterwere functionally successful.483.1. Physical Layout in 12nm FinFET3.1 Physical Layout in 12nm FinFETAside from physical design challenges specific to individual sensors, there are generalchallenges with working in a 12nm process that need to be overcome to ensure a func-tional, foundry-compliant layout. The majority of the physical design elements addressedare not necessary to discuss as part of sensor evaluation, however specific FinFET consid-erations, electromagnetic coupling, power distribution, and parasitics management areworth brief overview prior to sensor layout specifics. Manual hand layout is used forphysical design due to the presence of analog elements within each sensor design, andsince specific desired layout properties for the RO implementations (discussed in Sec.3.1.3) were not considered by automated layout tools available.3.1.1 Front End Design ConsiderationsIn nanometre-scale FinFET fabrication, feature patterned areas and density end up play-ing significant roles in manufacturability. The consequence of this for physical design isthat transistors cannot be placed individually without a massive area overhead of non-functional mask features surrounding that transistor to meet minimum area and densityrequirements. Instead, large areas (relative to an individual transistor) must be allocatedand then transistors must be arranged within pattern constraints. Maximum transistordensity can only be achieved through careful allocation to maximize terminal sharing(e.g., a single physical gate running across multiple transistors sharing a common gatenode) and ensuring interconnect complexity remains low in a given region (as metal in-terconnect sizes are large compared to closely packed transistors). Although maximumdensity is not a concern for the overall design as the full square millimetre test chip areascontain far more than enough space for the design complexity, parasitics minimization,achieved by keeping interconnect run lengths short, is crucial for ROs and gate leakagesensors.A balanced approach is taken to front end design, with significant time dedicatedto devising dense, tileable layouts for RO stage implementations but a reasonably time-efficient approach used for less crucial supporting logic. For the densest RO cells, theapproach is to allocate symmetric PMOS and NMOS patterned regions that containall transistors for a given stage. Significant sharing of drain and source terminals isachievable within these patterned regions, and where spacing is required between de-vices non-functional “dummy” transistors are used to maintain mask pattern continuity.The designs are moderately dense from a hand layout perspective but could be furtheroptimized given additional engineering hours and careful use of automated layout tools.493.1. Physical Layout in 12nm FinFET3.1.2 Back End Design ConsiderationsWith transistor placements set, over a dozen interconnect layers are used to link allthe devices together. Layout complexity is minimized by allocating most layers to onlycontain interconnect lines running either vertically or horizontally, with some exceptionsas needed. The two major concerns relevant to all elements within the chip design areelectromagnetic coupling minimization and power distribution resilience to EM.With around 50 oscillators running at extremely high frequencies during measure-ments, it is important to ensure that radiation does not couple to sensitive analog cir-cuits and impact readings. To provide maximum separation, the ROs and RO-basedsensors within the design are located far away from the induced offset voltage and gateleakage sensors, with separate power supplies used to minimize supply noise. Locally,crosstalk between ROs is reduced through avoidance of long parallel interconnect runsand using available die space and verticality to keep signals spatially separated (withshort perpendicular crossings where needed).The other major back end design challenge arises from the accelerated stress tests thatthe designs are subjected to. Though the ancillary circuitry used handles BTI and HCIby design and TDDB hard failure risks remain low on chips with transistor counts in themillions rather than billions, EM can occur during accelerated stress in power distributionnetworks if physical designs are poor, particularly since the staggered EM sensor designhas high current draw. Over-specified power distribution interconnect widths are used tomitigate this risk alongside redundant paths for nearly every supply and ground terminalconnection.3.1.3 Oscillator-Based Sensor LayoutThe proposed RO-based sensor design also contributes an approach for mitigating PVTvariability influences for comparison of semiconductor degradation mechanisms. Thenovel technique of interwoven RO layout is introduced where two (or theoretically more)ROs are made to experience nearly identical PVT conditions via coupled stage layout.Prior art has included adjacent placement that results in separation distances on theorder of micrometres between corresponding transistors in two ROs [153], however theinterwoven technique allows for separations of mere tens of nanometres in current pro-cesses, alongside shared power distribution and body biasing. This effectively negatesstochastic PVT influences on measured frequencies and couples self-heating effects be-tween ROs, allowing for extremely precise comparison of RO-based sensors under differentstress conditions. An abstract view of a single interwoven stage layout is shown in Fig.3.2, revealing how transistors within one oscillator are alternately placed with those of503.1. Physical Layout in 12nm FinFETthe other. The one potential drawback of the approach is increased interconnect lengthand thus parasitic capacitance in each oscillator, however high density layout using 3-finwidth transistors in the stages minimizes this increase such that parasitics remain lowrelative to transistor gate capacitance.Figure 3.2: Abstracted view of the introduced interwoven layout technique for the ROsensors. © 2024 IEEE [4]Leveraging the introduced interwoven layout technique, the implemented ROs contain51 stages to reduce free-running frequency and reduce the impacts of individual transistorvariability on overall RO frequency. As frequency measurements are conducted externalto the chip, multiplexers and frequency divider circuits are used to allow for multiplesensors to output on a single chip pin and meet I/O driver maximum frequency require-ments. In the final layout, the largest and highest power interwoven cell, containing twoHCI variant oscillator stages, occupies a total area of 4.02µm2 and consumes 125µW,which can be multiplied by n to find the maximum area and current for a pair of sensorswith n stages.3.1.4 Induced Offset Voltage Sensor LayoutFrom a physical design perspective, the DC operation of the induced offset voltage sen-sor mostly negates concerns over layout parasitics, but effective transistor matching isextremely important to sensor operation. Within the analog portion of the sensor core(refer to Fig. 2.3), matching of Q1 with Q2 and Q3 with Q4 is of paramount importance.Matching Q5 with Q6 is slightly less crucial due to their minimal impact on analog be-513.1. Physical Layout in 12nm FinFEThaviour so long as they do not introduce a substantial VDS drop. An abstracted viewof the NMOS variant sensor core layout used to achieve this matching is shown in Fig.3.3 with annotated transistor identifiers and functions. The smallest transistors withinthe design use 5-fin width sizing. The stress isolation passgates and leakage bias transis-tors placed before the additional amplifier from the supporting circuitry schematic areincluded in the sensor core layout.Figure 3.3: Abstract view of the induced offset sensor core layout. © 2024 IEEE [2]0 1 2 3 4 5 6 7 8 9 10 11Vth (mV)0.02.55.07.510.012.515.017.520.0Voltage gain (dB)Sensor differential gain across Vth for PVT variationsPMOS upper worst caseNMOS upper worst casePMOS nominal caseNMOS nominal casePMOS lower worst caseNMOS lower worst case10 20 30 40 50 60 70 80 90 100 110 120Sensor output (mV)0246810V th (mV)Vth Uncertainty due to PVT variation across sensor outputUpper boundLower boundFigure 3.4: Simulated gain and back-calculation uncertainty for the induced offset voltagesensor core across process variability corners. © 2024 IEEE [2]523.1. Physical Layout in 12nm FinFETThe sensor core layout occupies 17µm2 and the maximum power stress configurationresults in around 100µW of consumption. Supporting circuitry for the sensor core, namelythe voltage references and output amplifier, used basic topologies and a single-ended out-put to reduce chip pin usage (since voltage measurements were conducted external to thechip). These designs could be more sophisticated and include a differential output infuture implementations to improve sensor performance, though the basic designs are suf-ficient for validation purposes. The process-specific sensor implementation was simulatedto obtain expected small-signal gain for the sensor core. The process-variable gain andgain shift with increasing ∆Vth for the sensor in 12nm FinFET with tuned transistor sizesare shown in Fig. 3.4, containing an inset showing estimate errors for low magnitudes ofQ1 ∆Vth given a sensor core differential output voltage.3.1.5 Gate Leakage Sensor LayoutSimilar to the induced offset voltage sensor, transistor matching is the main concern forphysical implementation of the SILC sensor, though minimizing device leakage currents isalso important. The latter, as previously discussed, is achieved using I/O transistors andtransistor stacking, and a metal layer capacitor is selected for thicker dielectric separationbetween plates. Fig. 3.5 shows the implemented layout.Figure 3.5: Abstract FinFET layout view illustrating the SILC sensor implementationwith current mirror layout matching, revised from [3].533.1. Physical Layout in 12nm FinFETBoth NMOS and PMOS variants of the sensor are implemented with small and largeDUT dielectric area sub-variants for each, with 8-fin and 500-fin widths respectively. Off-chip voltage measurement required increased sizing of the capacitor and source followerto reduce voltage ramp rates and drive larger load capacitances. The front-end layoutarea of the largest variant implemented is 28.2µm2 and consumes less than 10nW as abenefit of measuring low gate leakage currents. The metal layer capacitor area is excludedsince it can be configured to use metal layers above the transistors where available in theback-end design. On-chip voltage measurement and industrial layout optimization couldsignificantly reduce required sensor area.3.1.6 Staggered EM Sensor LayoutAs the EM sensor operates at DC, capacitive parasitics are not a major concern, andresistance due to the high current density in the stressed interconnect has little impactso long as length is kept short. The only key consideration for sensor layout is ensuringthat EM failures are isolated to the intended interconnect, thus all other interconnectsand vias along the high current path must have duplicity. Fig. 3.6 shows an abstractedversion of the layout design used to meet this requirement.Figure 3.6: Abstract layout view of a staggered electromigration failure test line. Largerinterconnect cross-sectional areas are used except in the indicated EM failure line.Sensor implementation in the 12nm FinFET process intentionally did not follow theminimum and maximum sizing guidelines provided in Sec. 2.5, using an extremely broad543.2. Automated Accelerated Life Test Systemspread of current densities to validate sensor operation (with a largest drawing 25mA ofcurrent to test immediate failure functionality). The implemented version initially draws40mW across all sensor lines, decreasing as individual lines fail, and the total layout areaused for the sensor is 576µm2. Space and power draw could be significantly reduced ascompact layout was not prioritized and the largest sensor lines were significantly oversizedfor testing purposes.3.2 Automated Accelerated Life Test SystemOnce a chip design is fabricated, packaged, and initial functionality testing is complete,ALTs can be conducted. These tests require precise stress condition control and monitor-ing over hundreds of hours, repeated measurement of all chip outputs, and careful datamanagement of complex test definitions and collected observations. For these reasons,conducting industrial-scale accelerated wear-out testing is demanding. Typical reliabilitytest ovens such as those offered by Qualitau [154] are expensive, intended for testinglarge numbers of chips simultaneously, and the included temperature control infrastruc-ture and power supplies are large electrical loads. Within the academic research settingavailable these costs are prohibitive, thus an alternative solution is required to evaluatethe implemented sensor designs. Manual testing was eliminated as a possible approachfor three reasons: 1) voltage and temperature stress between measurements would bepoorly controlled and monitored, 1) the time investment required to measure hundredsof outputs repeatedly over a span of months is extremely high, and 3) the long peri-ods of applied voltage during manual measurement may age the sensor circuitry that isintended to remain unstressed. The alternative option, to develop a low-cost system toautonomously carry out accelerated reliability tests, was deemed feasible within time andbudgetary constraints.Initial versions of an automated test system for off-the-shelf device tests were devel-oped in 2020 and 2021, prior to the custom chip designs, but did not provide many of thefeatures required for control and measurement of the implemented sensors and were notsufficiently stable for 1000 hours of continuous operation. Significant design overhaulswere needed and thus a full redesign of the test system was conducted. Recommenda-tions based on evaluation of the redesigned automated test system, developed in 2023 fortesting the TC1 design, alongside new requirements introduced by TC2, led to one ad-ditional design revision that represents the current automated ALT system design. Thesystem consists of two custom printed circuit boards and a software driver for a com-puter universal serial bus (USB) connection. The first circuit board hosts the test chips553.2. Automated Accelerated Life Test Systemin a thermally isolated region and provides input and output control and multiplexingalongside a built-in temperature stress system. The second board executes automatedtests via a programmed microcontroller while providing all the input and output portsrequired by the chip host board as well as a USB port for interfacing with a computer.The computer software driver sends test specifications and receives test data for databaseupload. The complete system, pictured in Fig. 3.7 with the structural block diagramdepicted in Fig. 3.8, enables users to remotely connect to the driver computer, definetest measurements, measurement sequences, control configurations, and test specifica-tions, then transfer them to the control board and provide test start, pause, and stopcommands. This allows for full remote test capability with no user intervention requiredonce a test begins at a material cost below $250 USD (not included the custom chip costsor connected generic computer). The full system schematics, firmware code, and drivercode are all available for open-source use [155].Figure 3.7: Top-down photograph of the two custom boards that compose the automatedALT system hardware. Two TC2 chips are seen on the right. © 2025 IEEE [3].563.2. Automated Accelerated Life Test SystemFigure 3.8: Structural block diagram of the automated test system showing the variousdesign components and interfaces.3.2.1 Test Chip Host BoardThe host board design within the automated test system is used to mount test chips,provide temperature stress control and monitoring, and multiplex chip pins to compactchip outputs into the available input space of the control board design. The uniqueboard layout for TC1 is shown in Fig. 3.9, allowing for two custom chips to be testedsimultaneously. The layout for TC2 is extremely similar in terms of functionality butadjusted according to the specific pin map of the second chip. The biggest drawbacks ofthe design are that custom board designs must be completed for each test chip due to theunique pin-out of each design, and chips must be soldered on and desoldered to switchout the DUTs. Chip sockets would allow for quick swapping of DUTs to avoid repeatedsoldering and desoldering, however sockets were not available at a feasible price for thechip packages used. One benefit of the more permanent chip mounting solution usedis improved thermal coupling. To minimize power consumption and thermal resistancebetween the heating elements and implemented sensors, chip packages were ordered withthermal coupling from the die to package underside, then thermal paste is used to couplethe package to an exposed metal pad of the heating coil element. The thermal pastecoupling would not be achievable in a socket-based design due to the chips being raisedabove the board surface and the high thermal resistance of plastics used in the majorityof existing socket designs on the market.573.2. Automated Accelerated Life Test SystemFigure 3.9: Printed circuit board layout for the TC1 host board. Ground plane copperlayer is hidden for visual clarity.Thermal stress control is achieved through low-frequency pulse width modulation(PWM) control of an internal trace within the board (seen in orange in Fig. 3.9) thatforms a resistive heating coil. A high-power DC supply is provided to the heating coilwith a power transistor used to gate the current, then the control board can adjust thePWM signal to switch the transistor and tune the average current flow through the re-sistive element. Finally, temperature sensor ICs monitor the thermally isolated boardregion to enable fine temperature stress feedback control. Given a 12V supply, maximumtemperatures of over 150°C are achievable, and the proportional-integral-derivative con-troller implementation of the test system firmware can keep temperature deviations fromtarget within an average of 0.34°C and 1000-hour maximum error of 1.75°C for stresstargets of up to 125°C in an open air test environment.The final core function of the host board is to condense the variety of chip output pinsonto a reduced number of wires for measurement via multiplexing. There are both analogand digital signals for which this is required, with 8-to-1 reduction using three digitalselect signals. The digital multiplexers used are selected for high frequency operationto allow for RO signals to propagate without loss of fidelity, while the analog versionsare selected for minimum on-resistance to mitigate any impacts to the signal voltage.583.2. Automated Accelerated Life Test SystemAdditional features of the host board include a high temperature warning light for safetyand reference resistors for biasing on-chip current references. Various cable selections areused to provide high current supply for the heat coil, shielded high frequency signals forRO outputs, and reconfigurable wiring for other signals.3.2.2 Test Control BoardTo control and collect measurements from a host board, the test system control boarddesign functions similar to a full lab bench setup, albeit entirely implemented and au-tomated on a single board. The layout for the current design iteration is shown in Fig.3.10, powered off of a 12V DC supply via a barrel jack connector that is then used toboth directly feed the host board temperature stress circuit and regulated to providelow-noise voltage supplies for the on-board circuitry and four adjustable low-voltage DCstress supplies that apply voltage stress to DUTs on a host board. Control outputsinclude eight low-frequency analog pins, numerous basic digital outputs at configurablevoltage levels, and several higher-frequency PWM and clock output signals. Measurableinputs include eight low-frequency analog pins, four digital frequencies, and a selection oflevel-shifted digital signals. Finally, a micro-B USB 2.1 connection allows for high-speedcommunication with a connected computer that sends test instructions and receives col-lected measurements. The extensive I/O capabilities are all orchestrated by a MicrochipATSAMD21J18A microcontroller operating at 48MHz [156], with a backup flash chipkeeping a full test measurement record to avoid data loss in the event of USB communi-cation failures.Figure 3.10: Printed circuit board layout for the automated ALT system control board.Control board complexity arises from the large number of varied input and outputsignals; individual circuit complexity kept reasonably low. High frequency routing chal-lenges are minimized through close placement of the microcontroller to the USB connector593.2. Automated Accelerated Life Test Systemand prioritized routing of frequency inputs, carefully selected ICs allow for tuneable lowvoltage supply design via digital potentiometers, standard guidelines are used for crystaloscillator design, and isolated analog supply and layout techniques minimize noise forsensitive measurements.3.2.3 Test Control Firmware in the Rust Programming LanguageThe most challenging design element of the automated test system lies in the controlboard firmware, as typical accelerated test specifications demand continuous operationfor at least 1000 hours without interruption or faults. The microcontroller firmwaremust therefore be highly reliable despite complex operation required to simultaneouslyhandle test control, measurement, USB communication, stress condition regulation, andtest data movement. The majority of bare-metal firmware is written using the C pro-gramming language, which is extremely flexible and fast, but also notoriously hard towrite reliable code in since all memory management and pointer assignment must behandled manually. Memory mismanagement issues in C have produced some of the mostcatastrophic global outage and security breach events in history; a recent example beingthe Crowdstrike update in July of 2024 that brought airlines, healthcare, and bankingcompanies, among others, to an operational halt, with estimated direct losses in excess of$5 billion USD [157]. For the test system control firmware, without dedicated firmwareengineering expertise and lack of extensive verification workflows available, an alternativewas desired and identified in the emerging programming language Rust. The languageemphasizes software reliability through a host of compile-time verification methods in-cluding numerous memory error checks that can guarantee elimination of out-of-boundsreads and dangling pointers. Infrastructure and libraries for Rust firmware developmentare still in an unstable development phase, which results in numerous developmentalchallenges and necessary modifications, but the resulting machine code is less susceptibleto human error. Even the best engineering tools cannot prevent design flaws, however,and so verification and testing of the firmware still requires significant effort and iterationto achieve 1000 hour faultless operation.The high-level firmware structure is represented in Fig. 3.11, based on a bare-metalsuper loop architecture. The microcontroller’s real-time counter is used to generate the125ms software ticks necessary to track stress duration, calibrate frequency and slopemeasurements, and ensure stable stress condition control. For the latter, each tick triggersmeasurement of the temperature sensors and voltage stress supplies to maintain rollingaverages that reduce the influence of measurement noise. Every half second the tunedcontrollers for temperature and each voltage supply are updated using these averages to603.2. Automated Accelerated Life Test Systemdetermine and apply control outputs. The biggest consequence of the time-synchronizednature of this control scheme is that each iteration of the super loop must complete in lessthan 125ms for perfect stress control to be maintained. This assumption can potentiallybe violated when measuring very low frequencies and analog slopes that are given up to afull second to finish before aborting, however such measurements are infrequent and onlyoccur once stress has stabilized, thus stress control performance degradation is minimal.Figure 3.11: Firmware architecture for the automated stress test system following a superloop design paradigm. Arrows with hue indicate control flow, black arrows indicate datatransactions.The USB 2.1 specification requires communication responses when messages are sentfrom the computer, mandating an interrupt for USB operation. This has significantfirmware design ramifications, as the super loop execution could be briefly paused at613.2. Automated Accelerated Life Test Systemany time to handle an incoming USB message that may need to modify memory. Toavoid USB interrupts from introducing time-synchronized measurement errors, all mea-surement timing uses peripheral hardware of the microcontroller to offload time-sensitiveoperations in conjunction with polling. The controller requests a measurement from theconfigured hardware units then polls the peripheral until the measurement completes ora watchdog timer triggers, aborting the measurement in favour of a default value. Withthis design, USB interrupts only delay polling while measured values remain unaffected.Unexpected variable modifications are avoided through the use of buffered communica-tion and data channels between the interrupt and the core firmware code. This avoidsany complexities of using mutex variables or code design that can tolerate modification,at the cost of additional memory use. The USB interrupt can only request modificationsto data structures by placing data in a dedicated buffer and raising a flag to tell the superloop execution to process the new data.To allow for arbitrary test specifications to be sent over USB and executed, a dedi-cated test manager provides data structures and memory that can be loaded via USB.Long accelerated test specifications can require thousands of individual stress and mea-surement steps, thus the memory space allocated to storing these test specifications isnearly half of the total dynamic memory space of the microcontroller and specificationsare broken into subcomponents that can be referenced for reuse instead of restated toreduce memory requirements. Maximum size test specifications can specify up to 255unique measurements organized into up to five measurement sequences, with 30 uniquetest steps that can be arranged up to a maximum of 4000 total steps per test with fullflash chip data backup.The final complex design element of the test system firmware is the microcontrollerperipheral hardware configurations used to achieve frequency and analog slope mea-surement. The frequency measurement peripheral setup and control logic starts withthe on-board crystal oscillator and real-time counter peripheral generation of a 4096Hzclock. The frequency input pins are configured as clock inputs, and the selected frequencyto measure is set to be the source clock of a timer-counter peripheral unit of the AT-SAMD21J18A [156]. The counter within this peripheral increments on each rising edgeof the measured signal, and the counter value is buffered to a register on every rising edgeof the 4096Hz clock via the microcontroller’s event system. The software only needs toflush out the old register value, read the current counter value, then keep polling untilthe value changes to determine the increment rate and thus the signal frequency. If, how-ever, the frequency to be measured is lower than the 4096Hz clock, the counter will notincrement between events. To overcome this, if the measured frequency is below 80kHz623.2. Automated Accelerated Life Test Systema second measurement scheme is conducted. The input frequency is supplied to a secondtimer-counter unit configured to wrap to zero every time the counter increments aboveone and output a signal to the event system. This results in an event on every otherrising edge of the signal to measure, which is fed to a third timer-counter unit that countsthe 48MHz central processing unit (CPU) clock and updates a read register every timean event from the second timer-counter occurs. The counter difference between eventscan then be used to back-calculate the signal frequency. The combination of the twomeasurement approaches ensures USB interrupts do not affect measurements and allowsfor frequencies from just over 2Hz all the way to 50MHz to be measured with a highdegree of accuracy and precision. Implementation complexities such as counter wrappingare handled appropriately, with the greatest challenge arising from the unintended use ofchip clock inputs for frequency inputs. Data transfers between the peripherals and mi-crocontroller CPU must be synchronized since they operate on different clock domains,and all clocks are expected to oscillate reliably. Supplying arbitrary input signals asclocks is not intended by the chip designer and can quickly cause full chip stalls, as azero-frequency input prevents data synchronization and halts the entire microcontrollerif the CPU attempts to read a register that never synchronizes. Instead, the CPU mustvigilantly monitor the read synchronization flag for the timer-counter peripheral andmust abort and assume a frequency of zero if synchronization does not complete withina reasonable time frame.The developed analog slope measurement strategy leverages the freerunning mode ofthe microcontroller’s 12-bit ADC peripheral to obtain time-synchronized measurements.The 48MHz CPU clock is divided by 512 to obtain a 93.75kHz clock signal that triggersan ADC measurement of a selected input channel with every rising edge. Averaging themeasured voltage differences between consecutive measurements gives the signal slope.Stopping point determination is the biggest design challenge, as the signal must not bemeasured when saturating near the supply voltage limits of the ADC, and enough mea-surements must be taken to characterize gradual slopes that are difficult to discern fromnoise with only a few measurements. This is achieved by attempting a large number ofconsecutive measurements to account for gradual slopes, then tracking a moving averageto identify saturation conditions and exit early if saturation is observed. These condi-tions can either be based on passing minimum or maximum voltage thresholds or throughwatching for changes in average slope, with both strategies having different slope rangesover which they are accurate and thus both are used depending on the specific range ofslopes of interest. Minimum measurable slopes using the scheme are around 10V/s with amaximum of approximately 10kV/s depending on the saturation detection strategy used.633.3. Test and Evaluation of Implemented Sensor Designs3.2.4 Computer Driver and Data StorageThe final component of the automated accelerated test system is a command-line driverscript that is used to communicate with the control board, written in Python. Design isreasonably simple and leverages open source libraries to implement USB communication,database uploading, automated email notifications, and test logging. Test specificationsare written in markup language and then converted into the byte code formats expectedby the control board. User commands for the control board can be sent using livekeyboard input, and logic for dumping and interpreting the control board’s backup flashmemory is provided in the event of test execution faults.3.3 Test and Evaluation of Implemented Sensor DesignsTo induce degradation in the proposed sensors, the complete automated accelerated testsystem was set up in a lab environment. The 12V control board supply is converted froma standard 120V 60Hz AC wall outlet source that is passed through a backup batterysystem to allow for temporary power outages of up to a few hours to occur withoutdisrupting tests. A Raspberry Pi with an ethernet connection is used as the USB drivercomputer and set up to allow a user remote access to configure, run, and monitor ALTs.3.3.1 Conducted Accelerated Life TestsBoth the TC1 and TC2 custom chips are subjected to the same initial accelerated testprocedure to evaluate the sensors. A standard HTOL test is executed on each, consistingof 1000 hours of stress at 125°C and 1.1x nominal VDD. To observe changes in degradationrates, the chips are brought back to 30°C every 100 hours for intermediate measurements.Additionally, measurements at 125°C and nominal VDD are taken every hour. Althoughthe measured values at 125°C are not comparable to those taken near room temperature,hard failure times can be determined to the nearest hour and the sensors can be monitoredfor any potential recovery effects arising from the reductions in stress occurring every 100hours. Throughout the 1000 hours of stress, temperature and VDD readings are takenevery minute to ensure stress conditions do not drift.Chips are powered on for the first time at the beginning of the tests, at which pointinitial measurements are immediately collected. For TC1 evaluation four chips weretested, while only two TC2 chips were tested as fewer packaged units were available. TheRO-based sensor design, induced offset voltage sensor, and staggered EM sensor werefully evaluated using the TC1 chips, then the leakage current breakdown sensor using643.3. Test and Evaluation of Implemented Sensor Designsthe TC2 design. Burn-in was not conducted prior to testing, thus some initial physicalsettling was observed, mainly in the first 100 hours.After standard HTOL test conditions, an additional test was conducted on the TC1chips for 500 hours at 130°C and 1.2x nominal VDD to observe complementary biasingsensor behaviour under extreme stress conditions (as they experience reduced effectivevoltage stress). Per-minute stress condition readings, hourly measurements at stresstemperature, and 30°C measurements every 100 hours were still collected for monitoringpurposes. Note that an analog power domain open-circuit failure occurred in one TC1chip after 450 hours of extreme stress, so the final set of 30°C measurements were notobtained for five offset voltage sensor variant instances.3.3.2 Oscillator-Based Sensor ValidationFor the RO-based sensors, basic implementation correctness is verified through compari-son of initial measured frequencies to those predicted by layout-aware foundry simulationmodels, shown in Fig. 3.12. The maximum measured values that were observed afterearly stress led to settling (as the chips were not subjected to burn-in prior to testing) arealso included in the comparison, illustrating that all sensors were within expected free-running frequency ranges both before and after stress-induced settling. Initial frequenciesmeeting expectations merely demonstrates that the physical circuits are fabricated as in-tended without deficiencies, however; the usefulness of the sensor designs for detaileddegradation monitoring can only be evaluated after wear-out has occurred.Effectiveness of the designed sensor architecture in isolating degradation under differ-ent stress regimes is evidenced through comparison of degradation between the RO vari-ants (i.e., demonstrating that each sensor variant tracks different wear-out behaviours).Relative comparisons are used in absence of ground truth “correct” degradation mag-nitudes for the specialized sensor circuits undergoing degradation under specific stressconfigurations. Frequency degradation is taken using the maximum measured frequen-cies as reference in order to isolate degradation from early settling effects that causedfrequency increases. The degradation-induced relative frequency shifts observed after thefull 1500 hours are shown in Fig. 3.13, with degradation of several standard referenceROs included to provide a point of reference.653.3. Test and Evaluation of Implemented Sensor Designs(a) Initial frequency measurements comparison to simulation.(b) Maximum observed measurements comparison to simulation.Figure 3.12: Initial and post-settling free-running frequencies of implemented sensorinstances compared to simulated ranges across worst-case process corners indicated bythe brown dotted intervals. © 2024 IEEE [4].The degradation distributions are qualitatively distinct with some variance betweensensors of the same variant. The low relative degradation of NMOS versus PMOS BTI,standard RO degradation lying between NMOS and PMOS, and higher degradation whenHCI occurs on top of BTI are in agreement with a majority of the existing literature663.3. Test and Evaluation of Implemented Sensor DesignsFigure 3.13: Observed frequency degradation for all sensor instances of each variantalongside violin plots with quartiles to approximate the observed distribution, revisedfrom [4].[37, 39]. The different degradation behaviours monitored by each stress regime variant isdemonstrated quantitatively through statistical hypothesis tests. There are no groundsto assume equal or normally-distributed degradation variance given prior work that ob-serves different NBTI versus PBTI variability and distribution skew due to degradationprogressing in one direction from the initial value [158]. Standard analysis of variance(ANOVA) and pair-wise t-test techniques are thus inappropriate. Welch’s ANOVA ap-proach is appropriate for heteroscedastic variability but does assume normal distributions[159], while the Kruskal-Wallis non-parametric approach makes neither assumption but isinvariant to the magnitude of degradation [160]. Both tests are used to evidence effectivesensor functionality given the magnitude-invariant downside of Kruskal-Wallis and giventhat Welch ANOVA is reasonably robust to skewed distributions [161].Hypothesis tests are applied to the standard and complementary bias sensors sepa-rately as their test conditions are not equivalent (due to the reduced effective stress volt-age applied to the complementary biasing sensors). Both statistics yield extremely lowprobabilities (<1e-10) for both groups that the observed measurements all arise from thesame underlying global distribution, thus rejecting a null hypothesis and justifying post-hoc pair-wise comparisons via Games-Howell [162] and Holm-corrected Dunn [163, 164]tests; these are appropriate options following Welch ANOVA and Kruskal-Wallis global673.3. Test and Evaluation of Implemented Sensor Designshypothesis tests respectively. For the standard biasing RO variants, all pair-wise p-valuesfrom both Games-Howell and Dunn tests are less than 0.05, indicating >95% certaintythat each of the four variants are tracking different degradation behaviours. For thecomplementary variants, all p-values are less than 0.05 except when comparing the com-plementary BTI variants, which see p-values of 1.00 and 0.98 from the Games-Howell andDunn tests respectively. This indication that the complementary biasing BTI variantsare degrading identically is an interesting result. The standard BTI variants degradeat drastically different rates despite only differing from the complementary variants interms of the bias transistor type. Though no confident explanation can be given with-out direct probing access or further design exploration, a plausible hypothesis is thatcapacitive shifts due to aging (such as previously reported Cgd degradation [125]) in biastransistors have distinct impacts on overall RO frequency degradation. Such behaviourwould simultaneously explain the reduced degradation of the complementary PMOS BTIsensor variant in comparison to the standard one, and the increased degradation of thecomplementary NMOS BTI sensor variant in comparison to the standard one. Almostno existing literature is available to support or dispute this hypothesis (excepting Sezgin-Ugranlı and O¨zc¸elep [125]), however, and foundry-provided models of NBTI and PBTImore closely match the NBTI:PBTI ratio observed in the standard sensor variants un-der HTOL conditions (a 7.9% relative error). Future work is needed to investigate theobserved complementary BTI sensor variant behaviour as there are numerous possibleroot causes given the high complexity of wear-out behaviours and chip implementations.Effective sensor monitoring of different degradation mechanisms is clearly evidenced,however, through agreement with initial frequency simulation, the conducted hypothesistests, and qualitative observations agreeing with widely-reported degradation trends inthe literature.Finally, the contributed interwoven layout technique for RO sensor implementationalso requires evaluation. The interwoven oscillator pair data in Fig. 3.14 is selectedbased on minimal degradation during the initial 1000 hours of stress and the uniquesudden settling event that was fully compensated for by the interwoven layout. Effectivematching is demonstrated in the illustrated pair; until discrepancies due to degradationwere observed matching was maintained to within 1MHz even after absolute frequencyjumped noticeably. This pair was not unique, initial measurements before degradationfound that only two outlier pairs (out of 64 total) had a measured frequency differenceof greater than 1.05MHz, and the mean difference across all remaining 62 pairs was0.35MHz. Additionally, the interwoven layout strategy enabled improved fault diagnosisthrough the ability to distinguish whether a sudden failure or recovery event was isolated683.3. Test and Evaluation of Implemented Sensor Designsto a single oscillator versus a larger-scale power delivery or body bias effect that jointlyimpacted an oscillator pair (such as the event seen in Fig. 3.14).Figure 3.14: Frequency difference between two interwoven RO sensors throughout theevaluation test demonstrating exceptional matching. Absolute frequency is shown in theupper inset. © 2024 IEEE [4].Figure 3.15: Mean degradation curves across 20 duplicates for each of the four inducedoffset sensor stress regimes. © 2024 IEEE [2].693.3. Test and Evaluation of Implemented Sensor Designs3.3.3 Induced Offset Voltage Sensor ValidationAs described in Sec. 2.3, the NMOS and PMOS variants of the induced offset volt-age sensor have voltage outputs that decrease and increase respectively as degradationprogresses. To allow for direct comparison, all experimental data series are translatedvertically to give an initial reading of zero, then all PMOS data is inverted to producedecreasing values over time. Fig. 3.15 shows the mean degradation curves for each ofthe four stress regime variants across the 1500 hours of stress, while Fig. 3.16 plots thesensor output shift for individual sensor instances at the 1000 and 1500 hour marks. Notethat some physical settling was observed as burn-in was not conducted prior to testing,however this settling was far less pronounced than in the ROs and so initial readingswere representative of maximum readings for the majority of sensors.Figure 3.16: Offset sensor variants output voltage shift after 1000 and 1500 hours ofstress. High degradation variability is observed between instances, especially followingthe severe ET stress phase. © 2024 IEEE [2].Similar to the RO-based sensor design, sensor effectiveness is evaluated through qual-itative assessment and statistical hypothesis tests. An identical statistical approach isapplied to the full duration test degradation data of the four sensor variants, yieldingp-values of <1e-3 for both the Welch ANOVA and Kruskal-Wallis global hypothesis tests.The null hypothesis, that the sensor variants are all tracking identical degradation effects,703.3. Test and Evaluation of Implemented Sensor Designscan therefore be rejected with high confidence and pair-wise Games-Howell and Dunntests conducted. These post-hoc pair-wise tests both result in identical conclusions, withp-values <0.05 for all comparisons with the n-HCI sensor variant, but near 1.0 p-valuesbetween NBTI, PBTI, and p-HCI. This result could either indicate that specific sensorvariants are not tracking different degradation effects, or that degradation under each ofthe three stress regimes is comparable.Four arguments are presented in support of the latter conclusion. First, the pro-nounced difference in degradation between the NMOS BTI and HCI variants resultsfrom applied stress conditions only, as the sensor topologies themselves are identical.The PMOS BTI and HCI topologies are also identical and differ from the NMOS vari-ants only in their complementary transistor design, thus it is reasonable to conclude thatsince different applied stress variants monitor different wear-out behaviours in NMOS,the same should be true for the PMOS degradation sensors and the observed similaritywould be due to similar degradation under the two stress regimes. Second, the observedmean degradation ratio between the NBTI and PBTI variants after 1000 hours of stressaligns closely with provided foundry models, the relative error between the ratio estimatesis 4.2%. Third, the temporal degradation curves in Fig. 3.15 show qualitatively uniquebehaviour for each monitored stress regime, and the similar degradation at 1500 hoursmay be a result of the extreme stress conditions. Finally, the high observed variabil-ity of sensor degradation makes distinguishing comparatively small differences in meandegradation under different stress regimes challenging without very large sample sizes.This high variance between sensor instances (particularly following the severe ET stressphase) is significant enough to warrant detailed discussion.The high variability of shifts in sensor output voltages is the greatest challenge forfuture work to address prior to industrial adoption of the designed induced offset volt-age sensor. Though the initial implementation demonstrates a clear capability to trackdistinct wear-out behaviours in NMOS arising from different transistor stress regimes,and observed qualitative trends generally agree with existing research on scaled pro-cess degradation [37, 84], full validation through observing unique behaviour between allstress regimes is desired. Reduced sensor variability is a key requirement towards thisgoal alongside testing across a variety of stress conditions. Three potential approachesare identified that could reduce variability in subsequent sensor implementations.1. Supporting circuitry in this first implementation used small transistor sizing, andaccepted component-level simulations across process corners likely underestimatedsystem-level variability as they didn’t consider compounding effects. Larger sizingin future implementations could reduce this significantly [158].713.3. Test and Evaluation of Implemented Sensor Designs2. Oversized stressed transistors in the sensor are also more likely to regress to meandegradation levels and thus reduce overall variability, though this comes with atrade-off as multiple sensors with smaller stressed transistors provide a more com-plete characterization of degradation in typical core devices.3. At the cost of increased routing effort, stressed transistors could be distributedacross a die to reduce cross-die variability between between sensors. Long intercon-nect lengths are feasible given DC sensor operation, though resistivity may becomea challenge.Note that in eventual industrial applications some variability may be desirable, however,as data on cross-die PVT variations can be helpful for future SLM applications such asload balancing between processing cores.3.3.4 Gate Leakage Sensor ValidationThe SILC ramp sensor is briefly validated via successful observation of SILC-induceddegradation given that no other wear-out mechanisms result in a gate leakage currentincrease. The changes in voltage ramp rate of the individual sensor outputs over the 1000hour test duration are plotted in Fig. 3.17 for all eight implemented sensor variants. TheFigure 3.17: Relative increase in voltage ramp rate of individual SILC ramp sensors,grouped by variant and with associated summary statistics. © 2025 IEEE [3].changes in ramp rate over the course of the test are minor for most variants (and subjectto high variability even more pronounced than in the the induced offset sensor archi-tecture), which for small transistors can be expected given the extreme rarity of defectformation within the gate dielectric for modern processors. For the oversized stressedPMOS transistors with both regular (RVT in Fig. 3.17) and increased threshold voltage723.3. Test and Evaluation of Implemented Sensor Designs(HVT in Fig. 3.17), however, significant increases in all individual sensors are consistentwith SILC-induced gate leakage increases. Additionally, an apparent TDDB soft break-down event is observed in one sensor instance. This is explained by the much higherdefect formation probability in these sensors due to the larger stressed gate dielectric,hence why large capacitors are often used for in-lab TDDB characterization [100].3.3.5 Staggered EM Sensor ValidationThe simple operation of the staggered EM sensor makes validation comparatively simpleas well. The highest current line in the implemented version failed almost immediatelyin the tested chips, by design, providing immediate evidence of correct sensor operationduring initial functionality testing of the TC1 chip (separate chips from the four TC1subjected to stress). The hourly high-temperature sensor readings in each chip for one ofthe stressed lines within the sensor are plotted in Fig. 3.18, alongside the predicted MTTFof the foundry-provided model for the nominal line current and HTOL test conditions.Figure 3.18: Failure times across chips for one of the interconnect lines within the stag-gered EM sensor. Predicted MTTF from foundry modelling is included for comparison.As the EM sensor readings are not impacted by high temperature or voltage, hourlymeasurements throughout the test duration enabled precise identification of when theinterconnect line failed in each chip. All four lines significantly outlast the mean predictedlifespan and only failed following the increase in stress severity after 1000 hours. This ismost likely due to conservatism of the foundry model, lower than expected stress currentdue to neglected resistive losses associated with the large currents, PVT variations, orsome combination of the three. Future work to carefully tune stress currents in eachof the eight lines based on intended time markers is required prior to any industrialimplementation, as the test implementation currents spanned a much wider range thannecessary and planned line failure times may be application-dependent.733.4. Comments on Long-Term Reliability in Scaled FinFET Process Nodes3.4 Comments on Long-Term Reliability in ScaledFinFET Process NodesThe test measurements collected during evaluation of the contributed wear-out monitor-ing sensors also provide some insights into LTR in scaled semiconductor processes. Theobserved behaviours clearly evidence some of the upcoming challenges that motivate theresearch work of this dissertation and so additional discussion of these trends is provided.The different degradation resulting from different mechanisms under different stressis crucial to understanding LTR under diverse in-field conditions and circuit topologies.The full-test degradation of standard ROs in Fig. 3.13 does not follow any of the indi-vidual per-mechanism sensors directly and instead degrades according to some functionalcombination of their individual contributions. This may not be as simple as a weightedsum (given the potential for interactions between BTI and HCI [52]), but the collectedtest data indicates that understanding overall circuit degradation as a result of individ-ual mechanism contributions is incredibly valuable when attempting to predict how andthe rate at which individual circuits will degrade under different conditions. Table 3.1summarizes some key relative magnitudes of mean degradation between BTI and HCImechanisms observed from the RO-based and induced offset sensors after 1000 hours ofHTOL stress and then after the additional 500 hours under extreme stress (designatedETOL in Table 3.1).Table 3.1: Degradation magnitude ratios across BTI and HCI mechanisms observed withdifferent implemented sensors, revised and combined from [4] and [2].Relative Ratio NBTI:PBTI p-HCI:n-HCI p-HCI:NBTI n-HCI:PBTIPost test phase HTOL ETOL HTOL ETOL HTOL ETOL HTOL ETOLStandard RO 4.867 10.075 0.098 1.976 0.370 3.912 1.833 19.94Complementary RO 1.005 1.007 1.021 2.161 0.110 7.345 0.109 3.422Induced Offset 5.126 1.049 ∞ 4.544 0.664 1.020 0.000 0.236From this table, one key feature that emerges is the low rates of HCI degradationcompared to BTI in both NMOS and PMOS transistors under HTOL conditions. Afterthe extreme ETOL phase, however, their significance increases dramatically. These re-sults suggest that although HCI is typically found to be of less significance under HTOLconditions [37, 38], this is not necessarily true under different situations and thus HCIversus BTI contributions need to be considered individually to predict overall degrada-tion under varying conditions. Similarly, although NBTI is approximately 5x more severethan PBTI under standard test conditions (in agreement with foundry models as noted inprevious sections and excepting the unexplained similarity in the complementary ROs),the situation is complicated by changes in relative degradation under extreme conditions743.4. Comments on Long-Term Reliability in Scaled FinFET Process Nodes(though these results are further complicated by high variability). These results supportexisting research work and predicted trends that identify individual competing wear-outmechanism analysis as a key concern for ensuring high reliability of semiconductors underdifferent operating conditions [83–86, 165].A final comment on differences in degradation between mechanisms arises from thedifference in time curvature between NBTI and PBTI seen under extreme test conditionsin Fig. 3.15, where it appears that PBTI degradation progresses more gradually thanfor NBTI. A rudimentary analysis through mean squared error fitting of mechanism-agnostic first-order models of form Vout = A + Be−τt to the mean BTI degradationcurves reveals a time constant for NBTI that is 1.86 times greater than PBTI underHTOL conditions and 2.87 greater under ETOL. Future work would be needed to reachconfident conclusions, but this type of observed behaviour suggests that atomic defectformation rates (and subsequent saturation behaviours) may not be identical across wear-out mechanisms. This would mean that consideration is not only needed for individualmechanism degradation magnitudes, but also time-dependent rates that could lead todifferent root cause mechanisms for failures at different time periods under identicalstress.Aside from mean degradation trends, statistical distributions in LTR are of equalimportance. The most obvious trend observed during sensor evaluation was the highvariability concerns surrounding modern semiconductors, supporting prior research find-ings [158, 166] and predicted trends discussed in Sec. 1.5. Degradation exhibited partic-ularly high stochasticity in the induced offset and SILC ramp sensor designs, consistentwith increasing variability as transistors scale, and reduced variability in the larger SILCsensor variants and large ROs supports research suggesting that overall reliability can beimproved through variance reduction via increased transistor sizing [167, 168].The collected data also evidences the existence of significant group-level variabilityand correlations between different stochastic parameters. Fig. 3.19 plots chip-aggregatedfrequency throughout the stress duration for one of the RO-based sensor variants, whileFig. 3.20 plots SILC ramp sensor initial measurements against maximum observed mea-surements for each sensor.753.4. Comments on Long-Term Reliability in Scaled FinFET Process NodesFigure 3.19: Significant deviations in sensor measurements observed between differentchips. © 2024 IEEE [4].Figure 3.20: Correlated degradation with initial measured value observed in the SILCramp sensor. © 2025 IEEE [3].The first plot demonstrates how group-level variability, in this case chip-to-chip, cansignificantly exceed device-to-device variability. The presence of multilevel sources ofstochasticity can cause LTR to vary not just between individual transistors, but alsobetween lots and/or chips, and will be considered in great detail later in Part II. Thesecond plot evidences how individual devices can exhibit correlations between stochas-763.5. Part I Conclusions and Future Worktic parameters, potentially allowing for reliability of a specific part to be correlated todevice parameters that can be measured during production line testing. This observedcorrelation between initial and degraded values, though not addressed within the scopeof this dissertation, supports research efforts to leverage these potential correlations [169]and motivates the need for physical studies into the level of independence of stochasticwear-out effects.3.5 Part I Conclusions and Future WorkMotivated by identified gaps in the semiconductor reliability literature, enhanced andnovel sensor designs for on-chip monitoring of BTI and HCI in isolation (for both PMOSand NMOS transistors) were introduced, implemented, and evaluated, alongside supple-mentary novel sensor designs for monitoring the two other key semiconductor wear-outmechanisms of TDDB and EM. The enhanced RO-based design variants introduce new ca-pabilities for DC HCI stress monitoring that successfully isolate distinct HCI behaviours,alongside an interwoven layout technique that enables extremely tight PVT couplingof oscillation frequencies between multiple ROs. The novel induced offset sensor is thefirst available design to isolate HCI using DC circuit techniques and prevent degradationof ancillary transistors from impacting measurements, specifically targeting efficacy foranalog applications. Supplementary contributed TDDB and EM sensor designs allow forall four key semiconductor wear-out mechanisms to be isolated via on-chip sensors thatcan be continuously monitored during in-field operation. When brought to application,combined use of per-mechanism sensors can provide more informative response variablesand ongoing data to better model and learn complex LTR behaviours in modern semi-conductor fabrication processes. This is essential to ensure that mechanisms that maybe insignificant under normative field use conditions do not result in unexpected failuresunder the varied stress environments of high reliability applications, such as automotivevehicles.Following theoretic and simulated design, all sensor designs were implemented in a12nm FinFET process. Most contemporary sensor designs surveyed are restricted tosimulation-based studies or implementations in much larger process nodes, thus the real-world experimental results obtained are significant contributions towards demonstratingthe feasibility of on-chip wear-out sensors for scaled semiconductor processes. CollectedALT data quantitatively indicates that the sensor designs are successfully tracking dif-ferent mechanisms of interest and enables commentary on wear-out reliability trends inscaled CMOS, though high variability is certainly a shortcoming of the induced offset773.5. Part I Conclusions and Future Worksensor and the SILC ramp sensor. The automated test system developed as part of thesensor evaluation effort contributes a low-cost option for small-scale accelerated lifes-pan testing, demonstrating effective use of internal heating traces to control temperaturestress and of the Rust programming language to develop firmware for reliable operation.Several key directions for future work are identified in pursuit of effective on-chipmonitoring of individual wear-out mechanisms for industrial designs. First and foremostare iterative implementations of the sensor designs that optimize power, performance,and area (PPA), target more recent process nodes, and reduce variability through largertransistor sizing and more sophisticated supporting circuitry than the simple topologiesused within the constraints of the initial implementation. Analysis of the optimal de-gree of variability to maintain in sensor designs is an interesting related area of work thatcould be pursued, as eventual SLM strategies may require multiple sensors across chips toeffectively characterize the full distribution of degradation due to each mechanism. Howto minimize sensor quantities needed for confident wear-out characterization and coordi-nate measurements of these sensors for telemetry applications is only now beginning to beexplored within SLM. The second key future work direction is in application of individ-ual mechanism sensor data to solutions for effective LTR qualification, characterization,and in-field monitoring. Parts II and III of this research work partially address this di-rection by looking at overall enhanced reliability prediction and qualification strategiesthat incorporate per-mechanism data, but there are numerous opportunities for on-chipwear-out sensors to enable predictive maintenance and production-line test approachesthat are not examined within the present scope of work. Though the presented resultsdemonstrate the feasibility of the four contributed sensor designs for practical use, apath to industrial adoption is possible only through a combination of successive imple-mentations to refine the sensor designs and development of new strategies that leveragethe higher fidelity wear-out data to realize benefits in chip binning, SLM, and reliabilityqualification applications.78Part IIProbabilistic Modelling andComputational Bayesian Inferencefor Semiconductor LifespanPrediction79Chapter 4Probabilistic Physics-of-FailureModellingIn Sec. 1.6 the industrial standard approach to lifespan prediction via HTOL testing wasdescribed. Although JEDEC provides some models and guidelines for per-mechanisminvestigation of reliability in JEP-122 [49], the scope of industrial guidance is limitedand methods continue to rely on assumptions that are often unsound. To fully analyzedata obtained from the contributed on-chip wear-out sensors, alternative approaches areneeded that consider simultaneous effects of multiple degradation and failure mechanisms,focus on lifespan prediction rather than the binary acceptance criteria of demonstrationtests, and evaluate the confidence of extrapolations to field use conditions. Revealedthrough extensive survey, there are numerous research efforts that work towards effectiveLTR prediction for semiconductors following various statistical frameworks as a basisfor their enhancements. Following literature review, a probabilistic modelling approachwithin a Bayesian statistical framework was identified as the most promising basis for aprediction approach that could address both increasing semiconductor variability trendsdiscussed in Sec. 1.5 and uncertainty-aware lifespan estimates for high-reliability applica-tions identified in Sec. 1.3. As no existing work fully addressed both of these challenges,a probabilistic modelling approach for use within a Bayesian statistical framework is con-tributed to enable robust LTR predictions. The novel ability of the probabilistic modelarchitecture to explicitly incorporate and separate out epistemic and aleatoric uncer-tainty helps engineers to avoid making overconfident product lifespan predictions, whichis crucial to ensure safety in growing high reliability markets. Additionally, the novelmultilevel variability modelling capabilities of the architecture can help ensure that lifes-pan predictions respect the significant variability between chips and fabrication lots thatis expected to worsen with continuing semiconductor process scaling. This chapter firstdiscusses existing literature in detail before describing the novel probabilistic modellingarchitecture and associated statistical tools used to specify and analyze PoF wear-outmodels cast to this probabilistic formulation.804.1. Existing Semiconductor Long-Term Reliability Data Analysis Approaches4.1 Existing Semiconductor Long-Term Reliability DataAnalysis ApproachesBroadly speaking, surveyed research on improved lifespan prediction for semiconductorLTR can be categorized based on which statistical foundation it builds upon; frequentist,black box, or Bayesian. Prior work in each of these categories is summarized and critiquedto justify the resulting Bayesian approach of the pursued research.4.1.1 Enhanced Frequentist Statistical MethodsContributions to frequentist analysis of semiconductor reliability are numerous and oftensmall enhancements are introduced within larger works. Choice works, illustrative ofthe overall research directions, are presented to concisely capture how frequentist statis-tics are grappling with challenges of increasing variability and complex stress conditiondependencies of wear-out mechanisms within semiconductors.Wu et al. observe the challenges of fitting reliability data in the presence of highvariability in modern fabrication processes, and propose the use of multiple clusteringdistributions, a modification of the Weibull distribution, to develop independent predic-tions for different process variability corners [170]. Addressing variability in digital logictiming, Jafari et al. introduce a failure probability metric that can produce reliabilitypredictions that account for device-level wear-out variability [171]. This avoids the use ofmultiple distributions to describe failures of variable devices, but does require large datasets to effectively characterize cumulative distribution functions (CDFs) of failure times.Works by Wyrwas et al. [83], Bender et al. [172, 173], Wu et al. [174], and Wanet al. [175] all attempt to enhance prediction methods to operate under the presenceof multiple mechanisms that may compete or accumulate. Different mechanisms are fitto individual distributions, then their effects are combined through novel techniques ineach work to develop product-level wear-out predictions that can account for changingmechanism contributions under varied field-use operating conditions.Tsai et al. address the fixed acceleration factor assumption of the standardizedJEDEC approach by instead fitting lifespan data from multiple ALTs under differentstress conditions to extrapolation curves [176].There is other work on novel frequentist reliability engineering techniques worth men-tioning despite not originating from semiconductor applications. Zhang and Geiger intro-duce a frequentist approach to incorporating historical reliability data into the predictionprocess for automotive components that approximates how this data is used within aBayesian context [177]. They state that this approximated technique is adopted instead814.1. Existing Semiconductor Long-Term Reliability Data Analysis Approachesof the Bayesian approach it emulates based on resistance to adoption of Bayesian tech-niques within their industrial management and engineering teams. From a systems-levelperspective, Wang et al. consider predicting failures of systems with multiple componentsfollowing different Weibull failure distributions [178]. This parallels the mentioned worksaddressing multiple mechanisms and variability. In each, multiple failure distributionsare composed in some manner to predict overall wear-out reliability, highlighting howsingle distribution fits are insufficient for a wide range of reliability analyses.In general, the broad limitation of surveyed works built on an enhanced frequentiststatistical foundation is that although many overcome specific shortcomings of existingmethods, they do so using workarounds that are either rough approximations of moreintuitive techniques or that introduce new implicit assumptions to simplify challenges ofvariability, multiple mechanisms, or system-level interactions [179].4.1.2 Machine Learning Limitations for Long-Term ReliabilityPredictionWith black box machine learning methods having such widespread adoption and mo-mentum in both industrial and academic contexts, it would be natural to attempt toapply these tools to semiconductor lifespan prediction. In work by Alrahis et al., digitallogic designs are encoded as structured graphs, then graph neural networks are used topredict increasing digital logic delays due to wear-out [180]. The approach allows forincreasing delays prediction generalized across different digital logic timing paths, butrequires training data sets of measured path delay increases in similar digital circuits andso does not effectively generalize to different fabrication processes. Yang and Feng usestandard neural networks to predict S-parameter degradation in high-frequency oscilla-tors based on accelerated measure-stress-measure test data, thus attempting to generalizepredictions across stress conditions [181]. A very similar problem is tackled by Zhao andKerkhoff for product-level degradation, however they instead using genetic algorithms[182]. These two approaches were only evaluated using a single data set in each, leav-ing uncertainty as to how well the techniques generalize across fabrication processes orproduct designs, especially in cases where only limited test data is available for training.Finally, Genssler et al. use high-dimensional vector encodings of foundry reliability dataas a means to protect foundry models from disclosure while generalizing aging simulationmodels across customer workloads for use in product designs [183]. This requires that anaccurate compact physics model has already been developed by the foundry, and theirnetwork merely approximates the physical model across field-use conditions to obfuscateintellectual property. Across these identified existing works leveraging machine learning824.1. Existing Semiconductor Long-Term Reliability Data Analysis Approaches(ML) for semiconductor reliability, significant pre-existing wear-out data for training isrequired, highlighting the limitations of black box approaches in terms of applicabilityto predicting wear-out reliability in novel fabrication processes or designs in which littlepre-existing data is available.Theoretical evaluation of black box statistical methods revealed a significant challengewith standard deep learning approaches, in particular with the training aspect. Usinga standard setup, with accelerated wear-out test results constituting the network input,the trained model needs to successfully predict product lifespan at field-use conditions.This requires the model to be trained on representative input-output pairs where a con-sistent relationship (even if complex) exists between the test results and lifespan. Thefirst aforementioned challenge is that typically very little data exists for in-field failures.Without telemetry systems or programs for collecting and diagnosing failed parts fromcustomers, the field-use lifespan is not a known quantity. Based on discussions with in-dustry engineers this is the case for most historical semiconductor products, and thoughsignificant research into SLM techniques is beginning to alleviate this limitation [103],data access is restrictive where it may exist. Even if relevant data sets were available,however, the statistical relationships present in the data are not guaranteed to generalizewell given that reliability can not be assumed to be identical across semiconductor fab-rication processes or even different products in a mature process. Physical phenomenachange with process node, process drift can occur over time in a single node [184], andthe individual circuits and timing paths within a design are not identically susceptibleto degradation and failure mechanisms [182]. Experts can predict and collect early datato intuit how reliability may change for a new product or process, but incorporatingthese expert predictions into a machine-learning model is challenging [185]. There arepossible alternative mappings of the prediction problem to machine learning frameworksthat could reduce the uncertainty in the applicability of a trained model to a new prod-uct, for instance treating expert opinions on reliability shifts as additional inputs to thenetwork. As possible remappings were evaluated, however, the most promising formula-tions converged towards the alternative Bayesian inference approach that was also beingconsidered.4.1.3 Introduction to Bayesian Reliability AnalysisAlthough a shift towards Bayesian analysis in semiconductor reliability engineering hasbeen predicted by some individuals in the literature [14], prior art leveraging these sta-tistical techniques is sparse. Two works were identified that use Bayesian inference forsemiconductor reliability analysis, though only the first looks at lifespan prediction specif-834.1. Existing Semiconductor Long-Term Reliability Data Analysis Approachesically. Chien et al. take an analytical Bayesian inference approach to analysis of failuredata following either log-normal or Weibull distributions, providing reliability risk assess-ment during wafer-level production tests [169]. The second, by Date and Tanaka, appliescomputational Bayesian inference (CBI) to fabrication process control to help determineacceptable limits for control parameters [186]. The authors use a linear bathtub modelto represent product-level failure rates as a function of these parameters, with the no U-turn sampler (NUTS) algorithm used for Markov chain Monte Carlo (MCMC) posteriorinference [187].After the exploratory research phase to identify and predict the effectiveness of variousexisting approaches was concluded, Bayesian inference via probabilistic programmingapproach was deemed to be the best engineering solution as it provided three desideratanot supported by other frameworks:1. Per-parameter quantification of predictive uncertainty to facilitate predictive con-fidence analysis of models, test designs, and LTR requirements [188].2. Physically representative treatment of field-use extrapolation of wear-out and fail-ure data through compatibility with complex PoF models [189].3. Explicit incorporation of historical and expert knowledge into the reliability pre-diction process through prior beliefs [190, 191].From a methodological perspective, very few drawbacks to the Bayesian approach areidentified as it maps to the specific problem of accelerated lifespan testing exceptionallywell. From a technical perspective, however, there are a great deal of challenges relatedto computational complexity of probabilistic programming techniques (comparable toblack box ML approaches) alongside technical knowledge barriers that make industrialimplementation daunting. These technical challenges have historically limited Bayesiananalysis to simplistic problems with closed-form analytic solutions [169], but significantadvancements in hardware for performant parallel computation in the past decade, com-bined with raw semiconductor PPA improvements, has dramatically increased the fea-sibility of the computationally demanding numerical estimation techniques required forBayesian analysis of complex systems. A textbook by Hamada et al. provides an exten-sive overview of many of the concepts that will be leveraged throughout the remainder ofthis dissertation, and is an effective introduction to CBI techniques [192]. Of particularrelevance are Markov chain Monte Carlo (MCMC) algorithms, which have been leveragedto great success in the emerging field of probabilistic programming [193–195] and vastlyincrease the breadth of applications for which Bayesian statistical analysis is now viable.844.2. Structured Probabilistic ModelsThe growing array of methods for fast and accurate CBI not only enables broad applica-bility but has also led to new Bayesian statistical approaches that both borrow from andenable advancements in the broader field of machine learning [196]. Use of probabilisticprogramming methods in a Bayesian context is particularly valuable when attempting tolearn about fundamentally unobservable parameters for which little data is available, asituation that precisely describes LTR prediction for integrated semiconductor devices.Surveyed prior works evidence success within their specific applications in enablinghistorical data use within analyses and developing stochastic predictions, though are re-strictive in scope. The modelling architecture and software frameworks for semiconductorwear-out analysis contributed by this research work differ from these prior approaches inmany regards, allowing for user-specified probabilistic models of far greater complexity,separable modelling of different sources of uncertainty, simultaneous analysis of individualand group-level variability, and improved quantification of uncertainty based on informa-tion entropy. The research methods also remain fully agnostic as to which PoF models,circuits, and tests a practitioner may want to use and so enables generalized analysis fora broad range of situations in comparison to surveyed existing works.4.2 Structured Probabilistic ModelsA probabilistic model for any physical wear-out or failure mechanism differs from a clas-sical model only in terms of the introduction of stochasticity through random variables.This seemingly simple change, however, immediately opens up opportunities for Bayesianstatistical analyses and improved capabilities for investigating variability in semiconduc-tor wear-out and device parameters. Formally, a structured probabilistic model (SPM) isa declarative representation of some system containing significant uncertainty, encodedby a set of random variables, optionally some fixed parameters, and then the set of re-lationships between them [197]. For the engineering application at hand it is crucialto differentiate the two distinct sources of statistical uncertainty within an SPM: thephysical noise and stochastic processes that lead to variability in fabrication, measure-ment, and aging, referred to as aleatoric uncertainty, then the lack of perfect engineeringknowledge as to the physical behaviour of a system, designated epistemic uncertainty.Random variables within an SPM will later be categorized based on which componentthey encode based on the following schema:1. Any random variable that can be directly observed does not contain uncertaintyonce measured, since the value is known. These are referred to as observed variables.854.3. Hierarchical Probabilistic Physics-of-Failure Models2. Random variables that are not directly measured but introduce known quantitiesof aleatoric uncertainty will be called noise variables, encoding known sources ofvariability. Often these are stress variables, such as the variance in temperature orsupply voltage between transistor junctions, or stochastic device parameters withknown distributions.3. Random variables that contain a mix of both aleatoric and epistemic uncertaintyare latent variables.4. Hyper-latent variables contain only epistemic uncertainty, i.e., if the physics of thesystem were perfectly understood they would become deterministic parameters.Communication of SPMs is often done graphically to explicitly show the relationships be-tween random variables. In the graphical representations that will be used going forward,simple circles represent random variables, with the filled shade indicating the categoryof the variable from the above listing. Circles with an internal ring are dependent vari-ables that are defined in terms of deterministic combinations of random variables. Suchvariables are still stochastic, but only as a result of their inputs. Squares representdeterministic independent parameters, and arrows indicate dependency relationships be-tween the random variables and parameters that compose an SPM. Finally, dotted linebounded regions, called plates, are used to indicate multiplicity across some dimension,such as when five identical duplicate sensors are fabricated and measured. An exampleof a graphical SPM representation is shown in Fig. 4.1 that illustrates all the introducedelements via the experimental example of a model that could be used to infer the valueof the Boltzmann constant from Johnson-Nyquist noise in a set of resistors [198]. Amore detailed introduction to graphical models can be found in Koller and Friedman’s“Probabilistic Graphical Models: Principles and Techniques” [197].4.3 Hierarchical Probabilistic Physics-of-Failure ModelsThe simplest SPM to conceive of for semiconductor wear-out modelling is to directly mapexisting models into the probabilistic framework, and in the majority of existing Bayesianreliability research this is the taken approach, including in the identified applications tosemiconductor wear-out [169, 186]. Black’s model for EM failures, introduced previouslyin Eq. 1.4, will be used as an example without loss of generality for arbitrary PoF orempirical mechanism models. The direct SPM mapping for Black’s equation is shown inFig. 4.2.864.3. Hierarchical Probabilistic Physics-of-Failure ModelsFigure 4.1: Introduction to graphical representations of SPMs using resistor thermalnoise to illustrate different variable and parameter types.Figure 4.2: Direct mapping of Black’s equation for electromigration failure time to astructured probabilistic model, revised from [6].Within this defined model, two benefits are immediately realized. First is that therandom variables representing the physical parameters that describe EM reliability arenow defined in terms of distributions that model the uncertainty as to the exact valueof the variables. Initial distributions for Eaa and n must be chosen, explicitly specify-874.3. Hierarchical Probabilistic Physics-of-Failure Modelsing prior beliefs as to the variable values. This allows for historical data and expertopinions to be directly and transparently incorporated into the wear-out reliability mod-elling process. Second is that inherent stochasticity has been introduced through themeasurement process, thus explicit capability to model aleatoric uncertainty as part ofwear-out reliability. Naive models following this form are still very valuable for makinginferences about mean behaviours of physical processes (see the case study in Sec. 9.3for an example); its drawbacks are evident only for deeper investigations of variability.An immediate issue with the simple SPM arises despite the benefits over a determin-istic form in that aleatoric uncertainty is introduced via a single variable that is intendedto encode the variability introduced by measurement. If the EM lines are checked forfailure more frequently, this variability should intuitively decrease, leading to the limit-ing case where the model would become deterministic. This makes no sense however,as different interconnects will fail at different times experimentally due to aleatoric un-certainty in the physical process itself. A more complete approach is needed to capturethe inherent stochastic behaviour of EM failures independent of measurement precision.This is achieved through adding stochasticity to the internal model variables, not justthe measurement process. First, stress conditions and characterized device parameters(e.g., slight interconnect cross-sectional area differences due to process variations) arerepresented as random noise variables to model the fluctuations between individual de-vices on a chip that can not be directly measured per device. Treating these as noisevariables assumes that stress variations between devices can be fully characterized. Inmany situations this may be untrue, in which case they could be treated as latent vari-ables, though epistemic uncertainty as to stress conditions and device parameters is leftout of scope for this modelling approach. Additionally, the hidden parameters describingEM are also made to vary between devices. Mathematically, the random variables forEaa and n are now sampled once per EM test line such that any given test line sharesthe same underlying joint probability distribution of possible failure times, however eachtakes different independent values dependent on the exact sampled variable values. Theadjusted model is shown in Fig. 4.3; note that the hyper-latent variables have becomelatent variables and that the EM line multiplicity plate now encompasses both the stressand latent variables.884.3. Hierarchical Probabilistic Physics-of-Failure ModelsFigure 4.3: Mapping of Black’s equation to an SPM with stochastic behaviours introducedto the model parameters and stress conditions.A new issue occurs when trying to perform analyses with the updated SPM. Withthe latent variables modelling both epistemic and aleatoric uncertainty, the distributionsfor the latent variables are now “overloaded”, as in they are simultaneously encoding twodifferent quantities. This makes it difficult to place prior beliefs on the latent variables,and if the degree of variability itself is not fully known the latent variable distributionsbecome extremely challenging to deconstruct and reason about for both engineers andalgorithms. To overcome this, the epistemic and aleatoric variability must be separated,which is most effectively achieved through transformation to a hierarchical model. Sincehierarchical models have some additional benefits (though also additional technical chal-lenges that will be discussed in Sec. 6.1.1), there are limited existing works that use themfor reliability analysis in adjacent fields [199–203]. Of these works, only Kitai et al. lever-age them specifically to provide distinction between epistemic and aleatoric uncertaintyfor mechanical roller bearing lifespan prediction [199]. The hierarchical transformationof the EM model is shown in Fig. 4.4.894.3. Hierarchical Probabilistic Physics-of-Failure ModelsFigure 4.4: Mapping of Black’s equation to an SPM with stochastic model parametersand hierarchical priors to separate variability and uncertainty within the model.Equipped with this hierarchical model, complex reliability analyses can be conductedwith separate consideration for epistemic uncertainty and stochastic variability. Formany analyses this SPM is fully sufficient, however to fully model mechanisms in modernsemiconductor devices it is valuable to introduce one further element of complexity to thismodel. As seen in the HTOL test description in Sec. 1.6, the sample devices in HTOLtests are sourced from separate groups corresponding to different production lots. This isnecessitated by the impact of group level effects on semiconductor reliability. With minordifferences in process conditions significantly affecting physical parameters, a lifespanestimate based on data obtained from a single chip or lot may not be representative ofthe reliability across chips within a lot or between lots [170, 184]. Neglecting the impactsof group-level variability on LTR would be negligent for high-reliability products withstrict minimum lifespan requirements. By introducing multilevel variability modelling asa final transformation to the SPM these group-level variability effects can be representedsimultaneously with device-level shifts. This technique provides further justification for aBayesian approach as multiple aleatoric uncertainty sources can be incorporated explicitlyinto the reliability model without need for significant changes at the analysis/algorithmiclevel. The final probabilistic EM model with the full SPM architecture is shown in Fig.4.5.904.3. Hierarchical Probabilistic Physics-of-Failure ModelsFigure 4.5: Mapping of Black’s equation to the developed SPM architecture for semicon-ductor reliability analyses with multilevel variability and uncertainty quantification. ©2025 IEEE [6]Two new duplicity plates are added for chip-level and lot-level aleatoric uncertaintywith corresponding hyper-latent and latent variables to model the variability at each ofthese group levels. The parameters describing EM, Eaa and n, are now deterministicsummations of a mean value and multiple zero-mean deviations to obtain individualsample values for each interconnect line (or products of deviations with a mean of oneif desired). The same lot-level and chip-level sampled values are shared across multipleinterconnect lines, while the device-level is sampled independently for every line.Predictions made using this finalized model architecture can carry exceptional nu-ance, encoding epistemic and aleatoric uncertainty independently at the device, chip,and lot levels for each parameter of some arbitrary reliability mechanism model. Indi-vidual mechanism models, such as the EM example shown, can then be integrated intolarger SPMs that relate degradation to circuit level or even system level parameters thatcan be directly measured, allowing for inference of detailed behavioural models basedon higher-level observations that can be obtained in-field. Some interesting examplesof advanced system-level reliability modelling considerations in a Bayesian context aregiven by Zeng and Zio in generalized system failure mode analysis [70] and Yang et al.to handle prior knowledge at multiple levels of abstraction [204].914.4. Probability Distributions for Hyper-Latent VariablesAnalysis approaches leveraging the developed SPM architecture are constructed infuture chapters; Ch. 5 will introduce a generative modelling tool that simulates definedSPMs to provide physically representative wear-out data, while Ch. 6 will show howCBI can be conducted on these models to learn wear-out behaviours from test data.Each provides examples of how use of the SPM architecture realizes direct benefits inwear-out reliability prediction. First, however, the upcoming sections will discuss someconsiderations for specifying these particular SPMs in light of their complexity.4.4 Probability Distributions for Hyper-Latent VariablesWith wear-out model parameter variability decoupled from epistemic uncertainty in thedeveloped SPM structure, the probability distributions of hyper-latent variables directlyrepresents imperfect knowledge about a parameter value informed by expert opinion andhistorical data. Foreshadowing Part III, but also relevant for generative modelling and toallow for the theoretical idea of a “fully inferenced model”, it is important to consider howthe choice of distributions for hyper-latent variables impacts use of the SPM architecture.Consider some arbitrary hyper-latent variable, such as a mean humidity dependencecoefficient. If accelerated tests at a variety of humidity levels are conducted repeatedly,Bayesian inference based on the test observations gives a framework to form updatedbeliefs as to the value of this coefficient over time. Note that the magnitude of humiditydependence could be any arbitrary value, which is not perfectly known when selectingthe initial/prior distribution for the variable. The selected probability distribution shouldtherefore have a central tendency/location t that is dependent on the distribution pa-rameters and can take any real value so that inference can converge to arbitrary values.Different measures of central tendency (i.e., mean, mode, or median) can be used de-pending on the distribution to demonstrate this: in the limiting case discussed shortlyall well-defined measures for a distribution should converge to the same value. Addition-ally, in theory, infinite test and inference cycles should lead to near-perfect knowledgeif inherent aleatoric uncertainty in the test procedure and devices is neglected. Perfectknowledge implies no epistemic uncertainty, thus a hyper-latent probability distributionwith zero variance. Considering the need for arbitrary mode support and theoreticalzero variance together, any distribution used to represent epistemic uncertainty as to thevariable value should allow variance σ2 of the distribution to approach zero and centraltendency t to settle on some arbitrary “true” value if informative testing continues indefi-nitely. This leads to a limiting posterior density for the hyper-latent variable distributionthat looks like the time-delayed (sifting) Dirac distribution δ, defined in Eq. 4.1.924.4. Probability Distributions for Hyper-Latent Variableslimσ2→0+p(x) = δ(x− t) =∞, x = t0, x ̸= t (4.1)Infinite testing and perfect knowledge are idealizations, but imply that hyper-latentvariable distributions should contain the time-shifted Dirac distribution as a limitingcase (can also be thought of as a single arbitrary deterministic value or discrete dis-tribution taking a single value with probability 1). The argument provided thus far isintuition-based, however is further justified by leading to the SPM structure adapted forgenerative modelling, where model parameter hyper-latents are selected as determinis-tic values instead of distributions, and also this result is a necessary assumption in theimplication that more information leads to less uncertainty. This latter implication willbe explained and leveraged in Ch. 7, where information gain, based on reduction ofepistemic uncertainty, is used as a basis for comparisons of accelerated test designs.Some standard continuous probability distributions containing the Dirac distributionas a limiting case that are recommended for use in specifying hyper-latent variablesare listed in Table 4.1. Note that other distributions (such as the gamma distribution)contain the Dirac distribution but have coupled mode and variance, making the limitingcase extremely challenging to approach via inference, thus are excluded. This table isnot exhaustive; specialized distributions could also be suitable for specifying hyper-latentvariables but are not developed or surveyed within the scope of work. From this table,selection of specific distributions and appropriate prior beliefs for hyper-latent variablesshould be founded on best general practices and knowledge of the specific physical wear-out models and product application. A good overview of specifying prior beliefs in generalreliability engineering is provided by Tian et al. [190], and Sec. 6.1.2 will discuss somegeneral selection techniques.Table 4.1: Recommended distributions for specifying continuous hyper-latent variablesin semiconductor reliability models, revised from [6].Distribution Domain Parameters Mean Variance Further AlternativesBeta Proportion [205] (0, 1) µ, ϕ µ µ(1−µ)1+ϕGumbel (−∞,∞) µ, β µ+ (0.5772...)β 16π2β2Laplace (−∞,∞) µ, b µ 2b2 Asymmetric Laplace,Soft LaplaceLogistic (−∞,∞) µ, s µ 13π2s2 Log LogisticNormal (−∞,∞) µ, σ µ σ2 Log NormalPareto [x,∞) x, α xαα−1 ,∞ if α ≤ 1x2α(α−1)2(α−2) ,∞ if α ≤ 2Symmetric Pareto,Generalized ParetoLocation-Scale T (−∞,∞) µ, τ , v µ,undefined if v ≤ 1vv−2τ2,undefined if v ≤ 2CauchyUniform (−∞,∞) a, b a+b2 112(b− a)2 Reciprocal934.5. Useful Hyper-Latent Variable Transformations4.5 Useful Hyper-Latent Variable TransformationsOne challenge with limiting the types of probability distributions that can be selected forhyper-latent use is that it reduces user flexibility in selecting distributions that exhibitother desired qualities. The most common example of this is constraining the domainof variables. For example, using normally-distributed latent variables, the hyper-latentvariables encoding the epistemic uncertainty as to the latent variance must be positiveand non-zero for the specified normal to be valid. In the statistics literature half-normal orhalf-Cauchy distributions are common selections for hyper-latent distributions encodingvariance magnitude [206], but for the application at hand are not appropriate selectionsgiven that they do not have arbitrary mode support.Within the developed SPM architecture, variable transformations can be used toresolve this challenge while minimizing impacts to models and algorithms. In particularto the most common case of variables that must be constrained to (0,∞), the softplusmathematical transform can be applied to some hyper-latent random variable x in tandemwith the one-dimensional affine transform, both shown in Eq. 4.2, to allow for positivelyconstrained hyper-latent variables to be specified using an unconstrained distribution.For the vast majority of anticipated applications only the scaling factor a in the affinetransform is needed; the translation component b is set to 0.Softplus(x) = ln(1 + ex) , Affine(x) = ax+ b (4.2)The softplus variable transformation does significantly impact distributions when alarge portion of the probability density is near or below zero, thus can significantly distortor even change the mode of the transformed variable distribution. The affine transformis leveraged to reduce distortion of the mode resulting from the softplus and, as willbe seen in Ch. 6, is used to normalize the magnitudes of variable spaces for improvedCBI performance of some numerical Markov chain sampling methods. For variables withsmall magnitudes (such as an apparent activation energy of 0.7eV), the distribution canbe specified at a larger order of magnitude within a wear-out model SPM. A softplustransform is then applied, followed by an affine transform to scale down the variablemagnitude to the intended range. The transformation order can be reversed for variablesat large orders of magnitude to further minimize distortion. The variable is specified atreduced magnitude, then an affine transformation is used to scale up the value beforea softplus transform is applied to constrain the domain. Fig. 4.6 illustrates how thedescribed procedure minimizes distortion for an example case of specifying a strictlypositive soft Laplace distribution.944.5. Useful Hyper-Latent Variable TransformationsFigure 4.6: Illustration of using variable transformations to constrain the domains ofrandom variables while minimizing distortion of mean and variance.Without applying any transformation the left tail of the hyper-latent probability den-sity function extends into negative values, which may fall outside the domain of the latentvariable distribution parameter it represents. Applying the softplus transformation aloneleads to a 20% relative error in the distribution mean, thus an affine transformation isused to scale down a distribution specified at a larger order of magnitude. This results inmulti-modality, but minimizes distortion of the transformed distribution. Some unavoid-able minimum distortion occurs regardless of the scaling magnitude used, dependent onthe proportion of the target distribution density that extends below zero and the vari-ance. For the constrained soft laplace distribution seen in Fig. 4.6, the minimum meanand variance distortion errors of the transformed distribution are 0.2% and 3.6% re-spectively. The unavoidable distortion associated with specific target prior distributionsshould be considered when specifying models; in general the posterior distributions forhyper-latent will have reduced variance and thus reduced distortion in comparison to theconsidered prior distributions. Other types of variable transformations may be useful inspecific situations, however are found to be less commonly required across the majorityof semiconductor wear-out models used for case studies. For generative modelling usingthe developed SPM architecture in the coming chapter, hyper-latents can be specified asdeterministic values, thus variable transformations are rarely needed. For model infer-ence and reliability prediction applications seen in later chapters, however, the techniqueis widely applied to obtain constrained and numerically stable wear-out models.954.6. Interpretable Uncertainty Quantification4.6 Interpretable Uncertainty QuantificationIn the introductory chapter the need for effective quantification of uncertainty was em-phasized for enabling strict requirements in high reliability semiconductor markets. Theprobabilistic aspect of the developed SPM architecture is well suited for this applica-tion, and the separation of aleatoric and epistemic uncertainty further aids in analysis ofproduct lifespan uncertainty. Information entropy can be used in this context to describeand compare the uncertainty in the distribution of an individual or joint set of randomvariables. One important point to note is that model uncertainty is an important factorto consider in addition to parameter uncertainty, however is left out of the scope of thisresearch work. This limitation is due to both the relatively small number of compactPoF models available in the semiconductor reliability literature and the additional tech-nical challenge that would be introduced. No specific claims of low model uncertaintyin the case studies of this dissertation using real-world experimental data (Secs. 6.4.2and 9.3) can be made in light of sparse semiconductor LTR literature on NBTI or HCImodel comparison and error; this is a deficiency equally present in prior semiconductorlifespan prediction research. Case studies using simulated data have no or known modelinaccuracy and so are unaffected by this scope limitation. Future work to supplementvariable uncertainty analyses with model uncertainty quantification would be valuablefor enabling high reliability market regulation.For review, the Shannon information entropy H of some d-dimensional discrete ran-dom variable space X = {X1, ..., Xd}, distributed according to p(x), is provided in Eq.4.3, placing a quantitative value on the amount of uncertainty inherent to X in terms ofan expectation E over the information I(x) [207]. Note that the logarithm base can bechosen arbitrarily and determines the units of information (the natural logarithm withunits of “nats” will be primarily used going forward). Additionally, no similarity betweencomponent random variables of X should be assumed (i.e., it is not a multivariate ran-dom variable, merely a set). This slight abuse of bolded symbol notation is useful goingforward to identify groupings such as the set of all hyper-latent variables and follows theconventions of A. Owen’s text on Monte Carlo theory [208].H[X] = −∑x∈Xp(x)log[p(x)]= EX [I(x)] where I(x) = − log[p(x)](4.3)For discrete random variables Shannon entropy is well defined and has some physicalinterpretation in terms of the expected degree of surprisal when a specific outcome is964.6. Interpretable Uncertainty Quantificationobserved. For continuous random variables, however, the direct adaptation of Shannonentropy, differential entropy, can result in negative values and has little physical inter-pretation. This arises from the infinite number of real values in any continuous interval;any specific measured value is infinitely improbable. To combat this, Jaynes’ limitingdensity of discrete points (LDDP) correction to differential entropy is leveraged [209].The basic formulation of LDDP shown in Eq. 4.4 is still infinite, with entropy H[X]explicitly considering the infinite cardinality n of a continuous random variable space.A measure distribution m(x) across the possible values is used as the reference point ofcomparison for p(x).H[X] = limn→∞ log n− EX [log [p(x)m(x)]] (4.4)Consider that in any real-world experiment the number of measurable values is limitedby the precision of the instruments used. This practical consideration provides a wayto make n finite, instead of a limit, and for general computational use the precisionof floating point representations can be adopted. Furthermore, following the intuitionthat the uncertainty in a model variable should not depend on its order of magnitude(analogous to the preference for relative over absolute error), the exponent of the floatingpoint representation is discarded and the cardinality c of the combined sign and mantissais used for n. The reference m(x) is set to be a d-dimensional, magnitude-proportionaluniform distribution bounded by [a, b] across the variable space (corresponding to theuniform distribution of values a mantissa can take with a fixed exponent). These decisionsproduce a finite definition for practical continuous information entropy:H[X].= log [cd]−∫ bap(x) log [(b− a)dp(x)]dx (4.5)This expression has physical interpretation as the uncertainty relative to the limitof numerical precision, and reaches zero when sampling X always results in the sameset of floating point values. The expression can still produce negative values, but onlyif the range [a, b] is grossly inappropriate by several orders of magnitude. In generalthe integral has no closed-form solution and so numerical integration techniques must beused to estimate the entropy. Variable spaces should ideally be normalized to the sameorder of magnitude so that a and b are relatively proportional for all variables, howeverthe expression can be deconstructed into a sum of individual integrals for each randomvariable with unique a and b for each variable if needed. Finally, note that this expressionshares significant similarities with relative entropy (a.k.a. Kullback-Leibler divergence),but by fixing the comparison distribution m(x) and including the log [cd] term the LDDP974.7. Uncertainty-Aware Metrics for Specifying Product Lifespanentropy has a consistent physical meaning and can be interpreted with limited technicalbackground for engineering contexts.Unless otherwise stated, going forward entropy values all use the special case of theconstructed interpretable entropy expression with IEEE 32-bit floating point represen-tations (a 1-bit sign and 23-bit mantissa) and bounds a = −838.8608, b = 838.8607.This specific expression for interpretable entropy, denoted hereafter as Hφ for distinc-tion, results in increments of 0.0001 between successive values within the range, thusHφ[U(0, 0.0001)] = 0 nats exactly to allow for a reasonable tradeoff of precision andrange for random variables approximately normalized to N(0, 1) scales (to be pedanticthe IEEE representation uses two separate encodings for 0, resulting in a cardinality of224−1, but this is practically irrelevant). The definition results in quantified uncertaintyfigures such as Hφ[N(0, 1)] = 10.6288 nats and Hφ[U(0, 1)] = 9.2103 nats = 4 hartleys.4.7 Uncertainty-Aware Metrics for Specifying ProductLifespanAccepted metrics within semiconductor reliability engineering are simplistic and oftenmisused. Failures in time (FIT) is the greatest culprit, as the metric specifies a constantfailure rate. This is perfectly acceptable for operational life failures where the randomfailure rate is independent of time, however for wear-out failures the rate changes aswear-out progresses, thus FIT is time-dependent during the wear-out phase of productlife. Other metrics such as mean time to failure (MTTF) are more appropriate in thatthey do not assume a constant failure rate, however they provide an estimate of thetypical product lifespan, which is not of interest for high-reliability applications whereusually the objective is instead to characterize the lower/left distribution tail where thefirst wear-out failures appear across thousands of chips.One proposed metric for specifying semiconductor lifespan could be identified in theliterature, targeting lifespan prediction of flip-flops and dubbed the timing yield-awarelifetime reliability [171]. It integrates a specific failure criteria for flip-flop timing calledthe input-to-output maximum allowable delay, then evaluates the proportion of flip-flopsthat can be expected to remain within this delay requirement at some arbitrary time. Itimproves over MTTF in targeting a selectable proportion of chips, as in the point at whichsome chosen percentage of flip-flops are still functional, however is not appropriatelygeneric to account for arbitrary circuits or wear-out mechanisms. Additionally, none ofthe discussed metrics are compatible with a Bayesian approach to reliability that accountsfor epistemic uncertainty, instead only addressing aleatoric uncertainty.984.7. Uncertainty-Aware Metrics for Specifying Product Lifespan4.7.1 Lower Bound Quantile Credible IntervalWithin a Bayesian context, epistemic uncertainty leads to a range of possible failure ratecurves for a given product, even after extensive accelerated testing. Credible intervalsaddress this, specifying the range of values within some probability quantile bound. Ver-bally, an x% quantile credible interval under epistemic uncertainty states that, “It canbe said with x% confidence that the product lifespan is within this range.” Note thatcredible intervals are equally applicable to aleatoric uncertainty but instead communicatethat, “x% of chips will have a lifespan within this interval.” For the developed SPM struc-ture, a credible interval containing both epistemic and aleatoric influence means that, “Agiven chip has an x% probability of failing within this interval across all possible realitiesand stochastic outcomes.”For a given probability bound, there are in general an infinite number of possiblecredible intervals that contain the desired percentile of values. It is thus important toselect an appropriate procedure for choosing a credible interval. For wear-out reliabilityspecification this selection is intuitive, as the key concern is ensuring that x% of chips lastlonger than the specified product lifespan, thus the interval excludes the 1− x% of chipswith the shortest lifespan. This is evidenced by similar use of lower quantile analysisof lifespan distributions in the more general reliability engineering literature [210, 211].This is a lower-bounded credible interval, stating that x% of chips will fail within someinterval [τ,∞) across all possible scenarios and stochastic effects. This metric will bereferred to as the Qx%-LBCI, taking value τ for a target x% to demarcate extreme-valuefailures under uncertainty while still producing a single-point lifespan estimate based onapplication-specific required reliability. The metric can thus be used to effectively definethe boundary between the operational life and wear-out phases of a product’s bathtubreliability curve.A key benefit is that the predicted lifespan and uncertainty are both encapsulatedwithin this single statistic, while remaining relatively simple to compute and communi-cate. Sampling product lifespan from a probabilistic model will yield a broad range ofvalues. After a sufficiently large quantity of samples in comparison to the target quantilehave been drawn, the statistic can be computed in a straightforward manner via trans-formation to a CDF and then interpolation of the sampled points. From a regulatorystandpoint, metrics encapsulating uncertainty provide increased resilience to manipula-tion over those such as FIT and MTTF, as cherry-picking small data sets that lead tofavourable predictions is much more challenging given that inference is dependent onthe size of the data set. Manipulation of Qx%-LBCI is still possible through selectingoptimistic PoF models and/or favourable priors for hyper-latent variables, however these994.7. Uncertainty-Aware Metrics for Specifying Product Lifespanassumptions are explicitly stated and thus easy for a regulatory body to critique throughmandatory disclosure. For strict semiconductor markets, regulatory bodies could fullystandardize the models and priors to mitigate the potential for manipulation.Though the Qx%-LBCI benefits from accounting for both uncertainty and variability,their coupling into a single value does come with a drawback, as information gained fromaccelerated testing does not necessarily correspond to a better “score” if the informationsuggests poor reliability. The coupling also reduces interpretability if trying to commu-nicate uncertainty components in isolation. Future work towards complementary metricsthat address lifespan uncertainty and variability independently could supplement the twoproposed in this chapter.4.7.2 Highest Density Quantile Credible RegionWhile failures at the early extreme of the lifespan distribution are of primary interestfor specifying LTR requirements in high-reliability applications, characterizing typicalproduct lifespan can also be of interest. This is evidenced by existing metrics’ focuson the mean product lifespan. In support of mean lifespan analysis, a metric morein line with MTTF, yet providing some indication of the degree of lifespan variabilityand uncertainty, has significant value. The x% quantile highest density credible region,denoted Qx%-HDCR, is proposed to fill this gap.Almost identical to credible intervals, credible regions bound the same overall prob-ability percentage but additionally permit non-contiguous value ranges. This can beparticularly beneficial for analysis of multimodal lifespan distributions, which in the con-text of semiconductor reliability could occur in cases where multiple mechanisms areresponsible for different proportions of failures. Choosing a credible region based onhighest probability density results in a minimum size bound, capturing the desired totalpercentage of probable lifespan in as small a region as possible. The Qx%-HDCR there-fore characterizes typical product lifespan in the presence of uncertainty and withoutprecluding the presence of multimodal lifespan distributions. One drawback, however,is that the metric evaluates to one or more intervals as opposed to a single value, thusis less trivial to interpret and less well suited for regulatory use in comparison to theQx%-LBCI.Fig. 4.7 illustrates the proposed metrics on a multimodal lifespan distribution. Look-ing at the MTTF or statistical mode leads to an oversimplified impression of typicalproduct lifespan in comparison to Qx%-HDCR, while the Qx%-LBCI metric is agnosticto the distribution shape and merely indicates the end of operational life for some degreeof strictness as to LTR in terms of both epistemic uncertainty and lifespan variability.1004.7. Uncertainty-Aware Metrics for Specifying Product LifespanThese two proposed metrics are compatible with probabilistic analyses, and are thusleveraged significantly in the remaining part of this dissertation to define requirementsand quantify the value of accelerated tests.Figure 4.7: Comparison of proposed lifespan metrics to MTTF when working with abimodal failure distribution.101Chapter 5Generative Modelling forIn-Depth Aging SimulationsEven before introducing CBI, probabilistic modelling can be leveraged for generativemodelling of reliability data that accounts for complex variability effects in semiconductorwear-out. Simulated data is used in various applications, from design analysis to PoF andblack-box model development. Within the specific context of semiconductor LTR, themajority of existing simulations are based on the SPICE circuit simulator. The standardSPICE simulator has no functionality for reliability investigation, but is so prevalent asto be synonymous with electrical circuit simulation. Typical wear-out analysis consists ofan initial SPICE simulation, a separate software tool computes the aged device models,then a second simulation is conducted using the aged parameters to determine circuit-level performance degradation. Existing tools using this format can be grouped intotwo categories depending on whether they target analog or digital applications, withseveral simulators in each category. Seven existing analog tools were identified [212–218] alongside three for digital applications [171, 219, 220]. The final class of existingsimulation tools does not use SPICE in favour of targeting hard failure events in individualdevices (as opposed to degradation). These directly simulate time-to-failure data usingmodels such as the one presented for TDDB in Sec. 1.4, with three prior simulatorsidentified [175, 221, 222].Each of the three existing flavours of wear-out simulation have various benefits andlimitations, but there are multiple features offered by generative modelling using the SPMarchitecture developed in the previous chapter that are not found in any prior works.1. A fully agnostic perspective on specific PoF models, instead treating them as inputsto the simulation process.2. Multilevel variability support to allow for simulation results influenced by multiplesources of stochastic variations.3. Time-varying stress condition support for arbitrary temporal degradation modelsthat exhibit no wear-out under certain conditions.1025.1. Structure of the Simulation SoftwareThe resulting generative modelling tool is provided as a Python software library underthe Apache 2.0 license [223]. The design of the simulator is discussed first, followed bydemonstrative case studies evidencing how the simulator leverages the SPM architectureto deliver on the listed features.5.1 Structure of the Simulation SoftwareThe fundamental approach to generative modelling of wear-out data is achieved by sam-pling an SPM representing a PoF model (though typically the hyper-latents in the de-veloped SPM architecture are treated as deterministic parameters for simulation). Theuser specifies hyper-latent parameters, distributions, observed variables, and mathemat-ical relationships between the variables that constitute the model, which can then besampled given a set of stress conditions. The device wear-out model is situated within asimulated test environment that emulates the offset errors and variability of stress condi-tions alongside measurement precision and noise limitations. An abstract representationof the high-level software components used to describe a simulation is shown in Fig. 5.1.Figure 5.1: Abstract representation of the data class model in the simulation tool, withthe workflow indicated via blue arrows. © 2023 IEEE [5].1035.1. Structure of the Simulation SoftwareTest specifications within the simulator are constructed in a similar way as for theautomated test system design seen in Sec. 3.2, consisting of an ordered sequence of stepswith each step being either a stress or measurement specification. A stress step definestarget stress conditions such as temperature and voltage alongside a time duration, whilea measure step indicates the instantaneous target conditions for measurement alongsidea listing of quantities of device model parameters to measure. The full test specificationstores the ordered test step listing and indicates how many chips and lots are used.The environment model builds on features of the SPM architecture, introducing op-tional multilevel variability, noise for stress conditions, and measurement variability toenable simulations under imperfect testing conditions. Explicitly incorporating measure-ment precision, parameter noise, and non-uniform environmental conditions can helpwith evaluating the resilience of analysis methods to complex test data.The final major data model is the device SPM. For use without expertise in proba-bilistic modelling, the software library provides a layer of abstraction over the SPM andsub-divides the model into structural components to better align with standard represen-tations of PoF wear-out models. The physical model equation is provided as an input,then latent variables with stochasticity are specified individually. The device model isarranged hierarchically into an arbitrary set of circuit parameters dependent on deviceparameters that degrade according some number of wear-out mechanisms, with program-matic functions defining the relationships. This sub-division allows for intuitive re-use ofsmaller components to build a full, complex device specification.Once a set of data models have been specified by a user (some common pre-builtmodels are provided in the software library for ease of use), a simulation is performedvia a single function call that initializes stochastic device parameters and then executesa test, returning a report containing: i) all measurements as a long format table withinformation on which lot, chip, and device each measurement is associated with along-side timestamps, and ii) a long format table summarizing the test in terms of what stressconditions were applied for how long and when within the overall test duration. All sim-ulation state is isolated within the function call, keeping the specified models stateless toallow for parallel execution of multiple simulations. There are numerous implementationchallenges associated with managing state information, multi-level stochastic sampling,and performing input validation for users that are not discussed for brevity, howeverdocumentation for many of the internal aspects of the software is provided as part of theonline repository [223].1045.2. Time-Varying Stress Simulation Method5.2 Time-Varying Stress Simulation MethodThe vast majority of compact physics models for wear-out reliability mechanisms areexpressed algebraically as a set of mathematical equations. Crucially, stress time andstress conditions are almost always treated as single-valued variables, which precludesthe possibility of time-varying stress. This is justifiable for purposes of simplicity andto avoid the introduction of model state, however is unrealistic for the vast majority ofin-field use cases. The simulator is designed to enable time-varying stress, but with a lackof compact models that support time-varying stress internally, a workaround approachis leveraged to allow for physically accurate time-varying stress simulation of arbitraryalgebraic models (subject to a few restrictions). The technique, based on calculatingequivalent stress times under successive stress conditions, has previously been used byLu et al. [224], Guo et al. [212], and Huang et al. [225] in specific applications; herethe approach is adopted for general use and the necessary physical assumptions aremade explicit. The approach is also enhanced to allow for time-varying simulation ofmechanisms exhibiting threshold behaviours, as in those that only exhibit degradationunder certain conditions, and to remove a mathematical constraint on models requiredby prior works.The equivalent time method requires one physical assumption and two constraints onthe mathematical form of a compact wear-out mechanism model. So long as these aresatisfied, physically accurate simulations under arbitrary time-varying stress simulationscan be conducted for arbitrary algebraic and/or programmatic models. The physicalassumption is that a mechanism’s future rate of degradation only depends on the currentmagnitude of degradation and is independent of how that degradation occurred. In moreabstract terms, the future behaviour of the system must only depend on its current stateand not on how that state was reached. This assumption is implicitly accepted in muchof the wear-out reliability literature and is merely made explicit here. Extreme casescould be envisioned, such as an SILC gate leakage current magnitude arising from afew defects in the middle of a dielectric layer (maximizing overall tunneling probabilityper defect) versus arising from many defects near the dielectric edges, which could havedifferent future defect formation probabilities if the total number of candidate defect sitesis low. Even in this case only a simplified empirical SILC model is impacted; the physicalassumption still holds given that the actual dielectric state is different in each case. Ingeneral, this assumption is safe to adopt for the vast majority of PoF models, but isimportant to consider before use. The two mathematical constraints are as follows:1055.2. Time-Varying Stress Simulation Method1. Degradation must be monotonic with respect to time across all stress conditionsused within a test, but not strictly monotonic. Prior implementations requirestrictly monotonic behaviour, the relaxation of this constraint is contributed aspart of the simulator.2. At time t = 0, the computed degradation must be identical across all stress condi-tions used within a test.Prior works implementing the approach are additionally constrained to models withidentical degradation across all stress conditions used within a test as t → ∞ (infi-nite degradation permitted), however this constraint is not required within the simulatorimplementation.The method is described for the base case of a single change in stress conditionsduring a test, which can then be inductively extended to arbitrarily many stress changes.The empirical degradation model is denoted D(t,S) with stress duration t and stressconditions S. Under conditions that change from some set of values S0 to another, S1,at some time instant tsw, the total test-end degradation ytot at time ttot is defined asD(ttot,Sv) = ytot | Sv =S0, t ≤ tswS1, t > tsw (5.1)This expression defies direct computation, given that the model for D(t,S) onlyaccepts a single set of values S, and so ytot is instead computed in steps using theequivalent time approach. The principle is to first compute the intermediate degradationyint at time tsw under the set of stress conditions S0 asD(tsw,S0) = yint (5.2)and to then find the equivalent time tequiv that would be required under stress conditionsS1 to reach the same degradation state yint. This requires solving for tequiv inyint = D(tequiv,S1) (5.3)which for arbitrary degradation models may not have an analytic solution. Numericaloptimization is thus necessary to determine tequiv regardless of the specific model used.The choice of an appropriate optimization algorithm is considered in detail in Sec. 5.3.In prior implementations, three constraints are required to ensure a unique solution fortequiv is guaranteed to exist. The implementation within the simulator can handle twospecific exceptions to this, however, relaxing the model constraints. First, if multiple1065.3. Parallel Brent’s Minimization Methodsolutions exist (implying non-strict monotonicity) the minimum time among the multiplesolutions is selected given that the physical state of degradation in all cases is identical.Second, if no solution for yint exists then no degradation occurs between tsw and ttot, thusyint = ytot and the final step described below is not needed. Together, this additional edgecase handling enables physically accurate simulations of mechanisms that only exhibitdegradation past stress thresholds, such as melting points of interconnects or catastrophicdiode breakdown, and those that exhibit hard saturation, such as if a limited number ofpotential defect formation sites exists. With the equivalent time determined, the finaltest degradation ytot can then be computed by an equivalent constant stress testD(tequiv + (ttot − tsw),S1) = D(ttot,Sv) = ytot (5.4)that holds subject to the previously discussed physical assumption. Inductively followingthis base case, multiple stress changes can be computed by successively treating the basecase ytot as the subsequent yint and proceeding as before.5.3 Parallel Brent’s Minimization MethodFor simulation of wear-out in multiple transistors across many chips and lots, parallelcomputation is critical to achieve time-sensitive performance. For the most part thisis easily achieved through vectorized computation, as all mathematical operations areperformed identically for all simulated samples at the same time. The numerical opti-mization step within the equivalent time computation is the notable exception, as numericconvergence techniques may require different numbers of iterations per sample, and inparticular could contain branching logic depending on sampled values.An algorithm appropriate for wear-out simulation needs to guarantee solution con-vergence, cannot depend on function derivatives (as some models could be discrete),and should converge to a solution reasonably quickly regardless of function shape giventhat the method will be applied to large quantities of stochastic samples for arbitrarywear-out models where derivatives are not specified. Brent’s minimization method wasselected [226], combining parabolic interpolation with golden-section search techniquesto provide guaranteed minimum convergence rates to a valid solution, alongside highmaximum convergence rates when parabolic interpolation can be performed within thealgorithm. Additionally, the monotonicity constraint on mechanism PoF models withinthe simulator ensures that the negative degradation model function −D(t,Si) is alwaysunimodal under any specific stress conditions Si. In other words, D(t,Si) has no morethan one minimum inflection point. This allows Brent’s minimization method to also1075.3. Parallel Brent’s Minimization Methodguarantee that the found minimum is global within the specified interval. As a pointof clarification, a root-finding algorithm commonly referred to as Brent’s method wasalso introduced by Brent in 1973 but should not be confused as equivalent. The draw-back of Brent’s minimization method is that it requires complex branching logic, thusin its basic form needs to be run sequentially for each simulated sample for each stressstep in a test definition, drastically increasing overall simulation times. A version of thealgorithm is introduced that can be applied element-wise to multi-dimensional arrayswith full parallelization, allowing for drastic performance improvements due to more effi-cient software execution patterns and compatibility with hardware implementing vectoroperations. Additional support for logarithmic timescales and computational graph com-pilation is also introduced to enable use tailored for reliability applications and withinprobabilistic programming libraries.Parallelization of the method is built on two techniques, element-wise ternary op-erators and properties of mathematical identity values. Filling target values in arrayswith the identity value for a given operator allows for a statement to be uniformly ap-plied across an array without affecting certain values, while vector if-else statementsimplement optimized looping for rapid conditional operation on arrays. This requiresrestructuring the method to align the steps within each sub-problem regardless of theexecution path taken by each, with some additional identity operations incurred as acost. Finally, iterations must continue until all sub-problems have converged to withinsome small tolerance range, resulting in additional iterations for sub-problems that havealready converged. This incurs a further performance cost but is still orders of magnitudefaster than iterating for each sub-problem in turn.In an idealized compiled context, the speedup of the parallel implementation arisespurely from hardware batched memory and arithmetic capabilities. Both the sequentialand parallel approaches scale mathematically as O(n) in the number of function eval-uations needed to solve n problems. In the interpreted Python implementations used,however, performance improvements are also realized by avoiding re-interpretation ofthe algorithm and leveraging runtime compiler optimizations. The implemented purePython parallel Brent minimization algorithm is around 10x slower than the sequentialsolver when operating on a single input, but empirically scales over the first three ordersof magnitude of problem size as approximately O(1). Experimentally, for large n (>1000)the parallel algorithm is two orders of magnitude faster than standard Brent minimization(a 100x performance improvement). Additionally, the logarithmic timescale version oftentakes significantly fewer iterations to converge when working with exponential or power-law functions commonly encountered in wear-out modelling, providing further situation-1085.4. Demonstrative Generative Modelling Studiesdependent performance improvements of up to 3x. The full parallel Brent minimizationalgorithm description and abstract implementation is provided in Appendix A.5.4 Demonstrative Generative Modelling StudiesShort example use studies are presented to demonstrate the novel capabilities of thesemiconductor wear-out simulator in supporting arbitrary procedural models, physicallyrealistic time-varying stress simulation, and multilevel variability sources. Standard sta-tistical analysis of the data is conducted in these studies, however case studies in laterchapters will switch to computational Bayesian analysis following discussion of the soft-ware library for inference of models within the SPM architecture. Implementation cor-rectness of the developed software is verified through both unit and feature tests withinthe “tests” folder provided as part of the simulator library, and the case studies in thissection can be fully recreated using scripts in the “demos” folder [223].5.4.1 Threshold Voltage Degradation VariabilityA first case study demonstrates multilevel variability simulation of simultaneous BTIand HCI degradation in an amplifier design. Consider a hypothetical analysis of theimpact of switching to a less mature fabrication process that is expected to exhibit twiceas much lot-to-lot variability in initial threshold voltage and twice as much chip-to-chip variation in the voltage dependence of BTI and temperature dependence of HCIcompared to a current mature process. For the current process an accurate degradationmodel already exists, leveraging the BTI and HCI compact models from Eq. 1.1 andEq. 1.2 to characterize the threshold voltage shift. To show both BTI and HCI effects inthis demonstration, the HCI model is tuned to exhibit negative temperature dependenceand higher variability than BTI, though less overall degradation. A common sourceamplifier small-signal gain is the measured parameter of interest, simulated through asimple set of equations for the bias current in each transistor and the linearized gain,with bias voltages set proportional to supply voltage. The shift in threshold voltage isintroduced to both the saturation current equations and small-signal gain equation, thusthe amplifier gain is non-linearly dependent on the degree of degradation. The amplifieris assigned an arbitrary minimum tolerable gain criterion of 20. Adjustments for theless mature process with higher variability are introduced to the model, doubling thelot-level group variations of the initial threshold voltage (a stochastic device parameterin the graphical SPM architecture representation), the chip-level variability of α in theBTI model, and the chip-level variability of β in the HCI model.1095.4. Demonstrative Generative Modelling StudiesThree tests are simulated for the current and new processes, each containing 10 lotswith 10 chips with 10 amplifiers. Standard JEDEC HTOL and LTOL tests [75] comprisethe first two, then a stress-to-failure ramp test that cycles 90 hours of increasing voltageand temperature stress with 10 hour idle intervals between for the third. This latter testis enabled by the time-varying stress support of the simulator. Stochastic variations intemperature and stress voltage are introduced via the simulator environment model, andmeasurements are taken periodically to show degradation curvature and heteroscedasticvariance that increases over time. The total simulation time is 1.8 seconds on an Intel©i5-12400 processor, producing the aggregated degradation plots in Fig. 5.2 and thedetailed distributions plots of amplifier degradation at the end of the HTOL and LTOLtests in Fig. 5.3.Figure 5.2: Temporal degradation behaviour in each of the three tests for the currentand new simulated processes. Series show mean degradation, ±1 standard deviation isrepresented by the filled region. Revised from [5].Although BTI is more significant in terms of mean degradation in this study model,resulting in higher mean population degradation in the HTOL test, the higher varianceand negative temperature dependence of HCI results in a longer distribution tail in theLTOL test, which is aggravated by the new, less mature process. This manifests asseveral failed amplifiers in the simulated LTOL test for the new process, seen in the bot-tom right of Fig. 5.3. Such pronounced differences in BTI versus HCI degradation are1105.4. Demonstrative Generative Modelling StudiesFigure 5.3: End-of-test HTOL and LTOL degradation for current and new simulatedfabrication processes. Increased variability in HCI temperature dependence producestest violations under LTOL conditions. Revised from [5].exaggerated in comparison to real-world processes, however they illustrate the complexmulti-mechanism behaviours that can be captured using the SPM architecture in con-junction with the simulator. Additionally, the multilevel variability modelling capabilityallows for direct analysis of group-level variability effects. For this hypothetical casestudy, the simulated high variability under low temperature test conditions illuminatesrisk in the less mature process and further stochastic simulations could be leveraged toprovide rapid feedback on potential low-temperature analog design challenges.5.4.2 Individual Defect TDDB Model SensitivityA second study illustrates the arbitrary PoF wear-out model support of the SPM ar-chitecture and simulator, including full programmatic model definitions. Typical TDDBmodels, such as the power law model introduced in Sec. 1.4, directly output the expectedfailure times of transistors. These are contrasted with the introduction of a “toy” modelfor temporal TDDB modelling. Twelve individual defect formation sites are simulated,with four columns of three rows, representing a 2D cross-section of a transistor gatedielectric. The transistor experiences TDDB failure once all three sites in at least onecolumn contain defects, which is implemented by treating each individual defect forma-1115.4. Demonstrative Generative Modelling Studiestion as a failure mechanism governed by a time-independent, stochastic process. Theper-unit time probability of formation is computed following Eq. 5.5.formation probability = k(Tαγ)(Vgsβ) (5.5)The stress conditions are temperature T and gate-to-source voltage Vgs, then k, α,γ, and β are internal latent variables that must be learned/inferred for a given process.The overall probability of formation is obtained through scaling according to stress time,then the model randomly samples a corresponding Bernoulli distribution to determineif a defect forms. The resulting model is designed to highlight flexible arbitrary modelsupport and is not proposed as an accurate PoF model for use; in reality defect formationsites are not static, gate dielectric thickness is non-uniform, and numerous additionalphysical complexities must be accounted for.Figure 5.4: Fitted Weibull distributions to right-censored TDDB failure data simulatedusing the demonstrative temporal model across different values for parameter α. © 2023IEEE [5].Assume the model has been inferred for a process but that there is concern as to model1125.4. Demonstrative Generative Modelling Studiessensitivity with regards to α, which is determined to have a 95% likelihood of fallingbetween 1.05 and 1.15. The simulator is used to perform several simulations for differentvalues of α to observe the differences in failure predictions. In-field use conditions in thishypothetical study are characterized in detail, following a typical weekly cycle with 6hours of moderate stress per day, 2 intensive hours, and 16 idle hours, excepting weekendswhich see 21 idle hours and 3 intensive hours of daily use. Stochastic variations in stressare also characterized for this example. One thousand instances of the arbitrary modelwith per-defect formation and internal stochasticity are simulated across five reasonablevalues of α, with the in-field use conditions aggregated by stress load and checked forfailures on a weekly basis for 20 years (a total of 60 000 defect sites simulated overa test length of 4160 steps). The total simulation time is ∼32 seconds on an Intel©i5-12400 processor, after which the Python library “reliability” [227] is used to fit theright-censored simulation data to Weibull distributions and plot them in Fig. 5.4.Analyzing the worst case 95% confidence interval estimate of expected time to seeing1% of transistors fail, a spread of approximately 2.4 years is seen across the range ofα values, illustrating significant model sensitivity to the exact value of α and perhapsindicating a need for further testing to more precisely infer the model variables. Futurecase studies will follow a Bayesian analysis of failure data, as opposed to the frequentistfit methods conducted here, by leveraging the software framework for CBI of SPMspresented in the next chapter.113Chapter 6Computational Bayesian Inferenceof Physics-of-Failure ModelsIn the previous chapter the developed SPM architecture was leveraged to generate simu-lated wear-out data capable of exhibiting complex physical behaviours such as multi-levelvariability and stress thresholds. Generative modelling is incredibly useful for emulatingreal-world designs to obtain representative data and examining how wear-out models be-have under different in-field conditions, but to analyze this data and learn the wear-outbehaviours in the first place requires a framework for statistical inference. Common ap-proaches in a frequentist context are maximum likelihood estimation (MLE) and meansquared error loss minimization, working backwards from observed wear-out data tolearned fixed-point estimates for model parameters. In the developed SPM architecture,the model parameters are instead represented by probabilistic hyper-latent variables withcorresponding prior distributions that represent beliefs about the possible values for thevariables before wear-out data is observed. Bayesian inference provides a methodology toupdate these beliefs, conditional on the observed data, to obtain posterior distributionsfor the hyper-latent variables.This chapter describes a software framework for conducting CBI on wear-out modelsformulated within the SPM architecture, enabling robust model learning and subsequentanalysis and prediction of product lifespan. A review of Bayesian inference and associ-ated mathematical considerations is provided first, followed by a discussion of CBI. Thecontributed software library for ease of CBI with the SPM architecture is then explainedand discussed in detail.6.1 Bayesian Inference BackgroundWithin a probabilistic modelling context where wear-out model parameters are repre-sented as random variables rather than single deterministic values, Bayes’ rule is theaccepted approach to inference. This provides a way to reduce epistemic uncertaintyregarding some system given new evidence about the system’s behaviour in the form of1146.1. Bayesian Inference Backgroundobserved measurements. For the developed SPM architecture, the set of hyper-latentrandom variables that encodes all epistemic uncertainty will be denoted by X (notationwill broadly follow A. Owen’s text [208]). Sampling from X results in a specific set ofvalues, one per variable, which is denoted x. The probability distribution across theseoutcomes is notated p(x) and can always be assumed to be defined over the randomvariable(s) corresponding to the evaluated outcome. Given some observed test data set y(from the corresponding random variable space of possible observations Y ), Bayes’ rulestates that:p(x|y) = p(x)p(y|x)p(y)=p(x)p(y|x)∫p(y|x)p(x)dx ∝ p(x)p(y|x) (6.1)The conditional probability distributions p(y|x) and p(x|y) are known as the like-lihood and posterior respectively, and the marginal probability p(y) can be expressedin terms of an integral, illustrating the mathematical challenge of computing p(y) whenworking with complex models. Bayes’ rule must be applied ∀x ∈ X to characterizethe full posterior distribution p(x|y). Finally, the proportional equality is included toillustrate a common shortcut used in CBI. Since p(y) is a constant term independentof x, p(x|y) can be computed up to some common scaling factor ky without having tocompute the integral needed to obtain p(y). Since p(x|y) must integrate to 1 to be aproper distribution, the ky-scaled posterior can just be appropriately normalized to doaway with the need to compute p(y) altogether in some scenarios.One further benefit of a Bayesian statistical framework, in addition to the pointspresented in Sec. 4.1.3, is that Bayesian inference will always be consistent with thestatistical likelihood principle, in that what is learned from collected test data dependsonly on the data itself and not on the manner of how it was collected [228].6.1.1 Hierarchical Model Inference ChallengesWithin the developed SPM architecture, hierarchical structure results in intermediatelatent random variables that are not observed yet influence the likelihood p(y|x) ofobservations due to the dependencies in the SPM. The latent variable space is denotedV (and takes on specific value sets v). Note that the dependency structure of theSPM architecture is very explicit, with fully independent hyper-latents X, latents Vdepending only on X, and observations Y depending on both V and X. Sampling froma hierarchical model such as this is straightforward, as is done in Ch. 5, however thestructure introduces another layer of complexity during inference. In order to marginalizeout V via the law of total probability, the likelihood becomes an expectation over the1156.1. Bayesian Inference Backgroundconditional latent distribution p(v|x) according to Eq. 6.2.p(y|x) = Ev∼p(v|x)[p(y|v,x)] =∫Vp(y|v,x)p(v|x)dv (6.2)Note that this process of marginalization can be thought of as integration over theintrinsic aleatoric uncertainty of the wear-out model (the variability of stress conditions,device parameters, and measurement being extrinsic). The latent space V contains bothepistemic and aleatoric uncertainty as a result of the dependence on X, however by itselfintroduces only aleatoric uncertainty to the system given that the distribution p(v|x)can be perfectly characterized for any particular set of values x.6.1.2 Historical Knowledge Incorporation via PriorsThe challenge of specifying an appropriate prior distribution p(x) is unavoidable inBayesian inference. Often this is seen as a drawback of the approach, however the upsideis that all assumptions for a specific model are made mandatory, explicit, and transpar-ent, allowing existing knowledge to influence the inference process without obfuscation.Many sources of information are useful to determine priors, and guidance for definingpriors is a rich topic in the Bayesian statistical literature [190, 206, 229–231].Within this dissertation, several approaches to prior distribution elicitation are lever-aged in later case studies to illustrate various available options. Specific guidance and/orpreferences for selecting between these options is not provided given that specific appli-cation is expected to usefully inform decisions in most cases.• Non-informative priors are a commonly used and disputed approach to Bayesianpriors. The objective is to find a prior distribution that represents a complete ab-sence of preference/knowledge regarding the potential value of some variable. Thesimplest example is that of choosing a prior for a Bernoulli distribution, perhapsmodelling the bias of a coin (characterized by one distribution parameter p withdomain [0, 1]). An informed prior would leverage intuition that a typical coin isunbiased but permit the possibility of a weighted coin, perhaps leading to a normalprior of p ∼ N(0.5, 0.2). A non-informative prior, in contrast, attempts to remaincompletely ignorant of any intuition or historical experience and would use a uni-form distribution: p ∼ U(0, 1). Determining what constitutes “uninformed” quicklybecomes extremely difficult for distributions with infinite domains for parameters,leading to rich discussion of what distributions best represent a fully agnostic posi-tion. An excellent example of research developing non-informative priors to satisfydifferent ideals of ignorance for Weibull distributions in applications for reliability1166.2. Computational Inference Algorithms and Considerationsis provided by Kang et al. [231].• Use of historical knowledge is an ideal approach to prior elicitation, regardlessof the exact source of said knowledge. Typically such sources are challenging toincorporate into alternative reliability analysis frameworks, and so this capability isfrequently touted as a benefit of Bayesian inference [191, 232]. Specific sources caninclude industry standardized guidance (such as that provided in JEDEC’s JEP-122H [49]), data from previous fabrication processes, foundry provided models, orin-field telemetry from existing products.• Expert opinion is a useful alternate source of prior information, whether stemmingfrom intuition or high-level analysis. This method of prior elicitation is difficultto standardize, as human knowledge is rarely expressed in terms of a probabilisticdistribution [230, 233]. Codifying opinions, preferences, and qualitative statementsas mathematical expressions is challenging, and often expert knowledge is withregards to predictive outputs of the model (such as product lifespan) rather thanindividual hyper-latent variables. The significant desire for integration of expertknowledge in fields such as ML to supplement data driven learning demonstratesthat overcoming these challenges is worthwhile [185].• Weakly informative priors provide a balance between the three previous approaches,leveraging some reasonable expectations or knowledge regarding model behaviourwhile remaining non-committal and open to objection [206]. A simple example isselecting a wide-tailed distribution that covers a full order of magnitude, remainingmostly agnostic as to the exact value but expecting a certain overall effect magni-tude of interest (e.g., threshold voltage degradation magnitude is not expected toexceed supply voltage).6.2 Computational Inference Algorithms andConsiderationsWith a hierarchical SPM architecture supporting arbitrary PoF models, closed formexpressions for the full posterior distribution of the hyper-latent variables, p(x|y), aretypically not possible to obtain. Numerical estimation techniques must instead be usedto approximate Eq. 6.1 for all x ∈ X, with each sample x producing a unique inte-gral across the latent variables V . This leads to the use of probabilistic programmingtechniques to achieve CBI, providing an algorithmic framework for defining models that1176.2. Computational Inference Algorithms and Considerationscan be evaluated in multiple ways to compute probabilities and sample random variables.The simplest numerical estimation approach is naive Monte Carlo sampling, drawinguniform random sample values x according to p(x), computing the point estimate forp(x|y) (with secondary interior Monte Carlo sampling to estimate the integral acrossV and obtain p(y|x)), then characterizing the full distribution using the collection of xsamples with the computed p(x|y) values as weights. Though this naive method doeswork, there is a vast body of statistics literature on the design and implementation ofnumerical methods that improve on naive Monte Carlo to provide similarly accurateestimates using far fewer random samples.Theoretically, the most efficient sampling strategy possible is to draw samples directlyfrom p(x|y). On first glance this seems absurd due to its cyclic nature; p(x|y) is theexact distribution that is to be estimated. Very close approximation to sampling p(x|y)is possible, however, through the use of Markov chain Monte Carlo (MCMC) samplingalgorithms that introduce correlations between samples, leveraging what is learned aboutthe posterior from earlier samples to generate more sample points that are likely tomaximize p(x|y). A more formal mathematical definition of MCMC can be found invan de Meent et al. [234], but for the purposes of application to semiconductor wear-outmodels within the SPM architecture only an intuitive understanding is required. Whenusing an MCMC algorithm, sampled values are drawn proportional to the magnitude ofp(x|y) and so can be directly used to characterize the posterior distribution without anyweighting.6.2.1 The No U-Turn SamplerFor CBI in this dissertation the widely used NUTS sampler is leveraged [187]. Thealgorithm is an enhancement to Hamiltonian Monte Carlo [235], which is a physics-inspired MCMC method that generates samples by rolling an imaginary point massaround −log[p(x|y)], the high-dimensional negative log-probability space of a model afterdata y is observed. The potential energy of the mass is minimized when p(x|y) ismaximized, and kinetic energy via a random “kick” is applied at each iteration to forcethe mass to explore the overall topography. An internal numerical solver (leapfrog) is usedto simulate the motion of the mass for a tuned amount of “time”, then the total energyat the end location is compared to the start location to determine whether to acceptor reject the new sample location x. The simulation time L and the size of individualsub-steps ϵ in the leapfrog solver are important tuning parameters for the method thatmust be set manually.1186.2. Computational Inference Algorithms and ConsiderationsThe NUTS algorithm introduces mutations to standard Hamiltonian Monte Carlo toautomatically and adaptively determine L and ϵ by also rolling the mass backwards in“time” and determining when to stop based on when the forward and backward timetrajectories start to converge (i.e., a U-turn). The leapfrog resolution ϵ is adaptivelytuned according to a complex expression related to the average energy near the end ofthe simulation step in comparison to the initial position. The algorithm also acceptsmultiple evaluated points x along the two trajectories rather than only the stoppingpoint.Though each sampling step in NUTS is computationally expensive, it more thancompensates for this through extremely high sample efficiency in comparison to otheralgorithms, especially when the probability space of a model is high dimensional. Itsefficiency leads to its selection for use in this work, where model probability spaces oftenhave high dimensionality due to numerous latent variables needed in V for individualdevices. The degree of efficiency is analyzed via internally-computed MCMC performancediagnostics (effective sample size and split-R̂ [236]) to ensure sufficient sampling duringapplication.6.2.2 Defining Models for Effective NUTS InferenceThere are two important considerations when constructing models for NUTS CBI, re-quired to obtain a log-probability space −log[p(x|y)] that is easy to explore. First is thatall random variables must be continuous to avoid discontinuities/cliffs in the probabil-ity surface that would cause NUTS to misbehave. This is not a general restriction formodels in the SPM architecture (as other MCMC algorithms exist that are effective fordiscrete variables), but for simplicity this dissertation will mostly restrict models for CBIin case studies to use purely continuous random variables so that NUTS can be applieduniformly. A discrete pass/fail output model in Sec. 9.1 is a necessary exception andinstead uses a custom computational inference algorithm described in Sec. 8.4.1.Second is the need to normalize the magnitudes of component random variables in Xand V so that the curvature of −log[p(x|y)] is comparable across each dimension. Evenwith automatic tuning of and trajectory simulation time L and resolution ϵ in NUTS, ifappropriate values for these algorithm parameters are vastly different in some variabledimensions than others then overall sampling performance can become extremely poor.Since the optimal parameter values are related to the magnitudes of the slopes in the−log[p(x|y)] topology, all variables should exhibit similar magnitudes in their derivativesof probability with respect to variable value in the regions of interest [190]. This is morelikely to be true when the range of random variable samples are similar and is closely re-1196.3. Software Framework for Model Construction and Inferencelated to the need for normalization in ML gradient descent algorithms. For hyper-latentvariables, this is achieved through appropriate model specification such that the varianceof each distribution is in the same order of magnitude as N(0, 1), using variable scaling(i.e., affine transformations) where necessary. For latent variables, however, the varianceis entirely dependent on sampled values of the hyper-latents. Thankfully, reparameteri-zation via Eq. 6.3 can be used to express arbitrary normally-distributed latent variablesin terms of standard normals:N(µ, σ) = µ+ σN(0, 1) (6.3)Note that all latent random variables within the introduced SPM architecture arealready centred around zero, thus only the scaling portion is required. Identifying situa-tions where reparameterization will improve CBI performance can be tricky; the followingsection describes how the developed software library automatically handles such cases tominimize technical burden during application of the SPM architecture to semiconductorwear-out reliability studies.6.3 Software Framework for Model Construction andInferenceTo perform CBI in some wear-out PoF model formulated within the SPM architecture,the NUTS algorithm needs to be able to sample variables, compute the log-probabilitiesof sampled values, and compute gradients of those log-probabilities. This necessitatesthe specification of models within a probabilistic programming language (typically builtas an extension on top of an existing general-purpose programming language) that de-fines a set of probability distributions, a means of specifying models, and an approachto performing various non-standard mathematical operations on the model. There aretwo architectural frameworks for such languages: first-order probabilistic programminglanguages (FOPPLs) that use graph representations of models and compile differentmathematical operations on the graph into functions, and higher-order probabilistic pro-gramming languages (HOPPLs) that define models in terms of programmatic functionswith hooks for operations to be applied and values obtained as side effects of functionexecution [234]. Initially, the Python-based FOPPL PyMC [237] was selected to im-plement the inference framework based on its high rate of adoption, readable graphicalmodel definitions (in contrast to most HOPPL languages), and accompanying visual-ization tools. After significant development progress, and though PyMC works well forsimple CBI with NUTS, several technical limitations were identified that make PyMC1206.3. Software Framework for Model Construction and Inferenceextremely difficult to work with when constructing algorithms that inference multiplemodel variants in parallel (functionality that becomes important in Ch. 8).1. Any changes to the size of plates in an SPM (such as changing the number of chipsused in an ALT specification) modifies the graph representation, thus recompilationof model operations (such as sampling values for all hyper-latent variables) mustoccur for every test with unique numbers of lots, chips, or devices.2. Since all parameters are situated within the graph representation of a model, includ-ing stress conditions, changes to test specifications requires either recompilation ofmodel operations or tedious management of variables with shared memory addressesthat compiled operations can refer to but that can also be modified manually.3. Random seeds that determine stochastic behaviour in PyMC models are stateful,meaning parallel use of a single model is difficult to achieve.The noted technical roadblocks of PyMC implementation resulted in a switch to thePython-based HOPPL NumPyro [238]. In NumPyro, a model is defined as a functionwhere nodes in the SPM graphical representation are indicated by special statementsthat provide programmatic hooks for operations to observe and modify how the modelfunction behaves. The language is more conceptually challenging to grasp, but enablesall aspects of a test specification to be provided as inputs to the function and allows forparallel experiments using different random seeds to run on the same model with minimaldifficulty. The resulting Python software library for CBI of the SPM architecture is open-sourced under the Apache 2.0 license and available via GitHub [239].6.3.1 Software Design for Non-Expert UseabilityThe vast majority of engineers are not familiar with probabilistic programming languagesand so cannot be expected to directly define PoF wear-out models in NumPyro. For thisreason the contributed software library provides a layer of abstraction that minimizes theneed for users to interact with the underlying HOPPL. This abstracted interface providesa more conventional method of defining physical models and requesting analyses to beperformed on said models. A representation of the developed software tool structure isshown in Fig. 6.1.Users start by instantiating an empty builder object that they can then add to bydefining new variables with associated distributions and/or functional relationships. In-ternally, the builder object assembles a dependency graph based on variable names as newelements are added; the user can therefore define the model in a completely unordered1216.3. Software Framework for Model Construction and InferenceFigure 6.1: Abstract structural diagram of the software for performing CBI and experi-mental design with custom wear-out models.manner. The available elements to add are hyper-latent variables (with associated priorbeliefs), latent variables, intermediates (named deterministic functions of different ele-ments), parameters, observed variables (with associated device counts), and predictors(similar to observed variables). A distinction between observed variables and predictorsis necessary for conducting various analyses. Observed variables are test measurementssuch as sensor readings that are used as data for inference and so must always havesome stochastic variance (otherwise p(y|x) is zero everywhere except at the exact float-ing point value y), whereas predictors are typically more complex quantities of interestsuch as chip lifespan and can be deterministic. As an example, observed variables may bereadings from the RO-based BTI and HCI sensors contributed in Part I while a predic-tor is commonly the chip lifespan, a time determined by the first sensor to exceed somedegradation limit. Since computing such predictors requires back-calculating time fromdegradation in a PoF model, the parallelized Brent’s algorithm developed in Sec. 5.3 isalso leveraged within the contributed software tool for CBI to enable easy definition ofproduct lifespan predictors.Returning to Fig. 6.1, once a user has defined all elements of their PoF wear-outmodel, a build method is called that translates the engineering-style definition into a1226.3. Software Framework for Model Construction and Inferencecarefully defined NumPyro model function for effective CBI. The method then stores thefunction representation of the SPM and detailed information on all of the function hooksneeded to operate on the model in a Model object. This Model object is then passed toa Manager object. Various reliability analyses can then be performed by the user simplyby calling corresponding methods of the Manager without having to interact with thecomplexities of the underlying custom engine and Numpyro algorithms.6.3.2 Defining the Developed SPM Architecture as a ProgramThe build method of the software tool constitutes a significant technical challenge andso is worth discussing in detail. Three specific challenges must be addressed by theprocedure:1. Ensure all model function hooks/nodes are assigned names that are unique anddescriptive, these names must be tracked and sorted by node type for later use byalgorithms.2. The model function must be defined sequentially according to a constructed depen-dency graph, and dependent elements must have the correct prerequisite programvariables passed as arguments.3. Duplicity dimensions must be managed for all devices, chips, lots, and test batches.The test batch support enables test definitions with multiple sub-tests, though supportfor time-varying stress conditions during each test was not included in the scope of thesoftware tool for SPM inference. Time-varying stress support would require repeatedduplication of large portions of the SPM to obtain observed variables for all conductedmeasurements at each time, with each duplicate being dependent on previous variablesaccording to the time-varying stress simulation approach described in Sec. 5.2. Thisis certainly possible to implement and an important item for future work, but wouldsignificantly complicate the model structure. With the constant stress limitation in mind,the SPM architecture is formulated as a function closure according to Fig. 6.2.The various user-added model elements in a Builder object become programmaticstatements within the functional definition for HOPPL use, indicating that they arehooks/nodes that provide visibility into how the function executes and the likelihoods ofparticular stochastic executions. The formulated model function itself does not providetraditional output (i.e., returning a value); external algorithms influence and examineprogram execution traces to sample nodes, fix them at specific values, and evaluate theirprobabilities of producing specific values.1236.3. Software Framework for Model Construction and InferenceFigure 6.2: Hybrid graphical/functional representation of how wear-out models withinthe SPM architecture are formulated for HOPPL use in the custom inference software.Dependency graph sorting is necessary as intermediate nodes can reference otherintermediate nodes to model higher-level device parameters, circuits, or hardware blocks1246.4. Computational Inference Case Studiesas desired. Each observed and predictor node requires a separate device duplicity plate,as the number of observed instances for each per chip can be unique. One simplificationof Fig. 6.2 is that in the implementation sub-tests may also use unique numbers oflots, chips, or device instances, thus different lot, chip, and device plates are definedfor each test internally. Careful node naming is therefore required to uniquely identifynodes that are redefined for each sub-test and observable variable. Finally, to leveragehardware vectorization, all values within the model function are arrays of up to sevendimensions (devices, chips, lots, sub-tests, plus three batching dimensions for the numberof samples used across the X, V , and Y variable spaces) that require precise orderingand transformations to correctly map operations to values. The full model formulationmethod can be viewed in the provided software library for readers interested in how thesecomplexities are handled [239].6.4 Computational Inference Case StudiesPut together, the SPM architecture and software framework for CBI allow for complexPoF model behaviours to be learned from observed data. Demonstrations of the novelcapabilities of the SPM architecture, software, and supplementary contributions on epis-temic uncertainty quantification and lifespan metrics can be found in both the morecomprehensive case studies towards the end of this dissertation in Ch. 9 and in severalbrief case studies presented here. The studies in this section focus more on the nuances offrequentist versus Bayesian inference approaches. Graphical representations of the mod-els are only shown in the Ch. 9 studies, which are more extensive in scope and discussion,and implicit log domain transformations are used for some study models (see AppendixB for details).6.4.1 Characterizing Group Variability in Generic Failure DataThe first inference case study scenario is constructed to exhibit a simple issue raised byWu et al. [170] and then examine the utility of multilevel variability modelling whenanalyzing such generic failure data exhibiting lot-to-lot variations using a two-parameterWeibull distribution. A simulated data set is generated (also from Weibull distributionsto avoid introducing model-based error to the study) for three independent lots withsimilar but stochastic parameters. A conventional MLE fit with confidence intervals,shown in Fig. 6.3, does not account for lot-level variability and so the true distributionsof individual lots can quite easily fall outside of the 95% confidence interval.1256.4. Computational Inference Case StudiesFigure 6.3: Conventional MLE fit of Weibull failure data exhibiting group-level variability.The 95% confidence interval fails to bound individual lot failure distributions. © 2025IEEE [6].Existing work that identifies this issue of group-level variability shifts towards a proba-bilistic approach, recommending superpositions of individual MLE fits [170] or modellingthe fit parameters with additional distributions [240]. The SPM architecture realizes a fullprobabilistic formulation, enabling Bayesian inference of variability at different groupinglevels to effectively characterize these effects without having to modify the methodologyused to inference the model. Capability to capture group-level variability is shown inFig. 6.4, where the posterior likelihood of a lot that was not effectively characterized bythe MLE fit matches up well to its true likelihood under the generative model (listed inFig. 6.3).Prior beliefs for the hyper-latents in the probabilistic Weibull model are lightly in-formed Gaussian distributions, resulting in the light blue predicted distributions in Fig.6.4 that are more or less opaque proportional to their likelihood under prior beliefs. Thedark blue samples show the posterior after CBI on the simulated data, with reducedepistemic uncertainty according to Bayes’ rule from Eq. 6.1. Inference via the developedsoftware library with NUTS sampling takes approximately 5 seconds on a six-core Intel©i5-12400 processor.1266.4. Computational Inference Case StudiesFigure 6.4: Prior and posterior predicted failure distributions of a Weibull model withinthe SPM architecture, demonstrating effective characterization of group-level variabilitybehaviours. © 2025 IEEE [6].6.4.2 Inference on Real-World NBTI DataThe second inference case study moves to PoF models, analyzing some of the experimentally-observed data from the contributed RO-based sensors to characterize NBTI. Epistemicuncertainty quantification and historical knowledge integration features of the SPM archi-tecture are highlighted in particular. The empirical BTI model from Eq. 1.1 is formulatedwithin the SPM architecture, introducing both device and chip-level variability to Vthdegradation. Lot-level variability is excluded since all four TC1 chips used to collectthe data were from a single production run. The source document recommending theBTI model, JEDEC’s JEP-122H, Sec. 5.3.2 [49], also states observed ranges for the fitparameters of the model in historical semiconductor processes. Within non-Bayesian sta-tistical frameworks, this information is valuable for post-hoc sanity checks of model fitquality, but is not easily used to guide the fitting process. In the proposed methodology,however, this historical knowledge can be explicitly used to guide the inference processtowards reasonable values of parameters. Prior distributions for the mean values of theBTI model parameters are made sure to encompass the stated ranges from JEP-122Hwithout extending too far beyond, and moderate weakly informed priors, as discussedin Sec. 6.1.2, are used for device and chip variance hyper-latents to expect some, butnot excessive, variability. Aside from the industry-provided prior knowledge used in this1276.4. Computational Inference Case Studiesstudy, historical data used to elicit priors for Bayesian inference can also come from ex-isting test data, such as the database of test data used for wafer production tests in workby Chien et al. [169], or simple intuition of reliability bathtub curvature, as used by Dateand Tanaka [186]. With the model prepared, observed degradation after 1000 hours ofHTOL-like stress for the 16 standard NBTI variant sensors is used to inference the PoFmodel. On a six-core Intel© i5-12400 processor, CBI via NUTS requires just under 30seconds. Resulting expected prior and posterior degradation curves are shown in Fig.6.5.Figure 6.5: Prior and posterior degradation curve distributions for the probabilistic NBTImodel using experimental data from the contributed RO-based sensors for inference. ©2025 IEEE [6].After model inference conditional on accelerated test data, the epistemic uncertaintyof the model hyper-latent variables decreases. In other words, the hyper-latent distribu-tions tighten up according to which values are more likely given the data. The reductionis visualized in Fig. 6.6 for some of the model hyper-latents, with quantified valuescomputed using the interpretable LDDP entropy formulation from Sec. 4.6.The posterior distribution of the ςA0 hyper-latent variable in Fig. 6.6, encodingchip-level variability of the BTI scaling parameter, indicates that noticeable chip-levelvariability is present in the degradation data. This confirms what can be visually intuitedfrom Fig. 6.5, where sensors on the crimson-coloured chip all exhibit higher degradation1286.4. Computational Inference Case StudiesFigure 6.6: Hyper-latent prior and posterior distributions for the NBTI model comparedto show epistemic uncertainty reduction after inference. Numeric Hφ values are includedto quantify the reductions. Revised from [6].in comparison to the overall population. Another comment is regarding the low uncer-tainty reduction in the time exponent parameter µn (also observed in the µα hyper-latentvariable, though not shown), which is related to the limitations of using test data from asingle stress point in the space of temperature, voltage, and time. Intuitively, the degra-dation behaviour dependent on each stress condition can only be deduced from multipleobservation points in this space; with only one point inference mostly affects parameterswith higher prior uncertainty, in this case µA0 and µEaa . Even though inference leadsto significant uncertainty reduction here, it is fair to say that the data is not sufficientlyrich in quantity or variety to effectively characterize all the model parameters. Cer-tainly overall posterior epistemic uncertainty is still high, and thus further inference onadditional experimental data would be recommended before using the model to predictin-field NBTI degradation. Designing optimized accelerated tests to obtain efficient andinformative data sets for model inference is the primary focus of Part III.6.4.3 Inference on Sparse TDDB DataThe last brief study in this section illustrates use of the developed uncertainty-awarelifespan metrics, and how a Bayesian framework for inference can prevent overfitting whentest data sets are small. A power-law TDDB model according to Eq. 1.3 is implemented1296.4. Computational Inference Case Studieswithin the SPM architecture, where lightly-informed priors are placed on the hyper-latent variables for to, a, and b mean and variance (no chip or lot-level variability). Onlytemperature dependence is investigated here, so a more informed tight prior is placed onthe voltage dependence parameter n.A sparse data set is generated by simulating data from an alternative but stillcommonly-used TDDB model, the E-model [241]. Failure times are sampled under threeaccelerated temperature conditions with some minor lot-level aleatoric uncertainty tointroduce some model error to the probabilistic predictions. Computational Bayesianinference on the power-law probabilistic model and an MLE fit of an E-model are per-formed to learn from the data for preliminary prediction of reliability under a 330K fielduse scenario (thus model error is only present in the Bayesian approach). The resultingfits across temperature are shown in Fig. 6.7, while the predicted lifespan distributionsat field use temperature are shown in Fig. 6.8.Figure 6.7: Different inference approaches to learning from sparse TDDB data. Stochas-ticity of the data leads to high estimate variance in the MLE procedure that is mitigated inBayesian inference through prior information and modelling of uncertainty as to aleatoricvariability.The aleatoric variability in the test data, accentuated by the small sample sizes,results in the MLE fit producing a mean predictive curve that can be misleading if takenat face value, and a 95% CI on the field use prediction that effectively indicates the rangeof likely values for mean lifespan but does not meaningfully convey risk regarding theleft tail of the distribution. It should be pointed out that the base predictive MLE CI1306.4. Computational Inference Case StudiesFigure 6.8: Lifespan metrics generated from the MLE fit and CBI on sparse TDDB data.Different information regarding the likely true behaviour is conveyed by each metric andmethod.as shown in Fig. 6.8 does not account for aleatoric uncertainty. Additional fits wereperformed with explicit uncertainty equivalent to the that of the probabilistic model,however this caused the 95% CI predicted interval to expand drastically, producing amuch larger interval than the Q95%-HDCR that extends to zero. Careful post hoc tuningof the aleatoric uncertainty was required to achieve a similar bound as the Q95%-HDCR.The additional uncertainty input to the MLE fit procedure ends up in some ways beingcomparable to a prior belief itself (but is expected to be exact rather than an estimate).With the developed SPM architecture, aleatoric uncertainty is directly modelled and issubject epistemic uncertainty itself (also assumptions of normality are avoided), providinggreater control and transparency as to lifespan predictions.With relatively uninformed prior expectations, a sparse data set, and various sourcesof aleatoric uncertainty in the SPM architecture, the Bayesian posterior predictions aregenerally conservative in ensuring the Q95%-LBCI and Q95%-HDCR do not overfit tothe test data and still cover the range of possible underlying model behaviours. Draw-backs of the Bayesian approach are the subjectivity introduced by the prior beliefs, themore complex model specification, and the greater technical complexity required for CBI.However, as previously discussed in Sec. 6.1.2, prior subjectivity is often a benefit ratherthan a detriment in situations where reasonable prior knowledge can be identified, suchas in real-world engineering contexts. The developed software library is intended to mit-1316.5. Part II Conclusions and Future Workigate the other two drawbacks through abstracting away and automatically managingmuch of the probabilistic modelling and CBI complexity.The defined uncertainty-aware metrics based on this Bayesian inference posteriorcapture key summary statistics of the posterior predicted lifespan distribution. For qual-ification, it can be seen that the Q95%-HDCR is less appropriate than the Q95%-LBCIsince it accounts for the right tail of the distribution, resulting in an overly conservativelower region bound where only around 2.5% of parts would be expected to fail in advance.The Q95%-LBCI captures the risk of early failure more effectively. The Q95%-HDCR ismore useful for identifying expected failure time, however, as the lower bounded intervalprovides no indication of the distribution mode, mean, variance, or shape.6.5 Part II Conclusions and Future WorkEffective analysis of semiconductor wear-out data is complicated by the presence of mul-tilevel variability effects and epistemic uncertainty. These complications can result inreliability predictions which may not be accurate for certain fabrication lots or processcorners and that do not clearly reflect the level of confidence that can be placed in them.Prior research does partially address these challenges, but the statistical approaches usedoften struggle to generalize across different models of reliability, introduce implicit as-sumptions, and do not provide a means of quantifying model uncertainty as new testsare conducted over time. Motivated by the need to effectively characterize multilevelvariability for atomic-scale semiconductors and explicitly measure predictive uncertaintyfor high reliability applications, a novel probabilistic modelling architecture was devel-oped and a Bayesian statistical framework adopted as a basis for effective analysis ofarbitrary semiconductor PoF models. The fully computational solution approach withhierarchical model structure enables numerous enhancements including improved uncer-tainty reasoning and arbitrary model support over the limited literature on Bayesiansemiconductor reliability prediction. For high reliability markets, these enhancementsaddress the research gap of poorly quantified epistemic uncertainty in existing meth-ods for reliability prediction, while the Bayesian framework allows for easy historicalknowledge incorporation to avoid excessive testing when trying to meet strict LTR re-quirements in the presence of prior information. For semiconductor process innovation,the advanced multilevel variability modelling approach improves over identified variabil-ity analysis techniques in existing work [169, 170, 186], supporting the need to carefullymodel aleatoric uncertainty sources in order to maintain yield and design margins assemiconductors scale further.1326.5. Part II Conclusions and Future WorkThe developed probabilistic modelling structure is integrated into software tools forboth generative modelling and inference that automatically handle many of the technicalchallenges of working with probabilistic models and CBI, making the analysis approachaccessible to non-expert reliability engineers. Supporting Bayesian lifespan metrics andinterpretable uncertainty measures are introduced to further support these analyses. Ad-vantages of Bayesian statistical frameworks, software tool functionality, and the novelcapabilities of the SPM architecture in conducting semiconductor wear-out simulationand inference are evidenced through case studies.An important subsequent research direction, following the contributions introducedin this part of the dissertation, is to look at the problem of identifying what predicted re-liability and degree of uncertainty is acceptable for a given application, particularly whenhigh reliability is required. The final portion of this dissertation, Part III, investigatesin particular the resulting challenge of designing ALTs that can be expected to provideenough useful data to ensure that, following CBI, a posterior model will have sufficientlylow uncertainty to meet relevant reliability requirements. There are several future workdirections that are not addressed later in the scope of this research, however, and thatare valuable to consider. First are technical limitations of the software tools that weretoo expensive to implement in terms of time and technical challenge but are certainlyfeasible, such as time-varying test and multiple time measurement support for CBI. Con-sideration for model uncertainty in reliability predictions analyses is also important butwill require methodological innovations. Use of model ensembles and cross-model lifespanmetrics are identified as potential tools to tackle this challenge. Finally, the open-sourcesoftware tools developed for simulation and inference are still relatively sparse in termsof features for ease of use and documentation to guide non-experts through analyses us-ing the contributed SPM architecture. Maturation of these tools to provide graphicalinterfaces, improve ease of use, identify user errors, and improve stability is expected tobe by far the most important future work avenue if suitability for industry adoption is apriority.133Part IIIPredictive Bayesian ExperimentalDesign for Optimized Long-TermReliability Qualification134Chapter 7Semiconductor Accelerated LifeTest Design OptimizationWith the tools of probabilistic modelling, CBI, uncertainty-aware lifespan metrics, andper-mechanism on-chip sensors available, it is possible to run an accelerated test ona new product containing wear-out sensors, then infer a candidate PoF model fromthe obtained results to compute figures of merit regarding LTR. A procedure based onthese contributions already provides unique value over existing approaches, as previouslydetailed, in terms of being able to effectively inference on per-mechanism probabilisticmodels, incorporate prior information, model multi-level variability effects, and avoidoverconfidence in predictions when limited data is available.Perhaps in the context of some low-cost consumer products this procedure can becarried out naively, but when test costs (particularly time) are significant burdens and/orhigh reliability is demanded by a target market, strategic design of this procedure isrequired to strike a balance between risks of unnecessary costs and insufficient testing.Recall two primary motivations for this research: the market need for high-reliabilityproducts that meet specified reliability targets, and the demand to reduce the time andresource costs of accelerated testing. From these objectives questions arise related to thisrisk balancing challenge:1. What is the required LTR of the target markets?2. How much can the cost of the accelerated tests be reduced?3. Is it possible to ensure the accelerated testing provides sufficient information toevidence that the product meets the required LTR targets?Notice that the second and third questions lead to conflict, as longer and larger testsgenerally provide more information to evidence that reliability requirements are metwhile shorter and smaller tests enable cost savings. This specific challenge is highlightedin the IEEE IRDS More Moore 2024 [10], which states that, “The needs are clearly many,but a specific one is the optimal reliability evaluation methodology, which would deliver1357.1. Prior Literature on Accelerated Life Test Designrelevant long-term degradation assessment while avoiding excessive accelerated testingthat may produce misleading results.”Within the current industry standardized framework for LTR qualification, describedin Sec. 1.6, it is difficult to capture the abstract idea of “information obtained froma test” in any quantifiable manner, thus one dimension of the identified optimizationproblem is poorly defined. The epistemic uncertainty quantification approach seen whenperforming CBI with the introduced SPM architecture, in contrast, provides a foundationfor optimization of test information via entropy. The remainder of this dissertation willpresent and evaluate a methodology for LTR qualification built upon the presented novelsensors and Bayesian statistical techniques that allows reliability engineers to optimizeaccelerated tests to meet metric targets and conduct risk-based analysis of proposedtest plans. This provides a potential avenue to a future industry arrangement wherehigh reliability market regulators can mandate LTR requirements without encounteringoverwhelming pushback by providing effective qualification risk and cost managementtools.7.1 Prior Literature on Accelerated Life Test DesignDespite the significance of the optimal reliability evaluation challenge in enabling up-coming semiconductor processes, only a few works could be identified that address thissub-problem within the field. Three lines of research were found that point out deficienciesof single stress condition tests and propose alternative testing schemes based on multiplestress test groups. A multi-temperature operating life testing scheme is introduced byBernstein et al. to enable wear-out qualification in the presence of multiple mechanisms[84]. Their method is shown to be able to identify changes in the significance of differentmechanisms under different stress conditions. Work from Tsai et al. also introducesmulti-stress test groups, but instead leverages this strategy to perform system-level lifes-pan extrapolation without the use of assumed acceleration factors by fitting the lifespaninferred for each incremental stress condition to a regression curve to predict field-uselifespan [176]. Although these first two approaches identify and alleviate the problem oftrying to learn stress-dependent reliability behaviours from a single set of stress condi-tions, their proposed alternative schemes are based on human judgement and intuitionrather than a quantitatively justified approach to selecting stress conditions. The thirdline of work by Wu et al. addresses the same challenge as Bernstein et al., attemptingto find appropriate stress conditions to observe individual reliability mechanisms [174].They introduce a mathematical framework for selecting these stress conditions based on1367.1. Prior Literature on Accelerated Life Test Designminimizing the variance of a Weibull parameter estimate from simulated test data, fol-lowing principles of a more formal design of experiments (DoE) framework but withoutan explicit DoE methodology. The relatively ad hoc approach does lead to potential flawsin the validity of the optimality criterion and consideration of different experimental out-comes (topics discussed in more detail in later sections), and the application is focused ontest design for isolating mechanisms rather than overall LTR qualification. Despite this,their research does represent the most relevant existing work in the semiconductor liter-ature as a point of comparison to the experimental design strategy for ALTs developedwithin this dissertation.Individual mechanism characterization using DoE is briefly discussed in JEP-122H,however no formalized framework is provided [49]. Only one work in the semiconductorliterature was identified that uses formal DoE for test planning, research by Maricauand Gielen [218]. They use DoE techniques to optimally select transistor parametervalues to simulate, such as channel width, to build out a map of BTI and HCI agingbehaviours across different circuit configurations. Though the approach is used for sim-ulation and to optimize test structures rather than the test designs themselves, it doesdemonstrate existing use in the field. All remaining surveyed works to be discussed arefrom the broader reliability engineering and statistics literature on DoE, also known asexperimental design.7.1.1 Formalized Design of Accelerated Life TestsExperimental design, or DoE, is a field whose origin is attributed to R.A. Fisher whereit was developed for applications in agricultural science [242]. Typically, the objectiveis to identify the optimal design dopt within a space of possible designs d ∈ D for theexperiment/test that maximizes the expected value of utility U of said experiment acrossthe distribution of possible experimental outcomes p(y|d) that may be observed:dopt = maxd[Ep(y|d)[U(d,y)]] (7.1)Classical examples of a definition for utility include parameter estimate variance min-imization, or maximization of Fisher information. Although there is broad historicaldevelopment and a wide variety of applications for experimental design, from medicalstudy design to multivariate user testing, the scope of this literature survey is limited toworks directed towards the accelerated wear-out test design application being addressed.A general introduction to standard frequentist DoE techniques is provided by D. C. Mont-gomery [243]. Recent work on frequentist experimental design for optimal utility ALTis adapting established methods for unique considerations, such as research by Pei et al.1377.1. Prior Literature on Accelerated Life Test Designlooking at when series of products are to be qualified with a common test [244]. Thistype of situation leads to a definition for U that must consider the combined utility of atest across individual products, such as the maximizing the minimum test utility acrossa set of products.7.1.2 Reliability Demonstration Tests and Cost AwarenessAs ALT design is typically leveraged for engineering applications, the majority of liter-ature on generalized ALT design is contained in the long-standing sub-field working onenginering reliability demonstration tests (RDTs). This sub-field still follows the generalobjective of utility maximization, however the specific definition of utility also begins toaccount for the test cost and the idea of information suffiency rather than informationmaximization. Generally, RDTs are applicable when one need merely evidence that thereliability will be high enough for a given in-field use case.An explanation of RDT design is given by HTOL, which is itself a demonstrationtest based on early principles [78]. Accelerated stress conditions are selected from expertopinion with an associated acceleration factor to extrapolate to use conditions, then sta-tistical methods are used to optimize the number of samples required to meet a requiredconfidence interval target (90% for HTOL). If the test completes and zero samples havefailed, then the reliability of the overall population (the percentage of surviving units atsome target time, which is 99% for HTOL) can be assumed with the specified degree ofconfidence. In this situation the utility U is a balanced optimization between sufficientconfidence and sample size cost. An analytic solution to this utility optimization prob-lem provides the minimum number of samples required to meet the confidence threshold,thus minimizing the sample size cost. Recalling the discussion in Sec. 1.6, note that thedegree of confidence in the value of the acceleration factor is not considered as part ofthe HTOL statistical framework.Modern work on frequentist RDT techniques looks at special application consider-ations, such as Yadav et al. that investigate how to identify critical components andallocate reliability budget within a larger system [245], Ferna´ndez et al. who investigatehow overdispersion of measured values in comparison to expected variability can impactthe optimal RDT design [246], or Grundler and Dazer [191, 247] who consider utility asthe probability of an RDT passing when run for a given product. A major limitationof all of these works is that they rely on simple models of failure, such as Weibull orBinomial distributions, due to the fact that the choice of underlying model affects themethodology. Analytical solutions for parameter estimates are used to relate predictiveconfidence and sample size, which for more complex models may not exist.1387.1. Prior Literature on Accelerated Life Test DesignRegardless of the specific enhancements made to an RDT optimization methodology,the tests themselves suffer from significant drawbacks that have already been discussedextensively in prior chapters. These include the lack of an easy method for prior knowl-edge incorporation, the lack of consideration for confidence in the acceleration factor,no consideration for varied customer use conditions, an explicit avoidance of testing toproduct failure, and only predicting reliability for a single target point in time [248]. Asthe name suggests, an RDT is designed to evidence a sufficient survival rate for productrelease, and is not optimized for gaining knowledge about the stress-dependent degrada-tion and failure behaviours that can allow for modelling product lifespan across variedin-field use conditions and markets. For this reason, tests that are instead designed toinduce failures and degradation for effective inference of PoF models are more valuablefor high reliability applications and upcoming fabrication nodes. In these demandingsituations individual physical mechanisms may be aggravated under different stress con-ditions and strict requirements must be met across varied use cases under tolerance forhigh variability. The explicit consideration for practical engineering costs as part of thedefinition of test utility, however, is a valuable element from the RDT design literatureto learn from and apply to more general experimental design methods.7.1.3 Bayesian Accelerated Life Test DesignBayesian (optimal) experimental design (BED/BOED) shares most of the same generalprinciples as in frequentist frameworks, with the core differences being that test utility istypically derived from desirable qualities of the inferred posterior distribution of a modelrather than based on the variance of parameter estimates, and that the introduction ofprior knowledge can impact the optimal design. A historical overview of BED is providedin Sec. 3 of DasGupta’s “Review of Optimal Bayes Designs” [249], while a good primeron the underlying mathematical framework can be found in Chaloner and Verdinelli’s“Bayesian Experimental Design: A Review” [250]. Although BED has existed and hadits potential methodological benefits touted for many decades [251, 252], adoption hasbeen historically limited for the same reasons as CBI for reliability prediction; analyticsolutions for inference often do not exist for more complex models and so computationallyexpensive numerical estimation techniques are required. Computational methods forBED are very recent and less mature than for the sub-problem of CBI, but offer thesame potential for application of BED to arbitrary complex probabilistic models.To work with the SPM framework for multilevel variability and epistemic uncertaintyanalysis of PoF models, BED is necessarily adopted in this research work over frequentistincarnations. Computational BED specifically is required to generalize BED methods for1397.1. Prior Literature on Accelerated Life Test Designarbitrary models, but incurs the host of challenges related to ensuring representativesampling and algorithm performance seen previously in the Ch. 6 discussion on CBIsampling techniques. As a result, computational BED is as deeply entrenched in the fieldof computer science as in statistics; a good overview of the state of the art is provided byRainforth et al. [195]. Numerical estimation considerations for the BED approach thatwill be described later in this chapter is the focus of Ch. 8, the remainder of this chaptersimply assumes that a reasonable numerical estimate for the model posterior distributioncan be obtained.Extensive survey yielded numerous works on BED for ALT design in general relia-bility engineering application (no works could be identified that target semiconductorALTs). The first work in BED for ALT focuses on the RDTs discussed in the previoussubsection. Wilson and Farrow [253] introduce a very similar approach to RDT opti-mization as Grundler and Dazer [191], maximizing the probability of an RDT passingexcept using a Bayesian “assurance” perspective for the underlying inference problem(including use of computational MCMC methods for CBI, but an analytic approxima-tion for integration across possible observations and test designs). A full computationalapproach is pinpointed as an area for future work by the authors. The distinction be-tween RDTs, assurance tests, and ALTs (the focus of this work) is well explained inCh. 10 of Hamada et al. [192]. Ryan et al. also consider assurance testing but applyit to multi-step degradation tests for accepting or rejecting production lots [254]. Thistype of test is somewhat tangential to ALT, but the work is worth mentioning due to itsconsideration of risk in test utility and its use of MCMC methods for posterior inference(though once again analytic solutions are used to integrate across the range of possibleexperimental outcomes).Earlier works on general analytic ALT design optimization within a Bayesian frame-work range from maximizing Fisher information for log-location-scale reliability models[248] to providing a variance minimization strategy for exponential models [255] to con-sidering sample cost versus information gain optimization for exponential models [256].More recent approaches relax the model limitations of fully analytic approaches andleverage computational techniques for posterior inference, though typically the evalua-tion of ALT designs across the range of possible observed test results is still based onanalytic approximations or assumptions. These works tackle problems such as Weibullfailure distributions with utility defined in terms of information maximization [257], lin-ear degradation models with measurement cost to information maximization optimization[211], and Weibull distributions when the possibility of warranty rebate costs are consid-ered as part of the test utility [258]. Research by Lee et al. is significant for being the only1407.1. Prior Literature on Accelerated Life Test Designidentified example of ALT design in the literature that incorporates a PoF model, usedto characterize fatigue in polymer composites [210]. Notably, the authors also look at thelower quantiles of predicted lifespan, equivalent to considering the Qx%-LBCI metric,and the improved quality of their sequential test designs is evidenced in comparison todesigns obtained through non-Bayesian methods.Finally, Hong et al. [259] and Li et al. [260] provide the only identified examples of fullsampling-based BED for ALT design. Their approaches use custom-developed algorithmsspecific to their use cases and are restricted to log-location-scale and inverse Gaussian fail-ure distributions respectively, but demonstrate how fully computational BED can disposeof assumptions necessary for analytic ALT design methods to operate. A fully numericalapproach leads to more robust optimization results given sufficient computation. Futurework mentioned in the Hong et al. article also further motivates the research conductedtowards this dissertation, specifically mentioning the desire to work with models contain-ing multiple failure mechanisms and with definitions of test utility that simultaneouslyconsider information, cost, and constraints.7.1.4 Situating the Developed Accelerated Life Test DesignFrameworkSummarizing the presented literature survey, different fields have effectively addressedparts of the overall solution required for semiconductor ALT design using computationalBED. The semiconductor community identifies the challenges of multiple failure mecha-nisms but has not yet applied formal experimental design techniques to the field, whilethe general reliability engineering statistical community provides risk and cost-awaredefinitions of utility but rarely considers the specific physics of an application. The al-gorithms community, discussed in Ch. 6 and the next, understands the challenges ofeffective sampling and generalization but adopts simplistic definitions of test utility. Thework presented here brings contributions of all three fields to application, providing afirst general framework for PoF-based semiconductor ALT design.The BED framework developed through the remainder of this chapter leverages andcombines many of the risk- and cost-aware utility definitions seen in the varied workson ALT experimental design in the general reliability engineering statistics literature.Computational algorithms are introduced in Ch. 8 to evade the need for analyticalsolutions normally seen in the literature, enabling arbitrary changes to reliability modelsand utility definitions without modifying the underlying approach. Finally, this workfocuses on semiconductors specifically, leveraging the custom SPM framework to workwith PoF models that contain multiple competing degradation and failure mechanisms.1417.2. Information Gain in Computational Bayesian Experimental Design7.2 Information Gain in Computational BayesianExperimental DesignWithin the computational BED literature, the most prevalent measure of utility is ex-pected information gain (EIG), with the metric of information gain (IG) defined mathe-matically as:IG(y, d) = H[pr(x)]−H[po(x|y, d)] (7.2)Recall from Eq. 4.3 that H is the Shannon information entropy of a joint variabledistribution, in this case the prior and posterior distributions over the hyper-latent vari-able space X. These are explicitly indicated by the subscripts r and o respectively toaid readability going forward. The interpretable LDDP entropy formulation introducedin Eq. 4.5 can also be used for H, however the difference expression reduces to an iden-tical result for IG(y, d). Notice that the posterior distribution is now conditional on thespecific test design d as well as the observed data y. Test utility is then defined to be theexpected information gain over the full distribution p(y|d) of possible observations thatmay result from the test:EIG(d) = Ey∼pr(y|d)[IG(y, d)] (7.3)It is worth noting the relationships between the EIG formulation of expected utilityand experimental optimization objectives in related fields. First, EIG is the Bayesiananalog of D-optimality in the frequentist DoE alphabetic optimality criteria related toparameter estimate variance reduction [261] and is also effectively the same as the mu-tual information between the variable spaces X and Y for a specific d. Second, theKullback-Leibler divergence, commonly used to formulate loss functions in deep learningand variational inference applications, takes a very similar mathematical form in mea-suring relative entropy between two distributions [207]. The divergence could also beused in place of IG, but its asymmetry and slightly more involved computation makes itless desirable as a utility measure in comparison. Fisher information is closely related aswell but is defined less generally for arbitrary distributions and so is more challenging tocompute for arbitrary wear-out and failure models [262].Informally, computational BED based on EIG as utility identifies which consideredtest design d maximizes the average reduction in uncertainty. In many contexts wherethe goal is simply to learn as much as possible about a structured probabilistic model,EIG as an optimization objective may be perfectly sufficient. Within the context of en-1427.2. Information Gain in Computational Bayesian Experimental Designgineering design and risk analysis, however, the introduction of regulatory requirementsand potential for significant losses if testing is insufficient demands a more sophisticatedformulation of utility than a one-dimensional maximization viewpoint. Certainly a higherEIG is valuable in the target application considered, but given market compliance andhigh costs of product launch delays, it is of greater importance to maximize the proba-bility that the test yields data that allows for any imposed requirement threshold to besurpassed. In other words, the goal is to minimize the risk of having to conduct furthertests. An approach that incorporates multiple conceptions of utility and a variety ofsummary statistics must be devised to address this application complexity. Sec. 7.4 willaddress the design of a combined utility measure; within the scope of this section theobjective is to propose the component measures that can be feasibly estimated within acomputational BED framework. The measures will then later be considered in concert toform a reasonable overall optimization objective. Note that the time and resource costsof a given test design are crucial components of BED but will only be discussed later onas they are well defined and can usually be determined based on the test definition itselfwithout any need for computational estimation (though see the study in Sec. 9.2 for anexception).7.2.1 Auxiliary Information Gain StatisticsConsider a simple alternate summary statistic based on the distribution of IG across allprior-expected test observations in pr(y|d). The variance of information gain (VIG) canbe defined according to Eq. 7.4.VIG(d) = Vy∼pr(y|d)[IG(y, d)] (7.4)This statistic begins to include some idea of risk when used as part of a utility defini-tion. Minimizing VIG essentially optimizes for a test that provides a similar informationgain regardless of the “true” underlying system behaviour, thus reducing the unpre-dictably of the test outcome. The measure has some intuitive underlying meaning, butis difficult to place bounds upon. An estimate of how “unpredictable” a proposed testdesign is in terms of the range of possible observations is useful to know, but the tolerableVIG magnitude is unclear. It is possible to co-optimize to find a test that maximizes EIGwhile minimizing VIG, but the relative importance of these quantities and their inter-pretation is vague without an idea of how much IG is actually needed. Neither statisticis thus particularly useful as a primary measure of utility, but they can provide value inthe comparative analysis of otherwise equal test designs.1437.2. Information Gain in Computational Bayesian Experimental Design7.2.2 Threshold Information Gain as a Risk MeasureThe first application complexity introduced is the concept of “sufficient information”mentioned at the beginning of this chapter. When testing purely for compliance, thereis no benefit to obtaining additional information beyond that which is needed to meetimposed regulatory requirements. Framed in an engineering context, selecting the leastcostly ALT that is still sufficient to qualify a product is preferable to one which maxi-mizes expected utility but incurs additional testing costs. Similarities to RDTs can bedrawn here, as a demonstration test also aims to show sufficiency with minimal cost(though sufficiency is now with respect to learning enough about a PoF model to makeconfident LTR predictions rather than a comparative statistical sample under differentstress conditions).This complexity, rooted in the cost-aware tradeoffs of engineering design choices,reveals a deficiency in the canonical experimental design objective stated in Eq. 7.1. Theoptimal test dopt is no longer defined in terms of maximization, but instead satisfaction.The most obvious solution to this discrepancy is to revise the objective, but an alternativeapproach (that requires less modification of the overall DoE framework) is to insteadcomplicate the definition of utility. Consider the theoretical target “threshold informationgain” (TIG) defined in Eq. 7.5.TIG(X,m) = H[pr(x)]−H[pt(x)] (7.5)This quantity denotes the entropy difference between the prior, H[p(x)], and the en-tropy of the hyper-latent variable space distribution at some identified threshold, denotedH[pt(x)], past which a target LTR metric m is satisfied (note the independence with re-spect to d and y). An astute observation is the unclear relation between m and H[pt(x)].This issue will be discussed momentarily, but for now assume that given a value for m thetarget entropy can be computed or reasonably estimated. From the TIG, well definedstatistics to embed test risk into the utility U can be proposed, such as the probabil-ity that the observed data from a conducted test yields an IG equal to or greater thanthe TIG. This summary statistic can be denoted the “IG pass probability” (IGPP) anddefined for use in utility according to Eq. 7.6.IGPP(d) =∑y∈Y ′ pr(y|d)∑y∈Y pr(y|d), Y ′ = {y ∈ Y : IG(y, d) ≥ TIG(X,m)} (7.6)1447.2. Information Gain in Computational Bayesian Experimental DesignThis definition of utility now resembles some of the optimization criteria seen in theliterature, including the probability of test pass [191] and assurance statistics [253, 254]used for RDT and production test experimental design. An interesting interpretation ofthis utility is to view an ALT as a hypothesis test for whether product reliability meetsthe requirement m, with the IGPP as the corresponding statistical power of a particularALT design [192]. This interpretation of an ALT as a hypothesis test is in line with thegeneral objectives of RDTs and Bayesian assurance tests such as HTOL, but with ALTsthe objective is to learn a sufficient amount about an underlying physical process and sothe concept of a hypothesis test is somewhat less applicable.7.2.3 Limitations of Information Gain in Arbitrary Model ContextsThe unclear assumed method to determine the target entropy from m is now examinedand shown to be impossible to reliably obtain. There are two issues that prevent directcorrespondence of hyper-latent entropy to uncertainty-aware metrics. First is the effect ofthe “true” LTR on TIG. Consider the incredibly simple model Y = X ∼ N(µx, σx), witha reliability requirementm of Y ≥ 0 for 90% of samples and a prior µx = 3, σx = 3 (thus aprior Hφ = 11.73). If the “true” value of µx is 3, then σx must be ≲ 2.34 (Hφ(X) = 11.48nats, TIG = 0.25 nats). However, if µx = 1, then σx ≲ 0.78 (Hφ(X) = 10.38 nats, TIG= 1.35 nats), and furthermore when µx ≤ 0 then the requirement can never be met. Thiscorresponds to a dynamic TIG that may not even exist ∀µx.The second issue is non-unique posteriors that meet the TIG in models with Xconsisting of two or more variables, even if the location parameter of each hyper-latentis fixed. Consider the variance within a second simplistic model, Y = 100X1 −X2. Thetotal entropy reduction of a test providing an IG of 1 nat can be divided among thehyper-latent variables in different ways, such as a reduction of 1 nat to the entropy ofX1 but no change in X2, vice versa, an even reduction of 0.5 nats to each, or many otherintermediate situations. The variance of Y is far more sensitive to changes in the varianceofX1 thanX2, however, thus some of these divisions will have a disproportionate effect onthe output variance in comparison to others. Even when test IG and hyper-latent variablemodes are fixed, therefore, the TIG does not in general lead to predictable thresholds.When the variable locations are no longer fixed and model complexity is introduced, theeffects of obtaining some given test IG on a system are unpredictable.These problems extend to the simpler EIG statistic as well. Differences in sensitivityto individual hyper-latent variables and shifts in these sensitivities depending on themode/location of each variable distribution would require biased optimization of EIGdependent on the posterior distribution po(x|y, d) that is not yet known. Exploratory1457.3. Predictive Inference Formulations for Test Utilitywork in the course of this research proposed to provide some stability through reasonablesensitivity estimates, but the conclusion of this effort was the full realization of thefundamental limitations of optimizing for reduced epistemic uncertainty. Thus wheneverthe objective of an experimental design problem is to learn about the outputs of a system,optimization should proceed with regards to the outputs of the model representing thatsystem.7.3 Predictive Inference Formulations for Test UtilityFollowing work in decision theory, there is a comparatively small subset of the experi-mental design literature (originating from seminal work by S. Geisser [263]) that assertsthat in many contexts it is incorrect to frame the purpose of an experiment in terms ofgaining as much information about the latent/hyper-latent parameters as possible. In-stead, the objective is frequently to design an experiment that need only be informativeenough for reasonable decisions to be made regarding some action space. This is directlyin line with the conclusion of the previous section, where the relationship between IGin the hyper-latent space and satisfaction of engineering requirements is dynamic andnot one-to-one. Within an alternative predictive inference formulation, the informationgained is not with respect to the latent variable space of the model, but the predictivedistribution of observations that inform decisions/actions (in this application, those thatsatisfy requirements). Reframing BED in this way is in some respects conceptually sim-ple compared to defining utility in terms of abstract information gain. A model becomesabstracted as some uncertain object with different observable outputs. A test then mea-sures certain outputs to learn about the behaviour of others. Predictive experimentaldesign does require insight into the model, but the optimization is conducted only withregards to reducing uncertainty about the behaviour of model outputs that predict real-world outcomes on which decisions are made. For interested readers, although the textitself is more focused on specific sub-concerns, the case study on medical characteristictesting in Chapter 8 of Geisser’s book on predictive inference provides a concrete analyticapplication of predictive BED in a manner that is reasonably easy to follow [252].Predictive model quantities were already touched upon in the Ch. 6 design of asoftware library for CBI of PoF models within the developed SPM architecture, butwere only described and not formally defined or justified. Mathematically, a predictiveoutput variable will be denoted z, dependent on the hyper-latent, latent, and potentiallyobserved variables, but is typically a deterministic function of those random variablesand contributes no additional stochasticity. Additionally, even if z is dependent on other1467.3. Predictive Inference Formulations for Test Utilityobserved quantities, the aleatoric uncertainty of measuring that observable is avoidedand so equivalent deterministic “predictive” versions of those observables can be used tocompute z. For a deterministic predictive quantity computed as some arbitrary functionfz(v,x), the probability distribution p(z) is just a functional transformation of the jointdistribution p(v,x). Equivalently:p(z|v,x) =1, z = fz(v,x)0, otherwise (7.7)The distribution of the predictive quantity can then be used to compute some sum-mary statistic(s) S on which an engineering reliability requirement sreq can be placed.Such statistics are computed over the predictive probability distribution, which containsboth the epistemic uncertainty encoded in X and the aleatoric uncertainty of V and sorequiring a double integral that must be numerically estimated (given that fz does notalways have an analytic solution).Sz∼p(z)[z] = Sv∼p(v|x), x∼p(x)[fz(v,x)] (7.8)With this statistic of the predictive distribution, a revised definition for a risk-basedutility measure is constructed in terms of the previously-seen secondary summary statisticover Y . The definition in Eq. 7.9 is denoted the requirement pass probability (RPP).RPP(d) =∑y∈Y ′ pr(y|d)∑y∈Y pr(y|d), Y ′ = {y ∈ Y : Sz∼po(z)[z] ≥ sreq} (7.9)The core benefit of the RPP over the IGPP is that sreq is completely independent ofthe model and test design space, unlike the earlier TIG(X,m). So long as the predictivequantity z and statistic S appropriately represent LTR, sreq can be set without knowledgeof the internal model structure or prior beliefs.7.3.1 Uncertainty-Aware Lifespan Metrics as Predictive UtilityMeasuresWhen defined in terms of a generic predictor variable and statistic, it can be difficultto ground the RPP in practice. Without precluding the possibility of more nuancedand complex future strategies (e.g., predictors of component criticality for the type ofsystems-level analyses tackled by Yadav et al. [245]), the predictor variable proposed forbasic reliability qualification tasks is product lifespan. For the scope of this research,the product lifespan is typically taken as the minimum of the lifespans across a set1477.3. Predictive Inference Formulations for Test Utilityof individual devices or circuits (e.g., the first critical timing path to degrade beyondan allowable delay margin). Within a PoF model, each observable output is usuallyconsidered as a distinct possible point of lifespan-limiting failure.For the summary statistic S, the uncertainty-aware lifespan metrics proposed in Sec.4.7 are leveraged. The primary proposed predictor-statistic pair used is the chip-levellifespan with S = Qx%-LBCI. For each possible observation y, the probabilistic lifespanof the PoF model is sampled, subject to the posterior epistemic and aleatoric uncertainty,to obtain a spread of predicted failure times across which the Qx%-LBCI is computed.A required lifespan can then be compared against the estimated Qx%-LBCI to indicatewhether the test outcome y would provide sufficient information to qualify the product.The RPP for a given test design d thus evaluates what proportion of possible test obser-vations will lead to a successful qualification. A resulting utility definition incorporatingthe RPP of meeting the target Qx%-LBCI will directly consider the risk of insufficiencyfor each considered test design with explicit regards to the predicted LTR.A second option for a statistic over lifespan is the total width of the Qx%-HDCRregion. Placing a requirement on the actual HDCR region itself is less feasible sinceit can contain multiple intervals with arbitrary bounds. The total width directly sum-marizes the precision of a reliability prediction while allowing for multi-model lifespandistributions. This avoids the identified issues of IG, in that the lifespan may be partic-ularly sensitive to some hyper-latent variables over others, and instead directly considersthe uncertainty in the lifespan. By placing a Qx%-HDCR width requirement, the RPPestimates the proportion of possible observations resulting from a given test design thatlead to sufficiently precise predictions. Note that this option for S is not as useful formarket qualification since the statistic is entirely agnostic to the value of predicted lifes-pan and only evaluates the spread of predicted lifespan with respect to uncertainty (i.e.,the width could be small but the predicted lifespan may be far less than required). TheRPP with respect to Qx%-HDCR width is certainly possible to use, but direct optimiza-tion to minimize the Qx%-HDCR width without reference to a requirement is expectedto be more valuable as an alternative to EIG for optimizing the amount of informationobtained from a test.Both of these defined statistics for BED utility remain imperfect for some applicationsas they merge epistemic and aleatoric uncertainty when considering the product lifespanand do not explicitly consider whether the underlying product itself is sufficiently reliable.For the former concern, the separation of uncertainty in the SPM architecture allowsfor variants to be proposed where either uncertainty component is eliminated from thesampled lifespans (either by always sampling the zero mean of the SPM latent variables1487.4. Description of the Developed Accelerated Life Test Design Frameworkor always sampling the non-zero means of the hyper-latent variables). These two “mean”variants of S for BED may have value in certain scenarios, but diverge from the SPMarchitecture’s original motivation to consider product lifespan in light of both sources ofuncertainty for high reliability applications. The second concern is complex, as insufficient“true” reliability is both something to hide and to uncover quickly within real-worldcontexts. It may be possible to devise a BED analysis that assumes sufficient reliabilityby excluding “bad” y samples where the Qx%-LBCI, computed using fixed mean samplesxµ when sampling X (i.e., neglecting epistemic uncertainty), reveals poor reliability. ABED analysis using this strategy would effectively discard some information containedin the prior beliefs and potentially lead to unstable behaviours, however, and is notrecommended without an in-depth analysis that is beyond the scope of this dissertation.Future work to examine the relationship between experimental design and desirable versusundesirable underlying behaviours would certainly be interesting to pursue, as no suchdiscussion was identified in the existing literature, but is not anticipated to significantlyaffect the value of the BED framework proposed here.7.4 Description of the Developed Accelerated Life TestDesign FrameworkIt would be naive to assume that the objectives of all semiconductor ALTs are identical,and so it important to leave the exact formulation of the BED utility U as a design choicein a generalized BED framework. In many applications measures of information gain andtest risk could be complementary, thus the ability to evaluate both within a single analysisis valuable. The approach taken in this research is to evaluate and collect a selected setof statistics for each considered test design within a BED analysis, allowing for iterativetuning of a multi-faceted utility function without needing to rerun a computationallyexpensive algorithm. Note that test constraints are not expected to be incorporated aspart of a utility function since they instead inform the space of possible test designs D.Summarizing previous discussion and introducing some simple measures of cost, Table7.1 lists some key considered components of utility.1497.4. Description of the Developed Accelerated Life Test Design FrameworkTable 7.1: Component measures of test utility considered within the research scope.Utility Measure Statistics Name CategoryQx%-LBCI RPP Lifespan requirement pass probability RiskVIG Variance of information gain RiskQx%-HDCR Expected Width Expected predicted lifespan precision InformationEIG Expected information gain InformationTime Required test time CostResources Total number of chips needed CostA challenge for defining specific utility functions is that all the included measures resistdirect comparison without a common reference. For example, how much time is worthspending to decrease the expected HDCR width by one year? Such questions regardingrisk tolerance and relative importance of factors are dependent on project managementand particular to a given application, thus recommendation of specific utility functionsis not a focus of this research. Utility formulations seen in the Ch. 9 case studies are adhoc functions of measures in Table 7.1 based on the specific envisioned scenarios.To contextualize the listed measures, the most similar existing work on semiconductorALT design defines utility in terms of minimization of MLE parameter estimation error, afrequentist approach analogous to BED analysis based on EIG alone. The proposed BEDframework thus introduces the capability for prior knowledge integration, arbitrary PoFmodels, risk-based experimental design, and cost-aware experimental design over priorsemiconductor reliability research. In the more general reliability statistics literature,multiple works use the predictive Qx%-LBCI metric as a summary statistic within se-quential ALT design analyses [210, 211], however these approaches look at the reductionin the variance of the Qx%-LBCI estimate rather than situating it within an equivalentto RPP. This approach would be categorized as optimizing for information, similar to themean Qx%-HDCR width measure, rather than a risk measure. By introducing a requiredQx%-LBCI, the value of additional information saturates and allows for prioritization ofcost minimization above some tolerable risk threshold. It is asserted that the considera-tion of Qx%-LBCI generally implies an analysis of LTR with respect to the probability ofunits failing before some intended lifespan, thus a risk-based utility definition is usuallymore appropriate. Utility in terms of Qx%-LBCI variance minimization is interestingin that it identifies test designs that reduce uncertainty in the left tail of a distributionin particular, but suffers from the same limitation as when minimizing the Qx%-HDCRmean width in that the lifespan magnitude is not considered.With all the complexities of the introduced utility measures, the general experimen-tal design objective of Eq. 7.1 becomes too specific, as not all applications will use anexpectation across U(d,y) and instead may use some combination of alternative model1507.4. Description of the Developed Accelerated Life Test Design Frameworkquantities and summary statistics across Y . The objective is no longer a single generalequation and becomes application-specific; the methodological approach taken here alsoemphasizes the value in iteratively tuning the objective according to different importanceweights on various utility measures that may take time and feedback to determine. Byrecomputing the utility and expectation in consultation with stakeholders an eventualtest design can be identified that balances application-specific objectives and associatedpriorities. For this to occur, the individual component measures within a utility defini-tion that are demanding to estimate must be pre-computed and persisted. This leadsto the following recommended procedural steps within a given BED analysis using theframework, with the computational approach needed to perform step two being the topicof the following chapter:1. Decide on the set of individual utility measures (such as those listed in Table 7.1)that may inform a decision on which test to conduct. Each must be computed aspart of the BED analysis and so minimizing the size m of this set reduces the totalcomputational cost of the analysis.2. Run a computational BED algorithm to compute and persist all individual utilitymeasures based on the posterior distribution p(x|y, d) for each sampled observationy across each test design d.3. Propose an initial scoring function taking the utility measure statistics as inputsand outputting a scalar score u = f(M1, ...,Mm). Weighted and normalized sumsare used to internally reduce the individual measures to a single score within thescope of this dissertation, though other approaches are certainly possible.4. Compute the utility scores for each design d that then indicate an optimal ALTdesign. Human judgement from reliability engineers and/or leadership should beused to identify whether the identified test has tolerable risk and is feasible givenresources. Iteratively tune the utility function (e.g., summation weights or reduc-tion operations) until the resulting optimal design is deemed reasonable in termsof addressing the product qualification objectives and constraints.5. Proceed to conduct the selected experiment to obtain data for inference and sub-sequent lifespan prediction.151Chapter 8Implementing ComputationalPredictive Bayesian ExperimentalDesignDue to the recency and technical complexity of computational BED, there are few ex-isting software libraries that provide implementations of BED algorithms. Additionally,the unique design requirements of the developed hierarchical probabilistic framework andutility measures incur additional required features that are not addressed by any existingimplementations. This chapter will review existing implementations of computationalBED algorithms, provide background on importance sampling methods, then go throughthe design and implementation of a BED algorithm suitable for engineering applicationswith varied utility definitions (also incorporating predictive quantities and hierarchicalprobabilistic models). A brief performance analysis of the algorithm is included, howeverwithin the scope of this research the novel functional capabilities are the primary objec-tive, particularly since most accelerated test design applications have low time sensitivity,and thus performance is not heavily prioritized and remains a significant area for futurework.8.1 Necessary Software Infrastructure for ImplementationWith a reliance on computational techniques to estimate utility measures for arbitraryPoF SPMs, sophisticated software is needed to implement the formulated SPMs andalgorithms needed to realize the proposed BED framework. Similar to CBI, performanceis crucial as model complexity increases, but in the case of BED the computationaldemand is much higher as algorithms must also sample across the distributions p(y|d)of possible experimental observations and D possible experimental designs, instead ofonly the latent and hyper-latent variable spaces. As a result, almost all widely usedsoftware for probabilistic programming is built upon an underlying numeric computationlibrary that provides features such as automatic hardware vectorization and runtime1528.1. Necessary Software Infrastructure for Implementationcompilation of repeatedly used functions (this is similar to software for deep learning inwhich the forward inference and back-propagation procedures are compiled from a neuralnetwork specification). Interpreted languages (in particular Python) are still used in mostimplementations for the model specification and user-facing functionality over compiledlanguages, however, for ease of use, rapid iteration across hyper-parameters, and theirlarger collections of open source libraries.8.1.1 Existing Bayesian Experimental Design SoftwareAvailable implementations of BED algorithms are quite limited due to the recency andemerging nature of the field. Survey of publicly available software revealed only fivereasonably complete libraries that are summarized in Table 8.1.Table 8.1: Comparison of existing software libraries for BED.Name Ref Author Organization Year LanguagePyro OED [264] A. Foster et al. University of Oxford 2019 Pythonacebayes [265] A. M. Overstall et al. University of Southampton 2020 RMINEBED [266] Kleinegesse & Gutmann University of Edinburgh 2020 PythonOptBayesExpt [267] R. D. McMichael et al. NIST 2021 PythonPyApprox [268] J. D. Jakeman Sandia National Laboratories 2023 PythonOf the identified libraries, acebayes was not used due to the source language, whileall four Python-based implementations were evaluated. A key challenge with existingsoftware is that the definition of utility is frequently baked into the algorithm for perfor-mance optimization, thus custom utility measures cannot be evaluated without modifi-cation. The MINEBED and Pyro OED algorithms are fixed to EIG, thus they are unfitfor the more general utility components listed in Table 7.1.The OptBayesExpt library does provide several choices for utility but is designed forsequential inference, a sub-field of BED for on-the-fly optimization of experiments withmultiple measurements over time, and does not include predictive BED capability. Infuture work sequential inference could be used to create dynamic accelerated aging testswhere stress conditions vary as the test proceeds based on observed measurements, butthe library is not suitable to meet the design requirements in scope for this dissertation.The PyApprox software is unique amongst available software in that it does providecapability for basic predictive inference BED. This library was not deemed suitable foruse, however, as the library does not make use of runtime compilation and as of writingthere is no documentation or sample code available for the BED elements of the library.The combination of these two factors would lead to low performance and significantreverse engineering effort.1538.1. Necessary Software Infrastructure for ImplementationAdditionally, none of the five libraries discussed have consideration for hierarchicalhyper-latents that separate epistemic from aleatoric uncertainty, thus information gainwould incorrectly be computed with respect to aleatoric uncertainty of latent variablesas well as epistemic in these libraries. The most well documented implementation, PyroOED, was therefore leveraged as a reference during implementation of a custom algorithmthat allows for arbitrary utility based off of predictive quantities and isolated epistemicuncertainty. The NumPyro probabilistic programming software framework was used asthe foundation for program transformation and performance features [238], in alignmentwith the custom library for constructing models and performing inference using the SPMarchitecture detailed in Ch. 6.8.1.2 Custom Algorithm Design ApproachDevelopment of a custom predictive BED algorithm prioritized simplicity and flexibility.Though methods based on variational inference exist, using gradient descent approachesto match a proposal distribution to the target [264], these were not considered as a start-ing point as they are generally restricted to continuous variables, require the constructionof proposal distributions, and are complex to implement. Variational approaches are animportant direction for future research, however, as the additional effort and restrictionsimposed do have the potential to lead to drastic performance improvements and are thefoundation of presently-emerging enhancements to BED for sequential design [269, 270].Approaches based on augmenting existing CBI algorithms (such as NUTS) for eachpossible observation y would be functional but slow, as existing implementations arepoorly optimized for massively parallel usage. Such techniques based on a secondarysampling algorithm or analytic solutions to marginalize over the possible observationdistribution p(y|d) are used by some existing surveyed works in applications with smallmodels and observation spaces [210, 253, 259, 260].In lieu of variational or augmented MCMC algorithms, an algorithm using importancesampling and founded on the nested Monte Carlo approach of Foster et al. [264] isused for simplicity and flexibility in working with different utility measures. The corealgorithm will be presented in Sec. 8.3. First, though, a review of importance samplingand derivation of specific results needed for the algorithm are provided in the followingsection.1548.2. Necessary Importance Sampling Results8.2 Necessary Importance Sampling ResultsImportance sampling (IS) is valuable as an approach to numerical estimation that iscomparatively simple and, if the problem is well understood, can be more efficient thanMCMC methods. The general problem is to estimate the value ζfp(x) corresponding tosome summary statistic (S) reduction of the function f(x), defined over some targetdistribution p(x):ζfp(x) = Sx∼p(x)[f(x)] (8.1)In essence, IS is a superset of naive Monte Carlo sampling that allows for the randomsample points used to estimate this expectation to be sampled from an arbitrary aux-iliary/proposal probability distribution q(x). Although the statistic S can be arbitraryin general, IS is typically presented in terms of computing an expectation to explicatethe approach. This standard is kept here for clarity. In IS, an unbiased estimate of theexpected value µ˜fp(x) when using n random samples from q(x) is computed as:µ˜fp(x) =1∑ni=1p(xi)q(xi)n∑i=1p(xi)q(xi)f(xi), xi ∼ q(x) (8.2)The motivation behind IS is to minimize the variance (i.e., expected error) of thisestimate, thus minimizing the number of samples required to obtain confidence in theaccuracy of the estimate µ˜fp(x). By definition, the variance of this IS estimate is anotherexpectation, which can be estimated via naive Monte Carlo (following [208]):V[µ˜fp(x)] = Ex∼q(x)[(f(x)− µfp(x))2]≈ 1nn∑i=1[p(xi)q(xi)f(xi)− µ˜fp(x)]2, xi ∼ q(x)(8.3)Notice that the variance is in general not small, and is dependent on the distributionq(x), thus effective IS requires a good choice for this proposal. The optimal choiceguarantees zero estimated variance, shown in Eq. 8.4, but is unrealistic as it requiresknowing the full distributions and solution in advance.q(x) =p(xi)f(xi)µ˜fp(x)=⇒ V[µ˜fp(x)] ≈1nn∑i=1(µ˜fp(x) − µ˜fp(x))2 = 0 (8.4)1558.2. Necessary Importance Sampling ResultsThe original problem of estimating an arbitrary summary statistic can now be re-expressed in terms of taking the reduction across q(x) instead of p(x) by introducingan additional argument to the summary statistic, with a condensed importance weight(a.k.a., likelihood ratio, inverse propensity score) term w(x) notation for brevity. Theexact expression provides a more general and concise explanation of the theoretical un-derpinning of IS, though necessary alterations to the procedure for evaluating S will varydepending on the particular statistic:ζfp(x) = Sx∼q(x)[f(x), w(x)] where w(x) =p(x)q(x)(8.5)8.2.1 Importance Sampling from the TargetOn first encounter IS can be challenging to grasp conceptually, however the techniquebecomes more intuitive once seeing some of the specific cases that are leveraged. The bestpractical choice for q(x) is the target/nominal distribution p(x), causing all importanceweights to reduce to 1. This requires that samples can be drawn from p(x) (which isoften not possible), but gives the computationally simple expression:µ˜fp(x) =1∑ni=1p(xi)p(xi)n∑i=1p(xi)p(xi)f(xi) =1nn∑i=1f(xi), xi ∼ p(x) (8.6)Notice how this reduces to the original direct approach to the summary statisticproblem in Eq. 8.1, illustrating how direct Monte Carlo is a specific case of IS. If the targetdistribution can be sampled from directly, there is little need to consider IS explicitly.The variance of the estimate when performing IS from the target is:V[µ˜fp(x)] ≈1nn∑i=1(f(xi)− µ˜fp(x))2, xi ∼ p(x) (8.7)In expectation f(xi) will be µfp(x) following Eq. 8.1, thus the variance term µf − µ˜fis expected to be zero but varies with individual samples. The squared difference meansthe overall variance is non-zero and proportional to the variance of f(x), however. Inall following specific IS cases the variance expression not shown as it does not reduceusefully beyond the original definition in Eq. 8.3.8.2.2 Uniform Importance SamplingIf q(x) is uniform across the full domain of X (constant probability ku within the do-main), an expression similar to the exact formula for the finite discrete variable expected1568.2. Necessary Importance Sampling Resultsvalue emerges in Eq. 8.8, illustrating how finite discrete variable calculations are almostidentical to uniform IS. The only difference is that in the finite discrete case each value xcan be enumerated once instead of randomly sampled, giving an exact result and cumu-lative probability of 1. In the infinite and continuous cases, however, this sum dependson the random samples and so a normalization constant is required.µ˜fp(x) =1∑ni=1p(xi)kun∑i=1p(xi)kuf(xi), xi ∼ U=1∑ni=1 p(xi)n∑i=1p(xi)f(xi), xi ∼ U(8.8)8.2.3 Importance Sampling from the PriorIn Bayesian inference contexts, the target distribution is frequently the posterior po(x|y).Without MCMC methods (which as previously discussed are complex and do not par-allelize as efficiently for use in BED) this cannot be directly sampled from, and so aproposal sampling distribution is needed. The natural choice for q(x) in such situationsis the prior distribution pr(x), as a well-specified set of prior beliefs encodes relevantknowledge as to what po(x|y) might look like and thus what constitutes a good proposal.In effect, the existence of a proposal q(x) that is known to be closer to po(x|y) than pr(x)implies the existence of knowledge not incorporated into the prior beliefs, therefore sug-gesting that pr(x) could be better specified. Once prior beliefs are elicited, IS to computean expectation over the posterior distribution via samples from the prior is computed asin Eq. 8.9, with simplifications arising from substitution according to Bayes’ rule fromEq. 6.1.µ˜fp(x) =1∑ni=1po(xi|y)pr(xi)n∑i=1po(xi|y)pr(xi)f(xi), xi ∼ pr(x)=1∑ni=1pr(xi)p(y|xi)pr(y)pr(xi)n∑i=1pr(xi)p(y|xi)pr(y)pr(xi)f(xi), xi ∼ pr(x)=1∑ni=1p(y|xi)pr(y)n∑i=1p(y|xi)pr(y)f(xi), xi ∼ pr(x)(8.9)Recall from Sec. 6.1 that since pr(y) is computed by marginalizing p(y|x) over pr(x),the importance weights w(x) for IS from the prior can be computed solely from the1578.3. Computational Predictive Bayesian Experimental Design Algorithmlikelihood distribution p(y|x) via IS from the target. Eq. 8.10, where the importanceweights are notated as w(x,y), makes the added dependence on y explicit.w(x,y) =po(x|y)pr(x)=p(y|x)pr(y)=p(y|x)1n∑ni=1 p(y|xi), xi ∼ pr(x)(8.10)Finally, the original summary statistic problem can be re-expressed for posteriorstatistics with importance weights from the prior:ζfpo(x|y,d) = Sx∼po(x|y,d)[f(x)]= Sx∼pr(x)[f(x), w(x,y)] where w(x,y) =p(y|x)pr(y)(8.11)8.3 Computational Predictive Bayesian ExperimentalDesign AlgorithmThe starting point for the developed arbitrary utility BED algorithm is the nested MonteCarlo algorithm from Foster et al. [264]. Their approach estimates EIG directly via Eq.8.12, using naive Monte Carlo sampling and handling potential numerical instability bydiscarding “bad” samples at the end of computation.EIG(d) :=1nn∑i=1log[p(yi|xi, d)1m∑mj=1 p(yi|xj , d)],yi∼p(y|xi,d)xi/xj∼pr(x) (8.12)The nested Monte Carlo algorithm lacks several features needed for arbitrary utilitypredictive BED with hierarchical models (as touched on in Sec. 8.1.1). First, it does notallow for quantities other than EIG to be estimated. For example, the VIG cannot beestimated as IG is not computed directly at any point. Second, the algorithm does notconsider models with additional predictive quantities z beyond the observed variablesy. Finally, the estimator is poorly suited for use with the hierarchical SPM architec-ture, as the latent variable space V would not be marginalized out independently fromthe hyper-latent space X. The high-level implementation of the custom computationalpredictive BED algorithm shown in Algorithm 1 introduces capabilities for all of thesefeatures within a fully IS-based estimation approach.1588.3. Computational Predictive Bayesian Experimental Design AlgorithmAlgorithm 1 Importance sampling based algorithm for performing predictive BED anal-ysis with arbitrary utility definitions.1: procedure custom bed(model, {designs}, {measures})2: Xs ← model.sample(X)3: HXs ← − 1size(Xs)∑log[model.p(Xs)]4: for d in {designs} do5: MU [d]← eval d(model, d, {measures}, Xs)6: return MU7: procedure eval d(model, d, {measures}, Xs)8: Ys ← model.sample(Y |d)9: p(Ys|Xs, d)← marginalize v(model,Xs, Ys)10: p(Ys|d)← 1size(Xs)∑p(Ys|Xs, d)11: Ws ← p(Ys|Xs,d)p(Ys|d)12: Zs ← model.sample(Z|X, d) if m is predictive13: for m in {measures} do14: MUd [m]← m.compute(Ws, ...))15: return MUdThe outer procedure performs the outmost iteration over the set {designs} of all testdesigns being considered, collecting estimated values into the hash table MU for eachrequested utility measure in set {measures}. Prior to iteration over {designs}, all hyper-latent samples Xs are generated from pr(x) of the model since they are fully independentof d and all other model variables (thus can be re-used to save on computation). Theprior entropy estimate HXs is computed via IS from the target at this point as well sinceit is similarly independent (though can be skipped if not using IG-based utility measures).The inner procedure is separated out as it executes identically for every d, allowing forruntime compilation to be leveraged to drastically speed up repeat executions (exceptingchanges in test dimensionality d, such as a different number of chips per observation y,which only changes array sizing but still requires re-compilation). Samples Ys are gener-ated, then IS via a specialized proposal is used to marginalize over the latent variables Vto estimate the likelihood p(y|x, d). The custom algorithm used to generate samples fromthis proposal and compute the IS estimate is discussed shortly in Sec. 8.4. The marginalp(y|d) can be estimated using the likelihoods via IS from the target, at which point keyimportance weights for estimating the various utility measures via IS from the prior canbe computed. Each requested measure m is handled iteratively, with shared predictorsamples generated first so long as at least one measure uses them. Note that the computeprocedure for every measure performs two reductions, one over the hyper-latent space Xusing IS from the prior (and thus the calculated importance weights), then one over the1598.3. Computational Predictive Bayesian Experimental Design Algorithmpossible observation space Y using IS from the target pr(y|d) (thus no weights needed).The ellipses in the call to compute the measures indicate that different measures reduceover different functions f that require various quantities to compute. For example, allpredictive measure functions are dependent on Zs and in all IG-based measures f = IGand so the prior entropy HXs is needed. The specifics of these arguments are obscured tosimplify the pseudocode representation, but they are explicated in the following sectiondetailing how the measures from Table 7.1 are estimated.Altogether, the eval d procedure in Algorithm 1 performs four nested reductions oversamples from X, V , Y , and {designs}. Performance is highly dependent on the modelcomplexity since it must be sampled and have probabilities computed for every sample;this relationship is not easily quantified due to the wide variety of aspects of the modelthat impact performance (e.g., different mathematical operations, array manipulations,and parameter quantities can all vary between PoF models). For a fixed model and set ofutility measures (and constant dimensionality across each d in {designs}), the algorithmscales as O(ndnynvnx), where the terms are the number of samples taken from eachof {designs}, Y , V , and X. This is very computationally expensive but still feasibleand comparable to existing computational BED algorithms. Performance is aided bythe entirely independent and repetitive computations across ny, nv, and nx, thus drasticimprovements can be achieved through parallel execution and run-time compilation. Forthis initial algorithm design little consideration was given to improving the theoreticalalgorithmic performance; acceptable performance for use is instead primarily achievedthrough the mentioned implementation efficiencies. Total computational cost also endsup being a tradeoff against utility estimate variance, as increasing the number of samplesimproves the quality of estimates, but the minimum quality required for effective BEDanalysis can vary depending on the model and utility measures used. In many cases,trends of how test design impacts utility can be identified even when individual designestimates are poor, thus smaller than expected sample sizes can be tolerated. Total runtimes required for specific problems are stated in the upcoming Ch. 9 case studies.Many complexities of the algorithm are implicit in the pseudocode representation,such as managing how the sample dimensions for V , X, and Y are mapped correctlyfor array calculations on top of the existing internal model dimensions. Additional tech-nicalities include correctly working with the SPM to extract the necessary samples andprobabilities, tracking and deriving random seed keys to allow for repeatable stochasticbehaviour, generating performance diagnostics, and leveraging log domain computationto maintain numerical stability. The full procedural Python algorithm with all imple-mentation details is available in the open-source repository [239].1608.3. Computational Predictive Bayesian Experimental Design Algorithm8.3.1 Summary Statistic Estimation Using Importance WeightsWith sampled predictor values Zs ∼ pr(v,x) and corresponding importance weights Wsvia IS from the prior (weights are duplicated along the nv axis of Zs), the posterior Qx%-LBCI can be computed through weighted quantile estimation in parallel for each samplein Ys. This is done procedurally by sorting all the sampled predictor values and thendetermining the location of each sample in a weighted CDF. Finally, linear interpolationbetween the weights is used to find the exact x% quantile of the CDF. The RPP isthen computed by comparing each Qx%-LBCI estimate against the requirement sreq andreturning the proportion of y samples that pass. The marginal probabilities pr(y|d) usedin the exact definition of Eq. 7.9 are not required as the estimate is constructed bysampling y ∼ pr(y|d), which allows for IS from the target and so uniform importanceweights according to Eq. 8.6.A similar procedural method estimates the Qx%-HDCR width and associated meanusing IS from the prior. The distribution po(z) is estimated using a histogram of theweighted samples Zs, then the highest density bins of the histogram are successivelyincluded until the x% threshold is reached. The width is computed as the bin widthmultiplied by the number of included bins, and parallel computation across sampledy ∼ pr(y|d) enables the mean to be estimated via IS from the target according to Eq.8.6.From Table 7.1, other key component utility measures considered within the scope ofthis dissertation that require BED analysis to estimate are all different reductions of IGacross y ∼ pr(y|d). The prior entropy is computed in advance using IS from the targetin Algorithm 1 since it is fully independent of the test design d and sampled observationsy. The posterior entropy H[X|y, d] resulting from each y is estimated via IS from theprior:H[X|y, d] = Ex∼po(x|y,d)[− log po(x|y, d)]= Ex∼po(x|y,d)[− log[pr(x)p(y|x, d)pr(y|d) ]]= Ex∼po(x|y,d)[− log[pr(x)wz(x)]]= − 1∑ni=1wz(xi)n∑i=1[wz(xi) log[pr(xi)wz(xi)]], xi ∼ pr(x)(8.13)The IG is computed as H[X] − H[X|y, d] from the estimated entropy values, thenEIG and VIG can each be estimated using IS from the target, since y ∼ pr(y|d).1618.4. Hierarchical Latent Marginalization Algorithm8.4 Hierarchical Latent Marginalization AlgorithmDirect samples v ∼ p(v|x, d) are incredibly inefficient for estimating the observationlikelihood p(y|x, d) in most PoF models, even though IS from the target is very efficientin general. This is due to the high dimensionality of V and Y in many semiconductorreliability analyses, as well as the relationship between them resulting from the SPMarchitecture. The inefficiency is compounded by multilevel variability effects, leading toextremely sharp probability gradient curvature with respect to V in the high-dimensionalconditional distribution p(y|v,x, d). Note that the dependency of V on d is only in termsof dimensionality; V is independent of stress conditions, but needs to be duplicated foreach lot, chip, and device that can vary between test designs.To illustrate the IS inefficiency problem, consider measuring linear degradation of twochips with three devices each where the mean slope over time xµ = −1 but the device-level and chip-level slope variability xσ and xς are unknowns (hyper-latent variables). Thealeatoric latent variables vdev ∼ N(0, xσ) and vchp ∼ N(0, xς) are sampled then added tothe base slope to model the degradation slope of each device. Measurements of the slopeare conducted via an imperfect instrument, introducing a noise-based deviation ϵy = 0.05to all measured values y. Now consider inference (assuming some prior beliefs on xσ andxς) after observing the measurement y˜ = [[−0.8,−1.0,−0.9], [−1.0,−1.2,−1.1]] at timet = 1. Recall the integral from Eq. 6.2 that marginalizes out the aleatoric uncertainty inV , which is now to be estimated via IS from the target:p(y|x) = 1nvnv∑i=1p(y|vi,x), vi ∼ p(v|x) (8.14)The problem with sampling vi ∼ p(v|x) is the high-dimensional space of possiblesamples and the extremely sharp probability gradient present around f(v,x) ≈ y˜ (un-less ϵy is the dominant contributor to aleatoric uncertainty), where f is the PoF modelfunction.The consequence of this is that only samples v such that f(v,x) ≈ y lead to non-zero probabilities, and unless the total sample size nv is massive the estimates for p(y|x)are highly dependent on “lucky” samples. To combat this issue in general application,all samples v should be near the small high probability region of the distribution sothat all samples are uniformly “lucky”. The remaining volume of p(v|x) can be safelyignored since its contribution to the estimate for p(y|x) is negligible for high-dimensionalmodels. Note that good samples cannot be generated in reverse by solving the inverseproblem f(v,x) = y then adding stochasticity, as the inverse PoF model function f−1 isnot directly computable in general. Instead, Algorithm 2, inspired by sequential Monte1628.4. Hierarchical Latent Marginalization AlgorithmCarlo (SMC) [271], was developed to obtain appropriate samples v s.t. f(v,x) ≈ y andthen use these samples to estimate p(y|x).Algorithm 2 Custom layered resampling algorithm used to marginalize across V tocompute p(y|x).1: procedure marginalize v(model,Xs, Ys)2: ay ←√|var(Ys)−var(model.ϵy)|var(Ys)3: Ysa ← mean(Ys) + ay[Ys −mean(Ys)]4: Vinit ← model.sample(V |X)5: Vs ← 06: p(Vinit|Xs)← model.p(Vinit|Xs)7: for lvl in (lot, chp, dev) do8: Vslvl ← Vinitlvl9: p(Ysa|Vs, X)← model.p(Ysa|Vs, X)10: prs← p(Ysa|Vs,X)1+log[size(Vslvl )]p(Vinitlvl )11: Vslvl ← resample Vslvl according to prs12: p(Vs|Xs)← model.p(Vs|Xs)13: p(Ys|Vs, Xs)← model.p(Ys|Vs, Xs)14: return∑Vsp(Vs|Xs)p(Ys|Vs, Xs)The first step in the resampling algorithm is to adjust the variance of Ys proportionalto the summed variance resulting from measurement noise ϵy. Without reducing thevariance of Ys in this way, finding samples Vs s.t. f(Vs, Xs) ≈ Ys leads to overestimatesof inherent aleatoric uncertainty as the measurement noise is not introduced during re-sampling. After a large set of samples Vinit ∼ p(v|Xs, d) is generated for all individualsamples of Xs and the probability of each sample computed, resampling is conducted foreach level of variability, analogous to particle filter resampling procedures in SMC. Thisworks since the probability gradient in any single dimension of V is reasonably smooth,and so good samples for each component of V can be obtained. The challenge is to thenmatch up the good component samples from each dimension in a stochastic manner. Thegrouped-to-individual order of the levels ensures resamples Vs are likely under p(v|Xs)in comparison to other regions of the space V that give f(v,x) ≈ y. For example, y˜ inthe earlier model could be obtained with vς = [0, 0],vσ = [[0.2, 0.0, 0.1], [0.0,−0.2,−0.1]]or vς = [0.1,−0.1], vσ = [[0.1,−0.1, 0.0], [0.1,−0.1, 0.0]]. The latter is more likely un-der reasonable prior beliefs but would almost never be resampled if vσ was resampledfirst. As a result of this ordering, the algorithm is statistically biased towards posteriorsthat favour higher group-level variability over higher individual variability, however thisbias is only noticeable when both cases are similarly likely under prior beliefs and is notcrucial to address in a custom algorithm for an initial implementation of the developed1638.4. Hierarchical Latent Marginalization AlgorithmBED framework. Future work towards improved BED algorithms can likely address andquantify this statistical bias, though it is worth pointing out that other widely used prob-abilistic programming algorithms such as variational inference also introduce bias; thetopic is an open area of research [272].The resample probabilities are scaled by a power law according to the dimensionalityof the latent variable space and compensated for the sampling distribution p(v|x). Thisscaling is needed due to the severity of the lucky sample issue increasing with the dimen-sionality of V . Finally, the resampled values Vs are used to marginalize across V andobtain p(Xs|Ys). Notice that the returned expression is just un-normalized uniform ISdescribed by Eq. 8.8; the entire purpose of this algorithm is to obtain a set of samplesVs that is approximately uniformly lucky across the region near f(v,x) ≈ y.Similar to the higher-level BED Algorithm 1, various implementation complexitiesare left implicit in the marginalize v procedure. On top of all the random key track-ing, diagnostics, and log domain computation management details of Algorithm 1, theresampling procedure needs to explicitly handle the multilevel variability dimensions andtest design sizings to ensure resampling proceeds correctly. Computational performancescales very similarly to the main BED algorithm based on the size of each samplingdimension. For a fixed model the performance scales as O(nynvnx), and acceptable per-formance is similarly achieved through implementation efficiency rather than algorithmicoptimization for this initial design. The full algorithm is provided in the open-sourcePython library [239].8.4.1 Marginalization Algorithm ValidationUnlike in the outer BED algorithm where all IS sampling distributions are known (thusthe utility estimates are unbiased and can be validated mathematically), the intendedsampling distribution f(v,x) ≈ y in the latent marginalization algorithm has no directprobability distribution that can be evaluated and is only assumed to be somewhat uni-form in some bound around y. Within the context of this research where all that isneeded is a reasonably accurate initial working solution, no precise mathematical argu-ment is developed to describe the estimate error for the likelihood p(y|x, d). Evidenceof sufficiently low estimate inaccuracy for effective use is instead provided empiricallyby leveraging the latent marginalization algorithm within an IS-based algorithm for CBIand comparing the results to those obtained via the NUTS algorithm when inferencingon data from an exact true model. These empirical test cases that validate that thealgorithm performs acceptably well for the models of interest within the scope of thisresearch are provided as part of the developed software [239].1648.4. Hierarchical Latent Marginalization AlgorithmFrom a performance perspective, the third-party NUTS implementation is signifi-cantly faster than the custom implemented IS approach when the dimensionality of thelatent and observed variables spaces is small, however when scaling up to chip and lotcounts comparable to HTOL (beyond approximately 200 variables) NUTS slows downsignificantly to the point where the IS approach can become more performant on a per-sample basis. It is also worth noting that NUTS itself is not exact, and so generalagreement is the objective of validation. Models used in the validation range from verysimple to moderately complex, but all with significant hierarchical latent structure. Fo-cus is placed on the types of models used in the upcoming case studies. Table 8.2 showsrelative differences in inferenced posterior distributions between the custom marginaliza-tion algorithm and NUTS, evidencing reasonably good matching between the algorithms.Some systematic differences in bias between the two algorithms is observable for individ-ual variability hyper-latent inference, as is mathematically expected from the approach.This biased inference of variance hyper-latents occurs due to the interaction between themodelled measurement noise magnitude and true data noise as well as the ordered re-sampling procedure, but the upside is that the algorithm uniquely allows for inference ofvery high-dimensional hierarchical models without relying on MCMC methods (thus canbe parallelized far more effectively since MCMC samples are sequentially dependent).Table 8.2: Relative difference of inferences made using the custom latent marginalizationalgorithm in comparison to the state of the art NUTS algorithm across three test casestargeting models similar to those used in application.Test Case Variable Type Relative Differenceof MeanRelative Differenceof VarianceLarge device counts Mean latent value 0.32% 3.74%Large device counts Individual variability 1.90% 1.24%Log-linear multilevel variability Mean latent value 0.72% 7.16%Log-linear multilevel variability Mean latent value 0.42% 4.46%Log-linear multilevel variability Individual variability 8.67% 11.15%Log-linear multilevel variability Group variability 0.69% 3.24%PoF multilevel variability Mean latent value 1.10% 12.96%PoF multilevel variability Mean latent value 0.64% 10.41%PoF multilevel variability Individual variability 9.65% 21.91%PoF multilevel variability Group variability 2.24% 3.88%The consequence of this imperfect behaviour is that the noise magnitude must beconsidered relative to true data noise and the hyper-latent prior variances during themodel specification process to avoid compromising algorithm accuracy. Minimization ofbias can be achieved through effective tuning of the model in relation to the aleatoricuncertainty of the data, but can never be fully eliminated (due to the procedural orderof resampling at different levels of variability discussed previously). Note that NUTS1658.4. Hierarchical Latent Marginalization Algorithmsimilarly struggles with extreme measurement noise ratios, becoming unstable, and thata rudimentary performance diagnostic of resample diversity is computed as part of thelatent marginalization algorithm to help check for acceptable noise ratios and effectivesampling (values of around 10% typically avoid significant bias and provide accurateresults).166Chapter 9Towards Rigorous andUncertainty-AwareSemiconductor Long-TermReliability QualificationEquipped with the developed predictive BED framework and software implementation ofa corresponding computational BED algorithm, the value of semiconductor ALT designscan be analyzed from several different utility and cost perspectives. In this chapter threecase studies leverage BED analysis of ALT designs to answer questions of test value and tooptimize qualification and characterization methods. Following these studies, conclusionsand future work directions are discussed.The first study examines some of the original motivating industry questions and issueswith existing semiconductor LTR qualification tests, leveraging predictive BED analysisto provide new perspectives and insights on ALT value. The second study conducts aBED-integrated reliability qualification that leverages presented research contributionsto depict a methodology that explicitly addresses epistemic uncertainty in predictions,considers inherent wear-out variability in PoF models, and allows for dynamic ALT de-signs optimized for value versus cost considerations. The final study ties various dis-sertation components together to perform multi-mechanism wear-out characterization,demonstrating how the sensor designs, probabilistic modelling, uncertainty-aware met-rics, Bayesian inference, and predictive BED framework all work together towards im-proved LTR analysis.All case studies use different PoF models and utility measures to demonstrate howeach semiconductor reliability analysis may have unique needs and objectives, neces-sitating the BED framework for experimental utility that is agnostic to any specificformulations. The particular market, fabrication technology, product timeline, and levelof tolerance for risk should all influence choices of PoF models, utility measures, andtest design spaces, thus the presented studies are intended to be exemplary of possible1679.1. High Temperature Operating Life Test Utility Analysischoices as opposed to prescriptive in nature. Study complexity is restricted by the scopeof the research work and BED algorithmic performance (algorithm complexity discussedin Sec. 8.3), however each is still able to scale well in problem dimensions of interest.Sufficient performance and feature support is achieved to effectively incorporate largelatent dimensionality up to the number of chips and lots seen in HTOL tests, detailedmulti-mechanism PoF models, and large test design spaces. Some tradeoffs are made tothe scale of specific dimensions to provide headroom for scaling in others within the scopeof each study, but future work, identified at the end of the chapter, would be expected tolead to increased achievable problem complexity. As a final note, variable and log-domaintransformations are leveraged implicitly within the study PoF models in line with thesuggestions of Sec. 4.5 and Appendix B. The exact models, procedural steps, and figuresare all explicated and can be run as demos within the open-source Python library [239].9.1 High Temperature Operating Life Test UtilityAnalysisA first application of the developed BED framework is in answering some of the originalconcerns posed in Sec. 1.6 regarding the predictive confidence and value of standardHTOL tests that motivated the conducted research. This study looks at how BED canbe used to quantitatively compare the value of ALT designs, and how predictive BEDis used to enhance these comparisons and evaluate lifespan prediction confidence. ABayesian analog of the frequentist RDT approach is constructed within a probabilisticmodel context alongside an alternative degradation-based model for later comparison.Both models are based on the Arrhenius model for the temperature dependence of wear-out given in Eq. 9.1, with failure rate FIT as a function of two latent parameters A andEaa, Boltzmann constant k, and temperature T .FIT = Ae−EaakT (9.1)The first probabilistic model aligns with an RDT framework by computing a pass orfail state for each chip under test. No variability is introduced to the latent parameters(now variables in a probabilistic context), and general variability is introduced by placinga sigmoid activation centered on the difference between the computed FIT and the testduration to generate a probability of failure. This probability is scaled by a factor of 10to produce an appropriate amount of aleatoric uncertainty as to whether a given chipfails during a test. The observed variable is a Bernoulli distribution according to thescaled probability. The FIT is also used as a predictor within the probabilistic model1689.1. High Temperature Operating Life Test Utility Analysisto compute the field use lifespan. The second model instead treats the computed FITas a degree of overall degradation (thus resembles the JEDEC BTI empirical model inEq. 1.1) and introduces a time dependence through a tn term (with a fixed exponentn instead of an additional hyper-latent variable to simplify the analysis). The latentvariable A is subject to both chip-level and lot-level variability, governed by respectivehyper-latent variables Aσ and Aς according to the developed SPM architecture. Theobserved variable is a level of degradation, while failure time in this second model isbased on a degradation threshold, using Brent minimization to solve for time in theinverse computation. Graphical representations for both models are shown in Figs. 9.1and 9.2, where the pass/fail model only also shows the divided sub-tests version usedtowards the end of the study.Figure 9.1: Graphical representation of the Arrhenius temperature acceleration modelwith pass/fail observations at the end of HTOL. A sigmoid function is used to introducealeatoric uncertainty to the observations.In both models, field use conditions and the required lifespan for the chips are basedon the example values from Sec. 1.6, with a 55°C field use temperature resulting ina 8.865 year lifespan that would be traditionally demonstrated by a successful HTOLtest. For the probabilistic models, product reliability is measured via the Q99%-LBCImetric, equivalent to the targeted 99% of units outlasting the demonstrated lifespan inJESD22-A108 [75].Even before introducing BED analysis, inference of the first constructed probabilisticmodel can concretely demonstrate previously-discussed challenges with the HTOL RDTanalysis. An equivalent qualification approach to the HTOL RDT method is conducted,using a pessimistic prior belief on A of N(13.5, 1) and fixing Eaa to the assumed value1699.1. High Temperature Operating Life Test Utility AnalysisFigure 9.2: Graphical representation of the Arrhenius temperature acceleration modelwith time dependence to obtain degradation observations at the end of HTOL. Brentminimization is used to solve the inverse equation for time to compute chip lifespan.of 0.7eV. A successful HTOL test result is assumed, consisting of pass observations for3 lots of 77 chips (represented by zeros). Computational Bayesian inference of the prob-abilistic model is conducted, conditional on the test success data (note that importancesampling is used instead of NUTS due to the discrete observed variable making NUTSan inappropriate choice), after which a Q99%-LBCI of approximately 9 years is obtainedwhich satisfies the 8.865 years requirement. This lifespan prediction is dependent on theprior distribution for the hyper-latent A and on the scaling factor in the model sigmoidfunction (adjusting the amount of aleatoric uncertainty in the model), but these quan-tities are made explicit within a Bayesian framework and so can be contested if needed(whereas dependencies are implicit in the assumptions of the binomial limit theorem inthe frequentist RDT case). These dependent quantities are tuned here to yield a posteriorlifespan that almost matches yet exceeds the HTOL RDT prediction, i.e., conservativeequivalence.To demonstrate the problem with assuming the value of Eaa in an RDT, considernow introducing a very small amount of epistemic uncertainty to the prior for Eaa suchthat Eaa ∼ N(0.7, 0.005). To be absolutely conservative, the prior for A is also changed1709.1. High Temperature Operating Life Test Utility Analysisto N(13.5, 0.9) to compensate, resulting in an overall reduction in prior uncertainty as tothe product lifespan. Despite lower overall prior predictive uncertainty, after repeatingthe inference procedure given a successful HTOL test the posterior Q99%-LBCI is now8.52 years, which does not meet the 8.865 year requirement. From a practical standpoint,the amount of testing required to reduce prior epistemic uncertainty regarding Eaa towithin a standard deviation of 0.005eV in the first place would be very challenging toachieve for a new product or fabrication process, thus in most real-world applications thisposterior lifespan prediction is still likely to be overly optimistic. The conducted analysisis summarized in Fig. 9.3, where the prior and posterior predictive lifespan distributionsof the model are shown for both fixed Eaa and after introducing epistemic uncertainty.Figure 9.3: Prior and posterior product lifespan predictions after a successful HTOL testresult is observed for fixed and slightly uncertain activation energy within a probabilis-tic Arrhenius model, demonstrating overconfidence of predictions when assuming singlevalues for wear-out model parameters.Having demonstrated the impact of epistemic uncertainty on lifespan predictions,BED analysis is now conducted identically on both of the constructed probabilistic modelsto look at the dependence of these uncertain predictions on the design parameters of anHTOL test. Prior beliefs for both models are selected to obtain effectively identical priorpredictive lifespan distributions that are weakly informed so as to have high variance.For this study, instead of defining a single overall utility function, the utility measureswill be considered in detail individually, including EIG, RPP, and VIG. The developedarbitrary utility predictive BED algorithm from Sec. 8.3 is used for both models, thoughit is important to note that the pass/fail model does not include aleatoric uncertaintyin its latent variables. This was a necessary omission, as compressing the observationspace to binary values compromises the estimates of the latent marginalization algorithm1719.1. High Temperature Operating Life Test Utility Analysispresented in Sec. 8.4. The likelihood p(y|v,x, d) is high if f(x,v) = y but low otherwise(since y is discrete), and so the particular sampled values v aren’t important in manycases due to the loss of fidelity. Since the conditional probability p(v|x, d) is maximizedwhen all samples v are close to zero, which is more likely when xσ is small, these regionsof insensitivity of f(x,v) to v cause the aleatoric uncertainty to collapse towards zerofor many samples y due to the algorithm bias. This does identify a limitation of thedeveloped latent marginalization algorithm, but is closely linked to a more fundamentalissue with zero failure and binary fail state testing; virtually no information on aleatoricuncertainty can be gleaned if ALTs are specifically designed to eliminate all variabilityin observed data regarding LTR. Note that CBI via NUTS also fails in this case due tothe discrete Bernoulli distribution used for the observed variables.For the degradation-based model, the maintained fidelity of the observed variablespace allows for effective use of the latent marginalization algorithm and so the full SPMarchitecture can be leveraged with reasonable computational efficiency to perform BEDanalysis with consideration for aleatoric uncertainty in latent variables. The outer BEDalgorithm functions fine with non-hierarchical models and binary observed variables,therefore the pass/fail model can still be analyzed so long as latent aleatoric uncertaintyis avoided. In the computational estimates for each test design d, the pass/fail model uses10,000X samples and 10,000 Y samples. The degradation model uses only 1,000 samplesforX and Y , but also marginalizes over an additional dimension of 250 V samples. Thisis a tradeoff since the variance of the utility measure estimates for the pass/fail model aremuch lower than for the degradation model but do not consider group-level variability.The effective sample sizes for the degradation model BED analysis are certainly muchlower than desired and future work is much needed to design improved BED algorithmsfor efficient analysis of hierarchical models, but for a first approach where no comparablesolution was identified the implemented BED and latent marginalization algorithms allowfor rough analysis of a remarkably high-dimensional model in a reasonably performantmanner (the observation and latent spaces containing 231 and 235 variables respectively).It should also be noted that low effective sample sizes are more easily tolerated in a BEDcontext where all designs are considered in relation and so overall patterns in the testdesign space can be identified even with higher estimate variance. In the CBI case whereresults need to be more precise the computational load is drastically reduced and so lowvariance estimates are achievable.With the BED framework set up, the test design space is selected to investigate thetest utility impact of both test duration and the use of multiple stress temperatures.Additionally, the differences between the two probabilistic models are highlighted, illus-1729.1. High Temperature Operating Life Test Utility Analysistrating how the choice of response variable (observing a pass/fail state versus a level ofdegradation) can significantly impact test value. A total of 60 test designs are evaluatedvia the developed BED framework for both variants of the Arrhenius model, requir-ing 23 hours on a modern 48-CPU compute node (analysis time is dominated by thedegradation model due to the aforementioned high dimensionality and associated latentmarginalization).The first four test designs were designed to address the original motivating questionposed by industry in Sec. 1.7.4 as to the consequences of reducing the duration of HTOLby half. The test designs are identical except for test duration, evaluated for 100, 500,1000, and 2000 hours with estimated utility measures for each plotted in Fig. 9.4.Figure 9.4: Estimated test utility measures of HTOL variants where test duration ismodified, evaluated for both pass/fail state observation and parameter degradation ob-servation models.From an information gain perspective, the effect of test duration on EIG and VIG ispronounced in the pass/fail observation model but is mostly insignificant in the degra-dation model (when measurement variance is reasonably low, such as here). The VIG inthe degradation model only decreases slightly in longer tests as the magnitude of degra-dation increases relative to measurement noise. With pass/fail observations the durationnoticeably increases both EIG and VIG, though EIG saturates quickly. This is explainedby the higher probability of observing failures in longer tests, whereas shorter tests are1739.1. High Temperature Operating Life Test Utility Analysisexpected to see zero failures and thus a less informative/surprising result. A similarbehaviour could be expected in a much longer test where all chips are likely to fail andthus less information is expected. The increased EIG and VIG in the 1000 and 2000 hourtests results from the larger range of likely test results, with less knowledge as to whetherzero, some, or all failures may occur.The experimental utility picture is different from a predictive Q99%-LBCI and as-sociated RPP perspective (based on the 8.865 year reliability requirement). For thedegradation model the expected Q99%-LBCI and RPP increase in longer tests since itbecomes easier to distinguish outcomes that indicate very high reliability (low degrada-tion rates are likely to be discounted as measurement noise in shorter tests). For thepass/fail model, however, the expected Q99%-LBCI follows a root-like behaviour w.r.t.test duration while the RPP increases sharply as a zero-failure result becomes sufficientto qualify reliability but saturates afterwards. Additionally, the overall higher EIG andexpected Q99%-LBCI reliability estimates for the degradation model illustrate why highfidelity of the observed variable space is important, as binary pass/fail test observa-tions generally result in a loss of information. Note though that the increased EIG ofthe degradation model is partially attributable to the increased number of hyper-latentvariables.To summarize, this BED analysis reveals that the answer to the question, “Whatare the consequences of halving HTOL test duration?” depends on both the type ofmeasurements taken (response variables) and on the test objective. If an RDT qualifica-tion approach is used without changing the required lifespan, reducing the test durationcompletely eliminates the possibility of ensuring sufficient reliability. If degradation ismeasured instead, with reasonably low noise in order to simply characterize wear-out,the consequences are relatively insignificant with only a small improvement to the ex-pected reliability metric in longer tests. The only observed advantage of the pass/failmodel approach is the suppression of measurement error, leading to higher RPP valuesin the nominal 1000-hour test than the degradation model which needs to distinguishsufficient reliability from measurement luck. Future work to look at how these utilitymeasures vary with measurement noise in the degradation model would further elucidatethese behaviours, as currently the latent marginalization algorithm limits the magnitudeof measurement noise that can be introduced without compromising estimate accuracy.Further test designs split the HTOL test into three sub-tests that are each subjectedto different stress temperatures to evaluate the potential benefits of test designs thatmake use of multiple stress conditions. Each sub-test contains 3 lots with 26 chips each,for a total of 234 chips. The resulting test design space has three dimensions, each with1749.1. High Temperature Operating Life Test Utility Analysiseight possible temperatures T ∈ [25°C, 50°C, 75°C, 100°C, 115°C, 125°C, 135°C, 150°C] (fora total of 56 combinations without replacement). The evaluated design points are shownin the estimated EIG plot for the pass/fail model in Fig. 9.5. As 3D projections canbe difficult to interpret, key values for the remaining utility measures are summarized inTable 9.1 and trends are discussed.Figure 9.5: Expected information gain estimates across the three-dimensional test designspace of multi-stress HTOL variants. The highest EIG of 2.524 nats is seen with sub-testtemperatures [100°C, 125°C, 150°C].Table 9.1: Maximum utility measure designs out of the multiple temperature HTOLvariants and comparisons to base HTOL.Model Measure Max Multi-Temp Design Max Value Base HTOL ValuePass/fail EIG 100°C, 125°C, 150°C 2.524 nats 1.520 natsPass/fail RPP 115°C, 125°C, 150°C 47.8% 47.0%Degradation EIG 50°C, 125°C, 135°C 6.729 nats 6.607 natsDegradation RPP 115°C, 125°C, 150°C 43.1% 24.9%Notice that all the maximum value designs are similar to each other if not identi-cal, and the slight differences can be mainly attributed to BED estimate variance. Alldesigns retain high overall sub-test temperatures but with significant spread across thevalues. For the pass/fail model, similar trends to the those observed in Fig. 9.4 can beobserved, in that all estimated utility measures decrease when lower temperatures areused, and the maximum RPP saturates at a max value dependent on the prior probabilitythat the product is sufficiently reliable. For most multi-temperature designs, however,1759.2. Illustrative Electromigration Qualification Procedurethe estimated EIG is much higher than in the base HTOL design. Essentially, the baseHTOL test is effective at eliminating the possibility of poor reliability (given a zero-failure result), but learns little beyond excluding the low-reliability region. In contrast,the degradation model estimated EIG is relatively invariant to the temperatures usedand the majority of differences can be attributed to BED estimate variance. This is mostlikely due to the tradeoffs between learning about temperature dependence Eaa by usingmultiple temperatures versus testing many samples under identical stress to learn aboutthe inherent aleatoric uncertainty hyper-latents Aσ and Aς . When looking at RPP inthe degradation model, however, the use of sub-tests with different temperatures signif-icantly increases the RPP in the majority of designs. This improvement is explainableby considering the drawbacks of EIG discussed in Sec. 7.2.3. Though test utility basedon EIG is valuable for reducing epistemic uncertainty, for qualification the objective isto reduce uncertainty in specific regions of the posterior predictive, which in this specificscenario requires focusing on learning about Eaa more than Aσ and Aς . This concretelydemonstrates the importance of using predictive BED analysis approaches in reliabilityqualification over utility definitions based entirely on information gain.A final comment is that, like in the discussion regarding test duration, the degradationmodel has significantly higher estimated expected Q99%-LBCI and EIG than the pass/failmodel across the considered multi-temperature test designs. By monitoring degrada-tion instead of chip-level pass/fail state, the ALT is slightly less useful for eliminatinglow-reliability outcomes but is significantly more effective at characterizing wear-out be-haviours in the region of sufficient reliability. For pure qualification purposes, pass/failmeasures may be sufficient in ALT testing (though still must be conducted within anuncertainty-aware framework as evidenced earlier in this study), however for characteri-zation it is important to monitor response variables that provide more information thana binary value. Additionally, it should be noted that this study uses the single-activationArrhenius model, which prohibits the possibility of multiple mechanisms with differencesin stress-dependent behaviour. Characterization efforts are crucial in ensuring that fielduse reliability is not primarily limited by different mechanisms than those exacerbatedby ALT designs, which would invalidate the use of such a simplistic Arrhenius model.9.2 Illustrative Electromigration Qualification ProcedureA second study demonstrates how the developed BED analysis framework is integratedinto a semiconductor reliability qualification flow. Though the constructed example isrestricted to a single mechanism, EM, with small sample sizes and limited test design1769.2. Illustrative Electromigration Qualification Procedurespace in order to reasonably constrain scope, discussion is provided at the end as towhat changes and future work are needed for industrial scale applications. Consider thedevelopment of a new product where EM reliability is to be qualified. The following qual-ification steps are conducted within this study (in close alignment with a recommendedprocedure for generic experimental design problems given in Sec. 1.4 of Montgomery’stext [243]):1. Formally state relevant reliability requirements.2. Identify constraints on test capabilities and resources, choose product parametersthat can be measured.3. Select PoF models and construct corresponding probabilistic formulations. Inte-grate knowledge to specify prior beliefs for these models.4. Evaluate incremental test costs, risks, and objectives to determine utility measures.Complete a BED analysis to estimate these measures.5. Perform post hoc tuning of a utility function to finalize the ALT design. Executethe designed test and collect measurements.6. Inference the PoF models on the ALT observed data. From the posterior beliefs,determine if requirements are met.To begin, a common lifespan requirement of 10 years is selected, and the requiredprobability of a given part exceeding that lifespan will be based on the InternationalElectrotechnical Commission’s SIL3 electrical functional safety specification of less thana 0.1% probability of failure on demand [273]. This requirement can be formulated in aBayesian statistical context as a minimum Q99.9%-LBCI of 10 years at an assumed fielduse temperature for the product of 330K. No further requirements are imposed for thisstudy.The next procedural step is to constrain the ALT design. As EM is quite well under-stood from a physics perspective and occurs at a macroscopic scale, overall epistemic andaleatoric uncertainty is typically lower than for the other key semiconductor reliabilitymechanisms. For this reason, assume a fixed quantity of 15 chips have been allocatedfor EM qualification testing, and that epistemic uncertainty regarding temperature de-pendence is sufficiently low to de-prioritize. The ALT design will instead focus on EMvoltage dependence and inherent aleatoric uncertainty in the new product (perhaps un-certain due to some design tweaks in the process or power supply network design), andit is determined that three sub-tests will be conducted at different voltages and a fixed1779.2. Illustrative Electromigration Qualification Procedurestress temperature of 400K. The nominal supply voltage is 0.85V with an absolute max-imum voltage rating of 1.1V, and the 15 chips are divided equally between the sub-tests.Regarding measured parameters, the product design includes five EM surrogate test linesper chip that can be stressed beyond the maximum designed current in any functionalinterconnect by a factor of 5x. Two assumptions are introduced, stating first that thisfactor of 5x is close to exact, and then that the functional interconnects have an equiv-alent or better reliability distribution than the smaller set of test lines under 1x currentstress at field use conditions. Given these assumptions, the test line failure times, TTF,can be kept reasonably short with 5x current stress and thus used to infer the EM modelvia test-to-failure ALT design.Selection of a PoF model is relatively straightforward given wide acceptance of Black’smodel of EM, provided previously in Eq. 1.4. Current density J will be computed forthis model according to a transistor saturation current with amalgamated scaling term Ioand supply and threshold voltages VDD and Vth, multiplied by the number of transistorfins Nfins (controlled to scale the current stress between 1x and 5x):J = Nfins ∗ Io ∗ (VDD − Vth)2 (9.2)Inherent aleatoric uncertainty is added to the current/voltage dependence latent vari-able n at both the device and chip levels (hyper-latents nσ and nς) to capture potentialimpacts of process variations on EM behaviour. Additionally, a small external measure-ment/failure component to aleatoric uncertainty is introduced to TTF to represent noisesources such as stress fluctuations. The product-level lifespan predictor used to computemetrics is set to be equal to the minimum TTF across the five test lines. Prior be-liefs for the four hyper-latent variables are arbitrary given the hypothetical process andproduct, but scaled to have the three hyper-latents regarding latent variable n be con-sidered weakly informed. The prior on Eaa only contains a modest amount of epistemicuncertainty accordant with the assumption of sufficient knowledge regarding tempera-ture dependence to de-prioritize it in the test design. The full probabilistic model isrepresented graphically in Fig. 9.6.Utility for the ALT design balances the objective of qualification against the onlyunfixed test cost variable of test time. The RPP with respect to the 10-year Q99.9%-LBCI target is one key utility measure, and the other is expected test time, which iscomputed as part of the BED analysis by introducing a new utility measure based on theexpectation of the maximum failure time across the five EM test lines:ETTFmaxp(y|d) = Ey∼p(y|d)[maxy] (9.3)1789.2. Illustrative Electromigration Qualification ProcedureFigure 9.6: Graphical representation of the surrogate test line electromigration model formulti-voltage, test-to-failure ALT design and lifespan prediction.Overall utility is defined as some weighted difference of the RPP and ETTFmaxp(y|d) mea-sures; the exact weightings are left to be determined after the BED analysis is completedand results examined. The BED analysis dimension parameters are set to 1,000 samplesfrom p(x), 250 from p(v|x, d), 1,000 from p(y|d), and then a test design space D of size56 is constructed using discrete VDD ∈ [0.85V, 0.9V, 0.95V, 1.0V, 1.05V, 1.1V ] for each ofthe three sub-tests (then taking all combinations with replacement). As discussed in thefirst study of Sec. 9.1, these sizes are smaller than desirable, leading to higher utilitymeasure estimate variance and incomplete test design space exploration of interpolationregions, but are necessarily constrained by the current performance of the implementedcustom latent marginalization algorithm. The resulting BED analysis takes just over 12hours on a modern 48-CPU compute node to complete, providing the utility measureestimates plotted in Fig. 9.7.1799.2. Illustrative Electromigration Qualification ProcedureFigure 9.7: Estimated utility measures of RPP and expected test time across the three-dimensional test design space for EM qualification.A clear trend can be seen in the expected test time plot, with lower voltages leadingto longer expected test times as one would anticipate. No clear trend is observable inthe RPP values due to a combination of a relatively narrow range of values (a span of0.266) and relatively high variance resulting from the less than ideal number of samplesizes used to construct the estimates. No assumptions are made to discount the RPPvalues, however, and the utility function design proceeds given the estimates.Given that test results will be simulated, there are no true time costs in this example.For purposes of demonstrating why post hoc tuning is preferred to freezing the utilityfunction prior to BED analysis, weighting is determined through reasoning that the RPPestimates seem subject to significant random variance, however the values can not bediscounted entirely given the complexities of a 3-dimensional test design space and PoFmodel preventing easy elimination of a null hypothesis of test design having no effect onRPP. Perhaps some genuine effect is present but is simply not easily intuited. As such,each 0.1% improvement to estimated RPP is arbitrarily considered to be worth fouradditional hours of expected test time. The utility function itself is thus dependent onnot just the main input design d, but also the reference design with a minimum expectedtime of 533 hours and an associated RPP of 27.8%. Utility is then computed accordingto Eq. 9.4, where a test design with equal RPP but a reduction of four hours providesthe same utility as a design with the same expected duration but an RPP improvementof 0.001. The reference design therefore has zero utility.U(d) = 1000(RPP− 0.278) + 0.25(533− ETTFmaxp(y|d)) (9.4)1809.2. Illustrative Electromigration Qualification ProcedureEquipped with this utility function, all but four designs have utility ≤ 0, and the over-all highest utility gives dopt = {1.05V, 1.1V, 1.1V }. This test is carried out via simulationto obtain results for inference; three separate simulations are conducted with different“true” reliability models (i.e., fixed hyper-latent variables values) that represent poor,barely acceptable, and high reliability realities for the product. Fig. 9.8 shows the exactdistributions for the simulation models in comparison to the prior beliefs and reliabilityrequirement.Figure 9.8: Underlying “true” reliability distributions for each of the three simulated EMmodels. The prior predictive and reliability requirement are included for context.Figure 9.9: Posterior reliability distributions and metrics for each of the three simulatedEM models in comparison to the required reliability and prior distribution.The NUTS MCMC algorithm is used to conduct CBI of the model on each of thethree simulated datasets, requiring 25 seconds per inference on a six-core Intel© i5-12400processor. The posterior predictive lifespan distributions in each scenario and computeduncertainty-aware Q99.9%-LBCI lifespan metric are shown in Fig. 9.9. Although themodes for all three distributions are above the 10-year requirement, both the poor andbarely acceptable simulation data scenarios result in posterior beliefs that do not meet1819.2. Illustrative Electromigration Qualification Procedurethe required reliability, and even the high reliability scenario results in a posterior thatbarely meets the requirement. This outcome demonstrates the importance of both se-lecting sample sizes in ALT designs and considering epistemic uncertainty as part of LTRqualification. With larger sample sizes (or more precise prior knowledge) the uncertaintyin the posterior distributions would be reduced, but for the conducted qualification pro-cess confidence will not be high enough to claim sufficient reliability for SIL3 functionalsafety applications [273] in a majority of scenarios that can be expected under the prior(this was also previously indicated by the RPP estimates all lying below 50%). In scenar-ios where the reliability is sufficient even when accounting for this epistemic uncertainty,the Q99.9%-LBCI can then be reported as evidence of this fact to regulatory bodies. In anenvisioned ideal market regulation scenario, the reliability requirements and PoF modelselection steps in the conducted procedure would be pre-determined by a regulatory body,then prior beliefs and test data would also be reported to permit reproducibility and au-dits. The resulting regulated procedure would make statistical manipulation significantlymore challenging than in existing qualification standards, helping to discourage and/ormitigate such attempts.A brief discussion of scalability is warranted given that the conducted qualificationprocedure is smaller in scope and complexity than many envisioned industrial applica-tions would require. Complexity in many areas, such as test design and resource costconsiderations, is reduced for brevity as opposed to technical limitations, and is moreeasily introduced when tackling real-world complications in comparison to imagined sit-uations. Some considerations that were explicitly left out of scope, such as multiplemeasurements per device per test and non-constant stress conditions, will require fu-ture work to integrate into the SPM architecture. Many scaling dimensions are alreadyaddressed by the developed framework, successfully handling high lot, chip, and devicecounts up to industrial HTOL scale, multi-mechanism PoF models, and large discretetest design spaces. Most individual dimensions are either expected or observed to scalewell, though when considered in combination computational performance certainly be-comes a limitation. Aforementioned future work towards efficient BED algorithms basedon gradients can reasonably be expected to improve far beyond the relatively simplisticIS approach used in this research work and help alleviate these scalability concerns overtime.1829.3. Optimized Characterization of Per-Mechanism Sensor Test Chip9.3 Optimized Characterization of Per-Mechanism SensorTest ChipA final study is conducted to join the various components of the presented research effortinto a unified whole, conducting a characterization study of multiple wear-out mechanismsusing the sensors developed and physically implemented on the TC1 12nm test chip inPart I. Since the designed chip is not intended for productization, focus is placed oncharacterization rather than qualification to illustrate the use of Qx%-HDCR expectedwidth and EIG for ALT design. No reliability requirement is imposed; the objective is tomaximize the information gained regarding both the PoF model itself and the predicteddegradation under field use conditions. Consequently this final study does not furtherdemonstrate the cost- or risk-based ALT optimization capabilities of the BED frameworkand instead focuses on application of predictive BED to a real-world experimental settingthat incorporates the sensor designs from Part I for developing lifespan predictions underdifferent field use conditions.This scenario uses a complex PoF model definition incorporating four separate wear-out mechanisms: NBTI, PBTI, p-HCI, and n-HCI. The response variables (i.e., the testobservations) are selected to be the outputs of the standard bias RO-based sensors fromSec. 2.2 and induced offset voltage sensors described in Sec. 2.3, each with their fourvariants corresponding to the individual wear-out mechanisms. The BTI mechanismsand HCI mechanisms are represented using the empirical models from Eq. 1.1 andEq. 1.2 respectively, resulting in a total of 16 latent variables (the HCI drain-to-sourcevoltage dependence is kept constant for simplicity, like in the case study in Sec. 6.4.2).Due to the high complexity of the PoF model, the small number of test chips, andcomputational demand of the latent marginalization algorithm described in Sec. 8.4,this study only looks at mean degradation and does not model inherent mechanismvariability. The resulting hyper-latent space has 16 variables, and the latent variablescontain no aleatoric uncertainty (the model is effectively naive). Though the benefits ofthe novel SPM architecture in multilevel variability analysis and fully separable epistemicuncertainty are not available, they would be difficult to utilize given the sparse testdata that can be obtained, and the immediate benefits of probabilistic models discussedin Sec. 4.3 are still realized. To relate degradation to the sensor outputs, the fourmechanisms are incorporated into deterministic models of degrading transistor Vth, whichare subsequently used within circuit-based models of oscillation frequency and voltagegain for the RO-based and induced offset sensors respectively. The resulting observationspace has eight observed variable types, four variants for each of the two sensors, and1839.3. Optimized Characterization of Per-Mechanism Sensor Test Chipeach type is duplicated five times per chip for a total of 40 observed variables per chip.Finally, the chip lifespan is arbitrarily defined by the time at which the modelled PMOStransistor Vth surpasses 110% w.r.t. the initial value (an industrial chip for productionwould allow for lifespan to be defined in accordance with product requirements), whichis calculated using the parallel Brent minimization algorithm from Sec. 5.3. FinFETlifespan under field use conditions is assumed to be limited by PMOS following insightsfrom the sensor evaluations and existing literature [37]; this assumption allows for thePoF model to be separated into two fully independent probabilistic models to drasticallyimprove the sample efficiency of computational BED analysis, one for the NMOS sensorsand one for PMOS. Modifying this lifespan definition would impact any predictive utilitymeasures in the upcoming BED analysis (as explained in Sec. 7.3), however measuresbased on hyper-latent information gain would be invariant. Intentionally pessimistic priorbeliefs for the 16 hyper-latent variables are lightly informed by both JEDEC’s JEP-122Hguidelines [49] and rough insights from the sensor evaluations, merging two sources ofhistorical knowledge together to guide the analysis. The full PoF model is representedgraphically in Fig. 9.10, simplified by removing the various deterministic parameter andstress condition nodes for visual clarity and to emphasize the primary compute paths ofthe model.The available test design space is kept simple due to real-world requirements, con-taining no cost considerations and bounded by hard constraints on time, stress condi-tions, and available chips that can be tested simultaneously. Two of the custom testsystems (described in Sec. 3.2) are available to test two chips each, thus only twosets of stress conditions can be used and must be shared by the two chips in eachsystem. Stress conditions of temperature T , voltage VDD, and time in hours th arelimited by the test system, chip specifications, and real-world project timeline respec-tively, leading to ranges T ∈ [30°C, 130°C], VDD ∈ [0.8, 1.0], and t ∈ [0, 730], with 730hours corresponding to the mean duration of a month. To yield a set of specific testpoints that is computationally feasible after permutation, the following possible valuesare considered: T ∈ [30°C, 55°C, 80°C, 105°C, 130°C], VDD ∈ [0.8, 0.85, 0.9, 0.95, 1.0], andt ∈ [130, 330, 530, 730]. All possible combinations of the three stress variables for eachof the two boards in considered, for a total finite test design space D of 5050 tests (100permutations per board, 2 boards, combinations with replacement). For all test designs,field use conditions for computing chip lifespan are set to be VDD = Vnom = 0.8V andT = 330K in line with earlier case studies.1849.3. Optimized Characterization of Per-Mechanism Sensor Test ChipFigure 9.10: Simplified graphical representation of the four-mechanism PoF model usedto represent the TC1 chip wear-out sensors for the characterization study.With the PoF model, prior beliefs, and test design space defined, a BED analysiscan be conducted. Experimental utility in this study focuses on learning about themodel hyper-latents and lifespan directly rather than on ensuring a minimum lifespan,thus the Q90%-HDCR expected width is leveraged instead of a measure based on LBCI(in particular, HDCR computed using log lifespan to avoid favouring tests that elimi-nate the possibility of very high reliability rather than trying to pinpoint the lifespan).Since lifespan is assumed to be PMOS limited, an experimental utility definition purelybased on minimizing the Q90%-HDCR expected width would ignore the PBTI and n-HCImechanisms entirely. Conversely, if only EIG is considered, test optimization will prior-itize learning about model parameters with high uncertainty and ignore the sensitivityof lifespan with respect to individual model parameters. A balance between traditionaland predictive BED metrics is therefore desirable for effective model learning. For thepurposes of this illustrative case study experimental utility is defined in Eq. 9.5; equalweighting is given to the EIG and HDCR width factors by inverting and matching the1859.3. Optimized Characterization of Per-Mechanism Sensor Test Chipmean and variance of the Q90%-HDCR expected width distribution to the summed EIGdistribution of the two separable NMOS and PMOS probabilistic models, denoted theNEWQ90%−HDCR.U = (EIGp + EIGn) + NEWQ90%−HDCR (9.5)Note that since epistemic and aleatoric uncertainty are not fully separated in the de-fined naive PoF model, measures of EIG can be imperfect. Poorly calibrated prior beliefs(i.e., overconfident or wildly incorrect) coupled with the naive homoscedastic measure-ment variability could possibly lead to BED results that favour tests that reduce observedvariability, as high variability could “leak” into the hyper-latent variable estimates. Thepotential dependence is minimized here through reasonable choices for priors and ob-servation variance, so is not expected to impact results, though the issue still directlyillustrates the benefits of separating aleatoric and epistemic uncertainty within SPMsas a result of this caveat with regards to experimental utility. Future work to designand implement more sophisticated computational BED algorithms is needed to makeBED analysis of complex, multi-mechanism PoF models leveraging the developed SPMarchitecture computationally feasible.The custom computational BED algorithm described in Sec. 8.3 is run on the twoprobabilistic models with 10,000 observation samples and 20,000 hyper-latent samplesfor each d ∈ D. On a modern 48-CPU compute node the analysis takes approximately 19hours to complete; over 1 trillion individual PoF model sample points are evaluated. Theidentified optimal design dopt is T1 = T2 = 130°C, th1 = th2 = 730, VDD1 = 0.8V , andVDD2 = 1.0V , with an estimated utility of 33.94 (an EIG of 17.64 nats and a normalizedestimated posterior Q90%-HDCR expected width of 16.30). A two-dimensional slice ofutility estimates near the optimum for the test design space is plotted in Fig. 9.11, wheredopt is seen in the top left. Notice that utility generally increases as the difference in stressconditions between Board 1 and Board 2 increases. This quantitatively motivates ALTdesigns with more than one stress point over conventional tests, supporting qualitativearguments in the existing literature [84, 176]. It is also valuable to note, however, thata large difference in both temperature and voltage (bottom left point) provides lessutility than the more moderate midpoint or a large difference in just voltage, which arereasonable trends to expect since the maximum difference results in less degradationcompared to noise and the cause for differences in observed wear-out cannot be as easilyattributed to a single stress condition if both temperature and voltage are varied.Given the defined utility function, dopt is notable in that it uses the same stresstemperature and duration for both boards, sacrificing information about the temperature1869.3. Optimized Characterization of Per-Mechanism Sensor Test ChipFigure 9.11: Two-dimensional slice of the six-dimensional test design space showing es-timated utility from the TC1 characterization BED analysis. All stress conditions forBoard 1 and test duration for Board 2 are fixed in the plot.and time dependence of BTI and HCI in order to maximize learning about the voltagedependence. In this particular analysis the design is optimal even when EIG or Q90%-HDCR expected width are considered in isolation, suggesting that the magnitudes ofuncertainty in the model hyper-latents are reasonably well specified with regards to theirimpact on log lifespan. This makes a certain amount of sense considering that theirranges are informed by previous observations, thus their prior uncertainty correspondsto the degree of precision that can be inferred from measurement. Computing a Pearsoncorrelation coefficient between EIG and Q90%-HDCR expected width across all 5050analyzed designs gives a value of 0.87, indicating that the two measures are quantifyingsimilar but not equivalent definitions of utility in this study.The resulting test design dopt is carried out experimentally on the implemented sen-sors. Four fresh chips are soldered to two automated ALT system host boards, which arethen connected to the control boards and test specifications are loaded via USB from anin-lab driver computer. Once started, the full 730 hour test requires no further manualinteraction; the two test systems automatically stress and measure the test chips, performlive data uploads, and notify the user of test completion via email. Following the month-long test, data is retrieved from the database and formatted for CBI. Model inference1879.3. Optimized Characterization of Per-Mechanism Sensor Test Chipon the experimental data is conducted via the NUTS algorithm, requiring approximatelyone minute on a six-core Intel© i5-12400 processor. Prior and posterior hyper-latentdistributions with corresponding entropy reductions (i.e., information gain) are shown inFig. 9.12; associated predictive lifespan distributions are shown in Fig. 9.13.Figure 9.12: Prior and posterior hyper-latent variable distributions and interpretableentropy values for the four-mechanism degradation model of the TC1 12nm test chip.1889.3. Optimized Characterization of Per-Mechanism Sensor Test ChipFigure 9.13: Prior and posterior predictive lifespan distributions for PMOS sensors in acustom 12nm test chip.A significant overall reduction in uncertainty can be observed in the figures. Keypoints to notice in Fig. 9.12 are the large posterior shifts in voltage dependence variables(α for BTI, u for HCI), the lower than expected actual IG from inference (10.46 nats),and the minimal reduction in entropy for the temperature and time dependence variables(Eaa and n for BTI, α and β for HCI). The former feature is attributable to the largervoltage dependence required for an equivalent output shift since supply voltages are re-duced in modern fabrication processes. Priors informed by JEDEC recommendationsare influenced by older processes where a 1.25x increase in voltage was a larger absolutedifference, whereas in the 12nm FinFET process a 0.2V supply shift produces a largerrelative impact on degradation. Prior beliefs can be expected to be more well calibratedin industrial applications given better access to existing data than in this study. Asidefrom raw luck, the second point of lower than expected EIG is likely partially attributableto the prior underestimation of voltage dependence, thus the BED analysis did not sam-ple heavily in the posterior region. The sophisticated NUTS algorithm used for CBI isimpressive in that it still effectively finds the probable posterior region for nHCIu thatis very unlikely under the prior, thus provides significant resilience to poor prior beliefsduring CBI. Additionally, the lower than expected EIG may be partially due to the highheteroscedastic induced offset sensor variance discussed in Sec. 3.3.3 that was not ableto be incorporated into the model due to computational complexity constraints (as dis-cussed earlier in this section, directly learning the sensor-to-sensor variance would requirere-introduction of numerous device-level latent variables and drastically increase modeldimensionality). This possibility further motivates the need for future work on BEDalgorithms for computationally efficient analyses. Significant quantitative information1899.3. Optimized Characterization of Per-Mechanism Sensor Test Chipwas still obtained from the experiment, however, that indicates good overall reliability atfield use conditions but a Q90%-HDCR that still extends significantly below the 10-yearmark and over approximately three orders of magnitude, as seen in Fig. 9.13. In anindustrial qualification scenario this high degree of residual uncertainty would likely leadto insufficiently confident predictions, thus further testing following a procedure morein line with the previous qualification case study in Sec. 9.2would be necessary. Thefinal point of note in Fig. 9.12 is that very little is learned regarding temperature andtime dependence variables Eaa for BTI and β for HCI. This was anticipated given thatdopt only uses a single temperature and time stress point for both pairs of chips, insteadfocusing on reducing uncertainty regarding voltage dependence.The posterior beliefs generally agree with the insights discussed back in Sec. 3.4 asto FinFET semiconductor wear-out. Given the small number of chips available for thisexperiment, however, further studies incorporating inherent variability in probabilisticmodels, better informed priors, and larger test sample sizes are recommended for futurework to further investigate wear-out in modern semiconductor fabrication processes. Afirst agreement is that NBTI is significantly more severe in general than PBTI, and inthis study even the voltage dependence is noted to be potentially more severe. Secondis that the significant posterior voltage dependence of HCI means that it cannot be ne-glected under overvoltage conditions, even if it is not prominent during standard fielduse. This is shown in the predicted PMOS Vth degradation distributions of Fig. 9.14,demonstrating how analysis of LTR benefits from multi-mechanism PoF models that cap-ture how reliability may shift across varied field use and stress conditions. Degradationunder different transistor stress configurations can be predicted from a single model, andhigher epistemic uncertainty and voltage dependence for p-HCI results in different rel-ative increases in the HCI-stressed degradation distribution under overvoltage field useconditions compared to BTI-stressed transistors. Without modelling individual mech-anisms, inferred voltage dependence and uncertainty would be identical regardless oftransistor stress configuration.1909.4. Part III Conclusions and Future WorkFigure 9.14: Posterior predicted Vth degradation after 10 years for PMOS transistorsunder DC BTI and HCI stress across varied field use conditions.9.4 Part III Conclusions and Future WorkWith minimal prior work on DoE approaches for LTR in the field of semiconductors[174, 218], the presented BED research contributions of this part of the dissertation rep-resent some of the earliest steps towards a more formalized perspective on ALT designas part of semiconductor wear-out qualification strategies. Contrasted with the mostcomparable prior research, the mechanism-separating ALT design methodology of Wu etal. [174], the introduced BED analysis framework follows a formal mathematical DoEframework, leverages a Bayesian perspective to allow for prior knowledge incorporation,uses predictive quantities within multi-measure utility definitions, considers engineeringrisk and costs, and is compatible with arbitrary PoF models. The developed frameworkis, to the best of knowledge, the first application of computational BED and of predictiveBED to semiconductor reliability. Beyond the specific application of semiconductors,the motivation for arbitrary utility definitions in various engineering experimental designcontexts has led to a BED framework with the capability to conduct fully computationalpredictive BED with arbitrary probabilistic PoF models. This is, to the best of knowl-edge, a significant contribution to the state of the art in the broader reliability engineeringstatistics literature [210, 259, 260]. Finally, the software algorithms introduced compriseone of the first publicly available solutions in the emerging field of computational BEDfor predictive utility measures, and no approaches similar to the latent marginalizationalgorithm in terms of design and application for hierarchical models was identified. Theresulting sum of contributions in Part III provides novel value towards helping designfirms minimize product testing costs and risks when trying to meet high reliability mar-1919.4. Part III Conclusions and Future Workket requirements and manage variability as foundries approach single-nanometre processnodes. The contributions are designed to remain applicable regardless of the specific PoFmodels, resource constraints, and engineering objectives of a given application.The conducted case studies demonstrate the suitability of the developed BED frame-work for sophisticated analysis of semiconductor ALT designs. Though scalability is asignificant challenge for future work to address, current capabilities can already supportHTOL-scale test designs, complex PoF models with internal Brent minimization, andexpansive test design spaces. Industry-posed questions on the value of HTOL were ableto be addressed from multiple modelling perspectives, test costs effectively consideredas part of dynamic ALT design optimization strategies, and physical considerations ofmultiple mechanisms and multi-level variability captured as part of these BED analyses.With the development of new tools for semiconductor reliability analysis comes nu-merous opportunities for future work. There exist numerous limitations of the developedBED framework, including bias in the latent marginalization algorithm, high compu-tational cost of the predictive BED algorithm, and lack of support for repeated mea-surements of devices or time-varying stress conditions when PoF models are translatedto programmatic forms for algorithm use. Future work to improve algorithms throughgradient-based topological methods with non-myopic sequential design capabilities wouldbe greatly beneficial towards extending the scale of problems that can be tackled withequivalent computational resources [269], and implementation efforts to improve theopen-source software library would add support for the additional desired test designfeatures. Moving from limitations to opportunities, future work towards further applica-tion of the BED framework to a wide variety of specific problems and target applicationsis important in further establishing its adaptive support for arbitrary PoF model and ex-perimental utility definitions. Finally, it is worth repeating the conclusions of Part II todrive home the importance of mature software tools in making industry adoption feasible.The complexity of computational BED and hierarchical probabilistic modelling is signifi-cant, and the foundational computer science and statistical techniques within these toolsare not widely taught to reliability engineers. Minimizing the level of expertise needed toutilize the BED framework in concert with identifying ways to introduce emerging com-putational Bayesian statistics to reliability engineers is critical for any potential adoptionefforts [274].192Chapter 10Concluding RemarksConnecting back to the key motivating factors of growing high reliability markets andincreasing variability as the industry approaches the predicted limit of raw gate lengthscaling, no single introduced tool is sufficient to tackle the incoming challenges presented.A combination of efforts across the layers of abstraction described in Sec. 1.7 is neededto provide various solutions for wear-out sensing, in-field management, improved physicsmodels, data analysis methods, uncertainty-aware predictions, qualification procedures,and ALT design. The case studies conducted in the previous chapter begin to tie togetherthe research conducted towards this dissertation, demonstrating that only when leveragedin concert can larger problems be addressed. Multi-mechanism PoF models cannot beeffectively inferred without per-mechanism sensors providing informative response vari-ables, ALT value cannot be framed in terms of expected resulting reliability predictionswithout predictive BED, and insights regarding process variations are difficult to effec-tively utilize without CBI and probabilistic multi-level variability modelling. The finalcase study in Sec. 9.3 evidences this conclusion and demonstrates the significant breadthof research contributions introduced by this dissertation. Altogether, the fine-grainedwear-out sensors were able to be used as informative response variables, with a complexprobabilistic PoF model capable of representing their outputs in terms of the contribu-tions of multiple LTR mechanisms. The successful on-chip sensor implementations, BEDframework, and computational software allowed for a test design to be optimized to learnas much as possible about the predicted LTR given few available packaged chips and testenvironment limitations. Experimental test execution was made possible by the auto-mated ALT system, after which the real-world data and software library could be usedto infer the complex PoF model and then evaluate LTR in terms of uncertainty-awaremetrics and varied field use conditions.From the on-chip sensors for isolating semiconductor reliability mechanisms to theprobabilistic modelling framework for generative modelling and inference to the BEDframework for ALT optimization, work in each solution area builds on state of the artexisting literature to introduce novel capabilities for semiconductor LTR engineering.Many other important areas were not addressed within the scope of this work, however,193Chapter 10. Concluding Remarkssuch as PoF investigations and specific tools for SLM. Where these gaps and scope lim-itations exist, presented research contributions have attempted to remain fully agnosticand configurable to allow for future research efforts to easily leverage the provided tools.Support for arbitrary PoF models, prior knowledge sources, accelerated test designs,and experimental utility definitions were all prioritized as part of this research in hopesthat the developed tools can be leveraged in a much broader range of applications thandemonstrated by presented case studies. Example potential applications include leverag-ing the on-chip sensors within in-field telemetry solutions for SLM or performing BEDanalyses to optimize tests targeting the early and operational life facets of reliability.Furthering this goal of ease of third-party adaptability, all software developed as part ofthe conducted research is public and open-source in an effort to build towards a moretransparent and cooperative semiconductor research community [223, 239] as the fieldhas historically been and continues to be relatively closed off due to concerns of tradesecret protection. This is completely understandable but not well aligned with the needsof high reliability markets where disclosure and third-party validation are necessary toensure safety.By bringing the presented contributions of this work to application in concert witheffective third-party solutions, there are three outcomes that may be achievable followingfuture efforts towards industrial adoption. First is the potential for effective uncertainty-aware lifespan metrics and dynamic optimized ALT designs to provide companies in lowreliability semiconductor markets more opportunities for competitive quality differenti-ation in terms of reliability. If standard characterization procedures and metrics canbe introduced that are challenging to manipulate, are interpretable by consumers, andeffectively evidence LTR, there is significant potential to further efforts such as France’sdurability index [34] to provide reliability metrics at point of sale. Resulting down-stream outcomes could include improved consumer protections for repairability supportand reductions to e-waste footprints. Second is improved regulatory capability for highreliability markets. If similar qualification procedures and metrics can be enforced thatare challenging to manipulate and effectively ensure reliable performance, significantimprovements to current regulatory standards, such as AEC-Q100 for automotive [29],will be feasible and support increasing semiconductor use in safety-critical tasks withoutcompromising on safety. Third and last, effective frameworks to model, infer, and charac-terize significant multilevel variability sources are expected to be crucial towards furthertransistor scaling efforts as each single-atom defect becomes increasingly impactful tooverall wear-out. Accurate foundry-provided models of device, chip, and lot variabilitycan enable designers to margin efficiently for high yield and can help pinpoint areas for19410.1. Developing Comprehensive Monitoring and Qualification Strategiesimprovement in fabrication processes. Further improved variability modelling techniqueswill be invaluable towards future semiconductor node maturation.10.1 Developing Comprehensive Monitoring andQualification StrategiesThough this dissertation has presented all of the contributions as components towardscomprehensive solutions and even provided an illustrative example of a complete qual-ification procedure in Sec. 9.2, no specific strategy is prescribed for standard use con-sideration. To fix qualification across all application markets and industrial scenarioswould be inappropriate and lead to similar limitations of fixed lifespan prediction tar-gets and predefined resource costs that were critiques of the existing standard JEDECdemonstration test approach in Sec. 1.6. Market and scenario-specific strategies are alsonot prescribed given that the research scope is not sufficiently restricted to a particularmarket or industrial scenario to identify the assumptions, desiderata, and resource con-straints that would be needed to prescribe a method. To achieve the previously listedreal-world outcomes, individual company and/or regulatory involvement in the develop-ment of strategies is necessary. This of course makes it more challenging for potentialusers to take the the research to application, as additional effort is required to adopt themore general research tools and methods of this work and adapt them to unique needs.The upside, however, is that the developed components can generalize far better to avariety of applications. The most similar existing literature on experimental design isfixed to optimizing preset stress conditions for separation of two LTR mechanisms withregards to minimizing the variance of Weibull parameter fits [174]. Other relevant liter-ature approaches discussed in the dissertation also fix most elements of their respectiveanalyses when presenting their methods, for example assuming the form of consumer-producer cost risks [253] or the PoF models and lifespan metrics to use [172]. This makesimmediate application more straightforward, but bakes in assumptions that can becomesafety risks or expensive inefficiencies if violated. In contrast, the research effort towardsthis dissertation does not assume any particular cost model, reliability requirement for-mulation, or PoF model. Additional effort was necessary to achieve this generality, butthe resulting components towards complete strategies can hopefully be leveraged acrossa broader range of high reliability markets and next generation fabrication processes. Forinstance, not only do the proposed Qx%-LBCI and Qx%-HDCR metrics specify lifespanin light of both epistemic and aleatoric uncertainty, they are also parametric regardingthe level of reliability x desired for a given market and are completely agnostic to the19510.1. Developing Comprehensive Monitoring and Qualification Strategiesform of the lifespan distribution. Similarly, the arbitrary PoF model support of the SPMarchitecture means it is equally appropriate for current fabrication processes with fourkey semiconductor mechanisms as for a future technology node where presently-unknownnew mechanisms may emerge (though provisioning of reasonably accurate PoF modelsfor new mechanisms is a prerequisite for PoF-based predictions in such processes).In lieu of naively prescribing monitoring or qualification strategies for blanket use, theanticipated steps needed to develop specific approaches for a given industrial use scenarioare broadly described to aid in bringing the developed contributions to application. Anoverview of these recommended approaches for developing monitoring and qualificationstrategies is provided in Fig. 10.1 alongside indications as to which organizations shouldbe expected to provide input for each step. First, an approach for LTR monitoringin a semiconductor product is summarized. The specific mechanisms of concern for afabrication node should be identified in consultation with the foundry (who is expected tohave identified the significant LTR mechanisms in their process). Sensors should then beselected to obtain isolated monitoring coverage for all mechanisms of concern, and sensordistribution and duplication should be determined in order to balance observation of meanmechanism wear-out versus wear-out variance. With sensor designs and a placement plan,a readout/measurement scheme should be selected or developed that is appropriate for theproduct. For example, in an SoC this could potentially be done entirely on chip, whereasfor a low-cost analog product perhaps dedicated pins may be used to expose the sensoroutputs for external manual measurement. Notice that for this roughly described strategyto construct a monitoring solution, the contributed sensors only provide componentstowards appropriate sensor selection in current semiconductor processes along with somecollected data that can be analyzed to guide placement plans. Third-party research inPoF investigations must be leveraged to identify future mechanisms, and future workitems listed in the final upcoming section are needed to develop strategies for sensorplacement and measurement.Regarding LTR qualification, the developed research components cover a majority ofthe effort needed to develop a qualification strategy based on the six step procedure usedin Sec. 9.2. First the required reliability must be defined in terms of predictive metricsand in-field use conditions considered. After this the qualification test scope, measuredparameters, and constraints should be determined. Next, PoF model(s) should be set andhistorical knowledge sources selected (or alternatively constraints on the range of possiblemodels and knowledge sources). The scope of a BED analysis should then be bounded interms of test design space and utility measures. Finally, appropriate contingency plansfor and regulatory constraints on successive testing are recommended to address the pos-19610.1. Developing Comprehensive Monitoring and Qualification Strategiessibility that the conducted qualification test yields data that is insufficiently informativeor indicative of poor reliability. There are two expected types of qualification strategiesthat could be developed, regulated standard procedures and internal assessments. Forthe former, it is hypothesized that standards would be most effective if regulators fixmany of the qualification specifics, such as PoF models, in-field conditions, and/or evenprior knowledge. Though this would be challenging given that fixed selections wouldneed to be general enough to apply uniformly across different processes, it would greatlylimit opportunities for statistical manipulation in comparison with current industrial andresearch approaches.Figure 10.1: Rough steps recommended for developing application-specific LTR moni-toring and qualification strategies using the developed research components. To whichsteps relevant organizations are expected to provide input is included.The research components of this dissertation provide novel capabilities to effectivelyaddress the outlined qualification strategy development steps along with the tools toconduct the resulting qualification. The uncertainty-aware metrics are more appropriateselections for placing general reliability requirements than FIT, MTTF, or the timing-aware yield discussed in Sec. 4.7 (as they directly consider distribution tails and are not19710.2. Directions for Future Effortsapplication specific), thus better support the rigorous levels of reliability needed for highreliability markets. Reasonable examples are provided for historical knowledge integra-tion and experimental utility measures, uniquely supporting test cost and risk reductionfor companies. The open-source software allows for procedures to be conducted withreduced technical burden and with introduced modelling of multilevel variability to ad-dress growing challenges in semiconductor fabrication. Despite addressing many aspectsof the rigorous qualification challenge, this work is certainly not a final incarnation andalso builds on significant prior research from the semiconductor reliability literature. NoPoF models are developed or recommended within scope, and future work would be ben-eficial to fully investigate how multiple in-field use conditions should be addressed by asingle qualification procedure, to develop appropriate bounds on test scope, to supportmulti-stress and repeated measurement tests, to codify methods to translate historicalknowledge into priors, to consider additional experimental utility measures, and to im-prove BED algorithms so that the scope/complexity of qualification strategies can befurther expanded beyond the constraints of this work. Nonetheless, by leveraging ex-isting PoF models, the research effort reaches a state sufficient to fully carry out thisqualification strategy development process and conduct resulting procedures under mod-erate complexity constraints, as evidenced by the case study in Sec. 9.2. This representsa starting foundation for safety critical LTR qualification on which future work can buildas the semiconductor industry pushes towards further technology node scaling.10.2 Directions for Future EffortsImportant areas for future work have been mentioned frequently throughout this disser-tation. Combining discussion from each of the three major parts of the research effort,key directions are summarized here in rough order of perceived importance. Prioritiza-tion here is with respect to the objective of feasibility for industry adoption rather thanraw technical improvement potential or research novelty.1. Maturation of the contributed software libraries is the most important barrier toindustrial use by engineers without prior expertise in Bayesian statistics and prob-abilistic modelling (which represents the majority). Without features for ease ofuse, model validation and tuning, graphical interfacing, automatic visualization ofresults, and effective selection guidance, it is unlikely that the developed SPM archi-tecture would see significant use. Educational and training tools are also includedin the scope of this direction, but momentum towards adoption would need to beachieved first through third-party use by industrial engineers.19810.2. Directions for Future Efforts2. Subsequent implementations of the on-chip sensors are necessary to refine the de-signs to optimize PPA, provide more advanced supporting circuitry, and mitigatehigh variability in the initial fabricated induced offset voltage sensors and gateleakage current breakdown sensors through implementations with larger transistorsizing. Chip design is expensive, time consuming, and benefits from experiencedteams, however, and so for a second run to significantly improve on the success ofthe first implementations it would be highly desirable for to work in cooperationwith an industrial design team.3. The current limitations of the SPM builder method (that emits defined SPMs inprogrammatic form for CBI and BED use) in terms of no support for time-varyingstress conditions or repeated measurements of a single device are relatively welldefined work items to complete. The former is expected to be more challengingand have a greater performance impact than the latter, as the time-varying stressalgorithm will have to be implemented and run for every random sample pointwithin a CBI or predictive BED algorithm. Repeated measurements likely requireadditional observed variables and so can be expected to significantly increase thedimensionality of models.4. Though already sufficient for a broad range of initial applications, the current al-gorithms for latent marginalization and arbitrary utility predictive BED are bothcomputationally demanding. The latent marginalization algorithm bias is also non-ideal and not yet characterized mathematically. Research to develop improved algo-rithms, most likely based on gradient-based variational methods, can help expandthe stability and scalability of the computational approaches to enable applicationin increasingly complex and intensive scenarios. This direction is of reasonably highpriority but should ideally match up with demand and so is somewhat contingenton increasing adoption of the algorithms in practical and demanding applications.19910.2. Directions for Future Efforts5. Applications of the research contributions to aid in developing SLM solutions wouldhelp support an emerging field that is in line with the goals of supporting high re-liability market growth and consumer product repairability. The on-chip sensorsare designed to allow for in-field data collection, and so could support wear-outtelemetry solutions. Active efforts towards this direction are underway throughdevelopment of a CPU peripheral unit for sensor fusion, reducing the CPU bur-den required to read and process sensor data through a common communicationinterface, automatic management of sensor control inputs, and preprocessing ofmeasured data. Additionally, sequential CBI using on-chip sensor data has the po-tential to enable in-field live failure forecasting and predictive maintenance, whereeach posterior distribution is used as the prior for successive inference on new dataas a product ages over time to produce increasingly precise estimates as to failurerisk.6. Investigation and optimization of on-chip sensor placement and distributed designwould be helpful to balance the desiderata of minimizing the number of sensorsrequired to accurately characterize expected wear-out, of leveraging multiple sensorsto accurately characterize variability, and of minimizing the PPA impact of wear-out sensor integration for product designs. No perfect solution will be possible, butan improved understanding of the tradeoffs would be invaluable for application-specific tuning.7. Additional practical case studies are important to demonstrating value of the intro-duced SPM architecture, CBI framework, and predictive BED framework. Ratherthan specific construction of hypothetical problems, however, more value is expectedto be had through finding ongoing research efforts where these contributions canbenefit in statistical analysis of PoF models, wear-out data, and conducted tests.This is more challenging but targets real-world situations and helps identify specificsuccesses and shortcomings that can be marked for future use or work.8. Model uncertainty in reliability predictions is important to consider but less im-portant to address until a time when the less complex uncertainties have alreadybeen captured in existing wear-out qualification and characterization methods. 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This involvesevaluating f(x) for three values of x, then performing a parabolic fit to these points tofind an estimated minimum point, which is then used as one of the three points in the nextiteration. The approach provides superlinear convergence, but under certain conditionsbased on the shape of f(x) convergences slowly or not at all. Brent’s minimization isable to identify such conditions from the three values of x and the resulting parabolicfit and under those conditions use a golden section search as a fallback approach thatprovides only linear convergence but is guaranteed to converge at a fixed rate. Thisfallback approach consists of segmenting the search interval with interior points accordingto the golden ratio, then eliminating the portion of the interval that does not containthe large-scale implied minimum. The use of the golden ratio to select values of x toevaluate ensures that no matter which portion of the interval is eliminated, the size of theremaining interval used in the next iteration has a fixed ratio to the size of the previousinterval, providing a completely constant rate of convergence. Although conceptuallysimple, Brent’s minimization method also includes many details to ensure that the exactminimum is found to within a set tolerance, that the function is never evaluated too closeto the interval edges or at two points of x closer than the tolerance, and to perform allthe required management of points of x needed to correctly update intervals.A.1 Logarithmic AdaptationPhysical wear-out mechanisms frequently follow exponential acceleration with stress con-ditions and logarithmic failure distributions. Minimization over a time range spanningmultiple orders of magnitude with a linear search, as seen in existing Brent’s methodimplementations, leads to poor precision for early failures, unnecessary detail under longlifetimes, and many iterations required to converge. From an implementation perspec-221A.2. Parallel Brent Minimization Pseudocodetive, this adaptation is extremely simple and merely requires that the algorithm proceedswithin a log-transformed space. Conversion between the logarithmic and linear spacesonly needs to occur for the input interval to search, evaluations of f(x), and the finalreturned solution x that minimizes f(x). In simple validation tests the logarithmic trans-formation can reduce the number of required internal iterations by more than 50% andallows for far larger bounding intervals with equivalent performance when f(x) containsexponential behaviour. The potential for precision loss when working in the log domainis counteracted by the built-in relative tolerance adjustment within Brent minimization,which scales the algorithm precision proportional to the magnitude of x (e.g., using timeunits of hours, ϵmin = 1e − 5, and a minimum at 100 years the maximum error actu-ally decreases from ∼200 hours to 1 hour when using the log-transformed version of thealgorithm).A.2 Parallel Brent Minimization PseudocodeBrent’s minimization method adapted for parallel execution, logarithmic search, andfinite-size compute graph compilation (for use within a FOPPL) is presented across Al-gorithms 3, 4, 5, 6, and 7. The top-level argument F is the array of procedural functionsf(x) to minimize, but in practice is a single function that accepts array inputs and itselfperforms parallel execution of all the effective function variants based on input values.This initially sounds restrictive, but through similar strategies as used for the parallelBrent algorithm itself can permit nearly arbitrary complexity. A complete pseudo-codedescription using a base-10 logarithmic transformation is provided here to aid in imple-mentation in arbitrary languages (and to clarify the algorithm, as Brent’s 1973 descriptionpasses over details and so hinders rapid adaptation and implementation [226]). ExactPython implementations can be found in the provided open-source simulator [223] andinference [239] libraries.222A.2. Parallel Brent Minimization PseudocodeAlgorithm 3 Top-level enhanced Brent’s minimization procedure.1: gold← 2− 1+√52 , ϵ32bit ← 2−242: procedure brent min(F , lower bound, upper bound, ϵmin, nmax)3: dims← dimensions of F4: a← log (lower bound) expanded to dims5: b← log (upper bound) expanded to dims6: m← a+b27: e← d← 0 expanded to dims8: x← w ← v ← a+ (gold ∗ (b− a))9: fx← fw ← fv ← F (10x)10: tol← (√ϵ32bit|x|) + ϵmin311: n← 012: vals← (a, b,x,w,v,fx,fw,fv,d, e,m, tol)13: repeat14: vals, converged← brent iter(F ,vals, ϵmin)15: n← n+ 116: until converged ∨ n ≥ nmax17: return 10valsx ,valsfx223A.2. Parallel Brent Minimization PseudocodeAlgorithm 4 Single internal iteration of enhanced Brent minimization.1: procedure brent iter(F ,a, b,x,w,v,fx,fw,fv,d, e,m, tol, ϵmin)2: use interp← |e| > tol3: p, q ← fit parabola(use interp,x,w,v,fx,fw,fv)4: use interp← use interp ∧ (q ̸= 0)5: step← get step(x,a, b,m,p, q,use interp, e, tol)6: u← x+ step, fu← F (10u)7: e← d, d← step8: a←x, (fu ≤ fx) ∧ (u ≥ x)u, (fu > fx) ∧ (u < x)a, otherwise9: b←x, (fu ≤ fx) ∧ (u < x)u, (fu > fx) ∧ (u ≥ x)b, otherwise10: m← a+b211: x,w,v,fx,fw,fv ← next points(u,x,w,v,fu,fx,fw,fv)12: tol← (√ϵ32bit|x|) + ϵmin313: converged← |x−m| < (2tol− b+m) ∀ ∈ x14: return (a, b,x,w,v,fx,fw,fv,d, e,m, tol), convergedAlgorithm 5 Fit parabola to three points within Brent minimization.1: procedure fit parabola(use interp,x,w,v,fx,fw,fv)2: ∆xw, ∆xv ←{(x−w, x− v), use interp(0,0), ¬use interp3: q1 ←∆xw(fx− fv), q2 ←∆xv(fx− fw))4: q ← 2 ∗ (q2 − q1)5: p←{(∆xv ∗ q2)− (∆xw ∗ q1), q ≤ 0(∆xw ∗ q1)− (∆xv ∗ q2), q > 06: q ← |q|7: return p, q224A.2. Parallel Brent Minimization PseudocodeAlgorithm 6 Determine distance to new point within Brent minimization.1: procedure get step(x,a, b,m,p, q,use interp, e, tol)2: far bound←{a, x ≥mb, x <m3: step←{pq , use interpgold ∗ (far bound− x), ¬use interp4: u← x+ step5: gss revert← use interp ∧ ((b < u) ∨ (a > u) ∨ (|step| > |e|2 ))6: step←{gold ∗ (far bound− x), gss revertstep, ¬ gss revert7: u← x+ step8: ab close← ((u− a) < 2tol) ∨ ((b− u) < 2tol)9: small step← |step| < tol10: step←step, ¬ab close ∧ ¬ small steptol, (ab close ∧ (x <m)) ∨ (small step ∧ (step > 0))−tol, (ab close ∧ (x ≥m)) ∨ (small step ∧ (step < 0))11: return stepAlgorithm 7 Update the evaluation points within Brent minimization.1: procedure next points(u,x,w,v,fu,fx,fw,fv)2: pre← (fu ≤ fx) ∨ (fu ≤ fw) ∨ (w = x)3: v,fv ←(w,fw), pre(u,fu), ¬pre ∧ ((fu ≤ fv) ∨ (v = w) ∨ (v = x))(v,fv), otherwise4: w,fw ←(x,fx), (fu ≤ fx)(u,fu), (fu > fx) ∧ ((fu ≤ fw) ∨ (w = x))(w,fw), otherwise5: x,fx←{(u,fu), (fu ≤ fx)(x,fx), otherwise6: return x,w,v,fx,fw,fv225Appendix BLog Domain TransformationsThere are two sources of highly exponential behaviour within the modelling, inference,and experimental design software library that necessitate the widespread use of log do-main transformations for algorithmic computation and model formulation [239]. First,since all of the key semiconductor wear-out and failure mechanisms covered in Sec. 1.4contain exponential behaviour within their empirical models, the sensitivity of failuretimes to hyper-latent parameter distributions is accordingly exponential. This is notunusual in the broader field of reliability physics either, as limits on LTR for any well-engineered product can be expected to arise from unlikely events (or sequences thereof)rather than common occurrences. The second source is the topology of probability spaces,which are frequently exponential due to the model parameter distributions and/or powerlaw dependent due to the multiplication of many individual variables within a high di-mensional model when computing joint probabilities.The described exponential and power law sensitivities and probability topologies canquickly lead to significant numerical estimation instability and errors due to the limita-tions of floating-point representations and assumptions of the algorithms used to produceestimates. To combat this, log domain tranforms can be used to drastically smooth outthe topology of probability spaces, and can also help reduce model sensitivity w.r.t. cer-tain parameters. The log domain is used extensively within the algorithms and manyof the case study models for these reasons, but in the main body of the dissertationis rarely addressed explicitly as it would add complexity and hinder readability despitenot altering the fundamental methods developed. In addition to the explicitly describedlog domain enhancement to the parallel Brent’s minimization method described in Ap-pendix A, two specific use cases for log domain transformations are discussed in detailwith regards to implementation challenges and impacts to research contributions of thedissertation. Note that in both of these use cases there is no counteraction for potentialloss of precision in the log domain, however the impact is negligible in both cases. In theprobability case all considered FOPPLs and HOPPLs already compute log probabilitiesdirectly (for reasons about to be discussed) and precision is improved when working withmore commonly seen low probability values. In the probabilistic modelling case, for all226B.1. Working with Log Probabilitiesrealistic problems, any potential precision loss is insignificant in comparison to aleatoricuncertainty and so can be thought of as a miniscule noise source that is left neglected.B.1 Working with Log ProbabilitiesLog probabilities are primarily relevant to the experimental design algorithm componentof the conducted research effort discussed in Ch. 8. Most probabilistic programminglanguages produce log probabilities by default when evaluating likelihoods, includingNumPyro [238], so no effort is required to perform the initial transformation to the logdomain. With these values, joint probabilities can be computed as summations insteadof products, and zero probability equivalently becomes a negative infinite value.Numerical stability is much higher in general when working with log probabilitiesdue to the larger range of low-probability values that can be represented using floatingpoint numbers without encountering underflow. This may not seem like a major benefitat first glance given an intuitive assumption that extremely unlikely samples should notsignificantly affect results, but when working with high-dimensional models it is commonfor every single sample to be incredibly unlikely. In these scenarios standard probabil-ity values can quickly result in zeros or accumulation of floating-point imprecision indownstream operations and lead to reductions in sample diversity or divisions by zero.Additionally, though not used in the custom algorithms based on importance sampling,gradient-based approaches such as variational inference [272] or NUTS [187] cannot han-dle the extremely sharp topologies of standard probability spaces in comparison to thesmoother log probability equivalents.From a user-facing perspective, so long as final algorithm outputs are converted tostandard probabilities where needed, there is virtually no impact to working with logprobabilities aside from the higher stability observed by the user. Internally, however,the main challenge is to handle sums of probabilities, such as when marginalizing overhyper-latent variables in importance sampling. These sums have no direct equivalent inthe log domain, but conversion to linear domain to perform the sum immediately incursthe previously discussed issues. Instead, the log of the sum of exponents (log-sum-exp)computational shortcut must be used liberally:LSE(x1, ..., xn) = log(n∑i=1exi) (B.1)227B.2. Log Domain Model FormulationsAs an example of using this shortcut, an estimate of marginal probability using im-portance sampling from the target (following Eq. 8.6) can be computed using log prob-abilities as:log p(y|d) =NxLSEi=1(log p(y|xi, d))− logNx, xi ∼ p(x) (B.2)B.2 Log Domain Model FormulationsThe second application of log domain transformation is in the specification of PoF modelswithin the SPM architecture. As discussed in Sec. 6.2.2, even if log probabilities areused the NUTS probability topology may not be smooth due to sharpness arising fromthe model itself. To improve CBI stability and reduce high sensitivity of some modelvariables to hyper-latents in exponents (frequently the apparent activation energy) it canbe helpful to define the model in the log domain. This does result in user-facing impacts,as the user needs to explicitly define model functions in the log domain that used tocompute relevant intermediate values. The overall technical burden is moderate, asthe transformation can be obtained through simple algebraic manipulation but requiressome thought and expertise to decide which parts of a model to convert. Capabilityfor automatic conversion of some SPM architecture components to log domain couldpotentially be included as part of the future work item to improve the useability of thedeveloped software libraries (see Sec. 10.2), but better guidance and instructions viacomprehensive documentation may be more feasible in the short term. Note that ifspecified entirely in the log domain, measurement noise can also scale logarithmicallywhich may not be desired in some situations. Examples of log domain models can befound in some of the case study demos provided as part of the software library for CBIand BED [239].228
Thesis/Dissertation
eng
Electrical and Computer Engineering
Vancouver : University of British Columbia Library
Attribution-NonCommercial-NoDerivatives 4.0 International
Graduate
Ivanov, Andre
Long-term reliability monitoring and qualification strategies for integrated circuits
Text