AN EMBEDDED CALIBRATION TECHNIQUE FOR HIGH-RESOLUTION FLASH TIME-TO-DIGITAL CONVERTERS by JAMES C I C A L O B A . S c , University of British Columbia, 2002 A THESIS SUBMITTED IN P A R T I A L F U L F I L L M E N T OF THE REQUIREMENTS FOR THE D E G R E E OF M A S T E R OF APPLIED SCIENCE in THE F A C U L T Y OF G R A D U A T E STUDIES (Electrical and Computer Engineering) THE UNIVERSITY OF BRITISH C O L U M B I A August 2007 © James Cicalo, 2007 Abstract As CMOS technology continues to advance, device dimensions will continue to decrease, thus enabling the creation of circuits which operate at increasingly greater frequencies. However, this increase in operating frequency has resulted, in a reduced tolerance for circuit timing uncertainties. Therefore, techniques capable of measuring the timing characteristics of multi-GHz signals are needed to help address the growing number of timing problems found in modem CMOS circuits. For cost and accuracy reasons, embedded time interval measurement techniques which offer picosecond measurement accuracies and millisecond test-times are required to overcome these challenges. The( "sampling offset" based flash time-to-digital converter (SOTDC) is an embedded time interval measurement technique that has recently garnered much attention due to its attractive properties. These properties include sub-millisecond test times of multi-GHz signals, in addition to the potential for measurement accuracies in the order of picoseconds. However, the accuracy of an SOTDC is strongly dependent upon the capabilities of its calibration technique, and present SOTDC calibration techniques suffer from some very serious limitations. In fact, these limitations are so severe that present calibration techniques are impractical under realistic production test conditions. ii This thesis presents the design and analysis of a novel embedded SOTDC calibration technique. The proposed calibration technique offers the potential for both sub-picosecond calibration accuracies and sub-100 millisecond calibration times. However, the main contribution of this work concerns the suitability of the proposed technique with a realistic production test environment. The capabilities of the proposed calibration technique have been proven using both mathematical analysis and behavioural modelling simulations. in Table of Contents Abstract i i Table of Contents • 'iy List of Figures vii List of Tables.... • vi Acknowledgements • x Chapter 1 Introduction 1 1.1 Time Interval Measurement 2 1.2 Thesis Organization 6 Chapter 2 Flash-Based Embedded Time Interval Measurement Techniques 7 2.1 Single Delay Line-Based Flash T D C 9 2.2 Vernier Delay Line-Based Flash T D C 12 2.3 Sampling Offset-Based Flash T D C 14 Chapter 3 Embedded Calibration of a Sampling Offset-Based Flash T D C 20 3.1 Behaviour of a Non-Ideal Arbiter 21 3.1.1 A Model of Thermal Noise in an Arbiter 21 3.1.2 Non-Ideal Arbiters and T i me Interval Measurement 24 3.2 Direct Calibration Technique 25 3.2.1 Analysis 28 3.2.2 , Conclusions 38 3.3 Relative Offset Calibration Technique 39 3.4 Added Noise Calibration Technique 42 3.4.1 Analysis 46 3.4.2 Conclusions 48 Chapter 4 Proposed SOTDC Calibration Technique 50 4.1 Simplified Proposed Calibration Technique 50 4.2 Non-Ideal Arbiters and Added Noise 62 4.3 Oscillator Non-Idealities 69 4.4 Implementation 71 4.5 Summary „ .' 74 iv Chapter 5 Results and Analysis 76 5.1 Theoretical Error Bounds 77 5.2 Realistic Error Bounds 84 Chapter 6 Conclusions and Future Work 102 6.1 Summary and Contributions 102 6.2 Future Work : 104 6.2.1 The impact of non-idealities 104 6.2.2 Circuit implementation 105 6.2.3 Additional applications and SOTDC improvements 106 References 108 Appendix A Circuit Implementation of Proposed Calibration Technique and 16-bit SOTDC 112 v List of Tables Table 3.1: Optimal ratio of tA to a, given the number of repetitions performed 37 Table 3.2: Reported results from Matlab simulation of the added noise-based calibration technique (tA = 40 ps, O, = 250 ps, N = 100 000) [26] 46 Table 5.1: Properties of the oscillator cycle count histograms illustrated in Figure 5.5 89 Table 5.2: Four P L L divisors (A and B) and their corresponding Tj values (fi„- 50 kU) 98 Table 5.3: Time required to calibrate an SOTDC, assuming the P L L divisors of Table 5.2 (f,„ = 50 kl-I) [s] 99 vi List of Figures Figure 1.1: Timing jitter in a signal under test (SUT) 2 Figure 1.2: Three classifications of jitter. 3 Figure 1.3: P D F of random period jitter (a), and a combination of random and deterministic period jitter (b) 4 Figure 1.4: The growth of a random period jitter histogram as the number of measurement is increased 4 Figure 2.1: The role of a T D C 8 Figure 2.2: Single delay line-based flash T D C 10 Figure 2.3: Single delay line-based flash T D C timing waveform 11 Figure 2.4: A Vernier delay line-based flash T D C 12 Figure 2.5: Vernier delay line-based flash T D C timing waveform 13 Figure 2.6: Sampling offset-based flash T D C . 15 Figure 2.7: Symmetric C M O S arbiter 16 Figure 2.8: Behaviour of a perfectly symmetric arbiter 17 Figure 2.9: Behaviour of a positively biased arbiter 18 Figure 3.1: Voltage domain model of thermal noise in a biased arbiter 21 Figure 3.2: Time domain model of thermal noise in a biased arbiter 22 Figure 3.3: P D F of the sampling offset of a biased arbiter taking into account thermal noise ' 23 Figure 3.4: Gaussian C D F 23 Figure 3.5: Calculation of tso from the C D F of the sampling offset of a non-ideal arbiter 24 Figure 3.6: Sensitivity of the output of an arbiter to a, 25 Figure 3.7: Direct SOTDC calibration technique 26 Figure 3.8: Response of an arbiter to a sequence of increasing time intervals 26 Figure 3.9: Response of an arbiter to several repetitions of a sequence of increasing T& 27 Figure 3.10: Histogram and C D F of the output of an arbiter 28 Figure 3.11: Histogram of the output of an arbiter when tA < a, , 29 vi i Figure 3.12: Histogram of the output of an arbiter when tA > at 29 Figure 3.13: R M S tce/a, vs. tjo, using the direct calibration technique 31 Figure 3.14: Histogram and C D F of the output of a noise-free arbiter 32 Figure 3.15: -tso versus tce for a noise-free arbiter using direct calibration 33 Figure 3.16: tce probability density function 34 Figure 3.17: R M S tce/o, vs. tJot using the direct calibration technique 35 Figure 3.18: Log-log plot of R M S tcJat vs. tjoi using the direct calibration technique. 36 Figure 3.19: Log-log plot of R M S tce vs. at when tA = 10 ps, using the direct calibration technique 37 Figure 3.20: Gaussian distribution of arbiter sampling offsets due to process variation. 41 Figure 3.21: Log-log plot of R M S tce vs. ot when N = 100 000, using the direct calibration technique .-. 43 Figure 3.22: Time domain model of added and thermal noise in a biased arbiter 44 Figure 3.23: Arbiter sampling offset PDF with thermal and added noise 44 Figure 3.24: Addition of Gaussian temporal noise to a sequence of time intervals in order to create an arbiter sampling offset C D F 45 Figure 3.25: Added noise calibration technique implementation [26] 46 Figure 3.26: Log-log plot of R M S tce vs. a, when tA = 40 ps and N = 100 000, using the model of the direct calibration technique described in section 3.2.1 47 Figure 4.1: Time intervals created by two free-running oscillators 51 Figure 4.2: Sequence of linearly increasing time intervals 52 Figure 4.3: Periodic time intervals created by two free-running oscillators 53 Figure 4.4: Periodic sequence of time intervals generated from the output of oscA and oscB assuming TAITA = 5 >. 54 Figure 4.5: Determining the relative sampling offsets of two arbiters 55 Figure 4.6: Variation in arbiter sampling offsets while still maintaining a constant cycle count 56 Figure 4.7: Behaviour of a negatively biased arbiter 57 Figure 4.8: Behaviour of a positively biased arbiter (a), and a positively biased arbiter with reversed inputs (b) 58 Figure 4.9: Oscillator cycle count when the inputs to Arbiter2 are reversed 60 Figure 4.10: Summary of the information obtained by counting the number of oscillator cycles elapsed between the switching-events of two arbiters 61 Figure 4.11: (a) P D F of several Ts belonging to a sequence of Ts (b) PDF of two Ts (Note: the sampling offsets of two arbiters, tso! and tso2, are plotted along the x-axis of both figures) 63 Figure 4.12: Probability of oscillator cycle counts when Arbiter 2 has both normal and reversed inputs 68 Figure 4.13: P L L implementation of oscA and oscB 70 Figure 4.14: Conceptual circuit view of the proposed calibration technique 72 Figure 5.1: Minimum error of the proposed calibration technique across four different TA values 79 Figure 5.2: Oscillator cycle counts PDFs for several different values of ototai, all of which are < <5op,imai (TA =10 ps) 80 Figure 5.3: Oscillator cycle counts PDFs for several different values of otolai, all of which are > o'optimal {TA = 10 ps) 82 vm Figure 5.4: Flowchart describing the method of operation of the proposed SOTDC calibration technique Matlab model 87 Figure 5.5: Three oscillator cycle count histograms, generated using a different number of measurement repetitions 89 Figure 5.6: Comparison of the theoretical and realistic R M S error of the proposed calibration technique when TA = 10 ps 91 Figure 5.7: The R M S error of the proposed calibration technique when 7/^=10 ps, plotted for three different number of measurement repetitions (N) 93 Figure 5.8: Comparison of the theoretical and realistic R M S error of the proposed calibration technique when TA = 100 ps..: ....95 Figure 5.9: Comparison of the theoretical and realistic R M S error of the proposed calibration technique when TA = 1 ns 96 Figure 5.10: Comparison of the theoretical and realistic R M S error of the proposed calibration technique when TA = 1 ps 96 Figure 5.11: The effect of varying TA on the calibration time (tcai) and the calibration error (tce) (calculated using an optimal value of atotai) 100 Figure A. 1: Top-level schematic of the proposed SOTDC calibration circuit (1-bit of 16-bit SOTDC illustrated) 113 Figure A.2: Schematic of the Reference Arbiter Sampling circuit ("ref_arbiter_sampled") 114 Figure A 3 : Schematic of the Arbiter Array Counter Trigger circuit ("ref_arbiter_counter_trig") 115 Figure A.4: Schematic of the Arbiter Sampling circuit ("arbiter_sampled") 116 Figure A. 5: The output of a positively biased arbiter when two free-running oscillators of different frequency, oscArand oscB, are applied to its inputs (TA = 1 ns, TA = 20 ps) 117 Figure A.6: The sampled output of a positively biased arbiter when two free-running oscillators of different frequency, oscA and oscB, are applied to its inputs (TA = I ns, TA = 20 ps, sampling delay = 50 ps) 118 Figure A . 7: Schematic of the Arbiter Counter Control circuit ("arbiter_countercontrol") 119 Figure A. 8: Schematic of the Arbiter circuit ("arbiter_tO") 120 Figure A. 9: Schematic of the 24-bit Counter circuit ("24b_counter") 121 Figure A. 10: Schematic of one stage of a 24-bit Counter ("counter_cell") 122 Figure A . l 1: Layout view of a 16-bit SOTDC and proposed calibration circuit in 0.35 um C M O S (L = 1930 um, W = 690 um).. 123 ix Acknowledgements I would like to convey my most sincere gratitude to those who have helped me to complete this work. Firstly, I would like to thank my research supervisor, Professor Andre Ivanov, for providing me with the opportunity to join his research group in addition to the U B C SoC laboratory. Professor Ivanov's continued guidance and support throughout this work was instrumental to its ultimate success. Secondly, I would like to thank my colleagues at the SoC laboratory, and in particular, Zaman Mollah, Andy Kuo, Michael Jones, and Dr. Roberto Rosales. I learned much from our countless discussions, and I will always be grateful for their advice and friendship. I would also like to thank the Canadian Microelectronics Corporation for granting me access to their IC fabrication services, in addition to Micronet, a Canadian Network of Centres of Excellence focused on the design of microelectronic systems, for financial support. Last, but certainly not least, I would like to thanks my parents, Ke'n and Teresa, my sister Carolyn, and my fiancee, Linda Zhang, for their immeasurable love and encouragement during the many challenges I encountered over the years. x Chapter 1 Introduction As CMOS technology continues to advance, device dimensions will continue to decrease, thus enabling the creation of circuits which operate at increasingly greater frequencies. However, this increase in operating frequency has resulted in a decreased tolerance for circuit timing uncertainties. In addition, the behaviour of a circuit, and therefore the timing of its signals, is becoming increasingly sensitive to environmental influences. These environmental influences may disturb the operation of a circuit through a number of mechanisms. These mechanisms include capacitive and inductive coupling, as well as the injection of noise into the power-supply or the substrate of a CMOS circuit [1,2] . As these mechanisms are becoming increasingly prevalent in modem CMOS circuits, critical path signals are increasingly susceptible to unwanted timing variations. Unintended timing variations in a signal may cause a circuit to become non-functional. Therefore, the ability to detect, diagnose, and i f possible, repair timing problems is of the utmost importance i f the reliability of a CMOS circuit is to be guaranteed. However, detecting timing problems in multi-GHz signals can be a very challenging task due to the extremely short time intervals that must be measured. For example, a 10% deviation in the 1 period of a 10 GHz signal translates to a mere 10 ps. Without the ability to detect timing problems in multi-GHz signals, it is not possible to diagnose or repair them. As a result, techniques capable of detecting and diagnosing timing problems in multi-GHz signals are needed to help address the growing number of timing issues found in modern CMOS circuits. 1.1 Time Interval Measurement The detection or diagnosis of a timing problem in a CMOS circuit is often accomplished with the help of a time interval (TI) measurement technique. TI measurement is a time domain analysis technique that is often used to deduce the timing characteristics of a signal by estimating its threshold crossings in the voltage domain [3], Many types of TI techniques exist, however they all share a common goal of quantifying the amount of uncertainty in the timing of a signal. Once this timing uncertainty has been quantified, predictions regarding the probability of a circuit's failure can be made. Timing uncertainty is usually referred to as "timing jitter" or "absolute jitter", which is defined as the deviation from the ideal timing of an event, and can be accumulated over many cycles [4, 5]. This definition is illustrated in Figure 1.1, where the amount of timing jitter in a signal under test (SUT) is indicated by the degree of uncertainty in the temporal location of a signal transition. Another useful definition that is illustrated in Figure 1.1 is that of the jitter budget or tolerance of a design, which is the maximum amount of timing jitter that can exist in a signal before the circuit fails to operate reliably. Two additional classifications of jitter exist, as Ideal Period SUT j Timing Jitter Figure 1.1: T i m i n g j i t te r in a signal under test (SUT). 2 illustrated in Figure 1.2. The first of these classifications is the most common of the three, and is known as "period" jitter. Period jitter is simply the deviation of a single period from its ideal value. The second classification is known as "cycle-to-cycle" jitter, and is a measure of the difference between adjacent cycles. Ideal Signal / \ / \ / \ / j « — T i T 2 T 3 Actual Signal / \ / \ / \ / A B C Period Jitter: Ti - T 0 T 2 - T 0 T 3 - T 0 Cycel-to-Cycle Jitter: T 2 - Ti T 3 - T 2 ( T i + T 2 ) ( T ^ T j + Ts) Timing Jitter: ^ - T 0 - 2 T 0 - 3T 0 Figure 1.2: Three classifications of jitter. Each of the aforementioned types of jitter may contain both random and deterministic components, depending upon the source of the jitter. In any case, it is possible to predict the probability with which a signal will exceed a circuit's timing margins by constructing the probability density function (PDF) of the period jitter [6]. The PDF of a purely random source of period jitter is illustrated in Figure 1.3 (a). Inspection of Figure 1.3 (a) reveals that random period jitter can be characterized by a Gaussian distribution. Since a Gaussian distribution is unbounded, its peak-to-peak value (the difference between the shortest and longest cycles) is also unbounded, and is highly dependent upon the number of cycles measured. The 'PDF of period jitter resulting from both random and deterministic sources is illustrated in Figure 1.3 (b). The shape of this PDF is determined by the convolution of the 3 random and deterministic components' PDFs [7]. A s deterministic jitter is bounded in nature, its peak-to-peak value is also bounded. CC . Q O • ^ »J Jitter Budget / / ^ v 1 Tolerance 1 \ ' / "o\ J 1 \ 1 1 \ i __, • »J Jitter Budget / I Tolerance -15 -10 -5 0 5 10 Period Jitter [ps] (a) 15 -15 -10 -5 0 5 10 Period Jitter [ps] (b) Figure 1.3: P D F of random period jitter (a), and a combination of random and deterministic period jitter (b). A s the function o f a time interval measurement technique is to accurately estimate the duration o f a time interval, multiple measurements o f a signal's period can be performed and subsequently compiled into a histogram. If this histogram is normalized by the number o f measurements performed, a P D F o f the signal's period jitter can be produced. However, before an accurate P D F can be produced, many cycles need to be measured [8]. This idea is illustrated in Figure 1.4, where the random period jitter o f a signal is estimated using three different histograms. Each histogram is drawn using an increasing number o f measurement results. in m o >» O CD Jitter Budget / Tolerance -15 -10 -5 0 5 10 Period Jitter [ps] 15 # Cycles Measured n - N 3 • - N 2 NT < N 2 < N 3 Figure 1.4: T h e growth of a random period jitter histogram as the number of measurement is increased. 4 Inspection of Figure 1.4 reveals that both the standard deviation and the peak-to-peak jitter of the histogram may vary as the number of measurement cycles is increased. Although a few thousand measurements are often sufficient to provide an accurate estimate of standard deviation, hundreds of thousands, or even millions of measurements are often required in order to make an accurate prediction of the peak-to-peak jitter in a multi-GHz signal. Such information is frequently used as a metric when determining the probability of circuit failure [8]. While many different time interval measurement techniques exist [9], the choice of which technique to employ for a given application ultimately depends on the measurement requirements. For instance, the measurement of period jitter at giga-bits-per-second (Gbps) data rates necessitates very accurate results, as the jitter budget at these speeds is extremely small. For example, the authors in [20] predict that measurement accuracies of 1 ps or less will be required for bit-error-rate (BER) testing of 10 Gbps integrated circuit (IC) pins. As previously mentioned, obtaining accurate jitter results may require a large number of measurements. Therefore, as signal data rates increase along with jitter measurement requirements, the total measurement time of TI measurement techniques continues to rise. As a result, only a select group of low test-time measurement techniques are feasible in a volume production test environment, where test time is directly related to product cost [10]. Signal amplitude sampling-based techniques [11] can be used to reconstruct the shape of a voltage-time waveform based on a number of voltage-time samples. While these techniques are not strictly "time interval" based jitter measurement techniques, they have been successfully used to measure jitter with picosecond accuracy [12]. However, signal amplitude sampling-based techniques typically require tens of seconds per measurement, which is far too much time for a volume production test environment [13]. High-frequency production testers can be used to measure jitter with picosecond accuracy in a matter of seconds [i4, 15, 16]. However, these testers generally cost millions of dollars. In addition, probing gigaHertz signals for off-chip measurement can introduce significant additional jitter [20]. Therefore, for cost and accuracy reasons, embedded (on-chip) time interval 5 ( measurement techniques which offer picosecond measurement accuracies and millisecond test-times are very useful tools to enable the cost-effective analysis of a growing number of timing problems found in modem CMOS circuits [17]. In fact, embedded time interval measurement techniques are currently the subject of research within both academia and industry [18]. • One new time interval measurement technique which has recently garnered much attention is the "sampling offset" based flash time-to-digital converter (SOTDC) [23]. This time-to-digital converter (TDC) offers sub-millisecond test times for gigaHertz signals, as well as the potential for picosecond measurement accuracies. However, the accuracy of an SOTDC is strongly dependent on the capabilities of its calibration technique. To date, no feasible embedded calibration technique for an SOTDC has been proposed. This thesis is focused on the design of a novel embedded calibration technique for SOTDCs which offers the potential for sub-picosecond calibration accuracies, and calibration times in the order of milliseconds. While specific reference to the calibration of an SOTDC is made, this calibration technique is applicable to any flash-based TDC. 1.2 Thesis Organization This thesis consists of a total of six chapters. Important background information concerning the evolution of traditional flash-based TDCs into state-of-the-art SOTDCs is presented in Chapter 2. Three previously proposed SOTDC calibration techniques are described in Chapter 3, and the important limitations of each are investigated. Next, the embedded calibration technique proposed in this thesis is described in Chapter 4, followed by an analysis of its capabilities and limitations in Chapter 5. Finally, conclusions regarding the contribution of this thesis are presented in Chapter 6, along with a discussion of future work. 6 Chapter 2 Flash-Based Embedded Time Interval Measurement Techniques Embedded time interval measurement can be performed using a variety o f techniques, and is often realized using a time-to-digital converter (TDC) . A T D C is a circuit that outputs a digital codeword when a time interval is applied to its input, as shown in Figure 2.1. The time interval to be measured, referred to from hereon as Td, is defined as the difference in time between the rising edge transitions o f two signals, which are traditionally referred to as START and STOP. This digital codeword, once interpreted, approximates the duration o f the time interval. 7 START o-TDC 8 01101011 STOP START . . . _ n STOP n _ . . . H Figure 2 .1 : T h e role of a T D C . While many different types of TDCs exist, they can all be evaluated against the following criteria: • Accuracy: How closely the interpreted digital codeword matches Td. • Resolution: The smallest measurable difference in Td. • Precision: The degree to which a set of measurements of the same Td agree. • Measurement rate: The maximum rate at which different T& can be applied to the T D C s input while still receiving correct codewords at its output. • Dynamic range: The ratio of the maximum to minimum Td measurable by the TDC. • Power and A r e a requirements: The area required to implement an on-chip TDC with certain accuracy, resolution, precision, measurement rate, and dynamic range specifications, in addition to the power consumed by this TDC. 8 As the accuracy, resolution, precision, dynamic range, and measurement rate requirements placed upon TDCs become increasingly stringent, trade-offs are necessary in order to construct a feasible TDC architecture. Many TDC architectures target a reduced measurement rate in order to meet the accuracy, resolution, and precision requirements. Examples of such TDCs include the Vernier oscillator-based TDC [19], and the undersampling-based TDC described in [20], However, this trade-off can be very costly for integrated circuit (IC) manufacturers, since the resulting increase in production test time increases overall production costs. This chapter examines the evolution of "flash" TDC architectures. The chapter begins with a description of the most primitive form of a flash TDC, and concludes with a presentation of the state-of-the-art in flash TDC design, where picosecond measurement resolutions are achievable. In general, Flash TDCs are capable of very high measurement rates. In fact, flash TDCs are capable of operating at or near the frequency of the signal or signals under test, from which the START and STOP signals are derived. Flash TDCs are analogous to flash analog-to-digital converters (ADCs), since their output codeword is determined in a single step by a bank of comparators [21]. Therefore, the flash TDC architecture is a very good candidate for embedded time interval measurement in both a i production test environment or in a customer application, where measurement time is of comparable importance to measurement accuracy, resolution, and precision. 2.1 Single Delay Line-Based Flash TDC The most basic form of a flash TDC is the single delay line-based flash TDC, which is illustrated in Figure 2.2. This TDC architecture has two primary inputs, namely START and STOP, and a multitude of outputs, labelled Cj to CN in this embodiment. 9 START STOP IN1 OUT1 ARBITER 1 IN2 OUT2 V IN1 OUT1 ARBITER 2 IN2 OUT2 IN1 OUT1 ARBITER N IN2 OUT2 c 2 -c=> c N Figure 2.2: Single delay line-based flash T D C . If we define the instant at which the START signal transitions from a low to a high logic level as tstart, and i f we define tstop analogously for the STOP signal, then we can describe Td in mathematical terms with the following equation: Pd tstop ~ t stop 1 start (2.1) As shown in Figure 2.2, the START signal is delayed by a single buffer as it propagates from one arbiter to the next. The delay of each buffer is equal to T. At each stage, an arbiter determines which of its two inputs was the first to transition from a low to a high logic level, i.e., the first to make a "positive" transition. If INI is the first to perform such a transition then OUT1 is set to a high logic level and OUT2 to a low logic level, and vice versa i f IN2 is the first to arrive. Figure 2.3 illustrates the operation of a single delay line-based flash TDC 10 consisting of 4 arbiters. This type of TDC can be referred to as a 4-bit single delay line-based flash TDC. Arbiter 1 { IN1 IN2 C 2 { IN1 : I IN2 [ C 3 { IN1 —1 IN2 I C 4 Figure 2.3: Single delay line-based flash T D C timing waveform. As is shown in Figure 2.3, a single delay line-based flash TDC produces a thermometer code digital output (C4C3C2C1 = 1000). Td can be approximated by noting the location of the "0" to "1" transition in the output codeword. In the above example, Tj is shown to satisfy the following condition: 2r<Td<3r (2.2) The resolution of this TDC is limited by the buffer delay, r. This buffer delay has a practical lower bound due to the physical constraints of the technology in which it is implemented. Therefore, for high-resolution applications, a single delay line-based flash TDC may be inadequate, 11 2.2 Vernier Delay Line-Based Flash T D C In order to overcome the resolution limitations o f a single delay line-based flash T D C , a second delay line can be added, as shown in the Vernier delay line-based flash T D C of Figure 2.4. START STOP V V IN1 OUT1 ARBITER 1 IN2 OUT2 IN1 OUT1 ARBITER 2 IN2 OUT2 Cl C 2 IN1 OUT1 ARBITER N IN2 OUT2 C N Figure 2.4: A Vernier delay line-based flash T D C . This second delay line is used to incrementally delay the STOP signal as it propagates ( from one arbiter to the next, as is done to the START signal in the single delay line-based flash T D C . The delay o f each buffer in the START signal path is equal to Tj, whereas the delay o f each buffer in the STOP signal path is equal to T?. A n example o f the method o f ' operation o f a 4-bit Vernier delay line-based flash T D C is illustrated in Figure 2.5. 12 { IN1 _f IN2 C l _ Arbiter 2 Arbiter 3 Arbiter 4 Figure 2.5: Vernier delay line-based flash T D C timing waveform. As shown in Figure 2.5, a Vernier delay line-based flash TDC also produces a thermometer code digital output (C4C3C2C1 =/1000). Td can be found using the same procedure described for the single delay line-based flash TDC, i.e., by noting the location of the "0" to "1" transition in the output codeword. In the example illustrated in Figure 2.5, Td is shown to satisfy the following condition: 2(T1-T2)<Td<3(T1-T2) (2.3) The buffer delay difference, i.e., T/ - T2, where T) > T2, defines the resolution of a Vernier delay line-based flash TDC. Therefore, sub-gate delay resolution can be achieved with this architecture. Calibration of a Vernier delay line-based flash TDC is done to ensure that the buffers in each of the two delay lines provide the required delay, i.e., T; or r2. Normally a delay-locked-loop (DLL) is used to accomplish this, ensuring that integral nonlinearity (INL) errors in the converter are minimized [22]. However, the arbiters are most often constructed from flip-flops, since a flip-flop is essentially an arbiter. While flip-flops make efficient arbiters, 13 their non-zero setup times may influence the buffer delay difference (z> - xi) and hence contribute to the TDCs differential nonlinearity (DNL) error, as a DLL-based calibration technique cannot be used to perform stage-by-stage calibration. For example, there is no impact on the measurement accuracy of the TDC as long as the flip-flops have identical setup times, in which case they can be treated as a constant and removed from the measurement results. However, the setup times of flip-flops on the same semiconductor die can vary significantly due to process variations. For example, variations as large as 50 ps have been observed in a 0.35 um CMOS process [23]. As the resolution of a Vernier delay line-based flash TDC is increased, the importance of a flip-flop's setup time is amplified, as it is not accounted for during calibration. Therefore, there exists a limit to how small the buffer delay difference can be made before the variability between flip-flop setup times begins to add a significant level of error to the measurement results. For the measurement of 5 and 10 Gbps data rate signals, where the required accuracy is 10 ps or better, a Vernier delay line-based flash TDC is inadequate [20]. 2.3 Sampling Offset-Based Flash TDC A novel concept discussed in [23] attempts to address the time interval measurement accuracy requirements of 10 Gbps data rate signals and beyond. The author in [23] suggests that a TDC with a resolution of 2 ps or less can be constructed by removing the buffers from a Vernier delay line-based flash TDC, thereby making use of the inherent variations in the setup times of the arbiters. This type of TDC, shown in Figure 2.6, is known as a "sampling offset" TDC (SOTDC). 14 START STOP IN1 0UT1 ARBITER 1 IN2 0UT2 IN1 0UT1 ARBITER 2 IN2 0UT2 Cl C 2 IN1 OUT1 ARBITER N IN2 OUT2 CN Figure 2.6: Sampl ing offset-based flash T D C . The term "sampling offset T D C " arises from the fact that a time interval is quantized using the difference in the setup times, or sampling offsets, of the arbiters, assuming they are known. This is in contrast to a Vernier delay line-based TDC, which uses a difference in buffer delays to quantize time. Instead of implementing the arbiters or "sampling elements" with flip-flops, the author in [23] chose to use symmetric CMOS arbiters. A symmetric CMOS arbiter schematic is drawn in Figure 2.7. This circuit arbitrates between two inputs, INI and IN2, by determining which input was the first to perform a low to high transition, i.e., a positive transition. 15 0UT.1 O U T 2 Figure 2.7: Symmetric CMOS arbiter. The operation of a symmetric CMOS arbiter relies on the use of positive feedback. With inputs INI and IN2 discharged low, transistors M3 and M6 remain in cutoff mode. Therefore, the drains of M2 and M5 remain precharged high through transistors M l and M4, and outputs OUT1 and OUT2 remain predischarged low. Now, if INI is the first input to perform a positive transition, current will flow down the left-hand side of the arbiter as M3 leaves the cutoff mode of operation. If M l , M2, and M3 are properly sized, the voltage on the drain of M2 will fall low enough to cause OUT1 to switch,high. In addition, since the drain of M2 is connected to the gate of M5, M5 will enter the cutoff region, in turn maintaining a high voltage at the drain of M5 and a low voltage at OUT2. It is this use of positive feedback between transistors M2 and M5 that allows this arbiter to successfully resolve picosecond-timing differences, as demonstrated in [24]. An arbiter such as the one illustrated in Figure 2.7 is said to be perfecdy symmetric if its left hand side behaves identically to its right hand side. As a consequence of this perfect symmetry, its sampling offset (tso) is equal to zero seconds. An arbiter with a non-zero sampling offset is said to be "biased" towards one of its inputs. Therefore, a perfectly symmetric arbiter does not exhibit a bias towards either input. As a result, the first input to transition from a low to a high logic level is always recorded as such, with the corresponding output set to a high logic level. This behaviour is illustrated in Figure 2.8. 16 oscA oscB tso = 0 IN1 OUT1 ARBITER IN2 OUT2 oscA oscB H H « Tdi Td2 Td3 OUT1 OUT2 Figure 2.8: Behaviour of a perfectly symmetric arbiter. In Figure 2.8, two oscillators, oscA and oscB, are depicted as the inputs to a perfectly symmetric arbiter. The frequency of oscA is slightly greater than that of oscB. Therefore, a sequence of varying time intervals is generated from the rising edge transitions of the two oscillators. If the temporal location of a rising edge transition of oscB is denoted as toscB(i), and if toscA(i) is defined analogously for oscA, then each time interval can be expressed mathematically as: Td(i) — t, oscB(i) " 'oscA(i) (2.4) The preceding definition allows for the sampling offset of the arbiter in Figure 2.8 to be bound by the following inspection-based equation: Td2 < tso ^ Tdi (2.5) A biased arbiter, however, exhibits a non-zero sampling offset. This bias can be the result of transistor mismatches between the left and right hand sides of the arbiter, and is often attributed to process variations. However, it can be useful to intentionally bias an 17 arbiter, in which case the transistor mismatches are the result of design intent [25], The behaviour of a biased arbiter is illustrated in Figure 2.9, where a buffer delay (TM) has been inserted before input INI of a perfectly symmetric arbiter in order to mimic the behaviour of a biased arbiter. oscA oscB tso Tde l •CM Tde l I N 1 O U T 1 ARBITER I N 2 O U T 2 oscA oscB OUT1 OUT2 H H H I d1 d2 l d3 n Figure 2.9: Behaviour of a positively biased arbiter. Analogously, the sampling offset of the arbiter in Figure 2.9 can be bound with the following inspection-based equation: Td2 < tso ^ Td3 (2.6) In summary, inserting a buffer before input INI of a perfectly symmetric arbiter results in an arbiter that is biased by an amount equal to the delay of the buffer (T*/). For this reason, this type of arbiter is known as a "positively biased" arbiter. A typical SOTDC can be constructed from several positively biased arbiters, each with a unique sampling offset. If the arbiters are positioned within the SOTDC in order of smallest tso to largest, then the output codeword will be in the form of a thermometer code. 18 Therefore, if a time interval, Td, where Td > 0, is applied to the SOTDC, then the value of Td can be approximated by noting the location of the "0" to "1" transition in the output codeword. For example, assume an- SOTDC consisting of only 4 positively biased arbiters exists. Now, if a Td which is greater than the sampling offset of arbiters 1 and 2, but smaller than that of arbiters 3 and 4, is applied to the SOTDC, then the output codeword will look as follows: C4C3C2C1 = 0011. Such an output codeword'Can be used to approximate the value of the applied time interval, Td, as shown in Equation (2.7), where tS02 and tS03 represent the sampling offsets of arbiters 2 and 3, respectively. tso2<Td<tso3 (2.7) If the sampling offsets of the arbiters are equally spaced, then the error in the above approximation must be bounded by the resolution of the SOTDC, which is defined as the step size of the arbiter sampling offsets. The challenge associated with using an SOTDC for time measurement lies in determining the sampling offsets of the arbiters, as without such information it is impossible to extract useful data from the arbiter outputs. Several calibration techniques have been developed in order to measure the sampling offsets of the arbiters within an SOTDC. The merits and drawbacks of each are presented in the following chapter, and a new calibration technique is proposed in Chapter 4. 19 Chapter 3 Embedded Calibration of a Sampling Offset-Based Flash T D C Present SOTDC calibration techniques suffer from some very serious limitations. The most straightforward of these techniques require an accurately known sequence of closely spaced Td values, which for a picosecond resolution SOTDC is very difficult to generate on-chip. A more sophisticated technique, as described in [23], requires precise knowledge of the mean sampling offset of the SOTDC arbiters. Unfortunately, such information is usually not available. Another technique, as described in [26], requires the use of an external signal generator or an on-chip D L L in order to generate Td values which are not necessarily closely spaced, but accurately known nonetheless. Time interval accuracies in the order of picoseconds are required for successful implementation of this technique, and therefore dictate the use of only the most accurate signal generators or on-chip DLLs . In addition, this technique employs two on-chip variable delay elements that must be calibrated with picosecond accuracy in order to resolve any skew introduced between the output of the Td 20 generator and the input of the SOTDC, and is therefore not a complete solution. The technique proposed in Chapter 4 is exempt from any of these deficiencies. 3.1 Behaviour of a Non-Ideal Arbiter Before the aforementioned calibration techniques can be fully understood, a model that incorporates thermal noise in an arbiter must be developed. Such a model has been reported in [26]. This model suggests that the sampling offset of an arbiter is not a fixed number, but should instead be treated as a random variable that changes with time. The preceding implies that the sampling offset of an arbiter at a particular instant in time can only be described as having a certain probability of being a particular value. This "instantaneous" sampling offset is denoted as tiso. 3.1.1 A Model of Thermal Noise in an Arbiter An ideal arbiter is assumed to have a deterministic output, i.e., the arbiter's output can be predicted exactly if its input is known. Therefore, a given Td will produce a consistent output from an ideal arbiter. However, as discussed in [23, 27, 28], arbiters implemented using CMOS circuit elements are not ideal, and therefore do not behave deterministically. For example, thermal noise generated in the circuit elements of an arbiter can induce nondeterministic behaviour. A model which illustrates the impact of thermal noise in an arbiter has been developed in [29] and is illustrated in Figure 3.1. START IZ>| • © — J t , IN1 OUT1 UNBIASED ARBITER t > c v, noise STOP rz>f IN2 OUT2 L Figure 3.1: Voltage domain model of thermal noise in a biased arbiter. 21 Vnoise is a source of noise in the voltage domain, and is the result of thermal noise within the arbiter's circuit elements. This noise is assumed to be white Gaussian noise, with a standard deviation of o v and a mean of zero. However, a time domain model of thermal noise in an arbiter is more useful for time interval measurement purposes, since with such a model it is possible to account for the impact of thermal noise in the time domain. A time domain model has been developed in [23, 26], and is illustrated in Figure 3.2. START STOP noi-IN1 OUT1 UNBIASED ARBITER IN2 OUT2 L Figure 3.2: Time domain model of thermal noise in a biased arbiter. With the time domain model, V„oise has been replaced with tnoise, which functions as a variable delay element. A linear relationship between V„oise and tnoise is assumed in [23, 26], which allows for tnoise to be described by a Gaussian probability density function (PDF), with a standard deviation of o, and a mean of zero. Therefore, the time domain model of thermal noise in an arbiter states that the sampling offset of an arbiter is not a single number, but rather a distribution of numbers that can be described with a Gaussian PDF. The mean of this distribution is tso and the standard deviation is ot. The sampling offset of an arbiter according to the time domain model of thermal noise in a biased arbiter is depicted in Figure 3.3. 22 >% !o ro _Q o tso T ime [s] Figure 3.3: P D F of the sampling offset of a biased arbiter taking into account thermal noise. I f the Gaussian P D F shown in Figure 3.3 is integrated over time, the Gaussian cumulative density function (CDF) is produced. This is a useful function since it specifies the probability with which tiso is less than or equal to a specific temporal value, as shown in Figure 3.4, where the temporal value o f interest is Td. 1 • TD \ ~ VI o 0 Figure 3.4: Gaussian C D F . Therefore, according to the time domain model o f thermal noise in an arbiter, the probability that a given Td is greater than or equal to the sampling offset o f an arbiter is given by the Gaussian C D F : P(C = \) = P(tso<Td) = ^ 1 + erf 7 \ crt42 (3.1) 23 where erf(x) is the "error function", encountered when integrating a normalized Gaussian function [23, 30]. It is interesting to note that the mean sampling offset of an arbiter, tso, can be found from either the PDF or the CDF of the arbiter's sampling offset. Using the PDF of the arbiter's sampling offset, ts0 can be calculated by finding the mean of the distribution. The CDF of the arbiter's sampling offset can be used to find tso by estimating the value of t that satisfies P(tiso < t) = 0.5, as illustrated in Figure 3.5. 1 • vi S 0.5 -o_ ^ t S o Time [s] Figure 3.5: Calculation of tStt from the C D F of the sampling offset of a non-ideal arbiter. Of course, i f both tso and o~, are known, then the PDF and the CDF of the arbiter's sampling offset are easily reproduced. 3.1.2 Non-Ideal Arbiters and Time Interval Measurement An interesting observation concerning the sensitivity of an arbiter to time intervals near tso can be explained with the use of Figure 3.6. The aforementioned figure depicts the response of a symmetric CMOS arbiter with thermal noise to various, time intervals. However, the x-axis in this figure has been altered to emphasize the extent to which the arbiter's output can vary with respect to the standard deviation of the thermal noise. 24 0 1 2 5 Figure 3.6: Sensitivity of the output of an arbiter to at-From Figure 3.6 it can be seen that the output of an arbiter exhibits a strong sensitivity to time intervals near the arbiter's mean sampling offset, tso. In fact, a time interval equal to tso -3o, almost always elicits a different response from the arbiter than one equal to tso + 3ot. Therefore, the sensitivity of such an arbiter is highly dependent upon the standard deviation of the thermal noise, ot. A test chip consisting of a 64-bit SOTDC has been fabricated in a 0.35 pm CMOS, and is described in [23]. Measurements from this test chip report a 0, of 0.35 picoseconds. This number suggests that a symmetric CMOS arbiter is suitable for time interval measurement when picosecond accuracy is required. 3.2 Direct Calibration Technique One very intuitive method to calibrate a sampling offset based flash TDC is to input a sequence of increasing time intervals (T<is) into the SOTDC, beginning with a known time interval. Each 7 j should differ from its predecessor by a constant amount of time, denoted as tA. The instantaneous sampling offset of each arbiter can then be estimated using the value of the first Trfto produce a positive transition at the arbiter's output. The calibration of an 8-bit SOTDC is illustrated in Figure 3.7. In this figure, two oscillators of slightly different frequency, denoted as oscA and oscB, generate the sequence of Ts-25 Ce C, 00000000 00000001 00000001 00000011 00000011 oscA I J | T D 0 |*JTD1 ^ - |T D 2 |«—JTD3 |< |T D 4 J ~ | _ oscB L i l _ t t Arbiter 1 Arbiter 2 Positive Transit ion Positive Transit ion Figure 3.7: Direct S O T D C calibration technique. The S O T D C shown in Figure 3.7 produces an 8-bit codeword for each 7^ and this codeword is generated from the concatenation o f the arbiter outputs, C8 - C;. Normally the arbiters are positioned in order o f smallest tso to largest. Under such a scenario, i f 0, is much less than the difference in the sampling offsets o f adjacent arbiters, then a thermometer code can be expected at the S O T D C output. A s previously mentioned, the instantaneous sampling offset o f an arbiter within the S O T D C can be estimated using the first Td from the sequence o f time intervals to produce a positive transition at the arbiter's output, as shown in Figure 3.8. o CL "3 O l _ <D - w < lISO T d [s] Figure 3.8: Response of an arbiter to a sequence of increasing time intervals. 26 Mathematically, the tiso of an arbiter can be bound with the following equation: Td(t-i) < tiso < Td(i) (3.2) where T^y indicates the first Td to produce a positive transition at the arbiter's output, and Td(i-i) indicates its predecessor. This equation can be rewritten as follows: Td(t)-tA< tiso<Td(i) N (3.3) Therefore, a reasonable estimate of tiso is: tiso = Td(i)-tJ2 (3.4) The error in this estimate of tiso is bound by ± tJ2. While it is useful to know tisa the real objective of any SOTDC calibration technique is to determine the mean sampling offset of an arbiter, tso. Therefore, repeating the process depicted in Figure 3.7 multiple times may yield different yet useful results, as illustrated in Figure 3.9. Repetit ion 1 Repeti t ion 2 Repeti t ion N o ^ o 0 tiso Ta [s] t i S 0 T d [s] tjSo Td [s] Figure 3 . 9 : Response of an arbiter to several repetitions of a sequence of increasing Ts-A histogram of an arbiter's response to N repetitions of a sequence of Ts can be plotted by summing the number of times the arbiter's output (C) is a logic ' V for each Td, as shown in Figure 3.10. Since the variation in tiso follows a Gaussian PDF, the histogram has 2 7 the shape of a Gaussian CDF, assuming a sufficient number of repetitions have been performed. Now, if the histogram data is normalized and an appropriate curve fitting function is used, such as a cubic spline function, a Gaussian CDF may be produced. From this CDF the mean sampling offset of the arbiter (tso) can be determined. This is accomplished by finding the point on the CDF curve for which the arbiter's output is a logic ' 1 ' exactly half the time. The temporal value that corresponds to this point is the estimated mean sampling offset of the arbiter, or teso. Figure 3.10: H is togram and C D F of the output of an arbi ter . In order to produce an accurate Gaussian CDF from an arbiter's response to a sequence of increasing time intervals, iA needs to be chosen carefully, as will be discussed in the following section. 3.2.1 A n a l y s i s As noted earlier, experimental results from a 64-bit SOTDC fabricated in a 0.35 pm CMOS process indicate that the standard deviation of the thermal noise in an arbiter is approximately 0.35 picoseconds [23]. This result places an important bound on the size of tA. If the chosen tA is approximately equal to or less than <5t, then the histogram and the resulting CDF constructed from the data collected during arbiter offset calibration will closely resemble those shown in Figure 3.10. To further explain, Figure 3.11 may be of use. In this figure, the time intervals used during calibration are plotted on the x-axis of the arbiter 28 sampling offset PDF. From this PDF a histogram of the arbiter's output for each Td input is drawn. This histogram is drawn with the assumption that the number of repetitions (N) is large enough to ensure that the collection of arbiter instantaneous sampling offsets produces an arbiter sampling offset PDF that is nearly Gaussian. N Measurements JiLJiL T d [s] F igure 3.11: Histogram of the output of an arbiter when t& < ot-The key observation to be made here is that since tA is approximately of the same magnitude as O/, a histogram which closely resembles a Gaussian CDF can be drawn, and curve fitting of this histogram to find the arbiter's sampling offset, as shown in Figure 3:10, can be done with reasonable accuracy. However, i f the chosen tA is too large, then the histogram may resemble the one shown in Figure 3.12. N Measurements tA -=>- Td[s] F igure 3.12: Histogram of the output of an arbiter when > ct. T d [s] 29 It can be observed from Figure 3.12 that there exists only a small number of useful data points to which a curve can be fitted. Applying a curve fitting function to a small number of data points inevitably leads to an error in the estimation of tso that is much larger than would otherwise be obtainable if tA had been properly chosen. The error in the estimation of tso, known as the calibration error, is defined as: tce teso - tso (3.5) As part of this thesis, a quantitative analysis of the relationship between tA and tce has been performed using a software model of the direct calibration technique, one that accounts for thermal noise in an arbiter. This model has been constructed using Matlab, and accepts tA and o~, as parameters, in addition to the tso of each arbiter in the array. Using this information, the model constructs a sequence of 7^ that are applied to the inputs of the array of arbiters. It is also possible to specify the number of repetitions (N) of the sequence of Ts via an additional parameter. The output of this model is the root-mean-square (RMS) value of tce for the calibrated array of arbiters, estimated using a 6-th order polynomial fit of the arbiter output histograms. In order to ascertain the capabilities of the direct calibration technique over a range of tA values, several simulations were performed using the aforementioned model. In each case the array was specified to be 100 arbiters long, and N was varied incrementally in powers of 10, beginning at 100 and ending at 1 000 000. In order to keep the results independent of o,, tA and the RMS value of tce are expressed in terms of o,. The results of eleven simulations for five different values of N are shown in Figure 3!13. 30 2.5 ^ N = 1e6 * - N = 1e5 ^ N = 1e4 * - N = 1e3 *c -N = 1e2 Figure 3.13: RMS tce/atvs. tjatusing the direct calibration technique. From Figure 3.13 it can be observed that i f tA ^ 6a,, then the R M S value of tce is approximately bounded by a,, for any value of N . "However, as tA continues to increase, so does the R M S value of tce. In fact, for tA > 4o~,, the R M S value of tce increases linearly with tA. By the time tA reaches 10a,, the RMS value of tce has already surpassed 2a,. For an SOTDC with a resolution of 1 ps, i.e., the sampling offset of each arbiter differs from that of its neighbours by 1 ps, an RMS tce equal to a, may be tolerable, assuming a, = 0.35 ps. However, an R M S tce equal to 2a, (0.7 ps) may not be tolerable. Therefore, i f such an SOTDC is calibrated using the direct calibration technique, the required tA may be less than 3.5 ps. This requirement may not be practical, as the accurate generation of known time intervals with picosecond temporal resolution is very difficult to achieve on-chip. One intriguing question which to this point has remained unanswered is the quantitative effect of thermal noise on the accuracy of the arbiter sampling offset estimations obtained using the direct calibration technique. This question can be answered by comparing the RMS tce from Figure 3.13 with the theoretical RMS tce of a noise-free arbiter that is calibrated using the direct calibration technique. To calculate the theoretical R M S tce of the 31 direct calibration technique, the standard RMS formula for a continuous distribution, as shown in Equation (3.6) [31], may be used. RMS(tce) = \P{tce)t, ce dtce \P(tce)dtc (3.6) To solve Equation (3.6), the limits of integration must be determined. In order to determine the limits of integration, the curve fitting procedure used in the direct calibration technique to estimate the tso of a noise-free arbiter must be understood. The response of a noise-free arbiter to a sequence of Ts is shown in Figure 3.14. As shown in this figure, the histogram of this response resembles a discrete-time step function. Since there are only two useful data points to which a curve can be fitted, the most sensible approach is to linearly interpolate between the two points in order to construct the CDF of the arbiter's sampling offset and approximate tso. Normalize Data P O Curve Fit tL 0.5 Td[S] Td[s] Figure 3.14: Histogram and C D F of the output of a noise-free arbiter. The error in this approximation, tce, can be described mathematically by recognizing that the sampling offset of a noise free arbiter is estimated as: teso - (Td(i) + Td(i-l))l2 - Td(j) - tJ2 (3.7) 32 where Td(i) indicates the first Td to produce a positive transition at the arbiter's output, Td(i-i) indicates its predecessor, and tA = Td(t) - Td(i-i). By noting that tso can fall anywhere in the range Td(i-i) to T^, the calibration error is bound by the following equation: -tJ2<tce<tJ2 (3.8) This relationship is illustrated in Figure 3.15, where the actual sampling offset of an arbiter is plotted versus its associated calibration error. Figure 3.15: tso versus tce for a noise-free arbiter using direct calibration. Now that the limits of integration have been found, the probability density function of tce must be determined before integration can be performed. Since the goal of this exercise is to find the RMS calibration error of a noise-free arbiter for a given tA, the arbiter's sampling offset must fall in the range Td(t-i) to 7 ^ with equal probability, otherwise the results would be dependent on the actual value of the arbiter's sampling offset. In addition, the integral of this probability over the range -tJ2 to tJ2 must be equal to 1, since the arbiter has a fixed sampling offset that is greater than Tdp-t) but less than 7 ^ . These two conditions stipulate that for-tJ2 < tce < tJ2, P(tce) = \ltA as shown in Figure 3.16. 33 \ 1/tA -0) O -4—' D. -W2 Figure 3.16: tce p robabi l i ty density function. With this knowledge, the theoretical RMS tce of a noise-free arbiter calibrated using the direct calibration technique can be calculated as shown in Equation (3.9). jP(tce)tce2dtce=-^= (3.9) 2 Equation (3.9) is plotted in Figure 3.17 along side the RMS calibration error obtained using the Matlab model described earlier, which incorporates the effects of thermal noise in an arbiter. It should be pointed out that the results of such a model can be highly dependent on the distribution of the arbiter sampling offsets. For example, if the sampling offsets of an array of arbiters fall in a very narrow range, one that is much smaller than the minimum tA used during simulation, then the RMS calibration error may appear to be independent of GT. This result is intuitively wrong since the presence of thermal noise in an arbiter should result in a Gaussian-like CDF, from which a more accurate estimation of tso can be made. To remove this dependency, tA was fixed during simulation, and ot was varied instead. The sampling offsets of the array of 100 arbiters were then assigned fixed values uniformly distributed over the range T^.]) to 7^. This made for a fair comparison with the noise-free scenario. W2 tce [S] RMS{tce) = . 2dt ce "lce \]P(tce)t \p(tce)dtce l | / 34 3 i tA / Q t Figure 3.17: R M S tcelo, vs. tJot using the direct calibration technique. Inspection of Figure 3.17 reveals that for 2 < tJot £ 10, the presence of thermal noise in an arbiter significantly increases the accuracy of the arbiter sampling offset estimations obtained using the direct calibration technique. This result is expected since the presence of thermal noise in an arbiter contributes to a Gaussian-like CDF of the arbiter's sampling offset, from which a reasonably accurate estimation of tso can be made. This is in contrast to the ramp-like CDF of a noise-free arbiter, for which the best approximation is a straight line interpolation, which has a significantly larger RMS error! Inspection of Figure 3.17 also reveals that the gain in accuracy from the presence of thermal noise in an arbiter diminishes as tj<5, is decreased from 2. Further insight in to this result can be acquired if Figure 3.17 is redrawn with logarithmic x and y axes, as shown in Figure 3.18. 35 D 00 1000 100 10 1 0.1 0.01 0.001 0.1 - t _| :;::_!• i: ; : i . . . . - | -I | I I4 i i = 3 ^ | E r E | = H : U : | A; A; br-fctt z=:z:prf:.qz]zpi:|f 10 t A / a t 100 -*-N= 1e6 -s -N= 1e5 - A r - N = 1 e4 - X - N = 1e3 - * - N = 1e2 -•— Noise-free 1000 Figure 3.18: Log- log plot of R M S tcJcrtvs. tjat using the direct calibration technique. From Figure 3.18, it can be observed that when tjo, is decreased, the RMS value of tcJot reaches a saturation point somewhere in the range 0.2 S tjat S 1, depending upon the number of repetitions performed. This implies that the actual RMS value of tce increases as one moves deeper into the saturation region, since <5t increases as one moves closer to the y-axis, and the ratio of tce to c, is constant. By inspection of Figure 3.18, the rate at which the RMS value of tce increases as tJot moves deeper into the saturation region is unclear. In order to clarify this, actual values of tce can be obtained i f tA is fixed to a particular value and o ( varied. For example, the rate at which the RMS value of tce increases as tjat decreases can be estimated from Figure 3.19, where tA has been fixed at 10 ps and a, has been varied. The data required to plot Figure 3.19 is actually a special case of data displayed in Figure 3.18. For this reason Figure 3.18 is a more useful plot in a general sense, but.not as convenient for a specific scenario. 36 100 n 10 en Q . ~ 1 CO 0.1 0.01 1 k_* A_i A * 4 [ % £ i £ i £ 1 CT :7=:p::..; -~4-rH : : :|:.-.(• p:[ ... | - .".j "]4.I.:|..T:|: - e - N = 1e6 - ^ N = 1e5 - * - N = 1e4 - * - N = 1e3 - * - N = 1e2 -•— Noise-free 0.1 1 10 a , [ps] 100 Figure 3.19: Log- log plot of R M S tce vs. a , when tA = 10 ps, using the direct calibration, technique. Through inspection o f Figure 3.19 it is apparent that an optimal ratio between tA and a, exists, and is dependent upon the value o f N . This ratio has been found to hold true for any value o f tA. Therefore, by determining the value o f a, that minimizes tce for each o f the five curves displayed in Figure 3.19, it is possible to determine the optimal ratio o f tA to a, given the desired number o f repetitions. The optimal ratios for five different values o f N are summarized in Table 3.1. Table 3.1: Opt imal ratio of tA to at given the number of repetitions performed. N le2 le3 le4 le5 le6 tAIOt 2 1 0.8 0.6 0.4 37 This information can be used in the selection of tA for the direct calibration technique. For example, i f O", is equal to 0.35 ps [23] and N = le5, the value of tA which would produce the lowest tce is 0.35 ps x 0.6 = 0.21 ps. Of course, the accurate generation of time intervals with such a temporal resolution is a very difficult task. With this knowledge in hand, it is easier to explain why the gain in accuracy from the presence of thermal noise in an arbiter diminishes as tJot is decreased from approximately 2. Through inspection of Figure 3.19, it can be seen that the farther one deviates from the optimal tjo, ratio, the larger the calibration error. For example, i f G, is much smaller than its optimal value for a given tA, hence much smaller than tA, the difference between tce in this case and that of a noiseless arbiter calibrated using the same tA becomes increasingly diminished. This result makes intuitive sense, since as o, becomes very small with respect to tA, the CDF of the arbiter's sampling offset becomes less Gaussian-like and more ramp-like in appearance as the variation in the arbiter's sampling offset becomes less significant. Similarly, i f a, is much larger than its optimal value for a given tA, hence much larger than tA, tce once again exceeds its minimum value. In this case the increased error can be attributed to the incorrect use of a polynomial curve fitting function on the relatively linear histogram that is produced. 3.2.2 Conclus ions In theory, the direct calibration technique can produce very accurate estimations of tso given a sufficiently small tA. In fact, the accuracy of this technique is limited only by tA, which may be determined by the frequency difference of two oscillators. However in practice, this calibration technique has some very serious flaws. For example, any type of oscillator will have some amount of phase noise, and therefore wil l not have a perfectly stable frequency [32, 33]. Any instability in the frequency of either of the two oscillators can result in an increased error in the estimate of tso. In fact, it may not even be possible to place a bound on the error as the amount of phase noise in either oscillator may be unknown. 38 Another problem with this calibration technique concerns the requirement that the sequence of Ts must begin with a known Tj. One way to accomplish this may involve the use of an arbiter with a known sampling offset to detect alignment between the rising edge transitions of the two oscillators. However, as discussed in [23], the sampling offset of a reasonably sized arbiter may vary from its intended value by as much as 25 picoseconds. An error of 25 picoseconds in the initial Tj will propagate to the estimate of tso for each arbiter. One way to alleviate this problem is to oversize the transistors in the arbiter that is used for alignment. This will help to reduce the arbiter's sensitivity to process variations. However, even i f an arbiter with a known sampling offset is used to detect alignment between the rising edge transitions of the oscillators, there is still a quantization error in the edge alignment of at most tA seconds due.to the finite difference in the frequencies of the two oscillators. Also, any mismatch in the START and STOP signal paths will introduce some skew between them, and this skew will alter the sampling offset of the alignment arbiter by an unknown amount, adding another error to the estimate of tso. While the direct calibration technique is conceptually rather simple, it is not used in practice due to its many shortcomings; the most severe being the restriction placed on tA. The accurate generation of known time intervals with picosecond resolution is very difficult to achieve on-chip, and therefore renders this calibration technique ineffective for embedded applications. 3.3 Relative Offset Calibration Technique A technique capable of determining the relative sampling offsets of an array of arbiters is presented in [23, 25]. This technique analyzes the "bubbles" in the output codeword of an SOTDC. A codeword is said to be "bubble-free" i f there is at most one location in the codeword where adjacent bits differ. For example, an 8-bit "bubble-free" codeword may look like the following: "00001111". A codeword is said to contain a "bubble" if there are three locations where adjacent bits differ, as shown in the following codeword: "00101111". 39 / If there are more than three locations in a codeword where adjacent bits differ, then the codeword is said to contain more than one "bubble". "Bubbles" may appear in an SOTDC codeword when its resolution is comparable to a,. For example, if arbiters A; and A2 have sampling offsets of 100 ps and 101 ps, respectively, and a 100.5 ps time interval is applied to the inputs of both arbiters, the most probable outcome is that Aj will output a logic '1' and A2 will output *a logic '0'. However, there is a significant probability of the reverse scenario occurring, i.e., Ai outputs a logic '0' and A2 output a logic ' 1'. If this experiment is performed a sufficient number of times, this counter intuitive outcome is inevitable, and will occur with a certain probability. The ratio of these two probabilities can be used to determine the difference in the sampling offsets of arbiters A/ and A2. For example, if the probability of the more likely outcome is denoted as PAIA2(10), i.e., the output of ^ 4; is a logic ' 1' and the output of A2 is a logic '0', and the probability of the less likely outcome is denoted as PAJA2(01), then the ratio of these two probabilities, r = PAIA2(01)/PAIA2(10), depends only on S, which is the ratio of the difference in the sampling offsets of the two arbiters to 2oh i.e., S = (tSQA2 - tSOAi)/2dt. The exact relationship between these two ratios is derived in [23], where the following equation is produced: R = J W Q J ) _\ + ^ 8{erfcx{-8)) PAIAIW) l-4^8{erfcx{d)) The "erfcx" terms in the right hand side of the preceding equation are instances of the scaled complementary error function. In summary, the author in [23] proposes measuring r and inverting Equation (3.10) in order to find the relative sampling offsets of a pair of arbiters in terms of a,: However, the author does not present a viable on-chip solution for obtaining a,. In addition, a critical assumption about the mean sampling offset of the arbiters is made by the author, and is stated in [25]. In this work the author states that if the absolute sampling offsets of the arbiters are to be determined, then the mean sampling offset of the arbiters must be known. The author 40 suggests that the mean sampling offset of a large number of arbiters can be predicted i f the sampling offsets of the arbiters are altered by process variation alone, i.e., no attempt is made during the design of the arbiters to differentiate their sampling offsets from one another. In such a case the author predicts that the sampling offsets of the arbiters would follow a Gaussian distribution, as shown in Figure 3.20, where the mean sampling offset, denoted as Uso, is equal to the intended sampling offset of the arbiters. Figure 3.20: Gaussian distribution of arbiter sampling offsets due to process variation. For example, i f an array of 64 arbiters, designed to be perfectly symmetric, is fabricated on a single die, then the author predicts that the actual sampling offsets of the arbiters wil l follow a Gaussian distribution with a mean of zero. Several problems exist with this assumption. Firstly, since an SOTDC consists of a finite number of arbiters, it is difficult to ensure that the sampling offsets will vary according to a Gaussian distribution. While it is true that a distribution which closely matches a Gaussian may be obtainable i f an SOTDC is constructed using a very large number of arbiters, perhaps greater than 1000, the penalty to be paid in such a case is an excessive use of silicon area. Also, each arbiter may be subject to some constant amount of process variation which results in a common shift in the sampling offsets of all the arbiters. Such a scenario is not accounted for in the preceding assumption and will therefore increase the error in the estimations of the arbiter sampling offsets. 41 If the mean sampling offset o f an array o f arbiters cannot be determined with a reasonable degree o f confidence, then for the purpose o f time interval measurement, the only useful information that can be extracted from the arbiters is the amount o f variation in a series o f time intervals. For example, the standard deviation o f a series o f time intervals could be measured, however not the mean. Due to the aforementioned issues, the relative offset calibration technique is more interesting from a theoretical perspective than a practical one. 3.4 Added Noise Calibration Technique A calibration technique based on "added noise" has been described in [26]. This technique is fundamentally identical to the direct calibration technique, with the exception o f one important modification. Since a, has been measured to be approximately 0.35 ps [23], the direct calibration technique requires the accurate generation o f known time intervals with picosecond temporal resolution. This is a very difficult task to achieve on-chip. To better illustrate this requirement, ten different values o f tA have been simulated using the Matlab model described in section 3.2.1 with N = 100 000, while a, has been varied. The results o f these simulations are shown in Figure 3.21. 42 100 - e - 1 A = 10 ps - B - f A = 8 PS tA 6 ps tA = 4 ps t a = 2 ps - • — • *A = 1pS 100 Figure 3.21: Log- log plot of R M S tce vs. ot when N = 100 000, using the direct calibration technique. From Figure 3.21 it can be seen that i f a, = 0.35 ps, tA cannot be greater than 4 ps i f tce is to be kept below 1 ps. In reality, calibration accuracies greater than 1 ps are required for high-resolution SOTDCs. While it is possible to increase N in order to alleviate some of the restrictions placed on tA, demands placed on the total calibration time usually limit N to 100 AOOOorless [34]. In order to circumvent the restrictions placed on tA, the authors in [26] suggest adding Gaussian temporal noise to the arbiters in an SOTDC. In fact, the authors advocate adding Gaussian temporal noise with a standard deviation much larger than o,. A large amount of Gaussian temporal noise drastically alters the restrictions placed on the temporal resolution of the time intervals. For example, through inspection of Figure 3.21 it can be seen that i f tA = lps and at = 0.35 ps, the predicted tce is 0.07 ps. Now i f o, is increased to 17 ps, tA can be increased to 10 ps while still maintaining the same tce. That is, a 49-fold increase in o~, allows for a 10-fold increase in tA without an increase in N or tce. 43 In order to understand how the authors in [26] propose to add Gaussian temporal noise to the arbiters in an SOTDC, a time domain model of thermal and added noise in a biased arbiter must first be presented, as shown in Figure 3.22. START C Z > t, IN1 OUT1 U N B I A S E D A R B I T E R i=> c •noise_added '•noise.Jhermal t s o STOP cz>L IN2 OUT2 L Figure 3.22: T i m e domain model of added and thermal noise in a biased arbiter. The added Gaussian noise is modelled with the inclusion of a second variable delay buffer. Both the added Gaussian noise and the intrinsic thermal noise act to vary the sampling offset of the arbiter, however to different extents. An illustration of the contribution of each noise source, superimposed on one another, is shown in Figure 3.23. Figure 3.23: A r b i t e r sampling offset P D F with thermal and added noise. Assuming the noise sources are independent, the standard deviation of the arbiter's sampling offset can be determined with the aid of the following equation: Time [s] t, •so (3.11) 4 4 If the standard deviation of the added noise is chosen to be much greater than that of the thermal noise, i.e., oadded > : > G,, then atolai can be accurately approximated as <5added-Instead of injecting Gaussian temporal noise directly, into the arbiters themselves, the authors in [26] suggest modulating the time intervals. This clever idea provides a simple mechanism to effectively vary the sampling offset of an arbiter according to a Gaussian distribution without the need to actually change the arbiter's circuitry. Figure 3.24 illustrates how a CDF of an arbiter's sampling offset is created from a sequence of time intervals, where each time interval is distributed according to a Gaussian distribution with a standard deviation of Gadded. 1 i .—' Probabil Oadded k-+ M i f I. I ^ s o l I Td [s] i 1 • !L 0.5 O CL y i 0 i • Tdi Td2 Td3 TdM Td [s] Figure 3.24: Addition of Gaussian temporal noise to a sequence of time intervals in order to create an arbiter sampling offset CDF. In order to generate a sequence of accurately known time intervals with Gaussian distributions, the authors in [26] propose the use of a configuration as illustrated in Figure 45 3.25. In this configuration, a production tester or an on-chip D L L is used to generate the accurately known time intervals. The time intervals are then modulated by the Gaussian control voltage of a variable delay buffer. Figure 3.25: Added noise calibration technique implementation [26]. The feasibility of such an approach will be discussed in section 3.4.2. 3.4.1 Ana lys i s The authors in [26] have created a Matlab model of the added noise-based calibration technique and have reported the results of a small number of simulations. These results are displayed in Table 3.2. Table 3.2: Reported results from Matlab simulation of the added noise-based calibration technique (tA = 40 ps, a , = 250 ps, N = 100 000) [26]. Arbiter Offset [ps] Calibrated Offset [psl Error [ps] -35.00 -18.31 -2.00 5.00 6.00 17.40 27.50 -34.60 -17.91 -2.12 5.30 5.43 17.10 27.47 0.40 0.40 -0.12 0.30 -0.57 •-0.30 -0.03 46 The authors in [26] have chosen to perform their simulations with tA = 40 ps, O, = 250 ps, and N = 100 000. Calculation of the R M S error of the results in Table 3.2 yields 0.35 ps. This result can be compared with the predictions of the Matlab model of the direct calibration technique described in section 3.2.1. It should be noted that such a comparison is valid as the added noise calibration technique is theoretically identical to the direct calibration technique. The only difference between the two techniques is the amount of Gaussian noise in an arbiter. Using the Matlab model of the direct calibration technique described in section 3.2.1, it is possible to plot the RMS tce versus a, when tA - 40 ps. Such a plot is shown in Figure 3.26. 100 - L . , , , . ; , , : , „ : , „ , , , 0.1 A 1 1 : : ' ' ' | : L ± l i i l | , 0.1 1 10 100 1000 CJtotal [ P S ] Figure 3.26: Log-log plot of R M S tce vs. a, when tA = 40 ps and N = 100 000, using the model of the direct calibration technique described in section 3.2.1. Inspection of Figure 3.26 reveals that according to the Matlab model described in section 3.2.1, the R M S value of tce is approximately 1 ps i f c, = 250 ps. However, the authors in [26] present data with an R M S value of 0.35 ps. This discrepancy may be due to the fact that a relatively small number of arbiters (7) have been simulated in [26], whereas 100 arbiters have been simulated with the Matlab model described in section 3.2.1. Further inspection of 47 Figure 3.26 reveals that according to the Matlab model described in section 3.2.1, it is possible to obtain an RMS value of tce as low as 0.3 ps when N = 100 000. However, in order to do so, a, must be reduced to 67 ps. This value agrees with the optimal tA to a, ratio of 0.6 when N = 100 000, as shown in Table 3,1. Calculation of the ratio of tA to a, used in [26] produces a result of 0.16, indicating that o, should be decreased in order to reduce the R M S value of tce. While it may be true that ot = 250 ps produces a relatively low R M S tce for the arbiter sampling offsets specified in Table 3.2, this result may not hold true for a more general distribution of arbiter sampling offsets, such as the uniform distribution used in the Matlab model described in section 3.2.1. The amount of time required by the added noise-based calibration technique to perform calibration is proportional to N and M , the number of repetitions and the number of time intervals, respectively, and inversely proportional to f, the frequency at which the time intervals are applied to the SOTDC START and STOP signals. This relationship is summarized with the following equation [26]. _MN (3.12) = / This is the same amount of time required by the direct calibration technique. However, some additional time is required to apply a curve fitting algorithm to the histogram data. 3.4.2 Conclus ions The added noise-based calibration technique proposed in [26] is useful in the sense that it allows the step size of the time intervals (tA) to be increased while still maintaining the same level of calibration accuracy. However, this method does not alleviate the need for accurately known time intervals. This is a significant issue as it infers that either the external production tester or the on-chip D L L must generate known time intervals with picosecond accuracy. As the accuracy of the time intervals suffers, so does the accuracy of the calibration results. For example, i f all of the time intervals generated by the external tester or 48 the on-chip D L L are 1 ps greater than their assumed values, then the R M S value of the calibration error will increase by 1 ps. This error will propagate to the results of time interval measurements made by the SOTDC. In addition, the on-chip variable delay buffers must be calibrated in order to ensure that they do not add unwanted skew between 0 i and 02, and also to ensure that a linear relationship exists between the voltage of the control signals and the delay of the buffers. For these reasons it can be said that the method of implementation of the added^ noise-based calibration technique proposed in [26] is neither an ideal nor a complete solution. The SOTDC calibration technique proposed in Chapter 4 does not require knowledge of the time intervals used for calibration. 49 Chapter 4 Proposed SOTDC Calibration Technique As discussed in Chapter 3, several SOTDC calibration techniques exist. However, it has been shown that all such techniques suffer from at least one serious limitation, thus rendering these proposals either unfeasible or insufficiently accurate. In order to address the need for a feasible and accurate SOTDC calibration technique, a new calibration technique has been developed. This technique leverages some of the advantages of the added noise-based calibration technique, while omitting some of its limitations. 4.1 Simplified Proposed Calibration Technique The calibration technique proposed in this thesis relies upon the availability of two oscillators with a known frequency difference. That is, two oscillators, namely oscA and oscB, are required. T f the frequency of oscA and oscB are denoted a s ^ and fs, respectively, then the frequency difference of the two oscillators can be denoted as/A-/A=/B -/A (4-1) 50 The same analysis can be performed in the time domain i f the period of oscA and oscB are denoted as TA and TB, respectively, and the period difference of the two oscillators is denoted as TA. ) TA=TB-TA (4.2) When oscA and oscB oscillate freely, the difference in time between the rising edge transitions of each oscillator can be interpreted as a sequence of time intervals (Ts), with each time interval being TA seconds shorter or longer than its predecessor, as shown in Figure 4.1. • HTD1 HTD2 l T d 3 HTD4 HTDS o s c B ...I Figure 4.1: Time intervals created by two free-running oscillators. Figure 4.1 depicts the relative temporal locations of the rising and falling edge transitions of oscA and oscB. These waveforms are drawn with the assumption that both oscillators are perfecdy\table, and/B </A, or equivalently, TB> TA. A perfectly stable oscillator is defined as an oscillator that has a constant frequency, and hence a constant period. For the remainder of this section, oscillators will be assumed to be perfectly stable. In addition, arbiters will be assumed to be noise-free. Therefore, it will be assumed that the sampling offset of an arbiter is a constant value, independent of time. This assumption wil l make the explanation of the simplified proposed calibration technique easier to follow. The presence of temporal noise in the sampling offset of an arbiter will be considered in section 4.2. If the instant in time at which the output of oscB produces a rising edge transition is denoted as toscB, and i f toscA is defined analogously for oscA, then each time interval can be expressed mathematically as: 51 Tcl(i) — toscB(0 ' toscA(i) (4.3) where / denotes the i t h rising edge transition of an oscillator. Following this definition of a time interval, a sequence of time intervals N elements long, i.e., Tdi TJN, generated from the output of oscA and oscB can be defined as shown in Equation (4.4). Tdo) •— {Tdi, Td2, Td3, Td4, • • • TdN-i, TdN}', 1<'<N = {Tdi, TdI + TA TdI + 2TA, Tdl + 3TA ...TdI + (N-l)^}; 1</ <N (4.4) Through inspection of Equation (4.4) it can be seen that a general formula exists for the duration of a time interval generated from the output of two oscillators of different frequency. Such a formula is written in Equation (4.5), where / > 0. Td(i) = Tdi + (i-l)?4i (4.5) Equation (4.5) describes a linearly increasing sequence of time intervals, as shown in Figure 4.2. 1 2 3 4 5 6 7 8 9 10 11 Figure 4.2: Sequence of l inearly increasing t ime intervals. As discussed in Chapter 3, a periodic sequence of known time intervals can be used to determine the sampling offsets of an array of arbiters. It is possible to generate a periodic sequence of unknown time intervals from the output of two oscillators of different frequency 52 i f Tj(i) is restricted to a finite interval. For example, i f 7 ^ is bound by the following equation, 0 < Td(0 < TA (4.6) then a periodic sequence o f time intervals can be generated i f TAITA is an integer. Figure 4.3 illustrates how a periodic sequence o f time intervals can be produced from the output o f two oscillators o f different frequency, where 7^/7^ = 5. OSCA OSCB <— <— « «-T d i d2 T d 3 I d4 I d5 T r i »• « — d6 d7 Figure 4.3: Periodic time intervals created by two free-running oscillators. Inspection o f Figure 4.3 reveals that Td6 = Tdl and Td7 = Td2, or more generally, Td(o = Td(i-5) for / > 5. Therefore in general, i f TAITA is an integer, then a periodic sequence o f time intervals with TAITA unique values may be created from the output o f two oscillators o f different frequency. There is no need to physically impose a limit on the size o f T^,). This limit naturally occurs i f one oscillator is used as a reference edge generator, and the relative temporal location o f the other is used to indicate the duration o f the time interval, as is illustrated in Figure 4.3. Equation (4.5) can be rewritten to account for the periodic nature o f the time intervals generated from the output o f two oscillators o f different frequency, assuming TA/TA is an integer. Td(i) = Tdl +.[(/ - 1) mod (TA/TA)) TA; i > 0 (4.7) The periodic sequence o f time intervals described by Equation (4.7) is plotted in Figure 4.4, assuming TAITA = 5. 53 co 1 2 3 4 5 6 7 8 9 10 11 j \> T A /T A 1| Figure 4.4: Periodic sequence of time intervals generated from the output of oscA and oscB assuming TJT^ = 5. Inspection of Equation (4.7) reveals that one of the time intervals generated from the output of two oscillators of different frequency must be accurately known before the entire sequence of time intervals can be predicted. However, without this information, the entire sequence of time intervals is unknown, and therefore of no use to any of the calibration techniques discussed in Chapter 3. Their values could be determined i f an arbiter with a known sampling offset is used to detect alignment between the two oscillators. However, i f it was possible to determine the sampling offset of an arbiter, then a calibration technique would not be required in the first place. Even i f such an arbiter was available, any differences in the routing of the arbiter's inputs could significantly alter the arbiter's sampling offset. This in turn would affect the predicted values of the sequence of time intervals, and thus the accuracy of the calibration technique. As a result, the only useful information that can be directly extracted from a periodic sequence of unknown time intervals is the temporal difference between arbiter sampling offsets. This can be accomplished by counting the number of oscillator cycles elapsed between the "switching-events" of two arbiters, as illustrated in Figure 4.5. 54 oscA . . . I _ I. — ' Td1 —» Td2 Td3 -* Td4 + Td5 1 Td6 Td7 I Td8 |*| Td9 I. oscB 0 1 . 2 3 4 5 6 7 1 I Arbiterl Switching-Event Arbiter2 Switching-Event Figure 4.5: Determining the relative sampling offsets of two arbiters. In order to explain the meaning o f an arbiter's "switching-event", an arbiter's response to two important time intervals must be understood. A s discussed in Chapter 2, when a time interval which is less than the sampling offset o f an arbiter (tso) is applied to its inputs, the arbiter responds by asserting its OUT2 output while maintaining a low logic level on its OUT] output, i.e., OUT1 = ' 0 ' and OUT2 = T ' . On the other hand, i f a time interval which is greater than or equal to the sampling offset o f an arbiter is applied to its inputs, the arbiter responds by asserting its OUT1 output while maintaining a low logic level on its OUT2 output, i.e., OUT1 = ' 1 ' and OUT2 = ' 0 ' . Therefore, i f a sequence of time intervals is applied to the inputs o f an arbiter, such as the one plotted in Figure 4.4, where Tdi < tso, and TdQ ^ tso (Q = TA/TA is an integer), then for some Tdi < Td® 2 TdQ, the arbiter's response w i l l change from OUT1 = ' 0 ' and OUT2 = ' 1 ' to OUT1 = ' 1 ' and OUT2 = ' 0 ' . This event is known as the arbiter's "switching-event", and signifies that the arbiter's sampling offset has been surpassed or equalled by the most recently applied time interval, Td(i). Detecting the switching-event o f an arbiter is useful as the sampling offset o f the arbiter can then be estimated as Td(i-i) < tso ^ Tdp), where both Td(i-i) and Td(t) are unknown. Inspection o f Figure 4.5 reveals that the switching-event o f Arbiter2 occurs seven cycles after the switching-event o f Arbiterl. From this information one might surmise that the sampling offset' o f Arbiter2 is greater than that o f Arbiterl by 7TA seconds, or equivalently, tS02 = tsoi + 77^. However, it might be incorrect to form this assumption. In order to illustrate this point, Figure 4.6 may be o f use. Inspection o f Figure 4.6 reveals that 55 the difference in the sampling offsets of Arbiter! and Arbiter2 may vary from nearly 6T& seconds to almost 87/s seconds, while still maintaining an oscillator cycle count of seven. Arbi ter l Switching-Event Arbiter2 Switching-Event 0 1 2 3 4 5 6 7 i-1 1-4 • Tdi Td2 Td3 Td4 Td5 T d 6 Td7 Td8 Tdg Time [s] i > Figure 4.6: Variat ion in arbiter sampling offsets while still maintaining a constant cycle Therefore, the number of oscillator cycles elapsed between the switching-events of two arbiters provides enough information to estimate the relative temporal spacing between the sampling offsets of the arbiters to within a range of 2TA seconds. Using the scenario illustrated in Figure 4.5 as an example, Equation (4.8) describes the sampling offset of Arbiter2 in terms of the sampling offset of Arbiterl. Until this point, only perfectly symmetric or positively biased arbiters have been discussed. It is also possible to constmct a negatively biased arbiter. The behaviour of a negatively biased arbiter is illustrated in Figure 4.7. A buffer delay (Tdei) has been inserted before input IN2 of a perfectly symmetric arbiter in order to mimic the behaviour of a negatively biased arbiter. However in reality, the sizes of transistors within the arbiter are usually altered in order to induce a bias. count. tsoi + 67^ < tSQ2 < tsoi + 87^ (4.8) 56 tSo Td, oscA oscB oscA oscB OUT1 OUT2 n _ n _ n _ . . . H H H Tdi Td2 Td3 r u ~ i _ r Figure 4.7: Behaviour of a negatively biased arbi ter . Inspection of Figure 4.7 reveals that the sampling offset of the illustrated arbiter is greater than Tdi but less than or equal to Td2- Since Td(j) = tOSCB(i) - toscA(i), both Tdi and T<j2 are negative. As the difference between Tdi and Td2 is made increasingly small, the sampling offset of the arbiter can be found to be equal to -Tdei, as expected. Returning to the subject of Figure 4.5, it can be seen that the sampling offset of Arbiter! is a negative number. In addition, it can be seen that the magnitude of tsoi is greater than that of tso2, which is a positive number. Now, i f the inputs to Arbiter2 are somehow reversed, and its switching-event is redefined to occur when its input response changes from OUTl = 'V and OUT2 = ' 0 ' to OUTl = ' 0 ' and OUT2 = ' F , then the arbiter's sampling offset changes sign but not magnitude, as illustrated in Figure 4.8. This can be attributed to the topology of a symmetric CMOS arbiter. A typical CMOS D flip-flop does not share this property as its setup time is dependent upon the logic values of its present and previous inputs. 57 tso Tdel tso ~ -Td oscA oscB oscA oscB H H H oscB oscA oscA oscB T, d1 d2 n_rLj~L H H H d3 T d1 d2 T, d3 OUT1 OUT2 J~L OUT1 OUT2 (a) (b) Figure 4.8: Behaviour of a positively biased arb i ter (a), and a positively biased arb i ter w i th reversed inputs (b). This change in sign is extremely useful, as it provides a method of obtaining a second piece of information regarding the relationship between the sampling offsets of Arbiter! and Arbiter!. For example, i f the inputs to Arbiter2 are reversed while the inputs to Arbiter! remain unchanged, the relative temporal difference between the switching-events of the two arbiters changes. In fact, it decreases by exactly 2tso2. Therefore in theory, the sampling offset of Arbiter! can be estimated i f two pieces of information concerning the relative temporal difference between the switching-events of Arbiter 1 and Arbiter2 are obtained. The first piece of required information is the number of oscillator cycles elapsed between the switching-events of the two arbiters, with the inputs to both arbiters as illustrated in Figure 4.8 (a). The second piece of required information is the number of oscillator cycles elapsed between the switching-events of the two arbiters when the inputs to Arbiter2 are reversed, as illustrated in Figure 4.8 (b). From this information, the sampling offset of Arbiter2 can be estimated using Equation (4.9). 58 2tso2 = [cycleCoimt Arbiter! _ normal _ inputs TA)- [cycleCoimt Arbiter! _ reversed _ inputs t fycleCount Arbiter! _ normal _ inputs — cycleCoimt Arbiterl _ reversed _ inputs (4.9) This xresult is quite powerful as it demonstrates that it is possible to estimate the sampling offset o f an arbiter using two oscillators with a known frequency difference, a counter circuit, and a second arbiter with an unknown sampling offset. The need to generate a sequence o f known time intervals has been eliminated. In order to determine the theoretical accuracy o f Equation (4.9), it would be helpful i f the example illustrated in Figure 4.5 included information concerning the behaviour o f Arbiterl when its inputs are reversed. However, this would require knowledge o f the sampling offset o f Arbiterl. Therefore, in order to deduce the accuracy o f Equation (4.9), a value must be chosen for tso2. I f tso2 is arbitrarily fixed at 27^, then the number o f oscillator cycles elapsed between the switching-events o f Arbiterl and Arbiter2, when the inputs to Arbiterl are reversed, can be predicted. Under normal circumstances, i.e., when the inputs to Arbiter2 are not reversed, seven oscillator cycles are elapsed between the switching-events o f Arbiterl and Arbiterl. However, when the inputs to Arbiterl are reversed, its sampling offset changes sign, and is therefore equal to -2TA. Since each time interval differs by TA seconds from its predecessor, a decrease in tso2 of 47^ seconds corresponds to a decrease o f 4 oscillator cycles. Therefore, 3-oscillator cycles are elapsed between the switching-events o f Arbiterl and Arbiterl when the inputs to Arbiterl are reversed, as illustrated in Figure 4.9. 59 o s c A . . . I I HTdiHTd2HTd3 HTd4 HTds lTde lT d 7- lTds HT . . . . n _ d9 o s c B I.. 0 1 t I Arbi te i i Switching-Event Arbiter2 Switching-Event F igure 4.9: Osci l lator cycle count when the inputs to Arbiter2 are reversed. While it is important to know the number o f oscillator cycles elapsed between the switching-events o f Arbiterl and Arbiter!, for the purposes o f determining the accuracy of Equation (4.9), it is more insightful to know the temporal range o f tso2 that produces an oscillator cycle count o f three. A simple modification o f Equation (4.8), which provides an estimate o f tso2 in terms o f tsol assuming the inputs to Arbiter2 are not reversed, can yield such results. Since it is known that tso2 with reversed inputs is 4TA seconds less than tso2 without reversed inputs, <\TA seconds can be subtracted from all o f the terms in Equation (4.8) to make the required modification, as shown below. tsoi + 6TA - 47'A < tso2 - 4TA < tsoI + %TA - 4TA tsol 27^4. ^ tso2_reversed_inputs — ^sol (4.10) A summary o f the information contained in Equations (4.8) and (4.10) would be useful in order to make a conclusion regarding the accuracy o f Equation (4.9). Figure 4.10 serves as such a summary. 60 Arbiterl Switching-Event Arbiter2 Switching-Event (reversed inputs) Arbiter2 Switching-Event (normal inputs) 0 1 2 3 4 5 6 7 1-1 1.4 J...J Tdi Td2 Td3 Td4 Td5 Td6 Td7 Td8 Tdg Time [s] *—<—• T A Figure 4.10: S u m m a r y of the information obtained by counting the number of oscillator cycles elapsed between the switching-events of two arbiters. Through inspection of Figure 4.10 it can be seen that different values of tso2 may satisfy the relationships that have been found to exist between Arbiterl and Arbiter2. In fact, a range of tso2 values exist which satisfy the aforementioned relationships. In order to quantify the accuracy of Equation (4.9), the worst-case error in the estimation of tso2 must be determined. The worst-case error occurs when the range of tso2 values which satisfies the aforementioned relationships is maximized. The maximum and minimum difference between tso2 and -tso2 can be found through inspection of Figure 4.10, as shown below. Comparison with the known value of IT A reveals that the error of the simplified proposed calibration^technique can be bound as shown in Equation (4.12). 3TA < tso2 - {-tso2) < 5TA l.5TA<tso2<2.5TA (4.11) -772 < tce < TJ2 (4.12) 61 These error bounds are equivalent to those of the direct calibration technique as discussed in Chapter 3, assuming a noise-free arbiter. If the RMS error of the simplified proposed calibration technique is calculated assuming uniformly distributed arbiter sampling offsets, then Equation (4.13) is produced. RMS(tce) = (4.13) This result is equivalent to the R M S calibration error of the direct calibration technique, assuming noise-free arbiters as discussed in Chapter 3. Therefore, it can be concluded from the preceding analysis that for noise-free arbiters, the error of the simplified proposed calibration technique is equivalent to that of the direct calibration technique. 4.2 Non-Ideal Arbiters and Added Noise As discussed in Chapter 3, the sampling offset of a non-ideal arbiter is not a fixed number, but is instead characterized by a Gaussian probability density function. As a result, two identical time intervals can induce a different response from the same arbiter. However, this fact can be exploited, as is done by the added noise-based calibration technique of Chapter 3, to improve the accuracy of the proposed calibration technique. For example, i f Gaussian temporal noise with a standard deviation much larger than o, is added to the sequence of time intervals, many oscillator cycle counts can be recorded and then averaged in order to obtain a more accurate estimation of tso. In such a case, Equation (4.9) must be rewritten as shown in Equation (4.14), where TV refers to the number of oscillator cycle counts recorded when the arbiter's inputs are connected normally (state S = 0) or reversed (state 5=1). T tso = {totalCycleCount s = 0 — totalCycleCount s =,)—— (4.14) 62 In order to explain this assertion it is necessary to examine Figure 4.11. which illustrates the P D F o f each Td within a sequence o f Ts- In addition, the sampling offsets o f two arbiters, tso! and tso2, have been plotted along the x-axis. Note that both Figure 4.11 and the analysis to follow are predicated on the assumption that the Gaussian temporal noise added to each time interval is much greater than the intrinsic temporal noise within each arbiter, as explained in section 3.4 and depicted in Figure 3.22. Consequently, the sampling offset o f an arbiter can be treated as a constant value. (a) X I to xi o (b) X I ca xi o Tdi T d 2 Td3 T d 4 tsoi P( Td2 < t s „ , ) P( T d 2 £ t s oi ) / Tdio Tdn T d i 2 Tdi3 t S 02 P( Tal2 < tso2 ) P( Tdl2 S W ) T d [ s ] T d 2 tsoi T d [ s ] t. so2 Figure 4.11: (a) P D F of several Ts belonging to a sequence of Ts (b) P D F of two Ts (Note: the sampling offsets of two arbiters, tsol and tso2, are plotted along the x-axis of both figures). Through inspection o f Figure 4.11 (a) it can be seen that the sampling offsets o f Arbiterl and Arbiter2 are constant, while the instantaneous value o f each time interval, i.e., Tdi to Tdi3, is nondeterministic. A s a result, it is not possible to predict with absolute certainty the response o f either arbiter to any given time interval. Therefore, the number o f oscillator cycles elapsed between the switching-events o f these two arbiters is also 63 nondeterministic. This phenomenon is the direct result of the addition of Gaussian temporal noise to each time interval. However, i f a sufficient number of oscillator cycle counts are recorded, then the statistical properties of the added temporal noise can be leveraged to obtain a very accurate estimation of tso. For example, i f a histogram of each Td is compiled while the oscillator cycle counts are recorded, the histograms will more closely resemble a Gaussian distribution as time progresses. If the histograms can be accurately modelled with a Gaussian PDF, then it is possible to mathematically describe the probability of occurrence for any oscillator cycle count. To further explain, Figure 4.11 (b) may be of use. This figure depicts the probability with which Td2 is greater than or equal to tsol, as well as the probability with which Tdi2 is greater than or equal to tso2. With this sort of information it is possible to construct an equation to determine the probability of any oscillator cycle count value. In order to construct such an equation it is first necessary to determine the probability of the oscillator cycle counter being triggered by each Td. In the case of Tdi this amounts to the probability that Tdi is greater than or equal to tsol, or P(Tdi > tsol). The equation which describes the probability of the oscillator cycle counter being triggered by Td2 is only slightly more complicated. The probability of such an event is equal to the probability that Td2 is greater than or equal to tso, and Tdi is less than tsoi. Therefore, this equation is dependent upon the outcome of two distinct events, i.e., Td2 being greater than or equal to tsol zn&Sdi being less than tsol. However, since these events are independent, i.e., the value of Td2 is not dependent upon whether or not Tdi was less than tso, since the added temporal noise is random, their probabilities can be dealt with individually. Mathematically these events are known as statistically independent variables [35, 36], and the probability of these two events occurring can be solved as shown in Equation (4.15), where A and B represent two independent events, and A H B is the mathematical intersection of these two events. P(AfYB) = P(A) • P(B) (4.15) 64 V Therefore to summarize, the probability of the oscillator cycle counter being triggered by Tdi or Td2 is formally expressed in Equations (4.16) and (4.17), respectively. P(Td! triggers) = Y(Tdl > tso,) P(Td2 triggers) = Y(Td2 > tsol fl Td, < tso!) = P(T*2 * tsoi) • ?(Tdl < tsol) With this information in hand it is now possible to construct Equation (4.18), which can be used to determine the probability of the oscillator cycle counter being triggered by any Td, which may be represented as Td0). This equation follows directly from the preceding analysis. P(TdU) triggers) = P(TdU) > t„,) • f[p(Tm < tsoX) ( 4 A 8) 1=1 The following definitions must also accompany Equation (4.18). P(Td>tS0) = ± ?(Td<tS0) = l- ~P(Td>tSo) Now that it is possible to determine the probability of the oscillator cycle counter being triggered by any T V it is also possible to construct an equation to determine the probability of a specific oscillator cycle count. Using an oscillator cycle count of 1 as an example, many different scenarios can be constructed to achieve this value. For example, the counter could be triggered by Td! and stopped by Td2, thus producing a count of 1. It is also possible for the counter to be triggered by Td2 and stopped by Td3, therefore producing the same result. In fact, it is theoretically possible for any Td and its successor to start and stop (4.16) (4.17) l + erf fT -t A 1 d lso V ° ' t o t a l ^ J 65 the counter respectively. This fact is described in Equation (4.19), where the mathematical union o f these individual events is represented with the symbol ' U ' . P(Count = 1) = F([Tdl triggers fl Td2 stops] U [Td2 triggers fl Tdi stops] .. . (4.19) U [TdM-i triggers fl TM stops]) Whi le Equation (4.19) is mathematically concise, it is o f no use in predicting the probability o f a specific oscillator cycle count unless the union o f the events described in this equation are known. In order to solve the aforementioned equation, the mathematical definition o f the union o f two events must first be understood. Shown in Equation (4.20) is the definition o f the mathematical union operation. P(AUB) = P(A) + P(B) - P(AflB) (4.20) However, Equation (4.20) can be simplified by noting that each o f the events described in Equation (4.19) are mutually exclusive, i.e., it is only possible for one event to occur for any single oscillator cycle count, and thus the intersections o f these events are required to be zero. For example, i f event A represents the scenario that Td! triggers the oscillator cycle counter while Td2 stops it, it is not possible for some other event B to occur, which may represent the scenario under which Td2 triggers the oscillator cycle counter and Tdi stops it. This can be reasoned logically by observing that, for example, i f TdI is to trigger the oscillator cycle counter then it is not possible for Td2 or any other Td to re-trigger the counter until it has been stopped. Similarly, i f Td2 stops the oscillator cycle counter then it is not possible for Td3 or any other Td to stop the counter until it has been re-triggered. Therefore, events A and B can be said to be mutually exclusive since they can never occur simultaneously, and Equation (4.20) can be simplified to Equation (4.21), which describes the probability o f the union o f two mutually exclusive events. P(AUB) = P(A) + P(B) (4.21) 66 With the preceding information in hand it is now possible to simplify Equation (4.19), which describes the probability of an oscillator cycle count of 1. Equation (4.22) is the result of this simplification. \ P(Count = 1) = P( [Tdi triggers D Td2 stops] U [Td2 triggers D Td3 stops] ... U [TdM-i triggers f) T^M stops]) = F(Td! triggers)P(rrf2 stops) + V(Td2 triggers)-P(rrf5stops) ... + P(TdM-i triggers)-P(7W stops) {A.22) Finally, as shown in Equation (4.23), it is possible to write a simplified general equation to determine the probability of any oscillator cycle count. The symbol 'M' in Equation (4.23) represents the index of the last Tjthat is applied to the array of arbiters. M-j P(Count = / ) = ] £ P(Td(i) triggers) • P(Td0+n stops) ( 4 23) The equation which describes the probability of a specific Td stopping the oscillator cycle counter is given in Equation (4.24). This follows directly from the analysis used while writing the equation that specifies the probability of triggering the oscillator cycle counter, which for the sake of convenience has been reproduced below. P{Tm+j)stops) = P{Td^j)>tso2y f[P{Tdik)<tso2) ( 4 24) k= i+1 • P(Td0) triggers) = P(Td(l) > tso]) -Y[P{Td{k) < tml) ( 4 . 2 5 ) Now that it is possible to determine the probability of any oscillator cycle count, this information can be used to plot the probability of a range of oscillator cycle counts when the inputs to Arbiter2 are both reversed and normal, as shown in Figure 4.12. 67 0.2r 0.15 -IQ TO 0.1 -n o CL 0.05 -Probability of Oscillator Cycle Counts (Arbiter2 with normal inputs) 0.2 1 i i i i i 0.15 _ TO 0.1 X ) / / \ O ct 0.05 - / \ / \ 0 i — i i — — i . 1 — 10 20 60 70 30 40 50 Cycle Count Probability of Oscillator Cycle Counts (Arbiter2 with reversed inputs) 10 20 30 40 50 Cycle Count 60 70 80 i I -/ ^ / / \ I / ' / i i \ \ \ X . I 1 1 I 80 Figure 4.12: Probability of oscillator cycle counts when Arbiter2 has both normal and reversed inputs. Through inspection of Figure 4.12 it can be seen that the PDFs of the oscillator cycle counts closely resemble Gaussian PDFs, which as stated earlier is the direct result of the addition of Gaussian temporal noise to the applied time intervals. Therefore, a good approximation of the oscillator cycle count when the inputs to Arbiter2 are either reversed or normal can be obtained by calculating the mean of the appropriate PDF. If these mean oscillator cycle counts are known, then estimating twice the sampling offset of Arbiter2 is a matter of calculating the difference in these mean values and multiplying by The result is written in Equation (4.26), where state S = 0 indicates that the arbiter's inputs are connected normally, and state 5=1 indicates that its inputs are reversed. 2 ' „ ={Ms=o-Ms-i)T* (4.26) 68 Equation (4.26) has been written with the assumption that the PDFs of the applied time intervals are perfect Gaussians. However, this assumption is only valid when an infinite number of time intervals are applied to the arbiters. In normal circumstances only a finite number of oscillator cycle counts can be recorded due to calibration time constraints as well as physical limitations such as the depth of the oscillator cycle counters. Therefore, to be of any practical use, Equation (4.26) must be rewritten to account for these realities. Such an equation has been written in Equation (4.27), where N refers to the number of oscillator cycle counts recorded when S = 0 or 1. It, totalCycleCount s = 0 N totalCycleCount s N r A (4.27) Next, Equation (4.27) can be rewritten to solve for the sampling offset of an arbiter, as shown in Equation (4.28). tso = [totalCycleCounts=0 - totalCycleCounts = i ) ^ ^ " (4.28) This equation is identical to Equation (4.14), and is therefore the core equation of the proposed SOTDC calibration technique. An analysis of the accuracy of Equation (4.28) and the proposed SOTDC calibration technique in general will be discussed in Chapter 5. 4.3 Oscillator Non-Idealities Until this point it has been assumed that two perfectly stable oscillators with a known frequency difference are available for use during SOTDC calibration, where TAITA is an integer. These oscillators are necessary to produce a periodic sequence of time intervals. However, in reality it is quite difficult i f not impossible to obtain a perfectly stable oscillator with a precisely known frequency. Even i f it was possible to build two such oscillators, the frequency of both would need to be chosen very carefully so as to ensure that a periodic sequence of time intervals could be generated. For example, i f the oscillators are named 69 oscA and oscB with periods of TA and TB, respectively, then TA/TA, where TA = TB - TA, must be an integer in order to produce a periodic sequence of time intervals. One technique that could be used to eliminate the need for the aforementioned oscillators is to lock both to the same reference frequency. For example, a single reference frequency could be used to generate both oscA and oscB by means of two Phase-Locked Loops (PLLs) with different divisors. Figure 4.13 illustrates this technique. ' i n Phase-Locked Loop #1 fout — A * f j n r Phase-Locked Loop #2 fout = B • f n r o s c A o s c B Figure 4.13: P L L implementation of oscA and oscB. The output of the two PLLs illustrated above can be described by Equations (4.29) and (4.30). fA~ A - fin, TA — —— A JB — B - fir,; TB -B (4.29) (4.30) Now, as long as Equation (4.31) yields an integer result, i.e., Q, then the sequence of time intervals produced from oscA and oscB is guaranteed to repeat itself every Q+l time intervals. T 1 A = Q (4.31) 70 TA=TB-TA (4.32) Substituting Equation (4.32) into Equation (4.31) produces Equation (4.33). TA (4.33) T -T 1B 1A Further manipulation of Equation (4.33) by means of substituting Equations (4.29) and (4.30) and then simplifying the result yields Equation (4.34). B Analysis of Equation (4.34) indicates that it is possible to generate a periodic sequence of time intervals by locking two PLLs to a single known reference frequency.' The only caveat to using this technique is that A and B (the PLL divisors) must be chosen according to Equation (4.34) such that the resulting Q (the number of time intervals before the sequence repeats itself) is an integer. Further observation of this technique reveals that TA does not need to be calibrated or measured as it can be calculated as long as fin is known. Lastly, it is possible to reverse the inputs to the array of arbiters within the SOTDC by simply swapping the divisors of the two PLLs. 4.4 Implementation The proposed SOTDC calibration technique can be implemented in a variety of ways, oftentimes requiring only a few, relatively simple, modifications to a basic SOTDC. One possible arrangement is illustrated in Figure 4.14. 71 oscA START oscB STOP REF ARBITER 1 REF ARBITER 2 IN 1 O U T 1 ARBITER 1 IN2 O U T 2 IN1 O U T 1 ARBITER N IN2 O U T 2 oscA REFERENCE ARBITER SWITCHING EVENT DETECTOR REF ARBITER OUTPUT REFCLK CAL COUNT EN DATA CAPTURE, STORAGE, AND OUTPUT CAL COUNT EN COUNT CLK DATA OUT ARBITER 1 OUTPUT ARBITER 2 OUTPUT c J ARBITER.3 OUTPUT ARBITER 4 OUTPUT ARBITER N OUTPUT Figure 4.14: Conceptual circuit view of the proposed calibration technique. 72 The arbiters labelled "ARBITER 7" through to 'ARBITER N" in Figure 4.14 are responsible for time interval measurement, and their sampling offsets must be calibrated. Two additional arbiters, "REF ARBITER 7" and "REF ARBITER 2", are required to realize the function o f Arbiter], i.e., to provide a fixed temporal reference point during calibration. A s was the case for Arbiterl, both arbiters are required to have negative sampling offsets, and the magnitude o f their sampling offsets must exceed that o f any arbiter that is used for time interval measurement. Ideally, the sampling offsets o f the two arbiters should be identical. In order to achieve such stringent matching requirements, the sizes o f the transistors which comprise the reference arbiters must be made very large, usually ten times that o f a normal arbiter. This w i l l help to mitigate sampling offset deviations caused by process, voltage, and temperature variations. A s illustrated in Figure 4.14, the inputs to REF ARBITER 1 are connected in an opposite manner tothose o f REF ARBITER 2. In addition, a multiplexer is used to select between the outputs o f the two arbiters, indicating that only one reference arbiter is used at any given time. When S = ' 0 ' , the sampling offset o f REF ARBITER 1 is a negative number. Therefore, its switching-event can be used as a temporal reference point from which it is possible to trigger an oscillator cycle counter. However, when S = ' 1', the sampling offset o f REF ARBITER 1 changes sign, thereby negating its role as a fixed temporal reference point. Nevertheless, it is possible to create a fixed temporal reference point i f REF ARBITER 1 and REF ARBITER 2 are used in tandem, as the sampling offset o f REF ARBITER 2 should be nearly identical to that o f REF ARBITER 1 when S = ' 0 ' since its inputs are reversed in comparison to those o f REF ARBITER 1. However, in order to ensure that the temporal reference point provided by REF ARBITER 1 is nearly identical to the one provided by REF ARBITER 2, special attention must be paid when routing the inputs to these arbiters. Otherwise, any mismatch in the input routings may result in a significant difference between the sampling offsets o f the two arbiters. 73 In order to detect a reference arbiter switching-event, a "REFERENCE ARBITER SWITCHING-EVENT DETECTOR" block is required. This switching-event detector samples the output of the reference arbiter multiplexer on the rising edge of a delayed version of oscA. When a switching-event is detected, the "DATA CAPTURE, STORAGE, AND OUTPUT' block is notified. This block consists of N oscillator cycle counters, one for each arbiter. The notification triggers the counters to begin counting on the rising edge of oscA. Each counter continues to increment its count until a switching-event is detected at the output of its respective arbiter. A more detailed circuit implementation of each of the aforementioned blocks can be found in Appendix A . It is important to note that the oscillator cycle counters required by the proposed calibration technique are almost always used in a basic SOTDC to quickly store the results of a large number of time interval measurements. Therefore, these counters would not normally increase the area of an SOTDC. However, it is possible to reduce the area consumed by these counters by sharing only one amongst the TV arbiters and calibrating each arbiter sequentially. It should also be mentioned that care must be taken when routing the START and STOP inputs of an SOTDC. Otherwise, electromagnetic coupling between these two input lines may significantly alter the oscillator cycle counts, which would adversely affect the accuracy of the proposed calibration technique. Lastly,-two additional circuits not illustrated in Figure 4.14 are required for successful implementation of the proposed calibration technique. These circuits include a Gaussian noise generation circuit [37] and a voltage-controlled delay buffer [38]. Together these circuits can be used to generate and then convert Gaussian noise from the voltage to the time domain, which in turn is used to modulate the time intervals applied to an SOTDC during calibration. 4.5 Summary The practical benefit accrued from the use of the proposed calibration technique is the ability to perform calibration without knowledge of the values of the time intervals applied to the SOTDC during calibration. Only knowledge of the temporal difference between adjacent 74 time intervals is required. This information can be acquired through the selection o f a reference frequency (//„) and P L L divisors (A and B) according to Equation (4.34). In addition, there is no need to apply a curve fitting function to the calibration results. Post-processing o f the results consists o f simple subtraction, multiplication, and division operations. Therefore, the post-processing requirements o f the proposed calibration technique are much less demanding than those o f either the direct or the added noise-based calibration techniques. Chapter 5 w i l l present a thorough analysis o f the accuracy o f the proposed calibration technique. 75 Chapter 5 Results and Analysis The proposed SOTDC calibration technique has been presented in Chapter 4. This presentation included a discussion of the proposed calibration technique's principle of operation as well as a conceptual circuit-based implementation. In addition, an equation was presented to estimate the sampling offset of an arbiter assuming an absence of temporal noise in both the arbiters and the time intervals. A theoretical bound was then placed on the error of the proposed calibration technique given an absence of temporal noise in both the arbiters and the time intervals, and this bound was shown to be identical to that of the direct calibration technique assuming the same conditions. Next, the discussion progressed towards the consideration of thermal noise in the arbiters and Gaussian temporal noise in the sequence of time intervals. A statistically-based mathematical equation was developed to gain further insight into the operation of the proposed calibration technique in the presence of additive Gaussian temporal noise. Eventually it was shown that the equation used to estimate the sampling offset of a noise-free arbiter could also be used to estimate the sampling offset of an arbiter exposed to Gaussian temporal noise. 76 It was then mentioned that the practical benefit accrued from the use of the proposed calibration technique is the ability to perform calibration without knowledge o f the values o f the time intervals applied to the S O T D C during calibration. Only knowledge o f the temporal difference between subsequent time intervals is required, i.e., TA must be known. Lastly, it was shown that TA does not need to be calibrated or measured as it can be calculated as long as the reference frequency and divisors o f the two P L L s which generate oscA and oscB are known. However, the error o f the proposed calibration technique was not addressed in the preceding discussion, as it is the topic o f this chapter. 5.1 Theoretical Error Bounds The statistically-based mathematical equations developed in Chapter 4 are reproduced below. These equations were derived in order to gain further insight into the operation o f the proposed calibration technique in the presence o f Gaussian temporal noise. M-j P(Count = j) = YjP(Td(i) triggers)-P(Td(i+J) stops) 1=1 P(Tdfi) triggers) = P(Tm > tsol)-f[P(TdW< tsJ P(Td{!+}) stops) = P(Td{HD>tso2)- f\P(Td(k)<tso2) k= i+l The symbol ' M ' represents the index of the last Td in the sequence o f TdS that is applied to the array o f arbiters. In addition, the definitions o f P(Td S tso) and P(7# < tso) are reproduced below, where the assumption has been made that the time intervals applied to the arbiters have been altered to fit a Gaussian distribution with a standard deviation much larger than that o f the random temporal noise which is intrinsic to the arbiters, i.e., a added Cf,, and therefore, a,otai ~ oadded-77 P{Td>(so) = ^ ?(Td<tso)=\--p(Td>tso) These equations can be used to determine the probability of any oscillator cycle count value. As stated in Chapter 4, estimating the sampling offset of an arbiter is then reduced to finding the difference in the mean values of the oscillator cycle count PDFs when the inputs to the arbiters are normal and reversed, and then multiplying the result by TJ2 as shown in Equation (5.1). T ' » = t a = o - / ^ = i ) y (5-1) However, one would only estimate the sampling offset of an arbiter using these statistically-based mathematical equations i f they wanted to determine the theoretical error bounds of the proposed calibration technique. This is true since the sampling offset of the arbiter in question is a required parameter of these equations. In addition, the sampling offset calculated using these equations is very likely to contain the smallest possible proposed SOTDC calibration technique error given a particular value of TA and oto/fl/. This assertion can be explained by realizing that the PDFs of the time intervals applied to the arbiters are assumed to be perfectly Gaussian when using the aforementioned equations. However, in reality only a finite number of oscillator cycle counts can be recorded due to calibration time constraints as well as physical limitations such as the depth of the oscillator cycle counters. As a result, the PDFs of the time intervals applied to the arbiters during SOTDC calibration are not perfectly Gaussian, and it is this deviation that introduces additional error into the actual calibration results. In an effort to ascertain the theoretically smallest proposed SOTDC calibration technique error, a Matlab model has been constructed using the statistically-based 1 + erf '' T -t ^ 78 mathematical equations. This model provides the ability to calculate the minimum error of the proposed SOTDC calibration technique for any value of TA and o,oto/. The model has been constructed using an array of 100 arbiters uniformly distributed across one TA. This was done to ensure that the results were independent of any particular sampling offset value. The RMS calibration error of 100 arbiters calculated using four different TA values and numerous values of o,otai is shown in Figure 5.1. 1E-15 -I 1 • • —I -I , 1 10 100 1000 10000 Ototal [PS] Figure 5.1: M i n i m u m error of the proposed calibration technique across four different TA values. Inspection of Figure 5.1 reveals that for each value of TA there is a range of atoto/ values which yield a dramatically lower calibration error (tce) than do the rest. In fact, it appears as if this range of atotai values yields the lowest calibration error that is achievable using the proposed calibration technique. However, this perceived calibration error floor is the result of a limitation in the numerical accuracy of the computer used to perform the calculations, and does not represent an actual limitation in the lowest achievable calibration error for a 79 particular TA value. The true limit may in fact approach zero as the standard deviation o f the added temporal noise moves closer to some optimal value o f o t o t o / . Inspection o f Figure 5.1 also reveals that the'shape o f the minimum error curve is constant across all four TA values. A s atoto/ is decreased from its optimal value the minimum calibration error increases sharply. However, as <5to,ai is decreased even further, the minimum calibration error eventually saturates. Whi le it is true that the saturation value is dependent upon the actual value o f TA, it can be shown that TA and the saturation value scale proportionally. Analogously, as r j t o t o / is increased from its optimal value the minimum calibration error increases sharply and eventually saturates to a value that is proportional to TA. In order to understand why the minimum calibration error changes the way it does as ototal is varied from its optimal value, a plot o f the oscillator cycle count PDFs for numerous Gtotai values may prove useful. Such plots are shown in Figure 5.2 and Figure 5.3. 0.7 0.6 0.5 I* 0.4 ! n co x i o im-probabi l i ty of Oscil lator Cycle Counts 0.3 0.2 0.1 0 0 10 20 30 - Total Std Dev = 3 ps - B — Total Std Dev = 10 ps Total Std Dev = 20 ps - g Total Std Dev = 40 ps (optimal) 40 50 Cycle Count 60 70 80 Figure 5.2: Oscillator cycle counts PDFs for several different values of Ototat, all of which are < a„ptimai (TA = 10 ps). 80 Inspection of Figure 5.2 reveals that as o,olai is decreased from its optimal value, the oscillator cycle count PDFs become less Gaussian and begin to more closely resemble a unit impulse. In fact, i f Oiotd is reduced to 0 ps, as is the case with the simplified proposed calibration technique discussed in section 4.1, the oscillator cycle count PDF transforms into an ideal unit impulse. This makes intuitive sense as the oscillator cycle count must be a constant value when there is a complete absence of temporal noise in an arbiter. As discussed in section 4.1 and derived in section 3.2.1, the RMS calibration error of the proposed SOTDC calibration technique can be obtained using the following equation when <5lolai = 0 ps: RMS(tce)~ T a 2V3 This assertion can be verified by comparing the results obtained from the preceding equation with those plotted in Figure 5.1 when o, o t o/ « cjoptimai. In summary, the minimum calibration error of the proposed SOTDC calibration technique increases as o t o t o / is decreased from its optimal value. This phenomenon can be explained by observing that the mean value of an oscillator cycle count PDF approaches a whole number as o t o t a / is decreased from its optimal value, thereby increasing the calibration error for arbiters with sampling offsets that are not integer multiples of TA. Inspection of Figure 5.3 reveals that as o~toto/ is increased from its optimal value, the oscillator cycle count PDFs become less Gaussian and eventually converge to an exponentially decaying curve. 81 Probabi l i ty of Osci l la tor Cyc le Counts Total Std Dev = 40 ps (optimal) Total Std Dev = 75 ps Total Std Dev = 200 ps Total Std Dev = 500 ps Total Std Dev = 10 000 ps 30 40 50 C y c l e Coun t 70 80 Figure 5.3: Oscillator cycle counts P D F s for several different values of ototai, all of which are > C5optimai (TA = 10 ps). Equation (5.2) has been written to mathematically describe the oscillator cycle count PDF curve when ototai» \tso_arbuer - tSo_ref_arbuer\, where tso_arbiter represents the sampling offset of the arbiter under calibration and tso_ref_arbiter the sampling offset of the arbiter used as an unknown temporal reference point. The variable n represents the oscillator cycle count value. p ( „ ) = I e m ( o . 5 ) ( n - . ) / n > Q 2 (5.2) Equation (5.2) indicates that the probability of a particular oscillator cycle count value is exactly half that of its predecessor. It is also evident from the preceding equation that an oscillator cycle count equal to one occurs with a probability of 0.5 when a t o to/ » \tso_arbuer -tso_ref_arbiter\- These two facts can be explained by realizing that once the oscillator cycle counter has been triggered by a particular time interval, i.e., a time interval that is > tso_ref_arbuer has been applied to the arbiters, any subsequent time interval may exceed tso_art,iler with a probability of 0.5. This behaviour is a direct result of the relationship between the added temporal noise and the difference between the sampling offset of the reference arbiter 82 and that of the arbiter under calibration, i.e., C5totai » \tso_arbiter - Uo_refjxrbuer\- Assuming the added temporal noise is purely random, i.e., its future behaviour is not dependent upon its past, and o~toto/ » \tso_arbiter - tso_ref_arbiler\, the probability of a particular oscillator cycle count can then be found using Equation (5.3). P{Count=j) =P(Td(J)>tm arbiter)-f[P{Td{k)<tS0 arhiter) k=\ f i V = -z ; J>O V2y (5.3) Returning to the discussion of the shape of the minimum calibration error curve (Figure 5.1) when <5,otal > ooptimal, it is now possible to predict the value at which the curve saturates. For example, it is now understood that when alotai » \tso_arbiter - tso_ref_arbiter\, the shape of the oscillator cycle count PDF is always an exponentially decaying curve. In fact, this is true regardless of the orientation of the arbiter's inputs, i.e., normal or reversed, as the logic presented in the previous paragraph applies to either situation. To be more precise, as long as a,otai » \tso_arbiter- ts0_ref arbiter] holds true, then the oscillator cycle count PDF is always an exponentially decaying curve that can be described using Equation (5.2) or (5.3). However, this infers that the estimation of the arbiter's sampling offset is always equal to zero, as shown below, where S = 0 indicates the arbiter's inputs are connected in a normal manner, and S = 1 indicates that they are reversed. < - = f a - o - A - i ) y = ( 0 ) ^ = 0 If the arbiter's estimated sampling offset converges to zero as Gtotai is increased to the point where it is » \tso_arbiter- tso_ref_arbiter\, then the calibration error must saturate at the value of the arbiter's sampling offset. In fact, this can be observed in Figure 5.1, where each curve saturates at the RMS value of the sampling offsets of the 100 arbiters specified in the aforementioned Matlab model. The saturation value changes from one curve to the next 83 since the sampling offsets of the arbiters are variable as they have been intentionally chosen to always span one TA. This ensures that the results are independent of any particular sampling offset value. Further inspection of Figure 5.1 corroborates the assertion that the saturation value of the calibration error is equal to the RMS value of the arbiters' sampling offsets, as it can be seen that the saturation values are proportional to TA. At this point it 'is instructive to remind the reader that the recommended implementation of the proposed SOTDC calibration technique does not employ alternate routing in order to reverse an arbiter's inputs. Instead, the divisors of the two PLLs used to produce the calibration oscillators are swapped to achieve the same effect. 5.2 Realistic Error Bounds ' Now that the theoretical capabilities of the proposed calibration technique have been presented, it is possible to discuss the accuracy of the proposed calibration technique under a more realistic set of conditions. Under such a scenario, the assumption that the PDFs of the time intervals are perfect Gaussians is no longer justified, as a practical SOTDC calibration technique must operate within a finite amount of time. A restriction on the total calibration time places a limit on the number of measurements performed during calibration, or in the case of the proposed calibration technique, results in a finite number of oscillator cycle counts that can be recorded. A finite number of oscillator cycle counts translates into time interval PDFs that are no longer ideal Gaussians, and as these time intervals become less Gaussian, so then do the PDFs of the oscillator cycle counts. Finally, as the PDFs of the oscillator cycle counts become less Gaussian, a greater error is introduced into the arbiter sampling offset estimation. This is true since a component of the equation used to estimate the sampling offset of an arbiter involves calculating the mean value of the oscillator cycle counts when the inputs to the arbiter are both reversed and normal, as shown in Equation (5.4). 84 (totalCycleCount \ r 5 = 0 N totalCycleCount s =, N T (5.4) It is possible to test the assertion that the error of the proposed SOTDC calibration technique should decrease as the PDFs of the oscillator cycle counts become more Gaussian. For example, it has been shown that the PDF of a random variable approaches that of a Gaussian distribution as the number of trials increases [39]. Therefore, it would seem logical for the error of the proposed SOTDC calibration technique to decrease as the number of measurement repetitions is increased. In an effort to validate this theory, a behavioural Matlab model representation of the proposed SOTDC calibration technique has been constructed. The decision to construct the model using Matlab as opposed to a circuit-based simulation environment was made on the basis of simulation time. The Matlab model was found to execute simulations up to 100 times faster than the circuit-based model, As the circuit-based model did not provide any additional insight into the capabilities of the proposed SOTDC calibration technique, it was decided to collect all data using the Matlab model. The input to the aforementioned Matlab model consists of the following four parameters: • The number of arbiters in the SOTDC. • T^. the temporal difference in the periods of the two oscillators that are used to calibrate the SOTDC. • Gtotai the standard deviation of an arbiter's sampling offset. This number includes the Gaussian temporal noise that is added to the output of one of the calibration oscillators, in addition to the Gaussian temporal noise that is intrinsic to each arbiter. • N: the number of measurement repetitions. 85 These four parameters can be used to predict the R M S calibration error (tce) o f the estimated sampling offsets o f an array o f arbiters. To ensure that the results o f this model are independent o f any particular sampling offset value, the sampling offsets o f the arbiters have been uniformly distributed across one TA. The model's method o f operation can be described as illustrated in Figure 5.4. \ 86 Start Simulation • Create arbiter array • Reset calibration oscillators • Reset and enable all oscillator cycle counters j r • Advance oscillators 1 cycle -j> • Add Gaussian temporal noise to output of oscA Advance^oscillators 1 cycle Add Gaussian temporal noise to output of oscA Increment enabled oscillator cycle counters ! * • For each arbiter: - Disable oscillator cycle counter if Td> /„, NO Re-enable disabled oscillator cycle counters NO Reference arbiter switching event ^occurred?,, YES Completed all measurements? YES Capture values of oscillator cycle counters End Simulation Figure 5.4: Flowchart describing the method of operation of the proposed SOTDC calibration technique Matlab model. 87 Each Matlab simulation produces an array of oscillator cycle counter values, where the length of the array is equal to the number of arbiters in the simulated SOTDC. In order to obtain the RMS calibration error of the estimated sampling offsets, two distinct simulations must be performed, each consisting of N measurement repetitions. The first simulation is performed with the S O T D C s oscillator inputs connected in a normal manner, while the other with the inputs effectively reversed. Therefore, the first simulation yields the number of oscillator cycles elapsed between the switching-events of the reference arbiter and the arbiter under calibration, while the second simulation yields the number of oscillator cycles elapsed when the inputs to the arbiter under calibration are reversed. The two oscillator cycle counter value arrays produced by these simulations can then be used to calculate the estimated arbiter sampling offsets. Equation (4.28), which for the sake of convenience has been reproduced below, should be used to compute the estimated arbiter sampling offsets. tso - [totalCycleCounts = 0 - totalCycleCounts = Lastly, the RMS calibration error can be determined using the array of estimated arbiter sampling offsets. As stated earlier, the error of the proposed SOTDC calibration technique is expected to decrease as the number of measurement repetitions is increased. This conjecture was formed based on two interrelated assumptions; the first of which states that the mean value of an oscillator cycle count PDF will deviate from that of an ideal Gaussian, even when an v . . . optimal value of o total is used. The second assumption states that this deviation should decrease as the number of measurement repetitions is increased. Fortunately, it is now possible to validate this conjecture using the Matlab model of the proposed SOTDC calibration technique. The aforementioned model has been used to produce three oscillator cycle count histograms, each of which have been generated using a different number of measurement 88 repetitions. In addition, an optimal value o f ctotai has been used, while only one arbiter was simulated. These histograms are shown in Figure 5.5. Histogram of Oscillator Cycle Counts CO 150 I 1 1 T 1 1 Cycle Count Histogram of Oscillator Cycle Counts Cycle Count Figure 5.5: Three oscillator cycle count histograms, generated using a different number of measurement repetitions. A s it is difficult to visibly discern the,mean values o f these histograms, their pertinent properties have been compiled into Table 5.1. Table 5.1: Properties of the oscillator cycle count histograms illustrated in Figure 5.5. N Mean fps] Standard Deviation fps] Error fpsl 1 000 41.2560 4.440 0.5150 10 000 41.0178 4.450 0.3135 100 000 41.0037 4.547 0.0184 Analysis o f the results presented in Table 5.1 reveals that while increasing the number o f measurement repetitions from 1 000 to 100 000 doesn't appear to drastically alter the mean 89 value or standard deviation o f the oscillator cycle count histograms, the R M S error o f the estimated arbiter sampling offset is observed to decrease by more than a factor o f twenty-five. In addition, the histograms can be seen to converge towards a Gaussian distribution as the number o f measurement repetitions is increased. In summary, the results o f Table 5.1 demonstrate that relatively small deviations in the mean value o f an oscillator cycle count P D F can have a significant impact on the accuracy o f the estimated value o f an arbiter sampling offset. However, the magnitude o f these deviations, and hence the error they introduce into the estimated arbiter sampling offset, can be drastically decreased by increasing the number o f measurement repetitions. N o w that the Matlab model o f the proposed S O T D C calibration technique has been shown to yield sensible results, it is possible to perform a more thorough error analysis. For example, it is now possible to compare the error o f the proposed calibration technique, given <a certain number o f measurement repetitions, with the minimum error calculated using the statistically-based mathematical equations.presented in section 5.1. One way to perform this comparison would involve plotting the realistic error o f the proposed calibration technique alongside the theoretical results o f Figure 5.1. Indeed, such a plot has been created, as shown in Figure 5.6, where the R M S calibration error o f 100 arbiters have been calculated using numerous values o f atora/ while TA has been fixed at 10 ps. 90 1000 n 1E-14 j-j-, i — , = 4 f - : '— 1~~ ~ 1 10 100 1000 10000 CTtotal [PS] Figure 5 . 6 : Comparison of the theoretical and realistic R M S error of the proposed calibration technique when TA = 1 0 ps. Through inspection of Figure 5.6 it is possible to form numerous insights regarding the capabilities of the proposed SOTDC calibration technique in addition to the correctness of the two Matlab models that have been created i n order to predict its behaviour. Firstly, it can be observed that the realistic and theoretical calibration errors saturate at the same value when a total is decreased or increased from its optimal value. This fact serves to further increase the credibility of the two Matlab models, which together predict the theoretical and practical capabilities of the proposed SOTDC calibration technique, as these models employ completely different algorithms. Secondly, it can be observed that both models produce similar optimal values of a total- However, the range of optimal <stotai values produced by the realistic model is wider than that of the theoretical model. This can be explained by realizing that a practical implementation of the proposed SOTDC calibration technique is subject to two different sources of error, whereas a theoretical implementation is only subject to one. 91 \ For example, both models predict that the calibration error will increase as CW/ is moved farther from its optimal value. The effects of a non-optimal Otolai value on an oscillator cycle count PDF are depicted in Figure 5.2 and Figure 5.3. However, only the realistic model is capable of predicting the effects of a finite number of measurement repetitions on an oscillator cycle count PDF, and hence the calibration results, as depicted in Figure 5.5. Therefore, as <3totai is brought close to its optimal value, the realistic model predicts that the largest contributor to an arbiter's calibration error is the finite number of measurement repetitions. As a result, arbiter calibration performed using a finite number of measurement J repetitions is shown to produce a much higher error than is otherwise theoretically possible. Conversely, as a to to/ is moved farther from is its optimal value, an arbiter's calibration error is predicted to be dominated by the non-optimal ololai value. Perhaps the most useful insight that can be learned through inspection of Figure 5.6 concerns the relationship between the R M S error of the estimated arbiter sampling offsets and the number of measurement repetitions. It can be seen that in general, increasing the number of measurement repetitions does indeed decrease the RMS error of the estimated arbiter sampling offsets. However, since the temporal noise that is added to the output of one of the calibration oscillators is random in nature, and therefore cannot be guaranteed to conform to a Gaussian distribution over finite time intervals, it is possible for the RMS error to actually increase as the number of measurement repetitions is increased. Nevertheless, the probability of this scenario quickly diminishes as the number of measurement repetitions is further increased. This assertion can be supported by examining Figure 5.7, which depicts the three non-ideal curves shown in Figure 5.6 over an optimal range of <5totai values. Also shown in Figure 5.7 are three linear approximations to the aforementioned data sets. 92 1 1 0.001 -I ! ! ; : : "• 1 —, 10 100 0~total [PS] Figure 5.7: T h e R M S error of the proposed calibration technique when TA = 10 ps, plotted for three different number of measurement repetitions (N). While it can be observed from Figure 5.7 that it is possible for a tenfold increase in the number of measurement repetitions to have little positive effect on the R M S calibration error of the arbiter sampling offsets, it can also be seen that a one hundredfold increase wil l almost certainly provide a substantial reduction in this error. For example, i f the linear approximations are evaluated at <5totai = 30 ps, which is the optimal value of a,olai predicted by the statistically-based model, the resulting RMS calibration errors are approximately 0.3 ps, 0.06 ps, and 0.02 ps when N = 1 000, 10 000, and 100 000, respectively. Therefore, a fifteen fold reduction in the R M S calibration error of the arbiter sampling offsets is observed when the number of measurement repetitions is increased by a factor of one hundred. However, it should' be reiterated that due to the random nature of the temporal noise that is used to vary the oscillator time intervals, this improvement may vary significantly from one calibration to the next. While it is possible to reduce this random variation by fitting the oscillator cycle counts histogram to a Gaussian PDF curve before calculating its mean, similar to what is 93 performed as part of the Added Noise calibration technique of section 3.4, this would require a far more onerous post-processing step without contributing a meaningful improvement in calibration accuracy. As a final observation of Figure 5.7, it can be seen that it is possible to achieve an RMS calibration error well below 0.1 ps when TA = 10 ps through increasing the number of measurement repetitions to 100 000. In order to understand the .repeatability of the aforementioned results and their reliance on the chosen value of TA, three additional plots have been created, each using a different value of TA. Figure 5.8 depicts four data sets which are very similar to the ones shown in Figure 5.7, however in this case TA has been increased to 100 ps. Three key observations can be made from inspection of Figure 5.8. Firstly, increasing the number of measurement repetitions from 1 000 to 100 000 is observed to decrease the R M S calibration error by approximately a factor of ten. This result is in agreement with what was observed when TA= \0 ps. Secondly, a tenfold increase in the RMS calibration error is observed across all three measurement repetition values when compared with the results obtained when TA = 10 ps. Thirdly, and following directly from the two previous observations, approximately the same R M S calibration error is achieved with 100 000 measurement repetitions when TA= 100 ps as is achieved with 1 000 measurements when TA= 10 ps. Therefore, as TA is increased by a factor of ten, the number of measurement repetitions must be increased by a factor of one hundred in order to maintain the same calibration accuracy. 94 ( tn CL 1000 100 10 1 0.1 0.01 0.001 0.0001 1E-05 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 1E-13 1E-14 1E-15 10 100 Ototal [PS] : - -3 S B H Q S HE JJ iIiiplIljlpS|I|:: lilll:lEE|l:::EJ3::li? Elzl=l=i=lllliil|! i ' : : ^ ™ E : i ~ E E E E : : ^ • - -_ ~ * _ ~ Emit ihirlzlllSlsi! l l l l p l p p p l p l -a- Ideal Model - © - N = 100 000 - * - N = 10 000 - e - N = 1 ooo 1000 10000 Figure 5.8: Comparison of the theoretical and realistic R M S error of the proposed calibration technique when TA = 100 ps. Depicted in Figure 5.9 are four additional data sets produced when TAis further increased to 1 ns. Once again, the same three key observations can be made. For example, increasing the number of measurement repetitions by a factor of one hundred is shown to yield nearly a ten fold decrease in R M S calibration error. However, the predicted R M S calibration error is still approximately ten times greater than what was shown to be possible when TA= 100 ps, assuming the same number of measurement repetitions are performed. Lastly, in order to achieve the same RMS calibration error as was predicted when TA= 100 ps, the number of measurement repetitions must be increased by a factor of one hundred. Figure 5.10 depicts the R M S calibration error of the proposed technique when TA = 1 ps. 95 IE-12 - ::::::::;::::::.:r.;;: r ,^^p4^r-fc^'<- ^IJ^^Z^^^^ zzz~^~i~2Zn: 1 E - 1 3 - '~~^iirz;7i ~T!-~r izi^z^ii!^;rrLJi;^'i;Z i^z^iz^~|;:i^;iiu Z^ZZ^ IUXTLLXLII 1 E - 1 4 - zzLZZi ,I,,UJ,;I ,...ii„iizir:i:;;i;:ti3£ r~^z3z!z=SH: ^ ^!zi|iXJi!inili 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 Ototal [PS] Figure 5.9: Comparison of the theoretical and realistic RMS error of the proposed calibration technique when TA = 1 ns. 1 0 0 0 -i 1 0 0 -1 0 -1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 Ototal [PS] Figure 5.10: Comparison of the theoretical and realistic RMS error of the proposed calibration technique when TA = 1 ps. 96 Inspection of Figure 5.10 reveals that it is possible to achieve an R M S calibration error as low as 2 fs when 100 000 measurement repetitions are used. While calibration accuracies in the order of femtoseconds are certainly impressive, it is unclear what repercussions this level of accuracy will have on the required calibration time. It is possible to calculate the calibration time for any value of TA or N . The amount of time required by the proposed calibration technique to perform calibration is proportional to N and M , the number of measurement repetitions and the number of time intervals per measurement repetition, respectively, and inversely proportional to fB, the frequency at which the time intervals are applied to the START and STOP inputs of an SOTDC. To obtain the total calibration time, this result must then be multiplied by a factor of two. This is true since the calibration procedure is not complete until the oscillator cycle counts have been captured using both the normal and the reversed orientations of the S O T D C s inputs. This relationship is summarized in Equation (5.5). 2MN tcai = —r- (5-5) JB While Equation (5.5) can be used to calculate the required calibration time of the proposed calibration technique, it is not useful when predicting the impact of a particular value of TA on the total calibration time. A more convenient form of Equation (5.5) can be derived by recognizing that M , the number of time intervals per measurement repetition, is actually equivalent to Q, as shown in Equation (5.6). M = ^ = Q (5.6) - ' A As discussed in Section 4.3, Q is an integer chosen through careful selection of A and B, the P L L divisors, according to Equation (5.7). 97 0= 1 A _ } (5.7) B Therefore, after substituting Equation (5.6) into Equation (5.5), a new calibration time expression is produced, as shown in Equation (5.8). 27V _ 27V _ 2QN ^cal ~ r r r p — r _ r ~ r (5-8) JAJB^A JA JB JB While any one of the three relationships of Equation (5.8) can be used to calculate the total calibration time, it is most sensible to use an expression that does not include TA as a parameter. This is true since TA is actually a function of the chosen calibration oscillator parameters, i.e.,f/„, A, and B, and is therefore not independently selected. As previously mentioned, the calibration oscillators must produce a periodic sequence of time intervals, which can only be achieved through careful selection of the PLL divisors according to Equation (5.7). Once fin and the PLL divisors have been chosen, TA can be calculated according to Equation (5.9). T--k (59) If the chosen calibration oscillator parameters yield an unacceptable value of TA for the given accuracy constraints, then one or all offin, A , and B must be reselected. Table 5.2 contains four sets of PLL divisors that can be used to produce four different TA values, each differing from its predecessor by approximately a factor of ten. Table 5.2: Four P L L divisors (A and B) and their corresponding TA values (fm = 50 kH). A B Q TA Ips] 3335 2668 4 1 499.31 4191 4064 32 149.13 5397 5376 256 14.47 8196 8192 2048 1.19 98 Using the data contained in Table 5.2 it is possible to calculate the required calibration time of the proposed calibration technique over a range o f TA values spanning approximately 1.2 ps to 1.5 ns. Table 5.3 contains the resultant calibration times, with each TA value calculated across three different measurement repetitions numbers (N). Table 5.3: Time required to calibrate an SOTDC, assuming the PLL divisors of Table 5.2Gk = 50kH)[s]. ^ IPs! 1 499.3 149.1 14.5 1.2 1 000 5.98E-05 3.15E-04 1.90E-03 1.00E-02 N 10 000 5.98E-04 3.15E-03 1.90E-02 1.00E-01 100 000 5.98E-03 3.15E-02 1.90E-01 1.00E+00 W i t h this information in hand it is now possible to determine the effect that varying the value o f TA has on both the calibration time and accuracy o f the proposed calibration technique. To this end, the data contained in Table 5.3 has been plotted alongside a subset o f the data illustrated in Figure 5.6 through Figure 5.10 inclusive. . 99 1.00E+02 -i 1.00E-05 -I :- "\ : I ' : 1 ' M 1 : i 1 10 100 1000 10000 T A [ps] Figure 5.11: The effect of varying TA on the calibration time (tcai) and the calibration error (tce) (calculated using an optimal value of Gtotai)-It is immediately evident by inspection o f Figure 5.11 that the calibration error is adversely affected by an increase in the value o f TA, while just the opposite is true o f the calibration time. Whi le both observations are intuitive and have been supported either in theory or simulation, it is important to note that the trade-off which exists between calibration time and accuracy does have an intersection point, i.e., it is possible to assign an equal weighting to both calibration time and accuracy. However, since this intersection point is a function o f N , the number o f measurement repetitions, no universally optimal value o f TA exists. In fact, it can be observed from Figure 5.11 that the intersection points o f the calibration time and error data sets decrease as N is lowered, while they also occur at lower values o f TA. Therefore, i f both calibration time and error are o f equal importance, then it is possible to minimize both by reducing the number o f measurement repetitions employed during calibration in addition to appropriately reducing TA-100 While it is possible to reduce the calibration time and error o f the proposed calibration technique by lowering both N and TA the latter may require careful consideration. For example, as shown in Table 5.2, both P L L divisors (A and B) must be increased in order to produce a lower value o f TA, assuming the P L L input frequency (fin) remains constant. Whi le the desired frequency synthesis can be achieved by increasing the depth o f the counters in the P L L feedback path or by employing a cascaded P L L structure, a more serious issue o f unwanted temporal noise may exist. For example, as 7^ is decreased, the time intervals produced by the outputs o f the two calibration oscillators could begin to deviate substantially from their intended distributions, depending upon the nature o f the unwanted temporal noise. Therefore, there may be a practical l imit to how far TA can be lowered before unwanted temporal noise begins to limit the calibration accuracy o f the proposed calibration technique. 101 Chapter 6 Conclusions and Future Work As CMOS technology continues to advance, circuit timing problems are becoming more common and yet more difficult to diagnose. As a result, several sophisticated embedded time interval measurement techniques have been proposed to help address this growing problem. Perhaps the most promising of measurement techniques is the "sampling offset"-based flash time-to-digital converter (SOTDC). This embedded time interval measurement technique is capable of picosecond measurement accuracies in addition to millisecond test-times. However, the accuracy of an SOTDC is strongly dependent upon the capabilities of its calibration technique, and present SOTDC calibration techniques suffer from some very serious limitations. In fact, these limitations are so severe that present calibration techniques are impractical under realistic production test conditions. 6.1 Summary and Contributions In order to address the need for a feasible and accurate embedded SOTDC calibration technique, a new calibration technique has been proposed. This technique leverages the advantages of the added noise-based calibration technique, while doing away with its 102 limitations. The proposed calibration technique's method o f operation can be described as follows: 1) Two P L L s , each with carefully chosen divisors, are locked to a single known reference frequency and used to generate a periodic sequence o f time intervals. 2) The output o f one P L L is modulated such that its period distribution conforms to a Gaussian P D F , whose standard deviation has been appropriately selected. 3) A counter is then used to store the number o f P L L clock cycles that are elapsed between the switching-events o f a reference arbiter and the arbiter under calibration. Several thousand measurements are accumulated by the counter in order to increase the accuracy o f the estimated arbiter sampling offset. 4) The P L L divisors are then swapped in order to effectively reverse the inputs to the arbiter under calibration, and the counter is once again used to store the number o f P L L clock cycles that are elapsed between the switching-events o f a reference arbiter and the arbiter under calibration. 5) The sampling offset o f the arbiter under calibration is then estimated by performing simple mathematical operations on the captured counter values. The main contribution o f the proposed calibration technique is the ability to perform calibration without knowledge o f the values o f the time intervals applied to the S O T D C during calibration. Only knowledge o f the temporal difference between adjacent time intervals is required. This information can be acquired through the selection o f a reference frequency and P L L divisors according to Equation (4.34). In addition, there is no need to apply a curve fitting function to the calibration results. Post-processing o f the results consists o f simple subtraction, multiplication, and division operations. Therefore, the post-processing requirements o f the proposed calibration technique are much less demanding than those o f either the direct or the added noise-based calibration techniques. In order to understand the capabilities o f the proposed calibration technique, a set o f statistically-based mathematical equations were derived. These equations were used to 103 predict the estimated sampling offset of an arbiter calibrated using the proposed SOTDC calibration technique, and thus to determine the theoretical accuracy of this technique. These results were then compared to those of a behavioural Matlab model of the proposed calibration technique. It was concluded that the accuracy of the proposed technique is determined by the number of measurement repetitions performed during calibration, assuming a fixed value of TA and an appropriate value of 0"toto/. Finally, it was shown that it is possible to obtain both sub-picosecond calibration accuracies and sub-100 millisecond calibration times, while still placing realistic demands on the time intervals used during calibration, and hence the calibration oscillators. Therefore, the desirable features of the added noise-based calibration technique, i.e., sub-picosecond calibration accuracies using realistic time interval resolutions, have been maintained; however the impractical implementation requirements of such a technique have been eliminated. 6.2 Future Work While the SOTDC calibration technique proposed in this thesis has been discussed in some detail, the opportunity for further investigation remains possible. The following subsections present three avenues of future work. 6.2.1 T h e i m p a c t o f n o n - i d e a l i t i e s While it has been assumed over the course of this thesis that thermal noise is the only source of noise in an arbiter, in realty this is not the case. An arbiter fabricated in a modem CMOS process is subjected to several different sources of noise, each of which need to be considered in order to truly understand the potential of the proposed calibration technique. For example, power supply and substrate noise may alter the sampling offset of an arbiter in an unpredictable manner. However, it remains to be seen whether the resulting sampling offset variation would be significant enough to impact the recorded number of oscillator cycle counts, and hence the accuracy of the proposed technique. This is true since the 104 temporal noise that is added to each time interval, or equivalently to the arbiters themselves, may be so large as to dominate over the undesirable noise sources. Similarly, it has been assumed during the course o f this thesis that it is possible to generate a periodic sequence o f time intervals by locking two P L L s to a stable reference frequency. However, as shown in Table 5.2, the divisors employed in each P L L may be in the order o f several thousand. Whi le it is possible to achieve the desired frequency synthesis by employing a cascaded P L L structure, the resultant output signals may contain a significant amount o f unwanted phase noise. Again , the effect o f the undesired phase noise may depend upon the extent to which the time intervals are intentionally modulated. However, in order to understand the potential o f the proposed calibration technique, the limitations imposed by P L L phase noise must be identified. 6.2.2 C i r c u i t i m p l e m e n t a t i o n In order to prove the viability o f the proposed calibration technique, a working implementation must first be demonstrated. One possible embodiment o f the proposed calibration technique can be found in Appendix A , along with the schematics o f a 16-bit S O T D C circuit. A s shown in Appendix A , the output o f each arbiter, including the reference arbiter, is sampled using a delayed version o f one o f the calibration oscillators (PLLs ) . The reference arbiter is sampled in order to detect its switching-event, which is then used to trigger the 16 24-bit oscillator cycle counters o f the arbiters under calibration. However, an additional counter is required in order to determine the correct switching-event o f the reference arbiter, as the addition o f temporal noise to the time intervals can induce a false reference arbiter switching-event. Therefore, a counter is used as a shift-register to store the sampled output o f the reference arbiter over 24 cycles. This data can then be used to determine the number o f oscillator cycles for which the reference arbiter output has been sampled as logic ' 0 ' . In theory, as the number o f consecutive '0's in the shift-register grows, it becomes increasingly l ikely for a valid reference arbiter switching-event to occur. However, this 105 hypothesis has not been proven mathematically or experimentally, and is therefore a candidate for further exploration. Similarly, it should be demonstrated experimentally that a reference arbiter with'a constant sampling offset, irrespective o f the orientation o f its inputs, can be constructed from two over-sized symmetric C M O S arbiters with matched layouts. 6.2.3 Additional applications and SOTDC improvements W h i l e the primary focus o f this thesis has been the calibration o f an S O T D C , the proposed calibration technique may be useful in a wide variety o f applications. For example, the proposed calibration technique may be used to accurately calibrate the delay o f a variable delay line, instead o f the sampling offset o f a symmetric C M O S arbiter. Analogously, the proposed calibration technique may be used to measure the delay o f an inverter driving a known load. Such information is often helpful when estimating the strength o f a C M O S process, which in turn can be used to calibrate the bias currents o f analog circuitry on a shared die [1.8]. Lastly, a conventional S O T D C , such as the one presented in this thesis, is characterized by a limited dynamic range, i.e., the ratio o f the maximum to the minimum measurable time interval is generally less than one hundred. However, it may be possible to greatly extend the dynamic range o f an S O T D C , and therefore to increase its scope. For example, instead o f using a single S O T D C to measure a long time interval, it is conceivable that two S O T D C s could be used to divide the time interval into smaller, more manageable units; i.e., ones that do not exceed the dynamic range o f either S O T D C . Under such a scenario, it would then be possible to measure the entire time interval by alternating between the two S O T D C s when measuring the reduced time intervals. The creation o f the reduced time intervals may be achieved by pre-empting the STOP signal o f the active S O T D C before its dynamic range has been exceeded, while simultaneously initiating the measurement o f a new time interval on the alternate S O T D C by triggering its START signal. Once this process has terminated, the counters within the two S O T D C s may be analysed in order to estimate the 106 value o f the entire time interval. However, this proposal has not been formally investigated, and as such is a candidate for future examination. 107 References [1] D . A . Hodges, H . G . Jackson, and R. A . Saleh, Analysis and Design of Digital Integrated Circuits, M c G r a w - H i l l , 2003, ch. 10, 11. [2] M . X u , "Substrate Noise in Mixed-Signal Integrated Circuits," Ph .D. thesis, Center for Integrated Systems, Stanford University, Stanford, C A , U S A , 2001, ch 1, 2, 3. [3] K . Mol l ah , "Design of a Tunable CML-based Differential Ring Oscillator with Short Start-up and Switching Transients," M . A . S c . thesis, Dept. o f Electrical and Computer Engineering, University o f Bri t ish Columbia, Vancouver, B C , Canada, 2004, ch 2. [4] Jitter Fundamentals, W A V E C R E S T Corporation, 2001 [Online], Avai lable: http://www.wavecrest.conVteclmical/pdf/jittfun_hires_sngls.pdf [5] Jitter Measurements for CLK Generators or Synthesizers, M a x i m Integrated Products, Application Note, 2003 [Online], Available: http://www.maxim-ic.com/appnotes.cfm/appnote_number/2744 [6] Jitter Measurements in Serial Data Signals, LeCroy Corporation, White Paper, 2007 [Online], Available: http://www.lecroy.com/tm/Library/WhitePapers/PDF/WP_JitterMeasurement_in_Serial DataSignals.pdf [7] B . Analu i , J, F . Buckwalter, and A . Hajimiri , "Data-Dependent Jitter in Serial Communications," IEEE Transactions on Microwave Theory and Techniques, vol . 53, no. 11, November 2005. [8] Three Views Of Jitter, LeCroy Corporation, 2002 [Online], Available: http ://www. lecroy. com/tm/options/soft ware/j itter-and-JT A/page04. asp 108 [9] J. Kalisz, "Review of methods for time interval measurements with picosecond resolution," Institute of Physics Publishing, Metrologia 41, pp. 17-32, 2004. [10] M . L i , "Requirements, Challenges, And Solutions For Testing Multiple GB/s ICs In Production," ITCInternational Test Conference, Panel P8.3, pp. 1309, 2003. [11] Y . Zheng and K . L . Shepard, "On-chip oscilloscopes for non-invasive time-domain measurements of waveforms in digital integrated circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 3, pp. 336-344, June 2003. [12] T. Yamaguchi and M . Soma, " A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency. Clock Signals," Proc. 19th IEEE VLSI Test Symp. (VTS 01), pp. 102-110,2001. [13] H . Lane, "Improving Test Times with Fast Frequency, Amplitude and Waveform Switching," High Frequency Electronics, pp 32-37, November 2006. [14] SIA 3600 - Signal Integrity Analysis Solution, W A V E C R E S T Corporation, Application Note, 2003 [Online], Available: http://www.wavecrest.com/products/datasheet/SIA3600datasheet.pdf [15] High-Speed Serial Interface Test in Production, GuideTech Inc., 2004 [Online], Available: http://www.guidetech.com/pdf/wp/LeamCTIA/ITCGuideTechExhibitorPresentation-Oct2004finalgc.ppt [16] IP/Network Measuring Instruments, Anritsu Corporation, 2006 [Online], Available: http://www.anritsu.co.jp/Products/pdf_e/B05E_MP 1590B.pdf [17] T. M . Mak, M . Tripp, and A . Meixner, "Testing Gbps Interfaces without a Gigahertz Tester," IEEE Design & Test of Computers, July-August 2004, pp. 278-286. [18] R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, "1.3V 20ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS," IEEE Transactions on Circuits and Systems II, vol. 53, no. 3, pp. 220-224, March 2006. [19] S. Tabatabaei, "Embedded Test Circuits and Methodologies for Mixed-Signal ICs," Ph.D. thesis, Dept. of Electrical and Computer Engineering, University of British Columbia, Vancouver, B C , Canada, 2000. [20]'S. Sunter and A. Roy, "On-chip digital jitter measurement, from megahertz to gigahertz," IEEE Design & Test of Computers, July-August 2004, pp. 314-321. [21] H . Dang, M . Sawan, Y . Savaria, " A novel approach for implementing ultra-high speed flash A D C using M C M L circuits," IEEE International Symposium on Circuits and Systems, vol. 6, pp. 6158-6161, May 2005. 109 |[22] D . M . Santos, " A C M O S delay locked loop and sub-nanosecond time-to-digital converter chip," IEEE Transactions on Nuclear Science, vo l . 43, pp. 1717-1719, June 1996. [23] V . Gutnik, "Analysis and characterization of random skew and jitter in a novel clock network" Ph .D. thesis, M I T , Cambridge, M A , U S A , pp. 83-92, June 2000. [24] P. Levine, "High-Resolution Time Measurement and Calibration for On-Chip Test Systems," M . A . S c . thesis, Dept. o f Electrical and Computer Engineering, M c G i l l University, Montreal, Q C , Canada, 2004, ch 4. [25] V . Gutnik and A . Chandrakasan, "Mult ip le Arbiter Jitter Estimation System and Related Techniques," U S Patent no. 6,661,860, Patent and Trademark Office, Washington D C , 2003. [26] P. M . Levine and G . W . Roberts, " A high-resolution flash time-to-digital converter and calibration scheme," ITCInternational Test Conference, 2004, pp. 1148-1157. [27] L . Kleeman, "The jitter model for metastability and its application to redundant synchronizers," IEEE Transactions on Computers, vo l . 39, no. 7, pp. 930-942, July 1990. [28] W . A . M . V a n Noije, W . T. L i u , and S. J. Navarro, "Precise final state determination in mismatched C M O S latches," IEEE Journal of Solid State Circuits, vo l . 30, no. 5, pp. 607-611, M a y 1995. [29] W . L ian and X . S. Cheng, "Analyt ical model o f noise of a switched fl ip-flop," Electronics Letters, vo l . 24, no. 21, pp. 1317-1318, October 1988. [30] Erf Wolfram MathWorld , 2007 [Online], Avai lable: http://mathworld.wolfram.com/Erf.html [31] Root-Mean-Square, Wolfram MathWor ld , 2007 [Online], Avai lable: http://mathworld.wolfram.com/Root-Mean-Square.html [32] A . Hajimiri , T. H . Lee, The Design of Low Noise Oscillators, K luwer Academic Publishers, 1999, ch. 2, 3, 5. [33] J. A . M c N E I L L , "Jitter In Ring Oscillators," Ph .D. thesis, College o f Engineering, Boston University, Boston, M A , U S A , 1994. [34] B . Nelson and M . Soma, "On-chip calibration technique for delay line based B I S T jitter measurement," Proceedings of the 2004 International Symposium on Circuits and Systems, pp. 1-944 -1-947, M a y 2004. [35] C . M . Grinstead and J. L . Snell, Introduction to Probability, American Mathematical Society, 1997. 110 [36] Independent Statistics, Wolfram Math Wor ld , 2007 [Online], Avai lable: http://mathworld.wolfram.com/IndependentStatistics.html [37] G . Evans, J. Goes, A . Steiger-Garcao, M . D . Ortigueira, N . Paulino and J. Sousa Lopes, "Low-Vol tage Low-Power C M O S Analogue Circuits for Gaussian and Uniform Noise Generation," Proceedings of the 2003 International Symposium on Circuits and Systems, Volume 1, pp. 1-145 -1-148, M a y 2003. [38] P. Dudek, S. Szczepanski and J. Hatfield, " A high-resolution C M O S time-to-digital converter util izing a Vernier delay line," IEEE Journal of Solid-State Circuits, vo l . 35, no. 2, pp. 240-247, February 2000. •[39] Normal Distribution, Wolfram MathWorld , 2007 [Online], Avai lable: http://mathworld.wolfram.com/NormalDistribution.html 111 Appendix A Circuit Implementation of Proposed Calibration Technique and 16-bit SOTDC This appendix contains the schematics of a conventional 16-bit SOTDC circuit, in addition to those of the proposed calibration technique. 112 vdd _ 1*4 4444 "5 > 5 2 ^ « J u ^ ^ J O O O O O O O O O O O O O O O O O O O O O O O O >4< 'o |o [o JS jo [S o jo jo |o js 5 5 o 5 5 p 5 p 5 p S p ° 8 s f " I vss I vdd j gure A . l : Top-level schematic of the proposed S O T D C calibration circuit (1-bit of 16-bit S O T D C illustrated). 113 i | r i = 5 u A KB' ;t?^ iL_^ "nch" > Figure A . 2 : Schematic of the Reference Arbiter Sampling circuit ("refarbitersampled"). 114 Figure A .3: Schematic of the Arbiter Array Counter Trigger circuit ("ref_arbitef_countef_trig"). 115 v s s v d d O o v s s J v d d oj x i o 1 1 1 Z A A A > Figure A .4 : Schematic of the Arbiter Sampling circuit ("arbitersampled"). 116 time ( s ) Figure A.5: T h e output of a positively biased arbiter when two free-running oscillators of different frequency, oscA and oscB, are applied to its inputs (TA = 1 ns, T& = 20 ps). 117 2.0 . : /OUTl 1.0 0.8 2.0 1.5 1.0 500 m| 0.0 - ; / 0 U T 2 60.(Sr. 70.0n „,'88:0h •im« ( a ) 90.3n Vi-Zn 1>0n Figure A.6: The sampled output of a positively biased arbiter when two free-running oscillators of different frequency, oscA and oscB, are applied to its inputs (TA = 1 ns, = 20 ps, sampling delay = 50 ps). 118 " A Figure A .7 : Schematic of the Arbiter Counter Control circuit ("arbitercountercontrol"). 119 CM O vdd I CM J o > I! s 1 - 1 C N o L 1 I vss A"" CN CN CN (7) CN - CO CO " II II l a vdd C M : Q _ Q . o I—• o o •—I i II S vss Figure A .8 : Schematic of the Arbiter circuit ("arbitertO")-120 • 1 I * A, M i ' f 1 l' ° I ° i °i i j • 3 3 s 1 , 1 s " s" I s" Figure A.9 : Schematic of the 24-bit Counter circuit ("24b_counter"). 121 to 0 0 s > t/3 O 65 HQ n o o I f enable_in }3 shift_contro! QP Qprev wxor2_2 4 op ^enoble^out wand2_2 C L K _ • -Rb enab!e_in Qprev _ • -shift_control CLK Rb enable_in Oprev shift_control enoble^out ^ enable_out 16-to-1 Output Mux 16 24-bit counters 1 Arbiter Counter Trigger circuit + 16 Arbiter Control circuits 1 Ref Arbiter Sampling circuit + 16 Arbiter Sampling circuits 1 Reference Arbiter + 16 SOTDC Arbiters Figure A . l l : Layout view of a 16-bit S O T D C and proposed calibration circuit in 0.35 um C M O S (L = 1930 um, W = 690 um). 123
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An embedded calibration technique for high-resolution flash time-to-digital converters Cicalo, James 2007
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Title | An embedded calibration technique for high-resolution flash time-to-digital converters |
Creator |
Cicalo, James |
Publisher | University of British Columbia |
Date Issued | 2007 |
Description | As CMOS technology continues to advance, device dimensions will continue to decrease, thus enabling the creation of circuits which operate at increasingly greater frequencies. However, this Increase In operating frequency has resulted in a reduced tolerance for circuit timing uncertainties. Therefore, techniques capable of measuring the timing characteristics of multi-GHz signals are needed to help address the growing number of timing problems found in modem CMOS circuits. For cost and accuracy reasons, embedded time interval measurement techniques which offer picosecond measurement accuracies and millisecond test-times are required to overcome these challenges. The "sampling offset" based flash time-to-digital converter (SOTDC) is an embedded time interval measurement technique that has recently garnered much attention due to its attractive properties. These properties include sub-millisecond test times of multi-GHz signals, in addition to the potential for measurement accuracies in the order of picoseconds. However, the accuracy of an SOTDC is strongly dependent upon the capabilities of its calibration technique, and present SOTDC calibration techniques suffer from some very serious limitations. In fact, these limitations are so severe that present calibration techniques are impractical under realistic production test conditions. This thesis presents the design and analysis of a novel embedded SOTDC calibration technique. The proposed calibration technique offers the potential for both sub-picosecond calibration accuracies and sub-100 millisecond calibration times. However, the main contribution of this work concerns the suitability of the proposed technique with a realistic production test environment. The capabilities of the proposed calibration technique have been proven using both mathematical analysis and behavioural modelling simulations. |
Genre |
Thesis/Dissertation |
Type |
Text |
Language | eng |
Date Available | 2011-02-23 |
Provider | Vancouver : University of British Columbia Library |
Rights | For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use. |
DOI | 10.14288/1.0100865 |
URI | http://hdl.handle.net/2429/31637 |
Degree |
Master of Applied Science - MASc |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
Campus |
UBCV |
Scholarly Level | Graduate |
AggregatedSourceRepository | DSpace |
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