{"Affiliation":[{"label":"Affiliation","value":"Applied Science, Faculty of","attrs":{"lang":"en","ns":"http:\/\/vivoweb.org\/ontology\/core#departmentOrSchool","classmap":"vivo:EducationalProcess","property":"vivo:departmentOrSchool"},"iri":"http:\/\/vivoweb.org\/ontology\/core#departmentOrSchool","explain":"VIVO-ISF Ontology V1.6 Property; The department or school name within institution; Not intended to be an institution name."},{"label":"Affiliation","value":"Electrical and Computer Engineering, Department of","attrs":{"lang":"en","ns":"http:\/\/vivoweb.org\/ontology\/core#departmentOrSchool","classmap":"vivo:EducationalProcess","property":"vivo:departmentOrSchool"},"iri":"http:\/\/vivoweb.org\/ontology\/core#departmentOrSchool","explain":"VIVO-ISF Ontology V1.6 Property; The department or school name within institution; Not intended to be an institution name."}],"AggregatedSourceRepository":[{"label":"AggregatedSourceRepository","value":"DSpace","attrs":{"lang":"en","ns":"http:\/\/www.europeana.eu\/schemas\/edm\/dataProvider","classmap":"ore:Aggregation","property":"edm:dataProvider"},"iri":"http:\/\/www.europeana.eu\/schemas\/edm\/dataProvider","explain":"A Europeana Data Model Property; The name or identifier of the organization who contributes data indirectly to an aggregation service (e.g. Europeana)"}],"Campus":[{"label":"Campus","value":"UBCV","attrs":{"lang":"en","ns":"https:\/\/open.library.ubc.ca\/terms#degreeCampus","classmap":"oc:ThesisDescription","property":"oc:degreeCampus"},"iri":"https:\/\/open.library.ubc.ca\/terms#degreeCampus","explain":"UBC Open Collections Metadata Components; Local Field; Identifies the name of the campus from which the graduate completed their degree."}],"Creator":[{"label":"Creator","value":"Cicalo, James","attrs":{"lang":"en","ns":"http:\/\/purl.org\/dc\/terms\/creator","classmap":"dpla:SourceResource","property":"dcterms:creator"},"iri":"http:\/\/purl.org\/dc\/terms\/creator","explain":"A Dublin Core Terms Property; An entity primarily responsible for making the resource.; Examples of a Contributor include a person, an organization, or a service."}],"DateAvailable":[{"label":"DateAvailable","value":"2011-02-23T00:35:58Z","attrs":{"lang":"en","ns":"http:\/\/purl.org\/dc\/terms\/issued","classmap":"edm:WebResource","property":"dcterms:issued"},"iri":"http:\/\/purl.org\/dc\/terms\/issued","explain":"A Dublin Core Terms Property; Date of formal issuance (e.g., publication) of the resource."}],"DateIssued":[{"label":"DateIssued","value":"2007","attrs":{"lang":"en","ns":"http:\/\/purl.org\/dc\/terms\/issued","classmap":"oc:SourceResource","property":"dcterms:issued"},"iri":"http:\/\/purl.org\/dc\/terms\/issued","explain":"A Dublin Core Terms Property; Date of formal issuance (e.g., publication) of the resource."}],"Degree":[{"label":"Degree","value":"Master of Applied Science - MASc","attrs":{"lang":"en","ns":"http:\/\/vivoweb.org\/ontology\/core#relatedDegree","classmap":"vivo:ThesisDegree","property":"vivo:relatedDegree"},"iri":"http:\/\/vivoweb.org\/ontology\/core#relatedDegree","explain":"VIVO-ISF Ontology V1.6 Property; The thesis degree; Extended Property specified by UBC, as per https:\/\/wiki.duraspace.org\/display\/VIVO\/Ontology+Editor%27s+Guide"}],"DegreeGrantor":[{"label":"DegreeGrantor","value":"University of British Columbia","attrs":{"lang":"en","ns":"https:\/\/open.library.ubc.ca\/terms#degreeGrantor","classmap":"oc:ThesisDescription","property":"oc:degreeGrantor"},"iri":"https:\/\/open.library.ubc.ca\/terms#degreeGrantor","explain":"UBC Open Collections Metadata Components; Local Field; Indicates the institution where thesis was granted."}],"Description":[{"label":"Description","value":"As CMOS technology continues to advance, device dimensions will continue to decrease, thus enabling the creation of circuits which operate at increasingly greater frequencies. However, this Increase In operating frequency has resulted in a reduced tolerance for circuit timing uncertainties. Therefore, techniques capable of measuring the timing characteristics of multi-GHz signals are needed to help address the growing number of timing problems found in modem CMOS circuits. For cost and accuracy reasons, embedded time interval measurement techniques which offer picosecond measurement accuracies and millisecond test-times are required to overcome these challenges. The \"sampling offset\" based flash time-to-digital converter (SOTDC) is an embedded time interval measurement technique that has recently garnered much attention due to its attractive properties. These properties include sub-millisecond test times of multi-GHz signals, in addition to the potential for measurement accuracies in the order of picoseconds. However, the accuracy of an SOTDC is strongly dependent upon the capabilities of its calibration technique, and present SOTDC calibration techniques suffer from some very serious limitations. In fact, these limitations are so severe that present calibration techniques are impractical under realistic production test conditions. This thesis presents the design and analysis of a novel embedded SOTDC calibration technique. The proposed calibration technique offers the potential for both sub-picosecond calibration accuracies and sub-100 millisecond calibration times. However, the main contribution of this work concerns the suitability of the proposed technique with a realistic production test environment. The capabilities of the proposed calibration technique have been proven using both mathematical analysis and behavioural modelling simulations.","attrs":{"lang":"en","ns":"http:\/\/purl.org\/dc\/terms\/description","classmap":"dpla:SourceResource","property":"dcterms:description"},"iri":"http:\/\/purl.org\/dc\/terms\/description","explain":"A Dublin Core Terms Property; An account of the resource.; Description may include but is not limited to: an abstract, a table of contents, a graphical representation, or a free-text account of the resource."}],"DigitalResourceOriginalRecord":[{"label":"DigitalResourceOriginalRecord","value":"https:\/\/circle.library.ubc.ca\/rest\/handle\/2429\/31637?expand=metadata","attrs":{"lang":"en","ns":"http:\/\/www.europeana.eu\/schemas\/edm\/aggregatedCHO","classmap":"ore:Aggregation","property":"edm:aggregatedCHO"},"iri":"http:\/\/www.europeana.eu\/schemas\/edm\/aggregatedCHO","explain":"A Europeana Data Model Property; The identifier of the source object, e.g. the Mona Lisa itself. This could be a full linked open date URI or an internal identifier"}],"FullText":[{"label":"FullText","value":"AN EMBEDDED CALIBRATION TECHNIQUE FOR HIGH-RESOLUTION FLASH TIME-TO-DIGITAL CONVERTERS by JAMES C I C A L O B A . S c , University of British Columbia, 2002 A THESIS SUBMITTED IN P A R T I A L F U L F I L L M E N T OF THE REQUIREMENTS FOR THE D E G R E E OF M A S T E R OF APPLIED SCIENCE in THE F A C U L T Y OF G R A D U A T E STUDIES (Electrical and Computer Engineering) THE UNIVERSITY OF BRITISH C O L U M B I A August 2007 \u00a9 James Cicalo, 2007 Abstract As CMOS technology continues to advance, device dimensions will continue to decrease, thus enabling the creation of circuits which operate at increasingly greater frequencies. However, this increase in operating frequency has resulted, in a reduced tolerance for circuit timing uncertainties. Therefore, techniques capable of measuring the timing characteristics of multi-GHz signals are needed to help address the growing number of timing problems found in modem CMOS circuits. For cost and accuracy reasons, embedded time interval measurement techniques which offer picosecond measurement accuracies and millisecond test-times are required to overcome these challenges. The( \"sampling offset\" based flash time-to-digital converter (SOTDC) is an embedded time interval measurement technique that has recently garnered much attention due to its attractive properties. These properties include sub-millisecond test times of multi-GHz signals, in addition to the potential for measurement accuracies in the order of picoseconds. However, the accuracy of an SOTDC is strongly dependent upon the capabilities of its calibration technique, and present SOTDC calibration techniques suffer from some very serious limitations. In fact, these limitations are so severe that present calibration techniques are impractical under realistic production test conditions. ii This thesis presents the design and analysis of a novel embedded SOTDC calibration technique. The proposed calibration technique offers the potential for both sub-picosecond calibration accuracies and sub-100 millisecond calibration times. However, the main contribution of this work concerns the suitability of the proposed technique with a realistic production test environment. The capabilities of the proposed calibration technique have been proven using both mathematical analysis and behavioural modelling simulations. in Table of Contents Abstract i i Table of Contents \u2022 'iy List of Figures vii List of Tables.... \u2022 vi Acknowledgements \u2022 x Chapter 1 Introduction 1 1.1 Time Interval Measurement 2 1.2 Thesis Organization 6 Chapter 2 Flash-Based Embedded Time Interval Measurement Techniques 7 2.1 Single Delay Line-Based Flash T D C 9 2.2 Vernier Delay Line-Based Flash T D C 12 2.3 Sampling Offset-Based Flash T D C 14 Chapter 3 Embedded Calibration of a Sampling Offset-Based Flash T D C 20 3.1 Behaviour of a Non-Ideal Arbiter 21 3.1.1 A Model of Thermal Noise in an Arbiter 21 3.1.2 Non-Ideal Arbiters and T i me Interval Measurement 24 3.2 Direct Calibration Technique 25 3.2.1 Analysis 28 3.2.2 , Conclusions 38 3.3 Relative Offset Calibration Technique 39 3.4 Added Noise Calibration Technique 42 3.4.1 Analysis 46 3.4.2 Conclusions 48 Chapter 4 Proposed SOTDC Calibration Technique 50 4.1 Simplified Proposed Calibration Technique 50 4.2 Non-Ideal Arbiters and Added Noise 62 4.3 Oscillator Non-Idealities 69 4.4 Implementation 71 4.5 Summary \u201e .' 74 iv Chapter 5 Results and Analysis 76 5.1 Theoretical Error Bounds 77 5.2 Realistic Error Bounds 84 Chapter 6 Conclusions and Future Work 102 6.1 Summary and Contributions 102 6.2 Future Work : 104 6.2.1 The impact of non-idealities 104 6.2.2 Circuit implementation 105 6.2.3 Additional applications and SOTDC improvements 106 References 108 Appendix A Circuit Implementation of Proposed Calibration Technique and 16-bit SOTDC 112 v List of Tables Table 3.1: Optimal ratio of tA to a, given the number of repetitions performed 37 Table 3.2: Reported results from Matlab simulation of the added noise-based calibration technique (tA = 40 ps, O, = 250 ps, N = 100 000) [26] 46 Table 5.1: Properties of the oscillator cycle count histograms illustrated in Figure 5.5 89 Table 5.2: Four P L L divisors (A and B) and their corresponding Tj values (fi\u201e- 50 kU) 98 Table 5.3: Time required to calibrate an SOTDC, assuming the P L L divisors of Table 5.2 (f,\u201e = 50 kl-I) [s] 99 vi List of Figures Figure 1.1: Timing jitter in a signal under test (SUT) 2 Figure 1.2: Three classifications of jitter. 3 Figure 1.3: P D F of random period jitter (a), and a combination of random and deterministic period jitter (b) 4 Figure 1.4: The growth of a random period jitter histogram as the number of measurement is increased 4 Figure 2.1: The role of a T D C 8 Figure 2.2: Single delay line-based flash T D C 10 Figure 2.3: Single delay line-based flash T D C timing waveform 11 Figure 2.4: A Vernier delay line-based flash T D C 12 Figure 2.5: Vernier delay line-based flash T D C timing waveform 13 Figure 2.6: Sampling offset-based flash T D C . 15 Figure 2.7: Symmetric C M O S arbiter 16 Figure 2.8: Behaviour of a perfectly symmetric arbiter 17 Figure 2.9: Behaviour of a positively biased arbiter 18 Figure 3.1: Voltage domain model of thermal noise in a biased arbiter 21 Figure 3.2: Time domain model of thermal noise in a biased arbiter 22 Figure 3.3: P D F of the sampling offset of a biased arbiter taking into account thermal noise ' 23 Figure 3.4: Gaussian C D F 23 Figure 3.5: Calculation of tso from the C D F of the sampling offset of a non-ideal arbiter 24 Figure 3.6: Sensitivity of the output of an arbiter to a, 25 Figure 3.7: Direct SOTDC calibration technique 26 Figure 3.8: Response of an arbiter to a sequence of increasing time intervals 26 Figure 3.9: Response of an arbiter to several repetitions of a sequence of increasing T& 27 Figure 3.10: Histogram and C D F of the output of an arbiter 28 Figure 3.11: Histogram of the output of an arbiter when tA < a, , 29 vi i Figure 3.12: Histogram of the output of an arbiter when tA > at 29 Figure 3.13: R M S tce\/a, vs. tjo, using the direct calibration technique 31 Figure 3.14: Histogram and C D F of the output of a noise-free arbiter 32 Figure 3.15: -tso versus tce for a noise-free arbiter using direct calibration 33 Figure 3.16: tce probability density function 34 Figure 3.17: R M S tce\/o, vs. tJot using the direct calibration technique 35 Figure 3.18: Log-log plot of R M S tcJat vs. tjoi using the direct calibration technique. 36 Figure 3.19: Log-log plot of R M S tce vs. at when tA = 10 ps, using the direct calibration technique 37 Figure 3.20: Gaussian distribution of arbiter sampling offsets due to process variation. 41 Figure 3.21: Log-log plot of R M S tce vs. ot when N = 100 000, using the direct calibration technique .-. 43 Figure 3.22: Time domain model of added and thermal noise in a biased arbiter 44 Figure 3.23: Arbiter sampling offset PDF with thermal and added noise 44 Figure 3.24: Addition of Gaussian temporal noise to a sequence of time intervals in order to create an arbiter sampling offset C D F 45 Figure 3.25: Added noise calibration technique implementation [26] 46 Figure 3.26: Log-log plot of R M S tce vs. a, when tA = 40 ps and N = 100 000, using the model of the direct calibration technique described in section 3.2.1 47 Figure 4.1: Time intervals created by two free-running oscillators 51 Figure 4.2: Sequence of linearly increasing time intervals 52 Figure 4.3: Periodic time intervals created by two free-running oscillators 53 Figure 4.4: Periodic sequence of time intervals generated from the output of oscA and oscB assuming TAITA = 5 >. 54 Figure 4.5: Determining the relative sampling offsets of two arbiters 55 Figure 4.6: Variation in arbiter sampling offsets while still maintaining a constant cycle count 56 Figure 4.7: Behaviour of a negatively biased arbiter 57 Figure 4.8: Behaviour of a positively biased arbiter (a), and a positively biased arbiter with reversed inputs (b) 58 Figure 4.9: Oscillator cycle count when the inputs to Arbiter2 are reversed 60 Figure 4.10: Summary of the information obtained by counting the number of oscillator cycles elapsed between the switching-events of two arbiters 61 Figure 4.11: (a) P D F of several Ts belonging to a sequence of Ts (b) PDF of two Ts (Note: the sampling offsets of two arbiters, tso! and tso2, are plotted along the x-axis of both figures) 63 Figure 4.12: Probability of oscillator cycle counts when Arbiter 2 has both normal and reversed inputs 68 Figure 4.13: P L L implementation of oscA and oscB 70 Figure 4.14: Conceptual circuit view of the proposed calibration technique 72 Figure 5.1: Minimum error of the proposed calibration technique across four different TA values 79 Figure 5.2: Oscillator cycle counts PDFs for several different values of ototai, all of which are < <5op,imai (TA =10 ps) 80 Figure 5.3: Oscillator cycle counts PDFs for several different values of otolai, all of which are > o'optimal {TA = 10 ps) 82 vm Figure 5.4: Flowchart describing the method of operation of the proposed SOTDC calibration technique Matlab model 87 Figure 5.5: Three oscillator cycle count histograms, generated using a different number of measurement repetitions 89 Figure 5.6: Comparison of the theoretical and realistic R M S error of the proposed calibration technique when TA = 10 ps 91 Figure 5.7: The R M S error of the proposed calibration technique when 7\/^=10 ps, plotted for three different number of measurement repetitions (N) 93 Figure 5.8: Comparison of the theoretical and realistic R M S error of the proposed calibration technique when TA = 100 ps..: ....95 Figure 5.9: Comparison of the theoretical and realistic R M S error of the proposed calibration technique when TA = 1 ns 96 Figure 5.10: Comparison of the theoretical and realistic R M S error of the proposed calibration technique when TA = 1 ps 96 Figure 5.11: The effect of varying TA on the calibration time (tcai) and the calibration error (tce) (calculated using an optimal value of atotai) 100 Figure A. 1: Top-level schematic of the proposed SOTDC calibration circuit (1-bit of 16-bit SOTDC illustrated) 113 Figure A.2: Schematic of the Reference Arbiter Sampling circuit (\"ref_arbiter_sampled\") 114 Figure A 3 : Schematic of the Arbiter Array Counter Trigger circuit (\"ref_arbiter_counter_trig\") 115 Figure A.4: Schematic of the Arbiter Sampling circuit (\"arbiter_sampled\") 116 Figure A. 5: The output of a positively biased arbiter when two free-running oscillators of different frequency, oscArand oscB, are applied to its inputs (TA = 1 ns, TA = 20 ps) 117 Figure A.6: The sampled output of a positively biased arbiter when two free-running oscillators of different frequency, oscA and oscB, are applied to its inputs (TA = I ns, TA = 20 ps, sampling delay = 50 ps) 118 Figure A . 7: Schematic of the Arbiter Counter Control circuit (\"arbiter_countercontrol\") 119 Figure A. 8: Schematic of the Arbiter circuit (\"arbiter_tO\") 120 Figure A. 9: Schematic of the 24-bit Counter circuit (\"24b_counter\") 121 Figure A. 10: Schematic of one stage of a 24-bit Counter (\"counter_cell\") 122 Figure A . l 1: Layout view of a 16-bit SOTDC and proposed calibration circuit in 0.35 um C M O S (L = 1930 um, W = 690 um).. 123 ix Acknowledgements I would like to convey my most sincere gratitude to those who have helped me to complete this work. Firstly, I would like to thank my research supervisor, Professor Andre Ivanov, for providing me with the opportunity to join his research group in addition to the U B C SoC laboratory. Professor Ivanov's continued guidance and support throughout this work was instrumental to its ultimate success. Secondly, I would like to thank my colleagues at the SoC laboratory, and in particular, Zaman Mollah, Andy Kuo, Michael Jones, and Dr. Roberto Rosales. I learned much from our countless discussions, and I will always be grateful for their advice and friendship. I would also like to thank the Canadian Microelectronics Corporation for granting me access to their IC fabrication services, in addition to Micronet, a Canadian Network of Centres of Excellence focused on the design of microelectronic systems, for financial support. Last, but certainly not least, I would like to thanks my parents, Ke'n and Teresa, my sister Carolyn, and my fiancee, Linda Zhang, for their immeasurable love and encouragement during the many challenges I encountered over the years. x Chapter 1 Introduction As CMOS technology continues to advance, device dimensions will continue to decrease, thus enabling the creation of circuits which operate at increasingly greater frequencies. However, this increase in operating frequency has resulted in a decreased tolerance for circuit timing uncertainties. In addition, the behaviour of a circuit, and therefore the timing of its signals, is becoming increasingly sensitive to environmental influences. These environmental influences may disturb the operation of a circuit through a number of mechanisms. These mechanisms include capacitive and inductive coupling, as well as the injection of noise into the power-supply or the substrate of a CMOS circuit [1,2] . As these mechanisms are becoming increasingly prevalent in modem CMOS circuits, critical path signals are increasingly susceptible to unwanted timing variations. Unintended timing variations in a signal may cause a circuit to become non-functional. Therefore, the ability to detect, diagnose, and i f possible, repair timing problems is of the utmost importance i f the reliability of a CMOS circuit is to be guaranteed. However, detecting timing problems in multi-GHz signals can be a very challenging task due to the extremely short time intervals that must be measured. For example, a 10% deviation in the 1 period of a 10 GHz signal translates to a mere 10 ps. Without the ability to detect timing problems in multi-GHz signals, it is not possible to diagnose or repair them. As a result, techniques capable of detecting and diagnosing timing problems in multi-GHz signals are needed to help address the growing number of timing issues found in modern CMOS circuits. 1.1 Time Interval Measurement The detection or diagnosis of a timing problem in a CMOS circuit is often accomplished with the help of a time interval (TI) measurement technique. TI measurement is a time domain analysis technique that is often used to deduce the timing characteristics of a signal by estimating its threshold crossings in the voltage domain [3], Many types of TI techniques exist, however they all share a common goal of quantifying the amount of uncertainty in the timing of a signal. Once this timing uncertainty has been quantified, predictions regarding the probability of a circuit's failure can be made. Timing uncertainty is usually referred to as \"timing jitter\" or \"absolute jitter\", which is defined as the deviation from the ideal timing of an event, and can be accumulated over many cycles [4, 5]. This definition is illustrated in Figure 1.1, where the amount of timing jitter in a signal under test (SUT) is indicated by the degree of uncertainty in the temporal location of a signal transition. Another useful definition that is illustrated in Figure 1.1 is that of the jitter budget or tolerance of a design, which is the maximum amount of timing jitter that can exist in a signal before the circuit fails to operate reliably. Two additional classifications of jitter exist, as Ideal Period SUT j Timing Jitter Figure 1.1: T i m i n g j i t te r in a signal under test (SUT). 2 illustrated in Figure 1.2. The first of these classifications is the most common of the three, and is known as \"period\" jitter. Period jitter is simply the deviation of a single period from its ideal value. The second classification is known as \"cycle-to-cycle\" jitter, and is a measure of the difference between adjacent cycles. Ideal Signal \/ \\ \/ \\ \/ \\ \/ j \u00ab \u2014 T i T 2 T 3 Actual Signal \/ \\ \/ \\ \/ \\ \/ A B C Period Jitter: Ti - T 0 T 2 - T 0 T 3 - T 0 Cycel-to-Cycle Jitter: T 2 - Ti T 3 - T 2 ( T i + T 2 ) ( T ^ T j + Ts) Timing Jitter: ^ - T 0 - 2 T 0 - 3T 0 Figure 1.2: Three classifications of jitter. Each of the aforementioned types of jitter may contain both random and deterministic components, depending upon the source of the jitter. In any case, it is possible to predict the probability with which a signal will exceed a circuit's timing margins by constructing the probability density function (PDF) of the period jitter [6]. The PDF of a purely random source of period jitter is illustrated in Figure 1.3 (a). Inspection of Figure 1.3 (a) reveals that random period jitter can be characterized by a Gaussian distribution. Since a Gaussian distribution is unbounded, its peak-to-peak value (the difference between the shortest and longest cycles) is also unbounded, and is highly dependent upon the number of cycles measured. The 'PDF of period jitter resulting from both random and deterministic sources is illustrated in Figure 1.3 (b). The shape of this PDF is determined by the convolution of the 3 random and deterministic components' PDFs [7]. A s deterministic jitter is bounded in nature, its peak-to-peak value is also bounded. CC . Q O \u2022 ^ \u00bbJ Jitter Budget \/ \/ ^ v 1 Tolerance 1 \\ ' \/ \"o\\ J 1 \\ 1 1 \\ i __, \u2022 \u00bbJ Jitter Budget \/ I Tolerance -15 -10 -5 0 5 10 Period Jitter [ps] (a) 15 -15 -10 -5 0 5 10 Period Jitter [ps] (b) Figure 1.3: P D F of random period jitter (a), and a combination of random and deterministic period jitter (b). A s the function o f a time interval measurement technique is to accurately estimate the duration o f a time interval, multiple measurements o f a signal's period can be performed and subsequently compiled into a histogram. If this histogram is normalized by the number o f measurements performed, a P D F o f the signal's period jitter can be produced. However, before an accurate P D F can be produced, many cycles need to be measured [8]. This idea is illustrated in Figure 1.4, where the random period jitter o f a signal is estimated using three different histograms. Each histogram is drawn using an increasing number o f measurement results. in m o >\u00bb O CD Jitter Budget \/ Tolerance -15 -10 -5 0 5 10 Period Jitter [ps] 15 # Cycles Measured n - N 3 \u2022 - N 2 NT < N 2 < N 3 Figure 1.4: T h e growth of a random period jitter histogram as the number of measurement is increased. 4 Inspection of Figure 1.4 reveals that both the standard deviation and the peak-to-peak jitter of the histogram may vary as the number of measurement cycles is increased. Although a few thousand measurements are often sufficient to provide an accurate estimate of standard deviation, hundreds of thousands, or even millions of measurements are often required in order to make an accurate prediction of the peak-to-peak jitter in a multi-GHz signal. Such information is frequently used as a metric when determining the probability of circuit failure [8]. While many different time interval measurement techniques exist [9], the choice of which technique to employ for a given application ultimately depends on the measurement requirements. For instance, the measurement of period jitter at giga-bits-per-second (Gbps) data rates necessitates very accurate results, as the jitter budget at these speeds is extremely small. For example, the authors in [20] predict that measurement accuracies of 1 ps or less will be required for bit-error-rate (BER) testing of 10 Gbps integrated circuit (IC) pins. As previously mentioned, obtaining accurate jitter results may require a large number of measurements. Therefore, as signal data rates increase along with jitter measurement requirements, the total measurement time of TI measurement techniques continues to rise. As a result, only a select group of low test-time measurement techniques are feasible in a volume production test environment, where test time is directly related to product cost [10]. Signal amplitude sampling-based techniques [11] can be used to reconstruct the shape of a voltage-time waveform based on a number of voltage-time samples. While these techniques are not strictly \"time interval\" based jitter measurement techniques, they have been successfully used to measure jitter with picosecond accuracy [12]. However, signal amplitude sampling-based techniques typically require tens of seconds per measurement, which is far too much time for a volume production test environment [13]. High-frequency production testers can be used to measure jitter with picosecond accuracy in a matter of seconds [i4, 15, 16]. However, these testers generally cost millions of dollars. In addition, probing gigaHertz signals for off-chip measurement can introduce significant additional jitter [20]. Therefore, for cost and accuracy reasons, embedded (on-chip) time interval 5 ( measurement techniques which offer picosecond measurement accuracies and millisecond test-times are very useful tools to enable the cost-effective analysis of a growing number of timing problems found in modem CMOS circuits [17]. In fact, embedded time interval measurement techniques are currently the subject of research within both academia and industry [18]. \u2022 One new time interval measurement technique which has recently garnered much attention is the \"sampling offset\" based flash time-to-digital converter (SOTDC) [23]. This time-to-digital converter (TDC) offers sub-millisecond test times for gigaHertz signals, as well as the potential for picosecond measurement accuracies. However, the accuracy of an SOTDC is strongly dependent on the capabilities of its calibration technique. To date, no feasible embedded calibration technique for an SOTDC has been proposed. This thesis is focused on the design of a novel embedded calibration technique for SOTDCs which offers the potential for sub-picosecond calibration accuracies, and calibration times in the order of milliseconds. While specific reference to the calibration of an SOTDC is made, this calibration technique is applicable to any flash-based TDC. 1.2 Thesis Organization This thesis consists of a total of six chapters. Important background information concerning the evolution of traditional flash-based TDCs into state-of-the-art SOTDCs is presented in Chapter 2. Three previously proposed SOTDC calibration techniques are described in Chapter 3, and the important limitations of each are investigated. Next, the embedded calibration technique proposed in this thesis is described in Chapter 4, followed by an analysis of its capabilities and limitations in Chapter 5. Finally, conclusions regarding the contribution of this thesis are presented in Chapter 6, along with a discussion of future work. 6 Chapter 2 Flash-Based Embedded Time Interval Measurement Techniques Embedded time interval measurement can be performed using a variety o f techniques, and is often realized using a time-to-digital converter (TDC) . A T D C is a circuit that outputs a digital codeword when a time interval is applied to its input, as shown in Figure 2.1. The time interval to be measured, referred to from hereon as Td, is defined as the difference in time between the rising edge transitions o f two signals, which are traditionally referred to as START and STOP. This digital codeword, once interpreted, approximates the duration o f the time interval. 7 START o-TDC 8 01101011 STOP START . . . _ n STOP n _ . . . H Figure 2 .1 : T h e role of a T D C . While many different types of TDCs exist, they can all be evaluated against the following criteria: \u2022 Accuracy: How closely the interpreted digital codeword matches Td. \u2022 Resolution: The smallest measurable difference in Td. \u2022 Precision: The degree to which a set of measurements of the same Td agree. \u2022 Measurement rate: The maximum rate at which different T& can be applied to the T D C s input while still receiving correct codewords at its output. \u2022 Dynamic range: The ratio of the maximum to minimum Td measurable by the TDC. \u2022 Power and A r e a requirements: The area required to implement an on-chip TDC with certain accuracy, resolution, precision, measurement rate, and dynamic range specifications, in addition to the power consumed by this TDC. 8 As the accuracy, resolution, precision, dynamic range, and measurement rate requirements placed upon TDCs become increasingly stringent, trade-offs are necessary in order to construct a feasible TDC architecture. Many TDC architectures target a reduced measurement rate in order to meet the accuracy, resolution, and precision requirements. Examples of such TDCs include the Vernier oscillator-based TDC [19], and the undersampling-based TDC described in [20], However, this trade-off can be very costly for integrated circuit (IC) manufacturers, since the resulting increase in production test time increases overall production costs. This chapter examines the evolution of \"flash\" TDC architectures. The chapter begins with a description of the most primitive form of a flash TDC, and concludes with a presentation of the state-of-the-art in flash TDC design, where picosecond measurement resolutions are achievable. In general, Flash TDCs are capable of very high measurement rates. In fact, flash TDCs are capable of operating at or near the frequency of the signal or signals under test, from which the START and STOP signals are derived. Flash TDCs are analogous to flash analog-to-digital converters (ADCs), since their output codeword is determined in a single step by a bank of comparators [21]. Therefore, the flash TDC architecture is a very good candidate for embedded time interval measurement in both a i production test environment or in a customer application, where measurement time is of comparable importance to measurement accuracy, resolution, and precision. 2.1 Single Delay Line-Based Flash TDC The most basic form of a flash TDC is the single delay line-based flash TDC, which is illustrated in Figure 2.2. This TDC architecture has two primary inputs, namely START and STOP, and a multitude of outputs, labelled Cj to CN in this embodiment. 9 START STOP IN1 OUT1 ARBITER 1 IN2 OUT2 V IN1 OUT1 ARBITER 2 IN2 OUT2 IN1 OUT1 ARBITER N IN2 OUT2 c 2 -c=> c N Figure 2.2: Single delay line-based flash T D C . If we define the instant at which the START signal transitions from a low to a high logic level as tstart, and i f we define tstop analogously for the STOP signal, then we can describe Td in mathematical terms with the following equation: Pd tstop ~ t stop 1 start (2.1) As shown in Figure 2.2, the START signal is delayed by a single buffer as it propagates from one arbiter to the next. The delay of each buffer is equal to T. At each stage, an arbiter determines which of its two inputs was the first to transition from a low to a high logic level, i.e., the first to make a \"positive\" transition. If INI is the first to perform such a transition then OUT1 is set to a high logic level and OUT2 to a low logic level, and vice versa i f IN2 is the first to arrive. Figure 2.3 illustrates the operation of a single delay line-based flash TDC 10 consisting of 4 arbiters. This type of TDC can be referred to as a 4-bit single delay line-based flash TDC. Arbiter 1 { IN1 IN2 C 2 { IN1 : I IN2 [ C 3 { IN1 \u20141 IN2 I C 4 Figure 2.3: Single delay line-based flash T D C timing waveform. As is shown in Figure 2.3, a single delay line-based flash TDC produces a thermometer code digital output (C4C3C2C1 = 1000). Td can be approximated by noting the location of the \"0\" to \"1\" transition in the output codeword. In the above example, Tj is shown to satisfy the following condition: 2r