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UBC Theses and Dissertations

Synchronization, phase detection, lock detection, and SNR estimation in coherent M-PSK receivers Linn, Yair

Abstract

This thesis presents and investigates new structures for use within coherent M-PSK (M-ary Phase Shift Keying) receivers. The thesis is divided into three main parts. The first part of the thesis presents and investigates a new family of carrier lock detectors. These detectors are self-normalizing, i.e., they are independent of the AGC (Automatic Gain Control) circuit parameters. In the second part of the thesis, two new families of carrier phase detectors are presented and analyzed. The first family of phase detectors is self-normalizing (i.e., the phase detectors are independent from the AGC). The second family of phase detectors is based on an adaptive structure that achieves not only independence vis-à-vis the AGC, but rather also independence from the SNR (Signal-to-Noise Ratio), hence potentially allowing the carrier synchronization circuit to operate optimally at all SNRs. In the third part of the thesis, two new families of SNR estimators are presented. The first family of SNR estimators requires that the carrier synchronization PLL (Phase Lock Loop) be locked in order to function. The second family of SNR estimators is more complicated but has the advantage of dispensing with the carrier synchronization requirement; thus, this second family of SNR estimators is also suitable for SNR estimation in D-MPSK (Differential M-ary Phase Shift Keying) receivers. The aforementioned lock detection, phase detection, and SNR estimation structures are compared to previously available structures and it is shown that they have significant implementational and performance advantages. Three important unifying aspects of the proposed structures are: (1) They are Non Data Aided (NDA); (2) they all have compact fixed-point implementations suitable for use within an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array); and (3) they are all to a great extent independent from the AGC circuit. These key advantages make the proposed structures particularly attractive for use in FPGA-based or ASIC-based receivers.

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