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A low-swing, wide-tuning-range CMOS phase-locked loop

University of British Columbia

Increasing demand for affordable high performance communication devices, in particular in mobile systems, is the driving force behind the development of high-speed, low cost, and low power circuits in CMOS technology. This is mainly due to the fact that CMOS process facilitates the integration of analog and digital circuits on the same chip. A major technique to reduce the power consumption in a CMOS chip is the use of low-swing signaling. Integrated phase-locked loops (PLLs) are versatile components used in many communication and control applications. In this thesis, the design of a low-swing, wide tuning range charge-pump PLL is presented. PLLs are the integral part of many communication and computing applications. The PLL is designed and simulated in a 0.18μm standard CMOS technology. Its frequency range of operation is from 1.14GHz to 2.25GHz. Almost all of the PLL internal signals are fully differential and low swing (IV peak-to-peak differential swing). To further reduce the power consumption of the PLL, the charge pump current of 15μA is used. The PLL operates from a single 1.8V supply while consuming 14.5mW. It remains functional if the supply voltage changes by ±10%. Due to the low-swing nature of the internal PLL signals, the magnitude of the induced noise on the power supply is small, less than 0.8mV.

Text

2009-12-23

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http://hdl.handle.net/2429/17163

Electrical and Computer Engineering

University of British Columbia

UBCV

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