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Channel width reduction techniques for system-on-chip circuits in field-programmable gate arrays

University of British Columbia

Users of field-programmable gate arrays (FPGAs) typically measure the size of a FPGA by its logic capacity. If a design fits within the logic capacity limits of an FPGA, it is generally assumed that it must also be routable. To ensure this high routability, FPGA vendors typically over-design the routing network. Despite this over-design, there may still be circuits that remain un-routable in a given FPGA family. This thesis presents two new computer-aided design (CAD) tools, DHPack and Un/DoPack, that are able to route these un-routable circuits by trading off logic utilization for interconnect. DHPack uses the natural design hierarchy of the circuit to identify high congestion regions. For a set of benchmark circuits used in this thesis, DHPack is able to reduce channel width by 13% with a small area increase of 3%. DHPack can continue to decrease channel width by 29% with a larger area increase of 146%. Un/DoPack improves on DHPack by targeting hard channel width constraints without having to rely on the design hierarchy of the circuit to perform congestion estimation. For a set of benchmark circuits presented in this thesis, Un/DoPack can reduce channel width by 38% with an 18% penalty in critical path delay and 64% increase in area. The primary application of these tools is to make previously unroutable circuits routable by using an FPGA with more logic.

Text

2010-01-08

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http://hdl.handle.net/2429/17807

Electrical and Computer Engineering

University of British Columbia

UBCV

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