UBC Theses and Dissertations

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UBC Theses and Dissertations

System-on-a-chip (SoC) design and test : a case study Hong, Louis Tzu-Leng

Abstract

System-on-a-chip (SoC) and reuse of intellectual property (IP) is the emerging paradigm for integrated circuit designs. To understand the unique challenges in IP development and SoC integration, a microprocessor core and a network processor SoC were developed. The Reuse Methodology Manual (RMM) by Keatling and Bricaud was used as a guide during the development of the IP core and the SoC. This thesis presents several examples taken from the microprocessor and SoC designs that either support or counter the claims made in RMM. The problem of SoC testing is also a highly researched area. In an effort to validate the concept of an on-chip test network, a packet-switching test access mechanism (TAM) was designed and integrated into the network processor SoC. The TAM, known as NIMA, is an on-chip network that supports different types of embedded core testing. The NIMA architecture was compared with a serial TAM and a multiple-inputs TAM based on the Test Rail architecture. The three TAM designs were compared based on the total test time, area overhead, and complexity of the controlling mechanism. This thesis also discusses the trade-offs of the three TAM architectures and suggests some improvements for NIMA to reduce its area and delay overhead.

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