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Embedded test strategies for system-on-a-chip designs

University of British Columbia

System-on-a-chip (SoC) with reuse of intellectual property (IP) is gaining acceptance as the preferred style for integrated circuit (IC) designs. This paradigm shift poses great challenges to the overall design and test methodologies. To support SoC design and test, it is important to develop a corresponding set of Semiconductor Infrastructure IP (SI²P), which includes all components surrounding an IP core to facilitate system integration, timing synchronization, and test efforts. This thesis focuses on the SI²P needed for SoC test. First, a relationship is established between stuck-at (DC) and transition (AC) fault detection when applying a set of test vectors to a given design. To exploit this relationship, a new test pattern generation flow is proposed to maximize the DC fault coverage level with test patterns targeted at AC faults. The resulting vector set is a combination of pseudo-random test patterns and deterministic "top-up" vectors. The fault coverage of this approach is competitive with that achievable by an automatic test pattern generation (ATPG) tool. A hardware implementation of on-chip test pattern generation as part of a logic built-in self-test (logic BIST) solution is described. A matrix-based algorithm for constructing deterministic pattern generator circuits based on linear feedback shift registers (LFSR's) is presented. It is found that the resulting area overhead of the deterministic pattern generator is significant relative to the IP core under test and is a function of deterministic test pattern count. Additional SI²P components required for this embedded testing approach are also described.

Thesis/Dissertation

application/pdf

2009-10-21

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http://hdl.handle.net/2429/14115

Electrical and Computer Engineering

University of British Columbia

UBCV

DSpace