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UBC Theses and Dissertations
SoC interconnect architecture design and evaluation under timing constraints Grecu, Cristian
Abstract
System on chip design steadily evolves toward different non-overlapping abstraction levels. Very different competence and design tools will be needed at each level. One specific level of abstraction will deal with interconnect technologies, with a pronounced trend towards networks on chip. It is projected that, within five years, the large majority of end-user SoC products will consist of heterogeneous embedded processors, built on multi-processor SoC platforms (MP-SoC). There is a tremendous amount of research required to characterize the various topologies and their effectiveness for different application domains. A common issue with all network-on-chip topologies is communication latency. Due to the increase of global wire delay with technology scaling, pipelining is required to hide the latency associated with the exchange of data across the chip. The building blocks of a network-on-chip are intelligent switches, which provide a data transport mechanism across the chip. Their design is critical due to different architectural and circuit level trade-offs. This work is novel in that it addresses the issues of quantifying the delay of different pipeline stages in an on-chip topology, and evaluates the effectiveness of a given topology in forthcoming technology nodes.
Item Metadata
Title |
SoC interconnect architecture design and evaluation under timing constraints
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Creator | |
Publisher |
University of British Columbia
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Date Issued |
2003
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Description |
System on chip design steadily evolves toward different non-overlapping
abstraction levels. Very different competence and design tools will be needed at each
level. One specific level of abstraction will deal with interconnect technologies, with a
pronounced trend towards networks on chip.
It is projected that, within five years, the large majority of end-user SoC products
will consist of heterogeneous embedded processors, built on multi-processor SoC
platforms (MP-SoC). There is a tremendous amount of research required to characterize
the various topologies and their effectiveness for different application domains.
A common issue with all network-on-chip topologies is communication latency.
Due to the increase of global wire delay with technology scaling, pipelining is required to
hide the latency associated with the exchange of data across the chip.
The building blocks of a network-on-chip are intelligent switches, which provide
a data transport mechanism across the chip. Their design is critical due to different
architectural and circuit level trade-offs.
This work is novel in that it addresses the issues of quantifying the delay of
different pipeline stages in an on-chip topology, and evaluates the effectiveness of a
given topology in forthcoming technology nodes.
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Extent |
4839379 bytes
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Genre | |
Type | |
File Format |
application/pdf
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Language |
eng
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Date Available |
2009-11-20
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Provider |
Vancouver : University of British Columbia Library
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Rights |
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.
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DOI |
10.14288/1.0065466
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URI | |
Degree | |
Program | |
Affiliation | |
Degree Grantor |
University of British Columbia
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Graduation Date |
2004-05
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Campus | |
Scholarly Level |
Graduate
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Aggregated Source Repository |
DSpace
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Item Media
Item Citations and Data
Rights
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.