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Non-rectangular embedded programmable logic cores Wong, Tony Yau-Wai
Abstract
As System-on-a-Chip (SoC) design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other intellectual property (IP) in the SoC design methodology, except that their function can be changed after fabrication. In many cases, nonrectangular programmable logic cores are required, either to better mesh with the other IP cores, or because of I/O constraints. However, most CAD algorithm and programmable logic architecture research targets standalone field programmable gate arrays (FPGA's), which are invariably square or rectangular. In this thesis, we enable researchers to evaluate nonrectangular programmable logic cores by a novel specification method and an enhanced CAD tool. We also show that existing placement and routing algorithms do not work well when targeting non-rectangular programmable logic cores, and we present enhancements to existing placement and routing algorithms that allow the algorithms to better target these cores. It is shown that the new algorithms lead to a 12% critical path improvement for "U"- shaped cores, and a 4% critical path improvement for "0"-shaped cores. The density and speed penalty for using these non-rectangular cores is significant, compared to square cores, however, we show that the penalty would be significantly larger if the original algorithms were used.
Item Metadata
Title |
Non-rectangular embedded programmable logic cores
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Creator | |
Publisher |
University of British Columbia
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Date Issued |
2002
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Description |
As System-on-a-Chip (SoC) design enters into mainstream usage, the ability
to make post-fabrication changes will become more and more attractive.
This ability can be realized using programmable logic cores. These cores are
like any other intellectual property (IP) in the SoC design methodology, except
that their function can be changed after fabrication. In many cases, nonrectangular
programmable logic cores are required, either to better mesh
with the other IP cores, or because of I/O constraints. However, most
CAD algorithm and programmable logic architecture research targets standalone
field programmable gate arrays (FPGA's), which are invariably square
or rectangular. In this thesis, we enable researchers to evaluate nonrectangular
programmable logic cores by a novel specification method and
an enhanced CAD tool. We also show that existing placement and routing
algorithms do not work well when targeting non-rectangular programmable
logic cores, and we present enhancements to existing placement and routing
algorithms that allow the algorithms to better target these cores. It is shown
that the new algorithms lead to a 12% critical path improvement for "U"-
shaped cores, and a 4% critical path improvement for "0"-shaped cores.
The density and speed penalty for using these non-rectangular cores is
significant, compared to square cores, however, we show that the penalty
would be significantly larger if the original algorithms were used.
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Extent |
3849508 bytes
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Genre | |
Type | |
File Format |
application/pdf
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Language |
eng
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Date Available |
2009-09-22
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Provider |
Vancouver : University of British Columbia Library
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Rights |
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.
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DOI |
10.14288/1.0065345
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URI | |
Degree | |
Program | |
Affiliation | |
Degree Grantor |
University of British Columbia
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Graduation Date |
2002-05
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Campus | |
Scholarly Level |
Graduate
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Aggregated Source Repository |
DSpace
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Item Media
Item Citations and Data
Rights
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.