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UBC Theses and Dissertations
Design and evaluation of a high performance multipriority multicast ATM and IP switch Chu, Joseph
Abstract
Asynchronous Transfer Mode (ATM) and Internal Protocol (IP) are two commonly used protocols for the demands of high speed networking technology. The switching technologies employed in ATM cell and IP packet switches have seen extensively researched and studied in recent years. However, most of the switches developed have room for improvement in performance and cost-efficiency. Furthermore, most switching research is based on uniform incoming cell/packet traffic, which is very different from real time traffic. Real time traffic is not only bursty, but also involves multiple classes of prioritized traffic, as well as multicast traffic. In this thesis, a high performance A TM and IP switch architecture is introduced. The switching architecture is based on two existing technologies namely Random Early Detection (RED), and the internal buffer. Simulation results show that with a little modification of these schemes, a switch can perform extremely well under many kinds of real time traffic patterns, including multi-priority and multicast. In addition, the proposed switching architecture shows that cell loss ratio can be arbitrarily reduced using a finite internal buffer size.
Item Metadata
Title |
Design and evaluation of a high performance multipriority multicast ATM and IP switch
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Creator | |
Publisher |
University of British Columbia
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Date Issued |
2002
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Description |
Asynchronous Transfer Mode (ATM) and Internal Protocol (IP) are two commonly
used protocols for the demands of high speed networking technology. The switching
technologies employed in ATM cell and IP packet switches have seen extensively
researched and studied in recent years. However, most of the switches developed
have room for improvement in performance and cost-efficiency. Furthermore, most
switching research is based on uniform incoming cell/packet traffic, which is very
different from real time traffic. Real time traffic is not only bursty, but also involves
multiple classes of prioritized traffic, as well as multicast traffic.
In this thesis, a high performance A TM and IP switch architecture is introduced.
The switching architecture is based on two existing technologies namely Random
Early Detection (RED), and the internal buffer. Simulation results show that with a
little modification of these schemes, a switch can perform extremely well under many
kinds of real time traffic patterns, including multi-priority and multicast. In addition,
the proposed switching architecture shows that cell loss ratio can be arbitrarily
reduced using a finite internal buffer size.
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Extent |
3517665 bytes
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Genre | |
Type | |
File Format |
application/pdf
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Language |
eng
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Date Available |
2009-08-20
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Provider |
Vancouver : University of British Columbia Library
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Rights |
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.
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DOI |
10.14288/1.0065338
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URI | |
Degree | |
Program | |
Affiliation | |
Degree Grantor |
University of British Columbia
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Graduation Date |
2002-11
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Campus | |
Scholarly Level |
Graduate
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Aggregated Source Repository |
DSpace
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Item Media
Item Citations and Data
Rights
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.