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UBC Theses and Dissertations

A distributed transputer-based architecture using a reconfigurable synchronous communication protocol Vachon, Marie Josette Brigitte


A reliable, reconfigurable, and expandable distributed architecture supporting both bus and point-to-point communication for robotic applications is proposed. The new architecture is based on Inmos T800 microprocessors interconnected through crossbar switches, where communication between nodes takes place via point-to-point bidirectional links. Software development is done on a host computer, Sun 3/280, and the executable code is downloaded to the distributed architecture via the bus. Based on this architecture, an operating system has been designed to provide communication and input/output support. The message passing communication protocol uses circuit switching and a centralized reconnection control strategy. The communication protocol is composed of two modules: A Local Bus Interface (LBI) that runs on every processing element and a Central Switch Controller (CSC) which executes on a bus master and reconfigures the network topology as required by the user program. The LBI is small, simple, and deadlock free. User reconfiguration requests are interrupt driven, and the CSC can support real-time reconfiguration of the topology without interfering with other communications. An Input/Output Controller (IOC) process runs on the host computer and provides standard library support to each processor in the network. An important feature of the circuit switching communication protocol is that it preserves synchronous communication where processors do not need to store messages and no buffer management is required. Routing overhead occurs only when the circuit is set up, so subsequent messages may flow through the network with a guaranteed bandwidth and a maximum communication latency, which is an important consideration in real-time systems. The routing mechanism is adaptive where communication hot spots may be detected and bypassed. The centralized reconfiguration control strategy and the adaptive routing mechanism provides a basis for a reliable architecture. In the case of a link or processor failure, the routing mechanism is capable of bypassing a faulty component without affecting the application program, and can also redirect messages to a backup processor. Knowledge of the faulty component is required at the CSC only, in contrast to most routing algorithms where either the local or global state of the network is essential at every node. The performance of this communication protocol is compared with Helminen's store-and-forward model [1] running on the FPS T-series hypercube. The results show that the centralized circuit switching protocol provides better performance when a message crosses multiple hops, large message length, and when the algorithm contains temporal locality properties. Dynamic protocols, however, are less desirable for short messages due to the initial connection latency.

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