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NoCsim : a versatile network on chip simulator

University of British Columbia

The new network on chip paradigm that has been proposed involves radical changes to SoC design methodology. In this paradigm large numbers of heterogeneous IP blocks will by integrated together using a standard template. Each IP block is capable of sending and receiving data packets through an interconnect. The non-scalability of buses as on-chip interconnects forces us to select a more scalable alternative for communication. Many different network-centric interconnects have been proposed for the large scale SoC domain such as k-ary n-cubes, butterfly fat-trees, k-ary n-trees, and octagons. With this network-on-chip (NoC) paradigm many new design challenges arise such as physical switch design, and network topology selection. Without any other means of predicting system performance, a network simulation tool is required to evaluate and compare networks. Several network simulation tools exist, but fail to contain all functionality desired for NoC simulation (e.g. wormhole switching support). To fill this void we have developed NoCSim, an iterative flit-level network on-chip simulator capable of simulating networks under a wide variety of parameters and topologies. The tool was developed, tested, and verified against an established network simulator.

Text

2009-12-11

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http://hdl.handle.net/2429/16550

Electrical and Computer Engineering

University of British Columbia

UBCV

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