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Syncopation : an adaptive clock management technique for high-level synthesis generated circuits on FPGA

University of British Columbia

High-Level Synthesis (HLS) tools improve hardware designer productivity by enabling software design techniques to be used during hardware development. While HLS tools are effective at abstracting the complexity of hardware design away from the designer, producing high-performance HLS-generated circuits still generally requires awareness of hardware design principles. Designers must often understand and employ pragma statements at the software level or have the capability to make adjustments to the design in Register-Transfer Level (RTL) code. Even with designer hardware expertise, the HLS-generated circuits can be limited by the algorithms themselves. For example, during the HLS flow the delay of paths can only be estimated, meaning the resulting circuit may suffer from unbalanced computational distribution across clock cycles. Since the maximum operating frequency of synchronous circuits is determined statically using the worst-case timing path, this may lead to circuits with reduced performance compared to circuits designed at a lower level of abstraction. In this thesis, we address this limitation using Syncopation, a performance-boosting fine-grained timing analysis and adaptive clock management technique for HLS-generated circuits. Syncopation instrumentation is implemented entirely in soft logic without requiring alterations to the HLS-synthesis toolchain or changes to the FPGA, and has been validated on real hardware. The key idea is to use the HLS scheduling information along with the placement and routing results to determine the worst-case timing path for individual clock cycles. By adjusting the clock period on a cycle-by-cycle basis, we can increase performance of an HLS-generated circuit. Our experiments show that Syncopation improves performance by 3.2% (geomean) across all benchmarks (up to 47%). In addition, by employing targeted synthesis techniques called Enhanced Synthesis along with Syncopation we can achieve 10.3% performance improvement (geomean) across all benchmarks (up to 50%).

Text

2020-10-28

Attribution-NonCommercial-NoDerivatives 4.0 International

http://hdl.handle.net/2429/76384

Electrical and Computer Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by-nc-nd/4.0/