UBC Theses and Dissertations
A stochastic RTL circuit generator for FPGA architecture and CAD evaluation Mashayekhi, Motahareh
The performance and capacity of Field-Programmable Gate Arrays (FPGAs) have dramatically improved in recent years. Today these devices are emerging as massively reconfigurable and paralleled hardware computation engines in data centers and cloud computing infrastructures. These emerging application domains require better and faster FPGAs. Designing such FPGAs requires realistic benchmark circuits to evaluate new architectural proposals. However, the number of available benchmark circuits is small, outdated, and few of these are representative of realistic circuits. A potential method to obtain more benchmark circuits is to design a generator that is capable of generating as many circuits as desired that are realistic and have specific characteristics. Previous work has focused on generating benchmark circuits at the netlist level. This limits the usefulness of these circuits in evaluating FPGA Computer Aided Design (CAD) algorithms since it does not allow for the evaluation of synthesis or related mapping algorithms. In addition, these netlist level circuit generators were calibrated using specific synthesis tools, which may no longer be state of the art. In this thesis, we introduce an Register Transfer Level (RTL) level circuit generator that can automatically create benchmark circuits that can be used for FPGA architecture studies and for evaluating CAD tools. Our generator can operate in two modes: as a random circuit generator or as a clone circuit generator. The clone circuit generator works by first analyzing an input RTL circuit then it generates a new circuit based on the analysis results. The outcome of this phase is evaluated by measuring the distance between certain post-synthesis characteristics of the generated clone circuit and those of the original circuit. In this study we generated a clone circuit for each of the VTR set of Verilog benchmark circuits. We generate clones with post-synthesis characteristics that are within 25% of the corresponding characteristic of the original circuits. In the other mode, the random circuit generator extracts the analysis results from a set of RTL circuits and uses that data to generate a random circuit with post-synthesis characteristics in an acceptable range.
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