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UBC Theses and Dissertations

Whose cache line is it anyway : automated detection of false sharing Spear, Mark Anthony


The abstraction of a cache is useful to hide the vast difference in speed of computer processors and main memory. For this abstraction to maintain correctness, concurrent access to memory by different processors has to be coordinated such that a consistent view of memory is maintained. Cache coherency protocols are responsible for this coherency, but can have adverse implications for performance. The operational granularity of these protocols is a “cache line” (e.g. 64 bytes). Depending on the data contained in the cache line and the data’s access patterns, the coherence can be superfluous and the performance implications severe: Consider the case where each byte within a cache line is exclusively read and written by specific cores and no coherence between cores should be necessary. My collaborators and I developed a system which detects this phenomenon, known as false sharing, (my thesis), and present a system that can automatically rewrite programs as they are running to avoid the performance penalty. Some parallel programming benchmarks such as linear regression can see up to 3x-6x performance improvement.

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