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Experiments and simulations on negative/positive bias temperature instability in 28nm CMOS devices

University of British Columbia

CMOS transistors come with a scaling potential, which brings along challenges such as process variation and NBTI/PBTI (Negative/Positive Bias Temperature Instability). My objectives during this project are to investigate effects of aging on CMOS devices as well as to show experimental results in order to model the effect of N/PBTI specifically targeting the 28nm technology node. The direct effect of transistor aging is a degradation of device threshold voltage, which can lead to performance degradation or malfunctions. Places such as server farms, data centers, and outer space-crafts, where device reliability for a long period is significant and accessibility is an issue, can benefit from an aging reversal process. In addition, as transistor channel lengths become smaller, they are more prone to a reduced lifetime. The exact causes of aging are not entirely known until this day and as a result, no real mechanism to reverse the process has been fully implemented on FPGAs or ASICs. I believe the true solution to these scalability challenges lay within the device structure and materials used in CMOS transistors, however, accelerated recovery at high temperatures can also help in reversing the effect of aging by a noticeable amount. I have been able to use this technique to reverse the effect of threshold voltage degradation in FPGAs. In this thesis, I present experimental results on the effect of degradation and recovery on a commercial FPGA. I then use the experimental results to calculate degradation parameters of transistor aging in this technology node and propose experimental setups for a 28nm ASIC.

Text

2015-10-24

Attribution 2.5 Canada

http://hdl.handle.net/2429/55104

Electrical and Computer Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by/2.5/ca/