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Reliability study of bipolar transistors with metal-insulator-semiconductor heterojunction emitters Szeto, Ngam 1988

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RELIABILITY STUDY OF BIPOLAR TRANSISTORS WITH METAL-INSULATOR-SEMICONDUCTOR HETEROJUNCTION EMITTERS. by Ngam Szeto B.Sc., Queen's University , 1985 A thesis submitted in partial fulfillment of the requirements of the degree of Master of Applied Science in The faculty of Graduate Studies Department of Electrical Engineering We accept this thesis as conforming to the required standard The University of British Columbia July 1988 ©Ngam Szeto, 1988 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of £LZC W CAI /££R}/J& The University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 Date AUfr /Ml i i Abstract Bipolar transistors employing an MIS junction for the emitter exhibit the very desirable properties of high operating frequency and/or high common emitter gains. The topic of this thesis is to investigate the usefulness of the MIS bipolar transistor in real applications. The experimental results show two possible limitations of the devices. The principal limitation is the inability of these devices to withstand moderate temperature stressing. The second limitation is the relatively high emitter series resistance. The principal degradation mode of these devices under temperature stressing is suggested to be the reduction of the thin insulating oxide. Acknowledgement The author gratefully acknowledges the following people for their help during execution of this thesis. N.G. Tarr is credited for supplying the silicon wafers and masks for producing the MIS bipolar transistors. D.S. Camporese is acknowledged for his contributions to the development of the process for fabricating the transistor. Special thanks for D.L. Pulfrey for the continuous support and discussions that made the completion of this thesis possible. The author also acknowledges the financial support of the Natural Sciences and Engineering Council of Canada. "I Table of Contents Abstract Acknowledgement List of Figures List of Tables Chapter 1 Introduction Chapter 2 Theory 2.1. The MIS junction model 2.2. The MIS BJT model 2.3. Model calculations 2.3.1. Effect of oxide thickness . 2.3.2. Effect of carrier lifetime 2.3.3. Effect of metal work function 2.4. Chapter summary Chapter 3 Preliminary Experiments 3.1. Choice of metal 3.1.1. Fabrication of Al-I-S and Ti-I-S diodes 3.2. Emitter metal patterning 3.2.1. Fabrication of Mg-I-S diodes 3.3. Experimental results and discussion Chapter 4 MIS BJT Fabrication 4.1. Overview of processing 4.1.1. Pre-treatment 4.1.2. Collector metal deposition 4.1.3. Oxidation 4.1.4. Emitter deposition and definition 58 4.2. The transistor structure and test patterns ... 59 Chapter 5 Temperature Stress Tests 63 5.1. The experimental setup 63 5.2. Comparison of Mg, Al, and Ti devices 65 5.3. Comparison of Mg and Polysilicon devices 71 5.4. Discussion 75 Chapter 6 Series Resistances Measurement 83 6.1. Methods of measurement 83 6.1.1. Open collector method 83 6.1.2. Ning and Tang method 84 6.2. Discussion 91 Chapter 7 Conclusion 92 References 94 Appendix A. Fabrication Procedures 96 A.1. Procedure for MR-20 and GT-G series devices .. 96 A.2. Procedure for GT-J series devices 101 Appendix B. Software Listings 108 List of Figures vi Figure 1.1. Current components of a typical NPN transistor 2 Figure 1.2. Structure of the MIS BJT 7 Figure 1.3. Structure of the polysilicon emitter transistor 8 Figure 1.4. Alternative structure of polysilicon emitter transistor 9 Figure 2.1. Band diagram for a MIS junction 13 Figure 2.2. Band diagram for a MIS BJT 19 Figure 2.3. Current components of a MIS BJT 20 Figure 2.4. Gummel plots of a Mg-I-Si BJT with different oxide thickness 27 Figure 2.5. Gummel plots of an Al-I-Si BJT with different oxide thickness 28 Figure 2.6. Gummel plots of an Al-I-Si BJT with different carrier lifetime 30 "I Figure 2.7. Gummel plots of a M-I-Si BJT with different metal work functions 32 Figure 3.1a. Band diagram of a MIS junction that causes accumulation 35 Figure 3.1b. Band diagram of a MIS junction that causes inversion 35 Figure 3.2. Structure of the MIS dot diodes 38 Figure 3.3. The emitter mask for the MIS BJT vii experiment 44 Figure 3.4. Log(J) vs V curves for the Al-I-Si dot diodes 46 Figure 3.5. L®g(J) vs V curves for the Ti-I-Si dot diodes 47 Figure 3.6. L©g{J) vs V curves for the Mg-I-Si diaREtes - - 48 Fifure 4.1. Structure of the MIS BJT 51 Figure 4.2. Duping profile of the base implant for tils- 341S BJT 53 Figure 4.3. Log(U) vs V curves for Al-I-Si dot ditcaaes with different oxide growth csmfflitions .., - 56 Figure 4.4. SHaiHCtnare of the Van der Pauw test p£C-tern • 61 Figure 5.1. Dsssgrnadation of current gains for the GUMS series devices 66 Figure 5.2. GmMimsl plots for Mg-I-Si transistor ... 68 I Figure 5.3. Gmmmel plots for Al-I-Si transistor ... 69 Figure 5.4. Gjummel plots for Ti-I-Si transistor ... 70 Figure 5.5. Gramme1 plots for GT-J series Mg-I-Si tarsmsistor 73 Figure 5.6. Guatranel plots for GT-J series polysilicon enittter transistor 74 Figure 5.7. Lrogjl(Jc) vs V B C curves for Mg-I-Si taranasistor 76 vi i i Figure 5.8. Log(Jc) vs V B C curves for polysilicon emitter transistor 77 Figure 5.9. The effect of shunt resistance on Al-I-Si transistor characteristics 79 Figure 6.1. V C E vs Ig curves for Mg-I-Si transistor 85 Figure 6.2. V C E vs curves for polysilicon transistor 86 Figure 6.3. Series resistance components 88 Figure 6.4. (kT/qIc)In(IBQ/IB) vs 1/0 curves for Mg-I-Si transistor 89 Figure 6.5. (kT/qIc)In(IBQ/IB) vs 1/0 curves for polysilicon transistor 90 I List of Tables ix Table 2.1. Nominal Parameters used for MIS BJT model calculations 24 I 1 Chapter 1 Introduction Silicon bipolar junction transistors (BJTs) have been used extensively for the last thirty years or so. Although new technologies have evolved, the need for bipolar devices has never stopped. In fact, the fastest silicon digital logic nowadays is still emitter coupled logic (ECL), which is based on bipolar technology. However, as the need for faster computers and higher frequency communication devices grows, bipolar technology is continually being developed in order to further improve the operating speed. Presently the fastest devices have cut-off frequencies (fT) around 15-20 GHz. The techniques under development to increase the performance of BJTs, including the use of metal-insulator-semiconductor (MIS) and polysilicon emitter devices, are briefly reviewed in this chapter. The current components of a typical NPN BJT operating in the active mode are shown in Fig. 1.1. J I N j and J B I N j are the current components that make up the emitter current Jg. J___, J__„ and J„DI! are the recombination current components KHiHj KtiL KciD that correspond to recombination of holes in the neutral emitter, base-emitter space-charge region, and the neutral Emitter ( " ) Electron Flow INJ \ j REE / \ BINJ Hole Flow u REC 0 Base (P) V REB l / N JB Fig. 1.1. Current components Collector (n) j E H J CBpN typical NPN transistor 3 base respectively. Jg E N is the generation current in the base-collector space-charge region, and J C B p t h e hole saturation current due to transport across the base-collector junction. The current components at the three terminals of the BJT are then: JE - JINJ + JBINJ (1.1) JB " JB (1.2) JC " JCn + JCBp (1.3) One approach to obtaining a higher cutoff frequency in a BJT is to first increase the common-emitter current gain and then trade off some of this gain for a higher operating frequency. To achieve high common-emitter current gain, the collector current J c should be maximized while minimizing the base current Jg. Several techniques are available and can be used together to achieve the goal. the traditional approach to achieve higher performance BJTs is to increase the emitter injection efficiency by using a lightly doped base and a heavily doped emitter. This arrangement allows the base minority carrier diffusion current to dominate the base-emitter current carrier transport process, since the minority carrier concentration in the emitter is much less than that of the minority carrier concentration in the base region. Furthermore, the base-emitter depletion region appears mainly in the base 4 region, causing a narrower effective base width, and so reduces the neutral base recombination current. The dopants can be introduced by either diffusion or ion implantation techniques. The latter is preferred as it can provide better control for doping in the base and emitter regions of the transistor. The tight process control that is possible with ion implantation also allows the width of the base region to be made very narrow, further reducing the neutral-base recombination current. A typical base width in state-of-the art silicon BJTs is 0.15Mm [l]. Ion-implanted high/low emitter/base junctions and narrow bandwidths are employed in modern silicon bipolar transistors to achieve better performance and better process control. However, as the doping density of the emitter region increases, bandgap narrowing occurs and Auger recombination takes place. Both these effects cause a reduction in emitter injection efficiency, thereby reducing the transistor performance. It is known that metal in close vicinity to semiconductor material will cause band bending in the semiconductor. With the right choice of metal, the surface of the semiconductor can be inverted and the band bending in the semiconductor will resemble that of an ideal p-n 5 junction. Theoretically, if the separation between the metal and the semiconductor is infinitesimally small so that both electrons and holes can tunnel through the separating material, the structure will behave like an ideal p-n junction, with minority carriers within the semiconductor dominating the current transport process [2]. However, when the metal comes in direct contact with the semiconductor, the metal-semiconductor interface will have a large surface state concentration, due to dangling bonds that result from the incompatible bonding structures of the two materials. The large amount of surface states will accommodate the major portion of surface charges that result from the work function difference between the metal and the semiconductor, leading to less band bending in the semiconductor. As a result, the barrier height of a metal-semiconductor interface is usually determined by the property of the semiconductor surface and the barrier height for minority carriers is larger than that for majority carriers. Low temperature silicon oxide grown on top of silicon bonds nearly perfectly to the semiconductor surface without causing a large surface state concentration at the silicon surface, while the thickness of the oxide can be controlled to such a degree that charge can tunnel through the oxide. With this technology, one can produce a MIS junction that behaves like an ideal p-n junction with the minority carriers dominating the current transport process, while minimizing the majority carrier flow. Furthermore, the MIS junction will not suffer from the heavy doping effects which can degrade the performance of conventional homojunction bipolar transistors. Bipolar transistors employing the MIS junction as a replacement for the heavily doped emitter, are presently the subject of much research. The structure for these MIS BJTs is shown in Fig. 1.2. Extremely high common emitter gains, of the order of 30,000 have recently been reported for such devices [3,4]. Gains of this magnitude are not of great practical importance. However, the extremely high gain offers an opportunity for trading-off the gain to achieve a higher operating frequency. This can be most obviously done by increasing the base doping density. This reduces the emitter / base injection efficiency and the base transport factor, so lowering the current gain. However it also reduces the base resistance, and it is this factor which leads to an improvement in frequency response. This approach has been adopted by several large semiconductor companies. Silicon BJTs fabricated at Plessey research can be operated up to 11 GHz [5], while NTT and Tektronix have fabricated similar devices that have cutoff frequencies of 16 GHz and 15 GHz respectively [6,7]. These Base metal (Al) V / / / / / / / / A Emitter metal Tunneling oxide -JZ2I Si02 YzzzzzzzzzA p+ p+ n substrate Collector metal (Al) Fig. 1.2. Structure of MIS BJT -N Emitter metal (Al) Base metal (A l ) / ' _ Polysilicon / ) / / / / / / / / A V / J / / / / / / / X / . Si02  Y 7 / / / / / / / / A P+ P+ n substrate Collector metal (Al) Fig. 1.3. Structure of polysilicon transistor 00 Polysilicon Emitter (n+ ) Base metal (AlV T u n n e | i n g 0 x i d e P73 " ^ Si02 YZZZZZZZZZX P+ 2 Intrinsic Base L n substrate YzzzzzzzzzA Mono Emitter P+ Collector metal (Al) Fig. 1.4. Alternative Structure for Polysilicon Emitter Transistor 10 cutoff frequencies are a great improvement for silicon devices, and they are just high enough to be used in modern day microwave communication equipment. These excellent results have been achieved using transistors with polysilicon emitters, rather than MIS tunnel junction emitters. The polysilicon may act like the metal in a MIS BJT in the structure shown in Fig. 1.3. [8]. Alternatively the polysilicon tunnel junction may replace the metal layer in a conventional BJT structure, see Fig. 1.4. [9]. The reasons why these polysilicon emitter structures give high gains is still under discussion [9,10,11]. The highest gains so far reported are around 10000 [8]. Both of these new developments in improving the performance of bipolar transistor seem to be very attractive. However, to date there have been no stability and feasibility studies to indicate whether these high performance devices can be implemented in any real applications. A major concern with all the devices lies in the ability to grow the ultra thin oxide layer to an acceptable degree of uniformity in thickness, composition and quality. An additional concern.for the MIS junction is the stability and durability of the ultra thin layer of oxide. Aluminum is known to reduce silicon dioxide, both duri ng the deposition of the metal [12] and on subsequent temperature stressing [13]. It is the main purpose of this 11 thesis to investigate the stability of these MIS-emitter transistor (MIS BJT) devices and to draw a conclusion as to whether the current stage of development of these devices is such that they can be used in any real application. Another factor that determines the feasibility of implementing these devices is the series emitter resistance. It has been shown that the emitter current of a bipolar transistor of any size, should remain roughly unchanged in order to maintain optimal circuit performance [14]. In VLSI applications, the size of the emitter area is so small that any emitter series resistance would become an important factor in limiting the circuit performance. The interfacial oxide layer in the MIS BJT is a major threat to the successful implementation of the device in VLSI applications. The emitter series resistances of both the MIS BJT and polysilicon emitter transistors were measured to further ascertain the feasibility of implementing these devices in VLSI applications. Chapter 2 i Theory It is well known that the MIS tunnel junction can behave almost like an ideal pn junction diode [2]. Moreover, the MIS junction is far easier to fabricate than a conventional diffused or ion-implanted pn junction. To formulate the junction characteristics with respect to metal work function, oxide thickness, doping density, carrier lifetime and insulator bandgap is not an easy task. However, with the help of a computer, one can set up numerical model for the MIS junction. In this chapter a model for the MIS junction diode [2] is reviewed and then used as the basis for a model of a three terminal device, a BJT transistor with MIS emitter. 2.1. The MIS junction model l The band diagram of a typical M-I-p/Si junction is shown in Figure 2.1. There are two tunneling current components J C M and J ^ in the model which represent the electron and hole tunneling currents respectively: JCM " I e C M \ i T 2 ( F 1 [ ( E F n ( V " V X S ) ) / k T ] - F 1[(E p M(X s) - Ec(Xs))/kT]) (2.1) Rg. 2.1. Band diagram for a MIS junction under forward bias 14 JVM " "f e i M A h i T 2 ( F 1 [ ( E V ( X S ) " E F p ( X S ) ) / k T ] - F1[(EV(XS) - EpM(Xs))/kT]) (2.2) where and are the tunneling probabilities for 'fc * electrons and holes respectively, Ag and A^ are the effective Richardson constants for electrons and holes respectively, F1 is the Fermi-Dirac integral of order one and the summations run over all the conduction band peaks and valence band valleys. There are also three surface state current components, JMT' JCT' a n d JVT represent the metal to trap, semiconductor conduction band to trap and valence band to trap currents, respectively: J m t - " t M i > ( 2 . 3 ) Mi JCT = S NTi Cni [ n ( XS ) ( l- £Ti ) " nli fTi ] ( 2' 4 ) J ^ = q I N T i c P i [ p ( X S ) f T i " P U ( 1 " f T i)] (2.5) where N ^ is the trap density at the i t h level and f T i is the occupancy probability at that level, is the characteristic time for the metal-to-trap tunneling process and f M i is the probability that the i t h level will be occupied when in equilibrium with the metal, C and C are P n the capture cross sections for holes and electrons multiplied by the average carrier thermal velocity. The charge stored in the surface states Q g s is given by 15 QSS " J fTiNTi + 5 ^ (1 - f T i)N T i (2.6) acceptors donors Finally, there are two semiconductor current + + components, J p^ xs ^ a n d Jn^XS which represent, respectively, the hole current and the electron current just inside the semiconductor. These currents are linked together by the need for current continuity at the interface. For instance, JCM - JCT " Jn(XS> ( 2' 7 ) and JVM " JVT = V * ^ ( 2' 8 ) Another boundary condition comes from the summation of the potential drops across the entire diode. These three boundary conditions must be satisfied for the model to produce accurate solutions. By making the assumptions that the majority-carrier quasi-Fermi level is constant throughout the semiconductor and the quasi-Fermi levels for both carriers are constant throughout" the space-charge region, the boundary condition that is concerned with the majority carrier (2.8) is overridden. The net minority current component Jn(X*) is given by Jn ( XS } = Jd (* } + J r q ( * ' V " JUPC ( 2' 1 0 ) 16 where J^(<t>) is the minority carrier diffusion current, Jrg(0,*//g) is the recombination current in the space charge region and J Up C is uncompensated photocurrent. The expressions for J^ and Jrg from the standard pn junction theory are used here [15]. The uncompensated photocurrent term J Up C in the above expression allows for the modelling of photovoltaic effects. It is included for the sake of completeness, but will always be equal to zero for the purpose of this thesis. J d U ) = J o d [exp(q4>/kT) - 1] (2.11) and J r g U , ^ s ) = J o r g U s/2^ B) 1 / 2 [exp(q0/2kT)-l] (2.12) and J o rg are user input parameters through which the carrier lifetime and semiconductor doping density are included in the model, J 1 / ? — [D /r ] (2.13) od VT n7 n NA ? A and 9 n i 1 / ? J o r n = — [ 2 e„ ( 2\p^)qNh \ ' ( 2 . 1 4 ) org „ 1 S YB M A n where 2\p is the built-in potential at the onset of strong B inversion . Last of all, the potential across the insulator i/^  must be calculated in order to evaluate expression (2.9). is related to the total charge stored on both sides of the 17 insulator, by Gauss' law. The charge stored is comprised of Qg, the charge stored in the semiconductor space charge region, and Q g g the charge stored in the surface states. The expression of is then = -77 (Qs + Qss ) ( 2 - 1 5 ) where d is the insulator thickness. Qg can be found by assuming that both Ep^ and E p n are constant across the space charge region within the semiconductor [2], then Q s = sgnUg) (2kTes)l/2 { N cF 3 / 2 [ (Epn (Xg) - Ec(Xg))/kT] - n(Xn) + N vF 3 / 2[(E v(X s) - Epp(Xg))/kT] - p(Xn) qt 1/2 + N } (2 .16) U kT where p(xn) and °(xn) are the hole and electron concentrations at the boundary of the space charge region and the quasi-neutral base. ? All the terms in expressions (2.7) and (2.9) can be evaluated by knowing both and 4>. After postulating initial values, one can iterate on and $ until the two boundary conditions (2.7) and (2.9) are met, In this way the currents J ^ and J C M for a given applied voltage V can be computed. 2.2 The HIS BJT model The model to be discussed assumes a M-I-p/Si-n/Si 18 structure. The band diagram for such a device operating in the active mode, is shown in Fig. 2.2. The model for the MIS BJT is very similar to the MIS junction diode model. In fact, the MIS BJT model is merely an extension of the MIS junction diode model, with a few additional current components. A few assumptions were made, in order to keep the model simple and to make it easy to study the device sensitivity to various parameter changes. The assumptions are that the base region is uniformly doped and contains a quasi-neutral region during operation, and that both high level injection and series resistance effects can be ignored. The current components for the model (shown in Fig. 2.3), include those used in the MIS junction diode model, and the new currents J R E C , Jn<0)# J n ( W b ) ' JRE' Ji 'i n GEN and J CBP J R E C is the recombination current in the base-emitter space charge region, such that (2.17) where W B E is the depletion width of the base-emitter junction, and t is the electron life time. BE n W. (2ests/qNk) 1 /2 ( 2 . 1 8 ) BE S S 19 Fig. 2.2. Band diagram of MIS BJT Emitter Si02 Metal 'CM < JMT JVM JCT V JREC V JVT Base (p) S / JRE / \ l/Sl J G E N IS/I J B l / s i 0 w B Fig. 2.3. Current components of the MIS BJT Collector (n) JCn J C B p 21 The currents, at both boundaries of the neutral base are represented by Jn(0), the current at the emitter boundary, and Jn(wB)r the current at the collector boundary. The expressions for Jn(0) and Jn(wB)/ can be found by solving the continuity equation with no drift current component for a uniformly doped base. dn 6n (x) 32n (x) = - - + D 1 = 0 (2.19) dt r n dx* n where n is equal to the minority carrier concentration in the base region, 6nfi is the excess minority carrier concentration, and D n is the minority carrier diffusion constant in the base region. The solutions for the continuity equation are as follows: j (0) = q [ 5 nB ( 0 ) C° S h ( WBeff/ Ln ) " * n B ( V ] ( 2 2 Q ) L n sinh(WBeff/Ln) and , q D [Sn (0) - 8n (W ) cosh(W / L ) ] Sn(WB) = 0 1 B e £ f n (2.21) Ln s i n h ( WBeff/ Ln ) where the expressions for the excess carrier concentrations at the boundaries of the base region, and the effective base width are as follows: 8nB(0) = n B Q (exp(q<£ / kT) - 1) (2.22) 6nB(WB) = n B 0 (exp(qVBC / kT) - 1) (2.23) WBeff = WB " WBC " WBE (2.24) where V?BC is the base-collector depletion width in the base 22 region, and is expressed by WBC = ( 2 eS (Vbi " VBC ) / « N A ) 1 / 2 ( 2' 2 5 ) The difference between Jn(0) and ^ n( w B) is equal to the recombination current within the neutral base hence: Kiii JRE = J n ( 0 ) " J n ( V ( 2' 2 6 ) The current components contributed by the reverse biassed base-collector junction are J Q E N and J C B p, where J Q E N is the generation current within the base-collector space charge region and <JCBp is the reverse bias saturation current of the junction. q n i w c b JGEN = TT72 (2.27) TrJ n p and ;c b p = < v P > K where D p, rp and rn are model parameters that represent the diffusion constant for holes, and the effective lifetimes for holes and electrons respectively. is the total width of the base-collector depletion region, expressed by: 2ec N. + N n . WCB " [ - 7 - < * > <Vbi + V C B)] 1 / 2 (2.29) q n a d The minority carrier current component at the boundary of the semiconductor and insulator, Jn(Xg) is now given by: 23 Jn ( XS> = JREC + J n ( 0 ) ( 2' 3 0 ) The two boundary conditions for the MIS BJT model are then: " VBE " *M " + *SC " + = 0 ( 2' 3 1 ) and JCM " JCT " J n ( 0 ) + JREC ( 2 ' 3 2 ) Once again, the model can be solved by iterating both vl/g and <j>, until the two boundary conditions are met. The emitter, base, and collector currents are then: JE = JCM + JVM + JMT <2'33> JB = JVM " JVT + JRE + JREC ' JCBp " JGEN (2.34) J c - J N(W B) + J G E N + J C B p (2.35) 2.3. Model Calculation The theoretical MIS BJT model was tested, using parameters listed in Table 2.1. The values for N A and N^ were obtained by approximating the simulated doping profile of the experimental device MR-20 (refer to section 4.3.) using SUPREM II by uniformly doped regions. The electron affinity and the metal work functions for Al and Mg were obtained from the literature, together with the diffusion constants D n and D , and the effective Richardson constants A and A, [16], The effective lifetimes r and r were e n n p approximated from previous life time measurements of similar Parameter Value Substrate Doping Density (cm 3 ) 4.0x1016 Neutral Base Doping Density (cm — ^ ) 1.5x10 Silicon Valence Band Energy (eV) 3 . 7 3 * Metal-Insulator Barrier Height (eV) Aluminum 4 . 8 0 * Magnesium 5 .55 * Electron Effective Mass in Insulator 0.65 m e Insulator Band Gap (eV) 8.0 Insulator Thickness o (A) 10 Density of States Ratio (N C / N V ) 0 .372 Effective Richardson Constant Electrons ( A - c m - 2 o K - 1 ) 45 H6les ( A - c m - 2 ° K - 1 ) 78 Carrier Lifetime Electron (uS) 6 Holes (uS) 6 *: These energies are measured with respect to the insulator valence band. Table 2.1. Nominal Parameters used for MIS BJT Model Calculations. 25 devices [17], and the oxide thickness was also approximated from previous observations [2]. However, neglecting the series resistance, and high injection level effects does raise some problems regarding the usefulness of the device sensitivity studies. The emitter current will increase without bound as the oxide thickness or the metal work function is decreased. This problem was solved by using an external series resistance model in conjunction with the MIS BJT model. The series resistance model simply makes the approximation that I„ is equal to I c and then calculates the effective V B E by subtracting the voltage drop across the series resistance from the applied Vni:,. bet 2.3.1. Effect of oxide thickness The ultra thin layer of tunneling oxide is the key factof- in achieving high gain in a MIS BJT device. Any change in oxide characteristics is likely to have a direct influence on the device behavior. One of the most important parameters of the oxide, is the oxide thickness. It is so thin that it is very sensitive to processing conditions and oxide reduction by the overlaying metal. The eff ect of change in oxide thickness was investigated using the MIS BJT model. The model shows that 26 the gain of the device would increase without bound as the oxide thickness is reduced. This is due to the fact that the model assumes a perfect layer of oxide and both the high level injection and series resistance effects are ignored. A thinner layer of oxide would enhance the tunneling probabilities for both carriers leading to higher limiting currents, but as long as the oxide continues to passivate the semiconductor surface, the back injected hole current will still be orders of magnitude below that of the electron injection current. In reality, the gain of the device cannot be increasing without bound, as the current density will be limited by series resistance and high level injection effects. An external series resistance model was used to get more realistic results for the MIS BJT model. The simulated results with series resistance (shown in Fig. 2.4 & 2.5) show that the gain of the device is still increasing but at a much slower rate and is not going to be unbounded. From the simulated results, one can see that the device is not going to suffer from reduction of oxide thickness, as long as the oxide keeps its property of passivating the semiconductor surface. 2.3.2 Effect of carrier lifetime v B E (V) Simulated with series resistance of 500 Micro Ohm—cm^ Fig. 2.4. Effects of Oxide thickness on Mg—I—Si transistor 28 < < O -3 CD O O 4 -1 3 -2 -1 -0 - 1 - 2 - 3 H - 5 -- 6 -JC3 JB2 " T 0 X = 15 A I I q x = J°_A_ JB3, JC3 - Tgx = 5 A - 8 , | , t ' i ' i ' i 1 I 1—1—"Fnr™,™,T™T,L—r 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VB E (v) Simulated wfth series resistance of 500 Micro Ohm-cm2 Fig. 2.5. Effects of oxide thickness on Al—I—SI transistor 29 The carrier lifetime in the base region is another important factor in high performance MIS BJTs. A short carrier lifetime would increase both the recombination currents in the base-emitter space-charge region and neutral base region. This would in turn increase the base current and decrease the gain of the device. The MIS BJT model was used to investigate the effect of change in carrier lifetime. The model result (shown in Fig. 2.6) clearly shows an increase in base current in the low bias region as the minority carrier lifetime decreases. This is consistent with the argument of increasing base recombination current, since the recombination dominated region for a BJT is at the low bias region. However, the base currents at the higher bias region are virtually the same'for the range of carrier lifetimes investigated. This is because the base current at high bias regions is dominated by the holes back-injected into the emitter rather than the holes participating in the recombination process in the base. 2.3.3 Effect of metal work functiorr For low and moderate values of forward bias, the total electron current is small compared to its two components (i.e. J _ from metal to semiconductor and J_ from CM semiconductor to metal). This state of quasi-equilibrium 30 VBE (V) Pig. 2.6. Effects of carrier lifetime on A!-I—Si transistor 31 keeps E p n pinned close to E p m. However, for large currents there is an appreciable energy difference between these two Fermi levels, therefore the total applied base-emitter bias voltage will appear partially across the interfacial oxide. This would cause the device characteristics to deviate from an exponential dependency on the applied bias. Metals with different work functions will produce different surface carrier concentrations on the same semiconductor substrate and so will cause the device to enter the tunneling limited regime at different current densities [17]. The simulated result (shown in Fig. 2.7) shows that metals with higher work function would produce less surface inversion and would in turn lead to entry into the tunnel limited regime at a lower emitter current density. Note that this effect is similar to that resulting when series resistance is present. No series resistance was included in this simulation. The precise values of 4>M chosen, represent the of metals that have extremely low work function (2.3 eV), Mg (3.35 eV) and Al (4.4 eV). 2.4. Chapter Summary The predicted results appear to be reasonable in as much as they give realistic Gummel plots. As expected, high gain devices with p-type bases must have thin oxides, long electron lifetimes and employ metals with low work VBE (V) Fig. 2.7. Effects of metal work function on M—I—Si transistor functions. 34 Chapter 3 Preliminary Experiments 3.1 Choice of metal The dominating current transport carriers in a MIS junction can be determined by the combination of doping density of the semiconductor and the work function of the metal. The band diagram of a MIS junction with a n-type semiconductor and a low work function metal that causes accumulation at equilibrium is shown in Fig. 3.1a. Fig. 3.1b shows a MIS junction with a low work function metal and p-type semiconductor. This combination causes inversion of the semiconductor surface at equilibrium. It can be seen that any junction that is accumulated will have a large barrier height for its minority carriers in this case) causing the majority carrier to dominate the current transport process. However, the MIS junctions that cause inversion of the semiconductor surfaces will have a small barrier height for minority carriers and a large barrier height for the majority carriers (<t>Bn and respectively in this case), allowing minority carriers to dominate the current transport process. In order to optimize the performance of a silicon MIS BJT, electrons should be chosen as the dominating carrier Fig. 3.1a. Band diagram of a MIS £mction that causes accumlation <(>Bn r _ _.J e f tFm -©-r .. Fig. 3.1b. Band diagram of a MIS junction that causes inversion 36 because of their higher diffusivty as compared to holes. This will call for a M-I-p/Si-n/Si structure. Furthermore, the metal must have a low work function to invert the p-type base region, so that the relatively low barrier height for electrons will allow electrons to be easily injected into the base while blocking the back-injected holes through the high majority carrier barrier. The work function of the metal must be smaller than the effective work function of the intrinsic base, therefore the work function must be less than the intrinsic Fermi level. *M < *Si " XSi + V 2 = 4 ' 6 1 e V ( 3' 1 ) Several good choices of emitter metal from the point of view of work function would be Al, Ti, and Mg, since their work functions are all less than 4.61eV. However, the practical usefulness of devices made from these materials needs to be investigated. There have been several reports of degradation of tunnel junction diodes made with Al [13]. Mg is well-known to be very reactive and unstable [18]. While the Al metalization process is well established, Ti is a more stable metal leading to potentially more reliable devices. MIS diodes with the three selected metalizations were fabricated to verify whether the combinations of metal work functions and semiconductor doping densities were inverting 37 the semiconductor surface, and performing properly like pn junction diodes. 3.1.1 Fabrication of Al-I-S and Ti-I-S diodes Four boron doped, <100> orientated wafers with nominal resistivity of 0.1 fi-cm, 1 O-cm, 2 fl-cm and 10 fi-cm were cut into quarter wafers. Dot diodes were then fabricated simultaneously with quarters from each of the four different resistivity wafers, in order to investigate the effect of different doping densities. The structure of the dot diodes is shown in Fig 3.2. Groups of four quarter wafers were cleaned by following the standard RCA cleaning procedure [19]. Once the quarter wafers were cleaned, back contacts of aluminum were formed by evaporation of Al in a CHA vacuum chamber at a pressure of around 4x10 6 Torr. The back contacts were sintered at the s&me time as the growth of the ultra thin tunneling oxide in a quartz tube furnace. The oxide growth step required 5 minute warm-up and cool-down periods at 500°C with a nitrogen flow of 1L/min. The actual oxide growth period was between the warm-up angl cool-down periods at 500°C with an oxygen flow of 1L/min for 20 minutes [20J. The oxide thickness for such a procedure was estimated to be o around 15 A. The barrier metals were formed by evaporating the desired metal onto the front of the wafers, with a Barrier Metal • Tunnel Oxide y/////////////y. / !' v - ' i Depletion Xlnversion Layer Reg ion/ p Substrate b Ohmic Back Contact (Al) Fig. 3.2. Structure of the MIS dot diodes g o CP 39 shadow mask placed in between the wafers and the evaporation 2 source. The nominal area of the dot diodes was 0.01 cm . Problems were encountered during the evaporation of Ti. The CHA evaporation power supply can only supply filament current in the order of 100 A maximum, which is not enough to evaporate the Ti at an acceptable rate of deposition. The prolonged period of evaporation at an extremely high temperature caused the Ti contact to be oxidized, producing o a deposit of dark black color. The resulting film was 1500 A thick and was found to have a very high resistivity. A Veeco vacuum system, which was capable of supplying a higher current (150A), was also used to produce a second set of Ti diodes. However, this approach did not seem to help reducing the oxidation of Ti and hence did not reduce the metal resistivity. Tjhe Al metalization was performed in the CHA chamber, and did not lead to any oxidation problem, due to its relatively high vapor pressure. The rate of deposition can be easily adjusted to give an acceptable deposition time without overheating the substrate. The thickness of the Al o film was chosen to be 3000 A in order to reduce the metal resistance [20]. 40 3.2 Emitter metal patterning The shadow mask method is perhaps the best method to pattern the barrier metals for large MIS junctions. The method patterns the metal at the same time as the deposition of the metal, hence eliminating the possibility of damage to the underlying tunneling oxide by any further processing steps. However, the shadow mask method runs into a lot of problems when a fine metal pattern is required and alignment of the metal pattern to previous structures is critical. Photolithography provides a second means of patterning the emitter metal. Currently there are two photolithrography schemes available, namely the lift-off technique and the direct patterning technique. The lift-off technique can eliminate the over etching effects, which can occur with direct etching, and will work on any metal without having to worry about the choice of etchants. However, lift-off has a major5 drawback in producing MIS junctions. The lift-off method requires the photoresist to be patterned before metal deposition. This extra processing step could lead to possible damage and contamination of the underlying tunneling oxide. Therefore, the direct patterning method is preferable in MIS junction fabrication. Direct patterning of Al is well-established. The commonly used phosphoric acid is a safe etchant, since it 41 will etch off the Al without causing any damage to silicon and silicon oxides. Acceptable etch rates can be achieved by using diluted (1:1) H 3 p 0 4 with DI water when heated to 60°C. The etch rate for such an etchant is approximately 300 A/Min. Patterning Mg, however, is a much more difficult task than patterning Al. The highly reactive Mg reacts violently with many common etchants, leading to complete removal of the Mg contact. The right choice of etchant and the optimal concentrations must be determined, in order to fabricate high performance Mg-I-S devices. Despite the fact that the lift-off technique of patterning could lead to possible damage and contamination of the tunneling oxide, publications [3,4] have recorded working MIS BJT fabricated with' the lift-off technique of patterning the emitter metal. JTwo silicon wafers were used to study and optimize the Mg patterning procedure. The p-type 10 Q-cm <100> oriented o wafers were cleaned using the RCA cleaning procedure. 3600 A of Mg were deposited on the front of the wafers, using a "Drummel" type tantalum boat as the evaporation source in the CHA vacuum chamber with a pressure of 2 x 1 T o r r and o deposition rate of around 10 A/Sec. Positive photoresist (Shipley HR316) was spun onto the wafers followed by a soft bake to dry out the photoresist. The emitter mask (Fig. 3.3) 42 for the MIS BJT experiment was used to pattern the photoresist using a Karl Seuss model 505 maskaligner. Once the wafers were developed and hard baked, they were scribed into quarters for studying the Mg etching process. Nitric acid was chosen to be the etchant for Mg, because it is commonly used in commercial Mg etching for producing press dyes [21], A number of different concentration HNO^ solutions was used to try to optimize the Mg etching process. It was found that a 0.1 % solution gave a satisfactory etch time of 3 minutes with minimal amount of overetching. Any solution with a higher concentration was found to lead to significant overetching. With extreme care device structures with dimensions in the order of 1 m® can be patterned by using the 0.1 % etchant solution. Ti patterning can be done by using low concentration HF solution. The Ti etching process was not studied until the * actual Ti-I-S emitter transistor fabrication, where a 1 % HF solution was used. Although the Ti emitter was underetched, the devices seemed to suffer from some loss of the ultra thin layer of tunneling oxide. This is most likely due to the fact that the etch rate of silicon oxides in HF solution is much faster than that for Ti. Further study must be made concerning Ti patterning, if improvements in the performance of Ti-I-S devices are to be made. 43 3.2.1. Fabrication of Mg-I-S diodes A set of Mg-I-S diodes was fabricated using the direct patterning scheme, in order to study the feasibility of producing such junctions with the proposed patterning procedure. Both the structure and the processing steps of the Mg-I-S diodes were similar to that of the Al-I-S and Ti-I-S diodes. The only difference was that the emitter mask (Fig. 3.3) for patterning the emitter metal in the MIS BJT, was used together with the proposed method for patterning the Mg instead of using the shadow mask technique. The 300 Mm * 300 Mm metal pattern was used as the diode contact. The wafer used in this experiment was boron doped, p-type with nominal resistivity of 2 fi-cm and <100> orientation. The processing steps prior to barrier metal deposition were identical to those of the Al-I-S and Ti-I-S » . 0 dot diodes fabrication. After the thin oxide growth, 3500 A of Mg was deposited on top of the oxide covering the entire wafer. Then, the Mg was patterned using the technique discussed in the previous section. The resultant Mg contact showed minimal amount of over etching. No noticeable damage to the thin tunneling oxide was found on examining the electrical properties of the diodes. 3.3 Experimental results and discussion 10um x 10um MIS BJT emi t ter contac t pad Fig. 3.3. The emi t ter mask for the MIS BJT experiment -f* 45 The current-voltage characteristics of the dot diodes made with the three different barrier metals were examined. Observation of an ideal p-n junction characteristic would confirm that these metals were properly inverting the semiconductor surface. Both the Al and Mg diodes were tested using the HP4145 semiconductor parameter analyzer, while the Ti diodes were tested manually with a platinum ball-shaped probe in an attempt to reduce the contact resistance. In all three cases, the log(J) versus V curves (shown in Fig 3.4 to Fig 3.6) showed typical p-n junction characteristics with a recombination - regeneration dominant region at low bias, a minority carrier injection-diffusion dominant region with ideality factor nearly 1 at the medium biasing range, and finally a tunnel limiting region at high bias. The Al and Ti diodes characteristics were almost identical at both the low and medium biasing range for a given substrate resistivity. This similarity is to be expected because the work functions for the two metals are almost the same. The change in tunnel limiting characteristics for wafers with different substrate i resistivities at medium bias was also observed for the Al and Ti diodes. The tunnel limiting current decreases as the • substrate doping density increases. The less inverted surface would have less minority carriers available for the i I ] 46 4 i < o vx o o V D (V) Fig. 3.4. Log(J) vs V curves for the Al-I-Si dot diodes V D (V) Fig. 3.5. Log(J) vs V curves for the Ti—I—Si dot diodes 48 VD (V) Fig. 3.6. Log(J) vs V curve for the Mg—I—SI diode 49 bulk diffusion current carrying process, hence the overall current would be decreased. However, this change in characteristics was not observed at high bias, presumably because of high level injection and series resistance effects. The above results show that the three chosen barrier metals are inverting the p-type silicon properly, thus causing the electron minority carrier current to be the dominant current component. Fabrication of MIS BJTs with direct patterning of both Al and Mg metalization can be achieved with no noticeable damage or contamination to the underlying tunneling oxide. Therefore, no reduction in the performance of MIS BJTs due to surface state effects at the metal and the thin oxide interface should occur. In the case of Ti, the etchant used in the experiment seemed to have damaged the underlying tunneling oxide and caused poor stabilities. 50 Chapter 4 MIS BJT fabrication The MIS BJTs used for the MIS BJT experiments, were prepared partly at Carleton University and partly at UBC. The processing steps carried out at Carleton and UBC will be discussed separately in the following sections. 4.1 Overview of processing N-type, <100> orientated wafers with substrate resistivity of 3-5 fl-cm were used as the foundation for the M-I-p/Si-n/Si structure transistors (shown in Fig. 4.1). The extrinsic base region was formed by performing a boron diffusion at Carleton University, then the wafers were shipped to UBC for the intrinsic base implantation of boron. The intrinsic base was formed by ion implantation with an implantation energy of 50 keV for the first batch of MIS BJTs and 30 keV for the second with dosage of either 12""2 12 -2 10 cfn or 5x10 cm , then the implanted bases were annealed at 950°C for 30 minutes. The reasons for having two batches of devices was because the first batch of devices exhibited relatively low gains. The doping profile was modified on the second batch to try, to improve the device performance. Also, this batch of wafers contained" some ready-made polysilicon devices which could be used to compare MIS BJT and polysilicon emitter transistors. The Base metal (Al) V / / / / Z / / / A Emitter metal Tunneling oxide 0 T SiO-YzzzzzzzzzA p+ p+ Intrinsic Base overlap n substrate Collector metal (Al) Fig. 4.1. Structure of the MIS BJT showing intrinsic base overlap 52 1 o - 2 doping profiles for the 10 cm implantations, as computed from SUPREM II simulations are shown in Fig. 4.2. The first batch was labelled GT-G, and the second GT-J. Once the intrinsic base region was formed, the wafers were shipped back to Carleton. The implantation oxide mask over the base contact window and the emitter contact window region was removed, a layer of Lotox was deposited, and was patterned on the wafer to protect the surface of the emitter contact. The base contact was patterned using the direct patterning scheme as in the emitter contact patterning, after 1 Mm of Al was deposited by e-beam evaporation. The patterned contacts were sintered in a hydrogen environment at 450°C for 10 minutes. A second layer of protective Lotox was deposited on top of the entire wafer except for the emitter contact windows. This Lotox layer was intended to protect the structures formed on top of the wafer from any proceeding cleaning steps, while allowing the emitter contact window to be cleaned. The finished wafers were then shipped to UBC for completion of the fabrication of the MIS BJTs. The remaining processes to complete the MIS BJTs were: deposition of the back collector contact, growth of the thin tunneling oxide and lastly, emitter metal deposition and definition. Before performing any of the above steps, the 53 8 -1 7 -• I 0.0 0.1 0.2 Base width (In microns) Fig. 4.2. Doping profile of the intrinsic base region 54 exposed intrinsic base surface had to be cleaned in order to keep the level of contamination low. This is thought to be necessary for reducing the number of surface states and ensuring the growth of a good quality oxide. 4.1.1 Pre-treatment The pre-treatment step is designed to ensure the cleanliness of the silicon surface of the MIS junction, and remove any native oxide on the silicon surface. The RCA cleaning procedure was used on the first batch of MIS BJTs to perform the pre-treatment step. However, the protective Lotox layer failed to protect the underlying structures during the RCA clean. The base contact metalization was completely removed. A modified RCA cleaning procedure with 1/10 of the cleaning time and leaving the HF cleaning step to the last, was also tried; significant loss of base contact was still observed. In view of these difficulties, the pie-treatment step was reduced to a single 10 second dip in 10% HF. 4.1.2 Collector metal deposition The MIS BJTs on each wafer shared a common collector which was the substrate itself. Instead of patterning a set of collector contacts on the front of the wafer, a large back contact was used to establish connection to the common o collector. 5000A of Al was deposited on the back of each 55 wafer using the CHA vacuum chamber. The sintering of the back contact was performed at the same time as the tunneling oxide growth. 4.1.3 Oxidation The oxidation process for the MIS BJTs was the same as that previously described for the MIS diodes, except that varying the time and temperature of oxidation was investigated. The change in thickness of the tunneling oxide can be observed by its effect on the MIS diode I-V characteristics. A thicker tunneling oxide would lead to higher series resistance, principally due to the decrease in tunnel probabilities. Three sets of MIS dot diodes with different oxide growth conditions were fabricated and tested to study the effects of oxidation temperature and duration. The oxide growth? conditions for these diodes were 500°C for 20 minutes, 500°C for 50 minutes, and 600°C for 20 minutes. The log(J) vs V curves for these diodes (shown in Fig 4.3) showed that the effective series resistance for diodes with lower oxidation temperature was less than that of devices fabricated at higher oxidation temperature. For diodes " with the same oxidation temperature but different growth durations, the effective series resistance seemed to have increased as the duration was increased. 56 V D (V) Fig. 4.3. Electrical properties of Al-I-Sf dot diodes with different oxide growth The change in effective series resistances showed, as expected, that the tunneling oxide thickness increases as the growth temperature or the growth duration increase. However, for the low temperature oxide growth process, the oxide thickness is considered to be self limiting for a given temperature [3], This result contradicts the result of the above experiment. There are two ways to explain the discrepancy. First, the oxide may not have reached its self-limiting thickness for the conditions investigated. Secondly, the oxide growth may not be uniform over the entire wafer, leading to pin holes or small regions with thinner oxide than elsewhere. As the oxidation duration was increased, these thinner regions would continue to oxidize, while the rest of the oxide would be self-limited from any further growth. The second case was likely to be the cause for the discrepancy, since a much decreased reverse bias saturation current and recombination-generation current at low bias were observed in the case of diodes with growth conditions of 500°C for 50 minutes. In the MIS BJT experiments, the 500°C, 20 minutes growth process was chosen on account of its lower series resistance, and its use in previous studies [3,4]. It may be better to choose a different oxidation process for better device stability. 4878 4.1.4 Emitter deposition and definition The emitter metal was deposited on the front of the wafer after the oxidation process. A brief discussion of the choice of metals, and patterning of the metals was presented in the previous chapter. The actual emitter metalization procedures were as follows. o The emitter metal thickness was chosen to be 3000 A. This should give acceptable sheet resistivity, without having to use unsatisfactorily long etch times for any of the three metals. Both Al and Ti were evaporated using a tungsten coil as the heating element in the CHA chamber. Whereas Mg was evaporated using a "Drummel" type tantalum boat as the evaporation source, in the CHA chamber. The acceptable deposition rates for both Al and Mg were about 5 o to 10 A per second, whereas the deposition rate of Ti was limited by the evaporation power supply to about 2 A per second. The direct patterning photolithographic method as described in the previous chapter was used to pattern the emitter metal. The etchant for the patterning of Al was 50% phosphoric acid heated to 60°C, and the etch rate was o about 300 A/min. For patterning Mg, 0.4 ml of HNC>3 was diluted with 400 ml of DI water to make a 0.1% HNO, etchant. 59 The etch time for patterning 3000 A of Mg on a full wafer was about 5 minutes, giving an average etch rate of 600 o A/min. However, if the above-mentioned etchant were used to pattern quarter wafers or half wafers, then a significant increase in overetching was observed. Ti patterning was performed by using 1 % HF acid at room temperature with an o etch rate of about 600 A/min. Because HF attacks silicon dioxide, a portion of the underlying oxide was damaged by the etchant, resulting in less stable devices. 4.2 The transistor structure and test patterns Two batches of MIS BJTs were fabricated for studying the possibilities of implementing MIS BJTs in VLSI applications. The performance and relative stability of the di fferent emitter metals and polysilicon emitter devices can also be compared. The first batch of devices was fabricated on MR-20 and GT-G series wafers. They were used solely to study -the effect of different metalizations and their relative stability. The second batch of devices was fabricated on GT-J series wafers, and they were used to compare metal emitters and polysilicon emitters. The transistor structures (see Fig. ,1.2. and 1.3.) were identical in both batches of wafers. In the first batch of MIS BJTs, the transistor with the largest emitter contact area was the one chosen to be 60 studied, from a number of different sized transistors on the wafers. This was because the direct patterning scheme had shown some damage to the emitter metal for the smaller devices. The 10 ym x 10 mhi devices with different intrinsic base region overlapping(refer to Fig. 4.1) were studied and compared with polysilicon devices of the same configurations on the same wafers, for the second batch of MIS BJTs. The smaller sized transistors were studied as they were of a more reasonable size for VLSI applications. A Van der Pauw cloverleaf for measuring the intrinsic base resistivity was also available for checking the base implantation. The structure for such a test pattern is shown in Fig 4.4. Tfro separate voltage vs current measurements were required to determine the base spreading resistance using the Van der Pauw method. First of all, the resistance in the ab direction was measured by injecting a charge flow through node b, a and measuring the potential drop across node c,d. The resistance in the ab direction is given by: Secondly, the resistance in the orthrogonal direction was 61 d Intrinsic Base region a Contact window j • Metal pad • I • / C b Fig. 4.4. Structure of the Van der Pauw test pattern measured similarly by injecting the current through node b,c and measuring the potential drop across node a,d. The resistance in the be direction is then: Vad R, = (4.2) b c Jbc Once the two orthrogonal resistances were known then the spreading resistance could be computed from: 's = 2 In 2 <Rab + Rbc > <4'3> Rab where f(—= ) is known as the Van der Pauw function, and it be is equal to 1 , if R ^ is the same as R^ for a symmetrical test pattern. The spreading resistance for the first batch of transistors was measured and checked against the SUPREM II simulations for the implantation process. The two resistances were of the same order of magnitude. The measured value was 25 KQ/square, while the simulated value of 17 Kft/square was in close agreement. 63 Chapter 5 Temperature stress tests As discussed in chapter 1, the major concern with MIS BJTs is the stability of the thin oxide layer. To study this phenomenon we subjected MIS BJTs to temperatures which the devices would likely be exposed to in commercial processing, e.g. temperatures of up to 400°C as may be encountered in wirebonding and packaging. The tests reported in this chapter are referred to as temperature stress tests. The devices were heated to a certain temperature for a specified time and then returned to room temperature for measurement of J-V characteristics. 5.1 The experimental setup An HP4145 semiconductor parameter analyzer was used to perform all the measurements of the transistor characteristics at room temperature. The log(J„ & J_.) vs V C B BE curve! with a small collector-base bias voltage were recorded after each stress, in order to observe the change in device characteristics. The base-collector characteristics were measured from time to time to ensure that there was no degradation jLn the base-collector junction. A Statham convection oven was used to heat-treat the 64 MIS BJTs for temperatures up to 265°C. A 1 L/min. flow of nitrogen into the oven was used to ensure an inert environment while stressing the devices. The device under test was placed in the oven at room temperature, then the temperature was ramped up to the desired stressing temperature in the nitrogen ambient. The stress durations were measured from the instant that the desired stress temperature was reached to the instant of turning off the oven's heating element. The devices were allowed to cool to room temperature with the nitrogen flow maintained. Therefore, the effective stress times were longer than the recorded values, but by performing the test this way the chance of reoxidation by exposure of the heated devices to atmosphere was minimized. However, some recovery process was observed when leaving the devices at room temperature and atmospheric environment for around 20 Hours. A Minibrute quartz furnace was used to stress devices at temperatures of 400°C and higher, since the maximum temperature setting for the Statham oven was only 265°C. The quartz furnace was pre-heated to the desired stressing temperature before placing the wafers into the furnace. A nitrogen flow of 1 L/min. was also used to ensure an inert environment for the wafers. The stress duration in this case was measured from the instant of placing the wafers in the furnace to the instant of removing them. The heated wafers 65 were sprayed with Freon gas for a faster cooling while preventing the heated wafers from being exposed to the atmosphere, at the moment of their removal from the furnace. 5.2 Comparison of Mg, Al, and Ti devices The GT-G series wafer with an implant dosage of 1 2 - 2 1x10 cm was used to compare the relative performance of Mg, Al and Ti MIS BJTs. The GT-G-4 wafer was scribed into quarters, which were then processed simultaneously. However, during the emitter metal deposition step, the three emitter metals were deposited separately. By so doing, the properties of these devices should be identical, except for the emitter metals, allowing a fair comparison between them. The initial current gain of all the MIS BJTs (refer to Fig.,5.1) was very similar, with the Mg devices giving the highest gain of about 650 and both the Al and Ti devices exhibiting gains of about 550. The percentage yield was quite good for the Al and Mg devices, but was poor for the Ti devices. About 70% of the Mg and Al devices on the quarter wafers gave similar gains to the stated values, whereas the yield was only 20% in the case of Ti devices. The relatively low yield for the Ti devices was due to the major loss of interfacial oxide during the Ti metal patterning step. Therefore the temperature stress test on the Ti devices reflects not only the Ti-I-S junction 66 100 -0 o V , . oV , . oV, . o \ 0 <j\ . o\ . . oV . . Temperatures and durations of stresses. Fig. 5.1. Degradation of current gains for the GT—G series device? 67 stability but also the suitability of the fabrication process. The Gummel plots for GT-G series MIS BJTs with the three different metals after various stages of temperature stressing, are shown in Fig. 5.2 to 5.4. The large base current at low bias, with ideality factor being close to 2 for this batch of devices suggested that the relatively low gains could be due to large emitter / base space-charge region recombination. Two mechanisms which might be responsible for this large recombination current are: insufficient annealing of the base implantation leading to short carrier lifetime, and emitter metal penetration through the thin oxide leading to an increase in surface states. These two mechanisms would also account for the relatively low current gains for these devices. Three devices from each quarter wafer were monitored throughout the stress sequence, while other devices were randomly checked in order to ensure that the degradation of the devices was not local. The measured current gains of the three devices with the highest initial gain for the three different metallizations are shown in Fig 5.1. The current gains of the rest of the devices on the same quarter wafer also degraded with the same trend. 68 V B E (v) Fig. 5.2. Gummei plots for Mg-I-Si transistor 69 V B E (V) Fig. 5.2. Gummei plots for Mg-I-Si transistor 70 V B E (V) Fig. 5.2. Gumme i plots for M g - I - S i transistor / 1 Physical degradation of the Mg-I-S and Ti-I-S devices was also observed. The Mg emitter changed from a light greyish colour to dark brown and the texture of the metal changed from small uniform grains to large non-uniform grains, when the stress temperature was increased to around 200°C. The Ti emitter metal changed from black to a reddish colour when the stress temperature was around 200°C. The principal manifestation of degradation in all three MIS BJTs was an increase in base current with increasing temperature stress. However, the collector currents were virtually unchanged during moderate stress until the base currents were comparable to the collector currents. Further stressing on the devices, showed gradual loss of transistor action, as the base currents continued to rise and the collector currents began to decrease. * 5.3. Comparison o£ Mg and Polysilicon devices A number of the GT-J series wafers, with implant dosage of either 1x1012cm~2 or 5xl012cm~2 with both Mg and Al metalizations were fabricated to try to optimize the MIS BJT performance. It was found that the better MIS BJTs were those that had the lower implant dosage and Mg metalization, as expected. The GT-J series wafers also had a set of polysilicon emitter transistors available adjacent to the 72 MIS BJTs on the same wafers. This enabled the study of the effect of different emitters on otherwise identical devices. The highest gain devices for this set of wafers were the Mg devices; they showed gains of the order of 3,500. The polysilicon devices gave gains of 3,000 and the best gainfor the Al devices was 1500. The percentage yield for this batch of devices were very good. The yield of the devices on the wafers having gains in the same order of magnitude for all three different emitter devices was close to 90%. The log(J) vs V B E curves (shown in Fig.5.5 & 5.6) for both the Mg devices and polysilicon devices were almost identical initially, with the Mg devices having a slightly larger base recombination current at low bias. However, Mg devices seemed to have higher maximum gain at optimal bias, while polysilicon devices had a more consistent gain throughout the operational bias range. The devices were left at room temperature in an atmospheric environment for 1 week, and then the device characteristics were measured again. No change in device characteristics was observed, showing that the MIS BJTs were quite stable in room temperature. However, after the devices were heat treated at 200°C for 1 hour, the Mg devices showed the same degradation mode as the previous batch of MIS BJTs. The Mg metalization changed from a light greyish color to 73 VBE (V) Fig. 5.5. Gummel plots for GT-J series Mg-l-SI transistor 74 VBE (V) Fig. 5.6. Gummel plots for GT-J series polysilicon emitter transistor 75 dark brown with large non-uniform grains. The current gain of the Mg devices degraded to essentially zero due to a large increase in the base current at low bias. Whereas the polysilicon device characteristics were virtually unchanged by the temperature stress, except for a slight increase in base current at large base-emitter bias. After the polysilicon devices were stressed at 400°C for 1 hour, the polysilicon devices were all dead. The log(J) vs VDri curve BE (Fig 5.6.) showed a short-circuit in base-emitter junction, and the collector current was essential zero. The base-collector junctions for both Mg-I-S and polysilicon devices were checked to ensure that the degradati on mode of the devices was entirely due to effects at the base-emitter junctions. The log(j ) vs Vn curves C CB (Fig 5.7 & 5.8) before and after stress showed good diode characteristics in both devices, while a small increase in J c atJ low bias was observed in the case of Mg-I-S devices. 5.4. Discussion In the case of Mg and Al devices, the base current curves depart from a logarithmic dependency on base-emitter bias in the low bias region after temperature stressing of 200°C for 1 hour and 400°C for ll hours respectively. Attempts were made to simulate the form of these base current-voltage curves with the MIS BJT model. The model 76 V B C (V) Fig. 5.7. Log(Jo) vs V B C curves for Mg—I—Si transistor 77 Vfec (V) Fig. 5.8. Log(Jc) vs VB C curves for polysilicon emitter transistor 78 parameters such as oxide thickness, metal work function, and carrier lifetime in the base region were varied over a set of physically realistic ranges (refer to Fig. 2.3 through Fig. 2.6). Yet, none of the changes in these parameters resulted in the experimentally observed form of the base current. However, the actual results were well described by adding a resistive shunt current component to the base current exhibited by the device prior to any temperature stress. This suggested that temperature stressing of Mg and Al devices leads to gradual replacement of the MIS junction by an ohmic contact. In the case of Al devices, for example, a log(JB) vs V B E curve resulting from the parallel combination of the unstressed junction and a resistance of 3.5 O-cm (shown in Fig. 5.9) gave an excellent fit to the data obtained after stressing at 400°C for 1 Hour. The high contact resistance as compared to 5x10~4 fi-cm2 for typical Al/pSi contacts to silicon with the intrinsic base resistivity used here [22], could be interpreted as indicating that only small areas of the interfacial oxide were penetrated by the metalization. This would suggest that only selected regions, most probably "weak spots" or pinholes were present on the thin interfacial oxide leading to potentially unstable devices. Metal penetration through the insulating oxide and partially into the base region is further suggested by the observation of increasing collector-base recombination current at low bias in the 79 V B E ( V ) Fig. 5.9. The effect of shunt resistance on Al—I—Si transistor log(Jc) vs V C B curve as the temperature stressing increased. Metal penetrated into the base region would cause an increase in majority carrier concentration, leading to higher recombination current at low bias. In the case of Ti devices, the log(JB&Jc) vs V B E curves did not show a gradual replacement of the MIS junction by an ohmic contact. The base current curves did not depart from the logarithmic dependency on base-emitter bias at low values, but the extrapolated saturated current density at zero VfiE increased with increasing stress. The ideality factors for these set of base currents were all very close to unity, showing that the MIS junction was gradually shifting from a minority carrier dominated junction to one that was dominated by majority carriers without becoming an ohmic contact. A major decrease in collector current after stress complemented the above observation, since the collector current is determined by the minority carrier injection current. This degradation mode can be well described by penetration of Ti through the interfacial oxide. The combination of the work function of Ti and the intrinsic base doping density will cause a Schottky barrier when the metal is in contact with the base, whereas in the case of Mg and Al, although having similar work functions, these metals are good doping materials which would result in formation of an ohmic contact when in contact with the 81 p-type base at high temperature. The extrapolated saturation current density was 5.7x10~7 A/cm2 after a stress of 265°C for 3 hours, whereas the Ti/pSi Schottky barrier junction would have a saturation current density of 1.7X10~4 A/cm2 with barrier height of 0.6leV [23], showing that, either the junction did not completely reduce to a Ti/pSi Schottky barrier or only small areas of the oxide were penetrated by Ti to form Schottky barriers. The degradation mode cannot be easily determined, but the latter one mentioned would seem to be more likely, since it is consistent with the interpretation of the results for the Mg and Al devices. The rapid degradation of the polysilicon devices is due to the overlaying metal that was used to reduce contact resistance to the polysilicon emitter. It is not indicative of an intrinsic device failure mode since the devices were treated to temperatures of 500°C during processing before metal?deposition, but no loss in performance was observed. The metal used for this experiment were either Mg or Al, both of which are acceptor impurities in doping Si. Penetration of these metals at high temperature stressing will cause the n+ doped polysilicon emitter to gradually become p-type, hence shorting the base-emitter junction. Since the diffusion constants for these dopants are quite high for polysilicon [24], the device tends to degrade rapidly at high temperature stress, while remaining stable lower temperature stress. •J 83 Chapter 6 Series resistances measurement As discussed in Chapter 1, a potential drawback to the use of MIS BJTs in high speed applications is the presence of a thin insulating layer in the emitter current path. Because high gains are possible with MIS BJTs, some of this gain can be traded-off against the base series resistance. Reduction of this resistance means that the emitter series resistance can become the dominant resistance limiting the high-speed performance of the transistor. It is not easy to obtain an accurate measure of the emitter resistance. However some attempts to measure R E in MIS BJTs were made and are reported in this chapter. 6.1. Methods of measurement The re are two commonly used methods of determining the series resistances of bipolar transistors. They are the open collector method [25] and the method proposed by Ning and Tang {14]. Both of these methods were used to try to determine the effective series resistance of the thin tunneling oxide. However, the first method will only yield the emitter series resistance, whereas the Ning and Tang method will yield both the emitter and base series resistances. 6.1.1. Open collector method 84 This method is based on measuring the voltage across the emitter and collector contacts as a function of base current injected from a current source. The HP4145 parameter analyzer was setup to perform such a measurement, and the resulting V C E vs Ig curves for both Mg and Polysilicon devices are shown in Figs. 6.1 and 6.2 respectively. It was found that neither of the V„„ vs I B curves was perfectly linear. The slope at low current is slightly greater than that at high current. This is partially due to the nature of the method of measurement, since it has neglected the base conductivity modulation effect, and partially due to the non-linear nature of conduction in the thi n insulator. The estimated emitter series resistance for 2 the 10xl0Mm Mg and Polysilicon devices ranged from 90 to 120 fl and 75 to 95 fl respectively. 6.1.2; Ning and Tang method The Ning and Tang method [14] relies on the fact that IB & IC v s VBE c u r v e s f o r a n ideal bipolar transistor without any series resistance and high injection effects are strictly proportional to exp(qVBE/JcT) . Any deviation from the ideal I B Q and I C Q curves at high bias is assumed to be caused by either the emitter or base series resistances. The deviation in I R can be expressed by: 85 lB (mA) Fig. 6.1. VQ£ VS lg curves for Mg- I -S i transistor IB (mA) Fig. 6.2. VQ£ VS lg curves for polysilicon transistor 87 W ^ = " P ^ ^ E 1 ^ + :BRbi + IB Rbx ) / k T ) ( 6' 1 ) Where Rg is the emitter series resistance, R b x is the extrinsic base series resistance, and Rb- is the intrinsic base resistance. These series resistance components are shown in Fig 6.3. Since 0 = Ic/lg, the expression (6.1) can be rewritten as (kT/qIc) In (IB0/IB) = (Re + Rbi/0) + (RE + Rbx } /' (6'2> The term Rfai/0 can be treated as a constant, since Rfai can be shown to be proportional to 0 at all current levels [26]. When (kT/qIc) ln(IBO/I0) is plotted against 1/0, the slope of the curve will then be (Rfi + Rfcx) and the Y intercept will be (Re + Rbi/0). However, H b i/0 is generally small and can be neglected in the expression (6.2). Therefore R„ can be evaluated directly from the intercept, while Rfax can be readily evaluated from the slope of the curve. In the actual determination of the series resistance using the Ning and Tang method, values of I_ and I were B C extracted from the log (lB & i c) vs V B £ curves for both the Mg and Polysilicon devices. The l B g values were extrapolated from the values of at V B E = 0.7 V back to V B E = 0V with the assumption of the ideality factor being unity. The (kT/qIc) ln (IBQ/IB) vs 1/0 curves for both types of devices are shown in Fig 6.4 and 6.5. However, these curves show a E o B o H P " R e j R b x * - A A A / V W R b i s n Fig. 6.3. Series resistance components CD a> 89 1/P Rg. 6.4. (kT/qlc)'n(l0Q/lg) vs 1/p curve for Mg-I-Si transistor 90 200 1 8 0 " 160 -140 -E O 120 -6 0 " 40 -2 0 -0 i ) i | i | i | i | i | i | , , , ! , , 0.00 0.01 0.02 0.03 0.04 0.05 1/P Fig. 6.5. (kT/qlcJlnOgc/lB) vs 1/p curves for polysilicon transistor 91 negative slope while the intercepts were at around 115 fi for the Mg devices and around 75 fi for the Polysilicon devices. The intercept values representing the series emitter resistances R E agree well with the results of the open collect or method, but the negative slope would mean that the extrinsic base series resistances was negative! The effective negative base series resistances were due to the fact that dependence of l B on V B E, at high bias for the devices under test, was exponential instead of the ideal linear dependence. 6.2. Discussion The absence of a linear lB, V B E at high bias means that the Ning and Tang method is not helpful in estimating the series resistance of the BJTs used in this work. However, the open collector results appear to be reasonable. The specific contact resistivities for the Mg and Polysilicon devices were around 110 nil-cm2 and 85 M^-cm2 respectively. These values are high compared to conventional bipolar transistors, which have corresponding resistivities of the order of 1 M&-cm . The relatively high series resistances for the MISETs and Polysilicon devices would be a major drawback in implementing these device structures in ' VLSI applications. 92 Chapter 7 Conclusion The main conclusion to be drawn from the work reported in this thesis is that MIS BJT devices have some severe limitations which may prevent their successful implementation in a commercial IC processing technology. The principal drawback to the devices is the degradation of common-emitter current gain at moderate temperatures. Magnesium devices with initial gains in excess of 3000 have been shown to fail completely at temperatures as low as 265°C. Devices with aluminum and titanium metallization continue to act as transistors, but with steadily decreasing current gain, until slightly higher temperatures (around 400°C). For all cases the degradation in gain appears to be due to changing conditions at the emitter/base junction. Shunting of this junction by metal from the emitter penetrating the oxide at thin spots in the oxide is suggested as being a likely cause of the results observed. Another disadvantage of MIS BJTs is the series resistance associated with the thin insulating layer in the emitter tunnel junction. Our measurements of emitter 93 specific resistivity indicate that a reduction by nearly two orders of magnitude is needed for values of this parameter to reach acceptable levels for VLSI applications. It is proposed that the degradtion of MIS BJTs be further investigated. Chemical methods, such as angle-resolved photoelectron spectroscopy, would be very helpful in complementing the electrical measurements reported here. Information on the changing oxide composition with temperature stressing, coupled perhaps with the results of high resolution cross-section transmission electron microscopy, would help confirm or deny whether metal penetration into the oxide is, as suggested in this thesis, responsible for device degradation. I 94 References 1. J.E. Dufill, Plessey Research Ltd., England, private communication, (1986) 2. N.G. Tarr, D.L. Pulfrey and D.S. Camporese, IEEE Trans, on Electron Dev., ED-30, 1760 (1983) 3. M.A. Green and R.B. Godfrey, IEEE Electron Dev. Letters, EDL-4, 225 (1983) 4. M.K. Moravvej-Farshi, W.L. Guo and M.A. Green, IEEE Electron DEV. Letter, EDL-7, 632 (1986). 5. P.C. Hunt, Plessey Research Ltd., England, private communication, (1986) 6. H. Miyanaga, Y. Kobayashi, S. Konaka, Y. Yamamoto and T. Sakai, Proc. VLSI Technology Symposium, 50 (1984) 7. H.K. Park, K. Boyer, C. Clawson, G. Eiden, A. Tang, T. Yamaguchi and J. Sachitano, IEEE Electron Dev. Letters, EDL-7, 658 (1986) 8. M.B. Rowlandson and N.G. Tarr, IEEE Electron Dev. Letters, ED-6, 288 (1985) 9. P. Van Halen and D.L. Pulfrey, IEEE Trans, on Electron Dev., ED-32, 1307 (1985) 10. A. Neugroschel, M. Arienzo, Y. Komen and R.D. Isaac, IEEE Trans, on Electron Dev., ED-32, 807 (1985) 11. Z. Yu, B. Ricco, and R.W. Dutton, IEEE Trans, on Electron Dev., ED-31, 773 (1984) 12. J.R. Black, Proc. IEEE Reliability Physics Symposium, 257 (1977) 13. R.B. Godfrey and M.A. Green, Applied Physics Letters, Vol. 34, 860 (1979) 14. T.H. Ning and D.D. Tang, IEEE Trans, on Electron Dev., ED-31, 409 (1984) 15. A.S. Grove, "Physics and Technology of Semiconductor Devices", New York Wiley, 156-160 (1967) 16. S.M. Sze, "Physics of Semiconductor Devices 2nd Edition", Wiley Appendix H. (1981) 95 17. D.S. Gamporese and D.L. Pulfrey, Journal of Applied Physics, Vol. 57, 373 (1985) 18. A.W. Blakers, M.A. Green, S. Jiqun, E.M. Keller, S.R. Wenham, R.B. Godfrey, T. Szpitalak, and M.R. Willison, IEEE Electron DEV. Letters, EDL-5, 12 (1984) 19. W.Kern and D.A. Puotuien, RCA review, p. 187 (June 1970) 20. D.S. Camporese, Ph.D. Thesis, University of British Columbia, (1986) 21. M.J. Collie, "Etching compositions and processes", Park Ridge, N.J., 73 (1982) 22. H.H. Berger, J. Electrochem. Soc., Vol. 119, 507 (1972) 23. A.M. Cowley, Solid-State Electronics, Vol. 12, 403 ( 1970) 24. B. Swaminathan, K.C. Saraswat, R.W. Dutton and T.I. Kammis, Applied Physics Letters, Vol. 40, 795 (1982) 25. B. Kulke and S.L. Miller, Proc. IRE letters, Vol. 45, 90 (1957) 26. D.D. Tang, IEEE Trans. Electron Dev., ED-27, 563, 1980 96 Appendix A. Fabrication Procedures for the MIS BJTs A.l. Fabrication procedure for MR-20 and GT-G devices 1. Mask oxide growth a) RCA clean b) Oxidation: 1100°C 5 Min. preheat in 0 2 5 Min. push in 0 2 10 Min. dry oxidation in 0 2 20 Min. wet oxidation in 0 2 + H 20 10 Min. dry oxidation in 0 2+ 2% HC1 10 Min. anneal in N 2 5 Min. pull in N 2 10 Min. cool in N 2 Mask oxide thickness - 0.3 urn 2. Open windows for extrinsic base diffusion a) Use mask CU-063-01 with negative photoresist to pattern the windows, negative photoresist was also jused to protect the back of the wafers. b) Etched in buffered HF for approximately 4 Min. until bare silicon exposed. 3. Extrinsic base boron diffusion a) RCA clean b) Predep: 1000°C 5 Min. preheat in 0 2 + N 2 5 Min. push in 0 2 + N 2 5 Min. warm-up in 0 2 + N 2 97 10 Min. dope in °2 + N2 + dopant 10 Min. hold in °2 + N2 5 Min. pull in °2 + N2 10 Min. cool in °2 + N2 c) Boron deglaze: 30 Sec. in 10% HF d) drive-in: 1100°C 5 Min. preheat in °2 5 Min. push in °2 10 Min. dry oxidation in °2 15 Min. wet oxidation in °2 + H2° 5 Min. dry oxidation in 02+2.5% HC1 5 Min. pull in °2 10 Min. cool in °2 Phosphorous backside getter a) Protect wafer fronts with PR, and strip oxide from wafer backs. b) RCA clean c) Predep: 1000°C 5 Min. preheat in °2 + N2 5 Min. push in 0 2 + N2 5 Min. warm-up in °2 + N2 10 Min. dope in 0 2 + N 2 + dopant 5 Min. hold in 0 2 + N2 5 Min. pull in 0 2 + N2 10 Min. cool in 0 2 + N2 d) Phosphorous deglaze: 10 Sec. in 10% HF e) drive-in: 950°C 5 Min. preheat in °2 98 5 Min. push in C>2 5 Min. dry oxidation in C>2 20 Min. wet oxidation in C>2 + H 20 5 Min. dry oxidation in C>2 5 Min. pull in 0 2 tO Min. cool in C>2 5. Open windows for intrinsic base implant a) Use mask CU-063-02 with negative photoresist to pattern the windows, negative photoresist was also used to protect the back of the wafers. b) Etched in buffered HF for approximately 4 Min. until bare silicon exposed. 6. Implant mask oxide growth a) RCA clean b) drive-in: 1000°C 5 Min. preheat in 0 2 5 Min. push in 0 2 30 Min. dry oxidation in 02+2.5% HC1 ' 5 Min. dry oxidation in 0 2 10 Min. hold in N 2 5 Min. pull in 0 2 10 Min. cool in 0 2 7. Intrinsic base boron implant 1 2 - 2 Implant dosage : 1x10 cm Implant energy : 50 KeV 8. Base implant Anneal 99 a) RCA clean b) Anneal: 950°C 5 Min. preheat in N 2 2"/6 Sec. push in N 2 30 Min. anneal in N 2 2B/15 Sec. pull in N 2 10 Min. cool in N 2 9. Open emitter contact windows a) Use mask CU-063-03 with negative photoresist to pattern window. b) Etch in buffered HF for approximatly 40 Sec. until silicon exposed. 10. Open base contact windows a) Use mask CU-063-05 with negative photoresist to pattern window. b) Etch in buffered HF until silicon exposed. 11. Lotox deposition Deposit 0.1 Mm undoped Lotox, using 25% SiH4 and 27.5% 0 2 atJtemperature of 405°C for 6 Minutes. 12. Re-open base contact windows a) Use mask CU-063-05 with negative photoresist to pattern window. b) Etch in buffered HF for approximatly 50 Sec. until silicon exposed. 13. Deposit base contact metal a) Flash dip in 10% HF to remove native oxide from 100 windows b) Deposit 1.0 Mm Al on wafer fronts by e-beam 14. Pattern base contacts a) Use Mask CU-063-06 with Positive photoresist. b) Etch in H3PC>4 at 60°C for approximately 2 Minutes. 15. Base contact anneal Anneal in H 2 at 450°C for 10 Minutes. 16. Deposit protective Lotox layer Deposit 0.2 Mm Lotox using 25% SiH4 and 27.5% C>2 at 405°C for 12 Minutes. 17. Partial RCA clean The HF clean step was moved to the end and the duration was shortened to approximatly 3 Seconds. 18. Deposit back contact Al o Deposit 4000 A of Al on wafer front by evaporation in the CHA chamber with filament current of 35 to 40 amps and o deposition rate of 10 to 20 A/Sec. 19. Gi?ow ultra-thin tunnel oxide Anneal and grow oxide : 500°C 5 Min. warm up in N 2 20 Min. dry grow in 0 2 5 Min. hold in N 2 20. Deposit emitter metal o a) Deposit 3000 A of Al on wafer front by evaporation in the CHA chamber with filament current of 35 to 40 amps o and deposition rate of 10 to 20 A/Sec. for Al-I-S devices. 101 b) Deposit 3000 A of Mg on wafer front by evaporation in the CHA chamber using a "Drummel" type boat with filament current of 60 to 70 amps and deposition rate o of 10 to 20 A/Sec. for Mg-I-S devices. o c) Deposit 3000 A of Ti on wafer front by evaporation in the CHA chamber with filament current of 90 to 100 o amps and deposition rate of 2 to 5 A/Sec. for Ti-I-S devices. 21. Pattern emitter metal a) Use Mask CU-063-08 with Positive photoresist. b) Etch in 50% H 3P0 4 at 60°C for approximately 2 Minutes for Al emitter. c) Etch in 0.1% HNC>3 at 25°C for about 5 Minutes for Mg emitter. d) Etch in 1% HF at 25°C for about 5 Minutes for Ti emitter. A.2. Fabrication procedure for GT-J series devices 1. Ma^k oxide growth a) RCA clean b) Oxidation: 1100°C 5 Min. preheat in 0 2 2"/6 Sec. push in 0 2 10 Min. dry oxidation in 0 2 20 Min. wet oxidation in 0 2 + H 20 10 Min. dry oxidation in 0 2+ 2% HC1 10 Min. anneal in N 2 2"/l 5 Sec. pull in N 2 102 10 Min. cool in N2 Mask oxide thickness 0.3 Mm Open windows for extrinsic base diffusion a) Use mask CU-078-01 with negative photoresist to pattern the windows, negative photoresist was also used to protect the back of the wafers. b) Etched in buffered HF for approximately 4 Min. until bare silicon exposed. Extrinsic base boron diffusion a) RCA clean b) Predep: 1000°C 5 Min. preheat in 0 2 + 2"/6 Sec. push in 0 2 + N 2 5 Min. warm-up in 0 2 + N2 10 Min. dope in ° 2 + N2 + dopant 10 Min. hold in 0 2 + N 2 2"/l5 Sec. pull in 0 2 + N 2 10 Min. cool in 0 2 + N 2 c),Boron deglaze: 30 Sec. in 10% HF d) drive-in: 1100°C 5 Min. preheat in 0 2 2"/6 Sec. push in 0 2 15 Min. dry oxidation in 0 2 15 Sec. pull in 0 2 10 Min. cool in 0. 2 Mask oxide growth a) 10 Sec. dip in 10% HF to remove any contamination from Boron drive-in tube. 103 b) Oxidation: 1100°C 5 Min. preheat in 0 2 2"/6 Sec. push in 0 2 15 Min. wet oxidation in 0 2 + H 20 5 Min. dry oxidation in 02+2.5% HC1 5 Min. anneal in N2 2"/l5 Sec. pull in N 2 10 Min. cool in N 2 Phosphorous backside getter a) Protect wafer fronts with PR, and strip oxide from wafer backs. b) RCA clean Predep: 1000°C 5 Min. preheat in °2 + N2 2"/6 Sec. push in 0 2 + N2 5 Min. warm-up in °2 + N2 10 Min. dope in 0 2 + N2 + dopant 5 Min. hold in 0 2 + N2 2"/l 5 Sec. pull in 0 2 + N2 10 Min. cool in 0 2 + N2 Phosphorous deglaze: 30 Sec. in 10% HF drive-in: 950°C 5 Min. preheat in °2 2"/6 Sec. push in 0 2 30 Min. dry oxidation in °2 2B/15 Sec. pull in 0 2 10 Min. cool in 0 2 Open windows for intrinsic base implant 1 04 a) Use mask CU-078-02 with negative photoresist to pattern the windows. negative photoresist was also used to protect the back of the wafers. b) Etched in buffered HF for approximately 3 Min. until bare silicon exposed. 7. Implant mask oxide growth a) RCA clean b) drive-in: 1000°C 5 Min. preheat in 0 2 2"/6 Sec. push in 0 2 5 Min. dry oxidation in 0 2 30 Min. dry oxidation in 02+2.5% HC1 10 Min. anneal in N 2 2"/l5 Sec. pull in 0 2 10 Min. cool in 0 2 8. Intrinsic base boron implant Implant dosage : 1x1012 cm - 2 Implant energy : 30 KeV 9. PSG deposition Deposit PSG using 8.2% SiH4, 20.2% SiH4/PH3 and 27.5% 0 2 for 10 Minutes, and the thickness was approximatly 0.25 Mm. 10. Base implant Anneal a) RCA clean b) Anneal: 627°C 5 Min. preheat in N 2 2"/6 Sec. push in N 2 105 60 Min. anneal in N 2 2"/l5 Sec. pull in N 2 10 Min. cool in N 2 c) Anneal: 950°C 5 Min. preheat in N 2 2"/6 Sec. push in N2 30 Min. anneal in N 2 2B/15 Sec. pull in N2 10 Min. cool in N2 11. Open emitter contact windows a) Use mask CU-087-03 with negative photoresist to pattern window. b) Etch in buffered HF for approximatly 1.5 Min. until silicon exposed. 12. Deposit first emitter polysilicon a) RCA clean without HF etch. b) Perform HF dip etch immediately before deposition. c) Deposit polysilicon using 19.4% SiH4 and 15% SiH4/PH3 I for 55 minutes and the resulting thickness was o approximatly 1000A. 13. Pattern first polysilicon a) Using mask CU-078-04 with positive photoresist. b) Etch in wet poly etch. 14. Open base contact windows a) Use mask CU-078-07 with negative photoresist to pattern window. 106 b) Etch in buffered HF for approximatly 4 Min. until silicon exposed. 15. Deposit base contact metal a) Flash dip in 10% HF to remove native oxide from windows b) Deposit 1.0 Mm Al on wafer fronts by e-beam 16. Pattern base contacts a) Use Mask CU-078-08 with Positive photoresist. b) Etch in H3PC>4 at 60°C for approximately 2 Minutes. 17. Base contact anneal Anneal in H 2 at 450°C for 10 Minutes. 18. Deposit protective Lotox layer Deposit 0.2 Mm Lotox using 25% SiH4 and 27.5% 0 2 at 405°C for 12 Minutes. 19. Re-open first emitter window a) Use mask CU-078-03 with negative photoresist. b) Etch in siloxide etchant until polysilicon exposed. 20. Open second emitter window a) Use mask CU-078-05 with negative photoresist. b) Etch in siloxide etchant until bare silicon exposed. 21. Partial RCA clean 10 Second dip in 10% HF to remove any native oxide on the emitter window. 22. Deposit back contact Al o Deposit 4000 A of Al on wafer front by evaporation in the CHA chamber with filament current of 35 to 40 amps and 107 o deposition rate of 10 to 20 A/Sec. 23. Grow ultra-thin tunnel oxide Anneal and grow oxide : 500°C 5 Min. warm up in N 2 20 Min. dry grow in 0 2 5 Min. hold in N 2 24. Deposit emitter metal o a) Deposit 3000 A of Al on wafer front by evaporation in the CHA chamber with filament current of 35 to 40 amps o and deposition rate of 10 to 20 A/Sec. for Al-I-S devices. o b) Deposit 3000 A of Mg on wafer front by evaporation in the CHA chamber using a "Drummel" type boat with filament current of 60 to 70 amps and deposition rate o of 10 to 20 A/Sec. for Mg-I-S devices. 24. Pattern emitter metal a) Use Mask CU-078-09 with Positive photoresist. b) Etch in 50% H3PC>4 at 60°C for approximately 2 Minutes lfor Al emitter. c) Etch in 0.1% HN03 at 25°C for about 5 Minutes for Mg emitter. Appendix B. Software listing for the HIS BJT Model ct> © Listing of MISBJT.S at 11:24:09 on MAY 15. 1988 for CCid=NSZE on G 1 C PROGRAM MIS 2 C WRITTEN BY GARRY TARR SPRING 1982 3 C LAST REVISION JUNE 7 1982 4 C 5 C MODIFLIED BY NGAM SZETO FALL 1986 6 C LAST REVISION NOV 3 1986 7 C 8 C 9 IMPLICIT REAL * 8 (A-Z) 10 INTEGER CNTRL 1 ,DATFl,FDFL ,FREE, I, IAONR, IFAIL , ITMAX1 , ITMAX2.KR, 11 » LABEL,LP,MIN0.NT1MES.NIRAP 12 LOGICAL NEWY,NEWA,NEWB 13 EXTERNAL COMPF 14 C '5 OIMENSION NT( 100) ,RHO( 100) ,NI( 100) .PK 100) ,SIGMAN( 100) , 18 » SIGMAPI 100) ,CN< 100) ,CP( 100) ,IADNR( 100) ,TAUM( 100) 17 DIMENSION ACCESTI2),X(2),F(2) 18 DIMENSION FREE(1),LABEL(15) '9 DIMENSION FDFL A (81), FDFLC (81), FDFLE( 8 1) , FDFLF( 81), FDFLG (81) 20 C 21 COMMON /AREA1/ CBAR , CBCM. CBVM, CCM, CVM, CHISC , CHISV , CJCM, 22 # C JVM, CPSII, CQS, CTNLCM,CTNLVM, EGAP, EG API , 23 t NC,NA,ND,NI , NNO , NV , 0, PHIO, PNO , 24 I PSISIO,VTHERM, WB,TP,TN,DN,DP,EPSIS 25 COMMON / AREA2/ NT , RHO, N1 . P 1 , CN, CP . TAUM. IADNR , NTRAP 26 COMMON /AREA3/ ETAC , ETAMC, ETAMV , ETAV, JVM.NSURF , PHI, PSII, PSIS . 27 * PSURF , QS, THVM, THCM, U, VBE. VCE . JNO, JNWB , JREC 28 COMMON /AREA4/ CNTRL1,ITMAX1,LP,NTIMES 29 COMMON /AREA5/ CFD1. FDFL A, FDFLC , FDFLE, FDFLF, FDFLG 30 COMMON /SE$$0M/ A(20,22),B(20),Y(22, 2 1) 31 C 32 DATA EPSI0/8.85D -12/,HBAR/ 1.054D-34/.KB0LTZ/1.38054D-23/, 33 f KS/1 1 . 700/,ME/9. 110-31/,PI/3. 14592654D0/, 34 t T/300.000/,VELTH/1.005/ 35 DATA FDFL/2/,DATFL/3/,KR/5/.FREE/'*'/ 36 DATA NEWY/. TRUE./.NEWA/. FALSE./, NEWB/. FALSE./ 37 C 38 C 39 C READ IN DATA DESCRIBING DEVICE 40 C 41 READIKR,5) (LABEL(I),1 = 1,15) 42 5 FORMAT*15A4) 43 READ(KR.FREE) ITMAX1,1TMAX2,ERR 1,ERR2,DELY 44 READIKR,FREE) CNTRL1 45 C 46 READ(OATFL.FREE) NA, ND. CHISC, PHIM,MISTAR,D, KI, NCONV , AE , AH 47 READ(DATFL,FREE) WB.TP.TN 48 DO 100 1=1,100 49 READ(DATFL.FREE) RHO(I) ,NT(I),SIGMANII) , SIGMAPI I), TAUM( I) , I ADNR (I) 50 IF(NT{I) .LE. O.ODO) GOTO 200 51 100 CONTINUE 52 200 NTRAP=I- 1 53 C 54 READ (FDFL. FREE) (FDFLF (I), FDFLA (I), FDFLC (I), FDFLE (I) , 55 t FDFLG(I),1=1,81) 56 C 57 C ECHO PRINT 58 C Listing of MISBJT.S at 1 1:24:09 on MAY 15, 1986 for CCid=NSZE on G 5 9 WRITEILP.10) (LABEL(I).1=1,15) 60 6 1 62 10 FORMAT(' 1 * , 20X , 15A4///) WRITEdP, 15) NA,NO,CHISC,PHIM,MISTAR,O.KI,NCONV 15 F0RMATI1X, 'NA=' ,010.3,2*,'ND='.D10.3.2X, 'CHIS=',F5.3 2X 'PHIM=' " »F5.3,2X, 'MISTAR=' ,F5.3,2X, ' 0= ' .D10.3.2X, 'KI = ' ,F5 2 2X 64 »'NC0NV=',F7.5/) 6 5 WRITE(LP,20) KB,TP,TN.AE.AH 66 20 FORMAT(1X,'WB=\D10.3,2X.'TP=\D10.3,2X,'TN='.D10.3,2X 6 7 *'AE=',010.3,2X,'AH=',010.3,2X//) 68 IF(NTRAP .EQ. 0) GOTO 400 69 WRITE(LP,25) 70 25 FORMAT( 2X ,'I:',3X,'ETA:',5X,'NT:',7X, • SIGMAN : *. 5X . ' SIGMAP: ' , 7 1 #5X, 'TAUM:',5X,'IADNR:'/) DO 300 1=1.NTRAP 73 300 WRITEdP,30) I , RHO( I) , NT( I) , SIGMAN (I) , SIGMAP( I) , TAUM( I) IAONR(I) 74 30 FORMAT( 1X , 13 , 2X . F5. 3, 2X , D10. 3, 2X, 3(D10 . 3, 2X) , 12) 75 WRITEILP,35) 76 35 FORMAT!///) 77 C 78 r 79 C NORMALIZE POTENTIALS TO KBOLTZ*T/Q AND COMPUTE CONSTANTS 80 C 81 400 VTHERM=KB0LTZ'T/0 8 2 CTUNL=2. OOO'DSQRT ( 2 . 000•ME) /HBAR'DSQRT (Q) 83 CFD1=PI* PI/6.000 84 EPSIS=KS*EPSIO 85 EPSII=KI'EPSIO 8 6 NC=NI'DEXPL(EGAP/(2.0D0'VTHERM) )*OSQRT(NCONV) 8 7 NV=NI*DEXPL(EGAP/(2.0D0*VTHERM))/0SQRT(NC0NV) 8 8 EGAPI=EGAPI/VTHERM 89 EGAP=EGAP/VTHERM 90 CHISC=CHISC/VTHERM 91 CHISV=EGAPI-CHISC-EGAP 92 PHIM=PHIM/VTHERM 93 C 94 CBCM=EGAPI-2.0D0*CHISC 95 CCM=CHISC-(EGAPI-CHISC) 9 6 C TNL CM=-CTUNL*D*DSQRT(CCM* MI STAR/EGAPI'V THERM) 97 C 9S CBVM=2.ODO'CHISV-EGAPI 99 CVM=CHISV"(EGAPI -CHISV) 1 0 0 CTNLVM=-CTUNL*D*DSQRT( CVM'MISTAR/EGAPI'VTHERM) 1 0 1 c '02 NNO=NA '03 PNO=NI*NI/NA 104 PHIO=DLOG(NC/NA) 105 PSISI0=D10G(NA/PN0) 106 CJVM=AH*T*T 107 CJCM=AE'T'T 108 CBAR=PHIO+CHISC-PHIM 109 CPSII=D/EPSII/VTHERM 1'0 CQS=DSORT(2.ODO'KBOLTZ* T"EPSIS) 111 IFINTRAP .EQ. 0) GOTO 800 112 00 500 1=1,NTRAP 113 RHO(I)=RHO(I)/VTHERM 1 M CN(I)=SIGMAN(I)'VELTH 115 CP(I)=SIGMAP(I)'VELTH 116 NI(I)=NC*DEXPL (RHO(I)-EGAP) Listing of MISBJT.S at 11:24:09 on MAY 15. 1988 for CCid=NSZE on G " 7 500 P1(I)=NV"DEXPL( -RH0( I) J 118 C 1 19 C 120 C READ IN VOLTAGE V ANO A STARTING ESTIMATE FOR PHI 121 C 122 600 READ(KR,FREE,END=1400) VBE.VCE.PHI >23 V8E=VBE/VTHERM 124 VCE=VCE/VTHERM 125 PHI=PHI/VTHERM 126 C 127 U=VBE-PHI 128 C GIVEN PHI, COMPUTE A STARTING ESTIMATE FOR PSIS 129 CALL FPSIS 130 C 131 C CALL SSM TO FIND A SOLUTION FOR THE COUPLED POTENTIAL 132 C AND HOLE CURRENT CONTINUITY EQUATIONS 133 C 134 NTIMES=0 135 X(1)=U 136 X(2)=PSIS '37 DO 700 1=1,3 138 Y(1,I)=U 139 Y(2,I)=PSIS 140 700 Y(I,I)=Y(I,I)+DELY 141 NEWY=.TRUE. 142 CALL SSM( X ,F, 2.0. ERR 1. ITMAX2, COMPF, NEWY, NEWA ,NEWB, IFAIL , &800) 143 800 U1=X(1) 144 PSIS1=X(2) 145 NEWY=.FALSE. 148 C CALL SSM AGAIN TO OBTAIN AN ESTIMATE OF THE ERROR IN THE SOLUTION 147 CALL SSMI X,F, 2,0.ERR2,1TMAX2, COMPF, NEWY, NEWA, NEWB, IFAIL,&900) 148 C 149 C PREPARE FOR OUTPUT OF RESULTS 150 C 151 900 U=X(1) 152 PSIS=X(2) 153 PHIER=DABS(U-U1)'VTHERM 154 PSISER=DA8S(PSIS-PSIS1)'VTHERM 155 PHI=VBE-U 156 UO=U* VTHERM 157 C 158 CALL FQS 159 C 160 JVT=O.ODO 161 JCT=0.ODO 162 JMT=O.ODO 163 QSS=0.ODO 164 IFtNTRAP .EQ. 0) GOTO 1300 <65 CVALEN=PHIO-EGAP+PSIS 166 DO 1200 I=1,NTRAP '67 ZETA=CVALEN+RHO(I)+V 168 FM=1.0DO/d.ODO+DEXPL(2ETA)) 169 FTNUM=NSURF • CN(I) *P 1 (I) • CP(I) »FM/TAUM( I) 170 FTDNM= (NSURF+N1 (I)) • CN (I) • (PSURF»P 1 (I)) * CP (I) +1. OOO/TAUM! I) 17 1 FT=FTNUM/FTDNM '72 IF(IADNRtl) .EQ. 1) GOTO 1000 173 QSS=QSS-FT'Q*NT(I) '74 GOTO 1100 Listing of M I S B J T . S at 11:24:09 on MAY 15. 1988 for CCid=NSZE on G 175 1000 QSS=QSSM I.ODO-FT)'Q-NT(I) 77 ^^ Q^'NT'K'CPtnMPSURF'FT-PKII-d.OOO-FT)) 7n J C T= J CT+Q'NT(I)'CN(I)'(NSURFM1.0D0-FT)-N1(I)'FT) 179 1300 PSII=CPSII • (QS+QSS) 180 c 1 8 1 ETAMC=-(PHIO*PSIS+VBE) 1 8 2 ACM=-PSII*PSII '83 BCM=PSII"CBCM THCM^DEXPL^CTNLCM^CORFCTt^^^^ 000-BCM*BCM/24. OOO/CCM) /CCM EXCHANGE THE TWO TUNNELING CURRENT COMPONENTS 184 185 JCM=CJCM"THCMMFD HETAC) -FD1 (ETAMC) ) Io / C '88 CALL FJVM 189 C 190 CALL FJBASE 191 C 192 C 193 C 194 TEMP=JCM 195 JCM=JVM 196 JVM=TEMP 197 TEMP=JCT 198 JCT=JVT 199 JVT=TEMP 200 C 201 JRE=JNO-JNWB 202 VCB=VBE-VCE 203 WC8=DSQRT( 2 • EPS IS/Q • (ND+NA) / (ND • NA) * (0. 7 - VCB • VTHERM)) zo,1 JGEN=Q*NI *WCB/DSQRT(TN'TP) 2 0 5 JCBP=Q'DP" NI 'NI/OSQRT (OP * TP) /ND 2 0 6 JE=JCM*JVM*JMT 2 0 7 JC=JNWB+JG6N+JCBP 208 JB=JE-JC 2°9 HFE=(JC-JCBPJ/JB 2 1 0 c 211 UO=U"VTHERM 2 1 2 VBEO=VBE-VTHERM 2 , 3 VCEO=VCE*VTHERM 2 i 4 PHIO=PHI 'VTHERM 21 ^  PSISO=PSIS'VTHERM 2 . 6 PSIIO=PSII-VTHERM 2 . 7 WRITE(LP,40) VBEO,VCEO,IFAIL 218 40 FORMAT(1X,'VBE=',F8.5,3X,'VCE=',F8.5,3X,'IFAIL=' 14/) 2 1 9 WRITE(LP,45) UO.PHIO.PHIER.PSISO.PSISER.PSIIO 220 45 F0RMAT<1X,'U=',D14.7,2X,'PHI = ',D14.7,2X,'<PHIER=',D10.3 •)• 2X H I #'PSIS=' ,014. 7 , 2X, ' (PSISER=' ,D10.3, ') ' t2X, 'PS 11 = ' ,014.7/) 2 2 2 WRITEILP.50) PSURF.NSURF.ETAC.ETAV,ETAMC,ETAMV 223 50 FORMAT(1X.'PSURF=',D14.7,2X,'NSURF='.D14.7,2X,'ETAC=' FB 4 2X H i #'ETAV=' .F8.4.2X, 'ETAMC=' .F8.4.2X, 'ETAMV=' ,F8.4/) 225 WRITE(LP,55) JCM,JVM,JCT,JVT,JMT 226 55 FORMATt IX, ' JCM=' ,011 . 4 , 2X . ' JVM=' .011.4.2X,' JCT=' ,D11.4 2X 2 2 7 •' JVT=' ,011. 4 , 2X , ' JMT=' .D11.4.2X/) 2 2 8 WRITE(LP,60) THCM.THVM 229 60 FORMAT(1X,'THCM=', D11.4,2X,'THVMa' ,011.4/) 2 3 0 WRITEtLP,70) JE.JB.JC.HFE III 7 0 wottcI/2* ' ' >011.4,2X, ' JB=' .011.4.2X, ' JC=* ,011.4,2X, 'HFE=' ,011.4/) 2 3 2 WRITE1LP,71) JNO,JNWB,JRE,JGEN,JCBP,JREC Listing of MISBJT.S at 11:24:09 on MAY 15. 1988 for CCid=NSZE on G 233 7 1 FORMATOX, 'JN0=' .011.4,2*. 'JNWB=' ,011 .4. 2X, 'JRE=' ,011.4 2X 2 3 4 * 'JGEN=',011.4/,1X.•JCBP=',011.4,2X,1JREC=',D11.4////) 235 C 236 GOTO 600 237 C 238 C 239 1400 STOP 240 END 241 BLOCK DATA 242 C 243 IMPLICIT REAL'S (A-Z) 244 INTEGER CNTRL1.ITMAX1,LP.NTIMES 245 C 246 COMMON /AREA1/ CBAR,CBCM,CBVM,CCM,CVM,CHISC,CHISV,CJCM, 247 » CJVM,CPS11,CQS,CTNLCM,C TNLVM.EGAP,EGAPI, 248 * NC.NA.ND,NI.NN0,NV,Q,PHI0,PN0, 249 I PSISIO,VTHERM,WB,TP,TN.DN,DP,EPSIS 250 COMMON /AREA4/ CNTRL1,ITMAX1,LP.NTIMES 251 C 252 DATA EGAP/1.07988245600/,EGAPI/8.000/,Q/1.60210-19/,LP/6/ 253 #,ON/3.878D-1/,DP/1.1640-1/,NI/1.45016/ 254 C 255 END 256 SUBROUTINE COMPF(X,F) 257 C 258 C THIS ROUTINE COMPUTES THE RESIDUE OF THE POTENTIAL AND 259 C HOLE CURRENT CONTINUITY EQUATIONS 260 C 261 IMPLICIT REAL'S (A-Z) 262 INTEGER CNTRL1.I.IADNR.ITMAX1,LP.NTIMES.NTRAP 263 C 264 DIMENSION X(2).F(2),TAUM(100),RHO(100). 265 # NT<100),CN(100),CP(100),N1( 100),P1(100),IADNR(100) 266 C 267 COMMON /AHEA1/ CBAR,CBCM,CBVM,CCM,CVM,CHISC,CHISV,CJCM, 268 # CJVM.CPSII,CQS,CTNLCM,CTNLVM,EGAP,EGAPI, 269 # NC,NA,ND,NI,NNO,NV,Q,PHIO,PNO, 270 I PSISIO,VTHERM,WB,TP,TN.DN,DP,EPSIS 271 COMMON /AREA2/ NT,RHO,N1,PI.CN,CP,TAUM.IADNR.NTRAP 272 COMMON /AREA3/ ETAC,ETAMC,ETAMV.ETAV,JVM,NSURF,PHI,PSII,PSIS, 273 I PSURF,QS,THVM,THCM,U,VBE,VCE.JNO,JNWB,JREC 274 COMMON /AREA4/ CNTRL1,ITMAX1,LP.NTIMES 275 C 276 NTIMES=NTIMES+1 277 U=X(1) 278 PHI=VBE-U 279 PSIS=X(2) 280 C 281 CALL FQS 282 C 283 QSS=0.ODO 284 JVT=0.ODO 285 IF(NTRAP .EQ. 0) GOTO 300 286 CVALEN=PHI0-EGAP+PSIS 287 DO 200 1=1,NTRAP 288 ZETA=CVALEN+RHO(I)+V 289 FM= 1.000/ (1. ODO+DEXPL (ZETA)) 290 FTNUM=NSURF • CN (I) +P1 (I)" CP (I) *FM/TAUM( I) Listing of MISBJT.S at 11:24:09 on MAY 15. 1988 for CCid=NSZE on G 29 1 FTDNM= (NSURF+N 1(I))*CN(I)+( PSURF+P 1CI > ) * CP (I) + 1 . 0D0/TAUM( I) 292 FT=FTNUM/FTDNM 293 IF(IADNR(I) .EQ. 1) GOTO 100 294 QSS=QSS-FT"Q'NT(I) 295 GOTO 200 288 100 QSS=QSS+(1.ODO-FT)*Q*NT<I) 297 200 JVT=JVT+Q'NT(I)*CP(I)*(PSURF*FT-P1(I)* <1. ODO-FT)) 268 c 299 300 PSII=CPSII*(QS+QSS) 300 F(1)=CBAR+VBE+PSIS*PSII 301 c 302 CALL FJVM 303 CALL FJBASE 304 F(2)=JVM-JNO-JREC-JVT 305 c 306 IF(CNTRL1 .EQ. 0) GOTO 400 307 U0=U * VTHERM 308 PSISO=PSIS*VTHERM 309 WRITE(LP,5) NTIMES,UO,PSISO,F(1),F(2) 310 5 FORMAT!1X,13,2X.D23.16,2X,D14.7.2X,2(014.7 . 2X)) 311 c 312 400 RETURN 313 END 314 SUBROUTINE FQS 315 C 316 C THIS ROUTINE COMPUTES THE CHARGE QS STORED ON THE SEMICONDUCTOR 317 C 318 IMPLICIT REAL * 8 (A-Z) 319 INTEGER CNTRL1,1TMAX1,LP,NTIMES 320 C 321 COMMON /AREA1/ CBAR , CBCM, CBVM, CCM. CVM, CHISC , CHISV, CJCM. 322 # C JVM, CPSII ,CQS, CTNLCM, CTNLVM, EGAP.EGAPI, 323 # NC, NA ,ND ,NI, NNO, NV ,Q, PHIO ,PNO, 324 * PSISIO, VTHERM, WB, TP, TN,DN,DP,EPSIS 325 COMMON /AREA3/ ETAC , ETAMC. ETAMV . ETAV, JVM.NSURF,PHI. PSII, PSIS, 328 » PSURF, QS, THVM, THCM, U, VBE, VCE , JNO, JNWB, JREC 327 COMMON /AREA4/ CNTRL1,ITMAX1,LP.NTIMES 328 C 329 PXN=PNO"DEXPL (PHI) 330 NXN=NNO+PXN-PNO 331 ETAC=-(PSIS*PHIO) 332 NSURF=NC*FD102(ETAC) 333 NNSURF=NC'FD302(ETAC) 334 ETAV=-(EGAP-PHIO-PSIS-PHI) 335 PSURF=NV *FD102(ETAV) 336 PPSURF=NV*FD302(ETAV) 337 ARGMNT=NNSURF-NXN+PPSURF-PXN+NA'PSIS 338 IFIARGMNT .GE. O.ODO) GOTO 100 339 c 340 WRITE(LP,5) ARGMNT 341 5 FORMAT!IX,"WARNING: SQUARE OF SURFACE FIELD IS NEGATIVE',5X.D 342 ARGMNT=0.ODO 343 c 344 100 QS=CQS'DSQRT(ARGWT) 345 IFfPSIS .LT. O.ODO) QS=-QS 346 RETURN 347 END 348 SUBROUTINE FJVM L i s t i n g of M I S B J T . S at 11:24:09 on MAY 15. 1988 for CCid=NSZE on G 349 C 350 C THIS ROUTINE COMPUTES THE CURRENT FLOW JVM BETWEEN THE 351 C VALENCE BAND AND THE METAL 352 C 353 IMPLICIT REAL'S (A-Z) 354 C 355 COMMON /AREA1/ CBAR,CBCM.CBVM,CCM,CVM,CHISC,CHISV,CJCM, 356 I CJVM.CPSII,CQS,CTNLCM,CTNLVM,EGAP.EGAPI, 357 # NC ,NA ,ND , NI ,NNO, NV, Q, PHIO, PNO, 358 * PSISIO,VTHERM,WB.TP,TN.DN,DP,EPSIS 359 COMMON /AREA3/ ETAC.ETAMC,ETAMV,ETAV,JVM.NSURF,PHI,PSII,PSIS, 360 < PSURF.QS,THVM,THCM,U,VBE,VCE,JNO,JNWB,JREC 361 C 362 ETAMV=-(EGAP-PHIO-VBE-PSIS) 363 C 364 AVM=-PSII'PSII 365 BVM=PSII * CBVM 366 C0RFCT=1.OOO+IBVM/4.ODO+AVM/6.ODO-BVM'BVM/24.ODO/CVM)/CVM 367 THVM=DEXPL(CTNLVM*CORFCT) 368 C 369 IF (DABS(U) .GT. 1.0D-6) GOTO 200 370 IF( (ETAV .GT. -4.ODO) .OR. (ETAMV .GT. -4.000) ) GOTO 100 371 JVM=CJVM* THVM*DEXPL(ETAV)*U 372 RETURN 373 C 374 100 JVM=CJVM'THVM'DLOG(1,ODO*DEXPL(ETAV))'U 375 RETURN 376 C 377 200 JVM=CJVM* THVM* (FD1 ( ETAMV) -FD1 (ETAV) ) 378 RETURN 379 END 380 SUBROUTINE FJBASE 381 C 382 C THIS ROUTINE COMPUTES THE MINORITY CARRIER HOLE CURRENT FLOWING 383 C INTO THE SEMICONDUCTOR 384 C 385 IMPLICIT REAL'S (A-Z) 386 C 387 COMMON /AREA1/ CBAR.CBCM,CBVM,CCM,CVM,CHISC,CHISV,CJCM, 388 # CJVM.CPSII,CQS,CTNLCM,CTNLVM,EGAP,EGAPI, 389 # NC.NA.ND.NI .NNO.NV.Q,PHIO,PNO, 390 I PSISIO,VTHERM.WB.TP,TN,ON,DP,EPSIS 391 COMMON /AREA3/ ETAC.ETAMC,ETAMV,ETAV,JVM,NSURF,PHI,PSII,PSIS, 392 • PSURF,QS,THVM,THCU.U,VBE,VCE,JNO,JNWB,JREC 393 C 394 PSISI=PSISIO-PHI 395 IF(PSIS .GT. PSISI) PSISCR=PSISI 396 IF(PSIS .LT. PSISI) PSISCR=PSIS 397 IF(PSISCR .LT. 0.000) PSISCR=O.ODO 398 VBC=V8E-VCE 399 NBO=NI'NI/NA 400 DNB0=NB0*(DEXPL(PHI)-1.0) 401 DNBW8=NB0 *(OEXPL(VBC)- 1.0) 402 LN=OSQRT(DN'TN) 403 WBE=DSQRT(2 * EPSIS/Q/NA'PSIS * VTHERM) 404 WBEFF=WB -OSQRT (2 * EPSIS/Q/NA * (0. 7 - VBC • VTHERM)) - WBE 405 IF (WBEFF .LE. 0.0) WRITE(6.9999) 406 9999 FORMAT (1X.'WARNING THE BASE IS PUNCHED THROUGH !!!'/) L i s t i n g of MISBJT.S at 11:24:09 on MAY 15. 1988 for CCid=NSZE on G 4 0 7 0EN0M=2'LN"DSINH(WBEFF/LN) 408 A=DNBWB-0NB0*0EXPL(-WBEFF/LN) 409 B=DNBWB-DNBO"DEXPL(WBEFF/LN) 410 JN0=-Q'DN*(A+B1/DEN0M 4 1 ' JNWB=-Q'DN* ( A'DEXPL(WBEFF/LN)+B"DEXPL ( - WBEFF/LN))/DENOM 4 , 2 JREC=Q,WBE'NI*(DEXPL(PHI/2.0)-1)/2/TN 413 RETURN 414 END 415 SUBROUTINE FPSIS 416 C 418 C T H I S R 0 U T I N E C 0 M P U T E S PSIS GIVEN PHI, ASSUMING NO SURFACE STATES 419 IMPLICIT REAL'8 (A-Z) 420 INTEGER CNTRL1,I,ITMAX1,LP,NTIMES 421 C 4 2 2 COMMON /AREA 1/ CBAR . CBCM, CBVM, CCM, CVM, CHISC, CHISV, CJCM 4 2 3 1 CJVM.CPSII, COS, CTNLCM, CTNLVM, EGAP, EGAPI, 4 2 4 » NC,NA,ND,NI,NNO,NV,Q,PHIO,PNO, 4 2 6 ' PSISIO, VTHERM, WB , TP, TN.DN.DP, EPSIS 4 2 6 COMMON /AREA3/ ETAC , ETAMC , ETAMV , ETAV , JVM.NSURF, PHI, PSII PSIS 4 2 7 ' PSURF, QS, THVM, THCM, U, VBE, VCE, JNO, JNWB, JREC 4 2 8 COMMON /AREA4/ CNTRL1,ITMAX1,LP,NTIMES 429 C 430 CBARV=-(CBAR+VBE) 431 IFtCBARV .GT. O.ODO ) GOTO 100 432 IF(CBARV .LT. O.ODO) GOTO 200 4 33 PSIS=0.000 4 34 RETURN 435 100 PSISLO=0.ODO 438 PSISHI=CBARV 437 GOTO 300 438 200 PSISLO=CBARV 439 PSISHI=O.ODO 440 C 441 300 DO 500 I=1,ITMAX1 442 PSIS=(PSISLO+PSISHI)/2,ODO 443 CALL FQS 444 PSII=CPSII*QS 445 F1=PSIS+PSII-C8ARV 446 IFIF1 .EQ. 0.000) RETURN 447 IF(F1 .GT. O.ODO) GOTO 400 448 PSISLO=PSIS 449 GOTO 500 450 400 PSISHI=PS1S 451 500 CONTINUE 452 C 453 RETURN 454 END 455 DOUBLE PRECISION FUNCTION FDKETA) 456 C 457 C FERMI-DIRAC INTEGRAL OF ORDER ONE 458 C 459 IMPLICIT REAL'S (A-Z) 480 INTEGER INOEX 481 C 4 8 2 DIMENSION FDFLA(81),FDFLC(81),FDFLE(81),FDFLF(81),FDFLG(81) 483 C 484 COMMON /AREA5/ CFD 1, FDFLA , FDFLC, FDFLE, FDFLF, FDFLG r-r-( <—I Listing of MISBJT.S at 11:24:09 on MAY 15. 1988 for CCid=NSZE on G 465 C 466 IF(ETA .LT. -4.0D0) GOTO 100 467 IF(ETA .GT. 4.000) GOTO 200 468 X=(ETA+4.0D0)/0.100+0.500 469 INDEX=X+1 470 ETAO=OFLOAT(INDEX - 41)"0.100 471 DELETA=ETA-ETA0 472 OXPETA=DEXPL(ETAO) 473 FD1=FDFLF(INDE X)+DELETA'(DLOG(1.ODO+DXPETA) + * 7* » DELETA/2.000/(1.000+1.ODO/DXPETA)) 475 RETURN 476 C 477 100 FD1=DEXPL(ETA) 478 RETURN 479 C 480 200 FD1 = -DEXPL(- ETA)+ETA'ETA/2.OOO+CFD1 481 RETURN 482 END 483 DOUBLE PRECISION FUNCTION FD102(ETA) 484 C 485 C FERMI-DIRAC INTEGRAL OF ORDER ONE-HALF 486 C 487 IMPLICIT REAL'S (A-Z) 488 INTEGER INDEX 489 C 490 DIMENSION FDFLA(81),FDFLC(81),FDFLE(81),FDFLF(81),FDFLG(81) 491 C 492 COMMON /AREAS/ CFD1.FDFLA,FDFLC,FDFLE.FDFLF,FDFLG 493 C 494 IF1ETA .LT. -4,000) GOTO 100 495 IF(ETA .GT. 4.000) GOTO 200 496 X=(ETA+4.000)/O.100+0.5D0 497 IN0EX=X+1 498 ETA0=DFL0AT(INDEX-41)*0.1D0 499 DELETA=ETA-ETAO 600 FD102=F0FLE(INDEX)+DELETA'(FDFLC(INDEX)+DELETA/2,ODO*FDFLA<INDEX)) 501 RETURN 502 C 503 100 FD102=DEXPL(ETA) 504 RETURN 505 C 506 200 FD102=-DEXPL(-ETA)+ETA'ETA/2.0D0+CFD1 507 RETURN 508 END 509 DOUBLE PRECISION FUNCTION FD302(ETA) 510 C 511 C FERMI-DIRAC INTEGRAL OF ORDER THREE-HALVES 512 C 513 IMPLICIT REAL'S (A-Z) 514 INTEGER INDEX 515 C 516 DIMENSION FDFLA(81),FDFLC(81),FDFLE(81),FDFLF(81),FDFLG(81) 517 C 518 COMMON /AREA5/ CFD1.FDFLA,FDFLC.FDFLE,FDFLF,FOFLG 519 C 520 IF(ETA .LT. -4.000) GOTO 100 521 IFIETA .GT. 4.000) GOTO 200 522 X=(ETA+4.0001/0. 100+0,500 L i s t i n g of M I S B J T . S at 11:24:09 on MAY 15. 1988 for CCid=NSZE on G 523 INDEX=X+1 524 ETAO=DFLOAT(INDEX-41)*0.1D0 525 DELETA=ETA-ETAO 526 FD302=F0FLG<INDEX)*DELETA"(FDFLE(INDEX)+DELETA/2 527 RETURN 528 C 529 100 FD302=0EXPL(ETA) 530 RETURN 531 C 532 200 FD302=-0EXPL(- ETA)+ETA*ETA/2.ODO+CFO1 533 RETURN 534 END 535 DOUBLE PRECISION FUNCTION OEXPL(X) 536 c 537 IMPLICIT REAL*8 (A-Z) 538 c 539 IF(X ,LT. -150.000) GOTO 100 540 DEXPL=DEXP(X) 541 RETURN 542 100 DEXPL=O.ODO 543 RETURN 544 ENO 


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