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Reliability study of bipolar transistors with metal-insulator-semiconductor heterojunction emitters Szeto, Ngam 1988

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RELIABILITY STUDY OF BIPOLAR TRANSISTORS WITH METAL-INSULATOR-SEMICONDUCTOR HETEROJUNCTION EMITTERS.  by  Ngam Szeto  B.Sc., Queen's University , 1985  A thesis submitted in partial fulfillment of the requirements of the degree of Master of Applied Science  in The faculty of Graduate Studies Department of Electrical Engineering  We accept this thesis as conforming to the required standard  The University of British Columbia July 1988 © N g a m Szeto, 1988  In  presenting  degree  this  at the  thesis  in  partial  fulfilment  University of British Columbia,  freely available for reference and study. copying  of this  department publication  or  thesis by  his  for scholarly or  her  of the  for  I further agree that permission  purposes  an  advanced  I agree that the Library shall make it for extensive  may be granted by the head  representatives.  It  is  understood  that  of my  copying  or  of this thesis for financial gain shall not be allowed without my written  permission.  Department of  £LZC W CAI  The University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3  Date  requirements  AUfr  /Ml  /££R}/J&  ii Abstract  Bipolar transistors employing an MIS junction emitter  exhibit  the  very  desirable  operating frequency and/or high common  properties emitter  for of  the high  gains.  The  topic of this thesis is to investigate the usefulness of the MIS  bipolar  transistor  in  real  experimental results show two possible  applications. limitations  The  of  devices. The principal limitation is the inability of devices to withstand  moderate  second limitation is  the  temperature  relatively  high  these  stressing. emitter  resistance. The principal degradation mode of these  the  The  series devices  under temperature stressing is suggested to be the reduction of the thin insulating oxide.  Acknowledgement  The author gratefully acknowledges the following people for their help during execution of this thesis. N.G. Tarr is credited for supplying the producing the MIS bipolar  silicon  wafers  transistors.  and  D.S.  masks  Camporese  for is  acknowledged for his contributions to the development of the process for fabricating the transistor. Special  thanks  for  D.L. Pulfrey for the continuous support and discussions that made the completion of this thesis possible. The author also acknowledges the financial support of the and Engineering Council of Canada.  "I  Natural  Sciences  Table of Contents  Abstract Acknowledgement List of Figures List of Tables Chapter 1  Introduction  Chapter 2  Theory  2.1. The MIS junction model 2.2. The MIS BJT model 2.3. Model calculations 2.3.1. Effect of oxide thickness  .  2.3.2. Effect of carrier lifetime 2.3.3. Effect of metal work function 2.4. Chapter summary Chapter 3  Preliminary Experiments  3.1. Choice of metal 3.1.1. Fabrication of Al-I-S and Ti-I-S diodes 3.2. Emitter metal patterning 3.2.1. Fabrication of Mg-I-S diodes 3.3. Experimental results and discussion Chapter 4  MIS BJT Fabrication  4.1. Overview of processing 4.1.1. Pre-treatment 4.1.2. Collector metal deposition 4.1.3. Oxidation  4.1.4. Emitter deposition and definition  58  4.2. The transistor structure and test patterns ... 59 Chapter 5  Temperature Stress Tests  63  5.1. The experimental setup  63  5.2. Comparison of Mg, Al, and Ti devices  65  5.3. Comparison of Mg and Polysilicon devices  71  5.4. Discussion  75  Chapter 6  Series Resistances Measurement  6.1. Methods of measurement  83 83  6.1.1. Open collector method  83  6.1.2. Ning and Tang method  84  6.2. Discussion Chapter 7  Conclusion  91 92  References  94  Appendix A. Fabrication Procedures  96  A.1. Procedure for MR-20 and GT-G series devices .. 96 A.2. Procedure for GT-J series devices Appendix B. Software Listings  101 108  vi List of Figures  Figure 1.1.  Current components of a typical NPN transistor  2  Figure 1.2.  Structure of the MIS BJT  7  Figure 1.3.  Structure of the polysilicon emitter transistor  Figure 1.4.  8  Alternative structure of polysilicon emitter transistor  9  Figure 2.1.  Band diagram for a MIS junction  13  Figure 2.2.  Band diagram for a MIS BJT  19  Figure 2.3.  Current components of a MIS BJT  20  Figure 2.4.  Gummel plots of a Mg-I-Si BJT with different oxide thickness  Figure 2.5.  Gummel plots of an Al-I-Si BJT with different oxide thickness  Figure 2.6. "I  Figure 2.7.  different carrier lifetime  30  Gummel plots of a M-I-Si BJT with 32  Band diagram of a MIS junction that causes accumulation  Figure 3.1b.  28  Gummel plots of an Al-I-Si BJT with  different metal work functions Figure 3.1a.  27  35  Band diagram of a MIS junction that causes inversion  35  Figure 3.2.  Structure of the MIS dot diodes  38  Figure 3.3.  The emitter mask for the MIS BJT  vii experiment Figure 3.4.  44  Log(J) vs V curves for the Al-I-Si dot diodes  Figure 3.5.  46  L®g(J) vs V curves for the Ti-I-Si dot diodes  Figure 3.6.  47  L©g{J) vs V curves for the Mg-I-Si diaREtes  --  Fifure 4.1.  Structure of the MIS BJT  Figure 4.2.  Duping profile of the base implant for  48 51  tils- 341S BJT Figure 4.3.  53  Log(U) vs V curves for Al-I-Si dot ditcaaes with different oxide growth csmfflitions ..,  Figure 4.4.  56  SHaiHCtnare of the Van der Pauw test p£C-tern  Figure 5.1.  -  •  61  Dsssgrnadation of current gains for the GUMS series devices  66  Figure 5.2.  GmMimsl plots for Mg-I-Si transistor ... 68  Figure 5.3.  Gmmmel plots for Al-I-Si transistor ... 69  Figure 5.4.  Gjummel plots for Ti-I-Si transistor ... 70  Figure 5.5.  Gramme1 plots for GT-J series Mg-I-Si  I  tarsmsistor Figure 5.6.  Guatranel plots for GT-J series polysilicon enittter transistor  Figure 5.7.  73  74  Lrogjl(Jc) vs V B C curves for Mg-I-Si taranasistor  76  vi i i Figure 5.8.  Log(J c ) vs V B C curves for polysilicon emitter transistor  Figure 5.9.  The effect of shunt resistance on Al-I-Si transistor characteristics  Figure 6.1.  79  V C E vs Ig curves for Mg-I-Si transistor  Figure 6.2.  77  V C E vs  85 curves for polysilicon  transistor  86  Figure 6.3.  Series resistance components  88  Figure 6.4.  (kT/qI c )In(I B Q /I B ) vs 1/0 curves for Mg-I-Si transistor  Figure 6.5.  (kT/qI c )In(I B Q /I B ) vs 1/0 curves for polysilicon transistor  I  89  90  ix List of Tables  Table 2.1.  Nominal Parameters used for MIS BJT model calculations  I  24  1  Chapter 1  Introduction Silicon bipolar junction transistors (BJTs) used extensively for the last thirty years or  have  so.  been  Although  new technologies have evolved, the need for bipolar  devices  has never stopped. In  digital  fact,  the  fastest  silicon  logic nowadays is still emitter coupled logic is based on bipolar technology. However,  as  (ECL), the  which  need  faster computers and higher frequency communication  for  devices  grows, bipolar technology is continually being developed order to further improve the operating speed. Presently fastest devices have cut-off frequencies (f T )  around  in the  15-20  GHz.  The  techniques  performance  of  under BJTs,  metal-insulator-semiconductor  development including  to  increase  the  use  (MIS) and polysilicon  the of  emitter  devices, are briefly reviewed in this chapter.  The current components of a typical NPN  BJT  operating  in the active mode are shown in Fig. 1.1. J I N j and J B I N j are the current components that make up the emitter current  Jg.  J___, J__„ and J„ DI! are the recombination current components KHiHj  KtiL  KciD  that correspond to recombination of  holes  in  the  neutral  emitter, base-emitter space-charge region, and  the  neutral  INJ \ j  REE  Collector  Base  Emitter (") Electron Flow  (n)  (P)  u  V  REC  REB  jEH  /\  J CBpN  BINJ Hole Flow 0  l/N J  B  Fig. 1.1. Current components  typical NPN transistor  3  base respectively. J g E N is the  generation J  base-collector space-charge region, and saturation  current  due  to  current  CB  in  the  p  transport  the hole  across  the  base-collector junction. The current components at the three terminals of the BJT are then: J  E -  J  INJ  J  B "  J  B  J  C "  J  Cn  + J  (1.1)  BINJ  (1.2) +  J  (1.3)  CBp  One approach to obtaining a higher cutoff frequency a BJT is to first increase the common-emitter  current  and then trade off some of this gain for a higher  maximized  the base current Jg. Several techniques  while are  gain  operating  frequency. To achieve high common-emitter current gain, collector current J c should be  in  the  minimizing  available  and  can be used together to achieve the goal.  the traditional approach to achieve higher BJTs is to increase  the  emitter  injection  performance  efficiency  by  using a lightly doped base and a heavily doped emitter. This arrangement  allows  current  dominate  to  the  base  the  minority  base-emitter  carrier current  diffusion carrier  transport process, since the minority carrier  concentration  in the emitter is  the  much  less  than  that  carrier concentration in the base region. base-emitter depletion region appears  of  minority  Furthermore,  mainly  in  the  the base  4  region, causing a narrower  effective  base  width,  and  so  diffusion  or  reduces the neutral base recombination current.  The dopants can be introduced by  either  ion implantation techniques. The latter is preferred can provide better  control  for  doping  in  the  as  base  it and  emitter regions of the transistor. The tight process control that is possible with ion implantation also allows the width of the base region to be made very narrow, further  reducing  the neutral-base recombination current. A typical base width in state-of-the art silicon BJTs is 0.15Mm [l].  Ion-implanted  high/low  emitter/base  narrow bandwidths are employed  in  junctions  modern  silicon  and  bipolar  transistors to achieve better performance and better process control. However, as region  increases,  recombination  takes  the  doping  bandgap place.  density  narrowing Both  of  the  occurs  these  emitter  and  effects  Auger cause  reduction in emitter injection efficiency, thereby  a  reducing  the transistor performance.  It  is  semiconductor  known  that  material  metal will  in cause  close band  vicinity bending  semiconductor. With the right choice of metal,  the  in  to the  surface  of the semiconductor can be inverted and the band bending in the  semiconductor  will  resemble  that  of  an  ideal  p-n  5  junction. Theoretically, if the separation between the metal and the semiconductor is infinitesimally small so that electrons  and  material, the  holes  can  structure  tunnel will  through  behave  junction, with minority carriers  the  like  within  separating  an  the  both  ideal  semiconductor  dominating the current transport process [2]. However, the metal comes in direct contact  with  the  when  semiconductor,  the metal-semiconductor interface will have a large  surface  state concentration, due to dangling bonds that result the incompatible bonding structures of The large amount of  surface  states  the  two  will  p-n  from  materials.  accommodate  major portion of surface charges that result from  the  the work  function difference between the metal and the semiconductor, leading to less band bending result,  the  barrier  interface is usually  in  height  the of  determined  semiconductor. a  by  As  a  metal-semiconductor the  semiconductor surface and the barrier  property  height  for  of  the  minority  carriers is larger than that for majority carriers.  Low temperature silicon oxide grown on top  of  silicon  bonds nearly perfectly to the semiconductor surface  without  causing a large surface state concentration at  silicon  the  surface, while the thickness of the oxide can be to such a degree that charge can tunnel through With this technology, one can produce a  MIS  behaves  with  like  an  ideal  p-n  junction  controlled the  oxide.  junction the  that  minority  carriers dominating the  current  transport  process,  minimizing the majority carrier flow. Furthermore,  while  the  MIS  junction will not suffer from the heavy doping effects which can degrade the  performance  of  conventional  homojunction  bipolar transistors.  Bipolar transistors employing the  MIS  junction  as  a  replacement for the heavily doped emitter, are presently the subject of much research. The structure for these is shown in Fig. 1.2. Extremely high common  MIS  emitter  BJTs gains,  of the order of 30,000 have recently been reported for devices [3,4]. Gains of this practical  importance.  magnitude  However,  the  are  not  extremely  such  of  great  high  gain  offers an opportunity for trading-off the gain to achieve higher operating frequency. This can be most obviously by increasing the base  doping  density.  This  emitter / base injection efficiency and the factor, so  lowering  the  current  gain.  reduces the base resistance, and it  is  the  transport  However this  done  reduces  base  a  it  also  factor  which  leads to an improvement in frequency response.  This  approach  has  been  adopted  by  several  large  semiconductor companies. Silicon BJTs fabricated at research can be operated up to 11 GHz  [5],  while  Tektronix have fabricated similar devices that frequencies of 16 GHz and 15 GHz respectively  Plessey NTT  have [6,7].  and  cutoff These  Base metal (Al)  Emitter metal Tunneling oxide -JZ2I Si0 2  V////////A  YzzzzzzzzzA  p+  p+ n substrate Collector metal (Al) Fig. 1.2. Structure of MIS BJT -N  Base metal (Al)/' /  )////////A  Emitter metal (Al) _ Polysilicon  V/J///////X/.  2  Si0 2  Y7////////A  P+  P+ n substrate Collector metal (Al)  Fig. 1.3. Structure of polysilicon transistor 00  Base metal (AlV P73 ^ Si0 2 YZZZZZZZZZX P+  Polysilicon Emitter (n+) T u n n e | i n g 0 x ide "  2 YzzzzzzzzzA  Mono Emitter P+ Intrinsic Base L n substrate Collector metal (Al)  Fig. 1.4. Alternative Structure for Polysilicon Emitter Transistor  10  cutoff frequencies  are  a  great  improvement  for  silicon  devices, and they are just high enough to be used in day  microwave  results  have  polysilicon  communication  equipment.  been  achieved  emitters,  rather  These  using than  modern  excellent  transistors  MIS  tunnel  junction  emitters. The polysilicon may act like the metal BJT in the structure shown in Fig. 1.3.  [8].  with  in  a  Alternatively  the polysilicon tunnel junction may replace the metal in a conventional BJT structure,  see  Fig.  MIS  1.4.  layer  [9].  reasons why these polysilicon emitter structures  give  The high  gains is still under discussion [9,10,11]. The highest gains so far reported are around 10000 [8].  Both performance  of  these of  new  bipolar  developments transistor  in seem  attractive. However, to date there have and feasibility performance  studies  devices  to  can  indicate  be  improving to  been  be  no  whether  implemented  grow  the  ultra  acceptable degree of uniformity  thin  these  high  any  real  in  in  oxide  and quality. An additional concern.for the MIS the stability and durability of oxide. Aluminum is known to  the  reduce  ultra silicon  duri ng the deposition of the metal [12]  and  lies  in  to  an  layer  thickness,  very  stability  applications. A major concern with all the devices the ability to  the  composition junction  thin  layer  dioxide, on  temperature stressing [13]. It is the main purpose  is of both  subsequent of  this  11  thesis to investigate the  stability  of  these  MIS-emitter  transistor (MIS BJT) devices and to draw a conclusion as  to  whether the current stage of development of these devices is such that they can be used in any real application.  Another  factor  that  determines  the  feasibility  of  implementing these devices is the series emitter resistance. It has been shown that the  emitter  current  of  transistor of any size, should remain roughly  a  bipolar  unchanged  in  order to maintain optimal circuit performance [14]. In  VLSI  applications, the size of the emitter area is so small  that  any emitter series  resistance  would  become  an  factor in limiting the circuit performance. The oxide layer in successful  the  MIS  BJT  implementation  is of  a  major  the  important interfacial  threat  device  to  the  in  VLSI  applications. The emitter series resistances of both the MIS BJT and polysilicon emitter further ascertain  the  transistors  feasibility  devices in VLSI applications.  of  were  measured  implementing  to  these  i  Chapter 2  Theory  It is well known  that  the  MIS  tunnel  junction  can  behave almost like an ideal pn junction diode [2]. Moreover, the  MIS  junction  conventional  is  far  diffused  or  easier  to  fabricate  ion-implanted  pn  than  a  junction.  To  formulate the junction characteristics with respect to metal work function,  oxide  thickness,  doping  density,  carrier  lifetime and insulator bandgap is not an easy task. However, with the help of a computer, one can set up numerical  model  for the MIS junction.  In this chapter a model for the MIS junction diode is reviewed and then used as the basis  for  a  model  [2] of  a  three terminal device, a BJT transistor with MIS emitter.  2.1. The MIS junction model l The band diagram of shown  in  Figure  2.1.  components J C M and J ^  a  typical  There in  the  are  M-I-p/Si two  model  junction  tunneling  which  is  current  represent  the  electron and hole tunneling currents respectively: J  CM "  I  e  CM\iT2(F1[(EFn(V  "  V  X  - F 1 [ ( E p M ( X s ) - E c (X s ))/kT])  S  ) ) / k T ]  (2.1)  Rg. 2.1. Band diagram for a MIS junction under forward bias  14  J  e  V M " "f  iMAhiT2(F1[(EV(XS) "  E  Fp(XS))/kT]  - F 1 [ ( E V ( X S ) - E p M (X s ))/kT]) where  and  are  the  (2.2)  tunneling  probabilities  f 'c  electrons  and  holes  effective  Richardson  respectively, constants  Ag  for  and  A^  are  electrons  respectively, F 1 is the Fermi-Dirac integral and the summations run over all the  for  *  the  and  of  holes  order  conduction  band  one peaks  and valence band valleys. There are also three surface state current J  MT'  J  and  CT'  J  VT  represent  the  semiconductor conduction band to trap and  components,  metal  to  valence  trap,  band  to  trap currents, respectively:  J m t  -  "  (2.3)  t M i >  Mi J  CT  J^  where N ^ the  =  S N  =  q I  TiCni[n(XS)(l-£Ti) " nlifTi]  N  Ti  c  Pi  [p(X  S)fTi  " PU(1  (2  " fTi)]  is the trap density at the i t h level  occupancy  probability  at  that  (2.5)  and  level,  probability  that  the  ith  level  occupied when in equilibrium with the metal, C the  capture  cross  multiplied by the  sections average  for  carrier  holes thermal  fTi is  characteristic time for the metal-to-trap tunneling and f M i is the  '4)  P  and  and  the  process will Cn  be are  electrons  velocity.  charge stored in the surface states Q g s is given by  is  The  15  Q  J f Ti N Ti  SS "  +  5 ^ (1 - f T i ) N T i  acceptors Finally,  donors  there + J  components,  p^  x  (2.6)  are and  s ^  two J  +  semiconductor  n^XS  which  current represent,  respectively, the hole current and the electron current just inside the semiconductor.  These currents are linked  together  by  the  need  for  current continuity at the interface. For instance, J  CM - JCT " Jn(XS>  (2  '7)  J  VM " JVT  (2  '8)  and =  V * ^  Another boundary condition comes from the summation  of  the  for  the  potential drops across the entire diode.  These three boundary conditions must be model  to  produce  accurate  satisfied  solutions.  By  making  assumptions that the majority-carrier quasi-Fermi constant throughout the semiconductor levels  for  space-charge  both  carriers  region,  the  are  and  constant  boundary  the  the  level  quasi-Fermi  throughout"  condition  is  the  that  is  concerned with the majority carrier (2.8) is overridden. The net minority current component J n (X*) is given by J  n(XS}  = J  d(*}  + J  rq(*'V  " J UPC  (2  '10)  16  J^(<t>)  where  is  the  minority  carrier  diffusion  Jrg(0,*//g) is the recombination current in the region and  J  UpC  is  uncompensated the  theory are used here [15].  uncompensated  standard  term J U p C in the above expression allows for of photovoltaic effects. It is completeness, but will always  included be  space  equal  charge  photocurrent.  expressions for J^ and J r g from The  current,  for to  pn  The  junction  photocurrent the  modelling  the  sake  zero  for  of the  purpose of this thesis. JdU)  = J o d [exp(q4>/kT) - 1]  (2.11)  and JrgU,^s)  = Jorg  Us/2^B)1/2  and J o r g are user input carrier  lifetime  and  [exp(q0/2kT)-l]  parameters  semiconductor  through doping  (2.12) which  density  the are  included in the model, J  od  ?  VT N  — AA  [Dn 7/rn ]  1/?  (2.13)  and J org = o r n  9ni „ —  n  1[  1/? Y 2 eS„ ( 2\p^)qN B M Ah \ '  (2.14)  where 2\p is the built-in potential at the onset B  of  strong  inversion .  Last of all, the potential across the insulator i/^ must be calculated in order to evaluate expression (2.9). related to the total charge stored  on  both  sides  is of  the  17  insulator, by Gauss' law. The charge stored is comprised Q g , the charge stored  in  the  semiconductor  space  of  charge  region, and Q g g the charge stored in the surface states. The expression of =  -77  is then (Q  s  + Q  ss )  (2  where d is the insulator  thickness.  Qg  can  be  -15)  found  by  assuming that both Ep^ and E p n are constant across the space charge region within the semiconductor [2], then Q s = s g n U g ) (2kTe s ) l / 2 { N c F 3 / 2 [ (E pn (X g ) - E c (X g ))/kT] - n(X n ) +  NU  p(xn)  where  + NvF3/2[(Ev(Xs)  qt  }  kT and  - Epp(Xg))/kT] - p(X n )  1/2  °(xn)  (2.16) are  the  hole  and  space  charge  concentrations at the boundary of the  electron region  and the quasi-neutral base. ?  All the terms in expressions (2.7) evaluated by  knowing  both  and  initial values, one can iterate on  and  4>.  (2.9)  After  and $  can  be  postulating  until  the  two  boundary conditions (2.7) and (2.9) are met, In this way the currents J ^ and J C M for a given applied voltage  V  can  be  computed. 2.2 The HIS BJT model The model  to  be  discussed  assumes  a  M-I-p/Si-n/Si  18  structure. The band diagram for such a device  operating  in  the active mode, is shown in Fig. 2.2. The model for the MIS BJT is very similar to the  MIS  junction  diode  fact, the MIS BJT model is merely an extension junction  diode  model,  with  a  few  model. of  In  the  additional  MIS  current  components.  A few assumptions were made, in order to keep the model simple and to make it easy to study the  device  sensitivity  to various parameter changes. The assumptions are base region is uniformly doped and contains a  that  the  quasi-neutral  region during operation, and that both high level  injection  and series resistance effects can be ignored.  The current components for the  model  (shown  in  Fig.  2.3), include those used in the MIS junction diode model, and the new currents J R E C , J n < 0 ) # n  J  n  (W  b)'  J  R E ' Ji  GEN  and J  CBP  'i  JREC  is  the  recombination  current  in  the  base-emitter space charge region, such that  (2.17)  where  WBE BE  is  junction, and t W. BE  the n  depletion  width  of  the  base-emitter  is the electron life time.  (2ests/qNk) S S  1/2  (2.18)  19  Fig. 2.2. Band diagram of MIS BJT  Emitter  Base (p)  Si02  Metal  Collector (n) J  Cn  'CM J  <  J  CT  MT  V  S /  J  J  REC  l/Sl  RE  JGEN  IS/I  / \ V J J  VT  VM  JCBp J  B  l/si 0  w  B  Fig. 2.3. Current components of the MIS BJT  21  The currents, at both boundaries of  the  neutral  base  represented by J n (0), the current at the  emitter  boundary,  and J n ( w B ) r the  current  at  the  collector  expressions for J n (0) and J n ( w B ) / can be  are  boundary.  found  by  The  solving  the continuity equation with no drift current component  for  a uniformly doped base. dn dt  = -  3 2 n (x) 1 =0 dx*  6n (x) + D n r n  (2.19)  where n is equal to the minority  carrier  the  excess  base  region,  6nfi  concentration, and D n constant  in  the  is is  base  the the  minority  region.  The  concentration minority carrier  in  carrier diffusion  solutions  for  the  continuity equation are as follows: j (0) =  q  [5n  B ( 0 ) C°Sh(WBeff/Ln) " * L n sinh(W B e f f /L n )  n  B  (  V  ]  (2  2Q)  and , Sn(W B ) =  qD  0  [Sn (0) - 8n (W ) cosh(W /L)] Be£f n 1 (2.21) L  n  sinh(W  Beff/Ln)  where the expressions for the excess carrier  concentrations  at the boundaries of the base region, and the effective base width are as follows: 8n B (0) = n B Q (exp(q<£ / kT) - 1)  (2.22)  6n B (W B ) = n B 0 (exp(qV BC / kT) - 1)  (2.23)  W  Beff  = W  B " W BC " W B E  (2.24)  where V?BC is the base-collector depletion width in the  base  22  region, and is expressed by W  BC  =  (2e  (V  S  bi " V B C ) / «  N  A)1/2  (2  '25)  The difference between J n (0) and ^ n ( w B ) is equal to the recombination current within the neutral base J  RE  = J  n(0) "  J  n  (  Kiii  hence: (2  V  The current components contributed by  the  reverse  '26)  biassed  base-collector junction are J Q E N and J C B p , where J Q E N is the generation current within the  base-collector  region and <JCBp is the reverse bias  space  saturation  charge  current  of  the junction. n  q  J  GEN  w  i  =  n  T  c b  TT72 p  (2.27)  rJ  and  ;cbp  =  <v  P  >K  where D p , r p and r n are model parameters that represent diffusion constant for holes, and  the  effective  for holes and electrons respectively.  the  lifetimes  is the total width  of the base-collector depletion region, expressed by: 2e c W  CB " [ - 7 - < q  N. + N n * n  a  . V  > < bi  +  VCB)]  1/2  (2.29)  d  The minority carrier current component at the  boundary  of the semiconductor and insulator, J n (Xg) is now given by:  23  J  n(XS>  = J  +  REC  J  n(0)  (2  '30)  The two boundary conditions for the MIS BJT model are then: "  V  +  B E " *M "  +  *SC "  =  0  (2  '31)  (2  '32)  and J  CM " JCT "  J  n(0)  +  J  REC  Once again, the model can be solved by vl/g and <j>, until the two boundary  iterating  conditions  are  both  met.  The  emitter, base, and collector currents are then: J  E  = J  CM  + J  J  B  = J  VM " JVT  VM  Jc - JN(WB)  +  +  J  +  J  <2'33>  MT +  RE  JGEN  +  J  REC ' J C B p " J GEN  (2.34)  JCBp  (2.35)  2.3. Model Calculation The  theoretical  MIS  BJT  model  was  tested,  parameters listed in Table 2.1. The values  for  using  NA  and  were obtained by approximating the simulated doping of the experimental device MR-20 using SUPREM II by uniformly  (refer  doped  to  affinity and the metal work functions for obtained from the literature, together  profile  section  regions. Al  4.3.)  The  electron  and  Mg  were  the  diffusion  constants D n and D , and the effective Richardson  constants  A e and A, [16], The n  effective  with  N^  lifetimes  r  n  and  r p  were  approximated from previous life time measurements of similar  Value  Parameter 3)  4.0x1016  ^)  1.5x10  Silicon Valence Band Energy  (eV)  3.73*  Metal-Insulator Barrier Height  (eV)  Substrate Doping Density  (cm  Neutral Base Doping Density  (cm  —  Aluminum  4.80*  Magnesium  5.55* 0.65  Electron Effective Mass in Insulator Insulator Band Gap  (eV)  8.0  Insulator Thickness  o (A)  10  Density of States Ratio  (NC /  N  V  )  me  0.372  Effective Richardson Constant Electrons  (A- c m - 2 o K - 1 )  45  H6les  2 (A- c m - ° K - 1 )  78  Carrier Lifetime Electron  (uS)  6  Holes  (uS)  6  *: These energies are measured with respect to the insulator valence band. Table 2.1. Nominal Parameters used for MIS BJT Model Calculations.  25  devices [17], and the oxide thickness was also  approximated  from previous observations [2].  However, neglecting the  series  resistance,  injection level effects does raise some the  usefulness  of  the  device  thickness or the metal  work  is  external MIS  BJT  regarding  as  the  Ic  and  then  The oxide  decreased. series  This  resistance  model.  The  series  resistance model simply makes the approximation that equal to  high  studies.  bound  function  problem was solved by using an model in conjunction with the  problems  sensitivity  emitter current will increase without  and  calculates  the  effective  subtracting the voltage drop across  the  series  I„  is  VBE  by  resistance  from the applied Vni:,. bet  2.3.1. Effect of oxide thickness The ultra thin layer of factof- in achieving high gain  tunneling in  a  oxide  MIS  BJT  is  the  key  device.  Any  change in oxide characteristics is likely to have  a  direct  influence on the device behavior. One of the most  important  parameters of the oxide, is the oxide thickness.  It  thin that it is very sensitive  conditions  to  processing  is  so  and oxide reduction by the overlaying metal.  The  eff ect  of  change  in  oxide  thickness  investigated using the MIS BJT model. The model  shows  was that  26  the gain of the device would increase without bound  as  the  oxide thickness is reduced. This is due to the fact that the model assumes a perfect layer of oxide  and  both  the  high  level injection and series resistance effects are ignored. A thinner  layer  of  oxide  would  enhance  the  probabilities for both carriers leading to currents, but as long as the oxide  higher  continues  the semiconductor surface, the back  tunneling  to  injected  limiting passivate  hole  current  will still be orders of magnitude below that of the electron injection current.  In reality, the gain of the device cannot be increasing without bound, as the current density series resistance external series  and  high  resistance  realistic results for  the  level model  MIS  will  be  injection was  BJT  used  model.  results with series resistance (shown in  Fig.  limited  by  effects.  An  to The  get  more  simulated  2.4  &  show that the gain of the device is still increasing but  2.5) at  a much slower rate and is not going to be unbounded.  From the simulated results, one can see that the device is not going to suffer from reduction of oxide thickness, as long as the oxide keeps  its  property  semiconductor surface.  2.3.2 Effect of carrier lifetime  of  passivating  the  v B E (V) Simulated with series resistance of 500 Micro Ohm—cm^ Fig. 2.4. Effects of Oxide thickness on Mg—I—Si transistor  28  4 -1 3 2  -  JC3 1  -  0  <<  -1  O -3  - 2  JB2 CD  -3 H  O O  -5 -  - 6  -  " T 0 X = 15 A I I q x = J°_A_  JB3, JC3 - Tgx = 5 A -8  ,  0.0  |  0.1  ,  t  0.2  '  i  0.3  '  i  0.4  '  i  1  0.5  VBE  I  0.6  1 —1—" F nr™ , ™ , T™T ,L —r  0.7  0.8  0.9  (v)  Simulated wfth series resistance of 500 Micro Ohm-cm 2 Fig. 2.5. Effects of oxide thickness on Al—I—SI transistor  1.0  29  The carrier lifetime in important factor in carrier  lifetime  high would  the  base  performance increase  region MIS  both  is  BJTs.  the  another A  short  recombination  currents in the base-emitter space-charge region and neutral base region. This would in turn increase  the  base  current  and decrease the gain of the device.  The MIS BJT model was used to investigate the effect of change in carrier lifetime. The model result (shown in 2.6) clearly shows an increase in base current  in  Fig.  the  low  bias region as the minority carrier lifetime decreases. This is  consistent  with  the  recombination current,  argument  since  the  region for a BJT is at the low  of  increasing  recombination  bias  region.  dominated  However,  the  virtually  the  base currents at the higher bias region  are  same'for the range of carrier lifetimes  investigated.  is  because  the  base  current  at  high  base  bias  This  regions  is  dominated by the holes back-injected into the emitter rather than the holes participating in the recombination process in the  base.  2.3.3 Effect of metal work functiorr For low and moderate values of forward bias, the electron current is small compared (i.e.  J _  from  metal  semiconductor to metal).  to  to  its  semiconductor  This  state  of  two and  total  components  J_ from CM quasi-equilibrium  30  VBE (V)  Pig. 2.6. Effects of carrier lifetime on A!-I—Si transistor  31  keeps E p n pinned close to E p m . However, for  large  currents  there is an appreciable energy difference between these  two  Fermi levels, therefore the total applied base-emitter voltage will appear partially across the interfacial  bias oxide.  This would cause the device characteristics to deviate  from  an exponential dependency on the applied bias.  with  different work  functions  will  produce  carrier concentrations on the same  Metals  different  semiconductor  surface substrate  and so will cause the device to enter the tunneling  limited  regime at different current densities [17].  The simulated result (shown in  Fig.  2.7)  shows  metals with higher work function would produce less inversion and would in turn lead to entry  into  that  surface  the  tunnel  limited regime at a lower emitter current density. Note that this  effect  is  similar  to  that  resulting  when  series  resistance is present. No series resistance was included this simulation. The precise values of 4>M chosen, the  in  represent  of metals that have extremely low work function  (2.3  eV), Mg (3.35 eV) and Al (4.4 eV).  2.4. Chapter Summary The predicted results appear to  be  reasonable  in  as  much as they give realistic Gummel plots. As expected,  high  gain devices with p-type bases must have thin  long  electron  lifetimes  and  employ  metals  with  oxides, low  work  V B E (V)  Fig. 2.7. Effects of metal work function on M—I—Si transistor  functions.  34  Chapter 3  Preliminary Experiments  3.1 Choice of metal The dominating current  transport  junction can be determined  by  the  carriers  in  a  combination  of  doping  density of the semiconductor and the work metal. The band diagram of a semiconductor and a low  work  MIS  function  junction  function  with  metal  of  MIS  the  a  n-type  that  causes  accumulation at equilibrium is shown in Fig. 3.1a. Fig. 3.1b shows a MIS junction with a low work function metal  and  p-  type semiconductor. This combination causes inversion of the semiconductor surface at equilibrium. It can  be  any junction that is accumulated will have a  large  barrier  in this case)  causing  height for its minority carriers the majority  carrier  to  dominate  the  seen  current  that  transport  process. However, the MIS junctions that cause inversion the semiconductor surfaces will have a small barrier for minority carriers and a large majority carriers (<t>Bn and  barrier  height  respectively in  this  of  height for  the  case),  allowing minority carriers to dominate the current transport process.  In order to optimize the performance of a BJT, electrons should be chosen as  the  silicon  dominating  MIS  carrier  Fig. 3.1a. Band diagram of a MIS £mction that causes accumlation  <(>Bn  rt _  _.J r  e  f  ..  -©-  Fm  Fig. 3.1b. Band diagram of a MIS junction that causes inversion  36  because of their higher diffusivty  as  compared  This will call for a M-I-p/Si-n/Si  structure.  to  holes.  Furthermore,  the metal must have a low work function to invert the p-type base region, so that the relatively low barrier electrons will allow electrons to be  easily  height  for  injected  into  the base while blocking the back-injected holes through  the  high majority carrier barrier.  the  The  work  function  metal must be smaller than the effective  work  of  function  of  the intrinsic base, therefore the work function must be less than the intrinsic Fermi level. *M < *Si " X Si  +  V  2  =  4  '61eV  (3  '1)  Several good choices of emitter metal from the point of view of work function would be Al, Ti, and Mg, work functions  are  all  less  than  practical usefulness of devices made  4.61eV. from  since  their  However,  these  the  materials  needs to be investigated. There have been several reports of degradation of tunnel junction diodes made with Al [13]. is well-known to be very reactive and unstable the Al metalization process is well more stable  metal  leading  to  [18].  established,  potentially  more  Ti  Mg  While is  a  reliable  devices.  MIS diodes with the three selected  metalizations  were  fabricated to verify whether the combinations of metal  work  functions and semiconductor doping densities were  inverting  37  the semiconductor surface, and performing properly  like  pn  junction diodes.  3.1.1 Fabrication of Al-I-S and Ti-I-S diodes Four boron doped, <100> orientated wafers with  nominal  resistivity of 0.1 fi-cm, 1 O-cm, 2 fl-cm and 10 fi-cm were cut into  quarter  wafers.  Dot  diodes  were  then  fabricated  simultaneously with quarters from each of the four different resistivity wafers, in order to investigate  the  effect  different doping densities. The structure of the dot  of  diodes  is shown in Fig 3.2.  Groups of four quarter wafers were cleaned by following the standard RCA cleaning procedure [19]. Once  the  wafers were cleaned, back contacts of aluminum  were  by evaporation of Al in a CHA vacuum chamber at of around 4x10  6  Torr. The back contacts  the s&me time as the growth oxide in a  quartz  tube  of  furnace.  required 5 minute warm-up and with a nitrogen flow of period was between the  the  were  ultra The  cool-down  1L/min. warm-up  The angl  a  pressure  growth at  oxide  cool-down  at  tunneling  periods  actual  formed  sintered  thin  oxide  quarter  step 500°C growth  periods  at  500°C with an oxygen flow of 1L/min for 20 minutes [20J. The oxide thickness for such a procedure o  was  around 15 A. The barrier metals were formed the desired metal onto the  front  of  the  estimated by  to  be  evaporating  wafers,  with  a  Barrier Metal •  Tunnel Oxide  y/////////////y. / !' Depletion Region/  v-'i Xlnversion Layer p Substrate  b Ohmic Back C o n t a c t (Al) Fig. 3.2. S t r u c t u r e of the MIS dot  diodes  go  CP  39  shadow mask placed in between the wafers and the evaporation 2  source. The nominal area of the dot diodes was 0.01 cm .  Problems were encountered during the evaporation of Ti. The CHA evaporation power supply can  only  supply  current in the order of 100 A maximum, which is  filament  not  enough  to evaporate the Ti at an acceptable rate of deposition. The prolonged  period  of  evaporation  at  an  extremely  temperature caused the Ti contact to be oxidized,  high  producing o  a deposit of dark black color. The resulting film was 1500 A thick and was found to have a very high resistivity. A Veeco vacuum system, which  was  capable  of  supplying  a  higher  current (150A), was also used to produce a second set of  Ti  diodes. However, this approach did not seem to help reducing the oxidation of Ti and  hence  did  not  reduce  the  metal  resistivity. Tjhe Al metalization was performed in the and did not lead  to  any  oxidation  problem,  relatively high vapor pressure. The rate of be easily adjusted to give  an  CHA  acceptable  chamber,  due  to  its  deposition  can  deposition  without overheating the substrate. The thickness of  time  the  Al  o  film was chosen to be 3000 A in order to resistance [20].  reduce  the  metal  40  3.2 Emitter metal patterning The shadow mask method is perhaps the pattern the barrier metals  for  large  best  MIS  method  to  junctions.  The  method patterns the metal at the same time as the deposition of the metal, hence eliminating the possibility of damage to the underlying tunneling oxide  by  any  further  processing  steps. However, the shadow mask method runs into  a  lot  of  problems when a fine metal pattern is required and alignment of the metal pattern to  previous  structures  Photolithography provides a second means of emitter metal. Currently  there  are  two  schemes available, namely the  lift-off  direct patterning  The  technique.  critical.  patterning  the  photolithrography technique  lift-off  eliminate the over etching effects,  is  which  and  the  technique  can  can  occur  with  direct etching, and will work on any metal without having to worry about the choice of etchants. However, lift-off has major5 drawback in  producing  MIS  junctions.  The  a  lift-off  method requires the photoresist to be patterned before metal deposition. possible  This  damage  extra and  processing  step  contamination  of  could the  lead  to  underlying  tunneling oxide. Therefore, the direct patterning method  is  preferable in MIS junction fabrication.  Direct  patterning  of  Al  is  well-established.  commonly used phosphoric acid is a safe  etchant,  since  The it  41  will etch off the Al without causing any damage  to  silicon  and silicon oxides. Acceptable etch rates can be achieved by using diluted (1:1) The etch rate for  H  3  p  0 4 with DI water when heated to 60°C.  such  an  etchant  is  approximately  300  A/Min.  Patterning Mg, however, is a much more than patterning Al. The highly reactive Mg with many common etchants, leading to  difficult  reacts violently  complete  removal  the Mg contact. The right choice of etchant and the concentrations must be determined,  in  order  to  damage  and  patterning  contamination  could  of  the  lead  of  optimal fabricate  high performance Mg-I-S devices. Despite the fact lift-off technique of  task  that  to  possible  tunneling  publications [3,4] have recorded working MIS BJT  the  oxide,  fabricated  with' the lift-off technique of patterning the emitter metal.  JTwo silicon wafers were used to study and optimize Mg patterning procedure. The p-type 10 Q-cm  <100>  the  oriented o  wafers were cleaned using the RCA cleaning procedure. 3600 A of Mg were deposited on the front of "Drummel" type tantalum boat as the  the  evaporation  the CHA vacuum chamber with a pressure of o deposition rate of around  10  A/Sec.  wafers,  using source  2 x 1 T o r r  Positive  a in and  photoresist  (Shipley HR316) was spun onto the wafers followed by a  soft  bake to dry out the photoresist. The emitter mask (Fig. 3.3)  42  for  the  MIS  BJT  experiment  was  used  photoresist using a Karl Seuss model 505  to  pattern  the  maskaligner.  Once  the wafers were developed and hard baked, they were  scribed  into quarters for studying the Mg etching process.  Nitric acid was  chosen  to  because it is commonly used in producing  press  dyes  be  the  etchant  commercial  [21],  A  Mg  number  for  Mg,  etching  for  of  different  concentration HNO^ solutions was used to try to optimize the Mg etching process. It was found that a 0.1 % solution  gave  a satisfactory etch time of 3 minutes with minimal amount of overetching. Any solution with a  higher  concentration  was  found to lead to significant overetching. With extreme device structures with dimensions in the order of 1  care  m®  can  be patterned by using the 0.1 % etchant solution.  Ti patterning can be done by using low concentration HF solution. The Ti etching process was not studied *  until  the  actual Ti-I-S emitter transistor fabrication, where a 1 % HF solution was used. Although the Ti emitter was the devices seemed to suffer from some  loss  underetched, of  the  ultra  thin layer of tunneling oxide. This is most likely due to the fact that the etch rate of silicon oxides in HF solution is much faster than that for Ti. Further study must be made concerning Ti patterning, if improvements in the performance of Ti-I-S devices are to be made.  43  3.2.1. Fabrication of Mg-I-S diodes A set of Mg-I-S diodes was fabricated using the patterning scheme, in order producing  such  junctions  to  study  with  the  the  feasibility  proposed  procedure. Both the structure and the  of  of  patterning  processing  the Mg-I-S diodes were similar to that  direct  the  steps  of  Al-I-S  and  Ti-I-S diodes. The only difference was that the emitter mask (Fig. 3.3) for patterning the emitter metal in the MIS was used together with the proposed  method  for  BJT,  patterning  the Mg instead of using the shadow mask technique.  The  300  Mm * 300 Mm metal pattern was used as the diode contact.  The wafer used in p-type  with  nominal  this  experiment  resistivity  orientation. The processing steps  of  was  boron  doped,  2 fi-cm and  <100>  prior  to  barrier  deposition were identical to those of the Al-I-S and »  metal Ti-I-S 0  .  dot diodes fabrication. After the thin oxide growth, 3500 of Mg was deposited on top of the oxide covering the wafer. Then,  the  Mg  was  patterned  using  the  showed minimal amount of over etching. No noticeable oxide  was  found  electrical properties of the diodes. 3.3 Experimental results and discussion  on  entire  technique  discussed in the previous section. The resultant Mg  to the thin tunneling  A  contact damage  examining  the  10um x 10um MIS BJT e m i t t e r c o n t a c t pad  Fig. 3.3. The e m i t t e r mask for t h e MIS BJT experiment -f*  45  The current-voltage characteristics of the  dot  made with the three different barrier metals were Observation of an ideal p-n confirm  that  these  junction  metals  were  diodes  examined.  characteristic  properly  would  inverting  the  semiconductor surface. Both the Al and Mg diodes were tested using the HP4145 semiconductor the  Ti  diodes  were  ball-shaped probe  in  tested an  parameter manually  attempt  analyzer, with  to  a  reduce  while platinum  the  contact  resistance.  In all three cases, the log(J) versus V in  Fig  3.4  to  Fig  3.6)  showed  curves  typical  p-n  (shown junction  characteristics with a recombination - regeneration dominant region at low bias, a minority  carrier  injection-diffusion  dominant region with ideality factor nearly 1 at the  medium  biasing range, and finally a tunnel limiting region at bias. The Al  and  Ti  diodes  characteristics  were  identical at both the low and medium  biasing  given  similarity  substrate  resistivity.  This  range is  expected because the work functions for the two almost  the  characteristics i  same. for  The  change  wafers  with  in  almost for to  metals  tunnel  different  resistivities at medium bias was also observed  high  substrate  doping  density  increases.  The  I ]  are  substrate for  the  less  Al the  inverted  surface would have less minority carriers available for i  be  limiting  and Ti diodes. The tunnel limiting current decreases as •  a  the  46  4 i  < o vx o  o  V D (V)  Fig. 3.4. Log(J) vs V curves for the Al-I-Si dot diodes  V D (V)  Fig. 3.5. Log(J) vs V curves for the Ti—I—Si dot diodes  48  V D (V)  Fig. 3.6. Log(J) vs V curve for the Mg—I—SI diode  49  bulk diffusion current carrying process, hence current  would  be  decreased.  However,  this  characteristics was not observed at  high  because  and  of  high  level  injection  the  overall  change  in  bias,  presumably  series  resistance  effects.  The above results show that the metals are  inverting  the  p-type  causing the electron minority  three silicon  carrier  and  Mg  barrier  properly,  current  dominant current component. Fabrication direct patterning of both Al  chosen  of  to  MIS  be  BJTs  metalization  thus the with  can  be  achieved with no noticeable damage or contamination  to  the  underlying tunneling oxide. Therefore, no reduction  in  the  performance of MIS BJTs due to surface state effects at  the  metal and the thin oxide interface should occur. In the case of Ti, the etchant used in the damaged the stabilities.  underlying  experiment  tunneling  oxide  seemed and  to  have  caused  poor  50  Chapter 4  MIS BJT fabrication The MIS BJTs used for the  MIS  BJT  experiments,  prepared partly at Carleton University and  partly  were  at  UBC.  The processing steps carried out at Carleton and UBC will be discussed separately in the following sections.  4.1 Overview of processing N-type,  <100>  orientated  wafers  with  substrate  resistivity of 3-5 fl-cm were used as the foundation for  the  M-I-p/Si-n/Si structure transistors (shown in Fig. 4.1). The extrinsic base region diffusion at  was  Carleton  formed  by  University,  performing  then  the  a  boron  wafers  were  shipped to UBC for the intrinsic base implantation of boron. The intrinsic base was formed by ion  implantation  implantation energy of 50 keV for the BJTs and 30 10  12""2 cfn  or  keV 5x10  for  the  12 -2 cm ,  second then  first  with  the  with  batch  dosage  implanted  of  of  an MIS  either  bases  were  annealed at 950°C for 30 minutes. The reasons for having two batches of devices was because the first exhibited relatively  low  gains.  The  modified on the second batch to try, to performance. Also, ready-made  this  polysilicon  compare MIS BJT and  batch devices  polysilicon  of  batch doping improve  wafers  which emitter  of  devices  profile the  was  device  contained" some  could  be  used  transistors.  to The  Emitter metal Base metal (Al)  Tunneling oxide 0 T  V////Z///A  SiO-  YzzzzzzzzzA  p+  p+ Intrinsic Base overlap n substrate  Collector metal (Al) Fig. 4.1. Structure of the MIS BJT showing intrinsic base overlap  52  1o  doping profiles for the 10  -2  cm  implantations, as  computed  from SUPREM II simulations are shown in Fig. 4.2. The  first  batch was labelled GT-G, and the second GT-J. Once the intrinsic base region was formed,  the  were shipped back to Carleton. The implantation  wafers  oxide  over the base contact window and the emitter contact region was removed,  mask window  a layer of Lotox was deposited, and was  patterned on the wafer to protect the surface of the emitter contact. The base contact was  patterned  patterning scheme as  emitter  in  the  after 1 Mm of Al was deposited by  using contact  e-beam  patterned contacts were sintered in a  the  direct  patterning,  evaporation.  hydrogen  environment  at 450°C for 10 minutes. A second layer of protective was deposited on top of the  entire  wafer  emitter contact windows. This Lotox layer  except was  cleaning  steps,  while  allowing  Lotox  for  the  intended  protect the structures formed on top of the wafer proceeding  The  from  the  to any  emitter  contact window to be cleaned. The finished wafers were shipped to UBC for completion of the fabrication of the  then MIS  BJTs.  The remaining processes to complete the MIS BJTs  were:  deposition of the back collector contact, growth of the thin tunneling oxide and lastly,  emitter  metal  definition. Before performing any of the  deposition  above  steps,  and the  53  8 -1  7 -  0.0  •  I  0.1  0.2 Base width (In microns)  Fig. 4.2. Doping profile of the intrinsic base region  54  exposed intrinsic base surface had to be cleaned in order to keep the level of contamination low. This is thought necessary for reducing the  number  of  surface  to  be  states  and  ensure  the  cleanliness of the silicon surface of the MIS junction,  and  remove any native oxide on  RCA  ensuring the growth of a good quality oxide.  4.1.1 Pre-treatment The  pre-treatment  step  is  the  designed  silicon  to  surface.  cleaning procedure was used on the first batch of to perform the pre-treatment step. However, Lotox layer failed  to  during the RCA clean.  protect The  base  the  The MIS  BJTs  the  protective  underlying  structures  contact  metalization  completely removed. A modified RCA cleaning  was  procedure  with  1/10 of the cleaning time and leaving the HF  cleaning  step  to the last,  loss  base  was  also  tried;  significant  contact was still observed. In view of  these  of  difficulties,  the pie-treatment step was reduced to a single 10 second dip in 10% HF.  4.1.2 Collector metal deposition The MIS BJTs on each wafer shared  a  common  collector  which was the substrate itself. Instead of patterning a of collector contacts on the front of  the  wafer,  a  back contact was used to establish connection to the o  collector. 5000A of Al was deposited on  the  back  set large  common of  each  55  wafer using the CHA vacuum chamber.  The  sintering  of  the  back contact was performed at the same time as the tunneling oxide growth.  4.1.3 Oxidation The oxidation process for the MIS BJTs was the same that previously described for the MIS varying  the  time  and  diodes,  temperature  of  as  except  that  oxidation  was  investigated. The change in thickness of the tunneling oxide can  be  observed  by  its  effect  on  characteristics. A thicker tunneling  the  MIS  oxide  diode  would  I-V  lead  to  higher series resistance, principally due to the decrease in tunnel probabilities.  Three sets of  MIS  dot  diodes  with  different  growth conditions were fabricated and tested effects of oxidation temperature growth?  conditions  for  these  and  to  study  duration.  diodes  were  oxide  The  500°C  the oxide  for  20  minutes, 500°C for 50 minutes, and 600°C for 20 minutes. The log(J) vs V curves for  these  diodes  (shown  Fig  4.3)  showed that the effective series resistance for diodes  with  lower oxidation temperature was less than  that  in  of  devices  fabricated at higher oxidation temperature. For diodes " with the  same  oxidation  temperature  but  durations, the effective series resistance increased as the duration was increased.  different seemed  growth to  have  56  V D (V)  Fig. 4.3. Electrical properties of Al-I-Sf dot diodes with different oxide growth  The change in effective series resistances expected, that the tunneling oxide the growth temperature  or  the  thickness  growth  be  as  increases  as  duration  However, for the low temperature oxide growth oxide thickness is considered to  showed,  self  increase.  process,  limiting  the  for  a  given temperature [3], This result contradicts the result of the above experiment. There are discrepancy. First, the  oxide  self-limiting thickness  for  Secondly, the oxide growth  two may  the may  ways not  to  explain  the  have  reached  its  conditions not  entire wafer, leading to pin holes  be or  investigated.  uniform small  over  the  regions  with  thinner oxide than elsewhere. As the oxidation duration increased, these thinner regions would continue to  oxidize,  while the rest of the oxide would be self-limited further growth. The second case was likely to be for the discrepancy, since a  much  decreased  saturation current and recombination-generation low bias were observed in the case  of  diodes  was  from the  any cause  reverse  bias  current with  at  growth  conditions of 500°C for 50 minutes.  In the MIS  BJT  experiments,  the  growth process was chosen on account  of  500°C, its  20 lower  minutes series  resistance, and its use in previous studies [3,4]. It may be better to choose a different oxidation device stability.  process  for  better  4878  4.1.4 Emitter deposition and definition The emitter metal was deposited on  the  front  of  the  wafer after the oxidation process. A brief discussion of the choice of metals, and patterning of the metals was presented in the previous chapter.  The  actual  emitter  metalization  procedures were as follows. o  The emitter metal thickness was chosen to This  should  give  acceptable  sheet  be  resistivity,  having to use unsatisfactorily long etch times the three metals. Both Al and Ti  were  tungsten coil as the heating element Whereas Mg was evaporated using a boat as the evaporation source,  in  for  the  the  A.  without any  evaporated  "Drummel" in  3000  using  of a  CHA  chamber.  type  tantalum  CHA  chamber.  acceptable deposition rates for both Al and Mg were about o  to 10 A per second, whereas the deposition rate  5  Ti  was  A  per  method  as  pattern  the  emitter metal. The etchant for the patterning of Al was  50%  phosphoric acid heated to  was  limited by the evaporation power supply to  of  The  about  2  second. The  direct  patterning  photolithographic  described in the previous chapter was used  60°C,  and  the  to  etch  rate  o  about 300 A/min. For patterning  Mg,  0.4  ml  of  HNC>3  was  diluted with 400 ml of DI water to make a 0.1% HNO, etchant.  59  The etch time for patterning 3000 A of Mg on was about 5 minutes, giving an o  average  a  etch  full rate  wafer of  600  A/min. However, if the above-mentioned etchant were used pattern quarter wafers or half wafers, increase in overetching  was  then  observed.  a  Ti  significant  patterning  performed by using 1 % HF acid at room temperature o etch rate of about 600 A/min.  Because  HF  was  was  with  attacks  dioxide, a portion of the underlying oxide  to  an  silicon  damaged  by  the etchant, resulting in less stable devices. 4.2 The transistor structure and test patterns Two batches of MIS BJTs were the  possibilities  of  fabricated  implementing  MIS  for  BJTs  studying in  VLSI  applications. The performance and relative stability of  the  di fferent emitter metals and polysilicon emitter devices can also be compared. The first batch of devices was  fabricated  on MR-20 and GT-G series wafers. They were  solely  study -the relative  effect  of  stability.  different The  second  fabricated on GT-J series wafers, compare  metal  transistor  emitters  structures  and (see  used  metalizations batch and  of they  polysilicon Fig.  ,1.2.  and  their  devices were  was  used  emitters. and  to  to The  1.3.)  were  identical in both batches of wafers.  In the first batch of MIS BJTs, the transistor with the largest emitter contact  area  was  the  one  chosen  to  be  60  studied, from a number of different sized transistors on the wafers. This was because the direct shown some damage to  the  emitter  patterning metal  for  scheme the  had  smaller  devices.  The 10 ym x 10 mhi devices with different intrinsic base region overlapping(refer  to  Fig.  4.1)  were  studied  and  compared with polysilicon devices of the same configurations on the same wafers, for the second batch of smaller sized transistors were studied as  MIS they  BJTs. were  The of  a  more reasonable size for VLSI applications.  A Van der Pauw cloverleaf for measuring base resistivity was also available for  the  checking  intrinsic the  base  implantation. The structure for such a test pattern is shown in Fig 4.4.  Tfro  separate  voltage  vs  required to determine the base  current  measurements  spreading  resistance  were using  the Van der Pauw method. First of all, the resistance in the ab direction was measured by injecting a charge flow through node b, a and measuring the potential drop across node  c,d.  The resistance in the ab direction is given by:  Secondly, the resistance in the  orthrogonal  direction  was  61  d  j  Contact window  •I  C  a  Intrinsic Base region  • •  Metal pad /  b  Fig. 4.4. Structure of the Van der Pauw test pattern  measured similarly by injecting the current through node b,c and measuring  the  potential  drop  across  node  a,d.  The  resistance in the be direction is then: R,  =  bc  V  ad  J  bc  (4.2)  Once the two orthrogonal resistances  were  known  then  the  spreading resistance could be computed from: 's  =  2 In 2  < R ab  + R  <4'3>  bc >  R ab where f(—= ) is known as the Van der Pauw function, and it be  is equal to 1 , if R ^  is the same as R^  for  a  symmetrical  test pattern.  The  spreading  resistance  for  the  first  transistors was measured and checked against the simulations  for  the  resistances  were  of  implantation the  same  order  process. of  measured value was 25 KQ/square, while the of 17 Kft/square was in close agreement.  batch  of  SUPREM  II  The  magnitude. simulated  two The value  63  Chapter 5 Temperature stress tests  As discussed in chapter 1, the major concern  with  MIS  BJTs is the stability of the thin oxide layer. To study this phenomenon we subjected MIS BJTs to temperatures  which  the  devices would likely be exposed to in commercial processing, e.g. temperatures of up to 400°C as may wirebonding  and  packaging.  chapter are referred to as  The  be  tests  temperature  encountered  reported stress  in  tests.  in this The  devices were heated to a certain temperature for a specified time and then returned to room temperature  for  measurement  of J-V characteristics.  5.1 The experimental setup An HP4145 semiconductor parameter analyzer was used perform  all  the  measurements  of  the  to  transistor  characteristics at room temperature. The log(J„ & J_.) vs V C B BE curve!  with  a  small  collector-base  bias  voltage  recorded after each stress, in order to observe in  device  characteristics.  The  there  was  no  degradation  jLn  change  base-collector  characteristics were measured from time to that  the  were  the  time  to  ensure  base-collector  junction.  A Statham convection oven was used  to  heat-treat  the  64  MIS BJTs for temperatures up to 265°C. A 1 nitrogen  into  the  oven  was  used  to  ensure  environment while stressing the devices. test was placed in the oven at room temperature  was  ramped  up  to  the  instant  The  flow an  the The  that  temperature was reached to the instant of  durations  desired turning  stress off  oven's heating element. The devices were allowed to cool room  temperature  with  the  nitrogen  flow  test  the to  maintained.  Therefore, the effective stress times were longer recorded values, but by performing the  the  stressing  stress  the  under  then  desired  of  inert  device  temperature,  temperature in the nitrogen ambient. were measured from  L/min.  than  the  way  the  this  chance of reoxidation by exposure of the heated  devices  to  atmosphere was minimized. However, some recovery process was observed when leaving the devices at  room  temperature  and  atmospheric environment for around 20 Hours.  A Minibrute quartz furnace was used to at temperatures of  400°C  and  higher,  stress  since  devices  the  maximum  temperature setting for the Statham oven was only 265°C. The quartz furnace  was  pre-heated  to  the  desired  temperature before placing the wafers into  the  stressing furnace.  nitrogen flow of 1 L/min. was also used to ensure  an  A  inert  environment for the wafers. The stress duration in this case was measured from the instant of placing the wafers furnace to the instant of removing them. The  heated  in  the  wafers  65  were sprayed with Freon preventing the heated  gas  for  wafers  a  from  faster being  cooling exposed  while to  the  atmosphere, at the moment of their removal from the furnace.  5.2 Comparison of Mg, Al, and Ti devices The 12  1x10  GT-G  series  wafer  with  an  implant  dosage  of  performance  of  -2  cm  was used to compare the relative  Mg, Al and Ti MIS BJTs. The GT-G-4 wafer  was  scribed  into  quarters, which were then processed simultaneously. However, during the emitter metal deposition step, the three metals  were  deposited  separately.  By  so  emitter  doing,  the  properties of these devices should be identical, except  for  the emitter metals, allowing a fair comparison between them. The initial current gain of all the MIS BJTs (refer Fig.,5.1) was very similar, with the Mg devices  giving  highest gain of about 650 and both the  Ti  exhibiting gains of about  550.  The  Al  and  percentage  the  quarter wafers gave similar  Mg  and  gains  to  Al the  whereas the yield was only 20% in the case  for  the  on  the  stated Ti  loss  of  interfacial  oxide  during  the  values, devices.  The relatively low yield for the Ti devices was due major  devices was  devices  of  the  yield  quite good for the Al and Mg devices, but was poor Ti devices. About 70% of  to  Ti  to  the metal  patterning step. Therefore the temperature  stress  test  the  Ti-I-S  junction  Ti  devices  reflects  not  only  the  on  66  100  -  0 oV,.  oV,.  oV,.  o\0  <j\  .  o\ .  .  oV..  Temperatures and durations of stresses. Fig. 5.1. Degradation of current gains for the GT—G series device?  67  stability  but  also  the  suitability  of  the  fabrication  process.  The Gummel plots for GT-G  series  MIS  BJTs  three different metals after various stages stressing, are shown in Fig. 5.2  to  5.4.  of  with  the  temperature  The  large  base  current at low bias, with ideality factor being close  to  for this batch of devices suggested that the relatively gains could be due to region  recombination.  responsible  for  this  large  emitter  Two  mechanisms  large  /  base  low  space-charge  which  recombination  2  might  be  current  are:  insufficient annealing of the base implantation  leading  short  penetration  carrier  lifetime,  and  emitter  through the thin oxide leading to states. These two mechanisms  an  would  metal increase  also  in  account  to  surface for  the  relatively low current gains for these devices.  Three devices from each quarter throughout the stress sequence,  while  wafer  were  other  monitored  devices  were  randomly checked in order to ensure that the degradation  of  the devices was not local. The measured current gains of the three devices with the highest initial gain  for  different metallizations are shown in Fig 5.1. gains of the rest of the devices on the same also degraded with the same trend.  the The  quarter  three current wafer  68  VBE  (v)  Fig. 5.2. Gummei plots for M g - I - S i transistor  69  V B E (V)  Fig. 5.2. Gummei plots for Mg-I-Si transistor  70  VBE  (V)  Fig. 5.2. G u m m e i plots forM g - I - S itransistor  / 1  Physical degradation of the Mg-I-S and was also observed. The  Mg  emitter  Ti-I-S  changed  from  greyish colour to dark brown and the texture changed from  small  uniform  grains  to  devices  of  large  a  light  the  metal  non-uniform  grains, when the stress temperature was increased to 200°C. The Ti emitter metal changed from  around  black to a reddish  colour when the stress temperature was around 200°C.  The principal manifestation of degradation in all three MIS BJTs was an increase in temperature stress. However,  base the  current  with  collector  virtually unchanged during moderate stress  increasing  currents until  the  currents were comparable to the collector currents. stressing on the devices, showed gradual loss of action, as the base  currents  continued  to  were base  Further  transistor  rise  and  the  collector currents began to decrease. * 5.3. Comparison o£ Mg and Polysilicon devices A number of the GT-J series wafers, with implant dosage of either 1x10 1 2 cm~ 2 or  5xl0 1 2 cm~ 2  with  both  Mg  and  Al  metalizations were fabricated to try to optimize the MIS BJT performance. It was found that the  better  MIS  BJTs  were  those that had the lower implant dosage and Mg metalization, as expected. The GT-J  series  wafers  also  polysilicon emitter transistors available  had  a  adjacent  set to  of the  72  MIS BJTs on the same wafers. This enabled the study  of  the  effect of different emitters on otherwise identical devices.  The highest gain devices for this set  of  wafers  were  the Mg devices; they showed gains of the order of 3,500. The polysilicon devices gave gains of 3,000 and the best gainfor the Al devices was 1500. The percentage yield for this batch of devices were very good. The yield of the devices wafers having gains in the same order of magnitude  on  the  for  all  three different emitter devices was close to 90%. The log(J) vs V B E curves (shown in Fig.5.5 devices  and  polysilicon  &  5.6)  for  both  devices  were  almost  the  Mg  identical  initially, with the Mg devices having a slightly larger base recombination current  at  low  bias.  However,  seemed to have higher maximum gain at polysilicon devices had a more  optimal  consistent  Mg bias,  gain  devices while  throughout  the operational bias range.  The  devices  were  left  atmospheric environment for 1  at  room  week,  characteristics were measured again.  and No  temperature then change  in  an  the  device  in  device  characteristics was observed, showing that the MIS BJTs were quite stable in room temperature. However, after the devices were heat treated at 200°C for 1 hour, the Mg devices showed the same degradation mode as the previous batch of MIS BJTs. The Mg metalization changed from a light  greyish  color  to  73  VBE (V)  Fig. 5.5. Gummel plots for GT-J series Mg-l-SI transistor  74  VBE ( V )  Fig. 5.6. Gummel plots for GT-J series polysilicon emitter transistor  75  dark brown with large non-uniform grains. The of the Mg devices degraded to  essentially  current  zero  gain  due  to  large increase in the base current at low bias. Whereas polysilicon device characteristics were virtually by the temperature stress, except for a slight base  current  at  large  base-emitter  increase  bias.  After  polysilicon devices were all dead. The log(J) vs  V Dri BE  (Fig 5.6.) showed a short-circuit in base-emitter  The  base-collector  polysilicon  devices  essential  junctions  were  for  checked  to  curve  zero.  both ensure  log(j ) C  (Fig 5.7 & 5.8) before and after stress  the  junction,  Mg-I-S  and  that  the  degradati on mode of the devices was entirely due to at the base-emitter junctions. The  in the  hour,  was  the  unchanged  polysilicon devices were stressed at 400°C for 1  and the collector current  a  vs  showed  characteristics in both devices, while a small  effects  Vn CB  curves  good  diode  increase  in  J c atJ low bias was observed in the case of Mg-I-S devices.  5.4. Discussion In the case of Mg and  Al  devices,  the  base  curves depart from a logarithmic dependency on  current  base-emitter  bias in the low bias region after temperature  stressing  200°C for 1  respectively.  hour  Attempts were made  and to  400°C  for  simulate  ll the  current-voltage curves with the MIS  hours form  BJT  of  model.  these The  of  base model  76  V B C (V) Fig. 5.7. Log(Jo) vs V B C curves for Mg—I—Si transistor  77  Vfec (V) Fig. 5.8. Log(Jc) vs V B C curves for polysilicon emitter transistor  78  parameters such as oxide thickness, metal work function, and carrier lifetime in the base region were varied over of physically realistic ranges (refer to Fig. 2.6). Yet, none of  the  changes  Fig.  in  resulted in the experimentally observed  2.3  these form  a  set  through  parameters  of  the  base  current. However, the actual results were well described adding a resistive  shunt  current  current exhibited by the device  component  prior  to  to  any  the  by base  temperature  stress. This suggested that temperature stressing of Mg Al devices leads to gradual replacement of the MIS  and  junction  by an ohmic contact. In the case of Al devices, for example, a  log(J B )  vs  VBE  curve  resulting  from  the  combination of the unstressed junction and a 3.5 O-cm  parallel  resistance  (shown in Fig. 5.9) gave an excellent fit  to  data obtained after stressing at 400°C for 1 Hour. The contact resistance as compared to 5x10~ 4 fi-cm2 for Al/pSi  contacts  resistivity  to  used  silicon  here  [22],  with  the  could  indicating that only small areas of  be the  of the high  typical  intrinsic  base  interpreted interfacial  as oxide  were penetrated by the metalization. This would suggest that only  selected  regions,  most  probably  "weak  spots"  or  pinholes were present on the thin interfacial oxide  leading  to potentially unstable devices. Metal  through  penetration  the insulating oxide and partially into the base  region  further  increasing  suggested  by  the  observation  collector-base recombination current  at  of low  bias  in  is  the  79  VBE  (V)  Fig. 5.9. The effect of shunt resistance on Al—I—Si transistor  log(J c ) vs V C B curve as the temperature stressing increased. Metal  penetrated  increase  in  into  majority  the  base  carrier  region  would  concentration,  cause  an  leading  to  higher recombination current at low bias.  In the case of Ti devices, the log(J B &J c ) vs V B E curves did not show a gradual replacement of the MIS junction by an ohmic contact. The base current curves did not the logarithmic  dependency  on  base-emitter  values, but the extrapolated saturated zero V fiE increased  with  depart  increasing  bias  current stress.  showing  that  the  MIS  junction  at  low  density The  factors for these set of base currents were all to unity,  from  ideality  very  was  close  gradually  shifting from a minority carrier dominated junction  to  one  that was dominated by majority carriers without becoming ohmic contact. A major decrease in collector stress  complemented  collector current is injection  current.  described by  the  above  determined This  penetration  by  the  degradation of  Ti  current  observation,  through  can the  oxide. The combination of the work function of  an  after  since  minority  mode  at  the  carrier be  well  interfacial Ti  and  the  intrinsic base doping density will cause a Schottky  barrier  when the metal is in contact with the base, whereas  in  case of Mg and Al, although having similar  work  the  functions,  these metals are good doping materials which would result in formation of an ohmic  contact  when  in  contact  with  the  81  p-type base at high temperature. The extrapolated saturation current density was 5.7x10~ 7 A/cm 2 after a stress for 3 hours, whereas the Ti/pSi  Schottky  would have a saturation current density  of  barrier  265°C  junction  1.7X10~ 4  of  A/cm 2  with barrier height of 0.6leV [23], showing that, either the junction did not completely  reduce  to  a  Ti/pSi  Schottky  barrier or only small areas of the oxide were penetrated  by  Ti to form Schottky barriers. The degradation mode cannot be easily determined, but the latter one mentioned to  be  more  likely,  since  it  is  consistent  would  seem  with  the  interpretation of the results for the Mg and Al devices.  The rapid degradation of the polysilicon devices is due to the overlaying metal that  was  used  to  reduce  resistance to the polysilicon emitter. It is not of an intrinsic device failure mode since the treated to temperatures of 500°C  during  both  of  which  are  acceptor  Penetration of these metals at will cause the n + doped become p-type, hence  polysilicon  shorting  the  [24],  the  was  before  observed.  Mg  in  were  or  doping  Al, Si.  temperature  stressing  emitter  to  gradually  base-emitter  junction.  Since the diffusion constants for these high for polysilicon  devices  either  impurities high  indicative  processing  metal?deposition, but no loss in performance The metal used for this experiment were  contact  device  rapidly at high temperature stress, while  dopants tends  are to  remaining  quite degrade stable  lower temperature stress.  •J  83  Chapter 6 Series resistances measurement As discussed in Chapter 1, a potential drawback to use of MIS BJTs in high speed applications is of a thin insulating layer  in  the  emitter  the  the  presence  current  path.  Because high gains are possible with MIS BJTs, some of gain can be traded-off against the base  series  Reduction of this resistance means that the  resistance.  emitter  resistance can become the dominant resistance  this  series  limiting  the  high-speed performance of the transistor. It is not easy obtain  an  accurate  measure  of  the  emitter  However some attempts to measure R E in MIS  BJTs  to  resistance. were  made  and are reported in this chapter.  6.1. Methods of measurement The re are two commonly used methods of determining  the  series resistances of bipolar transistors. They are the open collector method [25] and the method proposed Tang {14]. Both determine  the  of  these  effective  methods series  were  by  used  resistance  to of  tunneling oxide. However, the first method will the emitter series resistance, whereas method  will  yield  both  the  resistances.  6.1.1. Open collector method  emitter  the and  Ning try the only  Ning base  and  and  to thin  yield Tang series  84  This method is based on measuring the emitter and collector contacts as  the a  voltage  function  across of  base  current injected from a current source. The HP4145 parameter analyzer was setup to perform such a resulting V C E vs Ig  curves  for  both  measurement, Mg  and  and  the  Polysilicon  devices are shown in Figs. 6.1 and 6.2 respectively.  It was found that neither of the V„„ vs I B perfectly linear. The  slope  at  low  current  curves is  was  slightly  greater than that at high current. This is partially due the nature of  it  has  effect,  and  partially due to the non-linear nature of conduction in  the  neglected  the  the  method  base  of  measurement,  conductivity  since  to  modulation  thi n insulator. The estimated emitter series resistance  for  2  the 10xl0Mm  Mg and Polysilicon devices ranged  from  90  to  120 fl and 75 to 95 fl respectively. 6.1.2; Ning and Tang method The Ning and Tang method [14] relies on the I  B  &  I  C  vs  V  BE  curves  for  an  ideal  bipolar  fact  that  transistor  without any series resistance and high injection effects are strictly proportional to exp(qVBE/JcT) .  Any  deviation  the ideal I B Q and I C Q curves at high bias is assumed  from to  be  caused by either the emitter or base series resistances. The deviation in I R can be expressed by:  85  lB (mA)  Fig. 6.1. VQ£ VS lg curves for M g - I - S i transistor  I B (mA)  Fig. 6.2. VQ£ VS lg curves for polysilicon transistor  87  W  ^  Where R g is  =  "P^^E the  1  ^  +  emitter  :  BRbi  +  I  BRbx)/kT)  series  (6  resistance,  extrinsic base series resistance, and R b - is base resistance.  These  series  resistance  Rbx the  '1)  is  the  intrinsic  components  are  shown in Fig 6.3. Since 0 = I c /lg, the expression (6.1) can be rewritten as (kT/qIc) In (I B 0 /I B ) = (Re + R b i / 0 ) +  (R  E  + R  bx}/'  (6  The term Rfai/0 can be treated as a constant, since  '2>  Rfai  can  be shown to be proportional to 0 at all current levels [26]. When (kT/qIc) ln(I B O /I 0 ) is plotted against 1/0, of the curve will then be (Rfi + R fcx )  and  the  the Y  slope  intercept  will be (Re + R b i /0). However, H b i / 0 is generally small  and  can be neglected in the expression (6.2). Therefore  R„  can  be evaluated directly from the intercept, while Rfax  can  be  readily evaluated from the slope of the curve.  In the actual determination of  the  using the Ning and Tang method, values of  series I_ B  resistance  and  I  C  were  extracted from the log (lB & i c ) vs V B £ curves for both  the  Mg and Polysilicon devices. The l B g values were extrapolated from the values of the assumption of  at V B E = 0.7 V back to V B E = the  ideality  factor  being  0V  with  unity.  The  (kT/qIc) ln (I B Q /I B ) vs 1/0 curves for both types of devices are shown in Fig 6.4 and 6.5. However, these curves  show  a  H P  E  B  o  o  s  j  "Re  - A A A / R  Rbx*  V  W  bi  n  Fig. 6.3. Series resistance components  CD  a>  89  1/P  Rg. 6.4. (kT/qlc)'n(l0Q/lg) vs 1/p curve for Mg-I-Si transistor  90  200  180  "  160 -  140 -  E O  120 -  60  "  40 -  20 -  0  i ) i | i | i | i | i | i | , , , ! ,, 0.00  0.01  0.02  0.03  0.04  0.05  1/P  Fig. 6.5. (kT/qlcJlnOgc/lB) vs 1 / p curves for polysilicon transistor  91  negative slope while the intercepts were at around 115 fi for the Mg devices and around 75 fi for the Polysilicon The  intercept  values  representing  resistances R E agree well  with  the  the  devices.  series  results  of  emitter the  open  collect or method, but the negative slope would mean that the extrinsic  base  series  resistances  was  negative!  effective negative base series resistances were due fact that dependence of l B on V B E ,  at  devices under test, was exponential  high  bias  instead  of  The  to  the  for  the  the  ideal  linear dependence.  6.2. Discussion The absence of a linear l B , V B E at high bias means that the Ning and Tang method is not helpful series resistance of the BJTs used in the open collector results  appear  in  estimating  this  work.  However,  to  be  reasonable.  specific contact resistivities for the  Mg  and  devices were around 110 nil-cm2 These values  are  high  and 85  compared  to  M^-cm 2  high  respectively.  conventional  for the MISETs and Polysilicon  devices  drawback in implementing these  device  applications.  series would  The  Polysilicon  bipolar  transistors, which have corresponding resistivities order of 1 M&-cm . The relatively  the  of  the  resistances be  structures  a  major  in ' VLSI  92  Chapter 7  Conclusion  The main conclusion to be drawn from the work in this thesis is that MIS limitations  which  BJT  may  devices  have  prevent  reported  some  their  severe  successful  implementation in a commercial IC processing technology.  The  principal  degradation  of  temperatures. excess of  drawback  common-emitter Magnesium  3000  to  have  temperatures as low as  the current  devices  been  shown  265°C.  with to  devices  is  gain  moderate  at  initial fail  Devices  with  titanium metallization continue to act as  the  gains  in  completely  at  aluminum  and  transistors,  but  with steadily decreasing current gain, until slightly higher temperatures (around 400°C). For all cases the degradation in gain appears to be due  to  changing  emitter/base junction. Shunting of this  conditions junction  at by  metal  from the emitter penetrating the oxide at thin spots in oxide is suggested as being a likely cause  of  the  the  the  results  the  series  observed.  Another  disadvantage  of  MIS  BJTs  is  resistance associated with the thin insulating layer in emitter  tunnel  junction.  Our  measurements  of  the  emitter  93  specific resistivity indicate that a reduction by nearly two orders of magnitude is needed for values of  this  parameter  to reach acceptable levels for VLSI applications.  It is proposed that further  investigated.  the  Chemical  angle-resolved photoelectron helpful  in  complementing  degradtion  of  methods,  spectroscopy, the  MIS  electrical  BJTs  be  such  as  be  very  would  measurements  reported here. Information on the changing oxide composition with temperature stressing, coupled perhaps with the results of  high  resolution  microscopy,  would  cross-section help  confirm  transmission or  deny  whether  penetration into the oxide is, as suggested in this responsible for device degradation.  I  electron metal thesis,  94  References 1. J.E. Dufill, Plessey Research communication, (1986)  Ltd.,  England,  private  2. N.G. Tarr, D.L. Pulfrey and D.S. Camporese, IEEE on Electron Dev., ED-30, 1760 (1983) 3. M.A. Green and R.B. Godfrey, IEEE Electron Dev. EDL-4, 225 (1983) 4. M.K. Moravvej-Farshi, W.L. Guo and M.A. Electron DEV. Letter, EDL-7, 632 (1986). 5. P.C. Hunt, Plessey Research communication, (1986)  Ltd.,  Trans, Letters,  Green,  England,  IEEE  private  6. H. Miyanaga, Y. Kobayashi, S. Konaka, Y. Yamamoto and Sakai, Proc. VLSI Technology Symposium, 50 (1984)  T.  7. H.K. Park, K. Boyer, C. Clawson, G. Eiden, A. Tang, T. Yamaguchi and J. Sachitano, IEEE Electron Dev. Letters, EDL-7, 658 (1986) 8. M.B. Rowlandson and N.G. Letters, ED-6, 288 (1985)  Tarr,  9. P. Van Halen and D.L. Pulfrey, IEEE Dev., ED-32, 1307 (1985)  IEEE  Electron  Trans,  on  Electron  10. A. Neugroschel, M. Arienzo, Y. Komen and R.D. IEEE Trans, on Electron Dev., ED-32, 807 (1985) 11. Z. Yu, B. Ricco, and R.W. Dutton, Electron Dev., ED-31, 773 (1984) 12. J.R. Black, Proc. IEEE 257 (1977)  Reliability  13. R.B. Godfrey and M.A. Green, Vol. 34, 860 (1979)  IEEE  Physics  Applied  Physics  14. T.H. Ning and D.D. Tang, IEEE Trans, on ED-31, 409 (1984)  Dev.  Isaac,  Trans,  on  Symposium, Letters,  Electron  Dev.,  15. A.S. Grove, "Physics and Technology of Devices", New York Wiley, 156-160 (1967)  Semiconductor  16.  Devices  S.M. Sze, "Physics of Semiconductor Edition", Wiley Appendix H. (1981)  2nd  95  17. D.S. Gamporese and D.L. Pulfrey, Physics, Vol. 57, 373 (1985)  Journal  of  Applied  18. A.W. Blakers, M.A. Green, S. Jiqun, E.M. Keller, S.R. Wenham, R.B. Godfrey, T. Szpitalak, and M.R. Willison, IEEE Electron DEV. Letters, EDL-5, 12 (1984) 19. W.Kern and D.A. Puotuien, RCA review, p. 187 (June 1970) 20. D.S. Camporese, Columbia, (1986)  Ph.D.  Thesis,  University  of  British  21. M.J. Collie, "Etching compositions and processes", Ridge, N.J., 73 (1982)  Park  22. H.H. Berger, J. Electrochem. Soc., Vol. 119, 507 (1972) 23. A.M. Cowley, ( 1970)  Solid-State  Electronics,  Vol.  12,  403  24. B. Swaminathan, K.C. Saraswat, R.W. Dutton and T.I. Kammis, Applied Physics Letters, Vol. 40, 795 (1982) 25. B. Kulke and S.L. Miller, Proc. IRE letters, Vol. 45, 90 (1957) 26. D.D. Tang, IEEE Trans. Electron Dev., ED-27, 563, 1980  96  Appendix A. Fabrication Procedures for the MIS BJTs A.l. Fabrication procedure for MR-20 and GT-G devices 1. Mask oxide growth a) RCA clean b) Oxidation: 1100°C  5 Min. preheat in 0 2 5 Min. push in 0 2 10 Min. dry oxidation in 0 2 20 Min. wet oxidation in 0 2 + H 2 0 10 Min. dry oxidation in 0 2 + 2% HC1 10 Min. anneal in N 2 5 Min. pull in N 2 10 Min. cool in N 2  Mask oxide thickness - 0.3 urn 2. Open windows for extrinsic base diffusion a) Use  mask  CU-063-01  pattern the windows,  with  negative  negative  photoresist  photoresist  was  to also  jused to protect the back of the wafers. b) Etched in buffered HF for approximately 4  Min.  bare silicon exposed. 3. Extrinsic base boron diffusion a) RCA clean b) Predep: 1000°C  5 Min. preheat in 0 2 + N 2 5 Min. push in 0 2 + N 2 5 Min. warm-up in 0 2 + N 2  until  97  10 Min. dope in 10 Min. hold in 5 Min. pull in 10 Min. cool in  °2 °2 °2 °2  +  N  2  +  N  2  +  N  2  +  N  2  + dopant  c) Boron deglaze: 30 Sec. in 10% HF d) drive-in: 1100°C  5 Min. preheat in 5 Min. push in  °2  °2  10 Min. dry oxidation in 15 Min. wet oxidation in  °2 °2  +  H  2°  5 Min. dry oxidation in 0 2 +2.5% HC1 5 Min. pull in 10 Min. cool in  °2 °2  Phosphorous backside getter a) Protect wafer fronts with PR,  and  strip  oxide  wafer backs. b) RCA clean c) Predep: 1000°C  5 Min. preheat in 5 Min. push in 0 2 5 Min. warm-up in  °2  +  +  2  N  °2  +  N  2  N  2  10 Min. dope in 0 2 + N 2 + dopant 5 Min. hold in 0 2  +  N  2  5 Min. pull in 0 2  +  N  2  10 Min. cool in 0 2  +  N  2  d) Phosphorous deglaze: 10 Sec. in 10% HF e) drive-in: 950°C  5 Min. preheat in  °2  from  98  5 Min. push in C>2 5 Min. dry oxidation in C>2 20 Min. wet oxidation in C>2 + H 2 0 5 Min. dry oxidation in C>2 5 Min. pull in 0 2 tO Min. cool in C>2 5. Open windows for intrinsic base implant a) Use  mask  CU-063-02  pattern the windows,  with  negative  negative  photoresist  photoresist  was  to also  used to protect the back of the wafers. b) Etched in buffered HF for approximately 4  Min.  until  bare silicon exposed. 6. Implant mask oxide growth a) RCA clean b) drive-in: 1000°C  5 Min. preheat in 0 2 5 Min. push in 0 2 30 Min. dry oxidation in 0 2 +2.5% HC1  '  5 Min. dry oxidation in 0 2 10 Min. hold in N 2 5 Min. pull in 0 2 10 Min. cool in 0 2  7. Intrinsic base boron implant 12 -2 Implant dosage : 1x10 cm Implant energy : 50 KeV 8. Base implant Anneal  99  a) RCA clean b) Anneal: 950°C  5 Min. preheat in N 2 2"/6 Sec. push in N 2 30 Min. anneal in N 2 2 B /15 Sec. pull in N 2 10 Min. cool in N 2  9. Open emitter contact windows a) Use  mask  CU-063-03  with  negative  photoresist  to  pattern window. b) Etch in buffered HF for  approximatly  40  Sec.  until  silicon exposed. 10. Open base contact windows a) Use  mask  CU-063-05  with  negative  photoresist  to  pattern window. b) Etch in buffered HF  until silicon exposed.  11. Lotox deposition Deposit 0.1 Mm undoped Lotox, using 25% SiH 4 and 27.5% 0 2 atJtemperature of 405°C for 6 Minutes. 12. Re-open base contact windows a) Use  mask  CU-063-05  with  negative  photoresist  to  pattern window. b) Etch in buffered HF for  approximatly  50  Sec.  until  oxide  from  silicon exposed. 13. Deposit base contact metal a) Flash dip in  10%  HF  to  remove  native  100  windows b) Deposit 1.0 Mm Al on wafer fronts by e-beam 14. Pattern base contacts a) Use Mask CU-063-06 with Positive photoresist. b) Etch in H3PC>4 at 60°C for approximately 2 Minutes. 15. Base contact anneal Anneal in H 2 at 450°C for 10 Minutes. 16. Deposit protective Lotox layer Deposit 0.2 Mm Lotox using 25% SiH 4 and 27.5% C>2 at 405°C for 12 Minutes. 17. Partial RCA clean The HF clean step was moved to the end and  the  duration  was shortened to approximatly 3 Seconds. 18. Deposit back contact Al o  Deposit 4000 A of Al on wafer front by evaporation in the CHA chamber with filament current of 35 to o  40  amps  and  deposition rate of 10 to 20 A/Sec. 19. Gi?ow ultra-thin tunnel oxide Anneal and grow oxide : 500°C  5 Min. warm up in N 2 20 Min. dry grow in 0 2 5 Min. hold in N 2  20. Deposit emitter metal  o  a) Deposit 3000 A of Al on wafer front by evaporation  in  the CHA chamber with filament current of 35 to 40 amps o  and deposition rate of 10 devices.  to  20  A/Sec.  for  Al-I-S  101  b) Deposit 3000 A of Mg on wafer front by evaporation the CHA chamber  using  a  "Drummel"  type  in  boat  with  filament current of 60 to 70 amps and deposition  rate  o  of 10 to 20 A/Sec. for Mg-I-S devices.  o  c) Deposit 3000 A of Ti on wafer front by evaporation the CHA chamber with filament current o  of  amps and deposition rate of 2 to 5 A/Sec.  90 for  to  in 100  Ti-I-S  devices. 21. Pattern emitter metal a) Use Mask CU-063-08 with Positive photoresist. b) Etch in 50% H 3 P 0 4 at 60°C for approximately 2  Minutes  for Al emitter. c) Etch in 0.1% HNC>3 at 25°C for about 5 Minutes  for  Mg  for  Ti  emitter. d) Etch in 1% HF at 25°C  for  about  5  Minutes  emitter. A.2. Fabrication procedure for GT-J series devices 1. Ma^k oxide growth a) RCA clean b) Oxidation: 1100°C  5 Min. preheat in 0 2  2"/6 Sec. push in 0 2 10 Min. dry oxidation in 0 2 20 Min. wet oxidation in 0 2 + H 2 0 10 Min. dry oxidation in 0 2 + 2% HC1 10 Min. anneal in N 2 2"/l 5 Sec. pull in N 2  102  10 Min. cool in N 2 Mask oxide thickness  0.3 Mm  Open windows for extrinsic base diffusion a) Use  mask  CU-078-01  pattern the windows,  with  negative  negative  photoresist  photoresist  was  to also  used to protect the back of the wafers. b) Etched in buffered HF for approximately 4  Min.  until  bare silicon exposed. Extrinsic base boron diffusion a) RCA clean b) Predep: 1000°C  5 Min. preheat in 0 2 + 2"/6 Sec. push in 0 2 + N 2 5 Min. warm-up in 0 2 + N 2 10 Min. dope in ° 2  + N  2  +  dopant  10 Min. hold in 0 2 + N 2 2"/l5 Sec. pull in 0 2 + N 2 10 Min. cool in 0 2 + N 2 c),Boron deglaze: 30 Sec. in 10% HF d) drive-in: 1100°C  5 Min. preheat in 0 2 2"/6 Sec. push in 0 2 15 Min. dry oxidation in 0 2 15 Sec. pull in 0 2 10 Min. cool in 0.  2  Mask oxide growth a) 10 Sec. dip in 10% HF to remove any contamination from Boron drive-in tube.  103  b) Oxidation: 1100°C  5 Min. preheat in 0 2  2"/6 Sec. push in 0 2 15 Min. wet oxidation in 0 2 + H 2 0 5 Min. dry oxidation in 0 2 +2.5% HC1 5 Min. anneal in N 2 2"/l5 Sec. pull in N 2 10 Min. cool in N 2 Phosphorous backside getter a) Protect wafer fronts with PR,  and  strip  oxide  wafer backs. b) RCA clean Predep: 1000°C  5 Min. preheat in 2"/6 Sec. push in 0 2 5 Min. warm-up in  +  °2 +  N  °2  N  2  N  2  2 +  10 Min. dope in 0 2  +  N  5 Min. hold in 0 2  +  N  2  2"/l 5 Sec. pull in 0 2  +  N  2  10 Min. cool in 0 2  +  N  2  2 + dopant  Phosphorous deglaze: 30 Sec. in 10% HF drive-in: 950°C  5 Min. preheat in  °2  2"/6 Sec. push in 0 2 30 Min. dry oxidation in B  2 /15 Sec. pull in 0 2 10 Min. cool in 0 2 Open windows for intrinsic base implant  °2  from  1 04  a) Use  mask  CU-078-02  pattern the windows.  with  negative  negative  photoresist  photoresist  to  was  also  used to protect the back of the wafers. b) Etched in buffered HF for approximately 3  Min.  until  bare silicon exposed. 7. Implant mask oxide growth a) RCA clean b) drive-in: 1000°C  5 Min. preheat in 0 2 2"/6 Sec. push in 0 2 5 Min. dry oxidation in 0 2 30 Min. dry oxidation in 0 2 +2.5% HC1 10 Min. anneal in N 2  2"/l5 Sec. pull in 0 2 10 Min. cool in 0 2 8. Intrinsic base boron implant Implant dosage : 1x10 12 c m - 2 Implant energy : 30 KeV 9. PSG deposition Deposit PSG using 8.2% SiH 4 , 20.2% SiH 4 /PH 3 and 27.5% for 10 Minutes, and the thickness was  approximatly  Mm. 10. Base implant Anneal a) RCA clean b) Anneal: 627°C  5 Min. preheat in N 2 2"/6 Sec. push in N 2  02 0.25  105  60 Min. anneal in N 2 2"/l5 Sec. pull in N 2 10 Min. cool in N 2 c) Anneal: 950°C  5 Min. preheat in N 2 2"/6 Sec. push in N 2 30 Min. anneal in N 2 2 B /15 Sec. pull in N 2 10 Min. cool in N 2  11. Open emitter contact windows a) Use  mask  CU-087-03  with  negative  photoresist  to  pattern window. b) Etch in buffered HF for  approximatly  1.5 Min.  until  silicon exposed. 12. Deposit first emitter polysilicon a) RCA clean without HF etch. b) Perform HF dip etch immediately before deposition. c) Deposit polysilicon using 19.4% SiH 4 and 15% I for  55  minutes  and  the  resulting  SiH 4 /PH 3  thickness  was  o  approximatly 1000A. 13. Pattern first polysilicon a) Using mask CU-078-04 with positive photoresist. b) Etch in wet poly etch. 14. Open base contact windows a) Use  mask  CU-078-07  pattern window.  with  negative  photoresist  to  106  b) Etch in buffered HF  for  approximatly  4  Min.  until  oxide  from  silicon exposed. 15. Deposit base contact metal a) Flash dip in  10%  HF  to  remove  native  windows b) Deposit 1.0 Mm Al on wafer fronts by e-beam 16. Pattern base contacts a) Use Mask CU-078-08 with Positive photoresist. b) Etch in H3PC>4 at 60°C for approximately 2 Minutes. 17. Base contact anneal Anneal in H 2 at 450°C for 10 Minutes. 18. Deposit protective Lotox layer Deposit 0.2 Mm Lotox using 25% SiH 4 and 27.5% 0 2 at 405°C for 12 Minutes. 19. Re-open first emitter window a) Use mask CU-078-03 with negative photoresist. b) Etch in siloxide etchant until polysilicon exposed. 20. Open second emitter window a) Use mask CU-078-05 with negative photoresist. b) Etch in siloxide etchant until bare silicon exposed. 21. Partial RCA clean 10 Second dip in 10% HF to remove any native oxide on the emitter window. 22. Deposit back contact Al o  Deposit 4000 A of Al on wafer front by evaporation in the CHA chamber with filament current of 35 to  40  amps  and  107  o deposition rate of 10 to 20 A/Sec. 23. Grow ultra-thin tunnel oxide Anneal and grow oxide : 500°C  5 Min. warm up in N 2 20 Min. dry grow in 0 2 5 Min. hold in N 2  24. Deposit emitter metal  o  a) Deposit 3000 A of Al on wafer front by evaporation  in  the CHA chamber with filament current of 35 to 40 amps o  and deposition rate of 10 devices.  to  20  A/Sec.  for  Al-I-S  o  b) Deposit 3000 A of Mg on wafer front by evaporation the CHA chamber  using  a  "Drummel"  type  in  boat  with  filament current of 60 to 70 amps and deposition o  rate  of 10 to 20 A/Sec. for Mg-I-S devices. 24. Pattern emitter metal a) Use Mask CU-078-09 with Positive photoresist. b) Etch in 50% H3PC>4 at 60°C for approximately 2  Minutes  lfor Al emitter. c) Etch in 0.1% HN0 3 at 25°C for about 5 Minutes emitter.  for  Mg  Appendix B. Software listing for the HIS BJT Model  ct> © L i s t i n g of M I S B J T . S at  1 2 3 4 5 6 7 8 9  10  11 12 13 14 '5 18 17 18 '9 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58  11:24:09 on MAY  15. 1988 for C C i d = N S Z E on G  C PROGRAM MIS C WRITTEN BY GARRY TARR SPRING 1982 C LAST REVISION JUNE 7 1982 C C MODIFLIED BY NGAM SZETO FALL 1986 C LAST REVISION NOV 3 1986 C C IMPLICIT REAL * 8 (A-Z) INTEGER CNTRL 1 ,DATFl,FDFL ,FREE, I, IAONR, IFAIL , ITMAX1 , ITMAX2.KR, » LABEL,LP,MIN0.NT1MES.NIRAP LOGICAL NEWY,NEWA,NEWB EXTERNAL COMPF C OIMENSION NT( 100) ,RHO( 100) ,NI( 100) .PK 100) ,SIGMAN( 100) , » SIGMAPI 100) ,CN< 100) ,CP( 100) ,IADNR( 100) ,TAUM( 100) DIMENSION ACCESTI2),X(2),F(2) DIMENSION FREE(1),LABEL(15) DIMENSION FDFL A (81), FDFLC (81), FDFLE( 8 1) , FDFLF( 81), FDFLG (81) C COMMON /AREA1/ CBAR , CBCM. CBVM, CCM, CVM, CHISC , CHISV , CJCM, # C JVM, CPSII, CQS, CTNLCM,CTNLVM, EGAP, EG API , t NC,NA,ND,NI , NNO , NV , 0, PHIO, PNO , I PSISIO,VTHERM, WB,TP,TN,DN,DP,EPSIS COMMON / AREA2/ NT , RHO, N1 . P 1 , CN, CP . TAUM. IADNR , NTRAP COMMON /AREA3/ ETAC , ETAMC, ETAMV , ETAV, JVM.NSURF , PHI, PSII, PSIS . * PSURF , QS, THVM, THCM, U, VBE. VCE . JNO, JNWB , JREC COMMON /AREA4/ CNTRL1,ITMAX1,LP,NTIMES COMMON /AREA5/ CFD1. FDFL A, FDFLC , FDFLE, FDFLF, FDFLG COMMON /SE$$0M/ A(20,22),B(20),Y(22, 2 1) C DATA EPSI0/8.85D -12/,HBAR/ 1.054D-34/.KB0LTZ/1.38054D-23/, f KS/1 1 . 700/,ME/9. 110-31/,PI/3. 14592654D0/, t T/300.000/,VELTH/1.005/ DATA FDFL/2/,DATFL/3/,KR/5/.FREE/'*'/ DATA NEWY/. TRUE./.NEWA/. FALSE./, NEWB/. FALSE./ C C C READ IN DATA DESCRIBING DEVICE C READIKR,5) (LABEL(I),1 = 1,15) 5 FORMAT*15A4) READ(KR.FREE) ITMAX1,1TMAX2,ERR 1,ERR2,DELY READIKR,FREE) CNTRL1 C READ(OATFL.FREE) NA, ND. CHISC, PHIM,MISTAR,D, KI, NCONV , AE , AH READ(DATFL,FREE) WB.TP.TN DO 100 1=1,100 READ(DATFL.FREE) RHO(I) ,NT(I),SIGMANII) , SIGMAPI I), TAUM( I) , I ADNR (I) IF(NT{I) .LE. O.ODO) GOTO 200 100 CONTINUE 200 NTRAP=I- 1 C READ (FDFL. FREE) (FDFLF (I), FDFLA (I), FDFLC (I), FDFLE (I) , t FDFLG(I),1=1,81) C C ECHO PRINT C  Listing of MISBJT.S at 1 1:24:09 on MAY 15, 1986 for CCid=NSZE on G 59  60 61  62 " 64  65  66 67  68 69 70 71  73 74 5 76 77 78 79 80 81 7  82  83 84 85  86 87 88  89 90 91 92 93 94 95  96  97  WRITEILP.10) (LABEL(I).1=1,15)  10 FORMAT(' 1 * , 20X , 15A4///) W R I T E d P , 15) NA,NO,CHISC,PHIM,MISTAR,O.KI,NCONV 15 F0RMATI1X, 'NA=' ,010.3,2*,'ND='.D10.3.2X, 'CHIS=',F5.3 2X 'PHIM=' »F5.3,2X, 'MISTAR=' ,F5.3,2X, ' 0= ' .D10.3.2X, 'KI = ' ,F5 2 2X »'NC0NV=',F7.5/) WRITE(LP,20) KB,TP,TN.AE.AH 20 FORMAT(1X,'WB=\D10.3,2X.'TP=\D10.3,2X,'TN='.D10.3,2X *'AE=',010.3,2X,'AH=',010.3,2X//) IF(NTRAP .EQ. 0) GOTO 400 WRITE(LP,25) 25 FORMAT( 2X ,'I:',3X,'ETA:',5X,'NT:',7X, • SIGMAN : *. 5X . ' SIGMAP: ' , #5X, 'TAUM:',5X,'IADNR:'/) DO 300 1=1.NTRAP 300 W R I T E d P , 3 0 ) I , RHO( I) , NT( I) , SIGMAN (I) , SIGMAP( I) , TAUM( I) IAONR(I) 30 FORMAT( 1X , 13 , 2X . F5. 3, 2X , D10. 3, 2X, 3(D10 . 3, 2X) , 12) WRITEILP,35) 35 FORMAT!///) C r C NORMALIZE POTENTIALS TO KBOLTZ*T/Q AND COMPUTE CONSTANTS C 400 VTHERM=KB0LTZ'T/0 CTUNL=2. OOO'DSQRT ( 2 . 000•ME) /HBAR'DSQRT (Q) CFD1=PI* PI/6.000 EPSIS=KS*EPSIO EPSII=KI'EPSIO NC=NI'DEXPL(EGAP/(2.0D0'VTHERM) )*OSQRT(NCONV) NV=NI*DEXPL(EGAP/(2.0D0*VTHERM))/0SQRT(NC0NV) EGAPI=EGAPI/VTHERM EGAP=EGAP/VTHERM CHISC=CHISC/VTHERM CHISV=EGAPI-CHISC-EGAP PHIM=PHIM/VTHERM C CBCM=EGAPI-2.0D0*CHISC CCM=CHISC-(EGAPI-CHISC) C TNL CM=-CTUNL*D*DSQRT(CCM* MI STAR/EGAPI'V THERM) C  9S 99  CBVM=2.ODO'CHISV-EGAPI CVM=CHISV"(EGAPI -CHISV)  100  101 '02 '03 104 105 106 107 108 109 1'0 111 112 113 1M 115 116  CTNLVM=-CTUNL*D*DSQRT( CVM'MISTAR/EGAPI'VTHERM) c  NNO=NA PNO=NI*NI/NA PHIO=DLOG(NC/NA) PSISI0=D10G(NA/PN0) CJVM=AH*T*T CJCM=AE'T'T CBAR=PHIO+CHISC-PHIM CPSII=D/EPSII/VTHERM CQS=DSORT(2.ODO'KBOLTZ* T"EPSIS) IFINTRAP .EQ. 0) GOTO 800 00 500 1=1,NTRAP RHO(I)=RHO(I)/VTHERM CN(I)=SIGMAN(I)'VELTH CP(I)=SIGMAP(I)'VELTH NI(I)=NC*DEXPL (RHO(I)-EGAP)  L i s t i n g of M I S B J T . S at "7 118 1 19  500 C C  121 122 >23  C 600  120  C  124  125 126 127 128 129 130 131 132 133 134 135 136 '37 138 139 140 141 142 143 144 145 148 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 <65 166 '67 168 169 170 17 1 '72 173 '74  11:24:09 on MAY  15.  1988 for C C i d = N S Z E o n G  P1(I)=NV"DEXPL( -RH0( I) J  READ IN VOLTAGE V ANO A STARTING ESTIMATE FOR PHI READ(KR,FREE,END=1400) VBE.VCE.PHI V8E=VBE/VTHERM  VCE=VCE/VTHERM  C  PHI=PHI/VTHERM  C  U=VBE-PHI GIVEN PHI, COMPUTE A STARTING ESTIMATE FOR PSIS CALL FPSIS  C C C C  CALL SSM TO FIND A SOLUTION FOR THE COUPLED POTENTIAL AND HOLE CURRENT CONTINUITY EQUATIONS  NTIMES=0 X(1)=U X(2)=PSIS DO 700 1=1,3 Y(1,I)=U Y(2,I)=PSIS 700 Y(I,I)=Y(I,I)+DELY NEWY=.TRUE. CALL SSM( X ,F, 2.0. ERR 1. ITMAX2, COMPF, NEWY, NEWA ,NEWB, IFAIL , &800) 800 U1=X(1) PSIS1=X(2) NEWY=.FALSE. C CALL SSM AGAIN TO OBTAIN AN ESTIMATE OF THE ERROR IN THE SOLUTION CALL SSMI X,F, 2,0.ERR2,1TMAX2, COMPF, NEWY, NEWA, NEWB, IFAIL,&900) C C PREPARE FOR OUTPUT OF RESULTS C 900 U=X(1) PSIS=X(2) PHIER=DABS(U-U1)'VTHERM PSISER=DA8S(PSIS-PSIS1)'VTHERM PHI=VBE-U UO=U* VTHERM C CALL FQS C JVT=O.ODO JCT=0.ODO JMT=O.ODO QSS=0.ODO IFtNTRAP .EQ. 0) GOTO 1300 CVALEN=PHIO-EGAP+PSIS DO 1200 I=1,NTRAP ZETA=CVALEN+RHO(I)+V FM=1.0DO/d.ODO+DEXPL(2ETA)) FTNUM=NSURF • CN(I) *P 1 (I) • CP(I) »FM/TAUM( I) FTDNM= (NSURF+N1 (I)) • CN (I) • (PSURF»P 1 (I)) * CP (I) +1. OOO/TAUM! I) FT=FTNUM/FTDNM IF(IADNRtl) .EQ. 1) GOTO 1000 QSS=QSS-FT'Q*NT(I) GOTO 1100  L i s t i n g o f M I S B J T . S at 175  1000  7n 179 180  1300 c  77  181  '83 184 185  205 206 207  208 2 °9 210 211 2 2 1  2,3 2i4 2  1^  2.6 2.7  218 219  220 HI  222  223 Hi 225 226 227 228 2  29  230  III 232  •'  15.  1988 for C C i d = N S Z E on G  ^^^Q'NT'K'CPtnMPSURF'FT-PKII-d.OOO-FT))  JCT JC = T+Q'NT(I)'CN(I)'(NSURFM1.0D0-FT)-N1(I)'FT) PSII=CPSII • (QS+QSS)  ETAMC=-(PHIO*PSIS+VBE) ACM=-PSII*PSII BCM=PSII"CBCM  182  Io/ '88 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 zo, 1  11:24:09 on MAY  Q S S = Q S S M I.ODO-FT)'Q-NT(I)  THCM^DEXPL^CTNLCM^CORFCTt^^^^ 000-BCM*BCM/24. OOO/CCM) /CCM JCM=CJCM"THCMMFD H E T A C ) -FD1 (ETAMC) )  C  CALL FJVM  C  CALL FJBASE C C EXCHANGE THE TWO TUNNELING CURRENT COMPONENTS C TEMP=JCM JCM=JVM JVM=TEMP TEMP=JCT JCT=JVT JVT=TEMP C JRE=JNO-JNWB VCB=VBE-VCE WC8=DSQRT( 2 • EPS IS/Q • (ND+NA) / (ND • NA) * (0. 7 - VCB • VTHERM)) JGEN=Q*NI *WCB/DSQRT(TN'TP) JCBP=Q'DP" NI 'NI/OSQRT (OP * TP) /ND JE=JCM*JVM*JMT JC=JNWB+JG6N+JCBP JB=JE-JC HFE=(JC-JCBPJ/JB c UO=U"VTHERM VBEO=VBE-VTHERM VCEO=VCE*VTHERM PHIO=PHI 'VTHERM PSISO=PSIS'VTHERM PSIIO=PSII-VTHERM WRITE(LP,40) VBEO,VCEO,IFAIL 40 FORMAT(1X,'VBE=',F8.5,3X,'VCE=',F8.5,3X,'IFAIL=' 14/) WRITE(LP,45) UO.PHIO.PHIER.PSISO.PSISER.PSIIO 45 F0RMAT<1X,'U=',D14.7,2X,'PHI = ',D14.7,2X,'<PHIER=',D10.3 •)• 2X #'PSIS=' ,014. 7 , 2X, ' (PSISER=' ,D10.3, ') ' t 2X, 'PS 11 = ' ,014.7/) WRITEILP.50) PSURF.NSURF.ETAC.ETAV,ETAMC,ETAMV 50 FORMAT(1X.'PSURF=',D14.7,2X,'NSURF='.D14.7,2X,'ETAC=' FB 4 2X #'ETAV=' .F8.4.2X, 'ETAMC=' .F8.4.2X, 'ETAMV=' ,F8.4/) WRITE(LP,55) JCM,JVM,JCT,JVT,JMT 55 FORMATt IX, ' JCM=' ,011 . 4 , 2X . ' JVM=' .011.4.2X,' JCT=' ,D11.4 2X JVT=' ,011. 4 , 2X , ' JMT=' .D11.4.2X/) WRITE(LP,60) THCM.THVM 60 FORMAT(1X,'THCM=', D11.4,2X,'THVMa' ,011.4/) WRITEtLP,70) JE.JB.JC.HFE 70  wottcI/2* ' ' WRITE1LP,71)  >011.4,2X, ' JB=' .011.4.2X, ' JC=* ,011.4,2X, 'HFE=' ,011.4/) JNO,JNWB,JRE,JGEN,JCBP,JREC  L i s t i n g of M I S B J T . S at 233 234  235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290  C  C  C C C C C C C C  C  C C  15.  1988 for C C i d = N S Z E o n G  7 1 F O R M A T O X , 'JN0=' .011.4,2*. 'JNWB=' ,011 .4. 2X, 'JRE=' ,011.4 2X * 'JGEN=',011.4/,1X.•JCBP=',011.4,2X, 1 JREC=',D11.4////)  C C 1400 C  11:24:09 on MAY  GOTO 600 STOP END BLOCK DATA IMPLICIT REAL'S (A-Z) INTEGER CNTRL1.ITMAX1,LP.NTIMES COMMON /AREA1/ CBAR,CBCM,CBVM,CCM,CVM,CHISC,CHISV,CJCM, » CJVM,CPS11,CQS,CTNLCM,C TNLVM.EGAP,EGAPI, * NC.NA.ND,NI.NN0,NV,Q,PHI0,PN0, I PSISIO,VTHERM,WB,TP,TN.DN,DP,EPSIS COMMON /AREA4/ CNTRL1,ITMAX1,LP.NTIMES DATA EGAP/1.07988245600/,EGAPI/8.000/,Q/1.60210-19/,LP/6/ #,ON/3.878D-1/,DP/1.1640-1/,NI/1.45016/ END SUBROUTINE COMPF(X,F)  THIS ROUTINE COMPUTES THE RESIDUE OF THE POTENTIAL AND HOLE CURRENT CONTINUITY EQUATIONS IMPLICIT REAL'S (A-Z) INTEGER CNTRL1.I.IADNR.ITMAX1,LP.NTIMES.NTRAP DIMENSION X(2).F(2),TAUM(100),RHO(100). # NT<100),CN(100),CP(100),N1( 100),P1(100),IADNR(100) COMMON # # I COMMON COMMON I COMMON  /AHEA1/  CBAR,CBCM,CBVM,CCM,CVM,CHISC,CHISV,CJCM, CJVM.CPSII,CQS,CTNLCM,CTNLVM,EGAP,EGAPI, NC,NA,ND,NI,NNO,NV,Q,PHIO,PNO, PSISIO,VTHERM,WB,TP,TN.DN,DP,EPSIS /AREA2/ NT,RHO,N1,PI.CN,CP,TAUM.IADNR.NTRAP /AREA3/ ETAC,ETAMC,ETAMV.ETAV,JVM,NSURF,PHI,PSII,PSIS, PSURF,QS,THVM,THCM,U,VBE,VCE.JNO,JNWB,JREC /AREA4/ CNTRL1,ITMAX1,LP.NTIMES  NTIMES=NTIMES+1 U=X(1) PHI=VBE-U PSIS=X(2) CALL FQS QSS=0.ODO JVT=0.ODO IF(NTRAP .EQ. 0) GOTO 300 CVALEN=PHI0-EGAP+PSIS DO 200 1=1,NTRAP ZETA=CVALEN+RHO(I)+V FM= 1.000/ (1. ODO+DEXPL (ZETA)) FTNUM=NSURF • CN (I) +P1 (I)" CP (I) *FM/TAUM( I)  L i s t i n g of M I S B J T . S at 1 1 : 2 4 : 0 9 on M A Y 29 1 292 293 294 295 288 297 268 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 328 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348  100 200 c 300  c c  c 400 C C C C  C  c c  100  15. 1988 for C C i d = N S Z E on G  FTDNM= (NSURF+N 1(I))*CN(I)+( PSURF+P 1CI > ) * CP (I) + 1 . 0D0/TAUM( I) FT=FTNUM/FTDNM IF(IADNR(I) .EQ. 1) GOTO 100 QSS=QSS-FT"Q'NT(I) GOTO 200 QSS=QSS+(1.ODO-FT)*Q*NT<I) JVT=JVT + Q'NT(I)*CP(I)*(PSURF*FT-P1(I)* <1. ODO-FT)) PSII=CPSII*(QS+QSS) F(1)=CBAR+VBE+PSIS*PSII CALL FJVM CALL FJBASE F(2)=JVM-JNO-JREC-JVT IF(CNTRL1 .EQ. 0) GOTO 400 U0=U * VTHERM PSISO=PSIS*VTHERM WRITE(LP,5) NTIMES,UO,PSISO,F(1),F(2) 5 FORMAT!1X,13,2X.D23.16,2X,D14.7.2X,2(014.7 . 2X)) RETURN END SUBROUTINE FQS  THIS ROUTINE COMPUTES THE CHARGE QS STORED ON THE SEMICONDUCTOR IMPLICIT REAL * 8 (A-Z) INTEGER CNTRL1,1TMAX1,LP,NTIMES COMMON /AREA1/ CBAR , CBCM, CBVM, CCM. CVM, CHISC , CHISV, CJCM. # C JVM, CPSII ,CQS, CTNLCM, CTNLVM, EGAP.EGAPI, # NC, NA ,ND ,NI, NNO, NV ,Q, PHIO ,PNO, * PSISIO, VTHERM, WB, TP, TN,DN,DP,EPSIS COMMON /AREA3/ ETAC , ETAMC. ETAMV . ETAV, JVM.NSURF,PHI. PSII, PSIS, » PSURF, QS, THVM, THCM, U, VBE, VCE , JNO, JNWB, JREC COMMON /AREA4/ CNTRL1,ITMAX1,LP.NTIMES PXN=PNO"DEXPL (PHI) NXN=NNO+PXN-PNO ETAC=-(PSIS*PHIO) NSURF=NC*FD102(ETAC) NNSURF=NC'FD302(ETAC) ETAV=-(EGAP-PHIO-PSIS-PHI) PSURF=NV *FD102(ETAV) PPSURF=NV*FD302(ETAV) ARGMNT=NNSURF-NXN+PPSURF-PXN+NA'PSIS IFIARGMNT .GE. O.ODO) GOTO 100 WRITE(LP,5) ARGMNT 5 FORMAT!IX,"WARNING: SQUARE OF SURFACE FIELD IS NEGATIVE',5X.D ARGMNT=0.ODO QS=CQS'DSQRT(ARGWT) IFfPSIS .LT. O.ODO) QS=-QS RETURN END SUBROUTINE FJVM  L i s t i n g o f M I S B J T . S at 349 350 351 352 353 354 355  C C C C  1 1 : 2 4 : 0 9 on M A Y  15.  1988 for C C i d = N S Z E on G  THIS ROUTINE COMPUTES THE CURRENT FLOW JVM BETWEEN THE VALENCE BAND AND THE METAL IMPLICIT REAL'S (A-Z)  C  356  I  357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406  # *  COMMON /AREA1/  CBAR,CBCM.CBVM,CCM,CVM,CHISC,CHISV,CJCM,  CJVM.CPSII,CQS,CTNLCM,CTNLVM,EGAP.EGAPI,  NC ,NA ,ND , NI ,NNO, NV, Q, PHIO, PNO, PSISIO,VTHERM,WB.TP,TN.DN,DP,EPSIS COMMON /AREA3/ ETAC.ETAMC,ETAMV,ETAV,JVM.NSURF,PHI,PSII,PSIS, < PSURF.QS,THVM,THCM,U,VBE,VCE,JNO,JNWB,JREC  C  ETAMV=-(EGAP-PHIO-VBE-PSIS) C AVM=-PSII'PSII BVM=PSII * CBVM C0RFCT=1.OOO+IBVM/4.ODO+AVM/6.ODO-BVM'BVM/24.ODO/CVM)/CVM THVM=DEXPL(CTNLVM*CORFCT) C  C 100 C 200  C C C C C  C  IF (DABS(U) .GT. 1.0D-6) GOTO 200 IF( (ETAV .GT. -4.ODO) .OR. (ETAMV JVM=CJVM* THVM*DEXPL(ETAV)*U RETURN  .GT. -4.000) ) GOTO 100  JVM=CJVM'THVM'DLOG(1,ODO*DEXPL(ETAV))'U RETURN JVM=CJVM* THVM* (FD1 ( ETAMV) -FD1 (ETAV) ) RETURN END SUBROUTINE FJBASE  THIS ROUTINE COMPUTES THE MINORITY CARRIER HOLE CURRENT FLOWING INTO THE SEMICONDUCTOR IMPLICIT REAL'S (A-Z) COMMON /AREA1/  CBAR.CBCM,CBVM,CCM,CVM,CHISC,CHISV,CJCM, # CJVM.CPSII,CQS,CTNLCM,CTNLVM,EGAP,EGAPI, # NC.NA.ND.NI .NNO.NV.Q,PHIO,PNO, I PSISIO,VTHERM.WB.TP,TN,ON,DP,EPSIS COMMON /AREA3/ ETAC.ETAMC,ETAMV,ETAV,JVM,NSURF,PHI,PSII,PSIS, • PSURF,QS,THVM,THCU.U,VBE,VCE,JNO,JNWB,JREC  PSISI=PSISIO-PHI IF(PSIS .GT. PSISI) PSISCR=PSISI IF(PSIS .LT. PSISI) PSISCR=PSIS IF(PSISCR .LT. 0.000) PSISCR=O.ODO VBC=V8E-VCE NBO=NI'NI/NA DNB0=NB0*(DEXPL(PHI)-1.0) DNBW8=NB0 *(OEXPL(VBC)- 1.0) LN=OSQRT(DN'TN) WBE=DSQRT(2 * EPSIS/Q/NA'PSIS * VTHERM) WBEFF=WB -OSQRT (2 * EPSIS/Q/NA * (0. 7 - VBC • VTHERM)) - WBE IF (WBEFF .LE. 0.0) WRITE(6.9999) 9999 FORMAT (1X.'WARNING THE BASE IS PUNCHED THROUGH !!!'/)  L i s t i n g o f M I S B J T . S at 407  4,2  C  418  C  419 420 421  THIS  C  PSIS GIVEN PHI, ASSUMING NO SURFACE STATES  1  426 426 427 428  482  C 0 M P U T E S  COMMON /AREA 1/ CBAR . CBCM, CBVM, CCM, CVM, CHISC, CHISV, CJCM CJVM.CPSII, COS, CTNLCM, CTNLVM, EGAP, EGAPI, » NC,NA,ND,NI,NNO,NV,Q,PHIO,PNO, ' PSISIO, VTHERM, WB , TP, TN.DN.DP, EPSIS COMMON /AREA3/ ETAC , ETAMC , ETAMV , ETAV , JVM.NSURF, PHI, PSII PSIS ' PSURF, QS, THVM, THCM, U, VBE, VCE, JNO, JNWB, JREC COMMON /AREA4/ CNTRL1,ITMAX1,LP,NTIMES  423 424  483 484  R0UTINE  IMPLICIT REAL'8 (A-Z) INTEGER CNTRL1,I,ITMAX1,LP,NTIMES  422  429 430 431 432 4 33 4 34 435 438 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 480 481  1 5 . 1 9 8 8 for C C i d = N S Z E on G  0EN0M=2'LN"DSINH(WBEFF/LN) A=DNBWB-0NB0*0EXPL(-WBEFF/LN) B=DNBWB-DNBO"DEXPL(WBEFF/LN) JN0=-Q'DN*(A+B1/DEN0M JNWB=-Q'DN* ( A'DEXPL(WBEFF/LN)+B"DEXPL ( - WBEFF/LN))/DENOM JREC=Q , WBE'NI*(DEXPL(PHI/2.0)-1)/2/TN RETURN END SUBROUTINE FPSIS  408 409 410 41 '  413 414 415 416  11:24:09 on M A Y  C  100 200 C 300  400 500 C  C C C C C  CBARV=-(CBAR+VBE) IFtCBARV .GT. O.ODO ) GOTO 100 IF(CBARV .LT. O.ODO) GOTO 200 PSIS=0.000 RETURN PSISLO=0.ODO PSISHI=CBARV GOTO 300 PSISLO=CBARV PSISHI=O.ODO DO 500 I=1,ITMAX1 PSIS=(PSISLO+PSISHI)/2,ODO CALL FQS PSII=CPSII*QS F1=PSIS+PSII-C8ARV IFIF1 .EQ. 0.000) RETURN IF(F1 .GT. O.ODO) GOTO 400 PSISLO=PSIS GOTO 500 PSISHI=PS1S CONTINUE RETURN END DOUBLE PRECISION FUNCTION  FDKETA)  FERMI-DIRAC INTEGRAL OF ORDER ONE IMPLICIT REAL'S (A-Z) INTEGER INOEX DIMENSION  FDFLA(81),FDFLC(81),FDFLE(81),FDFLF(81),FDFLG(81)  COMMON /AREA5/ CFD 1, FDFLA , FDFLC, FDFLE, FDFLF, FDFLG  r-  r-( <—I L i s t i n g o f M I S B J T . S at 465 466 467 468 469 470 471 472 473 *7* 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 600 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522  C  C 100 C 200  C C C  15.  1988 for C C i d = N S Z E o n G  IF(ETA .LT. -4.0D0) GOTO 100 IF(ETA .GT. 4.000) GOTO 200 X=(ETA+4.0D0)/0.100+0.500 INDEX=X+1 ETAO=OFLOAT(INDEX - 41)"0.100 DELETA=ETA-ETA0 OXPETA=DEXPL(ETAO) FD1=FDFLF(INDE X)+DELETA'(DLOG(1.ODO+DXPETA) + » DELETA/2.000/(1.000+1.ODO/DXPETA)) RETURN FD1=DEXPL(ETA) RETURN FD1 = -DEXPL(- ETA)+ETA'ETA/2.OOO+CFD1 RETURN END DOUBLE PRECISION FUNCTION FD102(ETA)  FERMI-DIRAC INTEGRAL OF ORDER ONE-HALF IMPLICIT REAL'S (A-Z) INTEGER INDEX  C  DIMENSION  C  FDFLA(81),FDFLC(81),FDFLE(81),FDFLF(81),FDFLG(81)  COMMON /AREAS/  C  C 100 C 200  C C C  1 1 : 2 4 : 0 9 on M A Y  CFD1.FDFLA,FDFLC,FDFLE.FDFLF,FDFLG  IF1ETA .LT. -4,000) GOTO 100 IF(ETA .GT. 4.000) GOTO 200 X=(ETA+4.000)/O.100+0.5D0 IN0EX=X+1 ETA0=DFL0AT(INDEX-41)*0.1D0 DELETA=ETA-ETAO FD102=F0FLE(INDEX)+DELETA'(FDFLC(INDEX)+DELETA/2,ODO*FDFLA<INDEX)) RETURN FD102=DEXPL(ETA) RETURN FD102=-DEXPL(-ETA)+ETA'ETA/2.0D0+CFD1 RETURN END DOUBLE PRECISION FUNCTION FD302(ETA)  FERMI-DIRAC INTEGRAL OF ORDER THREE-HALVES IMPLICIT REAL'S (A-Z) INTEGER INDEX  C C C  DIMENSION  FDFLA(81),FDFLC(81),FDFLE(81),FDFLF(81),FDFLG(81)  COMMON /AREA5/  CFD1.FDFLA,FDFLC.FDFLE,FDFLF,FOFLG  IF(ETA .LT. -4.000) GOTO 100 IFIETA .GT. 4.000) GOTO 200 X=(ETA+4.0001/0. 100+0,500  L i s t i n g of M I S B J T . S at 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544  C 100 C 200  c c  100  1 1 : 2 4 : 0 9 on M A Y  15.  1988 for C C i d = N S Z E o n G  INDEX=X+1 ETAO=DFLOAT(INDEX-41)*0.1D0 DELETA=ETA-ETAO FD302=F0FLG<INDEX)*DELETA"(FDFLE(INDEX)+DELETA/2 RETURN FD302=0EXPL(ETA) RETURN FD302=-0EXPL(- ETA)+ETA*ETA/2.ODO+CFO1 RETURN END DOUBLE PRECISION FUNCTION OEXPL(X) IMPLICIT REAL*8 (A-Z) IF(X ,LT. -150.000) GOTO 100 DEXPL=DEXP(X) RETURN DEXPL=O.ODO RETURN ENO  

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