UBC Theses and Dissertations

UBC Theses Logo

UBC Theses and Dissertations

Application of complex quantized feedback in direct conversion receivers for wireless applications Ebadi, Zahra sadat 2007

Your browser doesn't seem to have a PDF viewer, please download the PDF to view this item.

Item Metadata

Download

Media
831-ubc_2007-317648.pdf [ 15.55MB ]
Metadata
JSON: 831-1.0100561.json
JSON-LD: 831-1.0100561-ld.json
RDF/XML (Pretty): 831-1.0100561-rdf.xml
RDF/JSON: 831-1.0100561-rdf.json
Turtle: 831-1.0100561-turtle.txt
N-Triples: 831-1.0100561-rdf-ntriples.txt
Original Record: 831-1.0100561-source.json
Full Text
831-1.0100561-fulltext.txt
Citation
831-1.0100561.ris

Full Text

Application of Complex Quantized Feedback in Direct Conversion Receivers for Wireless Applications by Zahra sadat Ebadi M . A . S c , University of British Columbia, 2003 B . A . S c , Sharif University of Technology, 2000 A THESIS S U B M I T T E D IN P A R T I A L F U L F I L M E N T OF T H E R E Q U I R E M E N T S F O R T H E D E G R E E OF D O C T O R OF P H I L O S O P H Y in The Faculty of Graduate Studies (Electrical and Computer Engineering) T H E U N I V E R S I T Y OF BRITISH C O L U M B I A August 2007 © Zahra sadat Ebadi, 2007 11 Abstract The recent resurgence in radio frequency (RF) transceiver design for wireless applications is accompanied by aggressive design goals such as low cost, low power dissipation, small form factor, and high-speed data transfer. To address these objectives, extensive research has been focused on the development of monolithic transceiver architectures, especially using low-cost CMOS technology. It is in this context that there is renewed interest in the direct-conversion receiver (DCR) architecture, the subject of this research. Currently, the use of DCRs involves a number of challenges. Issues of DC offset, flicker noise, LO leakage and radiation, I /Q mismatch, and intermodulation distortion should be carefully consid-ered and addressed in a D C R design. Also, because of cost incentives and performance, one of the main trends in the evolution of wireless receivers is to implement more and more functionality by way of digital signal processing (DSP). The main objective of this thesis is the development and implementation of solutions to overcome these impairments in the D C R architecture and facilitate D C R design using DSP. To achieve this goal, we begin by using A C coupling to remove DC offset and to reduce flicker noise. Then, quantized feedback (QFB) is employed in both I and Q channels to reduce the baseline wander effect caused by AC-coupling. Such modifications are unable to combat carrier phase error and I/Q mismatch problems. However, they can be effec-tively reduced using a cross-coupled or complex Q F B (CQFB), the key contribution in the thesis. The performance of this CQFB-enhanced D C R architecture is theoretically ana-lyzed and experimentally validated. Next, the design issues for adaptive implementation of C Q F B using DSP techniques are addressed. Further, its use is illustrated in the context of a direct-conversion orthogonal frequency-division multiplexing (OFDM) receiver. We show that digital C Q F B is very effective in compensation of D C offset, I /Q mismatch, and carrier phase error in a D C R for O F D M signaling. To assist in validation of the de-veloped approach, a prototype R F front-end of the receiver is designed and fabricated in T S M C 0.18/zm CMOS process for 2.4GHz wireless applications. The developed prototype provides for user control of I /Q mismatch and includes all the main blocks of the R F front-end of the receiver, namely, a low-noise amplifier (LNA), two mixers and a voltage-controlled oscillator (VCO). This prototype can be used as test vehicle for evaluation of various I /Q mismatch compensation methods implemented in the back-end. i i i Table of Contents Abstract ii Table of Contents ii i List of Tables • • vi List of Figures vii List of Abbreviations xi Acknowledgements xiii 1 Introduction 1 1.1 Motivation 1 1.2 Research Goals and Challenges 4 1.3 Thesis Organization 5 2 Background 7 2.1 Receiver Architectures 7 2.1.1 Heterodyne Architecture 7 2.1.2 Image Reject Architecture 10 2.1.3 Direct-Conversion Receiver (DCR) Architecture 11 2.2 Direct Conversion Receiver Challenges 13 2.2.1 DC Offsets 14 2.2.2 Flicker Noise 20 2.2.3 Amplitude and Phase Imbalances 22 2.2.4 Second-Order Intermodulation (IM2) Distortion 25 2.3 DC offset Reduction Methods 27 2.4 I/Q Mismatch Compensation 34 2.5 Summary 35 Table of Contents iv 3 Complex Quantized Feedback 36 3.1 Overview of the New Approach 36 3.2 Carrier Phase Error Compensation 41 3.2.1 I /Q Mismatch Compensation 43 3.3 Simulation Results 44 3.4 Design Issues 55 3.4.1 Design Considerations for Adaptive Filters 57 3.4.2 Experiments on Adaptive Filters 58 3.4.3 Carrier Phase Error Estimation 59 3.5 Summary 61 4 Adaptive Digital Signal Processing Techniques for C Q F B 63 4.1 Introduction 63 4.2 I /Q Down-Conversion Based Front-End 65 4.2.1 I/Q Processing Principles 65 4.2.2 Architectural Aspects 67 4.3 Adaptive implementation of complex Q F B 69 4.3.1 DC-offset removal filters 69 4.3.2 Complex Q F B receiver 70 4.3.3 Estimation of non-ideality parameters 72 4.3.4 Direct adaptive decision feedback 76 4.3.5 Simulation results 77 4.3.6 Direct adaptive decision feedback with ISI 81 4.3.7 Simultaneous compensation for ISI and non-ideality parameters . . 85 4.4 Summary 89 5 Mismatch-Controllable R F Front-end Test Platform 91 5.1 Introduction and Motivation 91 5.2 Receiver Specifications 95 5.2.1 Receiver System Specifications 96 5.3 Low Noise Amplifier 98 5.3.1 Simulation Results 101 5.4 Down-Conversion Mixer 103 5.5 Voltage-Controlled Oscillator 109 5.6 Simulation results 113 5.7 Summary 119 Table of Contents v 6 Conclusions 121 6.1 Research Summary 121 6.2 Thesis Summary 122 6.3 Future Work 125 A Application: O F D M signaling 127 A . l Basics of O F D M 127 A . l . l O F D M Implementation 130 A. 2 Adaptive ISI and non-ideality compensation in O F D M signaling 133 B On-chip Inductor and Varactor 136 B. l Spiral Inductors 136 B.2 Varactors 138 C Testing of the R F Front-end Chip 141 Bibliography 147 vi List of Tables 5.1 SNR and N F requirement for various modulation schemes in I E E E 802.11a/g 97 5.2 L N A Performance Summary 105 5.3 Mixer's conversion gain for different Ibc 109 5.4 Mixer Performance Summary 109 5.5 VCO's characteristics 117 V l l List of Figures 2.1 Super-heterodyne receiver 8 2.2 The problem of image rejection in super-heterodyne receivers [1] 9 2.3 Image reject (Weaver) architecture 10 2.4 Direct conversion architecture 12 2.5 Frequency content of heterodyne (top) and D C R (bottom) output spectrum 14 2.6 LO signal leakage to the input of L N A and Mixer 15 2.7 Near-channel interferer leakage to the LO port of mixer 16 2.8 L O signal leakage to the antenna 17 2.9 Differential amplifier with mismatch 18 2.10 Flicker noise and concept of 1/f noise corner 21 2.11 IRR calculation for different gain and phase mismatch 23 2.12 The effect of I /Q mismatch 24 2.13 Second-order input intercept point (IIP2) concept 28 2.14 DC offset cancellation techniques using (a)capacitive coupling, (b) linear feedback; and (c) sampling . 29 2.15 D C offset cancellation using analog techniques [2] 31 2.16 Mixed-mode DC offset cancellation [3] 32 2.17 Single-balanced CMOS even-harmonic mixer [4]. 33 3.1 A direct-conversion receiver with AC-coupling 37 3.2 Conventional quantized feedback technique 38 3.3 Simple system including high-pass filter and quantized feedback 39 3.4 Complex Q F B system 40 3.5 Simulation results (DCR with H P F of different cut-off frequencies) 46 3.6 Simulation results (DCR with H P F and QFB) 47 3.7 Simulation results (DCR with H P F , Q F B and carrier phase error) 48 3.8 Simulation results (DCR using complex Q F B with carrier phase error) . . . 49 3.9 Simulation results (DCR using H P F with carrier phase error) 50 3.10 Time-varying carrier phase error 51 List of Figures viii 3.11 Simulation result of time-varying carrier phase error effect on different sys-tems 51 3.12 Simulation result of I /Q mismatch (e = 10% and A 0 = 10°) effect on different systems 52 3.13 Simulation result of different I /Q mismatch parameters 53 3.14 Simulation result for noise in carrier phase error estimation . 55 3.15 Simulation result for effect of noise in system with mismatch estimation . 56 3.16 Low-pass filter characteristics for different phase errors (0° < 9 < 70°) . . . 59 3.17 Cut-off frequency of low-pass filter for different phase error . 60 3.18 Complex Q F B with phase estimator 61 3.19 Simulation result (Complex Q F B with phase estimator) 62 4.1 Simplified receiver block diagram with DSP C Q F B 65 4.2 Basic I /Q downconversion principle in terms of: (a) complex signals and (b) parallel real signals 66 4.3 D C R with digital demodulation 68 4.4 Effects of non-idealities on Q A M signal points: e = 15%, Acj) = 9 = 18°, iDC = 1 and qDC = -1.5 and- SNR=20 dB (left) and 5 dB (right), super-imposed on the ideal 16-QAM constellation ("x") 69 4.5 Frequency response of the first order DC-offset removal filter for a = 0.9. . 70 4.6 Adaptive filter block diagram 73 4.7 The effect of the proposed method ("Compensation on") on symbol error rate vs. no compensation and ideal 16-QAM reception and detection (i.e., all non-ideality parameters, namely 9, e and A<fi are zero) 78 4.8 The effect of initial value of the filter ( W; 0.5/ 2x2 (light) and J 2 x2 (dark)) on convergence to non-ideality parameters. The SNR is set to 10 dB and the same pseudo-noise sequence is used for fair comparison. The 1000-symbol 16-QAM signal is generated with 9 = 0.2rad, Acb = -0.25rad, and e = 15% 79 4.9 The effect of gain mismatch (e) on symbol error rate, with and without adaptive compensation of non-idealities 80 4.10 Effect of carrier phase error (9) and phase mismatch (Acj)) on symbol error rate represented by image intensity (i.e., dark areas = small error rate), with (left) and without (right) adaptive compensation of non-idealities. 9 and Acj) vary between -0.9 and 0.9 rad (= 51° ) 81 List of Figures ix 4.11 Left: 16-QAM received signal (at the output of DC removal filters in Fig-ure 1) with ISI and receiver non-idealities. Right: The same signal after adaptive compensation of ISI and non-idealities (at the input of the thresh-old blocks in Figure 1; only the last 1500 symbols are mapped to ensure convergence occurred) 87 4.12 Convergence of adaptive compensation of ISI and non-idealities: because of high SNR (15 dB) no error occurred after convergence (after about 600 symbols) 88 4.13 Cumulative sum of reception errors for various types of ISIs. For ISI type (iv) the method does not converge within 5000 symbols 89 5.1 Controllable R F front-end with the DSP C Q F B 92 5.2 The block diagram of the implemented R F front-end 93 5.3 IRR improvement by adjusting the gain mismatch 95 5.4 Low Noise Amplifier (LNA) 99 5.5 Low Noise Amplifier with external matching network (LNA) 101 5.6 L N A simulation: Gain 102 5.7 L N A simulation: Noise Figure 103 5.8 L N A simulation: S l l 104 5.9 Single-balanced down conversion mixer 105 5.10 The implemented down conversion mixer 106 5.11 Result of transient analysis of the mixer 114 5.12 Circuit schematic of Q V C O 115 5.13 Output voltages and resonator currents when the output waveforms are perfectly balanced 115 5.14 VCO's amplitude and frequency versus Vctrl (varactor voltage control) . . 116 5.15 VCO's Output 118 5.16 V C O phase noise for different varactor control voltages 119 5.17 Die photograph of the R F front-end 120 A . l Spectral overlap of subcarriers in O F D M 128 A.2 Spectrum of O F D M signal 129 A.3 O F D M transmission 130 A.4 O F D M reception 131 A.5 The frequency response of the DC-offset reduction filter 135 A.6 Cumulative sum of reception errors for adaptive compensation of receiver non-idealities and ISI for O F D M signaling 135 List of Figures x B . l Inductor Model 137 B.2 Super-heterodyne receiver 138 B.3 Symmetric inductor with tap Model 139 B.4 The quality factor of inductor vs. frequency for different values of R . . . 139 B.5 The inductor value vs. frequency for different values of R 140 B. 6 Equivalent circuit of a MOS varactor 140 C. l Photograph of the test boards 142 C.2 Schematic of high frequency board for testing the chip 143 C.3 Schematic of bias board for testing the chip 144 C.4 Test setup for (a)Sll and (b) conversion gain measurements 145 C.5 Test setup for (a)NF and (b) I /Q imbalance measurements 146 List of Abbreviations A / D Analog to Digital Converter A D C Analog to Digital Converter A M Amplitude Modulation B E R Bit-Error-Rate B F S K Binary Frequency-Shift Keying B W Bandwidth CMOS Complementary Metal Oxide Semiconductor C Q F B Complex Quantized Feedback D A C Digital-to-Analog Converter D C R Direct Conversion Receiver DSP Digital Signal Processing D R Dynamic Range D R P Digital Radio Processing E H Even Harmonic F M Frequency Modulation G M S K Gaussian Minimum Shift Keying GPS Global Positioning System H P F High-Pass Filter I In-Phase IC Integrated Circuit I E E E Institute of Electrical and Electronics Engineers IF Intermediate Frequency IM2 2nd Order Intermodulation IM3 3rd Order Intermodulation IIP2 2nd Order Input Intercept Point IIP3 3rd Order Input Intercept Point ISI Intersymbol Interference K Boltzmann Constant L M S Least Mean Squares L N A Low-Noise Amplifier L O Local Oscillator L P F Low-Pass Filter M O S F E T Metal Oxide Semiconductor Field Effect transistor List of Abbreviations xii N F Noise Figure O F D M Orthogonal Frequency-Division Multiplexing P L L Phase Locked Loop Q Quadrature-Phase Q Quality Factor Q A M Quadrature Amplitude Modulation Q F B Quantized Feedback QPSK Quadrature Phase-Shift Keying R F Radio Frequency RLS Recursive Least squares SAW Surface Acoustic Wave SNR Signal-to-Noise Ratio SoC System-on-a-Chip SOI Silicon-on-Insulator T D M A Time division multiple access V C O Voltage-Controlled Oscillator W C D M A Wideband Code Division Multiple Access W L A N Wireless Local Area Network X l l l Acknowledgements This thesis would not have been completed without the appreciable help of many great people who made my life in U B C an enjoyable and enlightening experience. First of all I would like to express my gratitude to my supervisor, professor Resve Saleh for giving me the opportunity to work in his group. I am greatly indebted to him for his continuous support, patience, and enthusiasm. He has been a great friend and advisor for me. I would also like to thank professor Shahriar Mirabbasi for his great help in the early stages of this work. M y sincere thanks goes to Dr. Roberto Rosales for all his support and willingness to help. I also wish to thank Roozbeh Mehrabadi for C A D support and Sandy Scott for her administrative assistance in our lab. I gratefully acknowledge the support of my colleagues in System-on-a-Chip group in U B C . I am especially thankful to Samad Sheikhaei, Mohammad Hekmat, Rod Foist, Mehdi Alimadai, Neda Nouri, Sohaib Majzoub, Dipanjan Sengupta, and Peter Hallschmid. Finally I express my deepest appreciation to my wonderful parents and husband, and my daughter, Niayesh, for their love and endless support. If it were not for their sincere help and encouragement, I would not have made it as far as I did. This research was supported by NSERC (National Science and Engineering Research Council) through Canada Graduate Scholarship-Doctorate (CGS-D). Chapter 1. Introduction 1 Chapter 1 Introduction 1.1 Motivation Single-chip wireless transceivers with the long-established requirements of low-cost, low power dissipation, and small form factor while still achieving high performance are now a reality. Advances in deep submicron complementary metal-oxide semiconductor (CMOS) processes and technologies have resulted in radio-frequency (RF) circuits on scalable digi-tal CMOS processes. As a result, it is now possible to combine the best of both digital and analog worlds to truly enable the paradigm of digital radio processing (DRP) technology [5]. Designing R F and analog blocks in deep submicron digital CMOS processes is a sig-nificant challenge. Some of the reasons are listed below: 1. Because of technology scaling, the process node shrinks every 18 months; therefore, the R F and analog area should shrink with the same rate for the solution to be cost effective. However, analog design does not scale at the same rate. 2. Analog/RF must not require too many extra fabrication processing step because of cost. At present, analog and R F require many special process features. Chapter 1. Introduction 2 3. The supply voltage is being reduced but the analog blocks must still maintain their dynamic range. Today, typically analog designs use higher supply voltages than digital design. 4. Substrate noise coupling from digital to analog/RF requires careful design and iso-lation techniques. 5. The device characteristics are constantly updated, so the R F and analog circuits are often designed on an immature process where simulation models and device characterization are not finalized. Thus, conventional design techniques cannot be relied on in this new paradigm of a com-plete wireless mixed signal system-on-chip (SoC) design. On the other hand, analog and digital signal processing concepts can be used to alleviate some of the complexity of ana-log/RF design and, in fact, greatly simplify it. Architectures that have been known to result in smaller bill of materials (BOM), but were never implemented due to technology limitations are now being revisited. A direct conversion receiver (DCR) is one such architecture that allows monolithic integration. However, the D C R architecture suffers from classical R F impairments common to all kinds of receivers. The impact of some of these impairments is much more critical for D C R compared with other architectures such as heterodyne receivers. The major impairments of concern in DCRs are D C offset, flicker noise, even-order harmonic distortions and I/Q mismatch [1]. This research will mainly focus on addressing the impairments associated with the D C R architecture using digital techniques. In direct conversion receivers, the DC offset experiences a large gain in the stages Chapter 1. Introduction 3 following the down-conversion process [6]. If not controlled, DC offset can cause saturation of subsequent A / D converters. A related impairment of concern in DCRs is flicker or 1/ f noise that arises from random trapping of charge at the oxide-silicon interface of metal-oxide-semiconductor field-effect transistor (MOSFET) devices. Flicker noise introduces unwanted signal content close to DC. Even-order harmonic distortion, usually dominated by the 2nd-order harmonic, results in DC offset and possibly distortion in the frequency band around D C in the presence of a single strong interferer signal. If two strong interferer signals are present such that their difference frequency falls in the band of interest, then an unwanted signal will again be created in the band of interest. Finally, gain and phase mismatches between the I and Q channels in a quadrature receiver result in an unwanted image, which can cause degradation in the effective signal-to-noise ratio (SNR) in the presence of a large nearby modulated interferer. A slight variation in D C R results in what is called the low-IF (low intermediate fre-quency) architecture. In this architecture, instead of direct-conversion or zero-IF, the R F signal is down-converted to a very small IF, usually half of the channel bandwidth. The advantage of this architecture is that it is less vulnerable to DC offset and flicker noise, compared with zero-IF. However, it is also prone to problems that arise from I and Q mismatches. The objective of this research is to address the most important of these problems using digital techniques. Flicker noise is generally controlled by the dimensions of the transis-tors and it will be addressed with the same technique as D C offset compensation. The effect of flicker noise on receiver performance is reduced by using a higher IF frequency. Chapter 1. Introduction 4 Although the techniques proposed in this research are applicable to all receivers imple-mented using D C R or low-IF architectures, they are applied to a IEEE 802. l l g standard direct-conversion receiver in this thesis. 1.2 Research Goals and Challenges Having described the motivation and necessary background, it is now possible to describe the objectives of this research. First, a succinct research objective is as follows: To develop techniques that help alleviate analog impairments that plague DCR architec-tures, hence resulting in a robust receiver design. A more detailed set of research objectives is outlined below: • Develop a new technique for compensation of DC offset and low-frequency distur-bance, with minimal degradation of the wanted signal. • Develop a new technique for I/Q mismatch compensation. These circuits should be robust against interferer environment in which the receiver operates. • Develop a flexible R F front-end such that the user has some control over the degree of I /Q mismatch by changing the mixer's specifications. • Implement the proposed algorithms and circuits for a I E E E 802.llg (quadrature amplitude modulation (QAM) signaling) and present results to show the validity of the proposed algorithms and circuits. The proposed techniques should be applicable to standards other than wireless local area network (WLAN) standards. Chapter 1. Introduction 5 1.3 Thesis Organization Chapter 2 describes receiver architectures in detail along with major receiver impairments and divides them into two categories: the ones that can be improved primarily by following good analog circuit design techniques and the others that can be improved using digital compensation techniques. The latter category includes DC offset, I /Q mismatch and, to a certain extent, even-order harmonic distortion. The sources of these three impairments as well as their impact on receiver performance and the variation of these impairments over temperature, process and frequency, are described in detail in Chapter 2. A brief survey of previously proposed solutions to address these impairments is also given in Chapter 2. A new approach, complex cross-coupled quantized feedback, is introduced to solve most of the important issues of D C R and explained in detail in Chapter 3. A large number of simulations in MATLAB/Simul ink are carried out to demonstrate the effectiveness of complex quantized feedback system. It is shown that a complex quantized feedback (CQFB) system can effectively correct DC offset and compensate for receiver carrier phase error as well as I /Q mismatch. In Chapter 4, cross-coupled complex quantized feedback is implemented using digital signal processing techniques. Adaptive filters between I and Q channel data are used for correcting gain and phase mismatches. The non-idealities are estimated and complex filters are modified adaptively to compensate for I/Q mismatch and phase offset. The convergence issues of adaptive filters are also described. A n example of a system with orthogonal frequency-division multiplexing (OFDM) signaling using complex quantized feedback is presented in Appendix A. Chapter 1. Introduction 6 Chapter 5 describes the design and implementation of an RF-front end of I E E E 802.llg DCR, using CMOS T S M C 1 0.18 pm technology. The design of a low-noise amplifier, down-conversion mixer and quadrature voltage-controlled oscillator for 2.4 GHz I S M 2 band is explained in detail. The down-conversion mixer is designed in a way that the I and Q mixer gain can be controlled externally. Two benefits arise from this option: First, the known I/Q mismatch can be entered to system, so this R F front-end can be used to compare different I/Q mismatch cancellation techniques. Second, if the I/Q mismatch of the R F front-end has been estimated, it can be compensated efficiently, by using the change in the gain of one of the mixers. Chapter 6 provides conclusions and direction for future work. 1 Taiwan Semiconductor Manufacturing Company 2The industrial, scientific and medical (ISM) radio bands were originally reserved internationally for non-commercial use of RF electromagnetic fields for industrial, scientific and medical purposes. Chapter 2. Background 7 Chapter 2 Background 2.1 Receiver Architectures The recent resurgence in R F transceiver design for wireless applications has been accompa-nied by aggressive design goals such as low cost, low power dissipation, small form factor, and high-speed data transfer. These goals are driven by the need for better portability and better affordability. To address these objectives, recent research has been focused toward the development of monolithic transceiver architectures, especially using low-cost C M O S technology [7]. It is in this context that there is renewed interest in the direct-conversion architecture[l][8][9], which is the subject of this research. In this chapter, two traditional receiver architectures will be described, followed by a brief description of D C R and low-IF architectures. Some of the issues associated with these architectures will also be presented. 2.1.1 He te rodyne Arch i t ec tu re Many commercial radio receivers are designed based on a super-heterodyne architecture [7]. In its simplest form, a two-stage conversion process is used as shown in Figure 2.1. In such topologies, the input R F signal is down-converted to an intermediate frequency (IF), Chapter 2. Background 8 where it is amplified and filtered before the final demodulation by a low-frequency de-modulator. Typically, this demodulator is built to operate at frequencies below 100 MHz. Therefore, two intermediate conversions are sometimes needed to facilitate image filtering by using an additional IF sufficiently different from the R F signal. Signal amplification at IF, however, requires IF filters to be biased with large currents, causing substantial power dissipation. Further, these filters are typically off-chip passive components, adding to the receiver size and cost. Consequently, these multiple stages of filtering and amplification add to the complexity and the cost of the receiver. RF input (fc) Second down-conversion (quadrature, IF to baseband) Figure 2.1: Super-heterodyne receiver. The principal issue in super-heterodyne is the trade off between image rejection and adjacent channel suppression [1]. For given filter quality factors and losses, if the IF Chapter 2. Background 9 is high, the image is greatly attenuated whereas nearby interferers remain at significant levels, as shown in Figure 2.2. Conversely, if the IF is low, the image corrupts the down-converted signal but the interferers are suppressed. For this reason, both the image reject filter and the channel select filter require high-selectivity and expensive analog R F filters. Because of such stringent requirements, the image rejection (IR) filter of Figure 2.2 is difficult to design. The requirements can be relaxed by using a dual-conversion (two IF) or a triple-conversion (three IF) architectures at the cost of added receiver cofnplexity and size [9]. cos Channel Select Filter Figure 2.2: The problem of image rejection in super-heterodyne receivers [1]. Chapter 2. Background 10 2.1.2 Image Reject Arch i t ec tu re The image reject (IR) architecture attempts to address the problem of image rejection by-using a complex exponential local oscillator (LO), instead of a real LO, to down-convert R F signal to the first IF frequency. The final down-conversion to baseband is also done using another complex down-conversion stage at the IF frequency. There are two common topologies of an IR architecture: Hartley [10] and Weaver [10, 11]; both work on the same principle. Figure 2.3 shows a block diagram of the Weaver architecture [12]. Figure 2.3: Image reject (Weaver) architecture. In Figure 2.3, the received signal is passed through an R F filter and amplified by low noise amplifier (LNA) before entering the first complex mixer, which shifts the wanted signal to the IF frequency. The filters following the complex mixer remove frequency components at 2 / c — fjp. Next, another complex mixer translates the wanted signal to baseband. The baseband signal is then amplified, filtered and converted to the digital domain. The most serious issue with the IR architecture is that it is vulnerable to gain and Chapter 2. Background 11 phase mismatches between I and Q channels. As will be explained later, gain and phase mismatches cause an attenuated version of the signal at the image frequency to fold back on the wanted signal. The amount of fold back is described by image rejection ratio (IRR) and it is determined by the gain and phase mismatches between I and Q channels. Usually, the IR architecture requires two complex down-conversion stages in the analog domain and at least two filtering stages, which makes it challenging for highly-integrated designs. 2.1.3 Di rec t -Convers ion Receiver ( D C R ) Arch i t ec tu re One approach to reduce the number of stages in the R F front-end is to convert a received R F carrier signal down to D C (zero IF) in a single step. This is called direct conversion and is carried out in receivers known as homodyne, zero-IF, and DCR. In DCRs, the received radio frequency signals are directly converted into baseband signals; thus, sep-arate intermediate frequency stages are not required [13, 14]. Therefore, the number of high-frequency components of a direct-conversion receiver is less than in the conventional one. Because of their simplicity, a D C R can be much more easily integrated as compared to a heterodyne receiver [1, 15]. The basic architecture of a direct-conversion receiver is shown in Figure 2.4. In DCRs, after the desired signal is translated to the baseband, the analog-to-digital (A/D) converter and digital signal processing (DSP) circuits perform demodulation and other ancillary functions [15]. Intermediate stages are removed and the need for high-frequency IR filters is eliminated. Since bulky off-chip IR filters are no longer required, Chapter 2. Background 12 RF input (fc) Figure 2.4: Direct conversion architecture the R F L N A is not required to drive a typically low-impedance off-chip IR filter. The functions of channel selection and subsequent amplification at non-zero IF are replaced with low-pass filtering and baseband amplification, which are amenable to monolithic integration at lower power [1][7][8]. To carry out direct conversion, a local oscillator signal with the same frequency as the R F carrier is mixed with the received signal. The frequency content of the mixer output contains the sum and the difference of the LO and the carrier frequencies. Thus, copies of the spectrum of the desired signal are at twice the carrier frequency and at D C (zero Hz). The high-frequency spectrum can be removed by a suitable low-pass filter. The copy of the spectrum left at zero frequency (baseband) can be demodulated (e.g., F M 1 demodulator can be used to recover an FM-modulated signal or, I /Q demodulator for an I/Q modulated signal). 1 Frequency modulation Chapter 2. Background 13 2.2 Direct Conversion Receiver Challenges The use of a direct-conversion receiver is not without certain drawbacks. One of the main problems, and widely-recognized, is that of D C offset. DC offset is undesired DC signal at the output of the R F front-end and can cause considerable distortion in the desired signal if it is large enough. Because D C is in the IF bandwidth, the DC offset at the R F front-end output (and that contributed by the IF amplifiers) severely limits the sensitivity of the receiver if it is not removed. Low-frequency noise sources, such as flicker noise and spurious amplitude modulation (AM), can also cause similar problems. Figure 2.5 shows the frequency content at the output of D C R and heterodyne receivers and highlights the intermodulation distortions and other interfering signals that are of concern for each topology. In direct conversion receivers, the higher frequency components of the output can be easily removed by active or passive low-pass filtering in the baseband. However, because of the presence of the D C offsets and second-order (IM2) and third-order (IM3) intermodulations, the separation of the down-converted output from all of the extraneous signals can be challenging. In the heterodyne approach, however, D C offsets and IM2 can be easily eliminated through simple capacitive coupling, but the image interference and IM3 remain in-band. The major design considerations for a D C R can be summarized as DC offset, flicker noise, LO leakage and radiation, I/Q mismatch, and intermodulation distortion that are briefly discussed in the following. Chapter 2. Background 14 Flicker Noise SAW image IM2 IM3 i i & f t I ! v 1 IM3 IF DC-offset Flicker Noise .JBRF._. si - - \ LPF I M 2 IM3 LO i fa fb i i R F Spectrum Out of band interference fa fb, i i R F Spectrum Figure 2.5: Frequency content of heterodyne (top) and D C R (bottom) output spectrum 2.2.1 D C Offsets The main sources of DC offset are leakage of the LO signal and R F signal self-mixing due to leakage of a near-channel interferer to the LO, as described below. L O signal leakage into L N A and mixer The L O signal may reach the mixer's R F input port through the substrate or bondwire coupling, thus effectively mixing with itself and producing an unwanted DC component at the mixer output. Figure 2.6 shows the leakage of the L O signal to the input of the L N A and mixer. Since the isolation is not perfect between the L O port and the inputs of the L N A and mixer, the L O signal leaks into the input of the L N A and mixer. The leakage signal is mixed with the LO signal resulting in a constant DC offset. The level of Chapter 2. Background 15 the offset depends on the amount of leakage and the phase shift between the LO signal and leakage. The resulting DC offset at the mixer output can be orders of magnitude larger than the desired signal. LO signal LO signal leakage to ' input of LNA and Mixer Figure 2.6: L O signal leakage to the input of L N A and Mixer In-band. interferer leakage to the L O The leakage of a near-channel interferer to the L O port is shown in Figure 2.7. The resulting distortion component has a D C term and a spectrum, which depends on the envelope (amplitude) modulation characteristic and average power of the interferer [16]. Moreover, the phase shift between the interferer signals at R F and LO ports of the mixer affects the power of the resulting distortion component. DC offset cancellation schemes are effective only in removing constant D C offset [17]. Since it is very difficult to remove the in-channel baseband distortion component due to R F self-mixing of an amplitude modulated interferer after down-conversion, the leakage of a near-channel interferer to the LO port of the mixer should be suppressed to a sufficiently low level. Chapter 2. Background 16 V Strong in-band interferer Band Select Filter LNA Strong in-band interferer Leakage LO Figure 2.7: Near-channel interferer leakage to the L O port of mixer. L O signal leakage to the antenna Since D C R requires a L O signal frequency identical to the R F input carrier frequency, the L O signal is considered to be in-band interference. Because L O is usually a high-power signal, it can couple into the antenna, radiate out into the receiver band of other users, and saturate the R F front-end [1]. The L O signal can leak into and radiate from the antenna. The leaked L O signal may also reflect from external objects. Since the environment contains both stationary and moving objects, the magnitude and phase of the reflected L O signal varies accordingly. If the L O signal is reflected back from moving objects, the frequency of the reflected signal has a Doppler shift. Therefore, the reflected L O signal is down-converted to a nonzero baseband frequency that depends on the speed of the reflecting object. The impact of the low-frequency component generated due to the reflected L O signal depends on the amount of L O signal at the R F input. In addition, directly converting the R F signal to the baseband leads to signal filtering and amplification to be performed in the frequency band between DC and the signal bandwidth. Thus, the DC offset in the signal path is Chapter 2. Background 17 amplified and degrades the dynamic range of the receiver. The generated D C offset due to L O signal leakage has to be suppressed to relatively lower levels to maintain the receiver sensitivity at an acceptable level [17]. Reflected LO leakage signal Band Select Filter LNA r A LO signal leakage to antenna LO signal LO Figure 2.8: L O signal leakage to the antenna Most of the popular wireless standards only allow in-band L O radiations of less than —80 dBm, which would require 80 to 90 dB isolation between the L O signal source and the antenna. High reverse isolation in the front-end and good shielding of the receiver can reduce the L O leakage and radiation; however, alternative schemes such as sub-harmonic mixing can also be used to simplify this problem by moving the LO signal out of the R F frequency band of interest [18]. Circuit imbalance Another cause of D C offset is the imbalance between the two sides of a differential circuit. This imbalance can be due to threshold voltage mismatch in MOSFETs or unbalanced bias currents in the two sides of a symmetric circuit. For example, consider a differential amplifier as a baseband amplifier in I or Q path with a resistive load as shown in Fig-ure 2.9. Assume that transistors M l and M2 have threshold voltage mismatch and the Chapter 2. Background 18 Ri L1 RL2 Out- Out+ ln+ —1[7 M 1 M 2 j | — I n -? Figure 2.9: Differential amplifier with mismatch load resistors are not matched due to the process variation. The mismatches of transistors and loads are modeled as: RL\,2 = RL i VTL,2 = VT± AR 2 AVT The threshold voltage mismatch makes the bias currents of the two sides unbalanced: I\t2 = ^ i f (Vos-Vt)" ^ e n o n - s v m m e t r y of the circuit, caused by these mismatches, results in DC offset voltage at the output given by: V - A R T +M A V t VDC — ~TTIB + rilB-VGS - VT (2.1) Therefore, it is observed that the mismatch in a differential circuit generates DC-offset. Chapter 2. Background 19 Impact of D C Offsets on A D C Dynamic Range The filtered output from the mixer is fed to an amplifier and then to an A / D converter (ADC). A large D C offset at the input of an A D C reduces the effective dynamic range of the A D C . DC offset can also saturate amplifiers following the mixer. In a wireless receiver, there is a trade-off between the available dynamic range of the A D C and the required filtering. A higher dynamic range A D C allows relaxed filtering requirements and vice-versa. It is hard to design cost-effective high dynamic range ADCs; therefore, it is important to reduce the DC offset at the A D C input. Impact of D C Offset on Receiver S N R If uncorrected, D C offset results in degraded receiver performance. This is particularly true for zero-IF receivers and with modulation schemes that have strong signal energy at DC. A few examples are Gaussian minimum shift keying (GMSK) modulation, Q P S K and Quadrature amplitude modulation (QAM) followed by (root) raised-cosine filtering. A commonly used receiver performance metric is the ratio of energy per bit ( Eb ) to noise power density ( N0 ), represented as Eb/NQ. Baudin and Belveze in [6] give a closed-form expression of Eb/NQ degradation due to DC offset for a direct-sequence code-division multiple access (DS-CDMA) system that serves as a good example to explain the problem. The modified Eb/NQ is given by: E°b 1 (2.2) N§1 + Chapter 2. Background 20 In Equation (2.2), E^/NQ represents EB/N0 without any receiver impairments and RC is the chip rate. NQRC is the additive white Gaussian noise (AWGN) power in the band of interest and dc2 represents power in the D C signal. Hence, Equation (2.2) reveals that DC offset is as deleterious to receiver SNR as is A W G N noise. Since the signal is directly down-converted to baseband, flicker noise causes an in-band distortion. Figure 2.5 shows the co-existence of the demodulated signal and the flicker noise in the output of a D C R receiver [19]. Flicker noise arises from random trapping of charge at the oxide-silicon interface of M O S F E T 2 devices. It is represented as a voltage source in series with the gate. The noise power density is given by [10]: where W and L are the width and length of the gate and Cox is the gate capacitance. K is a process-dependent constant and / is the frequency. Since this noise is inversely proportional to frequency, it is also called 1// noise. As shown by Equation (2.3), one way of reducing nicker noise is by making the transistor dimensions larger and this is possible because the stages following the mixer in a receiver run at relatively lower frequencies; therefore, these stages can use relatively larger devices to minimize the effect of flicker noise. Another way of reducing flicker noise is to use PMOS devices instead of NMOS, because PMOS has smaller value of K compared with NMOS [20]. 2The MOSFET is composed of a channel of n-type or p-type semiconductor material, and is accordingly called an NMOS or a PMOS 2.2.2 F l i cker Noise K 1 WLCoxl (2.3) Chapter 2. Background 21 N X Flicker Noise 1/f Noise Corner Thermal Noise Frequency (Hz) Figure 2.10: Flicker noise and concept of 1/f noise corner Figure 2.10 shows flicker noise that has 1/f characteristics and thermal noise has flat characteristics over the frequencies of interest. This figure also defines the 1/f noise corner, fpL, &s the frequency at which flicker noise equals the level of thermal noise. It is highly desirable to make fpL as small as possible. This is of critical importance for a D C R architecture and for modulation schemes that have highest energy in the middle of the band (e.g., G M S K [21]). Flicker noise of each individual transistor in the baseband circuitry contributes to the overall flicker noise effect; therefore, reducing the number of active devices in the baseband reduces this effect. Higher-gain front-end circuitry can also help to reduce the impact of flicker noise; however, this may compromise the overall linearity of the receiver. The choice of semiconductor process also affects the level of flicker noise associated with each active element. Compound semiconductor and silicon (Si) bipolar processes typically have Chapter 2. Background 22 a lower flicker noise corner-frequency than the popular CMOS processes [19]. 2.2.3 A m p l i t u d e and Phase Imbalances Ideally, the sine and cosine signals from the local oscillator should be exactly 90 degrees out of phase and the gain and filtering of I and Q channels should also be identical. In practice, however, due to various imperfections that will be described later, the sine and cosine signals are not exactly 90 degrees out of phase. Also, the gain and filtering on I and Q channels do not exactly match. A l l of these mismatches result in the creation of an unwanted image signal that deteriorates the receiver performance. With no mismatch, the ideal LO signal is 3 XLo{t) = 2cosuLot + j2sinur,ot- However, in DCRs, I and Q demodulations are typically performed in the analog domain and thus are susceptible to component mismatches. In practice, all analog components in the I and Q paths, such as oscillators, mixers, filters, and A / D converters, contribute to the total receiver imbalance. Typically, the individual imbalances between the I and Q branches in the analog parts are combined and modeled as a single gain and phase imbalance in L O signal [13, 22], xLO(t) = 2coscoLOt + 2j(l + e)sm(uLOt + Acj)), where e is the gain mismatch and Acj) is the phase mismatch. This I/Q mismatch causes amplitude and phase distortions in the received signal and consequently degrades the bit-error-rate (BER) of the system. Ideally, the incoming real signal is multiplied by a complex exponential g-j^Lo* T n e e f f e c t of I/Q mismatch is equivalent to multiplying the R F signal with the following expression [10]: 3The 2 factor is just for convenience in calculation Chapter 2. Background 23 2 3 Gain mismatch (%) Figure 2.11: IRR calculation for different gain and phase mismatch. c(t) (2 .4 ) where, c(t) is the complex exponential carrier in the presence of mismatches. Note that if e and A 0 are zero, the second exponential disappears. From the expression in Equation (2.4), an expression for image rejection ratio (IRR) 4 can now be derived. It is simply the ratio of the amplitude of the positive exponential to the amplitude of the negative exponential. In terms of dB, this ratio is expressed as: IRRdB = 10logw l + 2(l + e) cos A 0 + ( l + e)2 1 — 2(1 + e) c o s A 0 + ( l + e) 2 ' (2.5) Figure 2.11 shows a graph of IRR dependence on both gain and phase mismatches. The IRR will be infinite at the origin when there are no mismatches. It drops off quickly for non-zero values of e and A0. The impact of I /Q mismatch is illustrated in Figure 2.12 in a 4 IRR is the ratio of the intermediate-frequency (IF) signal level produced by the desired input fre-quency to that produced by the image frequency. Chapter 2. Background 24 constellation diagram of a 4 -QAM system. The dark dots are the ideal positions whereas the light dots are due to a specific I/Q mismatch (e = 0.1 and A</> = 10°). Also shown here are the time-domain effects of this mismatch on the I and Q waveforms . Note the changes in voltage levels in the quadrature phase case. 2 -| • I 1 • • ; • Ideal • • Actual dvM to IQ mismatch 1 -2 -1 1 f 2 • -1 - • • -2 -- Ideal With IQ mismatch 200 400 600 800 1000 1200 - Ideal With IQ mismatch 400 600 1000 1200 Figure 2.12: The effect of I /Q mismatch Chapter 2. Background 25 Sources of I / Q Mismatch Even with careful layout and circuit design, the cos(wr/o't) and sin(wr,ot) signals from L O to mixer have layout and parasitica differences. These differences disturb the 90° phase difference between cos(wLot) and sin(wLot), resulting in phase mismatch. In addition, phase and gain mismatches are generated by the mixer itself because of M O S F E T thresh-old voltage mismatch between the transistors in a differential circuit [23]. In general, the cos(wi,ot) and sin(wLot) signals reaching the mixer may have a phase difference that is between 80-100 degrees, i.e., a phase mismatch of ±10 degrees. The gain mismatch primarily arises from the mismatch between the characteristics of transistors on the two channels used to achieve amplification and it can be as high as ±10% in existing receiver implementations. Another factor that produces both phase and gain mismatches is the difference in filtering between I and Q channels. 2.2.4 Second-Order In te rmodula t ion ( IM2) D i s t o r t i o n DCRs are susceptible to both odd and even order intermodulations. For the purpose of distortion analysis, the transfer characteristics of a circuit may be expressed by a Taylor series expansion: F[x(t)] = K0 + K![x(t)] + K2[x(t)}2 + K3[x{t)}3 + ... (2.6) The term K2[x(t)]2 represents the second-order nonlinearity, which can cause severe per-formance degradation in a DCR, especially when exposed to strong signals. Consider the Chapter 2. Background 26 scenario in which two strong signals, cosu-yt and cosu2t, are within the bandwidth of the receiver's preselection filter but differ in frequency by an amount less than or equal to the signal bandwidth of interest (as defined by the receiver's channel select filter). When these signals are exposed to a second-order nonlinear circuit behavior, undesirable base-band spectral components are generated. These include a D C component and a baseband spectral component centered at u>i — UJ2- This is based on the fact that: (cosuit + cos^t)2 = 1 + 0.5cos2uit + 0.5cos2u)2t + cos(coit + oj2t) + cos(cu2t — uit) Only the first and the last term (i.e., 1 and cos(u2t — uj\t)), where (to2 — ui) < (^channel) lie within the signal spectrum. These spectral components degrade the reception of the desired signal. Another undesirable effect is the result of exposing a single strong interferer to a second-order nonlinearity. This effect generates a beat, a2(t)/2, directly interfering with the desired signal, as given in Equation (2.7): (a{t)cos{ut + <p(t)))2 = ^ ^ ( 1 + cos(2ut + 2</>{t))) (2.7) Depending on the envelope, a(t), of this single strong interferer, IM2 will generate spe-cific baseband components affecting the performance of a DCR. For a constant envelope interferer, a(t) = Ac, IM2 generates an undesirable D C component which can be treated by methods of DC offset reduction. For a non-constant envelope, a(t) = Ac(l + m(t)), where m(t) is a function of time for amplitude modulation, the baseband beat generated from IM2 will be composed of several undesirable spectral components given by Equation Chapter 2. Background 27 (2.8): a2(t) _[l + Ac(l + m(t))}2 , , ^ 2 2 2 - -^[l + 2m(t)+m2{t)}. (2.8) These components include a DC component, A^/2, which can be addressed by known mit-igation methods, and other more troublesome baseband spectral components, ^[2m(t) + m(t)2}, for which mitigation would be very difficult. Protection of D C R against these undesirable effects requires a high second-order intermodulation rejection ratio (IMR2) between the amplitude level of the interferer(s) and resulting IM2 component. Typically, a figure of merit is specified by IIP2, which specifies a fictitious input amplitude at which the desired signal becomes equal in amplitude to the spectral component generated from IM2 (see Figure 2.13). Thus, a high IIP2 down-conversion mixer is required to minimize the effect of IM2 within a D C R [19]. 2.3 DC offset Reduction Methods One obvious solution to eliminate DC offset is to employ A C coupling; that is, use a highpass filter (HPF) in the down-converted data path, as in Figure 2.14(a). The transfer function of the A C coupling is HAC(S) = T+fic-This method has some drawbacks: 1. Many modulation schemes, e.g., G M S K and QPSK or Q A M followed by (root) raised-cosine pulse shaping, have significant signal energy in the center of the spec-trum. The center of the spectrum lies exactly at D C after down-conversion to zero-IF. In addition to removing unwanted DC, H P F also removes the desired signal Chapter 2. Background 28 Input Level (dBm) IIP2 Figure 2.13: Second-order input intercept point (IIP2) concept. energy and this results in degradation of B E R . If the modulation has no significant D C component (i.e., if there is no information close to DC), high-pass filters can remove DC offsets without significant degradation of the signal quality. This is the case in pagers using 2-FSK. This may also be a viable option for modulation schemes that have relatively wider channel bandwidth, e.g., W C D M A 5 . 2. The H P F is required to have a very small corner frequency to make sure that it does not unnecessarily filter out the spectral contents of the signal. As a rule-of-thumb, it is estimated that the 3-dB cut-off frequency of a high-pass filter should be approximately 0.1% of the symbol rate in these systems if significant degradation 5Wideband code division multiple access (WCDMA) is a type of 3G cellular network. Chapter 2. Background 29 Figure 2.14: D C offset cancellation techniques using (a)capacitive coupling, (b) linear feedback; and (c) sampling in the signal quality is to be avoided [24]. Such a low corner frequency requires prohibitively large capacitors (of the order nF) and resistors, or equivalent capacitors if implemented using switched capacitors. 3. Another major problem wi th A C coupling is that the coupling capacitors can take a significant time to charge up which means that the receiver can take tens of milliseconds to settle. In this regard, pre-charging techniques are often required. Another approach is a D C feedback loop, which uses negative feedback to cancel the D C offset, as depicted in Figure 2.14(b). A D C feedback loop forms a negative feedback at frequencies close to D C , thus filtering out the D C offsets. B o t h the D C offset of the Chapter 2. Background 30 input signal and the DC offsets of the amplifier are canceled at the output. The transfer function of the block diagram of Figure 2.14(b) becomes HFB(s) = Y ^ ^ f j ^ c -A major advantage of this approach over that in Figure 2.14(a) is that it employs only grounded capacitors and can therefore utilize MOSFETs [25]. Since the capacitance density of MOSFETs is much higher than standard parallel plate structures, this approach has a major area advantage compared to that in Figure 2.14(a). However, the nonlinearity of MOS capacitors can limit the system performance. The high-gain amplifier needed in this approach can also reduce the overall linearity of the system. A third approach uses the idle time intervals in digital wireless standards to carry out offset cancellation as shown in Figure 2.14(c). During the idle time intervals, the switch is closed and the offset is measured and stored on the capacitor. However, thermal noise of the switch mandates large values for the capacitor. Analog as well as mixed-mode solutions have been previously proposed to address the DC offset problem. Most solutions rely on good design and layout to reduce leakage and imbalances that cause these offsets. A n on-chip LO reduces DC offsets due to LO leakage, but this alone is not enough [16]. Some representative analog solutions are presented in references [2, 26-28]. A l l of these employ some form of a negative feedback loop to reduce DC offset. Figure 2.15 shows the architecture of the offset canceler proposed by Wang et al. in [2]. The summing amplifier has four inputs: in+ and in- are differential signals with DC offset component, Vref is a reference voltage and ctrl signal is a D C offset cancellation signal from the loop filter. The charge pump circuit will charge the loop filter if the comparator output is Chapter 2. Background 31 high and it will discharge the loop filter if the comparator output is low. Effectively, the output of comparator will have a 50% duty cycle in the absence of any DC offset in the input signal. If there is some non-zero D C offset, this will be reflected in the duty cycle of comparator output. When the loop converges, Ctrl will be adjusted to cancel the D C offset. The operation is similar to a Phase-Locked Loop (PLL). The response time and stability of this loop are determined by the charge pump and parameters of the loop filter. In summary, this solution has problems similar to an H P F and it is not sufficient by itself to remove DC offsets. As reported by Wang et al. in [2], after correction, the DC level is reduced to 5 mV and still needs further correction. Summing F r o m Loop Charge Filter Pump Figure 2.15: DC offset cancellation using analog techniques [2] Mixed-mode offset cancellation schemes are presented in references [2-4, 26-31]. While Lindquist and Isberg [26] and Shoval et al. [31] describe only one-step offset cancellation, Nezami [29] and Yoshida et al. [3] describe a two-step cancellation. Here, the solution presented by Yoshida et al. in [3], which is depicted in Figure 2.16, will be briefly described. Chapter 2. Background 32 In this scheme, time-invariant or static offsets are removed in the analog, or feedback, ADC LPF LPF A D C DAC Memory Averaging Circuit Averaging Circuit DAC Memory Figure 2.16: Mixed-mode DC offset cancellation [3] mode. The feedback loop includes A D C , averaging circuit, memory, D A C , summing circuit and L P F . Static D C offset is estimated by disconnecting the L N A from the antenna before the start of each burst. Time-varying or dynamic offsets are canceled in the digital feed-forward mode. The same averaging circuit in Figure 2.16 is used to estimate the D C level present at the A D C output and this estimate is then subtracted from A D C output to obtain a D C free signal. The presented approach is applicable to burst-based systems and the DC estimate made on one burst is applied to the data on the following burst. This will provide acceptable results only if data in contiguous bursts have more or less the same D C value; this may not be true for practical T D M A systems, especially in the presence of Chapter 2. Background 33 large nearby interferers. Some solutions utilize a known training data sequence to correct for DC offsets. A n example of this method is described in [30] where 5 training symbols in the preamble are used for offset correction. These schemes are not applicable to systems that do not have preamble and it also requires a very close collaboration with the digital baseband detector to achieve offset cancellation. In references [4, 32], an even harmonic mixer is proposed that, by design, eliminates LO leakage offsets if the transconductance (Gm) mismatch is considered negligibly small. Figure 2.17 shows a single-balanced version of the CMOS even-harmonic mixer as proposed by Fang et al. in [4]. The basic principle of an even-harmonic mixer is that the input R F signal is effectively mixed with the second harmonic of the LO generated frequency. Therefore, any L O leakage from L O to R F input does not get mixed down to D C . Rather, it is translated to the L O frequency and is easily filtered by receiver filters. Figure 2.17: Single-balanced CMOS even-harmonic mixer [4]. Chapter 2. Background 34 2.4 I/Q Mismatch Compensation As observed in Figure 2.11, to acheive an IRR of 30 dB or larger, phase and gain mis-matches of 3° and 3% (or less) are required. Such values are very hard to achieve without employing any mismatch correction techniques, either in the analog domain or in the digital domain. Both analog and digital correction techniques have been used to mitigate the effects of phase and gain mismatches. A l l of these techniques use some form of an adaptive algorithm to find the coefficients of a correction filter. A n example of a more recent mixed-signal technique is presented by Der and Razavi in [23]. A sign-sign (SS) least-mean squares (LMS) method is used to calibrate gain and phase errors of a Weaver image-reject receiver to achieve an IRR of 57 dB. A pure analog approach is presented by Behbahani et al. in [33]. A five-stage polyphase filter is used to achieve an IRR of 60 dB for wireless L A N applications. As explained in [33], the higher the number of polyphase filter stages, the higher the IRR. However, the area impact of this technique precludes its use in a low-cost, low-power design. Amongst the digital methods, the work of Y u and Snelgrove [34] is representative of signal separation techniques in the digital domain to improve receiver image rejection. A complex L MS algorithm is employed to separate the image from signal. Two other techniques are presented in references [35, 36]. Valkama and Renfors [36] proposed a method that requires separate complex digital mixers and filters for the image and signal paths to achieve a cleaner reference signal for L M S / R L S 6 adaptation. Having separate demodulation and filtering paths for signal and image is an unnecessary compli-6The LMS (least means square) and RLS (recursive least squares) algorithms used for determining the coefficients of an adaptive filter. Chapter 2. Background 35 cation. Tubbax et al. in [35] assumed that the training sequence is available as part of the preamble of a T D M burst. This is not true for some of the wireless standards such as G S M [21], where the training sequences are in the midamble. 2.5 Summary In this chapter, different receiver architectures have been reviewed, and since D C R has the lowest cost and power, this work focuses on it. D C R design issues have been addressed in detail, and the existing methods to address these problems have been reported. As mentioned before, DC offset, flicker noise and I/Q mismatch issues should be re-solved carefully in D C R design. The existing methods to address these problems are divided in two categories, analog and digital. The trend is to perform as much as pos-sible in the digital domain and to minimize the R F front-end (analog). Also, most of these methods focused on the problem for a specific case (a standard or a system) rather than providing a general solution. In the next chapters, we introduce a novel system-level approach which addresses DC offset, flicker noise and I/Q mismatch problems more generally, and can be implemented in digital or analog. Chapter 3. Complex Quantized Feedback 36 Chapter 3 Complex Quantized Feedback As emphasized in previous sections, there is a need to address the important issues of D C R design including DC-offset, baseline wander effect, I/Q mismatch and low-frequency noise. In this chapter, we address these issues with a general approach applicable to an arbitrary D C R receiver. The basic idea is to use the information available in the I and Q paths to minimize the effect of low-frequency noise, phase error, and mismatch in both paths. Communication systems using quadrature demodulation whose baseband signal spectrum have considerable energy near D C can benefit from this approach. 3.1 Overview of the New Approach First a simple Q F B system is used in both I and Q channels to reduce the effects of baseline wander due to AC-coupling as well as the effects of 1/f noise. Then, the use of complex (in the mathematical sense) cross-coupled Q F B is proposed and it is shown that the system can reduce the undesired effects of carrier phase error and I/Q mismatch. A cost-effective approach to remove such low-frequency disturbances is to use simple AC-coupling, i.e., a high-pass filter (HPF) in the down-converted signal path. This ap-proach has been successfully applied in pager systems to receive frequency-shift-keying Chapter 3. Complex Quantized Feedback 37 (FSK) modulated signals [8] [37]. Since the baseband spectrum of F S K signal has little energy around DC, AC-coupling allows low-frequency disturbance to be removed with minimal distortion to the signal spectrum. For more spectrally efficient modulation schemes, such as quadrature amplitude modu-lation, the baseband signal spectrum has significant energy at low frequencies. Employing AC-coupling H P F in the I and Q paths, as shown in Figure 3.1, can remove and/or mini-mize the unwanted effects of DC-offset and 1/f noise. However, this filtering also removes low-frequency portions of the desired signal. The filtering of the desired signal can cause significant performance loss and introduce severe intersymbol interference (ISI) [9]. V A C coupling A C coupling Baseband Processing Data "Out Figure 3.1: A direct-conversion receiver with AC-coupling • This inadvertent filtering out of the information bearing the low-frequency part of the signal, typically referred to as baseline wander (in connection with one-dimensional modulation schemes such as pulse amplitude modulation), makes the detection of the signal difficult and causes reduction of noise margin [38] [39]. To remove the baseline wander effect introduced by AC-coupling, a quantized feed-Chapter 3. Complex Quantized Feedback 38 back (QFB) circuit can be used [40]. Q F B is a DC restoration technique in which the low-frequency components of the desired signal are restored by post-decision feedback. Employing Q F B is essential for operation with input patterns having large low-frequency content [41]. For example, in 100 B A S E - T Fast Ethernet systems, Q F B is used to re-duce the baseline wander effect [42]. A conceptual block diagram of Q F B (also known as baseline wander correction) is shown in Figure 3.2. The corresponding time-domain waveforms at different nodes of the system are also shown. The basic idea behind this scheme is as follows: the low-pass filter (LPF) in the feedback path restores the low-frequency components from the output signal (assuming correct decisions) and adds it to the high-pass filtered input signal to reconstruct the entire spectrum [40] [43] [44]. Ideally, the L P F in the feedback loop has the same order and cut-off frequency as the H P F in the feed-forward path. A cross-coupled (CC) Q F B , an extension of the simple Q F B system, is the one of the main contributions in this dissertation, and is described in more detail in the next section. Vl(t) data in high-pass circuit v2(t) decision circuit r u i v4(t) v3(t) low-pass circuit data out Figure 3.2: Conventional quantized feedback technique Chapter 3. Complex Quantized Feedback 39 Simple AC-coupling and quantized feedback can be combined to obtain a cost-effective approach for removal of DC-offset and 1// noise. This scheme is shown in Figure 3.3. The received signal is down-converted into its I and Q components with high-pass filters HACI(S) and HACQ{S) performing AC-coupling in I and Q branches, respectively, and low-pass filters, Hn(s) and HQQ(S), complete the Q F B system. r(t). i LO r • m Figure 3.3: Simple system including high-pass filter and quantized feedback To improve this basic system, we propose the use of cross-coupled feedback circuits [45] to compensate for the carrier phase error and/or I/Q mismatch and to eliminate the crosstalk between the in-phase and quadrature paths. Figure 3.4 shows such a system which can be considered as a complex Q F B system. Cross-coupled filters are added between the two channels for carrier phase error compensation and/or I/Q mismatch Chapter 3. Complex Quantized Feedback 40 correction. HIQ(S), for example, represents the feedback system from in-phase channel to quadrature channel. HACI{S) and HACQ(S) are the transfer functions of the AC-coupling blocks in the in-phase and quadrature channels. The purpose of the in-phase feedback blocks, Hn(s) and HQQ(S), is DC restoration. 4N x(t) e H |Q(s) HQI(s) y(t) I * a(t) b(t) Figure 3.4: Complex Q F B system In this complex Q F B system, assuming that the properties of the high-pass filters, HACI and HACQ, are known, it is possible to derive the expressions for other filters in the system (namely, Hu, HJQ, HQJ and HQQ) that achieve approximate carrier phase error compensation and/or I /Q mismatch correction. Suppose the received signal is r(t) = a(t)cos(uct) + b(t)sin(uct), where the carrier frequency is uc, and a(t) and b(t) are information bearing baseband signals. As is done in Chapter 3. Complex Quantized Feedback 41 [46] in the context of an equalizer, if we assume that there are no decision errors, one can replace the output signals a and b with a and b, respectively. Therefore, in the Laplace transform domain, we can write: X(s) = HACi(s)I{s) + HII(s)A{s) + HQI(s)B(s) (3.1) Y(s) = HAcQ(s)Q(s) + HQQ(s)B(s) + HJQ(s)A(s). (3.2) Also, under ideal conditions and in the absence of noise, the sheer's output is the same as its input: X(s) — A(s) and Y(s) = B(s). Using the above equations and assumptions, the Q F B filters' transfer function can be derived, as discussed in the following subsections. 3.2 Carrier Phase Error Compensation In this section, we assume that there is a carrier phase error 9 between the transmitter and receiver LO. That is, both in-phase and quadrature L O signals encounter the same carrier phase error, 6. It is shown that a cross-coupled Q F B system can be used for compensating this carrier phase error. Recall that the received signal is r(t) = a(t)cos(uct) +b(t)sin(uct). Now let us assume that the carrier recovery system in the receiver has successfully recovered the carrier frequency; however, there is still a residual carrier phase error 9. That is, the L O signals are XLo,i(t) = cos(uct + 9) and XLo,o.(t) — sin(uct + 6). Multiplying r(t) by these two L O signals and filtering out the higher frequency components, the following baseband signals are obtained: xBB,i(t) = a(t)cos9 — b(t)sin9 and XBB,o.{t) = b(t)cos9 + a(t)sin9. Note Chapter 3. Complex Quantized Feedback 42 that the I and Q signals are now correlated and, in the s-domain, we have: I(s) = aA(s)-pB(s), (3.3) Q(s) = aA(s)+pB(s), (3.4) where a = cosO and (5 = sinO. At the summing nodes of Figure 3.4 in the I and Q signal paths, we have: A(s) = HACI(s)I(s) + HII(s)A(s) + HQI(s)B(s) (3.5) B(s) = HACQ(s)Q(s) + HQQ(S)B(s) + HIQ(s)A(s) (3.6) Substituting I(s) and Q(s) from Equation (3.3) and (3.4) into (3.5) and (3.6), we obtain: 0 = {aHACI(s) + Hn(s)-l}A(s) + {-PHAci(s) + HQI(s)}B{s) 0 = {0HACQ(S) + HIQ(s)}A(s) + {aHACQ(s) + HQQ(s) - l}B(s) Therefore, the following relationships can be established between the six filters: Hu(s) = l-aHACI{s) (3.7) HQI(s) = PHACi(s) (3.8) HIQ(s) = -(3HACQ(s) (3.9) HQQ(s) = l-aHACQ(s) (3.10) Chapter 3. Complex Quantized Feedback 43 This shows that the four Q F B filters, H N , HJQ, HQI and HQQ, are functions of the A C -coupling filters and residual carrier phase error. Assuming that Equation (3.7)-(3.10) are satisfied, the crosstalk can be minimized. Note that, in practice, the assumption of no decision errors is only valid for small phase errors, as confirmed by simulation results in Sections 3.3 and 3.4. 3.2.1 I / Q M i s m a t c h Compensa t ion I/Q mismatch can be characterized by two parameters: the amplitude or gain imbalance between I and Q branches, e, and the phase orthogonality mismatch, A 0 . Therefore, the L O signal for I and Q branches can be written as: After multiplying the received signal by the two L O components and low-pass filtering the result, we obtain the following baseband signals: xLO,i(t) = 2cosuct XLO,Q(t) = 2(1 + e)sin{ujct + A 0 ) XBB,l(t) = a(t) XBB,Q.{t) (1 + e)a{t)sinA(f) + (1 + e)b{t)cosA(f) or equivalently: I(s) A(s) (3.11) Chapter 3. Complex Quantized Feedback 44 Q(s) = [(l + e)sin/\(p}A(s) + {{l + e)cosA(p]B(s). (3.12) Substituting I(s) and Q(s) from the above in the Equations (3.5) and (3.6), we obtain: Hn's) = l-HACi(s) (3.13) HQI(s) = 0 (3.14) HIQ(s) = -{l + e)sinA<t>HACQ{s) (3.15) HQQ(s) = 1 - (1 + e)cosA<l>HAcQ(s) (3.16) In the presence of both carrier phase error and I /Q mismatch, we have: Hn{s) = l-cos9HACi(s), (3.17) HQI(s) = sinOHACI(s), (3.18) HIQ(s) = -(l + e)sin(6 + A(f>)HACQ{s), (3.19) HQQ(s) = l-{l + e)cos{e + A^HACQ{s), (3.20) By satisfying these equations, the effects of these non-idealities on B E R can be minimized. 3.3 Simulation Results To demonstrate the advantages of the use of simple and complex Q F B in AC-coupled integrated receivers, a D C R using a 4 -QAM scheme is simulated. In all simulations, root-raised-cosine pulse-shaping filters with 30% excess bandwidth are used. A flat communi-Chapter 3. Complex Quantized Feedback 45 cation channel with A W G N is considered. The simulations are performed using M A T L A B and Simulink. The simulation results for the base system, i.e., A W G N channel with no AC-coupling are verified with the theoretical bit error rate versus SNR per symbol for square M - Q A M constellations [47] to ensure testbench correctness. Further simulations on the testbench are then carried out to illustrate the benefits of employing simple and complex Q F B in an AC-coupled DCR. Each simulation is performed with a set of noise levels (resulting in SNRs between OdB and 12dB). Depending on the noise level, an ade-quate number of symbols are transmitted and received to collect reliable results. For each SNR level, the corresponding B E R is calculated. Simulation results are presented using B E R versus SNR graphs. - The results of the first simulation demonstrate the effect of baseline wander caused by AC-coupling, as shown in Figure 3.5. In this setup, a first-order H P F (HACi = HACQ = s+2nfc) * s added in the received I and Q baseband paths (as shown in Figure 3.1). It is seen that B E R increases significantly as the H P F cut-off frequency (fc) increases, primarily due to baseline wander effects. Note that the cut-off frequency of H P F is normalized to the baud rate of the system. It can be seen that when the cut-off frequency of the H P F is below 0.1% of the data rate, B E R degradations are negligible, as mentioned in [1]. Since the amount of ISI introduced increases as the AC-coupling cut-off frequency increases, a smaller cut-off frequency for the AC-coupling filters is preferable. However, the smaller the cut-off frequency of the AC-coupling filter, the larger is its associated time constant, resulting in a slower response time. On the other hand, in connection with DC-offset and l/f noise removal, a larger cut-off frequency of the AC-coupling filter is more Chapter 3. Complex Quantized Feedback 46 SNR (dB) Figure 3.5: Simulation results (DCR with H P F of different cut-off frequencies) desirable. Therefore, the selection of the AC-coupling cut-off frequency requires a careful balance between two conflicting objectives: minimizing ISI and maximizing immunity against DC-offset and 1// noise. To compensate for baseline wander effects, a simple Q F B (DC-restorer) is added to the I and Q baseband paths, as illustrated in Figure 3.3. It can be seen from Figure 3.6 that the B E R performance of the system is noticeably improved compared to that of Figure 3.5 where no Q F B is used. Further simulations are performed in Figure 3.7 to show the effect of the residual Chapter 3. Complex Quantized Feedback 47 10 - © — No HPF — HPF (fc=0.1% baud rate) + QFB - E h - HPF (fc=1% baud rate) + QFB -0— HPF (fc=5% baud rate) + QFB - s ^ — HPF (fc=10% baud rate) + QFB •^f— HPF (fc=20% baud rate) + QFB 4 6 SNR (dB) 10 12 Figure 3.6: Simulation results (DCR with H P F and QFB) carrier phase error in the receiver's LO. First, a system with H P F cut-off frequency of 1% of the baud rate and simple Q F B DC-restorer is used as the base system. A set of phase errors (referred to as ph in the simulation results) from 0° to 20° are applied to the system. Figure 3.7 shows the B E R versus SNR curves in the presence of different phase errors. It is worth noting that when the carrier phase error is below 1°, the performance degradation of the overall system due to carrier phase error is negligible. However, when carrier phase error becomes larger, system performance is considerably degraded. To compensate for carrier phase error in an AC-coupled DCR, a complex Q F B system Chapter 3. Complex Quantized Feedback 4 8 10 - 0 — HPF(fc=1%) + QFB + ph=0 deg HPF(fc=1%) + QFB + ph=0.2 deg - B — HPF(fc=1%) + QFB + ph=1 deg HPF(fc=1%) + QFB + ph=5 deg - 5 y t - HPF(fc=1%) + QFB + ph=10 deg HPF(fc=1%) + QFB + ph=20 deg 6 SNR (dB) 10 12 Figure 3.7: Simulation results ( D C R with H P F , Q F B and carrier phase error) similar to Figure 3.4 is simulated. The complex Q F B blocks are designed according to the equations derived in Section 3.2. The simulation results are presented in Figure 3.8. A comparison between Figure 3.7 and Figure 3.8 indicates that, relative to simple Q F B , complex Q F B drastically improves the B E R performance of an A C - C o u p l e d D C R in the presence of carrier phase error. A s another illustrative comparison, Figure 3.9 shows simulation results of a D C R in the presence of H P F and carrier phase error without any Q F B . A s can be seen by referring back to Figure 3.8, complex Q F B compensates the carrier phase error and, especially for phase errors of 10° or smaller, the result is very close Chapter 3. Complex Quantized Feedback 49 LD 10" O HPF(fc=1%) + QFB + ph(0 deg) + cross coupling — HPF(fc=1%) + QFB + ph(0.2 deg) + cross coupling - B — HPF(fc=1%) + QFB + ph(1 deg) + cross coupling HPF(fc=1%) + QFB + ph(5 deg) + cross coupling V HPF(fc=1%) + QFB + ph(10 deg) + cross coupling HPF(fc=1%) + QFB + ph(20 deg) + cross coupling 6 SNR (dB) 10 12 Figure 3.8: Simulation results (DCR using complex Q F B with carrier phase error) to ideal. By comparing the results illustrated in Figure 3.7, Figure 3.8, and Figure 3.9 the effectiveness of the simple Q F B and the improvement due to the complex Q F B approach are validated. In all these experiments, carrier phase error is assumed to be constant and known, but in reality carrier phase error may change with time, and it is unknown. To verify the performance of the proposed system in the presence of time-varying carrier phase error, systems with the carrier phase error shown in Figure 3.10 are simulated. This time-varying phase is given as a carrier phase error to different systems. First, Chapter 3. Complex Quantized Feedback 50 LU CO -4 10 10 HPF(fc=1% baud rate) + ph=0 deg + no QFB > HPF(fc=1% baud rate) + ph=0.2 deg + no QFB • HPF(fc=1% baud rate) + ph=1 deg + no QFB 0 HPF(fc=1% baud rate) + ph=5 deg + no QFB HPF(fc=1% baud rate) + ph=10 deg + no QFB HPF(fc=1% baud rate) + ph=20 deg + no QFB 6 SNR (dB) 10 12 Figure 3.9: Simulation results (DCR using H P F with carrier phase error) a system is simulated with only H P F (cut-off frequency=l% of the baud rate), then a system with H P F and simple Q F B , and finally a system with the complex Q F B . The result is shown in Figure 3.11. Since the carrier phase error is changing with time, the result is shown as cumulative error versus time. As can be seen from this figure, the performance improvement due to the complex Q F B is significant. The result of complex Q F B is very close to an ideal system without any carrier phase error. Also, simulations are performed to show the effect of I /Q mismatch. First, a system with amplitude mismatch (e = 10%) and phase mismatch (A</> = 10°) is considered. Chapter 3. Complex Quantized Feedback 51 25 20 15 10 i 5 0 -5 -10 -15 -20 Time-varying phase error 100 200 300 400 500 600 700 800 900 1000 time(s) Figure 3.10: Time-varying carrier phase error system without phase error HPF(fc=1%) HPF(fc=1%) + QFB HPF(fc=1%) + QFB + CC _ i u 100 200 300 400 500 600 700 800 900 1000 time(s) Figure 3.11: Simulation result of time-varying carrier phase error effect on different sys-tems Chapter 3. Complex Quantized Feedback 52 Several scenarios are considered: 1) a system with only H P F with cut-off frequency of 1% of the baud rate, 2) a system with H P F and simple Q F B , and 3) the complete system including H P F and complex QFB. In Figure 3.12, the results are compared with that of an ideal system (without I/Q mismatch). The effectiveness of the proposed complex Q F B approach for I/Q mismatch compensation can be seen from this figure. 10 10 ' Different systems with IQ mismatch gain=10% and phase=10 degree HPF(fc=1%) - S — HPF(fc=1%) + QFB -0— HPF(fc=1%) + QFB + CC -Sy*— system without IQ mismatch (gain=0% and phase=0 degree) SNR (dB) 10 12 Figure 3.12: Simulation result of I /Q mismatch (e = 10% and A<f) = 10°) effect on differ-ent systems Figure 3.13 shows the simulation results for a system with different I/Q mismatch parameters (different amplitude and phase mismatch). As can be seen from this figure, the performance of the system in the presence of different mismatch parameters are very Chapter 3. Complex Quantized Feedback 53 10 10 =10% and 8=10° HH— E= 10% and 6=5° - B " e = =5% and 9=10° ^ E= =5% and 9=5° ^ e= =0% and 9=0° 6 SNR (dB) 10 12 Figure 3.13: Simulation result of different I/Q mismatch parameters close to the case where there is no mismatch. This indicates the effectiveness of the complex Q F B approach in compensating I/Q mismatch, assuming that the I/Q mismatch parameters are known. Any carrier phase error estimation scheme is prone to inaccuracies, but the system should be able to tolerate them to some degree. To show that the proposed system is relatively robust to inaccuracies in carrier phase error and mismatch estimations, the system is simulated with different values for these errors. In the first experiment, the complete system including H P F , Q F B and cross-coupled Chapter 3. Complex Quantized Feedback 54 filters is simulated in the presence of noisy phase error estimations (Figure 3.14). The effect of an inaccurate carrier phase error estimation is modeled by adding a random zero-mean Gaussian variable to the nominal value of the phase error. The standard deviation of this variable is 5% of the nominal value of the carrier phase error. To demonstrate that the proposed system is stable to error in the carrier phase error and mismatch estimation, the system with different types of error has been simulated. In first experiment, the complete system including H P F and Q F B and cross coupled filter with carrier phase error was simulated. These results are shown in Figure 3.14. Here we assumed that the estimation of the real carrier phase error in the system is not accurate and is a random number with the same average as the real carrier phase error and 5% standard deviation. As observed in Figure 3.14, the results for accurate and noisy carrier phase error estimations are comparable. That is, the system is capable of tolerating a modest amount of noise in the estimation of the carrier phase error. The next experiment is designed to examine the behavior of the system with I /Q mis-match in the presence of noise and estimation errors (Figure 3.15). The complete system, including H P F and Q F B and cross-coupled filters, is simulated first with mismatch param-eters of e = 5% and Acf> = 5°. Then, the system with the same mismatch parameters, but with an error (zero-mean Gaussian with a 5% relative standard deviation) in mismatch estimation is simulated. The next simulation is for the system with time-varying I /Q mismatch parameters at the L O signal with a 5% standard deviation. In the last step, the system with the same mismatch parameters as before, plus 2% and 2° mismatch in the Chapter 3. Complex Quantized Feedback 55 0 1 2 3 4 5 6 7 8 9 10 SNR(dB) Figure 3.14: Simulation result for noise in carrier phase error estimation Q F B is simulated. The results show that the system is robust with respect to estimation errors of carrier phase error and mismatch, as well as variable mismatch parameters at the L O and mismatch in Q F B . 3.4 Design Issues In this section, some design issues of complex Q F B systems are discussed. Since the objective of this work is to develop a cost-effective and integrable technique for DC-offset removal and carrier phase error and/or I/Q mismatch compensation, a receiver design Chapter 3. Complex Quantized Feedback 56 10° SNR (dB) Figure 3.15: Simulation result for effect of noise in system with mismatch estimation that uses this technique should deliver on these objectives. Using CQFB in addition to AC coupling can make an AC coupling a practical solution. Since the CQFB technique recovers the low-frequency part of the desired signal, it can be used for modulation with low-frequency or DC component, and also the HPF is not required to have a very small corner frequency to make sure that it does not unnecessarily filter out the spectral contents of the signal. In the complex QFB system, shown in Figure 3.4, each AC-coupling filter can be a simple first-order HPF. However, the design of the four feedback and cross-coupling filters Chapter 3. Complex Quantized Feedback 57 is more involved. Ideally, these filters have to be monolithic and they need to be adjustable or adaptive to track the possible changes in the carrier phase error of the receiver LO. Therefore, one of the key challenges is the design of adaptive filters. 3.4.1 Des ign Considerat ions for A d a p t i v e F i l t e r s At low data rates, adaptive filtering is easily and efficiently performed using digital cir-cuits. On the other hand, analog filters are preferable, at high speeds when low power consumption, small integrated area, and moderate linearity are required [48]. The designer of a modern analog adaptive filter is required to simultaneously consider both system-level and circuit-level issues. The first step is to choose an adaptive algorithm. The algorithm adjusts the parameters of the filters to optimize their performance in an unknown and possibly time-varying environment. Two widely-used adaptive algorithms for filters are least-mean-square (LMS) algorithms and heuristic algorithms [48] [49]. The best adaptive algorithm for a particular situation is often dictated by the filter's structure. A n important criterion in selecting a filter structure is that a suitable adaptive algorithm exists, preferably with a straight-forward and robust hardware implementation. Also, the filter structure should not go unstable during adaptation. Possible choices of filter structure are transversal filters, biquad filters, Laguerre filters, and orthonormal ladder filters [48] [49]. Chapter 3. Complex Quantized Feedback 58 3.4.2 Exper iments on A d a p t i v e F i l t e r s Considering the equations for low-pass filters and cross-coupled filters, the adaptive design for two cross-coupled filters is relatively straight-forward, because the changes in the carrier phase error merely affect the gain of the filters. However, for low-pass filters in the Q F B , the changes in the carrier phase error affect both gain and cut-off frequency characteristics of the filters. Several experiments on the behavior of the feedback filters in the Q F B system were conducted. For a system with known H P F (AC-coupling filter), the transfer functions of the feedback Q F B filters for different values of carrier phase error are shown in Figure 3.16. It should be noted that the poles and zeros of HIQ and HQJ filters are fixed. However, for Hu and HQQ filters, the poles are fixed, but the zeros positions alter as the carrier phase error changes. Therefore, the cut-off frequencies of the Hu and HQQ filters change slightly as a function of carrier phase error. For a first-order H P F with cut-off frequency, fc, the cut-off frequency of the Q F B filters for different phase errors can be calculated as: The results for different phase errors are plotted in Figure 3.17. When there is no carrier phase error, the L P F cut-off frequency is the same as that of the H P F . When there is carrier phase error, it increases rapidly beyond 30° in the manner shown in Figure 3.17. For phase errors smaller than 30°, the change of cut-off frequency is negligible. This fcut—off fc (3.21) Chapter 3. Complex Quantized Feedback 59 Sing Figure 3.16: Low-pass filter characteristics for different phase errors (0° < 9 < 70°) observation is very important in design, because there are some clever single Q F B circuits (same cut-off frequency for low-pass and high-pass) [38] that would be useful for systems with small phase errors. 3.4.3 Ca r r i e r Phase E r r o r E s t i m a t i o n Of course, carrier phase error in the receiver LO can be time-varying. In order to ac-complish carrier phase error compensation in this case, the Q F B filters account for a time-varying carrier phase error. As a consequence, the ability to estimate or detect the carrier phase error is required. In the following, one of the standard methods of carrier Chapter 3. Complex Quantized Feedback 60 10 20 30 40 phase error (degree) 50 Figure 3.17: Cut-off frequency of low-pass filter for different phase error phase error estimation is considered. On the topic of carrier recovery in [46], a method to estimate carrier phase error is discussed. In the equation below, (xk,yk) and (dk,bk) are samples of the received signal before and after the decision maker (the slicer), respectively. Samples of carrier phase error in the demodulator are denoted as 9k- Carrier phase error can be estimated with the following expression [46]: o _ ^ - u I m { ( x k + 3Vk)(ak + jbk)*}, uk — [ | 9 J In Figure 3.18, a system that attempts to implement the above technique to estimate the carrier phase error and accordingly calculate the complex filters is shown. Note that the estimation of carrier phase error is mathematical, but the implementation can be Chapter 3. Complex Quantized Feedback 61 r(t) — * W Figure 3.18: Complex Q F B with phase estimator carried out using techniques such as look-up tables. The results of the experiments for this system are shown in Figure 3.19. As seen in this figure, the performance of the system for phase errors smaller than 10° is very close to ideal. 3.5 Summary In direct conversion receivers using bandwidth-efficient modulation-schemes (e.g., Q A M ) , DC-offset and l/f noise are problematic. If they are not compensated for, the overall sys-tem performance will deteriorate. It is shown that a complex Q F B system can effectively correct baseline wander effect and compensate for receiver carrier phase error as well as I/Q mismatch. A large number of simulations in MATLAB/Simul ink were carried out to Chapter 3. Complex Quantized Feedback 62 Complex QFB system with phase detector IO" L | | I I SNR (dB) Figure 3.19: Simulation result (Complex Q F B with phase estimator) demonstrate the effectiveness of complex quantized feedback system. Design considerations for adaptive filtering has been described, and based on the experiments, we found that for small amount of phase error, the changes in the filters characteristics are not significant. Also, a standard method to estimate the receiver's carrier phase error was reviewed. It is observed that, for carrier phase error of less than 10°, the system performs reasonably well when the carrier phase error is estimated using the aforementioned standard method. Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 63 Chapter 4 Adaptive Digital Signal Processing Techniques for CQFB 4.1 Introduction One of the main trends in the evolution of radio receivers and other wireless devices is to implement more and more of the receiver functionalities using digital signal processing (DSP). The design and implementation of radio receivers for wireless terminals is currently dictated by the strong push towards flexible and software configurable receiver structures able to operate over multiple frequency bands. The terms multimode, multiband, and multistandard radios are commonly used in this context. A key ingredient in building flexible radios is the efficient use of DSP. Enabled by the recent advances in DSP techniques, both at the algorithmic and the implementation levels, as well as in the A D C technologies, more and more of the receiver functionalities can be implemented using DSP. However, due to the fundamental gap in the used radio frequencies (typically on the order of 1 to 10 GHz) and supported maximum sampling frequencies (up to a few hundred megahertz, depending on the needed resolution and dynamic range), some receiver analog front-end stages are still needed. With the Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 64 ever-increasing demand for the system performance and supported data rates on one side, and the terminal flexibility and implementation costs on the other, the requirements for these remaining analog front-end stages become extremely challenging to achieve. One interesting idea in this context is to apply sophisticated DSP-based techniques to compensate for some of the most fundamental nonidealities of the receiver analog front-end. The proposed mitigation techniques are based on purely digital processing of the re-ceived signal and can be used to suppress distortions including carrier phase error, I /Q mismatch, D C offset and other low frequencies disturbances. In this chapter, we focus on developing and demonstrating the application of C Q F B techniques to mitigate the effects of the analog R F front-end using digital adaptive filtering. The approach in general is practically-oriented and largely based on analyzing and processing measured real-world receiver front-end signals. Our approach is illustrated in Figure 4.1 which shows where the DSP implementation of C Q F B fits into the overall system. The figure depicts a simplified receiver, from antenna (input) to detected symbol (output). As mentioned before, it is desirable to minimize the analog front-end. Therefore, the C Q F B is implemented in a DSP processor after A / D converters. Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 65 V LNA i(t) -XX) • LO q(t) AID AID HAc,<Z> HACQ® H„(Z) X[n] H | Q (Z) H Q I (Z) Y[n] I H Q Q ( Z ) DSP Processor Figure 4.1: Simplified receiver block diagram with DSP C Q F B . 4.2 I/Q Down-Conversion Based Front-End a[n] i b H | 4.2.1 I / Q Process ing Pr inc ip les Understanding the nature of bandpass signals and systems is the key in building efficient radio transmitters and receivers. In addition to the basic envelope and phase represen-tation, the so-called I/Q (in-phase/quadrature-phase) interpretation forms the basis for various spectrally-efficient modulation and demodulation techniques [46]. More generally, I /Q processing can be used in the receiver and transmitter front-end for efficient up/down conversion processing, independently of the applied modulation Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 66 technique. Given a general bandpass signal: 2Re[x(t)exp(juot)] = x(t)exp(ju>0t) + x*(t)exp(—ju0t) = 2xi(t)cos(tu0t) — 2xQ(t)sin(ujQi) the (formal) baseband equivalent x(t) = xi(t)+JxQ(t) can be recovered by multiplying the modulated signal with a complex exponential and low-pass filtering. This is illustrated in Figure 4.2, which also depicts the practical implementation structure based on two parallel real signals. In the receiver architecture context, the differences come basically from the interpretation of the down-converted signal structure. In general, both the direct-conversion and low-IF receivers utilize the I /Q down-conversion principle and are discussed in more detail in the following. exp(-jcoot) 2Re[x(t)exp(jo)0t)] cos(coot) 2Re[x(t)expCicoot)] Low-pass Filter x(t) (a) Low-pass Re[x(t)]=x,(t) ) Filter -sin(coot) fe Low-pass Im[x(t)]=Xo(t) Filter (b) Figure 4.2: Basic I/Q downconversion principle in terms of: (a) complex signals and (b) parallel real signals. Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 67 4.2.2 A r c h i t e c t u r a l Aspec ts As mentioned before, D C R or homodyne receiver is based on the idea of I /Q down-converting the channel of interest from R F directly to baseband. Thus, in a basic single-channel context, the down-converted signal after low-pass filtering is basically ready for modulation-specific processing such as equalization and detection. This is, in general, an interesting approach in the sense that it eliminates the use of any IFs results in a rather simple front-end processing, especially in terms of the needed R F / I F filtering. In the previous chapter, we showed that by using a complex quantized feedback (Fig-ure 3.4), the circuit design criteria can be simplified. The proposed receiver architecture mitigated D C offset, carrier phase error and I/Q amplitude and phase mismatches. They, however, assumed that the mismatch and error parameters are known (except for D C offset which is removed blindly). These parameters are then used to compute the decision feedback filters. In previous works, e.g. [50, 51], complex quantized structures were used to mitigate non-idealities of a D C R architecture. Although they do not assume that the non-idealities are known, both methods require a training mode prior to operation. We assume that the baseband signals after mixing are fed to the matched filters before being digitized. In Figure 4.3, the matched filters and anti-aliasing filters are represented as baseband filters. This way, the required sampling rate equals the symbol rate of the system - much less than the sampling rate necessary to perform matched filtering digitally. Following the previous chapter, we model the effects of noise (ni,nq), carrier phase error (6), phase mismatch (A0) , DC offset (iDC a,ndqDC ) and amplitude mismatch (e) on Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 68 L N A BPF Baseband Filters A / D LO Baseband Filters A / D Demod ulator .Data Out Figure 4.3: D C R with digital demodulation. the receiver signal (a[n], b[n]) by the formula given below: i[n] cos 8 — sin 8 ^ ^ a[n] + ni[n] ^ ^ (1 + e) sin(A0 + 8) (1 + e) cos(A<£ + 6) ) y b[n] + nq[n] J + 1>DC \ QDC J (4.1) where i[n] is the digitized Q A M signal to be demodulated digitally. The effects of the noise and other non-idealities are illustrated in Figure 4.4. The results of a high SNR= 20 dB are provided in Figure 4.4(a), and a low SNR= 5 dB in Figure 4.4(b). They are superimposed on the ideal 16-QAM constellation. Clearly, the effects of 8, e, A 0 , and D C offset are significant when no compensation is performed, especially for low SNR values. Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 69 t -SNR=5 dB (b) Figure 4.4: Effects of non-idealities on Q A M signal points: e = 15%, = 0 = 18°, iDc = 1 and qDC = —1.5 and SNR=20 dB (left) and 5 dB (right), superimposed on the ideal 16-QAM constellation ("x"). 4.3 Adaptive implementation of complex QFB 4.3.1 DC-offset removal filters To keep the detector circuit simple, we have to remove any DC offset prior to detection. A computationally-efficient way of removing the DC offset is to use a recursive first-order filter given by the following equation: 1 + a v[n] = — T T - C ^ W - x[n - 1]) + ay[n - 1] (4.2) in which x[n] and y[n] denote the input and output signals of the filter, respectively (not to be mistaken with I /Q signals before decision). The frequency response of this filter is shown in Figure 4.5. By choosing an a closer to one, a sharper transition to zero (-co Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 70 in dB) can be achieved at the cost of a longer time constant. The problem wi th a very sharp first-order filter is that it can become unstable when implemented in fixed-point arithmetic. In such a case, one may opt for a higher-order filter, which provides the same sharp transition to zero and remains stable when implemented in fixed-point [52]. 101 1 1 1 1 1 5 - -Normalized freq. (1 = TC) Figure 4.5: Frequency response of the first order DC-offset removal filter for a = 0.9. 4.3.2 C o m p l e x Q F B receiver We begin by assuming that the symbols are sti l l uncorrelated at the output of the D C offset removal filter 1 . Thus, the feedback filters given by Equations (3.17) to (3.20) can 1 Later in section 4.3.6, the system with ISI is considered. Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 71 be simplified to the following: Hn(z) = 1 — cosO, HQI{Z) = sinO, HIQ{Z) = -(l + e)sm(0 + A 0 ) , HQQ(z) = l - ( l + e)cos(0 + A 0 ) , which are simply gains. Let us define H = 1 H H ^ ( nil HQI \ HiQ HQQ J 1 — cos8 sinO y-{l + e)sin(A<j) + 9) 1 - (1 + e)cos(A(f> + 6) ] (4.3) Therefore, the complex quantized feedback detector should solve the following nonlinear equation for (x[n] y[n])T to detect each received symbol: x\n\ \ y[n\ j inoDc[n] \ QnoDcM J ^ 1 H H X ti-u HQI + • Q \ HIQ HQQ J x\n\ \ v[n\ j (4.4) H in which (in0Dc[n] QnoDc[n])T denotes the output of DC-offset removal filters for each symbol, and Q(x[n] y[n])Tis the detected symbol. The quantizer function Q(.) becomes sgn(.) in the case of 4-QAM signaling. A computationally efficient algorithm to solve this nonlinear equation is given in the following pseudo-code segment, in which IQ represents (inoDc[n] 7 n o D c W ) T - One may argue that it suffices to find one (x[n] y[n])T to satisfy the equation above. That is actually true in close-to-ideal detection (i.e., when noise and Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 72 other non-idealities are small). In other cases, Equation (4.4) may have multiple solutions, among which we are interested in the one that, minimizes the error (i.e., the distance from the ideal constellation). AB = All possible detected QAM symbols; . / / For example AB = {(-1, 1), (1, -1), (-1, -1), CI 1)} in / / 4-QAM. For k=l to length(AB), XY(k) = IQ + H * AB(k); D(k) = distance XY(k) and AB(k); End L = index of the smallest D The detected symbol is AB(L) The input to quantizer is XY(L) To perform complex Q F B detection, we assumed that the non-ideality parameters e, 9, and A 0 are known by measuring them in a training mode before operation. However, adding a training mode can complicate the receiver system. Besides, these parameters can vary in time and switching to training mode periodically may degrade the receiver performance. Thus, we employed a simple adaptive filter described later. 4.3.3 Estimation of non-ideality parameters The most intuitive approach to the problem, as suggested in [53], is to estimate the non-ideality parameters (e, 9, and Acp) and to update the Q F B filters accordingly. To that end, we re-write Equation (4.1) in the following form: lnoDc\n\ \ QnoDcln] J cos9 —sin9 \ (1 + e )sm(A0 + 9) (1 + e)cos(A(j) + 9) ) a[n\ + noise (4.5) ^ b[n] j w Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 73 Assuming that the noise power is small, we can attempt to compute the parameter-ized matrix, W, by pseudo-matrix inversion in a least-squares sense, since for each re-ceived symbol, we have (in0Dc[n] nnoDc[n])T a n d a good estimate of the decision output, A less computationally demanding solution to this problem is adaptive filtering as illustrated in Figure 4.6 [54]. This approach also accommodates variations of the 9, e, and A4> parameters. In Figure 4.6, (a[n] fr[n])T is the input signal x[n], the adaptive time-varying filter W is the digital filter block, the output W(a[n] b[n])T is y[n], and (inoDc[n] QnoDc[n])T is shown by d[n]. We would like to find W and update it over time, so that the output comes as close as possible to the ideal output. (d[n] b[n])T. d{n) x(n) Digital y(n) e{n) filter 2 Adaptive algorithm Figure 4.6: Adaptive filter block diagram. As indicated by the adaptive algorithm block in Figure 4.6, we need an adaptive algorithm for the filter implementation. The simplest algorithm, both intuitively and computationally, to perform this optimization is the well-known least mean squares (LMS) Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 74 [54] algorithm given by the following equations: W[n + 1] = w[n] + pX[n]e[n], (4.6) e[n] = d[n] - y[n], (4.7) y[n] = WT[n]X[n}. (4.8) L M S provides the updated filter weights using the input x[n] and the error e[n] which is the difference between the actual and the ideal outputs. Provided that the proportionality coefficient, p, is small enough, W[n] always converges to the optimal FIR filter. However, with a small p, L M S requires a long time to converge. Details of selection of a proper p given the signal statistics can be found in [54]. The LMS in our problem takes the following form: (Wn[n + 1] W12[n + l}) = {W11[n] W12[n]) + p(a[n] b[n])ei[n], e»[n] = inoDc[n] - (Wu[n] Wi2[n])(a[n\ b[n])T and {W21[n+1} W22[n + l]) = {W21[n] W22[n\) + p(a[n] b[n])eq[n], eq[n] = qnoDC[n} - (W2l[n] W 22W)(o[n] b[n])T in which Wij[n] is the element of the matrix W[n] at ith row and jth column. The non-Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 75 ideality parameters can be estimated from W by the following equations: . # 1 2 8 = —tan A 0 = t a n ' i ^ - e , e = \M2i + ^2 22 - l -which are used to update the complex Q F B filters given by Equation ( 4 .3 ) . Assuming that the non-idealities are small, the first-order approximations can be used for the computation of nonlinear functions in the following manner: e ^ W 2 2 - l . The initial value of W should be selected close to the final value, or the adaptive algorithm will experience slow convergence. That is, more symbols will not be correctly detected initially or more symbols are required in the training mode, if such a mode of operation is provided. Assuming that the non-ideality parameters are small, a good initial estimate of their values is zero. From Equation ( 4 . 5 ) , the initial value of W is thus 7 2x2 • Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 76 4.3.4 Di rec t adaptive decision feedback In this section, a computationally simpler solution, as compared to that of Section 4.3.3, is introduced. The method of this section is also numerically more stable than that of Section 4.3.3. After solving Equation (4.4) for a received symbol, we can consider the equation as a filter with H (given by Equation (4.3)) as the adaptive filter, and Q(x[n] y[n])T and (x[n] y[n])T as the input and output, respectively. The desired output, d[n] of Equation (4.7), is Q(x[n] y[n])T. By application of L M S , we reach the following update equation for H: (Hn[n + 1] H12{n + l}) = (Hn[n) H12[n}) + p(a[n] 6[n])e4[n], ei[n] = a[n] - inoDC[n} - (Hn{n] H12[n])(a[n] b[n])T and (H21[n + 1] H22[n + l]) = (H21[n] H22[n}) + p(a[n] b[n])eq[n], eq[n] = b[n] - qnoDC[n] - (H2l[n\ H22[n})(a[n] b[n])T in which (a[n] b[n])T is the decision output (i.e., Q(x[n] y[n))T) and (in0Dc[n] qnoDc[n])T denote the output of DC-offset removal filters for each symbol. The non-ideality parameters can be computed from H in order to monitor how well the adaptive filter compensates for the non-idealities. From Equation (4.3), we have: Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 77 A(f) = tan'1 J 1 2 1 - 9, H22 — 1 6 = ^ + (1 - tff2)2 - 1. Note that estimation of the non-ideality parameters is not necessary for detection (i.e., in the normal operation mode of the receiver). Thus, the computational complexity of this estimation should not be included in the overall complexity of the method. Unlike the method given in Section 4.3.3, the update formulas in the direct method, that do not include any nonlinear computations can be efficiently implemented in fixed-point arithmetic with no risk of instability. It is worth noting that, in floating point implementations of both methods, their B E R performance is almost the same although the estimates of non-ideality parameters differ for low levels of SNR. For the reasons given at the end of Section 4.3.3 and from Equation (4.3), H is initially set to 0 2 x 2 . 4.3.5 S imula t ion results To demonstrate the performance of adaptive compensation of non-ideality parameters in simulation, we generated a 1000-symbol 16-QAM sequence, with constant parameters of 9 = 0.2 rad, A</> = -0.25 rad, and e = 15%. With A W G N and SNR of 10 dB, only 3 (out of 1000) symbols were incorrectly detected whereas without the adaptive algorithm (i.e., H or W are not adaptively updated), 49 symbols were incorrectly detected. The same setup was used in both cases including the same pseudo-noise sequence, for fair Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 78 comparison. It is also observed that by increasing the SNR, adaptive compensation of non-idealities results in considerable improvement of symbol error rate 2 . Figure 4.7 shows the experi-ment performed with a 5000-symbol sequence while other parameters are the same as the first experiment. Clearly, the performance of the adaptive scheme is superior to the basic scheme. Using the C Q F B compensation, the performance is close to the ideal symbol error rate as illustrated in the figure. 10" 10 10 10 + Ideal x No compensation O Compensation on -2 6 8 10 S N R (dB) 18 Figure 4.7: The effect of the proposed method ("Compensation on") on symbol error rate vs. no compensation and ideal 16-QAM reception and detection (i.e., all non-ideality parameters, namely 9, e and A 0 are zero). The effect of initial values on convergence behavior of these parameters is shown in 2The symbol error rate is shown as Pe Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 79 Figure 4.8. Other parameters of this experiment were held the same values as in the first experiment. By initially setting W to i?,x2, the adaptive algorithm converges quickly (within the first 100 symbols) and fluctuates around the true values of non-ideality pa-rameters. By initially setting W to 0.5/2x2 , convergence takes 400 symbols to occur. During the time-to-convergence, 266 symbols are incorrectly detected! In contrast, the direct method has only a single detection error within the first 400 symbols. e A<|) e Symbol # Figure 4.8: The effect of initial value of the filter ( W; 0.5/ 2 x2 (light) and I2X2 (dark)) on convergence to non-ideality parameters. The SNR is set to 10 dB and the same pseudo-noise sequence is used for fair comparison. The 1000-symbol 16-QAM signal is generated with 9 = 0.2rad, Acp = -0.25rad, and e = 15%. The effect of gain mismatch on symbol error rate is shown in Figure 4.9. The other parameters are the same as the first experiment. It is observed that the adaptive com-pensation of non-idealities successfully controls the effect of gain mismatch on the symbol error rate. Note that in a well-designed circuit, the gain mismatch is ideally zero and will Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 80 not exceed 10%. 0 50 100 150 200 250 300 8 (%) Figure 4.9: The effect of gain mismatch (e) on symbol error rate, with and without adap-tive compensation of non-idealities. The effect of angular non-idealities (carrier phase error, 9, and phase mismatch, Ac/)) on symbol error rate is shown in Figure 4.10. A 3000-symbol 16-QAM sequence is used in this experiment with carrier phase error, 9, and phase mismatch, A 0 , varying between -0.9 and 0.9 rad (= 51° ). The other parameters are the same as the first experiment. The right figure shows the symbol error probability is low (dark points are desired since they mean close to zero values) for very small values of 9 and Acfi. After C Q F B compensation, for most of 9 and Acp values, the symbol error probability is small. Therefore, it is Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 81 observed that the adaptive compensation of non-idealities is successful (large dark area implies near zero symbol error rate for a wide range of non-ideality values). Also, note that if the carrier phase error (9) is small (the middle area of left image), the adaptive algorithm is effective for a large range of phase mismatch (A0) value. That is good news, as all receivers include a carrier synchronization mechanism that keeps 9 small. After CQFB Before CQFB -0.9 +0.9 -0.9 +0.9 9 (rad) Figure 4.10: Effect of carrier phase error (9) and phase mismatch ( A 0 ) on symbol error rate represented by image intensity (i.e., dark areas = small error rate), with (left) and without (right) adaptive compensation of non-idealities. 9 and A 0 vary between -0.9 and 0.9 rad (= 51° ). 4.3.6 Di rec t adaptive decision feedback w i t h ISI In communication systems, one of the effects of the channel on the transmitted symbols is inter-symbol interference (ISI). That is due to the fact that the frequency response of the channel is not ideal, i.e., not constant for all frequencies. Thus, the impulse response of the channel is not ideal, so a shifted impulse can result. Therefore, a convolution Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 82 of the channel impulse response with the transmitted signal, comprised of a sequence of modulated pulses, mixes a number of consecutive symbol pulses together. With no special provision to combat this effect, each symbol demodulated at the receiver is a linear combination of a number of the transmitted symbols. That is, the symbols that were uncorrelated at the transmitter can overlap and become correlated at the receiver. This ISI effect is well-known [55]. If the channel response is not known or varies with time, one way of ISI compensation is to use adaptive techniques [50]. To that end, a certain sequence of symbols known as a training sequence, which is known at the receiver, is sent once. At the receiver, the filters are adjusted to compensate for the ISI, and to de-correlate the received symbols. Here, we show that our method of adaptive compensation for non-ideality parameters can be generalized to remove small levels of ISI by decision feedback - with no need to use a training sequence. In Chapter 3, it was mentioned that decision feedback in the complex Q F B architecture is used to restore the D C components of the two signal channels lost by high-pass filter-ing. From another viewpoint, the high-pass filters, HACI(S) and HACQ{S) in Figure 3.4, generate a known ISI in I and Q channels and decision feedback filters are designed to remove ISI. When the ISI model is known, for example the ISI generated by DC offset removal filters, HACI(S) and HACQ(S) in Figure 3.4, the optimal decision feedback is simply given by Equations (3.17) to (3.20). Generally, the ISI is partly due to the channel and partly due to the D C removal filters and can be unknown and time-varying. That is why adaptive Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 83 compensation for ISI is necessary. Using the form of Equation (4.4), the new decision equation for the case with ISI becomes the following: x[n] = in0Dc[n] +a[n]* hu{ri\ + b[n] * hqi[n] y[n] = qnoDc[n] + a[n] * hiq[n] + b[n] * hqq[n] and the symbol '*' denotes the convolution. For example, ( hiq[0] a[n] * hiq[n] — (a[ri\, a[n — !],•••, a[n — N + 1]) ^[1] V hiq[N-l] j in which (a[n] b[n])T is the decision sequence, and him[n] is the impulse response of the filter that conveys the decision feedback from channel I to channel m. N is the length of each of the decision feedback filters. For detection, the nonlinear decision equation given above should be solved for every received symbol. The pseudo-code of Section 4.3.2 can now be used with the following definition: IQ = ^ inoDc[n] + a[n - 1] * (hti[n + l]u[n]) + b[n - 1] * (hqi[n + l]u[n]) ^ \ QnoDcin] + a[n - 1] * {hiq[n + l]u[n]) + b[n - 1] * (hqq[n + l]u[n]) That is, IQ represents the effect of current value of I and Q signals, plus the feedback of the decisions made so far filtered by the second coefficient of him[n] until the end. The Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 84 first coefficients of him[n] comprise the H that is used to filter the current decision. Following a procedure similar to that of Section 4.3.4, we reach the filter update equations below3: fr«+1M = h i M +p(a[n],a[n- 1],-• • ,a[nN+ l])T{a[n} - x[n]) hkqtM = hkqt[n} + p(b[n],b[n-l},---,b[nN + l])T(a[n}-x[n}) hk+x{n] = hkiq[n] + p(a[n], a[n - 1], • • •, a[nN + 1])T(b[n] - y[nj) KtM = hkqq{n}+p(b[n},b[n-l],---,b[nN + l})T(b[n}-y[n]) For reasons similar to those given in the previous section, all filters are initialized with zeros. The upper limit on p (required for convergence of LMS) is inversely proportional to the filter length, N [54]. Thus, we must choose a much smaller p as compared to the two-point adaptive filters used in the non-ISI case. This implies that the time-to-convergence will be much longer. Note that the decision feedback filters can be infinite-length impulse response (IIR). For example, if the recursive DC-offset removal filter of Section 4.3.1 is used in the archi-tecture shown in Figure 3.4, Equations (3.17) to (3.20) suggest IIR decision feedback for optimal compensation. In practice, however, IIR adaptive filters are usually avoided as they can become unstable if certain precautions are not taken. Also, the update algorithm for adaptive IIR filters is more computationally costly than L M S . For the same reason, in ' 3The constant /i is a step-size, which controls the amount of gradient information used to update each coefficient. Also, it directly affects how quickly the adaptive filter will converge toward the unknown system. Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 85 this work, we adhere to finite-length impulse response (FIR) adaptive filters for decision feedback. Since the impulse response of a stable IIR filter decays with time, it can be approximated by a sufficiently long FIR to the desired accuracy. 4.3.7 Simultaneous compensat ion for ISI and non-ideal i ty parameters To demonstrate good performance of the proposed method in ISI cancellation, we gen-erated a 5000-symbol 16-QAM sequence, with constant parameters of 9 = 0.2rad, A 0 = -0.25rad, and e = 15%, polluted by A W G N (SNR = 15 dB) with different types of ISI listed below: (i) FIR, h[n] =S[n] - ±u[n]u[16 - n - l ] . (ii) FIR, h[n] = {1, I J , § } . (iii) IIR (the system described by Equation 4.2, a — 0.9), (iv) FIR, h[n] = {0.1106, 0.7364, 0.7369, 0.6431}(samples taken from U[0, 1]). in which 5[n] and u[n] denote discrete-time impulse and step functions. As an example, let us consider ISI type (ii) listed above. Each received symbol is a linear combination of the current and three previous transmitted symbols, each weighted by 1/3. From Equations (3.17) to (3.20), we have: Hn(z) HQI(Z) HIQ(Z) = 1 - cos9HACi{z), = sin6HAci{z), = - ( l + e)sm(0 + A4>)HACQ(Z), Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 86 HQQ(z) = l-(l + e)cos(6 + A<t>)HAcQ{z), The nature of ISI in the context of Chapter 3 can be expressed as follows: HAci(z) = HACQ(Z) = 1 + i z " 1 + X-z~2 + By substituting HACi(z) and HACQ(Z) in the equations for the optimal decision feedback for compensation of ISI and non-idealities and taking the inverse z-transform we reach the following: hu[n] = {0.0199,-0.3267,-0.3267,-0.3267}, hqi[n] = {0.01987,0.0662,0.0662,0.0662}, hiq[n] = {0.0575,0.0192,0.0192,0.0192}, KM = {-0.1486,-0.3829,-0.3829,-0.3829}. Now, let us assume that ISI is unknown and that we use the method of Section 4.3.6 for adaptive compensation by decision feedback. At the last iteration (i.e., in processing the last symbol and long after convergence) the decision feedback filters are the following: {0.0206, -0.3331, -0.3364, -0.3306}, {0.1988,0.0687,0.0761,0.0734}, {0.0583,0.0199,0.0173,0.0233}, {-0.1441, -0.3780, -0.3830, -0.3827}. hii[n\ = hqi[n] = hiq[n) = hqq[n] = Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 87 Figure 4.11: Left: 16-QAM received signal (at the output of D C removal filters in Figure 1) with ISI and receiver non-idealities. Right: The same signal after adaptive compensation of ISI and non-idealities (at the input of the threshold blocks in Figure 1; only the last 1500 symbols are mapped to ensure convergence occurred). It is observed that the adaptive algorithm successfully computes the decision feedback filters. This can be also seen in Figure 4.11, in which the signal constellation before and after adaptive compensation is shown. Convergence of the adaptive filters, however, requires a significant amount of time, as illustrated in Figure 4.12. As we can see in that figure, the C Q F B adaptive filters can compensate the non-idealities (8 = 0.2rad, A</> = —0.25rad, and e = 15%) in the presense of IS type (ii) completely after 500 symbol. The performance of the proposed method is tested with the four types of ISI listed earlier (Figure 4.13). Assuming that the channel does not introduce any ISI or it is already equalized, and the system function of the channel is equivalent to pure delay, ISI types (i) and (iii) are likely to happen, as the effect of DC-offset removal filters. In fact, ISI type (i) is the impulse response of a 16-point moving average D C removal filter, and ISI type Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 8 8 3d 23 2d 151 o CO to 2 10| CD 4— o Converged- no error after that SNR=15dB 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 symbol count Figure 4.12: Convergence of adaptive compensation of ISI and non-idealities:. because of high SNR (15 dB) no error occurred after convergence (after about 600 symbols). (iii) is the system function of recursive DC-removal discussed in Section 4.3.1. In the case of. IIR ISI, the ideal decision feedback filters are IIR as well. Nevertheless, it is observed that 4-point FIR filters can effectively approximate the ideal IIR decision feedback filters. In the case of FIR ISI (types i , i i and iv), the adaptive filters of the same order (i.e., 16, 4 and 4) are used. It is also observed that when the ISI is significant, as in type (iv) where the effect of the three past symbols is much stronger than the current symbol, the algorithm does not converge, at least within the period of the 5000 symbols simulated. Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 89 4 C 10 : T 1 1 1 1 " 1 1 1 1 ; 3 10 § • # t (i) (ii) (iii) 4-point (iii) 2-point • 2 10 * * t (iv) — * « • • • 10 , r : 1 0 J L _ L J i i i i 1 1 1 1 1 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 symbol count Figure 4.13: Cumulative sum of reception errors for various types of ISIs. For ISI type (iv) the method does not converge within 5000 symbols. 4.4 Summary In this chapter, the idea of CQFB is implemented using DSP techniques. The adaptive system to compensate for carrier phase error and I/Q gain and phase mismatch, as well as ISI is implemented. As the results demonstrated, CQBF is a very effective approach to minimize the front-end non-idealities impacts, so it also relaxes some of the receivers front-end specification. To illustrate that CQFB is general and can be used in many applications, CQFB is ap-Chapter 4. Adaptive Digital Signal Processing Techniques for CQFB 9 0 p l i e d t o a n o r t h o g o n a l f requency d i v i s i o n m u l t i p l e x i n g ( O F D M ) s y s t e m . O F D M has b e e n successful i n n u m e r o u s wireless a p p l i c a t i o n s i n w h i c h s u p e r i o r p e r f o r m a n c e i n m u l t i p a t h e n v i r o n m e n t s is desirable . B e c a u s e of i ts p o p u l a r i t y a n d p e r f o r m a n c e , we i n v e s t i g a t e d t h e effect of C Q F B o n O F D M systems i n A p p e n d i x A . G o o d p e r f o r m a n c e of t h e s y s t e m is d e m o n s t r a t e d b y s i m u l a t i o n s , the results of w h i c h are r e p o r t e d i n t h e a p p e n d i x . Chapter. 5. Mismatch-Controllable RF Front-end Test Platform 91 Chapter 5 Mismatch-Controllable RF Front-end Test Platform 5.1 Introduction and Motivation In this chapter, the design and implementation of a prototype integrated receiver front-end are described. The prototype is intended to assist in validation of a DSP C Q F B scheme for compensation of non-idealities. The developed front-end provides user control of I /Q mismatch and includes a low-noise amplifier (LNA), two mixers and a voltage-controlled oscillator (VCO). It can be used as test vehicle for evaluation of various I /Q mismatch compensation methods implemented in the back-end. The prototype was fabricated using T S M C 0.18^m CMOS technology. The idea of having an R F front-end with externally adjustable I /Q mismatch parame-ter is attractive. The controllable front-end not only can be used as test bench for different DSP-based I/Q mismatch cancellation techniques, but it also enables the user to man-ually compensate I/Q mismatch gain completely. Therefore, it is possible to determine how effective the DSP processor is at mitigating the effects of I /Q mismatch. Figure 5.1 shows a complete digital wireless receiver, from antenna (input) to detected Chapter 5. Mismatch-Controllable RF Front-end Test Platform 92 Mixer's gain control Figure 5.1: Controllable R F front-end with the DSP C Q F B . symbol (output), using the DSP C Q F B technique. Although control of the I /Q mismatch for the R F front-end is desirable for system test, the implementation should be close to a real DCR. In Figure 5.1, the dotted box showing DSP C Q F B was described in previous chapter while the solid box, which is the R F front-end chip, is described in this chapter. In general, all analog components of the I and Q branches, such as mixers, filters, and A / D converters, contribute to the receiver imbalance properties [22]. However, the combined effect of these imbalances is such that the image attenuation produced by the down-converting is finite, causing the image signal to alias on top of the desired signal. As a consequence, the whole imbalance between the I and Q branches is usually modeled at the quadrature mixer as an imbalanced LO signal (Chapter 2). Since the mixer structure is simpler and more stable compared to a V C O , introducing mismatch is more feasible at Chapter 5. Mismatch-Controllable RF Front-end Test Platform 93 the mixer. Another important factor is that the mixer is in every R F front-end structure while VCOs can be external. This R F front-end is intended for the ISM band at 2.4GHz. The block diagram of the implemented design is shown in Figure 5.2. > > IF In IF Ip IF Qn IFQp Figure 5.2: The block diagram of the implemented R F front-end To create an amplitude mismatch between I and Q channels, I and Q mixer gain is con-trolled externally. This is implemented using a modified single-balanced mixer with con-trollable shunt current to provide a variable-conversion gain, as described in Section 5.4. In' our prototype front-end, the gains of I and Q mixers are externally controlled by shunt current Ibcl and hcQ, as shown in Figure 5.1. Since we intend to investigate the common Chapter 5. Mismatch-Controllable RF Front-end Test Platform 94 D C R output, a switch is placed to have the option of fixed (equivalent) mixers. Using a switch, the user controls the Ibc I and Ibc Q which can adjust the I and Q mixer gains, respectively. If a regular (non-adjustable) front-end is desired, the switch is turned off and the I and Q mixers gains are fixed. The details of switch and shunt current operation and the key contribution of this chapter are described in Section 5.4. As the proposed R F front-end can introduce mismatch, it can be used as a test vehicle to validate C Q F B implementation at the back-end. Also, it can be used as test vehicle for other I/Q compensation techniques implemented in DSP. In addition, such gain adjust-ment improves the I/Q amplitude imbalance, which results in dramatic increase in image rejection ratio (IRR). As a result the DSP techniques to compensate for the residual I /Q imbalance can be more successful. If we assume that we can get the estimation of gain mismatch (e), then we can manually adjust I and Q gains using the proposed R F front-end, so there will be no more gain mismatch. Therefore, IRR of the receiver would improve. In Figure 5.3, the amount of IRR ( improvement versus I/Q gain mismatch (e) is shown, for different phase mismatch (A</>) values, based on assuming completely compensating I /Q gain mismatch using controllable-gain I and Q mixers. For example, in the case of e = 12% and A<f> = 3°, using the proposed R F front-end can improve IRR by 7.5dB, shown by ' X ' on the Figure 5.3. From this figure, it is observed that IRR can be improved by up to 20 dB. A high IRR can relax some of the design constraints of the R F front-end blocks. In the next section, the overall R F front-end specifications and design process are given. Later, the blocks of the R F front-end are explained in more detail. Chapter 5. Mismatch-Controllable RF Front-end Test Platform 95 i i i i i 1 r Gain Mismatch (e) Figure 5.3: IRR improvement by adjusting the gain mismatch. 5.2 Receiver Specifications As mentioned before, the block design of a direct conversion receiver is very crucial in the overall receiver performance. A poor system design can place difficult design constraints on the underlying blocks, thus making the block specifications impossible to achieve. That is why a proper allocation of performance specifications to each block facilitates design success and speeds up the design cycle. To start the design, it is necessary to either assume or derive a set of overall receiver specifications. Some of the key criteria for receivers include sensitivity, dynamic range, out-of-band suppression, SNR, bandwidth (BW), and BER. Most of these performance criteria are very specific to the system being designed and are not set by the standards committees. However, the overall system generally has to stay within a set of limitations Chapter 5. Mismatch-Controllable RF Front-end Test Platform 96 such as maximum radiated power, out-of-band radiation, and total bandwidth that are set in well-defined standards. Other performance criteria can be derived from these well-defined criteria as it applies to a specific system. 5.2.1 Receiver Sys tem Specifications The key system specifications for the R F front-end building blocks can be broadly catego-rized in terms of conversion gain (or loss), linearity, and noise figure. These specifications can be further fine-tuned into a set of specifications consisting of (a) conversion gain (or loss), (b) overall noise figure (NF), (c) input PldB, (d) IIP3, (e) IIP2, and (f) I /Q im-balance, as appropriate. Also, the interfacing impedances play a role in an integrated environment. Noise Figure The noise figure referred to the antenna is calculated as follows [19]: where So denotes the minimum signal level; BW denotes the noise bandwidth (22 MHz); and SNR is the signal-to-noise ratio given by: NF = S0- SNR + llMBm/Hz - 101og 1 0 (£W) (5.1) SNR = Wlog10(Eb/N0) + 10log10(Es/Eb) (5.2) Chapter 5. Mismatch-Controllable RF Front-end Test Platform 97 Table 5.1: SNR and N F requirement for various modulation schemes in I E E E 802.11a/g Ra te M o d u l a t i o n C o d i n g So Es/Eb Eb/N0 S N R N F (Mbps) rate (dBm) (symbols/bit) (dB) (dB) (dB) 6 B P S K 1/2 -88 .1/2 7 4 9 9 B P S K • 3/4 -87 3/4 6.25 5 9 12 Q P S K 1/2 -85 1 6.5 •6.5 9.5 18 QPSK 3/4 -83 3/2 6.74 8.5 7.5 24 16-QAM 1/2 -80 2 8 11 10 36 16-QAM 3/4 -76 3 9.73 14.5 10.5 48 64-QAM 2/3 -72 4 12.97 19 10 54 64-QAM 3/4 -71 9/2 13.46 20 10 where Eb and Es are the average energy per bit and symbol, respectively. Equation (5.2) can be written as: SNR = Eb/N0+lO\ogw{{log2M)*R} (5.3) dB where R denotes the coding rate (1/2, 2/3, 3/4) and M denotes the constellation density (2, 4, 16, or 64). Table 5.1 lists the SNR and N F requirements for various modulation schemes. In the Table 5.1, So is set to 8 dB more stringent than specified to consider implementation losses. Eb/N0 requirements for 10% B E R are used for coherent demodu-lation. As we can see from the Table 5.1, the N F requirement for different modualtion scheme is very close. So, the system target noise figure is set to 10 dB with 5 dB of implementation margin. I /Q imbalance is targeted for 0.4 dB in amplitude and 3.7° in phase. Input PldB has been set to -16 dBm. The overall front-end gain can be set to 20 dB as a compromise between the overall system noise figure and linearity. The R F front-end is a critical building block in the receiver that greatly affects the sensitivity and linearity of the system. The one described here consists of a L N A , two Chapter 5. Mismatch-Controllable RF Front-end Test Platform 98 down-conversion mixers and a quadrature V C O (QVCO). A l l the circuits have been de-veloped with a 0.18//m CMOS process. In the next sections, the circuit design steps are described. 5.3 Low Noise Amplifier A L N A serves as the first amplification block in an R F receiver. Since typical incoming R F signals are relatively small, which leads to a small SNR, any additional noise will further degrade the overall SNR and therefore the receiver performance. Because the L N A is the first gain stage along the receiver chain, its noise and gain play the dominant role in the amount of total noise in a multiple stage circuit. The total noise figure of cascode stages is given by: _ NF2-1 NF3-1 NFn-l . A. NF = NF1 + —1 + — L . - + ...+ " (5.4) L r i t j l ( j T 2 L r i • • • ( j r n _ i where NF\, noise figure of the first stage, sets the lower boundary of NF. NF can be efficiently reduced by minimizing NFi and maximizing G\. For a receiver, NF\ and G\ are the noise figure and the gain of the L N A , respectively. The noise figure of the L N A has to be low enough, as the name suggests, to keep the overall system N F low, and the gain of the L N A needs to be high enough to reduce the noise contribution from the mixer and next stages, but not too high to degrade the overall system linearity. • In addition, because of the R F filters (typically required to be matched to 50fi) in Chapter 5. Mismatch-Controllable RF Front-end Test Platform 99 front of the L N A , impedance matching is part of LNA's specifications. In summary, the key features of a L N A are: low noise figure, sufficient gain, and good linearity. There are two topologies commonly used to design an L N A in R F MOS circuits: common-gate and cascode. While the common-gate topology provides a wide-band input matching and is less sensitive to parasitics, it has an inherently high noise figure. The cascode topology has the inherent advantage of separating the output and input optimization criteria. Input and output matching are also independent. Also, the reverse isolation is higher as compared to the other topologies. Cascode topology is better-suited to our design needs and is used here. Figure 5 .4 shows the circuit schematic of the cascode L N A under consideration. It is a single-stage inductive source-degenerated architecture. Transistor M l in a common-source configuration is the amplifying stage, while M 2 in a common-gate configuration is RFin Figure 5.4: Low Noise Amplifier (LNA). Chapter 5. Mismatch-Controllable RF Front-end Test Platform 100 the cascode stage. Cascoding transistor M 2 is used to reduce the interaction of the tuned output with the tuned input and also to reduce the effect of M i ' s Cgd. The total node capacitance at the drain of M 2 resonates with inductance Lmt both to increase gain at the center frequency and simultaneously provide an additional level of highly-desirable bandpass filtering. Inductor, Ls, in the source implemented by using the bond wires, provides degeneration to create a positive component for its input impedance. Another inductor, Lg, is the gate inductance to help with input impedance matching. Lout and Cout create an output tank circuit to help with output impedance matching. M3 is a current mirror with M l , which provides the bias voltage for the input port together with resistor R and hies-To complete the biasing, D C blocking capacitor C\ must be present to prevent any effects on the bias of M\. The value of C\ is chosen to have a negligible impedance at the signal frequency. To keep the design cost low, it is important not to use components with very large area. In this design, the largest size metal-insulator-metal (MIM) capacitor we used has a capacitance of 951.6/F (size of 30^ x x 30/i). The Lout is an on-chip spiral inductor (5.6 nH) and is implemented using an octagon shape spiral on metal 6 layer. The inductor is described in more detail in Appendix B . The L N A performance is optimized to have a high gain and low noise figure for the 2.4 GHz ISM band. The input impedance of the common source stage can be expressed as: Zin = Rt + R9 + (^)LS + s(Ls + L p ) + J L (5.5) As observed in the equation above, Lg and Ls are used to cancel out the effect of the Chapter 5. Mismatch-Controllable RF Front-end Test Platform 101 Lext Cext=±= Matching Network Ibias 1 M 3 J C3 4= Bondwire -j h -C 1 Lout R Cout C 2 Out Bondwire Figure 5.5: Low Noise Amplifier with external matching network (LNA). capacitors. The required input impedance is 50Q, at the central frequency 2.44GHz. The imaginary part of Zin should be zero at the central frequency. To avoid the large on-chip inductor required, it is common practice to use the inductance of the bond wires. However, because of their small inductance and inaccurate model, external impedance matching circuit on the board is also required to achieve 50Q impedance (Lext and Cext in Figure 5.5). 5.3.1 S imula t ion Resul ts To provide a close to real situation, the simulation was performed on the post-layout extraction, while assuming that the external input matching was ideal. The gain vs. frequency of the L N A is plotted in Figure 5.6. The L N A has a voltage gain of more than 28dB and a bandwidth of 100MHz. Chapter 5. Mismatch-Controllable RF Front-end Test Platform 102 User: zahra Date: Apr 30, 2007 Time: 10:35:55 AM PDT Y O - wave_15() 2*H 2CH - - - - - -. _ ,2 ^.444GHz, 28.66dB .387GHz, 25.57dBs^2.522GHz. 25 53d B - - -J--- - — - — - - • • - • - - / ^ - - - - - - -- - -- - / -- - ~ - — - — — - - - - -2.0 2.2 2.4 2.6 2.80 3.0 freq (GHz) Figure 5.6: L N A simulation: Gain. As mentioned before, it is very important to keep the noise figure of the L N A very small and the gain very high. By changing the inductor and capacitor values and the biasing, the L N A is optimized in a way that, in the frequency of interest, the gain would be at its maximum value while the noise figure is at its minimum value. The approach in [15] is used to achieve the minimum N F for CMOS L N A . As it is shown in Figure 5.7, the L N A noise figure is l d B around a frequency of 2.44 GHz. S\\ is an important parameter for input matching. The 5*11 of the L N A , including an external matching circuit, is -15dB at 2.44GHz, as shown in Figure 5.8. In the our design, a 5.6nH for Lout is used. L N A performance parameters are given in Table 5.2. Chapter 5. Mismatch-Controllable RF Front-end Test Platform 103 User: zahra Date: Apr 30, 2007 Time: 10:22:44 AM PDT Noise Response noise figure 3.0, 1 1 ,.0J 1 1 1-2.25 2.5 2.75 freq (GHz) Figure 5.7: L N A simulation: Noise Figure. 5.4 Down-Conversion Mixer The mixer is one of the most critical building blocks in modern R F wireless communi-cation systems. As a part of R F front-end circuits, its performance directly impacts the performance of the whole system. This block was chosen to implement the controllable mismatch feature. A single-balanced active mixer is presented in this dissertation, and is implemented in a 6-metal-l-poly 0.18/xm R F CMOS process. A simplified schematic of a single-balanced active mixer is shown in Figure 5.9. It consists of a driving stage, i.e., an input transconductance device (Ml ) , and a switching stage (symmetric switched differential pairs M2 and M3), and loads (RL)- The conversion gain of the mixer is determined by the product of the transconductance of M l and load Chapter 5. Mismatch-Controllable RF Front-end Test Platform 104 User: zahra Dale: Jan 31, 2007 Time: 5:39:43 PM PST S-Parameter Response - S 1 1 (1B20 2.5 resistors [15]: .".'r.'.Tj.Tr.j. : \ ' t / r r z i ; z u " ^ p ; " " 1 1 I 1 " 1 " " r "I' t ; j—-^rt".^T777j. j . . ; . . mm _ • ~ • • •- — r — i i i : i : 1 : i > . ! • • i ^ ^ ^ ^ ^ P -•! : 7 t : : : t : : : : r ~ T - T t : : : h : 1 : H - : : : •-t--- i --- J .;--- |---t~-; -|—-j— r - 1 . - . r - r - r -k ~ | - ~ ; — j — + ; : i . J . . . . . . 4 i : | '.]:;:.:;-:;..: . . . : . . ! . j . 1 I : : : ; : I —=—<—i—i— • ; J j _ i i ! i-;;j;-;t";f—-4 ; — i — z;j.T~:r:Trj:::: 1 j -r f . , ; :;:;r;r;;p:X::„ .. . : 1 ~~-r '--Z'-\-'T--- f — T"" 1 : : H : ± : . t ~ i - : : 2.0 2.5 freq (GHz) Figure 5.8: L N A simulation: S l l . AV — —QTURL 7T (5.6) in which gm is the M i transconductance and RL is the load resistor. If the gm can be controlled, then a variable gain can be achieved. As the second set of blocks in a direct down-conversion receiver, it is desirable that the mixers have high conversion gains and low noise figures. To increase the gain, one can increase the transconductance of M l . The transconductance of M l is given by the following equation: 9m— — 77 — l ° - ' J dVGS V g s - V T Chapter 5. Mismatch-Controllable RF Front-end Test Platform 105 Table 5.2: L N A Performance Summary. Process 0.187* Supply voltage(V) 1.8 Operation freq.(GHz) 2.44 Power dissipation (mW) 5.89 Voltage gain(dB) 28.6 Noise figure(dB) 1.07 ' B W (-3dB) 130MHz Sn(dB) -12 P l d B ( d B m ) -8 Out-LO M2 RF O Out+ M3 "~ ] |—LO-P C M1 Figure 5.9: Single-balanced down conversion mixer Where Vgs is the gate-source voltage of M i , Vr is the M l threshold voltage and ID is the D C drain current. The proposed method increases the gain of the mixer circuit by providing a shunt current, Ishunt, into the drain of transistor M i . A active mixer topology, based on the single-balanced design, was used for our application. The proposed mixer's gain is adjusted by using a current shunt circuit to modify the transconductance, as shown in Figure 5.10. The mixer includes a gain stage comprised of a pair of NMOS transistors, M2 and M3, coupled to the supply voltage Vdd through a pair of load resistors. It also includes a bias Chapter 5. Mismatch-Controllable RF Front-end Test Platform 106 circuit comprised of NMOS transistor M7 having a gate coupled to a coupling capacitor C3. The mixer gain can be increased by increasing Imix. This allows the differential input stage to operate at lower D C currents, which will result in less noise, and also allows for a larger output swing across the load resistors. Shunt ~~I  1 pC3 = m m m m « From Bias Circuitry From I/O pin Figure 5.10: The implemented down conversion mixer. The generator of the shunt current, I shunt, is comprised of transistors M4 and M5. This mixer is designed in a way that Ishunt can be controllable. The shunt current can come from the bias circuit that is on-chip (IShUnt would be fixed), or from an I/O pin externally (Ishunt would be controllable). By setting Vswitch, one has the choice to select the Ishunt set externally or internally. If Vswitch is Vdd then the Ibc pin can be disconnected and the IShunt is fixed current provided by bias circuitry. But if we connect the Vswitch Chapter 5. Mismatch-Controllable RF Front-end Test Platform 107 to ground then hc can be applied externally, and we have full control on IShunt- This is only added for validation of the approach, but would be removed when the method has been demonstrated to work properly. In that case, VswitCh alone would control the shunt current. There are several advantages to this structure: first, by using the shunt current, the conversion gain of the mixer can be increased dramatically. Second, by putting a switch we have the option of controlling the shunt current, which means we have control over conversion gain of the mixer. Note that this applies to both I and Q mixers. Since we use quadrature down-conversion, we have two identical mixers for I and Q path. This structure not only can increase/control their gains, it can also reduce the I /Q mismatch by controlling the mixers on I and Q path. The R F signal reaches the mixer input at the gate of M i . The signal is A C coupled through coupling capacitor CI and applied to the gate of transistor M i . The R F signal is amplified and generates a modulated bias current Imix. The D C bias current component of f-mix consists of current components through differential transistors M 2 and M 3 , and shunt circuit I shunt- The gate of M2 and M3 are biased by two anti-phase sinusoidal signals of period T (= l/fLo), i.e., VLO+ =VG + ALO smojLOt and VL-Q = VG- ALO smuLOt, where Vc is the common voltage and ALo is the amplitude. These LO signals are generated by a local quadrature oscillator that is placed on the same integrated circuit as the mixer circuit. The output of the mixer circuit is taken at nodes out+ and out—, after a low-pass R C filter at the output that filters out the high frequency components. Considering noise due to the switches, the loads and the transconductance stage, the Chapter 5. Mismatch-Controllable RF Front-end Test Platform 108 total white noise at the mixer output is [56]: V02n = 8kTRL + 8kTj R\l (5.8) nALO 2 where the first term is due to the two load resistors, the second term is due to the two switches (in which I = Imix — I shunt and 7 is the channel noise factor), and the third term shows the noise of the transconductance stage transferred to the mixer output. As observed in the design, I is fixed while Ishunt and Imix can increase. Therefore, the conversion gain can increase while the noise of the switch stage does not change. The results of transient analysis of the mixer is shown in Figure 5.11. As shown in the figure, the conversion gain of the mixer is around 22 dB when the switch is on and Ishunt is fixed ( 1.3mA, and Ibc is lOOpA from inside the chip). If Vswitch is G N D and Ibc — 0 then the mixer does not have any gain (-2.5 dB; the minimum value of Ibc such that the mixer works properly is 20pA). Conversion gains for some Ibc values are listed in Table 5.3. Each of the two mixers can be controlled separately to provide the desired level of mismatch. For example, the I mixer with Ibc = 20pA has a gain of 7.0dB while the Q mixer with Ibc = 60pA has a gain of 19.2dB. The gain mismatch for this case is 12.2dB. A summary of mixer's characteristics is given in Table 5.4. Note that the values for HPS and PldB are measured at the highest gain. Chapter 5. Mismatch-Controllable RF Front-end Test Platform 109 Ibc (pA) Conversion Gain (dB) 20 7.0 30 11.5 40 13.3 50 15.6 60 19.2 70 21.4 80 21.9 100 22.0 Table 5.3: Mixer's conversion gain for different Ibc Table 5.4: Mixer Performance Summary. Process 0.18p Supply voltage(V) 1.8 IF 5MHz Power dissipation(mW) 3.42 Voltage Conversion Gain(dB) 21.6 Noise figure (dB) 6.89 I I P 3 (dBm) -5.68 P l d B ( d B m ) -15.35 5.5 Voltage-Controlled Oscillator Voltage-controlled oscillators with quadrature outputs (referred to as quadrature voltage-controlled oscillators, QVCOs) are the key building blocks in many wireless and wired communication systems [10, 57]. The conventional method for generating I/Q signals is to use a non-quadrature V C O and feed it to a polyphase filter. Another technique is the design of a V C O with double the frequency and a divider for generating quadrature signals. Both of above-mentioned methods are power hungry. Using cross-coupled VCO's for generating I/Q signals not only consumes less power but it also achieves better phase noise performance. In this section, the design of a low phase noise, quadrature CMOS V C O is discussed. A two-stage differential ring oscillator can be employed to generate quadrature phases Chapter 5. Mismatch-Controllable RF Front-end Test Platform 110 in a straightforward way, but its notorious poor spectral purity (for a given power budget) disqualifies this choice for most applications. A more attractive approach for quadrature signal synthesis relies on the possibility of coupling two identical LC-tank oscillators to each other, taking advantage of the superior phase noise performances achievable with the L C tanks [58]. For this purpose, several methods are available in the literature. The best known implementation of the idea is the parallel-coupling quadrature oscillator [59]. Figure 5.12 shows a very well-known implementation of a CMOS Q V C O (symmetrical components have been named only once for better readability). Two identical oscillators, I and Q, are connected to each other by means of two additional differential pairs. Di -rect connection from Q to I and cross-connection of I to Q ensures a quadrature relation between the phases of the output waveforms. Also, the common source nodes of the differ-ential pairs driving the I-tank and the Q-tank are connected together. As a consequence, both oscillators are tied together and biased with the same current. In the following, we derive the oscillation frequency and signal amplitude for this circuit. Assuming full current switching and negligible parasitic capacitances, the resonator currents are pulses of a quarter-period duration, aligned with the corresponding driving voltages. Figure 5.13 depicts the resonator currents for the left oscillator. By Fourier analysis, the amplitude of the fundamental component is [58]: / = —1B (5.9) On the other hand, we assume that the selectivity of the tank is high enough that the differential output voltages Vj and VQ can be considered sinusoidal with very good ap-Chapter 5. Mismatch-Controllable RF Front-end Test Platform 111 proximation, and expressed as: V,(t) = Vj cos (uosct) (5.10) VQ(t) = VQ cos (uosct + 0) (5.11) where OJOSC is the oscillation frequency and 0 is the phase difference between the two waveforms. Figure 5.13 depicts this situation for the left oscillator. The load seen by each oscillator is an equivalent parallel R L C resonator with admittance: AM = J j + £ ( - - - ) = G + 3Y{u) (5.12) where u>0 = 1/\fhC is the resonance frequency of the unloaded resonator, R is the tank impedance at resonance, and Q is the quality factor of the tank at resonance. From Figure 5.13, it is clear that the current flowing in each resonator is made up of two components, each in phase with the voltage driving the respective differential pair. This composite current, on the other hand, generates a tank voltage that is in phase with the fundamental component of the current in the cross-coupled differential pair. In exponential notation, the behavior of the quadrature oscillator is described by the following system of equations: V l = (5-13) Chapter 5. Mismatch-Controllable RF Front-end Test Platform 112 From the above equations, the amplitudes of the output waveforms are: and the oscillation frequency is given by: U™ = Uof + 4 & 2 Q * i W 0 2 Q ( 5 - 1 6 ) The phase noise performance of an oscillator at an offset frequency A C J , from the center frequency UJ0, is given by [60]: r / A , ( 2 F ( A u ; ) K T L(Au>) = 10 log | K p ' sig 1 + ( J _ ^ ) 2 K2QAOJ' where F is an excess noise factor, and can be calculated by [61] F(Au) = 1 + - ^ - f - + 7 n t o M 3 J R p (5.18) tanfc resistance noise s v / v v ' M l and M 2 noise M 3 « o i s e and P s i g is the output power of the oscillator, Q is the quality factor of the tank, and Au is the corner frequency between the 1/f2 and 1/f3 regions. Thus, the oscillator phase noise can be improved by increasing Psig and Q. Also, to achieve the minimum phase noise, one has to minimize F(Au) [61]. Chapter 5. Mismatch-Controllable RF Front-end Test Platform 113 5.6 Simulation results The inductors and varactors used in our design are specified in Appendix B. The first step in V C O design is choosing the bias current. As the bias current, IB, is increased, based on Equation 5.15, the V C O swing is also increased. Figure 5.14 shows the variation of amplitude and frequency of the V C O versus varactor voltage control. Chapterd. Mismatch-Controllable RF Front-end Test Platform 114 Usenzahra Date: Dec21, 2006 Time:4:58:31 PM PST - VT(7ne131-) 750n -Transient Response - v (/LOQn /LOQp); tran (V)(1) - v (/LOQn /LOQp); tran (V)(2) £ 04 -750-. 995.0 996.0 User: zahra Date: Dec 21, 2006 Time: 5:24:26 PM PST 997.0 time (ns) Transient Response Figure 5.11: Result of transient analysis of the mixer. Chapter 5. Mismatch-Controllable RF Front-end Test Platform 115 Figure 5.12: Circuit schematic of Q V C O . i V I P V Q P V , N V Q N Figure 5.13: Output voltages and resonator currents when the output waveforms are per-fectly balanced. Chapter 5. Mismatch-Controllable RF Front-end Test Platform 116 V C O c h a r a c t r i s t i c 0 . 7 I 1 1 1 1 1 1 1 r O 0 .2 0 . 4 0 . 6 0 . 8 1 1.2 1.4 1.6 1.8 v a r a c t o r c o n t r o l v o l t a g e • 0 . 2 0 . 4 0 . 6 0 . 8 1 1.2 1.4 1.6 1.8 v a r a c t o r c o n t r o l v o l t a g e Figure 5.14: VCO's amplitude and frequency versus Vctr l (varactor voltage control) Chapter 5. Mismatch-Controllable RF Front-end Test Platform 117 A good choice for V C O voltage control is 1.45V which is in the middle of 1. I V and 1.8V. The phase noise is highly-degraded when the control voltage is between 0.8V to 1.1V where the oscillating amplitude has some variations. The simulation performance of the Q V C O is summarized in Table 5.5 for the typical-typical (TT) process corner. It is observed that in the fast-fast (FF) mode, the value T T (Temp = 27°) Vctrl Freq. (GHz) Amp. (mV) Phase Noise (dBc/Hz) 0 2.097 352 -116 1.8 2.768 663 -95.2 1.3 2.451 505 -85.2 SS (Temp = = 120°) Vctrl Freq. (GHz) Amp. (mV) Phase Noise (dBc/Hz) 0 1.991 100 -106.5 1.8 2.652 440 -96.4 1.3 2.368 305 -85.2 F F (Temp = = -40°) Vctr l Freq. (GHz) Amp. (mV) Phase Noise (dBc/Hz) 0 2.185 530 -110.2 1.8 2.851 795 -93 1.3 2.476 640 -86.1 Table 5.5: VCO's characteristics of L and C is decreased and the oscillating frequency is increased. But in the slow-slow (SS) mode, the Q and R of the inductor are degraded which leads to lower swing in the ..VCO's output. The worst condition for the circuit is the SS corner case when Vctrl=0. The QVCO's output (for T T process corner, Temp=27°C) is shown in Figure 5.15 (just three out of four signals are shown). The Q V C O has four outputs with 90° phase difference as LO/+, I/O/-, LOQ+, and LOQ-. . Figure 5.16 shows the VCO's phase noise for different control voltages. The design represented in Figure 5.2 was implemented in a T S M C 0.18/xm C M O S Chapter 5. Mismatch-Controllable RF Front-end Test Platform 118 »: V T f y O n " ) - : VT("/lp") 1.4 .'• VT("/ln") time ( s ) Figure 5.15: VCO's Output process. A picture of the fabricated chip is shown in Figure 5.17. Because of the number of I/Os, the 44CQFP package was used. The design has 27 pads, as shown in Figure 5.17, of which 23 are I/Os. The testing procedure for this chip is outlined in Appendix C. The measurements are not reported here since the part was not fully functional. The main test was to apply a 2.4GHz signal at the input and observe the corresponding outputs. We expected to see 40dB gain for the whole R F front-end with down conversion, but we saw very small gain (around 8dB). Further probing of each block (LNA, Mixers, QVCO) required a new board, which is still under construction. While full chip testing is not completed, the basic approach has been demonstrated using simulation in this chapter. Chapter 5. Mismatch-Controllable RF Front-end Test Platform 119 O . V C O T O P . V C C B e h . A 3 . V 2 s c h e m a t i c : Mor 13 13:'2:33 2 0 0 5 Periodic Noise Response . : V ' c t r l = " J , 8 " ; P h a »: Vctrl«"t .6";Pho •,: Vctrl»"1.4";Pha k - 3 0 0 c : Vc t r l» "800m" ;Phw: Vctn = " 6 0 0 m " ; P h » : Vctrl = M 4 0 0 m " ; P h --120 VctrU V e t c h "1,2";Pha < "200m";Ph< V c t r l -V c t r h "1";Phos* "0";Phase Figure 5.16: V C O phase noise for different varactor control voltages. 5.7 Summary In this chapter, the RF-front end design was described and the simulation results of the extracted layouts of all blocks were reported. Also, the novel mixer design which has a controllable gain was introduced: we showed that with changes of Ibc, the gains of mixers for I and Q can be controlled separately. Since all mismatches of all blocks and components can be modeled as I/Q mismatch at the mixer, separate gain control of I and Q mixer can minimize the effect of I/Q gain mismatch. At the beginning of this chapter, it was shown that with minimizing I/Q gain mismatch, e, the IRR of the R F front-end can improved by up to 20dB, which means that with this technique one of the important requirements of the R F front-end can be relaxed. The completion of the work will require a new board and another sequence of testing Chapter 5. Mismatch-Controllable RF Front-end Test Platform 120 Figure 5.17: Die photograph of the R F front-end. to determine the problem with this initial design. The next stage is to fabricate a second chip with the overall R F front-end and DSP back-end to validate the entire approach with controllable mismatch. This will be part of the future work. However, the basic approach has been validated in simulation and is expected to be functional with another iteration through silicon and test. Chapter 6. Conclusions 121 Chapter 6 C o n c l u s i o n s 6.1 Research Summary This research introduced a new approach to mitigate the effects of certain analog im-pairments that plague the direct conversion receiver architecture. For the first time, an A C coupling plus a cross-coupled quantized feedback is applied to a D C R . By using a cross-coupled quantized feedback (CQFB) in DCR, not only are D C offset and 1/f noise removed without wander effect, but also carrier phase error and I/Q mismatch effects are reduced. The proposed approach can be applied to many application while addressing many of the D C R design issues in one solution. It can be implemented in the digital domain for many wireless applications. Motivated by a new paradigm of digital R F pro-cessing (DRP) that reduces the complexity of the receiver by maximizing the use of digital signal processing techniques, C Q F B is implemented in DSR Extensive use of digital con-trol and digital signal processing techniques will hopefully relax the requirements on R F and analog circuits. The main conclusions of this dissertation are as follows: • The Cross-coupled quantized feedback is a very effective method to address impor-tant issues of the DCR, including DC offset and low frequency disturbance, phase Chapter 6. Conclusions 122 error, and I/Q mismatch and may" have a wider range of applications than illustrated in this thesis. • The completely digital C Q F B is implemented to minimize the analog R F front-end non-idealities and to relax it requirements. Since it is better to remove the D C offset before A D C , it would be better to implement the AC-coupling filters in analog domain, and other C Q F B filters in digital, and the feedback from digital goes to analog. • The C Q F B is very effective for amplitude-based modulations, however, it is very difficult to implement frequency-based modulation schemes, e.g. G M S K , and G F S K . These contributions are described in more details in next section. 6.2 Thesis Summary In Chapter 2, various receiver architectures were investigated and their design challenges discussed. The direct conversion receiver architecture offers many advantages over the conventional heterodyne receivers including smaller size, lower cost, and reduced power consumption. However, the design of monolithic receivers using direct-conversion involves many challenges including low-frequency disturbances, namely, DC-offset and 1// noise (especially in CMOS implementations), I /Q amplitude and phase mismatch, L O leakage, and even-order distortions. The necessary background was described to help understand the nature and severity of various analog impairments. Also, the existing methods to address the D C R design challenges were reported extensively. Chapter 6. Conclusions 123 We noted that most of the existing methods work only for a specific application or focus on one or two issues. In contrast, we tried to develop a rather general solution to a number of problems with the direct conversion receivers. More specifically, in Chapter 3, a system solution was introduced that mitigates the effects of low-frequency disturbance, phase error and I/Q mismatch. The DC offset and 1/f noise are the main design issues of the DCR. A cost-effective method to minimize the low-frequency disturbances is to use AC-coupling in the baseband signal path. Such an approach, however, results in baseline wander effects as the low-frequency part of the signal is filtered out. This is more critical in spectrally efficient modulation schemes such as quadrature amplitude modulation (QAM) where the baseband signal spectrum contains a significant amount of energy near DC. Our system-level solution uses quantized feedback (QFB) in conjunction with AC-coupling to minimize the baseline wander effects. Also, cross-coupled niters are added to the quantized feedback to compensate for the receiver L O phase error and the I/Q mismatch. Theoretical analysis and simulation results, along with practical and implementation issues were reported in this chapter. In Chapter 4, a digital implementation of the C Q F B technique using adaptive fil-tering was discussed. Our simulation results indicated that the proposed compensation technique can be used to suppress non-ideality effects of receiver front-end sections un-der realistic signaling assumptions. The low-complexity DC compensation system can be used in a wide variety of applications. I /Q mismatch compensation was addressed using adaptive filtering. Our analysis showed the evolution of adaptive decorrelation from a LM S algorithm for the cases that the mismatches can be assumed constant over the Chapter 6. Conclusions 124 operating frequency band. Also, a method to estimate the non-ideality parameters was reported that is used along with the C Q F B adaptive implementation. Also in Chapter 4, the performance and convergence of the C Q F B adaptive algorithm in systems with ISI was derived. The effectiveness of the DSP implementation was validated by a number of results to demonstrate the efficiency of C Q F B system to compensate for the most im-portant D C R design issues. This was followed by an optimized implementation for the application of 16QAM signaling that is used in IEEE 802.llg W L A N standard. In addi-tion, successful application of the adaptive C Q F B algorithm to O F D M signaling, which has become particularly successful in wireless applications where superb performance in multipath environments is essential, is reported in Appendix A. In Chapter 5, design and fabrication of a mismatch-controllable R F front-end capable of introducing a desired level of I /Q gain mismatch was reported. The I/Q mismatch parameter of the circuit can be controlled externally by adjusting the shunt current, and hence gain, of I and Q mixers. Therefore, it can be used as a front-end testbench for I /Q mismatch compensation techniques implemented at the back-end. Also, with the capability of compensating I/Q mismatch gain completely, IRR can be increased by 20dB, which relaxes the requirements of R F front-end blocks. A fully-integrated 0.18^m C M O S direct-conversion receiver R F front-end for 2.4 GHz ISM band was implemented for this purpose. This design includes a low-noise amplifier (LNA), two mixers (quadrature down conversion) and a quadrature V C O . The I and Q path mixers can operate in normal mode, or they can be controlled externally to introduce a known mismatch or to compensate for the estimated mismatch. It achieves a conversion gain of 40 dB, and a noise figure of 8.1 Chapter 6. Conclusions 125 dB. The circuit dissipates 25 mW and occupies an active area of 2.5 mm2. 6.3 Future Work In the current trend of decreasing cost and increasing complexity, delivering more function-ality and flexibility is driving the future of integrated wireless devices. Today's wireless research is now focusing on design of a multi-mode, multi-band radio systems. Since C Q F B is not application-specific, it would be useful to investigate an effectiveness and limitation of the application of C Q F B in muti-mode, multi-band radio systems, in future. The methods of Chapter 4 can be implemented in DSP by automatic conversion of Matlab and Simulink codes into a target digital signal processor. The power dissipation of this approach may be high, so this aspect should be investigated further. For indus-trial implementation of the system, however, the algorithms should be studied from a hardware/software co-design perspective to determine what parts should be hardwired (i.e., the optimal hardware) and what parts should be programmable, to achieve the least-expensive implementation strategy, given the application-specific constraints such as power consumption, frequency band, bit-rate, etc. The complete design with the controllable front-end and the DSP back-end should be implemented to fully demonstrate the approach. It would be also be useful to study mismatch compensation by using the front-end adjustable I and Q gains. This way, it may be possible to compensate for all non-idealities that cause I /Q mismatch (such as slightly different characteristics of A/Ds) that are not included in our study altogether, by embedding them in the decision feedback loop. Chapter 6. Conclusions 126 Extension of the adaptive C Q F B circuit to wider bandwidth systems, where the mis-matches can have larger changes over frequency, is another good subject for further re-search. Although 1/f noise was identified to be one of the major problems in direct conver-sion receiver (DCR) architecture, this research removed 1/f noise as a side-effect of our approach but did not address any specific solution for 1 ji noise. It was mentioned in Chap-ter 2 that 1/f noise belongs to the class of impairments that can primarily be improved using only circuit techniques, for example, by using larger transistors. A n extension of C Q F B to solve this problem may be possible and should be pursued. To conclude, this research demonstrated the power of system-level reduction of the impairments of the blocks using a new C Q F B approach. Of course, the eventual objective in wireless receivers is to achieve an all digital receiver by converting the signal right at the antenna output to digital. While this may not be feasible today, D R P allows a gradual move in that direction. Appendix A. Application: OFDM signaling 127 Appendix A Application: OFDM signaling In this section, the application of the proposed DSP-based receiver architecture in orthog-onal frequency division multiplexing ( O F D M signaling) is described. Over the last 20 years, O F D M techniques and, in particular, discrete multitone (DMT) implementation, have been used in a wide variety of applications. O F D M has been par-ticularly successful in numerous wireless applications in which superior performance in multipath environments is desirable. Because of its popularity and performance, we in-vestigate the effect of C Q F B on O F D M system. To that end, a brief description of O F D M is given first. Then, an implementation of O F D M that we used in the simulations is described. Good performance of the system is demonstrated by simulations, the results of which are reported in Section 4.3.5. More details on O F D M signaling can be found in [55], although our implementation (described below) is a bit different. A . l Basics of O F D M O F D M , in conjunction with proper coding and interleaving, is a powerful technique for combating wireless channel impairments. Figure A . l shows a system block diagram for Appendix A. Application: OFDM signaling 128 OFDM. i, i 1 - «§ <p <H i S \ S I # * # * t > * » • > * * * * * l x sample 1 1 w , F F I Figure A . l : Spectral overlap of subcarriers in OFDM The frequency response of the ideal channel has a flat magnitude and pseudo-linear (i.e., linear + constant) phase. In the time domain, this translates to pure delay and frequency-constant gain. In the real world, the channels are not ideal thus introducing ISI (as well as noise) in the signal. However, if the pass-band of the channel is divided into several small bands, each of those bands can be considered a nearly ideal narrowband sub-channel: the magnitude of the frequency response is almost constant and the phase can be considered almost pseudo-linear. The basic idea of OFDM is to modulate several carriers with the center frequencies of each sub-channel at a symbol rate K times less than the single-carrier system that uses the same channel. The sub-carriers can transmit different bits/symbol (e.g., use M-QAM with various Ms). This way, for example, sub-channels with smaller attenuations (i.e., higher SNRs) can carry more of the data. The major contribution to the OFDM complexity problem was the application of the FFT algorithm to the modulation and demodulation processes. At the same time, Appendix A. Application: OFDM signaling 129 DSP techniques were being introduced in modems. The technique involved assembling the input information into blocks of N complex numbers, one for each subchannel. A n inverse F F T is performed on each block, and the resultant is transmitted serially. At the receiver, the information is recovered by performing an F F T on the received block of signal samples. This form of O F D M is referred to as discrete multitone (DMT). The spectrum of the signal on the line is identical to that of N separate Q A M signals at N frequencies separated by the signaling rate. Each such Q A M signal carries one of the original input complex numbers. The spectrum of each Q A M signal is of the form sin(kf)/f, with nulls at the center of the other sub carriers, as shown in Figure A . l . Figure A.2 shows the O F D M spectrum. Figure A.2: Spectrum of O F D M signal Care must be taken to avoid the overlap of consecutive transmitted blocks. This is solved by the use of a cyclic prefix. The process of symbol transmission is straightforward if the signal is to be further modulated by a modulator with I and Q inputs. Otherwise, it is necessary to transmit real quantities. This can be accomplished by first appending the Appendix A. Application: OFDM signaling 130 complex conjugate to the original input block. A 2N point IFFT yields 2N real numbers to be transmitted per block, which is equivalent to N complex numbers. A . 1.1 O F D M Implementa t ion In the following, we describe an implementation of O F D M signaling that is used in our simulations. The block diagram of the transmitter is given in Figure A.3. The serial-to-parallel converter divides each B bits of the input data to K groups, with the ith group having 6, bits. Using M r Q A M for sub-channel i, the multi-carrier modulator selects one of M ; = 2bi symbols, depending on the data. This way, we will have K symbols for every B bits of the system's input. Inverse D F T is then applied to the sequence of K symbols. The reason for this operation will be seen later. The real (xn\ n = 0, • • •, K — 1) part of this sequence is then prefixed by cyclic repetition to make xx-m, XK-m+i, • • •, XK-I,XQ, XI, • • •, XK-I, in which m is the length of the channel sam-pled impulse response. The imaginary part of the signal, yn, undergoes the same process. The resulted sequences are converted to analog signals and are mixed with the carrier sine and cosine carriers to make the band-pass signal to be sent over the channel. Data _ ^ (bit stream) Serial-to-parallel Multi-carrier Modulator & I D F T Re{} Im{} A d d cyclic prefix Parallel-to-serial D / A | : u o 90Y*t_J -*g)— T o the channel Figure A.3: O F D M transmission. Unlike the O F D M implementation of [55] that gives real baseband signals, we used quadrature signaling that is complex in the baseband, but gives real quadrature and Appendix A. Application: OFDM signaling 131 in-phase band-pass components. Serial-to-parallel Remove cyclic prefix i["] + M"] Multi-carrier de-modulation (DFT) ISI removal A Re{} Im{} CQFB QAM detectors Figure A.4: O F D M reception. The input to the receiver depicted in Figure A.4 is supplied by the R F front end shown in Figure 4.3. In [55], it is shown that the channel ISI corrupts the cyclic prefix (which is easily removed) and affects signal in the following manner. Xi = dXi + Noise, , i = 0,1, • • •, K - 1, in which Xi is the Q A M symbol transmitted through the i th sub-channel, {C;} is the K-point D F T of the sampled impulse response of the channel {co,Ci , • • •, c m _i}(padded by K — m zeros), and {Xi} is what we have (polluted by noise). Note that the proce-dure automatically de-correlates the received symbols, thus removing ISI. To recover the transmitted symbols, {Xi}, we can measure {C;} by passing a training sequence through the channel. Alternatively, assuming that we have a good initial guess for {Cj} and that the channel characteristics is constant through time or varies slowly, we can use L M S to adaptively find {Q} . Since ISI is automatically handled in O F D M signaling as described above, C Q F B filters are simply gains in this case. The detection equation becomes the following: Appendix A. Application: OFDM signaling 132 Re{Xi} Im{Xi} \ ( I/Q 0 V 0 I/Q j + H Qi 1 Re{Xx} ^ Im{Xi} , i = 0 , - - - , A " - l ( A . l ) in which {h+jQi} = DFTk{i[n] +jq[n]}, n = KN, KN + K-l and Qt{.) is Mr Q A M detector used for demodulation of the i th sub-channel. H is the C Q F B gain matrix that is given by Equation (4.3), if the receiver non-ideality parameters are known. Note that we assumed the same H for all sub-channels. That may not be the case as the sub-carrier frequencies are different for different sub-channels. If the receiver's characteristics significantly vary for different sub-channels, we can consider different Hs. Equation (A.l) above should be solved for every received symbol, although the D F T operation is performed once for every batch of K symbols. For an adaptive solution, we assume H and {C — i) (or an initial guess of them) are known and use the method of Sec-tion 4.3.2 to detect the symbols. Once Equation A . l is solved, it can be considered as two linear filtering equations: (a) with input Qi{(Re{X — i} , Im{Xi})T} (the decided sym-bol), output (Re{Xi}, Im{Xi})T , filter H, and ideal output Qi{(Re{X — i}, Im{Xi})T}, and (b) with input (Ii,Qi)T , output (Re{Xi}, Im{Xi})T, filter diag{(l/Ci,l/C — i)}, and ideal output Qi{(Re{X — i}, Im{Xi})T}. Using L M S , the update equations for {d} and H become the following. For z = 0, • • • ,K — 1: 1 ^ \ B i J ( Re{X{} ImiXi} \ H = H + pei(Ai B^, Appendix A. Application: OFDM signaling 133 Ci = d + p Qi) ti in which Ci = 1/Cj and (Ai BA = Qi{(Re{Xi}, Im{Xi})T} denotes the decision for the i th sub-channel. Note that Q is assumed to be real or the update equations would be a bit different. A.2 Adaptive ISI and non-ideality compensation in O F D M signaling In this section, an experiment and its results are reported that confirm good performance of the method described in Chapter 4. 6000 bits of randomly generated bits are to be transmitted by O F D M signaling through A W G N channel with SNR of 15 dB. O F D M employs two sub-channels, the first one with 4 -QAM (2 bits/symbol) and the second one with 16-QAM (i.e., carrying 4 bits/symbol) modulation. Therefore, the 6000 bits are transmitted via 2000 symbols. The effects of the channel and the DC-offset removal filter are considered as a single 5-point discrete filter, with the impulse response given below: hISi[n] = {0.82 -0 .18 -0 .18 -0 .18 -0 .18}. Note that in O F D M signaling we cannot use a DC-removal filter with zero DC gain or use a channel that has a zero gain somewhere within in the allocated signaling bandwidth. That is because the C* corresponding to the sub-carrier that falls on the zero, becomes very Appendix A. Application: OFDM signaling 134 small, making the detection equation (Equation (A.l)) ill-conditioned. In other words, if the channel (i.e., channel + DC-removal filter) has very small gain in a certain frequency (e.g., a zero gain at D C if a DC-removal filter is used), that sub-channel is not suitable for communication and the transmission will suffer from a large probability of error. In practice, the channel does not have a zero in its pass-band but the DC-offset removal filter at the receiver can make negligible, and make Co the first sub-channel unusable. To alleviate this problem, we can simply put aside the first sub-channel and use the rest of them for transmission. Alternatively, we can use a filter with non-zero (but small) D C gain for DC-offset reduction. Such a filter reduces the DC-offset that is necessary for good performance of the receiver and, at the same time, allows for using of the first sub-channel perhaps at a lower bit-rate as compared to the rest of sub-channels with higher gains and thus higher SNRs. In this experiment, we used the second approach above (the frequency response of hisi[n] is shown in Figure A.5): the DC-offset reduction filter has a small D C gain (-20dB). The receiver non-ideality parameters are considered 9 = 0.2rad, <j> = — 0/25rad, and e = 15%. The initial guesses we used for this experiment are 0 2 and 1 2 X 2 for H and {Q} , respectively. The results are shown in Figure A.6. It is observed that the receiver converges within the first 600 symbols, and because of rather high SNR, no error occurs after convergence. The application of C Q F B on the O F D M receiver has been reported, and the result is promising. Appendix A. Application: OFDM signaling 135 0.4 0.5 0.6 Normalized freq. (1 = n) 0.9 1 Figure A.5: The frequency response of the DC-offset reduction filter. 200 400 600 800 1000 1200 symbol count 1400 1600 1800 2000 Figure A.6: Cumulative sum of reception errors for adaptive compensation of receiver non-idealities and ISI for O F D M signaling. Appendix B. On-chip Inductor and Varactor 136 Appendix B On-chip Inductor and Varactor B . l Spiral Inductors The equivalent circuit model of a spiral inductor (not symmetric, with two ends) is shown in Figure B . l , where L I and L2 are the series inductance and R l and R2 are the series resistance of the metal lines. C12 is the coupling capacitance between the two ports. Coxl, Cox2, and Cox3 are the oxide capacitances between the spiral and the substrate. Csubl, Csub2, and Csub3 are the capacitances of the silicon substrate, and Rsubl, Rsub2, and Rsub3 are the resistances of the silicon substrate. L s l (Ls2) and R s l (Rs2) are the inductance and resistance to model the skin effect of the metal track. The quality factor of a spiral inductor is defined as the ratio of energy stored in it over the energy lost in one oscillation cycle. Metal wire resistance, capacitive coupling to the substrate, and magnetic coupling to the substrate limit the Q-factors of on-chip spiral inductors. The Q factor of the implemented inductor used for the L N A is plotted in Figure B.2. It is observed that for the frequency of our interest, the Q of the on-chip inductor is around 9, which is very good for on-chip inductor. For the inductor used in V C O , a symmetric inductance with central tap is used. The equivalent circuit model of a symmetric spiral inductor is shown in Figure B.3, which Appendix B. On-chip Inductor and Varactor 137 Rsubl C12 •AMr R1 Ls2 Rs2 J T Y Y V L1 T Cox1 L2 R2 Cox2 - r =FCsub1 Rsub3 =FCsub3 Rsub2 : ; Csub2 Figure B . l : Inductor Model. is the same as spiral model just L I and L2 have mutual inductance M and Let are the inductances due to the central tap metal and Ret is the resistance due to the central tap metal. If the curve of the Q (Quality factor) of inductor is plotted versus frequency, it is observed that the Q is first increased by increasing frequency due to increase of X L (Inductor impedance) and then decreased because of the impedance of the inductor with parasitic capacitors is decreased. Moreover, the Q is increased by (1) Increasing f (/ < 5GHz), (2) Decreasing T (number of Turns) , and (3) Decreasing Radius, R. Note that as R and T are increased, the A L / A / is also increased which causes the inductor value to change sharply with frequency. In the selection of L and C for resonator, it is important that (1) L be large enough to provide the necessary parallel resistance at the output, and (2) the value of L should be chosen properly, in order to achieve the minimum A L / A / . Appendix B. On-chip Inductor and Varactor 138 10, Freq (GHz) Figure B.2: Super-heterodyne receiver. B.2 Var actors We used MOS Varactor. The equivalent circuit representation of the MOS varactor is shown in Figure B.6. The definitions of the parameters are: • Lgate:overall inductance of port 1 vias and gate. • Lsd: overall inductance of port 2 vias and bulk. • Rgate: resistance of the unit cell vias/contacts as port 1 and gate. • Rsd: resistance of the unit cell vias/contacts as port 2 and bulk. • Cgate: variable capacitance of the MOS varactor. Appendix B. On-chip Inductor and Varactor 139 Rsubl • BR1 LS1 C12 M Ls2 Rs2 4=Csub1 R s u b 3 ^ =r=Csub3 R s u b 2 ^ =}= Figure B.3: Symmetric inductor with tap Model. *: R="9Bu";( imo, : R - "120u" ; ( i m o : R » " 1 1 0 u " ; ( i m » : R = " 1 0 0 u " ; ( i m - : R = " 8 0 u " ; ( ; r n a . : R="70u";(]mc • : R="120u";( iwo: R « " 1 1 0 u " ; ( i m » : R « " 1 0 0 u " ; ( i m « : R="90u";(ima-: R - " 8 0 u " ; ( : m o . : R-"70u";(imo 0 0 »: R " " 1 0 0 u " ; ( i m « : R - "120u" ; ( i m o : R - " 1 1 0 u " ; ( i m * ; R - " 9 0 u " ; ( ; m o - : R « " 8 0 u " ; ( ; m a i : R="70u";(;mc * r e q ( H z ) Figure B.4: The quality factor of inductor vs. frequency for different values of R Appendix B. On-chip Inductor and Varactor 140 5.00n r i , , 0-0 1.0G 2.0G 3.0G 4.0G 5.0G freq ( Hz ) F i g u r e B .5 : T h e i n d u c t o r value vs. frequency for different values of R Cpar Lgate Rgate P M Gate o jpj^ V W L ^ P -Cgate Rsd Lsd j y \ / \ / y y y O Bulk Dnwpsub Rsub 1 =5= Csub F i g u r e B .6 : E q u i v a l e n t c i r c u i t of a M O S v a r a c t o r Appendix C. Testing of the RF Front-end Chip 141 Appendix C Testing of the RF Front-end Chip In this section, the measurement sequence for the developed receiver front-end is presented. This testing sequence is tailored to the equipment available at the SoC test Lab, and work is still in progress. For testing, we decided to design two P C B 1 boards, a high-frequency board for the chip itself, and another to generate the low-frequency signals required for biasing and control of the chip. The two boards are connected together using two wire buses. A picture of the two test boards are shown in Figure C . l . The schematics of two boards are shown Figure C.2 and C.3. • The first step was to set up the D C bias points for the circuit under test (labeled as receiver under test or R U T in the following figures), and observe the D C currents flowing through the IC. The bias current can be monitored by using an ammeter. The supply voltage in the circuit should be adjusted to the nominal value as per the simulation. If the current through the circuit is much higher than expected, there might be a short in the circuit, and the D C operating condition will not be satisfied. In this case, another IC sample should be tried. Also, if the circuit is functional, the D C test arrangement can be used for splitting up the current consumption for different receiver blocks. For example, a 1 Printed Circuit Board Appendix C. Testing of the RF Front-end Chip 142 Figure C . l : Photograph of the test boards. DC test on the entire receiver would indicate the power dissipation of the LNA, mixer, and VCO separately. With biasing, the total power consumption of this design was 2.5mW. After the DC bias points have been set up, a test was carried out to determine whether the circuit is functional. For the RF front-end, it must down-convert the incoming RF signal to a desired IF frequency. The bias values can be adjusted a little bit to obtain the proper functionality of the circuit. In this specific test, one RF frequency source is used at frequencies of 2.445 GHz (Signal Generator Agilent 8648D is used) and an oscilloscope is used to observe the 5MHz down-converted IF signal. This provides the indication that the circuit is functional as a down-converter. If the circuit does not pass this test, there is a chance that the VCO does not work properly. This design did not pass the functionality Appendix C. Testing of the RF Front-end Chip 143 Figure C.2: Schematic of high frequency board for testing the chip. test. However, this contingency was considered and VCO can be turned off, and the quadrature LO signal can be applied externally. Unfortunately, a new board is required for this purpose. Next, a one-port S-parameter test was performed on the receiver to observe the match-ing at the input port of the circuit, shown in Figure C.4(a). The calibration for this mea-surement is performed off-chip. This test should be performed prior to any other tests in the receiver, to verify that maximum power transfer occurs from the RF signal generator to the RUT. Only DC supplies are required for the one-port S-parameter test and vector network analyzer (VNA Agilent 8362B) to measure Sn-To measure receiver conversion gain, DC supplies and signal generator for RF input Appendix C. Testing of the RF Front-end Chip 144 Figure C.3: Schematic of bias board for testing the chip. signal are required, as in Figure C.4(b). The two differential output (IF/+ and IF/ - ) are connected to the Agilent DSO81304A Scope to measure the conversion gain. For measuring noise figure, DC supplies, a N F meter(Agilent E4440A PSA Series Spectrum Analyzer), and a balun (to obtain a single-ended signal from the differential IF output) are required, as in Figure C.5(a). For I /Q imbalance and DC-offset test, DC supplies and signal generator for R F input signal are required, as per Figure C.5(b). The four differential output (IF/+, IF / - , IFQ+, I F Q - ) are connected to the Agilent DSO81304A Scope to obtain the waveform statistics (amplitude and phase information, along with their mean and variance values). From this information, the I /Q imbalance can be extracted. It is important to use exactly identical cables in this test, as the imbalances in the cables might otherwise introduce some I / Q Appendix C. Testing of the RF Front-end Chip 145 Bias Board Vector Network Analyzer Agilent 8362B (a) Test Setup for SI 1 parameter Bias Board Signal Generator Agilent S c ° P e Agilent DS081304A 8648D (b) Test Setup for conversion gain measurement Figure C.4: Test setup for (a)Sll and (b) conversion gain measurements imbalance during the measurement. The same test setup can be also used for DC offset measurement, just two IF terminals are interfaced with the scope to measure the voltage difference. Appendix C. Testing of the RF Front-end Chip 146 Spectrum Analyzer Agilent E4440A (a) Test Setup for noise figure measurement Bias Board Signal Generator Agilent Scope Agilent DS081304A 8648D (b) Test Setup for I/Q imbalance and DC offset measurement Figure C .5: Test setup for (a)NF and (b) I /Q imbalance measurements 147 Bibliography [1] B. Razavi, "Design considerations for direct-conversion receivers," IEEE Trans, on Circuits and Systems II, vol. 44, no. 6, pp. 428-435, June 1997. [2] H. Wang, M . Lin, and H. C. Y . L i , "A novel dynamic dc-offset canceller," in Proc. of 5th International Conf. on ASIC, 2003, pp. 639-642. [3] H. Yoshida, H. Tsurumi, and Y . Suzuki, "Dc offset canceller in a direct conversion receiver for qpsk signal reception," in 9th IEEE International Symp. on Personal, Indoor and Mobile Radio Communications, 1998, pp. 1314-1318. [4] S. J. Fang, S. T. Lee, D. J. Allstor, and A . Bellaouar, "A 2 ghz C M O S E V E N HARMONIC MIXER FOR DIRECT CONVERSION RECEIVERS," IN IEEE International Symp. on Circuits and Systems, 2002, PP. 807-810. [5] K . M U H A M M A D , R . B . STASZEWSKI, AND D . LEIPOLD, "DIGITAL RF PROCESS-ING: TOWARD LOW COST RECONFIGURABLE RADIOS," IEEE Communications Mag-azine, V O L . 43, PP . 105-113, A U G . 2005. [6] P . BAUDIN AND F . B E L V E Z E , "IMPACT OF RF IMPAIRMENTS ON A DS-CDMA RECEIVER," IEEE Trans, on Communications, V O L . 52, PP. 21-36, J A N 2004. [7] S. MlRABBASI AND K . MARTIN, "CLASSICAL AND MODERN RECEIVER ARCHITEC-TURES," IEEE Communication Magazine, PP. 132-139, N o v . 2000. ' [8] A . ABIDI, "DIRECT-CONVERSION RADIO TRANSCEIVERS FOR DIGITAL COMMUNI-CATIONS," IEEE Journal of Solid-State Circuits, VOL. 30, NO. 12, PP. 1339-1410, D E C . 1995. [9] W . N A M G O O N G AND T . M E N G , "DIRECT-CONVERSION RF RECEIVER DESIGN," IEEE Trans, on Communications, V O L . 49, NO . 3, PP. 518-529, M A R C H 2001. [10] B . RAZAVI, RF Microelectronics. N J : P R E N T I C E - H A L L , 1998. [11] D . W E A V E R , " A THIRD METHOD OF GENERATION AND DETECTION OF SINGLE-SIDEBAND SIGNALS," IN Proc. of IRE, VOL. 44, 1956, PP . 1703-1705. [12] D . G . Y E E , " A DESIGN METHODOLOGY FOR HIGHLY-INTEGRATED LOW-POWER "RECEIVERS FOR WIRELESS COMMUNICATIONS," P H . D . DISSERTATION, UNIVER-SITY OF CALIFORNIA, B E R K E L E Y , 2001. Bibliography 148 [13] K . P U N , Circuit Design for Wireless Communications: Improved Techniques for Image Rejection in Wideband Quadrature Receivers. K L U W E R A C A D E M I C P U B -LISHER, 2 0 0 3 . [14] J . C R O L S AND S . S T E Y A E R T , " L O W - I F TOPOLOGIES FOR HIGH-PERFORMANCE A N A L O G FRONT-ENDS OF FULLY INTEGRATED RECEIVERS," IEEE Trans, on Cir-cuits and Systems II, VOL. 4 5 , NO. 3 , PP. 2 6 9 - 2 8 2 , M A R C H 1 9 9 8 . [15] T . H . L E E , the Design of C M O S Radio-Frequency Integrated Circuits. C A M -BRIDGE UNIVERSITY PRESS, 2 0 0 4 . [16] M . F A U L K N E R , " D C OFFSET AND IM2 REMOVAL IN DIRECT CONVERSION R E -CEIVERS," IEEProceedings-Communications, VOL. 1 4 9 , PP. 1 7 9 - 1 8 4 , J U N E 2 0 0 2 . [17] A . A . L . N O O R , " D I R E C T CONVERSION RECEIVER FOR RADIO COMMUNICATION SYSTEMS," IEEE Potentials, VOL. 2 4 , PP. 3 2 - 3 5 , D E C . 2 0 0 5 . [18] S. A . M A S S , Microwave mixers. A R T E C H H O U S E , 1 9 9 3 . [19] B . M . J . L A S K A R AND S . C H A K R A B O R T Y , Modern receiver Front-Ends: Systems, Circuits, and Integration. J O H N W I L E Y AND SONS, 2 0 0 4 . [20] S . Z H O U AND M . C H A N G , " A CMOS PASSIVE MIXER WITH LOW FLICKER NOISE FOR LOWPOWER DIRECT-CONVERSION RECEIVER," JSSCC, VOL. 4 0 , PP. 1 0 8 4 -1 0 9 3 , M A Y 2 0 0 5 . [21] "3RD GENERATION PARTNERSHIP PROJECT (3GPP) TECHNICAL SPECIFICATION; GROUP G S M / E D G E , RADIO ACCESS NETWORK: R A D I O TRANSMISSION AND R E -CEPTION," R E L E A S E 6 , 3 G P P T S 4 5 . 0 0 5 V 6 . 5 . 0 , A P R . 2 0 0 4 . [22] M . V A L K A M A , M . R E N F O R S , AND V . K O I V U N E N , " A D V A N C E D METHODS FOR I /Q IMBALANCE COMPENSATION IN COMMUNICATION RECEIVERS," IEEE Trans, on Signal Processing, VOL. 4 9 , NO. 1 0 , PP. 2 3 3 5 - 2 3 4 4 , O C T 2 0 0 1 . [23] L . D E R AND B . R A Z A V I , " A 2 -GHZ CMOS IMAGE R E J E C T RECEIVER WITH LMS CALIBRATION," JSSCC, VOL. 3 8 , PP. 1 6 7 - 1 7 5 , F E B 2 0 0 3 . [24] B . R A Z A V I , " A 2 . 4 G H Z CMOS RECEIVER FOR IEEE 8 0 2 . 1 1 WIRELESS LANS," JSSCC, VOL. 3 4 , PP. 1 3 8 2 - 1 3 8 5 , O C T O B E R 1 9 9 9 . [25] , " A 5 . 2 G H Z CMOS RECEIVER WITH 6 2 D B IMAGE REJECTION," IN Symp. VLSI Circuits Dig. Tech. Papers, 2 0 0 0 , PP. 3 4 - 3 7 . [26] B . LINDQUIST, M . ISBERG, AND P . W . D E N T , " A NEW APPROACH TO ELIMI-NATE T H E DC OFFSET IN A T D M A DIRECT CONVERSION RECEIVER," IN 43rd IEEE • Vehicular Technology Conf, 1 9 9 3 , PP. 7 5 4 - 7 5 7 . [27] R . SCHREIER AND G . C . T E M E S , Understanding Delta-Sigma Data Converters. PlSCATAWAY, N J : I E E E PRESS, 2 0 0 5 . Bibliography 149 [28] C . W A N G AND P . H U A N G , " A CMOS LOW-IF PROGRAMMABLE GAIN AMPLIFIER WITH SPEED-ENHANCED DC OFFSET CANCELLATION," IN IEEE Asia-Pacific Con], on ASIC, 2 0 0 2 , PP. 1 3 3 - 1 3 6 . [29] M . K . N E Z A M I , " P E R F O R M A N C E ASSESSMENT OF BASEBAND ALGORITHMS FOR DIRECT CONVERSION TACTICAL SOFTWARE DEFINED RECEIVERS: I / Q IMBALANCE CORRECTION, IMAGE REJECTION, DC REMOVAL, AND CHANNELIZATION," IN Proc. of IEEE MILCOM, 2 0 0 2 , PP. 3 6 9 - 3 7 6 . [30] S . SAMPEI AND K . F E H E R , " A D A P T I V E DC-OFFSET COMPENSATION ALGORITHM FOR BURST MODE OPERATED DIRECT CONVERSION RECEIVERS," IN 42nd IEEE Vehicular Technology Conf, 1 9 9 2 , PP. 9 3 - 9 6 . [31] A . SHOVAL, D . A . JOHNS, AND W . M . S N E L G R O V E , " M E D I A N - B A S E D OFFSET CANCELLATION CIRCUIT TECHNIQUE," IN Proc. of IEEE International Symp. on Circuits and Systems, 1 9 9 2 , PP. 2 0 3 3 - 2 0 3 6 . [32] Z . Z H A N G , Z . C H E N , L . TSUI, AND J . L A U , " A 9 3 0 MHZ CMOS D C - O F F S E T F R E E DIRECT- CONVERSION 4 -FSK RECEIVER," IN ISSCC, 2 0 0 1 , PP. 2 9 0 - 2 9 1 . [33] F . BEHBAHANI , Y . KISHIGAMI, J . L E E T E , AND A . A . ABIDI, " C M O S MIXERS AND POLYPHASE FILTERS FOR L A R G E IMAGE REJECTION," JSSCC, VOL. 3 6 , PP. 8 7 3 - 8 8 7 , J U N E 2 0 0 1 . [34] L . Y u AND W . S N E L G R O V E , " A NOVEL ADAPTIVE MISMATCH CANCELLATION SYSTEM FOR QUADRATURE I F RADIO RECEIVERS," IEEE Trans, on Circuits and . SystemsII: Analog and Digital Signal Processing, VOL. 4 6 , PP. 7 8 9 - 8 0 1 , J U N E 1 9 9 9 . [35] J . T U B B A X , B . C O M E , L . V . P E R R E , S . D O N N A Y , M . E N G E L S , AND C . D E S S E T , " J O I N T COMPENSATION OF IQ IMBALANCE AND PHASE NOISE," IN Proc. of the 57th IEEE Semiannual Vehicular Technology Conf, 2 0 0 3 , PP. 1 6 0 5 - 1 6 0 9 . [36] M . Y A L K A M A AND M . R E N F O R S , " A D V A N C E D DSP FOR I /Q IMBALANCE C O M -• PENSATION IN A LOW-IF RECEIVER," IN Proc. of IEEE International Conf. on Communications, 2 0 0 0 , PP. 7 6 8 - 7 7 2 . [37] W . N A M G O O N G , " P E R F O R M A N C E OF A DIRECT-CONVERSION RECEIVER WITH AC COUPLING," IEEE Trans, on Circuits and Systems II, VOL. 4 7 , NO. 1 2 , PP. 1 5 5 6 - 1 5 5 9 , D E C . 2 0 0 0 . [38] T . G A B A R A AND W . FISCHER, " C A P A C I T I V E COUPLING AND QUANTIZED F E E D -BACK APPLIED TO CONVENTIONAL CMOS T E C H N O L O G Y , " IEEE Journal of Solid-State Circuits, VOL. 3 2 , NO. 3 , PP. 4 1 9 - 4 2 7 , M A R C H 1 9 9 7 . [39] A . H A Y E S , Z . GHASSEMLOOY, N . S E E D , AND R . M C L A U G H L I N , " B A S E L I N E -WANDER EFFECTS ON SYSTEMS EMPLOYING DIGITAL PULSE-INTERVAL MODULA-TION," IN IEE Proc. Optoelectron, V O L . 1 4 7 , NO. 4 , A U G 2 0 0 0 , PP. 2 9 5 - 3 0 0 . Bibliography 150 [40 [41 [42 [43 [44 [45 [46 [47 [48 [49 [50 [51 [52 [53 M . K A N D L I K A R AND I. JACOBS, "ANALYSIS OF QUANTIZED F E E D B A C K LOW-FREQUENCY RESTORATION IN DIGITAL REGENERATORS," IEEE Trans, on Com-munications, V O L . 38, NO . 8, PP . 1118-1120, A U G . 1990. M . H . SHAKIBA, " A 2 .5GB/S ADAPTIVE C A B L E EQUALIZER," IN Proc. of IEEE International Solid-State Circuits Conference, 1999, PP. 396-397 AND 483. P . R o o , S. SUTARDJA, F . A . S. W E I , AND Y . C H E N G , " A CMOS TRANSCEIVER A N A L O G FRONT-END FOR GIGABIT E T H E R N E T OVER CAT-5 CABLES," IN Proc. of IEEE International Solid-State Circuits Conference, 2001, PP . 310-311, 458. O . SHOAEI, A . SHOVAL, AND R . LEONOWICH, " A 3v LOW-POWER 0 .25^M CMOS 100MB/S RECEIVER FOR FAST E T H E R N E T , " IN Proc. of IEEE International Solid-State Circuits Conference, 2000, PP . 308-309, 467. J . B A B A N E Z H A D , " A 3.3v A N A L O G ADAPTIVE LINE-EQUALIZER FOR FAST E T H -ERNET DATA COMMUNICATION," IN Proc. IEEE Custom Integrated Circuits Con-ference, 1998, PP. 343 -346. S. SHANG, S. MlRABBASI, AND R . S A L E H , " A TECHNIQUE FOR DC-OFFSET RE-MOVAL AND CARRIER PHASE ERROR COMPENSATION IN INTEGRATED WIRELESS RECEIVERS," IN Proc. of the Int. Symposium on Circuits and System, 2003, PP. 1-173 - 1-176. J . B A R R Y , E . L E E , AND D . MESSERSCHMITT, Digital Communication, 3RD ED. K L U W E R A C A D E M I C PUBLISHER , 2004. S. HAYKIN, Communication Systems. J O H N W I L E Y AND SONS, 2001. A . C A R U S O N E AND D . JOHNS, " A N A L O G ADAPTIVE FILTERS: PAST AND PRESENT," IN IEEE Proceedings of Circuits Devices System, 2000, PP . 82-90. P . S. R . DINIZ, Adaptive filtering : algorithms and practical implementation. K L U W E R A C A D E M I C PUBLISHER , 1997. Y . Z H E N G , M . C A O , AND H . G A R G , " A NOVEL ADAPTIVE EQUALIZATION AND CANCELLATION ALGORITHM FOR DIRECT CONVERSION RECEIVERS," IN Proc. of Information, Communications and Signal Processing conf., 2003, PP. 631- 635. M . C A O , Y . Z H E N G , AND H . G A R G , " A NOVEL ALGORITHM FOR DC OFFSETS AND FLICKER NOISE CANCELLATION IN DIRECT CONVERSION RECEIVERS," IN Proc. of Int. Conference on Communications systems, 2003, PP. 441- 445. A . OPPENHEIM AND R . SCHAFER, Discrete-time signal processing. P R E N T I C E H A L L , 1999. Z . EBADI , S. MIRABBASI, AND R . S A L E H , " T H E APPLICATION OF C O M P L E X QUANTIZED F E E D B A C K IN INTEGRATED WIRELESS RECEIVERS," IEEE Transaction on Circuits and systems, V O L . 53, PP. 594-604, M A R . 2006. Bibliography 151 [54] S . Kou AND B . L E E , Real-time digital signal processing. J O H N W I L E Y , 2 0 0 1 . [55] J . PROAKIS AND M . SALEHI, Communication systems engineering. P R E N T I C E H A L L , 2 0 0 2 . [56] H . D A R A B I AND A . ABIDI, "NOISE IN R F - C M O S MIXERS: A SIMPLE PHYSICAL MODEL," IEEE Trans, on Solid State Circuits, VOL. 3 5 , PP. 1 5 - 2 6 , J A N . 2 0 0 0 . [57] B . R A Z A V I , Design of Integrated Circuits for Optical Communications. N E W Y O R K : M C G R A W - H I L L , 2 0 0 3 . [58] A . M A Z Z A N T I , F . S V E L T O , AND P . A N D R E A N I , " O N T H E AMPLITUDE AND PHASE ERRORS OF QUADRATURE L C - T A N K CMOS OSCILLATORS," JSSC, VOL. 4 1 , PP. 1 3 0 5 - 1 3 1 3 , J U N E 2 0 0 6 . [59] A . R O F O U G A R A N , J . R A E L , M . R O F O U G A R A N , AND A . ABIDI, " A 9 0 0 MHZ CMOS LC-OSCILLATOR WITH QUADRATURE OUTPUTS," IN Proc. of IEEE International Solid-State Circuits Conference, 1 9 9 6 , P. 3 9 2 3 9 3 . [60] T . L E E AND A . HAJIMIRI, " O S C I L L A T O R PHASE NOISE: A TUTORIAL," JSSC, VOL. 3 5 , PP. 3 2 6 - 3 3 6 , M A R C H 2 0 0 0 . [61] " L E C T U R E 1 2 : NOISE IN V O L T A G E CONTROLLED OSCILLATORS," H I G H S P E E D COMMUNICATION CIRCUITS AND SYSTEMS M I T C O U R S E , SPRING 2 0 0 3 . 

Cite

Citation Scheme:

        

Citations by CSL (citeproc-js)

Usage Statistics

Share

Embed

Customize your widget with the following options, then copy and paste the code below into the HTML of your page to embed this item in your website.
                        
                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            src="{[{embed.src}]}"
                            data-item="{[{embed.item}]}"
                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
                            data-width="{[{embed.width}]}"
                            async >
                            </script>
                            </div>
                        
                    
IIIF logo Our image viewer uses the IIIF 2.0 standard. To load this item in other compatible viewers, use this url:
http://iiif.library.ubc.ca/presentation/dsp.831.1-0100561/manifest

Comment

Related Items