SELF-ALIGNED GALLIUM ARSENIDE INTEGRATED MESFETs FOR MICROWAVE CIRCUITS by DAVID B . A . S c , A THESIS THE B. SUTHERLAND Queen's SUBMITTED IN REQUIREMENTS MASTER University, PARTIAL 1986 FULFILMENT FOR THE DEGREE OF APPLIED OF SCIENCE in THE FACULTY Department We accept to THE OF GRADUATE of E l e c t r i c a l t h i s the thesis required UNIVERSITY David B. Engineering conforming standard OF BRITISH July © as STUDIES COLUMBIA 1988 Sutherland, 1988 OF In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department The University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 DE-6G/81) ABSTRACT A refractory gallium a r s e n i d e MESFETs h a s s a m p l e and hold c i r c u i t . the p a r a s i t i c factor t o be self-aligned end gate been developed The p r o c e s s has i n t h e i r microwave performance. compatible 18GHz on with FETs microwave probes Ottawa O n t a r i o . s a m p l e and was The producing o f TiW and at anneal the The an u n d e r c u t gate metal was c o n t a c t s t o GaAs. end I t was Centre in used found and the gate an e v a p o r a t e d metal a to to test sampling rate plasma etch airbridges Metal-Insulator-Metal yielded t h e d i e l e c t r i c were a single rapid thermal suitable MESFETs with by technique the was MESFETs procedures evaporation capacitors using s i l i c o n developed. alloy fabricated A ion suitable r e s i s t a n c e of s e l f - a l i g n e d using (MIM) provide maintained Also, for self-aligned that a implant process. overlayer. up MHz. r e s i s t a n c e when compared t o t h o s e t o reduce fabricating Research implant characteristics more c o n v e n t i o n a l s e l e c t i v e developed the structure for developed chip with included f o l l o w i n g the s e l f - a l i g n e d reduced on amplifiers tested equipment t o 2 5 0 ' T' designed measured were a l s o maximum process limiting g a i n was Communications The a reduce which allowed buffer for to A method o f s p u t t e r i n g a t h e r m a l l y s t a b l e TiW/GaAs S c h o t t k y using on a A mask s e t was Usable microwave probes the t e s t refractory Schottky 5GHz fabrication implantation. applied b e e n shown t o Cascade Inc. probes hold operation. l i m i t e d by and process r e s i s t a n c e o f MESFETs w h i c h c a n be m i c r o w a v e m e a s u r e m e n t s t o be made. to fabrication nitride for and as The effect of gate resistance performance of the s e l f - a l i g n e d modeling with the EEsof MESFETs Inc. Touchstone. The m o d e l i n g showed capable giving of greater devices implant operation o f t h e s a m p l e and h o l d version o f SPICE t h a t model. The s i m u l a t i o n s be u s e d f o r gigahertz that with the was microwave high selective on investigated software frequency gain circuit showed was Sussman iii are than are geometry. The simulated Fort t h a t t h e s a m p l e and sampling. by package, s e l f - a l i g n e d MESFETs t h e same d e s i g n included the microwave using GaAs hold a MESFET could TABLE OF CONTENTS Page ABSTRACT i i L I S T OF FIGURES v i i ACKNOWLEDGMENT x 1. 1 2. INTRODUCTION 1.1 GaAs MESFET T e c h n o l o g i e s 1 1.2 Microwave Performance 6 1.3 T h e Sample a n d H o l d 8 1.4 Sample a n d H o l d Performance 8 1.5 Sample a n d H o l d Structures 9 SAMPLE AND HOLD DESIGN AND LAYOUT 2.1 The Sampling 2.2 The Hold C a p a c i t o r 14 2.3 Buffer Amplifiers 16 2.4 3. Gate 11 12 Layout 17 FABRICATION 3.1 Special 19 Structures 19 3.1.1 Fine Line Resist Profiles 3.1.2 Self-aligned 3.1.3 Post-anneal 3.1.4 Airbridges 26 3.1.5 MIM C a p a c i t o r s 29 'T' G a t e S t r u c t u r e Gate T h i c k e n i n g iv 19 21 24 Page 3.2 3.3 The R e f r a c t o r y Metal/GaAs Contact 31 3.2.1 Effect o f a Furnace Anneal 33 3.2.2 Effect o f Rapid Thermal Anneal 34 3.2.3 Effect o f Change o f TiW C o m p o s i t i o n 35 The Microwave Integrated Circuit Fabrication 36 Process 4. 41 MEASUREMENT AND TESTING 4.1 4.2 S t a t i c Measurements 41 4.1.1 T h e TiW/GaAs S c h o t t k y J u n c t i o n 41 4.1.2 Sheet R e s i s t a n c e o f Implanted Layers 43 4.1.3 Ohmic C o n t a c t R e s i s t a n c e 45 4.1.4 Source S e r i e s R e s i s t a n c e 45 4.1.5 S h e e t R e s i s t a n c e o f TiW F i l m s 48 4.1.6 Isolation 49 4.1.7 MESFET C h a r a c t e r i s t i c 4.1.8 Threshold Voltage 51 4.1.9 Low F r e q u e n c y T r a n s c o n d u c t a n c e 53 Microwave Curves 55 Measurements 4.2.1 S-Parameters o f MESFETs 4.2.2 S-Parameters of the Buffer 55 Amplifier 58 Stage 4.3 Testing 50 o f t h e Sample a n d H o l d C i r c u i t s v 60 Page 5. 5.1 5.2 6. 63 ANALYSIS AND MODELING M o d e l i n g o f MESFETs 63 5.1.1 Scattering 65 5.1.2 Maximum G a i n o f MESFETs parameters S i m u l a t i o n o f Sample a n d H o l d O p e r a t i o n 66 69 71 CONCLUSION REFERENCES 72 APPENDIX A - F a b r i c a t i o n P r o c e d u r e 78 APPENDIX B - I n p u t L i s t i n g s f o r M o d e l i n g APPENDIX C - M i c r o w a v e G a i n D e f i n i t i o n s vi 84 91 List Figure of Figures Description Page 1.1. Recessed gate f a b r i c a t i o n process 3 1.2. Refractory process 4 1.3. S e l e c t i v e implant 1.4. A high frequency equivalent GaAs MESFET in the configuration s e l f - a l i g n e d gate fabrication 5 f a b r i c a t i o n process circuit for a common-source 6 1.5. Basic 1.6. MESFET s a m p l i n g s w i t c h 10 2.1. Sample and 11 2.2. Triple 2.3. Interdigitated capactitor layout 2.4. Cross s e c t i o n of (MIM) s t r u c t u r e o f s a m p l e and hold schematic diagram g a t e s a m p l i n g FET Metal 13 cross-section 15 Insulator Metal 16 capacitor 2.5. Sample and 2.6. Mask s e t o v e r a l l l a y o u t 3.1. SEM s h o w i n g r e s i s t p r o f i l e w i t h 2/-/m g a p s Production of 'T' gate s e l f - a l i g n e d implant 3.2. 8 hold hold 17 with buffer amplifiers 18 of 1 lines 20 structure 3.3. SEM showing 'T' gate structure self-aligned ion implantation 3.4. Procedure o v e r l a y e r on 3.5. TiW 3.6. Airbridge technique 3.7. Airbridge evaporation for depositing a s e l f - a l i g n e d gates for for metal fabrication and l i f t o f f vii 23 25 26 gate with A l overlayer f a b r i c a t i o n by 22 a conventional by single 27 28 3.8. SEM o f a i r b r i d g e 29 3.9. SEM o f MIM 30 3.10. Doping p r o f i l e tail obtained from the mercury contact probe on a sample a n n e a l e d a t 8 0 0 ° C f o r 25 m i n u t e s w i t h TiW encapsulant 34 Doping p r o f i l e o b t a i n e d from t h e mercury c o n t a c t p r o b e on a s a m p l e g i v e n a n RTA a t 8 5 0 ° C f o r 60s w i t h TiW e n c a p s u l a n t 35 Doping p r o f i l e o b t a i n e d from t h e mercury c o n t a c t p r o b e on a s a m p l e s p u t t e r e d with W f o i l on t h e TiW t a r g e t t h e n given an RTA a t 9 5 0 ° C f o r 5s 36 3.13. The m i c r o w a v e i n t e g r a t e d c i r c u i t e m p l o y i n g s e l f - a l i g n e d MESFETs 37 3.14. A s e l f - a l i g n e d microwave FET 40 3.15. A completed 40 4.1. (kT/q) l n ( I ) v s . V for a TiW/GaAs S c h o t t k y j u n c t i o n 4.2. I vs. V f o r TiW (solid) and Ti/Pd/Au (dashed) S c h o t t k y j u n c t i o n s t o GaAs 43 4.3. Pad t o pad r e s i s t a n c e v s . pad for ohmic contacts to n transmission line separation implanted 44 4.4. Current d i s t r i b u t i o n s measurement resistance 4.5. Rend = d V / d l vs. 1/I for selective i m p l a n t a n d s e l f - a l i g n e d MESFETs 47 4.6. M e a s u r e d r e s i s t a n c e o f TiW a n d o f A l o v e r l a y e r v s . number o f s q u a r e s 49 4.7. I-V c h a r a c t e r i s t i c s for a d e p l e t i o n mode MESFET with l e n g t h a n d 200^m g a t e w i d t h self-aligned 0.8 ^m gate I-V c h a r a c t e r i s t i c s for a enhancement mode MESFET w i t h l e n g t h a n d 200^m g a t e w i d t h self-aligned 0.8 gate 3.11. 3.12. capacitor sample and h o l d a m p l i f i e r self-aligned + 4.8. 4.9. d s process g f o r end 46 d TiW g s viii with 50 -/l vs. V f o r a) a d e p l e t i o n MESFET b) a n enhancement MESFET d 42 and 51 52 4.10. Low f r e q u e n c y t r a n s c o n d u c t a n c e ( g ) vs. gate bias (V ) for a 100 /JUI w i d e s e l f - a l i g n e d MESFET 54 Mean w i t h s t a n d a r d d e v i a t i o n l i m i t s o f |S2i| in dB for self-aligned FETs (solid curves) and selective implant FETs (dashed c u r v e s ) 56 S m i t h c h a r t p l o t s o f mean with standard d e v i a t i o n l i m i t s o f a) Su and b) S22 from 2 t o 18GHz for self-aligned FETs ( s o l i d c u r v e s ) and s e l e c t i v e i m p l a n t F E T s (dashed curves) 57 |S | i n dB f o r b u f f e r amplifier circuit implemented w i t h s e l f - a l i g n e d FETs .58 m g s 4.11. 4.12. 4.13. 4.14. 4.15. 4.16. 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. C.l. 21 Smith c h a r t p l o t s o f a) Su f r o m 0.1 t o 5GHz for buffer circuit Sample and hold c o n f i g u r a t i o n used and b) S amplifier 2 2 59 layout and for testing probing 60 Oscilloscope traces of input and output s i g n a l s f r o m a s a m p l e and h o l d w i t h g u a r d g a t e s b i a s e d a t -0.8V 62 Lumped e l e m e n t 64 model o f MESFET | S i | v s . f r e q u e n c y from model measured d a t a ( p o i n t s ) 2 S and S from (solid lines) (cross-hatch) X 1 2 2 2 to and (lines) 18GHz from measured and 65 model data 66 Maximum gain of self-aligned MESFETs from model (lines) and measured data f r o m s e l f - a l i g n e d and s e l e c t i v e implant devices (points) 67 S i m u l a t e d i n p u t and o u t p u t w a v e f o r m s a sample and hold under the c o n d i t i o n s o f s e c t i o n 4.2 68 S i m u l a t e d i n p u t and o u t p u t w a v e f o r m s a s a m p l e and h o l d f o r 2.7GHz s a m p l i n g a 360MHz s i g n a l Power g a i n b l o c k d i a g r a m ix for test for of 70 .....91 Acknowledgement The work on t h e s a m p l e a n d h o l d the Defence D r . L. Young, f o r s u g g e s t i n g many o f t h e i d e a s o f t h i s Mr. H i r o s h i on was s u p p o r t e d by R e s e a r c h E s t a b l i s h m e n t , Ottawa. I t h a n k my s u p e r v i s o r , and circuit fabricating Kato i s t o be t h a n k e d for his guidance work. forhis collaboration devices. I a l s o thank David Hui f o r writing t h a t were u s e d t o p r e p a r e some o f t h e f i g u r e s x software in this routines thesis. 1. The INTRODUCTION o b j e c t o f t h e work d e s c r i b e d examine t h e a p p l i c a t i o n implantation technology of a gallium i n this arsenide t o microwave d e v i c e s t o a GaAs s a m p l e a n d h o l d circuit. u s i n g a r e f r a c t o r y metal gate c h a r a c t e r i s t i c s were m e a s u r e d a n d compared from d e v i c e s implant fabricated process. by the GaAs MESFET The m a j o r i t y o f work on mode MESFETs f o r d i g i t a l FET GaAs (SDFL), those obtained conventional the ultimate the technology. self-aligned fabrication logic circuits. implemented only The f i r s t (BFL) a n d GaAs digital Schottky depletion mode T h e s e a p p r o a c h e s were s u c c e s s f u l i n a c h i e v i n g h i g h Diode devices. speeds [ 1 , 2 ] however, h i g h power d i s s i p a t i o n p r e v e n t e d GaAs selective t o t h e d e v e l o p m e n t o f enhancement a p p r o a c h e s , B u f f e r e d FET L o g i c Logic microwave Technologies t e c h n o l o g i e s has been r e l a t e d logic with fabricated and M o d e l i n g was u s e d t o d e t e r m i n e p e r f o r m a n c e t h a t c a n be a c h i e v e d 1.1 more to to particular were Static was self-aligned and i n Devices process. thesis using their use approach o f D i r e c t Coupled FET i n VLSI a p p l i c a t i o n s . The Logic l o w power GaAs l o g i c (DCFL) using Enhancement-Depletion FET Logic r e q u i r e s t h e development o f a c o n s i s t e n t f a b r i c a t i o n f o r enhancement mode d e v i c e s require very 0.1 - tight [3]. Enhancement 0 . 2 V ) i n order t o allow f o r adequate 1 technique mode control of the threshold voltage voltage (EDFL) devices (typically swing and noise [4], margins unmodulated channel Also i t is necessary to make o f a n enhancement mode d e v i c e s h o r t b e c a u s e it i s d e p l e t e d by s u r f a c e s t a t e p i n n i n g o f t h e Fermi is therefore highly resistive The most important unmodulated channel self-aligned process regions n used. type methods implant o r a w a f e r w i t h an n i s opened over p h o t o r e s i s t p a t t e r n t h a t i s used MESFETs. used to The channel is In the i s used type to define so that is must be to dope the gate active layer regions gates b a s i c types of self-aligned GaAs MESFETs have been demonstrated. Implantation f o r N^-layer Technology," uses a temporary implant. a second The gate gate gate structure the with the Schottky process the or SAINT [6]. "Self-Aligned process the the Schottky other process uses a r e f r a c t o r y metal the h i g h temperature The r e f r a c t o r y post-implant self-aligned involves undercutting a lateral One, block 'dummy 1 [7] self-aligned anneal, contact. g a t e w h i c h must then The withstand anneal. gate gate gap between t h e s e l f - a l i g n e d itself. in technologies for i s removed f o r t h e p o s t - i m p l a n t i s d e p o s i t e d t o form gate characterized implant to the of o r d e r t o g i v e r e p r o d u c i b l e t h r e s h o l d v o l t a g e s o f MESFETs Two is using MESFETs well the recessed i s deposited. A d i f f i c u l t y with the recessed gate that the gate recess etch the and epitaxial channel etched gate d e s i r e d t h r e s h o l d v o l t a g e a r e o b t a i n e d when t h e metal and reduce r e s i s t a n c e are the recessed 1.1), a single A window level [5]. implantation technologies. (figure the process (figure 1.2) [8] s o a s t o l e a v e a s m a l l source/drain and the gate T h i s i s done t o d e c r e a s e and t o i n c r e a s e t h e r e v e r s e breakdown v o l t a g e o f n gate + implant capacitance the Schottky contacts while channel. The reduced expected using 1.3). a the length the device selective For a be and the gate reduced beyond the unmodulated MESFET transconductance implant fabricated using s e t by that technology a selective the source/drain i s d e f i n e d b y t h e mask l a y o u t the limits c a n be over fabrication i m p l a n t p r o c e s s , t h e l a t e r a l gap between implant of l e n g t h o f the unmodulated channel t o increase achieved (figure minimizing and lithography and mask - pattern f o r device wells K* region - implant 3.1. GaAs substrate - anneal Au6e 4, p.n. - pattern f o r ohmic contacts - evaporate and l i f t o f f AuGe - alloy n1 IS 1 p.fl. - pattern f o r Schottky gate - etch channel - evaporate and l i f t o f f gate source Schottky gate drain —'-isr-'— Figure 1.1. Recessed completed MESFET gate fabrication process + cannot alignment. P.fl. n 4 P.R. K" region - pattern f o r device wells - implant channel n~ S.I. BtAs substrate - anneal - sputter TiW gate metal - pattern and l i f t o f f A l dummy gates P.R. fi U N* region - undercut dummy gates - pattern and implant source/drain n' T l - N * region MlBt TU pte i 1 _ J 1II w 11 I - pattern and l i f t o f f AuGe ohmic contacts - alloy - completed MESFET Figure 1.2. Refractory self-aligned gate fabrication process 5 P.R. H" region — p a t t e r n and implant device wells n" S.I. GaAs substrate - anneal P.R. N* region pattern and implant source/drain n tr region AuGe i 1 1 - evaporate and l i f t o f f AuGe 1 Schottky gate 1 i 11 1 - pattern for ohmic contacts - alloy i - pattern and l i f t o f f Schottky ( Figure 1.3. Selective implant - completed MESFET f a b r i c a t i o n process gate 6 1.2. Microwave Performance An e q u i v a l e n t high-frequency circuit [9] for m o d e l i n g o f t h e GaAs MESFET i n t h e common-source configuration i s shown the model intrinsic t h a t was u s e d b y L i e c h t i includes parasitic i n figure 1 . 4 . as well as The f i g u r e the extrinsic shows model both which elements. 1 INTRINSIC M O D E L -dg r GATE g O — A W R d DRAIN AVV 0 'ds SOURCE SOURCE Figure 1.4. A high frequency equivalent circuit for a GaAs MESFET i n t h e common-source c o n f i g u r a t i o n . Using the intrinsic model assuming t h e feedback c a p a c i t a n c e neglected, C g s the c u t o f f frequency i s equal tog V B shown C d g i n figure i s very / T where small 1.4 and and can the current be through i s given by 2 n C ge 2 rr T [1.1] Here T = the channel, L L/ i s the c a r r i e r V e i s the e l e c t r o n i s the modulated channel oscillation / transit saturation d r i f t length. The through velocity maximum where u n i t y power g a i n i s r o a x time and frequency achieved is of given by: de Equation non-unilateral 1.2 can extrinsic [1.2] be generalized GaAs MESFET model [9] for the as 1^2 de R It c a n be source s e r i e s + g using gate Also, 2nf R . ( de T R g C [1.3] ) dg are critical The than and the determining the refractory MESFETs self-aligned in L with low self-aligned source series g a t e s c a n be made can those smaller fabricated implant or recessed gate techniques since the from devices the gate s e r i e s the r e f r a c t o r y gate r e s i s t a n c e significant. mask have R e f r a c t o r y gate metal gate m e t a l i z a t i o n s used effective B lithography self-aligned circuits. + yield length i s undercut result, e o f a MESFET. can [10]. optical selective R resistance R technique resistance + >• seen t h a t the l e n g t h o f the gate frequency response gate R gate resistance R g a t e m e t a l may in g may be be d e s i r a b l e As a microwave c a n be more r e s i s t i v e i n o t h e r p r o c e s s e s and actual length. application by than the as a r e s u l t , the greater. i f the e f f e c t on t h e m i c r o w a v e p e r f o r m a n c e o f t h e Plating of the device is 8 1.3 T h e Sample a n d H o l d The consists 1.5. basic structure o f a sampling of switch ) a and sample a hold and hold circuit capacitor (figure sampling switch hold node hold . capacitor' Input Figure The is 1.5. s t r u c t u r e o f sample and h o l d most common a p p l i c a t i o n o f s a m p l e a n d h o l d i n analogue t o d i g i t a l used conversion. A sample a t t h e f r o n t end o f an analogue t o d i g i t a l to relieve ADCs. some o f t h e a p e r t u r e The s h o r t provides acquisition a constant take place. 1.4 Sample a n d H o l d The its Basic Output time problems time signal level of period the hold is converter (ADC) associated with sample f o r A/D and conversion hold to Performance main measures o f a sample and h o l d ' s a c q u i s i t i o n time, and circuits input performance are impedance, droop r a t e , and output impedance. The specification acquisition time is o f a sample and h o l d . the key performance I t i s t h e time required t o s t o r e on the the hold s a m p l e and hold maximum s a m p l i n g The hold on i f the to impedance input charge The It can output directly become to a connected to the hold input signal i s presented and is input to be For the sample and to supply the then very impedance path. required capacitor, the the frequency limited. r a t e of decay of the important i t approaches the i f the s a m p l e and hold i f hold node load. . If the hold output, then the capacitor l o a d may affect is the rate. Sample and The sample Hold Structures m o s t common and holds disadvantage of the the hold. impedance i s i m p o r t a n t must d r i v e c u r r e n t 1.5 s a m p l e and limits at rate. The droop time h o l d may i s the signal present acquisition the hold s a m p l e and droop r a t e potential. of signal the of the s a m p l e and impedance l i n e response of the sampling The importance of the a high current input. level frequency of the depends upon t h e example, c a p a c i t o r the diode bridge are of diode must be of very the in characteristics sampling bridges diode bridge sampled r e p r e s e n t a t i o n Variations types and well balanced to give input across signal a cause i n t e g r a t e d diode bridges results. Also, complementary s t r o b e f e e d t h r o u g h from b e i n g at wafer to pulses observed used A FETs. arrangement i s the therefore prevent pulse switches are on major fact that an accurate the output. surface give in could inconsistent required the to output. GaAs d i o d e b r i d g e s a m p l e and holds P o u l t o n e t a l [11] and b y Wong and The MESFET implemented sampling have been Fawcett [12]. switch i n GaAs f o r h i g h s p e e d (figure described 1.6) sampling. The a single fabrication MESFET a s s a m p l i n g p u l s e and nonuniformities. the capacitance sampling (C capacitance. t h e h o l d node g s ) As to gate One is i t i s n o t as s e n s i t i v e disadvantage that its a result, a the sampling certain extent. of gate using to e t . a l . [13] MESFET and [14]. Figure 1.6. MESFET s a m p l i n g switch to a source node pulse i s fed through GaAs of i t requires a c t s as a v o l t a g e d i v i d e r w i t h t h e h o l d s w i t c h e s a r e d e s c r i b e d by A k e r s al that often advantages a MESFET o v e r t h e d i o d e b r i d g e a r r a n g e m e n t a r e t h a t only is by to sampling Swierkowski et 2. The Barta and sample Rode sampling gate amplifier that SAMPLE AND and [15]• The (figure of Rutherford testing hold followed stage and circuit circuit by a in hold probes allow on to require a regular contact was used GaAs and a high using by MESFET buffer modified allow performance made b u t a capacitor layout order The that consisted of The probes. LAYOUT followed hold 2.1). [16] o f sample HOLD DESIGN AND from frequency Cascade Inc. c h i p microwave measurements t o pad be arrangement. Buffer amplifier Sampling gate rt Pula« i n v bito o Hold Capacitor *T in Figure 2.1. Sample and hold 11 < > schematic diagram. +0 RF out 12 The sample implementation integrated 2.1 in circuit and hold circuit both selective was and designed self-aligned t e c h n o l o g i e s u s i n g e i g h t mask 1) Registration for subsequent l e v e l 2) n~ FET channels. 3) TiW 4) n 5) AuGe/Ni ohmic c o n t a c t s . 6) Dielectric MIM 7) Schottky d i o d e s , MIM 8) Au a i r b r i d g e body, b o n d i n g The implant self-aligned implant + Barta and Rode tops, airbridge addressed of the sampling applied to the centre •guard gates. "the thickening. of pulse g a t e by t h e u s e of a triple 2.2. pulse to the h o l d was 'sampling* pulse d i s p l a c e d by t h e triple t h e s a m p l e and pad problem smaller gate They found that i n p u t and t o the hold when rather feedthrough could momentary f o r w a r d c o n d u c t i o n o f t h e g u a r d and footings. the pulse than the was outer R u t h e r f o r d showed u s i n g S P I C E s i m u l a t i o n s the reduction i n single bottoms. Gate node o f t h e s a m p l e and carriers alignment. g a t e s , MIM g a t e s a m p l i n g MESFET a s shown i n f i g u r e 1 levels. insulator. f e e d t h r o u g h w i t h a MESFET s a m p l i n g feedthrough implant FET s o u r c e s / d r a i n s . plating Sampling for pulse. g a t e s , a l l o f 1+m hold layouts. For be gates attributed which comparative length, were that to remove purposes, included in 13 Guard gates Sampling gate Ohmic contact nnn N Channel Source S.I. 6a As substrate F i g u r e 2.2. Another T r i p l e gate sampling effect FET c r o s s - s e c t i o n . e x a m i n e d b y R u t h e r f o r d was t h a t p r o p a g a t i o n on t h e g a t e . TiW g a t e metal (=*3n/square ) a n d b e i n g o v e r t h e c h a n n e l IfF/Mm 2 capacitance per unit transmission applied i t has resistive approximately area depending on g a t e b i a s . The l i n e nature o f t h e gate causes a phase s h i f t o f an signal along i t s width. The e f f e c t f o r s m a l l width gates such as those used circuits, i s quite of signal b u t becomes i m p o r t a n t i s not i ndigital f o r analogue important integrated a n d power MESFETs. S P I C E s i m u l a t i o n s show t h a t a p u l s e i n p u t w o u l d t a k e a b o u t t o propagate To 100/jm a l o n g a g a t e o f l e n g t h 0.5/jm. reduce t h i s phase s h i f t effect, the d e s i g n e d b y R u t h e r f o r d was d r i v e n b y a c o n t a c t connected t-junction at 2Ops the center of the gate's s t r u c t u r e o f t h e sampling gate w i t h t h e Cascade I n c . microwave probes source c o n t a c t pad o f t h e sampling sampling pad 60 jjm was which width. not to be was The compatible because i t r e q u i r e d gate gate split. the This restriction the gate on c o n t a c t pad of the sampling l a y o u t made i t MESFET f r o m one necessary end in to drive the present design. 2.2 The Hold The the signal constant Capacitor i n p u t time frequency value gate arrangements. half due the g i v e n by the o f 25ps f o r b o t h The to parasitic to the fixed hold 60Mm w i d e FET o f 100 Q order sampling be sample capacitance FET was node c a p a c i t a n c e were r e d u c e d . typically an single is has hold a channel node. input sampling approximately and half node resistance capacitor s e t t o 0.13pF i n o r d e r t o significantly In a d d i t i o n , p u l s e sampling of the hold and time capacitance. o f 0.25pF. the d e p l e t i o n l a y e r of the chosen t o g i v e the t r i p l e limits input depletion layer capacitance The then hold The the product h o l d node c a p a c i t a n c e and and sampled. o f t h e h o l d c a p a c i t a n c e was constant A of the can r e s i s t a n c e and time due that i s approximately MESFET c h a n n e l The constant I f the value give the a a total nonlinearities c a p a c i t a n c e might cause s i g n a l and such of the hold c a p a c i t o r from t h i s v a l u e , feedthrough for in signal in distortion. droop r a t e would increase. Two the types s a m p l e and interdigitated 2.3) . o f h o l d node c a p a c i t o r s were hold layouts. The f i n g e r s of Schottky first metal incorporated c o n s i s t e d o f 2 pm with 2^m gaps in wide (figure 15 GND Figure The (figure 2.3. Interdigitated capactitor s e c o n d was a m e t a l 2.4). An MIM than an i n t e r d i g i t a t e d difficult shorting as capacitor requires Pinholes of i t s terminals. alloying capacitors to form i s quite on t h e o t h e r value more T h e TiW m e t a l i z a t i o n c o u l d b e used contacts low as r e p o r t e d i n this is cause could be so by employed quite design. as rough in after the yield of these Barta and Rode [15]. h a n d r e m a i n s smooth e v e n a f t e r t h e r e f o r e was u s e d but area could AuGe t e n d s t o become ohmic structure substrate i n the d i e l e c t r i c t h e MIM b o t t o m p l a t e o r A u G e / N i design. (MIM) less c a p a c i t o r of equal to fabricate. Rutherford's TiW i n s u l a t o r metal layout. annealing and 16 Figure 2.4. Cross section of Metal Insulator Metal (MIM) capacitor. 2.3 Buffer Amplifiers A s a m p l e and h o l d switch and a h o l d signal source i s high, amplifier current a high capacitor. i n front of i t may the c a n be as s i m p l e be impedance sampling at the output. where sample and h o l d ' s quantizers which have l a r g e i n p u t in hold with figure 2.5. to switch capacitor. input This is add to sampling a the and o u t p u t b u f f e r s is shown t o the capacitor [17]. sees in A the i f the current case the buffer provide a r e added i n f r o n t o f capacitance of Similarly, be n e e d e d s o t h a t t h e h o l d conversion and necessary i s required to drive significant a b u f f e r may as a However, i f t h e i m p e d a n c e needed t o charge t h e h o l d sample and h o l d output, circuit A/D flash sample schematically 17 input output sampling buffer buffer switch hold high Figure 2.5. output about logic output Sample a n d h o l d w i t h 3dB g a i n a n d t o i n s u r e t h a t t h e h o l d by t h e l o a d . i n v e r t e r with Hornbuckle, Van T u y l and Provided the has and E s t r e i c h [18-21]. the node been droop buffered examined gate input but impedance was b u f f e r would o n l y serve has sufficient current to increase c i r c u i t not as i s . a p p e a r s a s a 0.25pF c a p a c i t o r t h r o u g h the input s i g n a l path by A similar amplifier sampling b e c a u s e t h e sample and h o l d has a h i g h sample and h o l d i n the design T h e a m p l i f i e r was a feedback c o u l d have been added b e f o r e The buffer amplifiers. b u f f e r a m p l i f i e r was i m p l e m e n t e d r a t e was u n a f f e c t e d FET impedence capacitor input to give low hold impedence An node lOOfi. drive, complexity. 2.4 L a y o u t The buffer p a d arrangements f o r sample and h o l d s , a m p l i f i e r and compatible with discrete MESFETs were t h e Cascade I n c . microwave an designed probes. isolated to be 18 Figure E l e m e n t s 1-8 for implementation 9-11 were 2.6. Mask on t h e c h i p set overall layout i n a self-aligned selectively implanted. shown gate 12-14 e l e m e n t s i n c l u d i n g V a n D e r Pauw c r o s s , line, and r i n g - d o t included so t h a t metalization could structures. the be A resistivity determined. TiW of fat layout i n f i g u r e 2.6 were technology were FET, stepped the whereas diagnostic transmission resistor self-aligned was gate 3. 3.1 FABRICATION Special Structures Before performing a f u l l fabrication run, experiments were conducted t o develop procedures f o r making s t r u c t u r e s t h a t were r e q u i r e d f o r the sample and h o l d s . 3.1.1 Fine Line Resist P r o f i l e s The most common technique f o r on GaAs i s l i f t - o f f . The patterning lift-off process metalizations involves opening windows i n a l a y e r of p o s i t i v e p h o t o t o r e s i s t by exposure t o UV l i g h t f o l l o w e d by development. the wafer by evaporation. The p h o t o r e s i s t s t r i p p e r such as d e p o s i t e d on top o f the behind where metal only The metal i s d e p o s i t e d wafer is acetone. photoresist the then The is windows on soaked metal lifted were in that off opened a was leaving to the substrate. Difficulties can arise in lift-off p r o f i l e of the patterened p h o t o r e s i s t i s if rounded the sidewall or tapered. Evaporated metal w i l l then form a continuous f i l m which may not lift o f f o r may l e a v e metal pattern. It 'wings 1 on the edges of the d e f i n e d i s t h e r e f o r e most d e s i r a b l e t o c r e a t e an or r e v e r s e t a p e r e d s i d e w a l l r e s i s t p r o f i l e . using techniques d i e l e c t r i c assisted that involve lift-off two [22], t e c h n i q u e was employed i n t h i s work. 19 levels however T h i s can of a undercut be resist done or chlorobenzene 20 An overhang s t r u c t u r e can be c r e a t e d i n a o f r e s i s t by soaking the r e s i s t i n a developer as chlorobenzene p r i o r t o development. the r e s i s t The single inhibitor surface i s m o d i f i e d by the soak so t h a t i t so as t o l e a v e an overhang. 3.1 resist 1 pm chlorobenzene t e c h n i q u e . profile produced such layer develops than the u n d e r l y i n g r e s i s t i s an SEM o f a layer of slower Figure using I t shows good v e r t i c a l s i d e w a l l s the and undercut. Figure 3.1. gaps. SEM showing r e s i s t p r o f i l e o f l^m l i n e s w i t h 2/JIP. 21 3.1.2 Self-aligned A " I " gate s t r u c t u r e self-aligned sidewalls gate process. may source/drain is 'T* G a t e S t r u c t u r e serve i s not necessary f o r the refractory A both refractory as the t o leave a l a t e r a l refractory capacitance mask gate. gap b e t w e e n structure the T h e e f f e c t . o f t h e gap n + is , r e d u c e MESFET s h o r t c h a n n e l with itself heavy 3.2) regions and to n [23]. (figure decrease effects, t h e r e v e r s e b r e a k d o w n v o l t a g e [24] s o t h a t vertical f o r the i m p l a n t and as t h e S c h o t t k y g a t e advantageous however i f a T g a t e used gate + It is the gate and i n c r e a s e larger values of V d s may b e s w i t c h e d when compared w i t h MESFETs f a b r i c a t e d w i t h no T gate structure. orientation The similar CF 4 The l a t e r a l sensitivity also helps t o produce t h e T gate by S a d l e r and Eastman p l a s m a e t c h o f t h e TiW was u s e d rather than a r e a c t i v e to reduce gate [25,26]. t e c h n i q u e used t o t h a t used gap ion etch. to structure [10] e x c e p t produce the that was a undercut 22 Sputter TiU -RlP.R. P.R. Pattern For dummy gates EuBporate RI GsRs substrate LlFtoFF GsRs substrate Etch TiU in CF, pi asms 4 Figure 3.2. Production of 'T' g a t e structure for self-aligned implant. The determining suitable most critical of this the d u r a t i o n of the plasma e t c h undercut. composition aspect and The situation was process was required to complicated thickness of the r e f r a c t o r y metal was when in give the changed. For t h i s r e a s o n , the wafer was o p t i c a l l y checked d u r i n g the e t c h i n g p r o c e s s t o an time. An SEM o f a described process i s Figure 3.3. 'T' structure shown i n f i g u r e SEM showing ion implantation. gate determine ' T ' gate periodically appropriate produced using etch the 3.3. structure for self-aligned 24 3.1.3. Post-anneal Gate Thickening F o r t h e b e s t microwave performance o f a desirable that the r e s i s t i v i t y discussed i n s e c t i o n 1.2. conductive gate gate structure self-aligned annealing Sadler 'T' result, i n place during and t o p s were alloying left A l dummy g a t e s small after of of t h e 'T' annealing occured the e f f e c t s when A l , during were u s e d t o s e r v e severe during C r o r Pd/Au dummy g a t e s i n place highly Unfortunately, metal the were used. N i , Au, o r Pt annealing. as the n as As a implant + t h e y were removed f o r t h e a n n e a l . Geissberger self-aligned gates et a l . [28] d e p o s i t e d after SiON t h e n patterning Rutherford [16] required and implant. + c y c l e when e i t h e r mask, t h e n be w o u l d be t o l e a v e t h e 'dummy' g a t e [27] r e p o r t e d s i m i l a r gate o f t h e gate metal i ti s T h e s i m p l e s t way t o o b t a i n a source/drain n interdiffusion MESFET, and gates on annealing by p l a n a r i z i n g suggested a l l MESFET metal evaporating an an a top of layer overlayer electroplating of o f Au. technique t o be c o n t a c t e d by a removable that metal i n t e r c o n n e c t web a n d a l l a r e a s where p l a t i n g was n o t d e s i r e d t o be masked o f f . I n t h i s work, a n e v a p o r a t i o n method u s i n g two l e v e l s p h o t o r e s i s t was d e v e l o p e d the self-aligned hardbaking overlayer width The gates. a lower level f o r obtaining a The t e c h n i q u e of resist from c o n t a c t i n g t h e n and alignment procedure + metal overlayer of on i n v o l v e d p l a n a r i z i n g and in order regions and to to prevent the allow line t o l e r a n c e s on t h e o v e r l a y e r t o be i s o u t l i n e d i n f i g u r e 3.4. relaxed. 25 m P.R. Spin -TiU on p h o t o r e s i s t Hardbake CeR> s u b s t r a t e P.R. P l a n a r i r e r e s i s t i n CeRs kubfcirete - R i P.R. \ etch o f p h o t o r e s i s t P.R. Spin TiU P.R. 0. 2 on Pattern upper l e v e l p h o t o r e s i s t u s i n g gate mask CBRS m b i trBie Evaporate D i s s o l v e Figure 3.4. self-aligned Procedure for shown because in poor lower l e v e l figure 3.5. alignment The y i e l d o f o v e r l a y e r r e s i s t metal The of g a t e w i t h an structure the overlayer on Al to was the Al overlayer not symmetric TiW o f g a t e s w i t h t h e o v e r l a y e r was a d h e s i o n o f t h e A l t o t h e TiW. planarization a A l gates. precise possible. l i f t o f f depositing A n SEM o f a TiW s e l f - a l i g n e d is and e t c h was n o t s u f f i c i e n t t h e t o p o f t h e TiW g a t e . It is possible was not l o w due t o that t o c l e a r the r e s i s t the from 26 Figure 3.1.4. 3.5. TiW g a t e w i t h Airbridges Airbridges are an integral microwave i n t e g r a t e d c i r c u i t f o r making c o n n e c t i o n s for A l overlayer. spiral inductors, interconnects. parasitic metalizations The utilizes and as a second l e v e l a r e used associated with on a d i e l e c t r i c most common of (MMIC) p r o c e s s e s . t o the top electrode Airbridges capacitance part monolithic They o f MIM are used capacitors, of metalization f o r because them t h a n there i s there less i s for layer. technique two l e v e l s o f r e s i s t , most f o r producing an evaporation, airbridges an etch, and an 27 electroplating step [29]. This procedure i s outlined i n figure 3.6. EwBporated T l Pet tern photoresist P.R. P.R. F i r s t leuel P.R. EuBporate T i ( lBBBS) GaRs Substrate A S V- Socond l M l For a i r b r i d g e Footings Second E l e c t r o p l a t e d flu P.R. leuel P R . P a t t e r n tecond I sue! photoresist for B i r b r l d g e bodies P.R. F i r s t leoet P . R . P.R E l e c t r o p l a t e exposed t i t o n l u t with gold Befit Substrate V- Dissolve upper photoresist Etch level In Acetone titftniu* I n HF D i t t o ! w e lower level Goflt A Figure 3.6. Substrate photoresist i n Deetone y^A i r b r i d g e f a b r i c a t i o n by a c o n v e n t i o n a l technique. A t e c h n i q u e was d e v e l o p e d t o two levels of resist 3.7). (figure lower l e v e l was a p p l i e d . the lower to give and a The p r o c e d u r e resist single involved produce evaporation f r o m b e i n g d i s s o l v e d when t h e of resist good m e t a l so t h a t sidewall and using liftoff a hardbake t o prevent the T h e c h l o r o b e n z e n e t r e a t m e n t was level airbridges second not level applied i t s edge p r o f i l e was to rounded coverage. P a t t e r n photoresist For Birbri.dcjfc Footings H&rdbeke r e s i s t P a t t e r n second teuel photoresist For e i r b r i d g e bodies EuBporBte Ru Figure 3.7. liftoff. Airbridge f a b r i c a t i o n by single evaporation and Gold technique [30]. g i v i n g them a s h e e t Thicker metal strength not a i r b r i d g e s c o u l d be f o r long normally interconnects circuit. method An a span a i r b r i d g e s . concern, 3.1.5 MIM to The employed in 0.050/square improve sheet the mechanical resistivity for this short sample and the is span hold liftoff 3.8. 3.8. SEM of a i r b r i d g e . Capacitors Metal-insulator-metal extensively of about airbridge fabricated using i s shown i n f i g u r e Figure l/urn t h i c k w i t h particularly those o f an to resistivity i s sometimes u s e d s u c h as SEM made up i n MMIC d e s i g n s (MIM) f o r RF capacitors tuning and are bypassing. used The MIM consists two metal p l a t e s . thinner be a thin than the l a y e r of d i e l e c t r i c Since the airbridge with thick d i e l e c t r i c airbridge The [31], can be in this of nitride layer. was dielectric e v a p o r a t e d as lower e l e c t r o d e . that was an fabricated as Figure 3.9 top generally metal avoid use top electrode footing and TiW SEM of an o f MIM capacitor must An of enhanced of 800& was much more a r e a . The shows an SEM shorting. work u s e d a p l a s m a described. 3.9. plate element r e q u i r e s approximately airbridge Figure is between f a b r i c a t e d without the chemical vapor deposition f o r the the i n order to however s u c h an MIMs f a b r i c a t e d sandwiched dielectric bottom metal p l a t e , c o n n e c t e d w i t h an MIM an of silicon of the u s e d as MIM MIM the capacitor 31 3.2 The R e f r a c t o r y Metal/GaAs The process most c r i t i c a l i s that aspect elemental of good such for reproducible Tungsten the desirable of 8 00°C and properties h i g h temperature s t r e s s when a n n e a l e d [33]. alloy to give better et a l . [35] GaAs/Ti of T i W Q3 ? found that w a s r e p o r t e d by i f t h e a l l o y was r e a c t i o n degraded such on gates Also, without s p u t t e r e d under p a r t i c u l a r In t h i s work, a n alloy A procedure c o n t a c t probe annealing requiring mercury requiring was involving devised parameters a complete contact on electrodes is to be used Mukherjee i n titanium, the a barrier. self-aligned t u n g s t e n has been used for problems used when as t h e r e f r a c t o r y metal. the for was [42]. Electronics run i t stress reduce TiW/GaAs fabrication probe tungsten. [34] has test the thermal nitrides t h e MSI to GaAs and conditions to was to of the Schottky adhesion o f TiW due on Yokoyama e t a l . silicides pure easily electrical stability for An sputtering. low too r i c h materials as r e f r a c t o r y metal been p u b l i s h e d [36-41]. self-aligned the q u a l i t y other of peel a d h e s i o n t o GaAs t h a n p u r e C o n s i d e r a b l e work process 0 after or greater. by chemical f o u n d t o c r a c k and metal i s t h e most deposition [ 3 2 ] , h o w e v e r i t was An implant characteristics as t u n g s t e n characterized has self-aligned Schottky annealing at temperatures r e f r a c t o r y metal resistivity the of the high-temperature-stable r e f r a c t o r y g a t e w h i c h must e x h i b i t post-implant Contact to effects mercury of various interface be C-V evaporated Inc. conducted. profiling on without samples The without [43]. Instead, two mercury contact with the contacts to the t o back electrodes implanted are temporarily s u r f a c e o f a specimen. s u r f a c e a c t a s two Schottky The diodes into mercury placed back [44]. The series capacitance of the two Schottky measured between t h e mercury c o n t a c t s w i t h m o d e l 4275A LCR greater than very drawn meter. t h a t of the c l o s e t o the reverse bias conventional The implanted obtained Since C-V other, capacitance was applied curves the and area the of the to the doping a t o be with w i t h TiW present 1) Etch wafer surface 2) Implant without 3) Light 4) Sputter with 5) Anneal with 6) Remove TiW 7) Obtain chemical 2* to allow on t h e profiles of surface to be steps. 3^m. patterning (blanket implant 3xl0 1 2 cm~ ). etch. TiW. TiW i n CF doping as 4 A made. doping a m i n i m a l number o f p r o c e s s i n g was junction. contact profiles much capacitance contact small was Packard c o n t a c t was measured f o l l o w i n g t e s t procedure allowed wafers annealed Hewlett o f one small junctions encapsulant using test plasma. p r o f i l e with mercury probe. parameters. 2 33 3.2.1 Effect of a Furnace Tests using encapsulated furnace quarter furnace observed on annealing, furnace. furnace. pulled from procedure, greatly the annealed surface oxidized. A on on TiW in the removal residual film a f t e r the was oxidized TiW the the TiW added t o t h e b o a t was Another wait heated of surface nitrogen was part of TiW the pushed t o the allowed after the flow during in the substrates heated part the furnace. surface during boat Using annealing of was this was reduced. on the reducing of a high a CF 4 plasma e t c h s u b s t r a t e was atmosphere. TiW, o b s e r v e d e v e n on The could be f i l m was obtained s a m p l e s w h i c h were a p p a r e n t l y profiles of the a residual p r e s u m e d t o be showed o n l y 3.10. a tail of from some c l e a r e d of the activated surface samples annealed t e m p e r a t u r e GaAs/TiW r e a c t i o n r a t h e r t h a n Doping p r o f i l e s figure TiW made f o r 15 m i n u t e s w i t h o x i d a t i o n of the After film was gases flowed the been surface oxidation a load lock before the The were plasma. 4 h y d r o g e n gas The had minutes. GaAs s u b s t r a t e prevent probe that a p p e a r e d t o be r e m o v e d i n a CF To in the mercury wafers a t 8 00°C f o r 25 from the was the Anneal evidence oxidation. areas surface dopant in as of the film. The seen in 34 Figure 3.10. c o n t a c t probe TiW Doping profile tail obtained on a s a m p l e a n n e a l e d from the mercury- a t 8 00°C f o r 25 m i n u t e s with encapsulant. 3.2.2 Effect o f Rapid Thermal Similar results subjected to a rapid seconds. Anneal were observed thermal By v a r y i n g t h e RTA anneal time probe c o u l d be t h e RTA a t 8 5 0 ° C f o r 60s under Gaussian positions 1.6xl0 1 2 increased. The on two wafer 2 950 temperature, °C for i t was observed u s i n g the in figure t o doping p r o f i l e s quarters ± 0 . 4 x l 0 c m ~ o r 40110%. 1 2 at wafers 5 found mercury b e s t r e s u l t s were o b t a i n e d u s i n g a s shown curves f i t t e d quarter (RTA) and t h a t t h e amount o f a c t i v a t e d d o p a n t for gave an 3.11. The obtained activated area at dose 6 of 35 l x io .1 .2 .3 DEPTH Figure 3.11. Doping p r o f i l e (MICRONS) obtained p r o b e o n a s a m p l e g i v e n a n RTA at from the mercury 850 ° C contact f o r 60s w i t h TiW encapsulant. 3.2.3 Effect o f Change o f TiW C o m p o s i t i o n Further improvement increasing the tungsten The tungsten attaching using 50% content film. content o f the sputter a piece o f tungsten the surface proportionately a c t i v a t i o n was o b t a i n e d b y o f the sputtered c o n d u c t i v e epoxy. of i n doping reduce foil The f o i l area of to which film deposited was the target test procedure was was s a m p l e s s p u t t e r e d w i t h t h e TiW t a r g e t a n d W f o i l on i n t h e RTA. samples without The r a p i d thermal encapsulation anneals but with a p r o x i m i t y t o p r o v i d e some a r s e n i c o v e r p r e s s u r e . by target approximately expected t h e amount o f t i t a n i u m i n t h e The mercury c o n t a c t annealed increased the sputtering covered TiW. deposited conducted i n place were GaAs to on then conducted wafer in I t h a s been found t h a t significant c a p l e s s RTA out-diffusion i s performed with The activated RTA a t 950°C dose measured no arsenic f r o m two w a f e r f o r 5 s e c o n d s was 2 . 8 x l 0 .2 3.12. Doping p r o f i l e p r o b e on a s a m p l e The Microwave obtained Integrated f o r the registration self-aligned p r o c e d u r e was Circuit measured. Details cm" or an 70±5%. 2 contact on t h e TiW t a r g e t then Fabrication Process etched about supplier's i n figure etch. 3.13. g a t e s i s n o t shown not 1 2 given from t h e mercury T h e a l i g n m e n t mask was t h e n u s e d t o steps are outlined quarters f o r 5s. remove a n y damage c a u s e d b y t h e quarters a (Blcren) The GaAs s u b s t a t e s were i n i t i a l l y [46]. when overpressure [45]. ±0.2xl0 sputtered with W f o i l g i v e n a n RTA a t 9 5 0 ° C 3.3 1 2 occurs .3 tteplh Figure of arsenic conducted 3 polishing pattern The s u b s e q u e n t process the figure until after of the process are given 3.13 the wafer processing The m e t a l o v e r l a y e r on in to because devices i n a p p e n d i x A. the the were 37 5 i I i con n i i r i de 5.1. a) GaRs s u b s t r a t e S u b s t r a t e c l e a n e d , e t c h e d , and about silicon 300A nitride deposited. 1 n region 5 ( 1 icon n i t r i d e GaFIs s u b s t r a t e 5.1. b) ^ P h o t o r e s i s t patterned f o r device w e l l s then implanted n " , TiU n region 5.1. EaRs s u b s t r a t e c) Annealed i n furnace w i t h s i l i c o n n i t r i d e c a p . and about of TiW s p u t t e r e d on s u r f a c e . 3 000A 3 [ Rl- P.R. P.R. Cap removed P.R. O n reg i 5.1. d) Gafls s u b s t r a t e P a t t e r n e d f o r dummy gates and MIM bottoms. About 5000A Al evaporated on s u r f a c e . Figure 3.13. employing The microwave self-aligned MESFETs. integrated circuit process TiU RI I n i i ^ wwwMmy///////^ n region 5.1. GaRs sub&trate 5.1. GaRs s u b s t r a t e Al lifted off. B n f) region Undercut etched i n CF„ plasma. B - PR ^ n regions ' ^ r e g i on g) P a t t e r n e d and implanted n + . RuGe b) Removed A l , annealed i n RTA, p a t t e r n e d and evaporated ohmic c o n t a c t s . F i g u r e 3.13. continued AuGe i) L i f t e d off AuGe, alloyed deposited s i l i c o n n i t r i d e to form ohmic contacts, and dielectric. PR. n n j) regions region R e s i s t d e f i n e d f o r H I M and s i l i c o n n i t r i d e etched. Ti/Pd/Ru i _1_ n n X) reaions regio' T i / P d / A u S c h o t t k y metal e v a p o r a t e d , and l i f t e d MESFET MIM off. Schottky diode RuEe 1) Au a i r b r i d g e s e v a p o r a t e d , sample and h o l d s completed. Figure 3.13. continued 40 Scanning e l e c t r o n micrographs of a microwave FET sample and hold circuit s e l f - a l i g n e d technique are fabricated shown in and using the described figures 3.14 and respectively. 100/jm F i g u r e 3.14. A s e l f - a l i g n e d microwave FET. 2 00/L/m F i g u r e 3.15. a A completed sample and h o l d a m p l i f i e r . 3.15 4. 4.1 MEASUREMENT AND TESTING S t a t i c Measurements S t a t i c measurements were made on MESFETs and d i a g n o s t i c s t r u c t u r e s u s i n g a Hewlett parameter a n a l y z e r . model 4145A semiconductor The measurements were used t o e v a l u a t e the b e n e f i t s of using the self-aligned s e l e c t i v e implant p r o c e s s . i n t h e modeling o f d e v i c e s 4.1.1 Packard process rather than the A l s o , measured parameters were used (chapter 5 ) . The TiW/GaAs Schottky J u n c t i o n Measurements on t h e TiW/GaAs Schottky j u n c t i o n were made t o determine whether s u i t a b l e c h a r a c t e r i s t i c s e x i s t e d a f t e r the r a p i d thermal anneal o f t h e s e l f - a l i g n e d d e s i r a b l e t h a t t h e Schottky gate barrier height and low of reverse a n + implant. MESFET leakage Enhancement mode MESFETs which operate w i t h have current t h e gate It is a large [47]. forward b i a s e d r e q u i r e t h e b a r r i e r t o be s u f f i c i e n t l y h i g h t o a l l o w adequate v o l t a g e swing [ 4 8 ] . The r e v e r s e important leakage an current i s i n microwave d e v i c e s f o r low n o i s e a p p l i c a t i o n s [49]. The c u r r e n t - v o l t a g e r e l a t i o n s h i p o f a diode neglecting series r e s i s t a n c e i s g i v e n by I for kT V >> [4.1] q P l o t s o f t h e l o g a r i t h m o f forward diode c u r r e n t I versus 41 42 applied voltage V currents f o r TiW f r o m 30nA t o of such curves gave an i d e a l i t y leakage current of I -0.5V. The s t a t e d v a l u e s f o r data gates factor = 6 ± 2nA a t r f r o m 10 linear for linear portion o f n = 1.20±0.05 a a r e t h e mean a n d collected were The s l o p e o f t h e IOO/LJA. reverse deviation Schottky reverse bias estimated MESFETs on and a of standard two quarter wafers. k T ln(I) I I T 1 1/' s l o p s — -800 I -.5000 Figure 4.1. The by • 1 . 20 2500/div ln(I/amps) vs. V for a the o f Schottky 'knee' in the contacts diode r e l a t i o n s h i p when p l o t t e d o n a n a p p r o p r i a t e The knee v o l t a g e higher not than 2.000 ( V) self-aligned junction. b a r r i e r heights observing «= n - (kT/q) TiW/GaAs S c h o t t k y / obtained was o b t a i n e d undergo thermal f o r TiW/GaAs with processing were current-voltage current scale contacts was t h e Ti/Pd/Au contacts (figure 4.2). compared [50]. slightly which d i d (cnA) 10.00 1 1 1 // // 1.000 /div ll II II If 0000 -.5000 4.2. Figure Schottky 4.1.2 I v s . V f o r TiW R e s i s t a n c e o f Implanted Although implanted source, (solid) thermal interface, i t must drain and of n + other be reduce Ti/Pd/Au to f o rcarrying v o l t a g e probes activate doped n . + structures. [51]. the other U s i n g t h e V a n d e r Pauw o n two q u a r t e r w a f e r s the of the The d o p e d r e g i o n s was m e a s u r e d u s i n g b o t h current while TiW/GaAs t h e sheet r e s i s t i v i t y sheet Van d e r The V a n d e r i s a f o u r t e r m i n a l s t r u c t u r e i n w h i c h two locations (dashed) Layers sufficient regions Pauw c r o s s a n d t r a n s m i s s i o n l i n e used and a n n e a l i n g must n o t damage t h e donors and thus resistivity cross 2.000 ( V) j u n c t i o n s t o GaAs. Sheet Schottky .2500/div VF Pauw terminals two are technique f a b r i c a t e d by t h e used at are as 10 self-aligned process r e s i s t a n c e s o f 190±4 0 o / s q u a r e gave s h e e t doped n + (2.0xl0 doped n 2 (3.0x10 resistances and 1700 ± 3 0 0 n / s g u a r e ions/cm ) 1 3 ions/cm o f 270 ). fi/square for Sadler [27] regions f o r regions obtained a n d 1600 fi / s q u a r e on n sheet and + n~ regions respectively. The s h e e t obtained two of resistance of the n f r o m t r a n s m i s s i o n l i n e -measurements quarter wafers. a series of The t r a n s m i s s i o n l i n e ohmic 2,4,6,8, a n d lO^m pad doped + contact on t h e n resistance versus slope of the f i t t e d + implanted spacing + structure with mask layer. sheet was also a t 10 l o c a t i o n s on consisted spacings A plot i s shown i n f i g u r e the n line, pads layer o f pad 4.3. of to From t h e r e s i s t a n c e was found to b e R B h = 200 ± 60 n / s q u a r e . K o H p 0 1 0.02 1 1 OJW 1 1 0.06 1 1 0.08 1 1 0.1 ' ' 0.12 1 ~ 0.14 r Number of Souorva Figure 4.3. contacts to n Pad t o p a d r e s i s t a n c e v s . p a d s e p a r a t i o n f o r ohmic + implanted transmission line. 45 4.1.3 Ohmic C o n t a c t Resistance The 'y' intercept of represents the r e s i s t a n c e o f two product of contact contact resistance of Source S e r i e s One xeason self-aligned fitted 0.4 ± 0 . 2 by pad C5mm. process was The using the 'end' Contact in series. The a normalized resistances Price make current through the forward source to by [53]. 4.3 of [52]. f o r f a b r i c a t i n g MESFETs u s i n g t h e gate MESFET w h i l e figure Resistance The the in width gave M u r a k a m i and resistance small. passing line ohmic c o n t a c t s r e s i s t a n c e and 0.3 fimm h a v e b e e n r e p o r t e d 4.1.4 the the source s e r i e s r e s i s t a n c e can Schottky drain contact as refractory be series measured gate contact a voltage probe r e s i s t a n c e o f t h e MESFET i s t h e n d e f i n e d R d e « e n d d of as [4.2] I 9 where V I g i s the d s being passed distributed the end drain-source from gate t o source. along the r e s i s t a n c e as r e s i s t a n c e of the length of the defined conducting R Here a is a voltage constant • n d . = that that results Since the channel from current gate current (figure 4.4), i n c l u d e s a c o n t r i b u t i o n from channel R e is + a R is then the R . c h [4.3] ch determined by the current d i s t r i b u t i o n i n t h e channel. this way is resistance. then Several series resistance an The end r e s i s t a n c e as measured i n overestimate techniques of for the source determining the of the channel doping p r o f i l e i n order t o e l i m i n a t e t h e e f f e c t of the channel r e s i s t a n c e on t h e measured end r e s i s t a n c e . Lee et al. channel resistance shown can be that the contribution determined directly by the source nature [56] have [53-55] r e q u i r e knowledge o f series of the measuring d i f f e r e n t i a l end r e s i s t a n c e f o r v a r i o u s v a l u e s o f d r a i n I d the current applied. Sou rce Gat. Dr8 i n R.. Rcn Figure 4.4. Current distribution for end resistance measurement. The measured d r a i n - s o u r c e drain currents Yds where = voltage are applied i s given when both g d a r e the source and and by ( I d - r l g ) R e + I d Rch + l ( n k T / q I d ) + Rd I d and R gate drain series [4.4] resistances 47 respectively [56]. R The *nd source From e q u a t i o n 4.2 we f i n d = R e + ^ series k T /qi ) [4.5] d resistance may then f i t t i n g a l i n e o f s l o p e nkT/q t o a p l o t o f R resistance measurements self-aligned value of the and two s e l e c t i v e source t e c h n i q u e was R self-aligned were e series made at implant resistance 10 be vs. e n d l/l . d locations quarter R g on by End two wafers. The using this obtained = 3 8 ± 7Q f o r s e l e c t i v e and found = 5 ± lfi for devices. F i g u r e 4.5. Rend = d V ds s e l f - a l i g n e d MESFETs. /dig vs. 1/I for selective d implant and 48 4.1.5 Sheet Resistance The o f TiW speed o f s i g n a l propagation increases as t h e r e s i s t i v i t y [57-60]. The s h e e t measured u s i n g chip layout. applying along Films of on t h e g a t e o f a the gate metal resistance of the sputtered MESFET is film was included on the The s t r u c t u r e c o n s i s t e d o f s i x c o n t a c t s , two for the stepped r e s i s t o r current the length pattern t o t h e TiW r e s i s t o r of the resistor. was a l s o u s e d t o m e a s u r e s h e e t TiW reduced and f o u r as v o l t a g e probes The s t e p p e d r e s i s t o r resistance after the pattern overlayer o f A l was e v a p o r a t e d on t o p o f t h e TiW. The measured r e s i s t a n c e R = V VI M e a s u r e d ' in f i g u r e 4.6 a g a i n s t probes used. at low the The measured s h e e t applicable frequencies, the effective o f t h e m e t a l i z a t i o n s becomes s m a l l e r as a At effect. The high skin p and p e r m e a b i l i t y 6 = f depth M J where / i s t h e s i g n a l f r e q u e n c y at Profilometer 40GHz are t h i c k and t h e A l o v e r l a y e r films the skin effect at frequencies The resistances slopes of R s h = a and the depths lOOOOA t h a t t h e TiW f i l m than with [4.6] [ 6 1 ] . The s k i n was material of by 400OA ± 200 o n l y becomes i m p o r t a n t greater of of result 1^2 4100A scans revealed 6 LJ i s g i v e n 1 P ( " / result, c are skin TiW plotted resistivities resistivity and is t h e number o f s q u a r e s b e t w e e n t h e v o l t a g e frequencies. thickness ,. . applied Al respectively. was A of 3700 ± 2 0 0 & thick. for the As a metal 40GHz. lines 0.87 ± 0.06 in figure ^/square 4.6 for gave the sheet TiW m e t a l i z a t i o n and R overlayer. R = 3.7 the Sadler fi/square TiW f i l m = 0.11±0.01 [27] fi/square reported a of work may the be sputter a f o r TiW w i t h sheet on a 2000A" TiW f i l m . i n this tungsten content resistivity B h resistance Al of The l o w e r r e s i s t i v i t y o f result deposited o f T i i s eight times that the of the film. enhanced The bulk of W [62]. o 0 20 40 Numbar of Squares Figure 4.6. M e a s u r e d r e s i s t a n c e o f TiW and of TiW with Al o v e r l a y e r v s . number o f s q u a r e s . 4.1.6 Isolation Transmission line s t r u c t u r e s 48 0^m long and s e p a r a t e d 30/jm o f s e m i - i n s u l a t i n g GaAs were u s e d t o m e a s u r e t h e provided b y t h e s e m i - i n s u l a t i n g GaAs s u b s t r a t e . A by isolation current of 50 200 ± 50nA was measured when a potential across the transmission l i n e contacts. of 10V was applied This i s t y p i c a l of the i s o l a t i o n a c h i e v e d i n many GaAs f a b r i c a t i o n p r o c e s s e s [ 6 3 ] . 4.1.7 MESFET C h a r a c t e r i s t i c Curves Drain current c h a r a c t e r i s t i c s f o r a mode MESFET f a b r i c a t e d figure typical depletion by t h e s e l f - a l i g n e d p r o c e s s a r e shown i n 4.7. Id (mA) Vgs (V) 50.00 0.0 -0.5 5.000 /div -1.0 -1.5 -2.0 0000 0000 F i g u r e 4.7. -2.5 3000/div I-V c h a r a c t e r i s t i c s f o r a ( V) 3.000 self-aligned depletion mode MESFET w i t h 0.8/jm gate l e n g t h and 2 00^/m gate width. The was 3.0x10 channel implant dose used f o r d e p l e t i o n cm . Enhancement mode MESFETs mode MESFETs were fabricated using a lighter current channel implant dose of 2.0x10 c h a r a c t e r i s t i c s f o r s u c h a MESFET a r e cm' . Drain in figure 2 shown 4.8. Id (mA) Vg« (V) 0.6 .0000 Figure 4.8. Vds I-V 0.8^m 4.1.8 Voltage Plots versus the 0.5 mA fitting < I of the < 5mA. a line to Sample p l o t s a r e depletion gate length square root and 200Mm g a t e of the applied gate-source voltage d The threshold s u c h p l o t s and shown mode d e v i c e s . w a f e r s gave V . = 3.000 ( V) c h a r a c t e r i s t i c s f o r a s e l f - a l i g n e d enhancement mode MESFET w i t h Threshold .3000/div -1.7 in g s voltage drain figure 4.9 V was h f o r the for 10 -/T current & were n e a r l i n e a r extrapolating Measurements o f ±0.2V V width. for determined by to 0. Vl^ = enhancement MESFETs on d e p l e t i o n mode 2 and quarter devices. Figure 4.9. -/T^ v s . V g s f o r a ) a d e p l e t i o n MESFET and b ) a n e n h a n c e m e n t MESFET. 53 4.1.9 Low Frequency Transconductance The transconductance o f a MESFET, g (R h t h e channel r e s i s t a n c e resistances ( R and R s = = — — - dV m and source , can be r e l a t e d t o and d r a i n dCl/(R»+Rd+Rcr,)) Vds dVga Vds f-dReh (R»+Rd+Rch) [4.7] [ dVge Z The s m a l l source and d r a i n s e r i e s r e s i s t a n c e s w i t h s e l f - a l i g n e d MESFETs s h o u l d t h e r e f o r e r e s u l t d e v i c e t r a n s c o n d u c t a n c e when compared MESFETs. m with associated i n improved selective implant The measured transconductance o f 10 MESFETs from two s e l f - a l i g n e d and two g series ) by d dl g ) C B - 140 ± 10 selective mS/mm and A sample curve o f g given i n figure m 4.10. g m = implant 100 ± 10 quarter mS/mm wafers gave respectively. v s . gate b i a s f o r a s e l f - a l i g n e d MESFET i s Figure ( v g s 4.10. Low f r e q u e n c y t r a n s c o n d u c t a n c e ) f o r a 100pm w i d e s e l f - a l i g n e d M E S F E T . (g ) v s . g a t e ffi bias 55 4.2 Microwave Measurements Microwave network measurements analyzer and microwave p r o b i n g Centre a Cascade apparatus i n Ottawa O n t a r i o . at bonding calibration it pads using the HP 8510 54 automated Communications probes characteristic [64]. an I n c . model Because Research are coplanar impedance the o f t h e measurement s y s t e m r i g h t was n o t n e c e s s a r y wires made The m i c r o w a v e w a v e g u i d e s t h a t b r i n g a 50Q device were probes The probing a t t h e probe arrangement and bonded M i c r o w a v e m e a s u r e m e n t s were made on t h e A l o v e r l a y e r was e v a p o r a t e d 4.2.1 S - P a r a m e t e r s o f MESFETs wafers scattering fabricated wafers measured u s i n g standard by the the Cascade p a r a m e t e r s were computed microwave self-aligned jigs. devices on t h e TiW g a t e s . process selective and implant Inc. probing f o r both and e i g h t s e l e c t i v e two quarter process stage. shorted gates. measured forward types implant f r o m t h e c o m p u t a t i o n s due t o a p p a r e n t as requiring of devices. MESFETs were fabrication were Estimated d e v i a t i o n s f r o m t h e mean m a g n i t u d e a n d p h a s e o f self-aligned bond p a r a m e t e r s o f 80 MESFETs f r o m two q u a r t e r by t h e s e l f - a l i g n e d fabricated to the before The tips, allowed o n - w a f e r measurement o f d e v i c e s a n d c i r c u i t s w i t h o u t mounted, the allowed t o de-embed d e v i c e m e a s u r e m e n t s f r o m and f i x t u r e e f f e c t s . c h i p s t o be d i c e d , to these Five excluded failures such F i g u r e 4.11 shows t h e mean m a g n i t u d e o f the transmission coefficient S 2 1 with deviation limits i n dB f r o m curves) d s The s e l f - a l i g n e d showed g r e a t e r g a i n i n t h e selective V 2 t o 18GHz. implant devices = 4V. Smith (dashed chart plots self-aligned selective were implant devices. sensitivity the gate devices than and S x l 2 2 V d i d the = g s (solid OV and a r e shown i n f i g u r e The measured S - p a r a m e t e r s f o r t h e more uniform those of the result of the r e s i s t a n c e t o misalignment of This i s o f the source s e r i e s for selective system curves) with of S 4.12 a) a n d b) r e s p e c t i v e l y . 50n devices than likely a implant devices. e.ooo 1 1 1 3 j k 3.000 > > s N \ N -2.000 2.000 Figure for 4.11. \ s\ 10.00 (dashed c u r v e s ) . FETs (solid curves) X s*.1 1 18.00 FHEQ-GHZ Mean w i t h s t a n d a r d d e v i a t i o n self-aligned j 1 limits and s e l e c t i v e o f |S 2 |i n implant dB FETs Figure 4.12. limits o f a) S FETs (solid Smith c h a r t p l o t s a n d b) S curves) 2 2 o f mean w i t h from and s e l e c t i v e 2 to standard deviation 18GHz implant FETs for self-aligned (dashed curves). 58 4.2.2 S-Parameters The b u f f e r circuit Amplifier a m p l i f i e r was n e e d e d t o present a s u f f i c i e n t l y node t o p r e v e n t output of the Buffer signal signal t o a 50Q implemented w i t h layout. high droop, and line. An S-parameters i n t h e sample and hold impedance the hold to present isolated s e l f - a l i g n e d F E T s was The measured Figure 4.13 shows t h a t for five 50O s y s t e m up t o 2.6GHz. is nearly matched a n open The i n p u t circuit and t o 50O a s s e e n i n f i g u r e output buffered amplifier on the provided 4.13 gain of the is chip amplifiers figures impedance the the buffer in the amplifier to buffer included w e r e a v e r a g e d a n d t h e r e s u l t s a r e shown 4.14. Stage very and in a amplifier closely 4.14. 6.000 JO 1.000 2.550 Figure 4.13. '21 in dB for implemented w i t h s e l f - a l i g n e d FETs. buffer FREQ-GHZ amplifier 5.000 circuit 59 Figure to 4.14. S m i t h c h a r t p l o t s o f a) 5GHz f o r b u f f e r a m p l i f i e r circuit. S^ and b) S 2 2 from 0.1 4.3. Testing Using applied was and H o l d t o t h e RF signal oscilloscope Figure 4.15. Circuits t h r e e microwave probes, a input was sinusoidal o f t h e s a m p l e and h o l d , f e d i n t o the sampling gate, input used o f t h e Sample observed at a signal pulse and t h e s a m p l e d v e r s i o n the output on a was train of the sampling ( f i g . 4.15). Sample for testing. and h o l d layout and p r o b i n g configuration O s c i l l o s c o p e t r a c e s o f a 10MHz s i n u s o i d a l a t t h e s a m p l e and sampling figure hold input, g a t e , and 4.16 a). the The an 80MHz p u l s e t r a i n sampled sample signal are hold output signal and signal of the level i n t h e 12ns amplitude sampling of the sampling signal. t o the sampling i n p u t and s i g n a l s when t h e output 3 6MHz and The 0.8ns. for r a t e was maximum t e s t e d sampling The As feedthrough o f the sampling rate frequency pulse t h e RF output of the probe As with by the time that generator was fall nearly [16] sinusoidal showed gate r a t h e r than a not observed The lower used guard induced i t was and gate the two gates of the in the I t i s suspected of the h o l d was stage configuration, when a c t e d a s an RF the e f f e c t o f t h e s a m p l e and single a microwave probe t o measure t h e d e v i c e s . 'bias' probe a increased p u l s e t o t h e o u t p u t o f a sample T h i s e f f e c t was a result, the 250MHz. momentary c u r r e n t w h i c h w o u l d o t h e r w i s e be gate contact. of limited and became h o l d were n o t c o n t a c t e d b y arrangement used t h e low was minimum r i s e t y p e s o f s a m p l e a n d h o l d were m e a s u r e d . s a m p l e and 2% F i g u r e 4.16b) shows t h e by R u t h e r f o r d implemented w i t h a t r i p l e s a m p l i n g MESFET. of the l e s s than lOOmV a i n c r e a s e d t o 250MHz. frequencies g r e a t e r than conducted in was droop i n p u t f r e q u e n c y was a result,the pulse t r a i n sampling the shown feedthrough o b t a i n e d w i t h t h e T e k t r o n i x 115 Simulations hold gate. the sampling available pulse generator. c o u l d be The p u l s e t o t h e s a m p l e and h o l d o u t p u t was IV p u l s e a p p l i e d to The p e r i o d was applied fed into output sampled r e p r e s e n t a t i o n o f t h e i n p u t s i n u s o i d . held signal that choke t o i n the guard suppressed. not p o s s i b l e any guard gates on Because t o use a 62 fourth microwave supplying probe the biases V d d for and V. the s guard to the gate contact while circuit. strobe i n > input > output > input > output > Figure 4.16. O s c i l l o s c o p e t r a c e s o f i n p u t and from a sample and h o l d . with s e l f - a l i g n e d FETs. The s a m p l e and hold output was signals implemented 5. ANALYSIS AND M o d e l i n g o f t h e microwave performance done u s i n g t h e E E s o f I n c . s o f t w a r e m o d e l i n g was primarily gate resistance same a s t h a t on t h e s e l f - a l i g n e d package, Touchstone. shown i n f i g u r e and h o l d of was The the and to c a n be e x p e c t e d f o r g a t e s g i v e n 1.4. A Touchstone version i n c l u d e d t h e Sussman F o r t GaAs MESFET m o d e l 5.1. MESFETs device performance The MESFET m o d e l u s e d b y s i m u l a t e "the s a m p l e of intended t o determine the e f f e c t e s t i m a t e t h e improvement t h a t metal overlayer. MODELING of [65,66] is SPICE was a the that used t o devices. M o d e l i n g o f MESFETs The potential along the width of a s e l f - a l i g n e d not g e n e r a l l y u n i f o r m because nature. effect A of the gate's lumped e l e m e n t m o d e l was of a distributed lumped e l e m e n t m o d e l used gate r e s i s t a n c e (figure each h a v i n g the p r o p e r t i e s 5.1) MESFET. 63 transmission to and consisted o f a 1/8 slice gate of approximate capacitance. of eight the is line the The MESFETs, self-aligned 64 output port F i g u r e 5.1. The s e t t o 1/8 4.1.9. The Lumped e l e m e n t m o d e l o f MESFET. transconductance of the low source o f e a c h o f t h e MESFET e l e m e n t s frequency and drain series were g i v e n v a l u e s e i g h t t i m e s measured from gate series determined (section resistance from applied The C-V gate-source measurements t o the Schottky that of C for g g s . measured f o r t h e listing 4.1.4. of contact. (namely C R d s and R^ d g ,C in R end The the value The d c , 3.2.3) C ) d s , the width was TiW area with film given that zero other capacitors and d of was g s R resistance gate capacitance C section and s r e s i s t a n c e of the (section t h e S - p a r a m e t e r s o b t a i n e d by input 1/8 the to the capacitance per u n i t m o d e l o f t h e MESFET 1/10 g r e a t e r than t h e measured s h e e t 4.1.5). from R measured resistances, the devices i n s e c t i o n value corresponding found value was was bias in were g i v e n a the values were c h o s e n t o g i v e a g o o d f i t o f the model s e l f - a l i g n e d MESFETs i n with the values of the to those section components lumped e l e m e n t m o d e l f o r T o u c h s t o n e i s i n a p p e n d i x that were 4.2.1. The used B. in the 65 5.1.1 Scattering The parameters lumped e l e m e n t m o d e l was u s e d t o o b t a i n f o r MESFETs w i t h g a t e s e r i e s resistance R g a t e s a n d f o r MESFETs TiW overlayer. with S-parameters gates obtained g c o r r e s p o n d i n g t o TiW with from an modeling m e a s u r e m e n t s o f s e l f - a l i g n e d MESFETs a r e shown i n and 5.3. The e f f e c t o f the gate overlayer 2.000 Figure 5.2. measured d a t a |S | 21 vs. (points). frequency from Al (or and Au) from figures 5.2 i s seen p r i m a r i l y i n FREQ-GHZ 10.00 S-parameters model 18.00 (lines) and 66 .2 Figure 5.3. lines) and 5.1.2 Maximum when port is always cause the output part negative a S of from 2 of the be r e s i s t i v e r c or is gain of unstable. In has with a from two conjugate the matched ) 18GHz provided. impedance L to because device T -r model (solid MESFETs attainable to 2 2 (cross-hatch). simultaneous impedances ( 1 available conjugately c o e f f i c i e n t 2 data Gain device loop when and maximum output not X 1 measured The achieved S .5 an The match maximum a v a i l a b l e gain this terminations magnitude of is and required a device input impedance y i e l d s port terminations case, the input with a are provided. source greater or negative load than may or real The r e f l e c t i o n unity. A b r i e f summary o f power g a i n s S-parameters i s g i v e n maximum a v a i l a b l e i n Appendix and t h e i r r e l a t i o n s h i p t o C. gain of self-aligned Figure 5.4 devices as f r o m m e a s u r e d S - p a r a m e t e r s a n d f r o m t h e lumped The maximum s t a b l e available frequency implant gain than 1. the Data maximum the The model gave from model. from included. overlayer measured determined element of the the greater selective devices. 2.000 Figure i s also a gate was place L devices device with in \T \ > C implant the self-aligned high i s plotted \T \ > l o r g a i n where measured s e l e c t i v e of gain shows 5.4. 20.00 FREQ-GHZ Maximum g a i n o f s e l f - a l i g n e d (lines) and measured implant devices data (points). from MESFETs self-aligned 40.00 from and model selective By m o d e l i n g of the velocity a GaAs MESFET, M a l o n e y a n d relationship between the length L . The model gave parameters used o f c a r r i e r s through Frey cutoff / = T 27GHz. gave a frequency model A cutoff theoretical and for L 25GHz i n t h e Touchstone MESFET g a v e / = -J^Q—= [67] t h e channel of = the 0.8 pm. the frequency gate The self-aligned of / T = 30GHz 9° was o b t a i n e d b y Chao e t a l . [68] f r o m Morgan elements they a n d Howes o f a MESFET can oscillation be / [69] h a v e shown t h a t ( R , Rd, R , B a x and C g neglected, m a MESFET w i t h L = 0.3pm. then the d s i f the ) are so maximum parasitic small frequency that of i s g i v e n by [ 6 9 ] : 33 / From figure MESFET m o d e l e d L (GHz) 5.4, with an f = > maM Al L 4 0GHz f o r the overlayer at 0.8pm, e q u a t i o n 5.1 i n d i c a t e s [5.1] (pm) that on the self-aligned gate. the effect of parasitics on t h e microwave performance o f t h e MESFET i s s m a l l . et = al. [29] obtained MESFETs w i t h L = 0.5pm. / m < x x 2 0GHz Since with selective North implant 69 5.2. S i m u l a t i o n of Sample and Hold The v a l u e s f o r Rg, Rd, Rs, Operation C g s , Ca , g Cds and used for modeling w i t h Touchstone were used i n the SPICE s i m u l a t i o n s the sample and h o l d . A lumped element S i m u l a t i o n o f the sample and h o l d o f s e c t i o n 4.2 model under the was also test gave an output waveform ( f i g u r e 5.5) t h a t observed i n f i g u r e used. conditions similar to 4.16. 10 0 of 20 30 40 SO Tlm« ( n a ) F i g u r e 5.5. Simulated i n p u t and output waveforms f o r a and h o l d under the t e s t c o n d i t i o n s o f s e c t i o n Simulation at higher sampling 4.2. frequency a l l the T = lOOps i f a gate o v e r l a y e r was MESFETs in the circuit. An 5.6) (figure showed t h a t the a c q u i s i t i o n time o f the sample and be as s m a l l as sample hold could evaporated acquisition time on of 70 T = 500ps was bridge using obtained scheme. by Wong and Fawcett Swierkowski et a l . a GaAs MESFET s a m p l e and [14] [3-2] u s i n g achieved T a diode = 2 0Ops hold. -0.2 0 1 3 2 s 4 Tim* ( n » ) Figure and 5.6. hold Simulated output f o r 2.7GHz s a m p l i n g o f a 3 60MHz Complete i n p u t included i n p u t and i n appendix listings B. f o r the waveforms f o r a sample signal. SPICE simulations are 6. A gallium circuit arsenide fabrication g a t e s was microwave integrated p r o c e s s e m p l o y i n g MESFETs w i t h self-aligned developed. The with lower source s e r i e s t h a n MESFETs f a b r i c a t e d fabrication of CONCLUSIONS monolithic self-aligned resistance by implant y i e l d e d and selective larger Measured microwave scattering parameters MESFETs were more u n i f o r m a c r o s s s u r f a c e and between selective i m p l a n t MESFETs. available gain of that of the selective gate metalization resistance of o v e r l a y e r was A and of the were reduced. self-aligned A the of wafer measured that the of from maximum superior resistance method the GaAs MESFETs w o u l d be i m p l a n t MESFETs i f t h e was the those M o d e l i n g showed self-aligned to of the reducing the gates by evaporating circuit was fabricated a metal demonstrated. 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Pande, " S c h o t t k y C o n t a c t Barrier Height Modification by Ion Implantation of A l into GaAs," J . A p p l . P h y s . , V o l . 56, No. 6, p p . 1717-1721, (1984). 50. C. Canali, L. Umena, F. Fantinim A. Scorzoni, and E. Zanoni, "Increase i n Barrier Height o f Al/n-GaAs C o n t a c t s I n d u c e d b y H i g h C u r r e n t , " I E E E E l e c . Dev. Lett., EDL-7, No.5, p p . 291-293, ( 1 9 8 6 ) . 51. L . J . Van d e r Pauw, "A Method f o r Measuring R e s i s t i v i t y and H a l l E f f e c t o f D i s k s o f A r b i t r a r y P h i l . R e s . Rep., V o l . 13, No. 1, p p . 1-9, (1958). for No. CV 9, "Doping Dependence Ti-Pt Contacts to 5, pp. 1832-1833, Specific Shape," 76 52. M. Murakami a n d W.H. Price, "Thermally Stable, R e s i s t a n c e N i l n W Ohmic C o n t a c t s t o n-Type GaAs," P h y s . L e t t . , V o l . 51, No. 9, p p . 664-666, ( 1 9 8 7 ) . Low Appl. 53. P.L. Hower a n d N. G. Bechtel, "Current S a t u r a t i o n and S m a l l - S i g n a l C h a r a c t e r i s t i c s o f GaAs FETs," IEEE Trans. E l e c . Dev., V o l . ED-32, No. 5, p p . 213-220, ( 1 9 7 3 ) . 54. H. F u k u i , " D e t e r m i a t i o n o f t h e B a s i c D e v i c e P a r a m e t e r s a GaAs MESFET," B e l l S y s t . Tech. J . , V o l . 58, No. pp. 711-797, ( 1 9 7 9 ) . 55. S. C h a u d h u r i a n d M. Das, "On t h e D e t e r m i n a t i o n o f Source and D r a i n S e r i e s R e s i s t a n c e s o f MESFETs," I E E E E l e c . Dev. L e t t . , EDL-5, p p . 244-246, ( 1 9 8 4 ) . 56. K.W. L e e , M. S h u r , A. V a l o i s , G. R o b i n s o n , X. Zhu, and A. V a n d e r Z i e l , "A New T e c h n i q u e f o r C h a r a c t e r i z a t i o n o f t h e End R e s i s t a n c e i n Modulation-Doped FETs," IEEE Trans. E l e c . Dev., V o l . ED-31, No. 10, p p . 1294-1398, ( 1 9 8 4 ) . 57. P.H. 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APPENDIX A - F a b r i c a t i o n P r o c e d u r e The d e t a i l s listed of the developed fabrication process are as f o l l o w s : 1) Scribe 3 i n c h wafer. 2) Degrease i n boiling acetone followed by rinse in b o i l i n g methanol and blow d r y . 3) GaAs e t c h i n 8 : 1 : 1 / H S 0 : H 0 : H 0 f o r 2m45s 2 3pm o f GaAs f r o m w a f e r 4) Rinse 4 2 2 2 - removes surface. i n D e - I o n i z e d (D.I.) H 0 2 cascade f o r 4min and blow d r y . 5) Cleave wafer i n t o 6) Oxide etch 7) Plasma d e p o s i t i) NH i n 10% NH OH f o r 15s a n d b l o w d r y . 4 nitride. Parameters: Temp: 3 Pressure: ii) silicon plasma p r e c l e a n . 3 Gas: NH NH quarters. 500mTorr Power: F l o w : 42.5sccm/min 3 Silicon nitride G a s e s : He, S i H , 4 Pressure: Time: deposition. NH 1500mTorr Power: He F l o w : 500sccm/min SiH NH 8) Spin 3 Flow: 4 Flow: Time: lmin 300°C 100W/500cm 2 4min 42.5sccm/min on S h i p l e y S o f t bake 2 540sccm/min 1400-30 p h o t o r e s i s t 30s. 9) l00W/500cm Parameters: Temp: 3 300°C a t 95°C f o r 25min. 78 (PR) a t 4700rpm f o r 79 10) Expose under registration mask #1 a t 25mW/cm 11) P o s t e x p o s u r e b a k e a t 95°C 12) Develop 13) R i n s e i n D.I. H 0 14) Remove n i t r i d e f o r 45s. 2 f o r 20min. i n MF312 d e v e l o p e r f o r 5 0 s . cascade 2 f o r l m i n and blow d r y . from r e g i s t r a t i o n marks i n Buffered HF f o r 30s. 15) R i n s e i n D.I. H 0 cascade f o r lOmin 16) Etch registration marks i n 5:2:240/NH OH:H O :H 2 and blow d r y . 4 2 2 0 2 for 50s. 17) R i n s e i n D.I. H 0 18) Remove cascade 2 PR methanol 19) ..24) in boiling f o r 4min a n d b l o w d r y . acetone followed by boiling and blow d r y . Pattern f o r i m p l a n t w i t h n " mask #2 same a s steps 8-13. 25) Channel implant 29 Parameters: Species: Energy: 12 . Si Dose: 2.0 - 3.0x10 90 - 125 KeV 26) Remove p h o t o r e s i s t 27) R i n s e i n D.I. H 0 28) Thicken s i l i c o n 29) F u r n a c e a n n e a l c h a n n e l i m p l a n t a t 850°C 30) Remove s i l i c o n cascade 2 i) With i n 80°C microstrip. f o r 4min. a n d b l o w d r y . n i t r i d e a s i n 7) (time=2min). f o r 25min. nitride. B u f f e r e d HF f o r 7min a n d lOmin D.I. cascade rinse. ii) CF 4 plasma. Parameters: Gas: CF Temp: 4 Pressure: 300mTorr Power: CF. 140sccm/min Time: Flow: 100°C 100W/500cm 2min 2 80 A 31) Light etch i n l:l:240/NH OH:H O :H O f o r 3sec. 32) D.I. r i n s e f o r 4min i n c a s c a d e 33) Oxide e t c h i n 10% NH OH f o r 15s a n d b l o w d r y . 'T' g a t e ion 4 structure with suitable using S p u t t e r TiW r e f r a c t o r y g a t e Parameters: 2 bath. undercut steps f o r self-aligned 34)..43) : metal. B i a s s p u t t e r mode Gas: Argon Pressure: Patterning 2 4 i m p l a n t a t i o n was o b t a i n e d 34) 2 Power: 2 00W/180cm 2 0mTorr o f l^m l i n e s was a c h i e v e d T i m e : 2 0min using steps 35)..40) 35) Spin 36) S o f t b a k e a t 7 0 ° C f o r 25min a n d a l l o w t o c o o l . 37) Soak i n c h l o r o b e n z e n e f o r 7min a n d b l o w d r y . 38) E x p o s e u n d e r TiW dummy g a t e mask #3 a t 25mW/cm 39) D e v e l o p i n MF-312 d e v e l o p e r f o r 60s. 40) Rinse 41) Evaporate 42) Liftoff o n S h i p l e y 1400-30 p h o t o r e s i s t a t 4700rpm f o r 3 5 s . f o r 45s. and blow d r y . 5000A A l . metal i nboiling Parameters: acetone followed by boiling and blow d r y . Undercut e t c h i n CF 4 plasma. Gas: CF CF Flow: 4 Pattern f o r n + Temp: 4 Pressure: 44) ..49) 2 i n DI w a t e r c a s c a d e f o r l m i n . methanol r i n s e 43) 2 300mTorr Power: 140sccm/min implant with Time: 100°C 100W/500cm 2 15min mask #4 a s s t e p s 8 - 1 3 . 81 50) Source/drain implant. Parameters: Species: Energy: 51) Remove p h o t o r e s i s t 52) Rinse 53) Remove A l dummy g a t e s 54) Rinse 55) Anneal i n D.I. i n D.I. in Si Dose: 1.0 - 2 . 0 x l 0 i n 80°C H 0 cascade 2 microstrip. f o r 4min. a n d b l o w d r y . i n 50% H P 0 3 H 0 cascade 2 a t 5 5 ° C f o r 2min. f o r 4min. a n d b l o w d r y . f o r 5s o v e r l a y e r o n t h e TiW g a t e s was e v a p o r a t e d T h e s e s t e p s were a c t u a l l y i nthe fabrication. t o A l a s was u s e d (capless i n proximity). c o m p l e t i o n o f t h e d e v i c e s b u t would point 4 s o u r c e / d r a i n i n RTA a t 950 ° C steps 56)..67). 1 3 130 - 150 KeV a n n e a l w i t h GaAs w a f e r A metal 2 9 be as described performed better done after at this E v a p o r a t i n g Pd/Au w o u l d b e p r e f e r r e d here. 56) S p i n o n S h i p l e y 1400-30 p h o t o r e s i s t 57) S o f t b a k e a t 9 5 ° C f o r 25min. 58) Hardbake i ) ramp o v e n f r o m a t 4700rpm f o r 3 0 s . 140 ° C to 150 °C over 20min. ii) 59) l e t c o o l t o 120°C o v e r Planarization etch i n 0 Parameters: Gas: 0 2 0 60) ..65) Evaporate Temp: 3 00mTorr F l o w : 2 00sccm/min P a t t e r n second TiW 66) 2 plasma. 2 Pressure: level 20min. of resist Power: 100W/500cm Time: 60min for liftoff dummy g a t e mask #8 a s i n s t e p s 5000A" A l . 100°C 35-40. using 2 82 67) Liftoff metal i n boiling methanol r i n s e 68) ..73) Pattern acetone followed by boiling and blow d r y . f o rl i f t o f f w i t h o h m i c mask #5 a s i n s t e p s 35-40. 74) E v a p o r a t e 2 000A AuGe t h e n 300& N i . 75) Liftoff metal i n boiling acetone followed by boiling methanol r i n s e and blow d r y . 76) Alloy 77) Test ohmic c o n t a c t s FETs. Steps 7 8 ) . . I l l ) dielectric 78) i n f u r n a c e a t 4 2 5 ° C f o r 2min. were f o r formation of the silicon nitride l a y e r a n d t h e MIM t o p p l a t e . Plasma d e p o s i t Parameters: silicon nitride. G a s e s : He, S i H Pressure: 4 , NH Temp: 3 0 0 ° C 3 1500mTorr Power: He F l o w : 500sccm/min SiH NH 3 4 F l o w : 42.5sccm/min S p i n on W a y c o a t HRN 200 n e g a t i v e 80) S o f t b a k e a t 6 0 ° C f o r 20min. 81) E x p o s e a t 25mW/cm 82) Develop i n xylene 83) Rinse 84) Etch n i t r i d e 85) Rinse 86) Remove p h o t o r e s i s t i n isopropyl photoresist. f o r 10s. f o r 90s. alcohol i n HF t o l e a v e and blow d r y . islands i n D.I. water cascade bath boiling T i m e : 8min F l o w : 540sccm/min 79) 2 100W/500cm in methanol r i n s e boiling a t MIM sites. f o r lOmin. acetone and blow d r y . followed by 2 83 S t e p s 87-95 a r e n o t r e q u i r e d c o n t a c t s and 87)..92) selective Pattern steps 93) Oxide 94) Evaporate 95) Liftoff for Schottky diode implant gates. for liftoff using Schottky p l a t e t l as i n 35-40. e t c h i n 10% methanol f o r MIMs b u t NH 0H. 4 3000A o f T i / P d / A u metal in boiling rinse Schottky metal. acetone followed by boiling and b l o w d r y . A i r b r i d g e s were f a b r i c a t e d i n steps 96)..111). 96) S p i n on S h i p l e y 1400-30 p h o t o r e s i s t 97) S o f t b a k e a t 9 5 ° C f o r 25min. 98) Expose under 99) Develop S c h o t t k y mask #7 a t 4700rpm f o r 30s. a t 25mW/cm 2 f o r 45s. i n MF312 d e v e l o p e r f o r 50s. 100) R i n s e i n DI w a t e r 101) Hardbake cascade f o r l m i n . and b l o w d r y . i ) ramp o v e n f r o m 140 °C to 150 °C over 20min. ii) 102) ..107) l e t c o o l t o 12 0°C o v e r 2 0min. P a t t e r n second Au p l a t e mask #8 108) E v a p o r a t e Au 109) Liftoff methanol level of r e s i s t for liftoff using a s i n s t e p s 35-4 0. airbridges. metal rinse in boiling acetone f o l l o w e d by boiling and b l o w d r y . 110) Remove l o w e r l e v e l resist 111) R i n s e i n D.I. water 112) T e s t s a m p l e and h o l d i n hot cascade microstrip. f o r 4 min. amplifiers. and b l o w d r y . APPENDIX B - I n p u t L i s t i n g s B.l ! Touchstone f o r Modeling Input Lumped e l e m e n t model o f s e l f - a l i g n e d MESFET DIM FREQ GHZ RES OH IND NH CAP PF LNG M I L TIME PS COND /OH ANG DEG VAR G =» 0.0025 T =• 6 A/V) ( T Cl = 0.035 Gl « 1E-8 pF) A/V) R I •= 20 Ohms) C2 = 0.004 C3 - 0.004 C4 - 0.004 R4 - 4000 RS = 24 RG = 5 ps) <c d g pF) pF) (c d 6 pF) Ohms) (R. Ohms) ( o r RG = 0.63 f o r g a t e w i t h A l o r Au o v e r l a y e r ) 84 RD = 24 (Ohms) L=0 (nH) CKT SRL 4 2 R R D L=0 A SRL 3 1 R R G L=0 A FET2 3 4 0 G G T T F F C G S C 1 GGS G1 R I R 1 CDG C2 CDC C3 CDG C2 CDC C3 CDG C2 CDC C3 FET2 9 10 0 G G T T F F C G S C 1 GGS G1 R I R 1 CDG C2 CDC C3 A A A A A A A A + C D S C 4 RDS R4 R S R S A A A SRL 6 2 R R D L=0 A SRL 5 3 R R G L=0 A FET2 5 6 0 G G T T F F C G S C 1 GGS G1 R I R 1 A A A A A A A A + C D S C 4 RDS R4 R S R S A A A SRL 8 2 R R D L=0 A SRL 7 5 R R G L=0 A FET2 7 8 0 G G T T F F C G S C 1 GGS G1 R I R 1 A A A A A A A A + C D S C 4 RDS R4 R S R S A A A SRL 10 2 R R D L=0 A SRL 9 7 R R G L=0 A A A A A A A A A + C D S C 4 RDS R4 R S R S A A A SRL 12 2 R R D L=0 A SRL 11 9 R R G L=0 A FET2 11 12 0 G G T T F F C G S C 1 GGS G1 R I R 1 CDG C2 CDC C3 A + C D S C 4 RDS R4 A A A A A A A A A RS RS A SRL 14 2 R R D L=0 A SRL 13 11 R R G L=0 A FET2 13 14 0 G G T T F F C G S C 1 GGS G1 R I R 1 CDG C2 CDC C3 A + C D S C 4 RDS R4 A A A RS RS SRL 16 2 R R D L=0 A A A A A A A A SRL 15 13 R R G L=0 A FET2 15 16 0 G G T T F F C G S C 1 GGS G1 R I R 1 C D G C 2 A + C D S C 4 RDS R4 A A A A A A A CDC C3 A RS RS A A SRL 18 2 R R D L=0 A SRL 17 15 R R G L=0 A FET2 17 18 0 G G A + C D S C 4 RDS R4 A A DEF2P 1 2 T T F F C G S C 1 GGS G1 R I R 1 C D G C 2 A A A RS RS A TRA OUT TRA DB[S21] GR1 TRA DB[S12] GR2 TRA DB[GMAX] J TRA SB1 TRA Sll TRA S22 ! TRA SB2 FREQ SWEEP 2 40 2 RANGE 2 40 2 GRID GR1 -2 8 1 GR2 -40 0 4 GR3 0 20 2 GR3 A A A CDC C3 A 87 B.2 Spice Input Sample a n d h o l d - t e s t c o n d i t i o n s *Cycle Controls .OPTIONS ITL4=1000 ITL5=0 LIMPTS=2000 NOPAGE .WIDTH OUT=80 * •Active Elements * •Sampling Switch BSWI 10 20 3 RSAG12 60 * * F i x e d H o l d Node Capacitance CHOLD 3 0 13OFF * •Amplifier BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU 2 4 6 RSAG12 90 Dl 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 •Standard A c t i v e Element Models •model i s f o r 1 um s l i c e o f MESFET o r DIODE * .MODEL RSAG12 GASFET(VT0=-1.7, VBI=1.23, RG=1, + BETA=9E-5, LAMBDA=0.055, CGS0=1.0FF, + IS=2.0E-15, RD=600, RS=600, ALPHA=2.3, CGD=0.1FF, CDS=0.05 TAU=3.0PS) * .MODEL TD4 D(IS=1.24E-14, RS=1300, + VJ=0.72, EG=1.42, N=1.2, TT=2PS, CJ0=8.0E BV=8, I B V = l E - 3 ) * •Independent VDD 2 0 DC VSS 1 0 DC VIN Sources 5.25 -2.25 10 0 S I N ( - 0 . 6 5 0.32 36MEGHZ) VCTRL 20 0 P U L S E ( - 3 . 0 -1.9 700PS 700PS 700PS 700PS 3700PS) •Transient Analysis •.TRAN .TRAN Parameters T S T E P TSTOP <TSTART TMAX UIO 100PS 50NS * •Output Parameters .PRINT DC V ( 1 0 ) V ( 3 ) V ( 5 ) .PRINT TRAN V ( 1 0 ) V ( 2 0 ) V ( 3 ) V ( 5 ) .END 89 Sample a n d h o l d *Cycle - ultimate performance Controls .OPTIONS ITL4=1000 ITL5=0 L I M P T S = 2 0 0 0 .WIDTH NOPAGE OUT=80 * •Active Elements •Sampling Switch BSWI 10 20 3 RSAG12 60 * • F i x e d H o l d Node Capacitance CHOLD 3 0 13OFF * •Amplifier BIN 4 3 0 RSAG12 67 BFB 4 5 0 RSAG12 23 BLPU 2 4 4 RSAG12 45 BPU DI 2 4 6 RSAG12 90 6 7 TD4 66 D2 7 8 TD4 66 D3 8 5 TD4 66 BPD 5 1 1 RSAG12 90 * •Standard •model * A c t i v e Element i s f o r 1 um s l i c e Models o f MESFET o r DIODE 90 .MODEL RSAG12 GASFET(VTO=-l.7, VBI=1.23, RG=0.1, ALPHA=2.3, + BETA=9E-5, LAMBDA=0.055, CGS0=1.0FF, CGD=0.1FF, + IS=2.0E-15, RD=600, RS=600, CDS=0.05FF, TAU=3.0PS) * .MODEL TD4 D(IS=1.24E-14, RS=1300, N=1.2, TT=2PS, CJO=8.0E-15, + VJ=0.72, EG=1.42, BV=8, I B V = l E - 3 ) * •Independent VDD 2 0 DC Sources 5.25 VSS 1 0 DC -2.25 VIN 10 0 S I N ( - 0 . 6 5 0.32 360MEGHZ) VCTRL 20 0 P U L S E ( - 3 . 0 -2.9 70PS 20PS 20PS 20PS 370PS) * •Transient Analysis .TRAN 10PS Parameters 5NS * •Output Parameters .PRINT DC V ( 1 0 ) V ( 3 ) V ( 5 ) .PRINT TRAN V ( 1 0 ) V ( 2 0 ) V ( 3 ) V ( 5 ) .END APPENDIX C - M i c r o w a v e G a i n Definitions out Input matching netwo *< Output matching network Mtsm r Figure The scattering ou t gains C.l. ( o r power parameters gain block ratios) CI diagram. are related to the o f t h e MESFET b y [ 7 0 ] : Transducer power gain in 50-ohm system Transducer power gain for arbitrary T and T c Power 50 L Power gain with input conjugate matched G = \S \ T 2 [C.l] 2I 0-l ci )|s | 0-ir | ) r l J l 2 1 l(i - s „ r ) ( i 2 12 |s | (i-|r | ) J t |i-s 2rj(i-|5;,| ) l^.l (>-|r j') c c J l |5 ,[ 2 2 1-|S | 2 22 (forr = 0) c 91 [C.3] J = |»-S„r | (l-|5„| ) L n 2 J 2l i-|5 | (for 1^ = 0) : c n 21 2 Available power gain with output conjugate matched L |s | J 21 [C.2] -s T )-s s r r \ c G= t [C.4] 92 |5 ,t (<-ircl )(i-|rj ) 2 : Unilateral transducer power gain 2 2 11 — S r | ! 1 — S ^ r j ™ Maximum unilateral transducer power gain _ n _ O TUm»» c : 2 L |S;i| (l — | S | ) ( l — | S | ) J 2 3 [C-6] 2 M 2J [C.7] Maximum available power gain 5 Maximum stable power gain {k-jiS-\) _ |S il |s | .. _ 2 ' |2 where k i s t h e s t a b i l i t y factor 1 -1S,,| -|S | 2 2 : : -! as given by: + 1A|\ , 2 |S S | 12 " > forstability ! 21 [C.9] here |A| = | S S n and r and can be r e l a t e d c and r 2 2 t - S, S 2 2 1 | [ C I O ] a r e t h e s o u r c e and l o a d reflection coefficients t o impedances by: r c = Z ~ c z C r - Z ° z +z l [C.ll] o ~ ° ^-zTTT z tc.i2]
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Self-aligned gallium arsenide MESFETs for microwave integrated circuits Sutherland, David B. 1988
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Title | Self-aligned gallium arsenide MESFETs for microwave integrated circuits |
Creator |
Sutherland, David B. |
Publisher | University of British Columbia |
Date Issued | 1988 |
Description | A refractory self-aligned gate fabrication process for gallium arsenide MESFETs has been developed and applied to a sample and hold circuit. The process has been shown to reduce the parasitic end resistance of MESFETs which can be a limiting factor in their microwave performance. A mask set was designed to be compatible with Cascade Inc. probes which allowed on chip microwave measurements to be made. Usable gain was measured up to 18GHz on FETs and 5GHz on buffer amplifiers with the microwave probes at the Communications Research Centre in Ottawa Ontario. The microwave probes were also used to test sample and hold operation. The maximum tested sampling rate was limited by the test equipment to 250 MHz. The fabrication process included a plasma etch for producing an undercut 'T' gate structure for self-aligned ion implantation. A method of sputtering a thermally stable alloy of TiW refractory metal was developed to provide suitable Schottky contacts to GaAs. It was found that a rapid thermal anneal following the self-aligned implant maintained suitable TiW/GaAs Schottky characteristics and yielded MESFETs with reduced end resistance when compared to those fabricated by the more conventional selective implant process. A technique was developed to reduce the gate resistance of self-aligned MESFETs using an evaporated metal overlayer. Also, procedures for fabricating airbridges using a single evaporation and Metal-Insulator-Metal (MIM) capacitors using silicon nitride as the dielectric were developed. The effect of gate resistance on the microwave performance of the self-aligned MESFETs was investigated by modeling with the EEsof Inc. microwave software package, Touchstone. The modeling showed that self-aligned MESFETs are capable of giving greater high frequency gain than are selective implant devices with the same design geometry. The operation of the sample and hold circuit was simulated using a version of SPICE that included the Sussman Fort GaAs MESFET model. The simulations showed that the sample and hold could be used for gigahertz sampling. |
Subject |
Microwave circuits -- Design and construction |
Genre |
Thesis/Dissertation |
Type |
Text |
Language | eng |
Date Available | 2010-09-16 |
Provider | Vancouver : University of British Columbia Library |
Rights | For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use. |
IsShownAt | 10.14288/1.0097924 |
URI | http://hdl.handle.net/2429/28522 |
Degree |
Master of Applied Science - MASc |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
Campus |
UBCV |
Scholarly Level | Graduate |
AggregatedSourceRepository | DSpace |
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