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FET upconverter design using load dependent mixing transconductance Lord, Joseph Louis Martin 1988

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F E T U P C O N V E R T E R DESIGN USING L O A D D E P E N D E N T MIXING T R A N S C O N D U C T A N C E by J O S E P H L O U I S M A R T I N L O R D B . Eng. (Honours), M c G i l l University, 1984 A THESIS S U B M I T T E D I N P A R T I A L F U L F I L L M E N T O F T H E R E Q U I R E M E N T S F O R T H E D E G R E E O F M A S T E R O F A P P L I E D S C I E N C E in T H E F A C U L T Y O F G R A D U A T E S T U D I E S (Department of Electrical Engineering) We accept this thesis as conforming to the required standard T H E U N I V E R S I T Y O F B R I T I S H C O L U M B I A M a y 1988 ©J. L . Martin Lord , 1988 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department The University of British Columbia Vancouver, Canada Date ^ | ^ P ) ( . f t f t DE-6 (2/88) A B S T R A C T The conversion gain of GaAs M E S F E T mixers is known to be dependent on the impedances seen by the applied signals and the resulting mixing products at all ports of the device. For an accurate representation, all these loading conditions should be con-sidered; however, the design of gate and drain networks then becomes rather difficult. A s a result, no sufficiently accurate and yet usable design procedures exist for M E S F E T mixers; instead, a few simple rules involving short- and open-circuit terminations have been given by various authors. Unfortunately, these rules are often inappropriate, partic-ularly in upconverter applications. In this thesis, the conversion efficiency dependence on the drain loading at the local oscillator frequency has been studied for a gate upconverter; the local oscillator signal is by far the most dominant in terms of its influence on mixer performance. It has been found that the conversion gain can significantly deteriorate for a narrow range of load values. In addition, the local oscillator drain termination resulting in highest gain has been found to be generally different from the short-circuit recommended in the literature. Based on these findings, a novel F E T upconverter design procedure has been developed that incorporates the local oscillator loading phenomenon in the F E T equivalent circuit by means of a load dependent mixing transconductance. It allows the optimization of the drain network for an acceptable match at the selected sideband and desired local oscillator rejection while avoiding impedance values in the local oscillator frequency range which would otherwise cause severe degradation in conversion gain. - i i -T A B L E O F C O N T E N T S Page A B S T R A C T i i T A B L E O F C O N T E N T S i i i L I S T O F S Y M B O L S A N D A C R O N Y M S v L I S T O F T A B L E S v i L I S T O F F I G U R E S v i i A C K N O W L E D G E M E N T S ix C H A P T E R 1: I N T R O D U C T I O N 1 C H A P T E R 2: B A S I C A S S U M P T I O N S A N D C O N S T R A I N T S 5 C H A P T E R 3: D E S C R I P T I O N O F T H E M E T H O D 10 3.1 Conversion gain measurements 10 3.1.1 Broadband 50 Q termination 10 3.1.2 L O reflection 16 3.2 Proposed model 20 3.2.1 Equivalent circuits 20 3.2.2 Nonlinearity expression 23 3.3 Determining the mixing transconductance 28 3.4 Method summary 32 C H A P T E R 4: A C C U R A C Y O F T H E M E T H O D A N D ITS P H Y S I C A L F O U N D A T I O N : D I S C U S S I O N 34 4.1 Additional experimental details 34 - i i i -4.2 Element acquisition and accuracy enhancement 36 4.3 Simulation details and accuracy 43 4.4 Physical l ink between the L O voltages and conversion efficiency 51 4.4.1 Circuit - voltages relation 52 4.4.2 Transconductance - voltages interaction 53 C H A P T E R 5: A P P L I C A T I O N S O F T H E M E T H O D 58 5.1 Drain network synthesis 58 5.2 Additional considerations in using the method 62 5.3 Dual-gate F E T 64 C H A P T E R 6: C O N C L U S I O N 72 R E F E R E N C E S 73 A P P E N D I X A : T H E C L A S S I C A L M I X E R T H E O R Y 75 A P P E N D I X B : H I G H F R E Q U E N C Y S I M U L A T I O N I M P R O V E M E N T 81 A P P E N D I X C: L I S T I N G O F P R O G R A M T O C A L C U L A T E T H E B E S T D A T A FIT 84 A P P E N D D C D : E Q U I V A L E N T C I R C U I T E L E M E N T A C Q U I S I T I O N W I T H T O U C H S T O N E 87 A P P E N D I X E : C O N V E R S I O N G A I N S I M U L A T I O N S F O R S A M P L E 3 91 A P P E N D I X F: F R E Q U E N C Y R E S P O N S E O F L O V O L T A G E S F O R T = 1 100 A P P E N D I X G : D E R I V A T I O N OF M I X I N G T R A N S C O N D U C T A N C E E X P R E S S I O N F R O M A L I N E A R M O D E L 107 A P P E N D I X H : U P C O N V E R T E R S I M U L A T I O N W I T H T O U C H S T O N E 110 - iv -LIST O F S Y M B O L S AND A C R O N Y M S L O Loca l Oscillator IF Intermediate Frequency R F Radio Frequency U S B Upper SideBand L S B Lower SideBand SSB Single SideBand IP3 Third order output intercept point, d B m F O M Figure O f Merit , dB C G Conversion Gain, dB C G m a x . Conversion gain maximum, dB CGmin : Conversion gain minimum, dB A C G '• C G m a x - CGmin, dB VGG Gate bias, V ^GGmax • Gate bias yielding maximum conversion gain, V ^GGopt Gate bias yielding "optimum" conversion gain, V vDD Drain bias, V Pinch-off voltage, V Voltage magnitude across Cgs, V VRds Voltage magnitude across Rds, V A\ | / Phase of VCgs - phase of VRds , degrees IDS D C drain to source current, A r Magnitude of L O drain reflection coefficient 0 Angle of L O drain reflection coefficient, degrees ®min Angle of reflection coefficient at conversion gain minimum 0 Angle of reflection coefficient at conversion gain maximum O Electrical length of drain transmission line, degrees RL Load resistance of drain reflection circuit, O gmMIX M i x i n g transconductance, mS gm Linear small-signal transconductance, mS Cgs Gate to source capacitance, pF Rds Drain to source resistance, Q. C g d Drain to gate capacitance, pF Rs Source resistance, Q. L s Source inductance, n H cc,Ti, p Coefficients of mixing transconductance function T, E , G Exponents of mixing transconductance function R L Return Loss, dB Q Quality factor F Frequency - V -LIST O F T A B L E S T A B L E Page I : Measured and calculated output/input mapping 38 II : Typical F E T equivalent circuit element values 40 I I I : Upconverter data for several samples for FIF = 70 M H z 45 - v i -LIST O F FIGURES F I G U R E Page 1: VGG and circuit performance -vs- L O power at 1.52 G H z 12 2: "Optimum" circuit performance -vs- L O power at 1.52 G H z 14 3: Conversion gain -vs- frequency for "optimum" conditions 16 4: L O reflection measurement setup 17 5: Typical C G -vs- L O reflection coefficient at 1.46 G H z 19 6: Typical large-signal S parameters 21 7: Complete packaged F E T equivalent circuit 24 8: L O reflection circuit 25 9: Typical L O voltages at 1.39 G H z for T = 0.8 26 10: RF/1F equivalent circuit 29 11: Typical simulation results at 1.46 G H z for T = 0.8 31 12: A C G and F O M -vs- L O power at 1.5 G H z 35 13: Experimental output/input mapping at 2.03 G H z for Y = 0.8 38 14: Simplified F E T equivalent circuit 40 15: L O voltages for T = 1 at 10 G H z 41 16: Large-signal S parameter measurement diagrams 42 17: C G -vs- L O reflection coefficient for sample 3 47 18: C G -vs- L O reflection coefficient including uncertainty 50 19: Typical D C characteristics of NE70083 54 20: Matching network 1 59 - v i i -21: C G -vs- frequency with network 1 60 22: Matching network 2 61 23: C G and R L -vs- frequency with network 2 61 24: Dual-gate F E T equivalent circuit 66 25: C G -vs- L O reflection coefficient at 1.5 G H z with T = .83 67 26: Dual-gate F E T L O reflection circuit 68 27: L O voltages-vs-reflection coefficient at 1.5 G H z with T = 1 69 A . l : Nonlinear F E T equivalent circuit 75 A . 2 : F E T equivalent circuit with element harmonics 77 A . 3 : Conversion equations and diagram 78 A . 4 : Conversion equations circuit representation 79 A . 5 : L S B / U S B interaction 79 A . 6 : Second L O harmonic effects 80 A . 7: Approximations of this method 80 B . 1: Modified RF/ IF circuit for arbitrary loadings 83 E : Conversion Gain Simulations for Sample 3 91 F: Frequency Response of L O Voltages for T = 1 100 - v i i i -A C K N O W L E D G E M E N T S I would first like to thank my supervisor Dr. Lawrence Young. His financial help at the early stage of my studies coupled with many informative discussions and the interest he showed throughout contributed significandy to the success of this project. I am also very appreciative of my co-supervisor Dr. Josef Fikart's direction and support during this work. His patience, poise, and insight into problems were particularly stimulating. I would like to thank M P R Ltd 's management for giving me access to their excellent facilities. In particular, I am indebted to all members of the microwave group for their cooperativeness during this project. A special mention for M r . Ettore Minkus whose M E S F E T characterization techniques were particularly relevant to the experimental aspects of the project. Many thanks to Miss Wendy Taylor for her moral and technical contributions in the production of this document. I am very grateful to the British Columbia Science Council which funded this work. Last but not least, Vancouver and its wonderful setting provided the stimulating environment that has made this work possible. - ix -CHAPTER 1: INTRODUCTION The first GaAs M E S F E T mixer results were reported in 1973 by Sitch & Robson [1]. Since then, a good deal of research has been conducted on their application in various frequency conversion circuits. The understanding of this device has evolved to the point where fairly sophisticated models now yield good prediction accuracy of its nonlinear circuit behavior. Compared to the more popular GaAs Schottky-barrier diode, FETs offer conversion gain and better saturation characteristics, both of which are obtained with much simpler circuit configurations and lower L O drive. Their principal disadvantage is the relatively poor noise figures that they show under large-signal operation. However, since our interest is to study M E S F E T s as upconverters, the noise figure is not of particu-lar importance. To quote state-of-the-art performance of both devices, Maas [2] has obtained, for an X band mixer with low IF (30 M H z range), single sideband noise figures of 4 to 5 dB , conversion gains of 6 to 10 dB, and third-order output intercept point of 20 d B m , for 6 to 10 d B m of L O power. A good GaAs Schottky-barrier diode balanced mixer typically has 5 to 9 dB of conversion loss, L O power requirements of 8 to 18 dBm, and third-order output intercept point of 0 to 13 dBm, with a lower bound for the noise figure of about 3.5 dB. The drive behind this work originates from F E T mixer experiments conducted at M P R . The conversion gain and the input/output impedances of gate upconverters were measured in a 50 Q. system at C band. Small-signal techniques were used to conjugate-match the gate at IF and the drain at R F . Normally, this would then yield a predictable value of conversion gain based on the original measurements. However, when - 1 -prototypes were built and tested, they had much lower conversion gain than expected. B y means of these results and various publications on this topic, it was concluded that the impedance seen by other signals present in the mixer, which had been neglected in the analysis, is also very important in determining conversion efficiency. So far, much of the research effort on M E S F E T mixers has concentrated on the conversion efficiency dependence on bias, input L O power, and in some cases, terminat-ing impedances at both ports for the various signal frequencies. Apart from the obvious input and output matching requirements, the general consensus is that only terminations at IF, R F , image (possibly), and L O frequencies need to be considered. For a gate down-converter, the trend is to short-circuit the IF at the gate and the R F and L O at the drain. Yet, given the major influence of the L O , the importance of its drain termination appears to have been somewhat underestimated. Since Harrop & Claasen's work identified the optimal L O impedance to be a short-circuit [3], little detailed supporting evidence for that particular result has been offered. More recently, Maas [2] justified that choice by stating that a "well-behaved" F E T transconductance mixer should always operate in the current saturation region with the smallest L O drain voltage variation; Camacho-Pefialosa & Aitchison [4] suggested that the conversion gain eventually drops as a func-tion of L O power when the L O drain termination is not a short-circuit because the F E T operates outside of the saturation region. To design a F E T mixer circuit, the frequency response of the embedding networks thus requires careful analysis. A t the input, the combining circuit must offer good match and signal isolation. A t the output, selected sideband match and L O rejection must be realized. Both circuits must also provide optimum terminations for the other signals. For - 2 -downconverters, where the IF and L O are quite far apart, the L O short-circuit at the drain appears to be a satisfactory and easily realizable approximation of optimum L O loading. For upconverters, the usual proximity of the R F and L O frequencies makes a simultane-ous realization of the above three requirements difficult, especially over a substantial L O / R F bandwidth. Furthermore, the experience gained with F E T upconverter measure-ments in this study revealed that the optimum L O loading at the drain is dependent on F E T parameters and operating frequency and thus not always identical to a short-circuit. In general, the conversion gain was fairly flat and LO-termination insensitive around the optimum impedance while a sharp dip of up to 20 dB occurred over a narrow range of impedance values. Therefore, avoiding the minimum region rather than maximizing gain should be the goal sought when designing F E T mixers. It is the aim of this work to contribute to more accurate M E S F E T upconverter design by thoroughly investigating the L O loading phenomenon and integrating the results into a design method. The approach taken relies on a combination of R F measurements and equivalent circuit representations with commercial frequency-domain C A D tools to create a simple but realistic mixer model simulating the L O dynamic loading, thereby allowing interactive circuit analysis and synthesis. Specifically, Touchstone and S P I C E w i l l be used as analysis tools in this work. The thesis is structured as follows: First, Chapter 2 outlines the basic philosophy of the design method, including the assumptions that w i l l be used throughout this work. Then, Chapter 3 describes the development of the method from basic theoretical concepts supported by corresponding experimental evidence and accompanied by actual results in a summary fashion. Chapter 4 provides more experimental, computational, and - 3 -simulation details and attempts a thorough investigation of the concepts involved. Chapter 5 then discusses some applications. - 4 -C H A P T E R 2: BASIC ASSUMPTIONS AND CONSTRAINTS In the context of accuracy enhancement due to proper L O loading characterization, the principal thrust of this design method is to simplify data acquisition procedures and modelling steps by using standard microwave measurements and suitable equivalent cir-cuits. When dealing with nonlinear components, the accuracy and repeatability afforded by a design method are important concerns. Yet, the complexity of many of the available modelling techniques considered accurate enough makes the characterization of a large number of samples, necessary for any scale of production, rather unrealistic. For practi-cal circuit design, the methods introduced by Curtice [5] and a few others [6,7,8] could be considered, but they normally deal with the nonlinearities by means of analytical expressions with their parameters fitted to D C data, the pertinence of which at microwave frequencies is not assured. The time-domain models require iterative techniques for their solution which make them involved computationally. The package of the F E T must also be thoroughly characterized, since these methods usually apply best to chip devices. Given a good qualitative understanding of the device/circuit interaction, it is possible to restrict the F E T to its most efficient operational mode. Our efforts are aimed toward realizing a "pure" transconductance mixer, since it usually yields maximum linearity con-sistent with good conversion efficiency. This choice can result in a simpler but more res-trictive model. In addition, a relaxation of the mixer's sensitivity to the test environment is required. Specifically, the conversion efficiency of a F E T gate mixer w i l l normally be - 5 -affected by the device/drain circuit interaction not only at the L O frequency (which is the < object of this study) but also at the L O harmonics. Separate control of these two effects is almost impossible for realistic microwave measurements. However, i f the mixer is made weakly nonlinear by restricting the L O pumping effect and consequently reducing the harmonics level, the problem is considerably simplified. The resulting trade-offs in performance are necessary to achieve the goals of predictability and repeatability. Wi th this condition enforced, the effect of the second and third L O harmonics (the most influential ones) is neglected experimentally and analytically. Likewise, al l the side-band terminations other than the upper sideband, on which we concentrate in this work, are neglected. This is common to most mixer analyses. Hence, only the IF, R F and L O signals concern us here. Since the other signals present in the mixer are of much lower amplitude than the L O , they can be treated with the standard small-signal techniques. This design method thus reflects the main philosophy of the classical mixer theory where both large-signal and small-signal solutions are featured. A t this point, it is worth discussing briefly the paral-lel between the classical theory and this approach. The mechanisms of the classical mixer theory and relevant details of its application are described in Appendix A . Maas [2] is a good reference for its adaptation to F E T mixers. The classical theory relies on equivalent circuits and splits a mixer problem into large-signal time-domain and small-signal frequency-domain solutions. This formulation is based on the common situation where the L O pumps the device and thus actually sets the operating conditions. A l l the other signals present are considered as small perturba-- 6 -tions superimposed on the L O swing and do not contribute to the pumping. Hence, the application of the theory is limited to cases where all the signals involved have small amplitudes. First, a nonlinear circuit model of the F E T must be devised where each nonlinear ele-ment is expressed as a function of selected voltages of the device. The large-signal prob-lem then consists in solving for the controlling voltages, given amplitude and frequency of the source and the F E T embedding impedances. Currently, the most popular solution technique is the Harmonic Balance method: it separates the network into linear (frequency-domain) and nonlinear (time-domain) parts and attempts a simultaneous solu-tion of their I /V equations. The voltage waveforms allow the calculation of the nonlinear elements' time dependence; after Fourier analysis, an equivalent circuit is constructed where the harmonics are represented as voltage-controlled current or voltage sources. The resulting linear circuit is now processed to calculate the conversion matrix. This matrix can be represented by impedances, in which case its calculation is similar to the common Z parameters but with the difference that several frequencies are involved. In practice, the number of harmonics of the elements' spectra is restricted. Al so , as men-tioned in Chapter 1, extensive simulations by researchers have allowed further simplifications of the matrix by neglecting sidebands and signals other than the IF, R F and the image. The matrix is dependent both on the signal frequencies and terminations and on the values of the elements' harmonics, which relate it to the pumping solution. Wi th the latter being a function of the embedding impedances and L O frequency, the matrix must be recalculated every time these are changed. On the other hand, i f the pumping solution - 7 -is obtained over a bandwidth for a series of different loadings, then the elements' har-monics are characterized within these ranges and the matrix becomes only signal-frequency and -termination dependent: any IF /RF pair can be used as long as the L O variables are kept in the ranges set. The convenience of frequency-domain analysis also allows the derivation of relatively simple analytical conversion gain expressions under certain assumptions [9]. The proposed method uses similar small-signal equivalent circuits to represent the conversion matrix but actually proceeds backwards. Instead of attributing a priori a specific time-domain function to the transconductance and calculating the resulting conversion characteristics, we use measured conversion characteristics to extract the function describing the transconductance factor involved in conversion, but in the fre-quency domain; the latter is possible due to the fact that we limit the analysis to the L O fundamental. In essence, the work described here is not so much concerned with different ways of manipulating the conversion matrix but rather with obtaining the matrix elements' depen-dence on the L O conditions in the circuit. This dependence is obtained from measure-ments rather than from a predefined mathematical description of the nonlinearities. Oth-erwise, the same approximations and limitations as in the classical theory prevail. A s an additional simplification, the reverse transfers (RF to IF) of the F E T mixer are neglected in our model due to the relatively low range of IF and R F frequencies commonly used. A s is shown in Figure A.7, this is the equivalent of setting four terms of the conversion matrix equal to zero. - 8 -When mixer operation at "higher" R F frequencies is sought ( "higher" is actually dependent on the specific transistor chosen), the accuracy of the model can be increased by a slight modification of the corresponding equivalent circuit to account for the degra-dation of the isolation between the gate and the drain. This improvement is described in Appendix B . In addition, the IF frequency used during a mixer simulation can also be varied and does not need to be fixed to the experimental value. Appendix B also shows how these variations can be easily implemented in the model. - 9 -C H A P T E R 3: DESCRIPTION O F T H E M E T H O D 3.1 Conversion gain measurements The characterization is performed on several N E C NE70083 single-gate transistors from two separate batches (#1, #2) at room temperature (25 °C). The device has a 0.5 |i.m gate length and a typical pinch-off voltage (V^) of -0.9 V . The transconductance mixing mode requires that both IF and L O be fed to the gate, with the output (RF) taken at the drain. We are considering an upconverter whose gate is fed from a broadband 50 Q. source. To realize the goals stated in Chapter 2, we utilize three degrees of freedom afforded by the F E T structure: the bias, the input L O power, and the port terminations. Vp is an additional parameter affecting the achievable conver-sion efficiency for a given L O level. Due to test components availability and other practical limitations, the test frequen-cies and power levels have been chosen as follows: IF : 70 M H z , -20 d B m L O : 1.39 - 2.03 G H z , 0 - 6 d B m R F : 1.46-2.1 G H z 3.1.1 Broadband 50 Q termination The bias and L O power are the two first parameters to be fixed. A broadband 50 Q. termination is connected at the drain for this purpose. The drain bias is fixed at 3.0 V , the device's standard value for operation in saturation. Optimization of this value never showed significant improvements. In accordance with the preceding discussion, both the - 10-gate bias and the L O power are set to their "optimum" values, meaning values providing the best compromise between conversion gain, third-order output intercept point, figure of merit, and the minimum output level of both the second and third L O harmonics. The harmonics are kept at below -20 dBc; the adjustment of the other parameters is subjec-tive. The figure of merit (FOM) is a quantity defined especially for this application. It rates the upconverter by the relative amount of R F (PRF) and L O (Pw) power present at its output (FOM =PRFIPL0), which directly determines the filtering necessary to achieve a desired L O rejection. The standard two-tone test (same as for the third-order intercept point measurement) is used to determine PRF, the output power of the upconverter for a third-order intermodulation distortion specification of -30 dB. The implications are obvi-ous. For instance, an upconverter generating +10 d B m of R F and 0 d B m of L O requires only 30 dB of filtering to achieve a rejection of 40 dB; with +10 d B m of L O , 40 dB of attenuation is necessary. 0 d B m L O power and a typical gate bias of -0.4 V (compared with -0.6 to -0.7 V for, maximum conversion gain) yield the "optimum" performance. Typically, a -2 dB conversion gain, a 6 d B m third-order output intercept point, and a -19 dB figure of merit were measured at 1.52 G H z . The small pinch-off voltage of the NE70083 allows a rea-sonable conversion gain at this low level, which in turn is attractive for measurement simplicity and subsystems considerations. F ig . 1 depicts some of this data for one sam-ple at 1.52 G H z . The gate bias, conversion gain, third-order output intercept point, and figure of merit are plotted against L O power for both "maximum" and "optimum" conversion gate biases. The gate biases have opposite slopes as the L O power increases: - 11 -Figure 1: and circuit performance -vs- L O power at 1.52 GHz -O.h -0.2 G a t e b i a s -0.4 -0.5 - • optimum ~Q maximum -0.6--0.74 2 3 4 LO power (dBm) Fig. 1-a: Gate bias -vs- LO power —i— - B -—I— - B -—I— -e-C -1\ G d B -34 -4 -5--• optimum -a maximum -64 2 3 4 LO power (dBm) Fig. 1-b: Broadband 50 Ohm CG -vs- LO power - 12-1 6 -13-for the "maximum" bias case, it gets closer to pinch-off; for the "optimum" bias case, it tends toward 0 V . A s can be seen, the maxima of the three circuit quantities do not necessarily coincide. In particular, for the "maximum" bias case, the figure of merit peaks at a lower L O power than its counterparts, but its slope is much smaller than for the "optimum" bias case; maxima of both conversion gain and third-order output inter-cept point appear simultaneously. For the "optimum" bias case, the maximum conver-sion gain occurs around 2-3 dBm, but the third-order output intercept point and figure of merit degrade quickly with L O power increase; however, at 0 dBm, they are only 2 and 5 dB below the "maximum" bias values, respectively, while the corresponding conver-sion gain is 3 dB worse. F ig . 2 shows the same quantities ("optimum" bias and 0 d B m L O power case) for several samples of batch 2. A good consistency is observed. The Figure 2: "Optimum" circuit performance -vs- L O power at 1.52 G H z 0 c G d B -4 -3 -2 -1 •A sample 4 + sample 5 -5-0 1 2 3 L O power (dBm) Fig. 2-a : Broadband 50 Ohm C G -vs- L O power 4 5 - 14-- • sample 1 - a sample 2 -o sample 3 - A sample 4 -v sample 5 2 3 L O power (dBm) Fig. 2-b: F O M -vs- L O power 0 1 2 3 4 5 L O power (dBm) Fig. 2-c: IP3 -vs- L O power - 15-"optimum" L O power choice thus depends on a somewhat subjective compromise between conversion gain and linearity. This does not affect the validity of the method outlined here as long as the harmonics levels are as stated above. F ig . 3 depicts the fre-quency response of several samples of the same batch for the "optimum" bias and L O power case. A s expected, a slight negative slope is present. Figure 3: Conversion gain -vs- frequency for "optimum" conditions C 1.00 1.25 1.50 1.75 2.00 RF frequency (GHz) 3.1.2 L O reflection The reflection measurements are now performed with the "optimum" gate bias and L O power. The experimental setup is shown in F ig . 4. This is a modified load-pull measurement: the phase of the reflection coefficient is variable at L O frequency while a good return loss is maintained at the selected sideband. The circuit works as follows: the bandpass filter is tuned for good return loss at R F and is narrowband enough to reflect - 16-HP 8350A LO signal generator MPD 1-3 GHz anpllfier HP 3200B 70 MHz IF source G-3 dB att. a . NARDA 5072 directional coupler ANATEK 6020 power, supply HP 4 2 8 B dc anneter 6 dB att. - | / \ / N A | — HP 8566B spectrun analyzer interdigital bandpass filter HP 11590B ^ bias T sliding short-circuit Figure 4: L O reflection measurement setup completely the L O which is 70 M H z away. The L O wave then travels to the third port of the circulator whose sliding short-circuit causes an additional delay before reflecting it back to the drain of the F E T . The full Smith chart can be spanned by varying the posi-tion of the stub. The magnitude of the L O reflection coefficient can be varied by insert-ing an attenuator between the sliding short and the circulator; its maximum is limited primarily by the circulator losses. Hence both the magnitude and the phase of the L O reflection coefficient can be varied (almost) independently. A n IF short-circuit is added at the drain; its presence eliminates IF impedance varia-tions inherent to the setup, but more importantly, it reduces considerably the direct con-tribution from the channel conductance. This is desirable to further enhance our "pure" transconductance mixing approximation. A s an intermediate step, the "narrowband" 50 Q conversion gain is measured by ter-minating the third port of the circulator in 50 Q. In general, it is slightly higher than the values obtained in Section 3.1.1 and shows little frequency dependence. A plot of the conversion gain as a function of the phase of the L O reflection coefficient with its magnitude as a parameter is shown in Fig . 5 for a typical case. It is similar to the results of Hirota & Ogawa [10]. Note the sharp dip at high magnitudes of the reflection coefficient (up to -8.5 dB) and the reasonably flat maximum (0 dB), some-what off the short-circuit point. The dip progressively decreases as the magnitude of the reflection coefficient does, and the whole curve eventually converges to the 50 Q "nar-rowband" conversion gain. Clearly, the dip region must be carefully avoided when designing any drain network for this mixer. - 18-Figure 5: Typical C G -vs- L O reflection coefficient at 1.46 G H z 3.2 Proposed model 3.2.1 Equivalent circuits A F E T model suitable for simulating the conversion efficiency dependence on this L O loading is now constructed. The first concerns are the choice of the equivalent cir-cuits and the acquisition of the value of their elements. A n extension of small-signal Scattering parameters measurement, now performed at the "optimum" L O power, enables the characterization of the device. This gives a kind of large-signal S parameters where both the input and output parameters are measured by feeding the respective ports with the same test signal level, as for regular small-signal measurements. The impedances obtained reflect some of the non-linearities of their vo l -tage dependence. Only small bias current variations were observed during the L O reflection experiments (= ± 7 % between maximum and minimum conversion gain, respectively), and for practical purposes, the resulting S parameters are essentially con-stant, consequently supporting our fixed element values approximation. This technique is rather crude, but the good accuracy we have obtained shows that it is sufficient for our purpose. One important aspect of microwave transistor measurement is deembedding the microstrip test fixture, whether chips or packaged devices are used. For the best accu-racy, a thorough characterization of the fixture is necessary to construct its equivalent cir-cuit. From the embedded S parameters and the fixture's model, the actual S parameters can be extracted. In practice, a good fixture can be considered essentially as a linear phase-shifting element. Given the time delays of the input and output lines which can be - 2 0 -calculated, the S parameters can be deembedded in real-time on the network analyzer. This has proven satisfactory for our purpose. Fig. 6 shows typical "large-signal" S parameters of the NE70083 measured accordingly with an HP8510A network Figure 6: Typical large-signal S parameters 1 •5 1 2 =r f l : 0.20000 f2: 5.00000 -21 -r - .5 0 1 - l -3 -2 f l : 0.20000 f2: 5.00000 analyzer. It appears that only \S2^ shows compression compared to its small-signal value, depicted simultaneously in Fig. 6-c. Generally, apart from compression, the fre-quency response of 5 2 I has sizeable fluctuations, and it needs to be smoothed out with filtering controls on the network analyzer to allow representation by an equivalent circuit. Wi th Touchstone and its circuit optimizer, the standard F E T small-signal equivalent circuit including package and chip parasitics, shown in F ig . 7, is fitted to the measured S parameters, and the values of its elements extracted. Wi th reference to the classical mixer theory, three separate equivalent circuits (for the L O , IF and R F signals) are con-structed using these element values. It appears that using large-signal element values for the IF and R F circuits is more accurate than using the small-signal ones: the low level IF and R F signals essentially see the impedances created by the wide L O swing in an aver-age sense. For example, this approximation is found in [9]. Thus, the L O circuit herein obtained reflects the pumping mechanism, while the com-bination of the IF and R F circuits allows a representation of the conversion matrix. Indeed, we are actually seeking to model the dependence of the elements of this matrix on the L O pumping. 3.2.2 Nonlineari ty expression Based on the experimental conditions we have enforced, we postulate that only the transconductance is nonlinear, neglecting the reactive pumping as is commonly done elsewhere [5, 9], and we study the loading of the pumped circuit (LO) in the frequency domain with a network as depicted in F ig . 8 (simplified here for clarity). The drive behind this is the intuition that the observed conversion gain behavior must be the result - 23 -Ccoup Figure 7: Complete packaged FET equivalent circuit Figure 8: L O reflection circuit Cgd R L of voltage patterns across one or more nonlinear elements of the FET directly affecting its conversion mechanism as a function of the drain load. The experimental load model of F ig . 8 allows the variation of both the magnitude (T) and phase (@) of the reflection coefficient. The equations relating them to the circuit variables are: O = ( l80-6 ) /2 d - n RL =50 (l+O (1) (2) where O is the electrical length of the lossless transmission line at a given frequency and RL the value of the load resistance. -25-In F E T quasi-static models, the gate-source capacitance (VCgs) and drain-source resis-tance (VRdl) voltages control the nonlinearity of every element so defined. B y calculating the voltages on various elements, it is found that the magnitudes of both VCg, and VRds indeed show very good correlation with the measured conversion gain patterns. These two quantities and their phase difference were generated with S P I C E and are plotted in F ig . 9 for a typical case. The reflection coefficient phase corresponding to the voltages' maxima lines up very closely with the minimum conversion gain locus, and vice versa (Fig. 5). We postulate (for the time being without any "physical" foundation) that these two voltages directly modify the magnitude of the first harmonic of the transconductance spectrum (Chapter 2), the "sideband generator", without significantly altering the average Figure 9: Typical L O voltages at 1.39 G H z for T = 0.8 0.84 0.66-1 1 1 1 1 . 1 1 1 1 1 1 I-0 30 60 90 120 150 180 210 240 270 300 330 360 Reflection coefficient angle (deg) Fig. 9-a: Vcgs -vs- L O reflection coefficient angle - 2 6 -value. This first harmonic is therafter termed "mixing transconductance" (gmMIX). Hence, we model the upconverter's L O reflection mechanism in the R F circuit v ia gmMIX which is dependent on voltages obtained at the L O frequency in the pumped circuit and by VCgs as calculated from the IF circuit. Thus, I{FRF) = gm-/ LO u LO /Cgs > VRds VCgs(FIF) (3) Fig . 10 depicts the resulting IF /RF circuit combination and F ig . A.7 shows the corresponding IF /RF interconnection and the conversion matrix that it represents. Given the linear relationship between gmMK and the 15211 (IF to R F transmission coefficient) of this circuit, and the latter's equality, by definition, to conversion gain, the experimental conversion gain data along with the calculated L O voltages are used to extract the above gmMIX function. This analysis thus naturally couples internal F E T parameters and L O voltages to the sideband conversion gain. This formulation is specific to the F E T structure and is expected to be more universal than i f gmMIX was related directly to the external circuit. Practically, a significant computation economy can also be achieved since the L O voltage variables are implicitly functions of frequency. 3.3 Determining the mixing transconductance To obtain gmMIX (VCgsLO, VRdsw), the standard technique of multivariable least-square curve fitting is used to match a polynomial expression in VCgs and VRds to the mixing tran-sconductance values obtained from the experimental conversion gain data, independently - 2 8 -Figure 10: RF/IF equivalent circuit of frequency and of the magnitude and phase of the reflection coefficient. A n approxi-mate form for the function has been guessed by studying some of the published transcon-ductance expressions, and by trial and error. The phase difference between VCgs and VRds (A\|/) is an important variable for the best fit. Its physical meaning is discussed in Sec-tion 4.4. The following expression was found to give the best results for each sample studied: gmMIX ( V C g s w ,VKdsIX>) = aVCgs T + r, I VRds cos ( A y ) I E + p I VRds cos ( A y ) I G (4) with VCgs and VRds representing the voltage magnitudes. The optimum fit is then obtained by a grid search seeking to minimize an error function which gives an equal effective weight for each data point. It is expressed as: 1 N e=—-—y (N-m) f Sm CALCi Sm MEASi 8m MEASi (5) where N is the number of data points and m the number of independent variables. It is the equivalent of the usual Standard Error of least-square regressions. The listing of the computer program used to solve that equation is presented in Appendix C. A typical example of a fit that can be obtained using this function is shown in F ig . 11. The peak error in the predicted values of conversion gain for any phase of the reflection coefficient at 1.46 G H z is about 1 dB. Equation (4) is discussed in more detail in Section 4.3. - 3 0 -3.4 Method summary In summary, the proposed design method involves the following steps: a] Wi th the drain terminated in a broadband 50 Q load, find the bias and the input L O power which yield the "optimum" operation of the F E T , where all three of conver-sion gain, third-order output intercept point, and figure of merit are maximized while the output level of the second and third L O harmonics is kept as low as possi-b] Use a modified load-pull method to measure the conversion gain over an L O fre-quency tuning range at least as wide as the intended bandwidth of operation. This renders conversion gain C G as a function of the magnitude (T) and phase (0) of the reflection coefficient, and the L O frequency Fw: c] Construct three equivalent circuits representing the F E T at IF, R F and L O ; extract their element values from S parameters measured at the L O level and bias obtained in a]. d] Assume the transconductance is the sole nonlinear element of the F E T . In the R F equivalent circuit, define a conversion current source, to be controlled by the IF gate voltage, with an associated mixing transconductance gmMK. The latter must obvi-ously be a function of T, 0 and : ble. CG = CG(F, B,FLO) (6) (7) - 3 2 -e] Use the IF and R F equivalent circuits to determine the theoretical IS 2i I from IF to R F . First, in the loaded IF circuit, the voltage on the gate-source capacitance (VCgs) is calculated over the desired bandwidth; next, via the conversion source, the theoretical IS2 1I is determined as a function of gmMIX and sideband frequency FRF. B y definition, IS211 must be equal to the measured conversion gain C G : \S2l\(gmM,x,FRF) = CG(r,e,FL0) (8) with FRF and F^ related by F,F. The solution of this equation for gmMIX allows the extraction of (7). f] Study the voltage patterns in the L O circuit with a model of the experimental load of b]. This yields functions of the type: Vwi=VU)i(T,®,FLO) (9) where Vw',- represent the voltage on the elements of the equivalent circuit. Correlat-ing (6) and (9), the gate-source capacitance Cgs and drain-source resistance are selected as the key elements. g] Assume that the conversion gain variations are caused by a mechanism linking gmMIX to VCgs and VRds at L O . Then, gmMIX can be written as: gmM!X=gmM!X(VCg™,VRdsL0) (10) Using least-square curve fitting, solve (10) by combining (7) and (9). h] Upconverter performance optimization can now be performed as the effect of a par-ticular drain network on the two selected L O voltages can be evaluated, and in turn the conversion gain predicted. - 3 3 -C H A P T E R 4: A C C U R A C Y O F T H E M E T H O D AND ITS P H Y S I C A L F O U N D A T I O N : DISCUSSION 4.1 Additional experimental details During the course of these experiments, it became clear that the choice of the gate bias has an impact on the depth of the conversion gain dip. This was investigated for the case of the "maximum" bias (near pinch-off). F ig . 12 depicts A C G ( = conversion gain maximum - conversion gain minimum ) and F O M (figure of merit) as a function of L O power for the cases of "maximum" and "optimum" bias &tFRF = 1.50 G H z . Two samples of batch 1 were used for these measurements; this batch shows a much higher sensitivity to the L O loading than batch 2. A C G is indeed smaller when the device is biased near pinch-off: the neighborhood of 0 - 2 d B m yields simultaneously the best F O M and the smallest A C G . A C G is about 4 dB there. For the "optimum" bias case, the results of Sec-tion 3.1.1 are reproduced at 0 d B m (best F O M ) ; A C G is also the smallest there, but it now goes as high as 18 dB (for sample 9). This shows how sensitive certain devices can be to the drain loading (compare with a typical A C G of 9 dB for batch 2). Batch 2, at the "maximum" bias, showed a typical A C G of 3.5 dB at 2.1 G H z and 0 d B m L O power. It is clear that the choice of operating conditions influences the magnitude of A C G . However, for the "maximum" bias case, the drain-source D C current variation between the maximum and minimum conversion gain for a large value of the magnitude of the L O reflection coefficient is now close to 50% of its 50 Q value, compared with only 14% for the "optimum" bias. Hence, the S parameters are likely to vary substan-tially. Furthermore, the reflection coefficient phase angle corresponding to - 34 -Figure 12: A C G and F O M -vs- L O power at 1.5 G H z -10 -17 - 3 5 -the minimum conversion gain is not the same as for the "optimum" bias. This is also verified by monitoring the L O power at the drain of the F E T (simply by inserting a direc-tional coupler after the bias T in Fig . 4) as a function of the load: the phase angle at the maximum power no longer corresponds to the minimum conversion gain's phase angle, although no precise deviation can be quoted. Nevertheless, even the relatively small conversion gain difference obtained for the "maximum" bias can be significant when a combination of input L O power, temperature, bias variation, frequency, and device non-linearity variations are involved. The design method reported here would not be applica-ble for this case. A n apparent experimental discrepancy was revealed in Section 3.1.2 which occurs for the conversion gain measurement between the broadband and the narrowband 50 Q loads. The latter causes a conversion gain increase of more than 1 dB over the former. This could be due to the L O harmonics, still influential, or to feedback effects at IF. Cal -culations using the IF equivalent circuit show that the voltage across the drain-source resistance is decreasing significantly between these two loads and suggest that there is a channel conductance contribution which interferes destructively with the transconduc-tance when the drain is terminated in 50 Q at IF. 4.2 Element acquisition and accuracy enhancement The L O controlling voltages (VCgs and V^) are quite sensitive to the value of some elements of the equivalent circuit. It is therefore important to extract these with the best accuracy possible. Two sources of uncertainties are involved: first, the ability of the equivalent circuit to represent closely a real F E T ; second, the accuracy of the S parame-- 3 6 -ters themselves. Unfortunately, there is a trade-off between the certainty in the value of an element and the variable-element count of an equivalent circuit [11]. Wide bandwidth (to 18 G H z ) S parameters and direct measurement of a number of elements are the only ways to increase certainty and keep the correct internal physical representation of the F E T . Even extensive wideband (12 G H z ) S parameters fitting performed during this work still yielded wide ranges for the sensitive elements. Using packaged FETs creates an even more complex situation. It is our experience that with only S parameter and manufacturer (such as package and chip parasitics) data available, simple parasitic elements whose values are variable together with a narrower optimization bandwidth are preferable to ensure a closer fit, within measurement uncer-tainties. These simplifications require meeting additional constraints to fix internal cir-cuit relationships. For that purpose, F E T output/input mappings at selected frequencies and values of the reflection coefficient magnitude can be enforced simultaneously with the S parameters during the element acquisition procedure. A direct byproduct of our analysis, these mapping relations can be easily verified experimentally, and provide further support for our constant element assumption. F ig . 13 depicts such a mapping obtained experimentally for a full 360 degrees span at the drain. The magnitude of the drain reflection coefficient is = 0.83, the L O power is 0 dBm, and the frequency is 2.03 G H z . The same setup as in Fig . 4 is used but with the HP8510A directly connected to the gate of the F E T . The plot shows that the F E T has a negative input resistance over a region of the Smith chart which does not appear to have direct relations with the conver-sion gain patterns. - 3 7 -Figure 13: Experimental output/input mapping at 2.03 G H z for T = 0.83 Table I presents a comparison of the measured and calculated (with Touchstone and the large-signal S parameters) input reflection coefficients for two samples. These values agree quite well . Table I: Measured and calculated output/input mapping at 2.03 G H z Sample # T, © (mag,ang) Input reflection coefficient (mag,ang) Measured Measured Calculated 2 .822/45.5 .833/64.8 .854/1.11.6 1.000/-53.7 1.042/-49.1 1.0O0/-43.7 .999A53.5 1.035/-49.5 1.000/-44.5 4 .823/44.9 .839/71.3 .829/105.2 1.000/-53.9 1.043/-47.5 1.000/-43.5 1.001/-53.3 1.038/-47.9 1.006/-44.5 - 3 8 -A l l the simulations reported here were obtained with that approach. The simplified equivalent circuit is shown in F ig . 14, and a set of typical element values is presented in Table II. A 2 G H z bandwidth of S parameters was used together with the output/input mapping of the drain load (calculated from the measured S parameters) at 1.39 and 2.03 G H z for two values of the L O reflection coefficient magnitude. The loci of maximum and unity magnitude of the resulting input reflection coefficient were chosen for con-venience. This adds 12 extra optimization goals to the basic S parameters fit. A sample Touchstone file used to extract the elements of the circuit is shown in Appendix D . O f course, the elements of this simplified circuit are more distant from their "correct" physical values, but by nature, equivalent circuits are limited in scope. Nevertheless, as long as the circuit models correctly the external characteristics of the upconverter, this "black box" representation is the most attractive in terms of accuracy, measurement efforts, and modelling complexity. Straight wideband S parameter fitting is still valuable. It enables a quick qualitative assessment of the upconverter's frequency response based on the frequency response of the L O voltages. For example, F ig . 15 depicts calculated gate-source capacitance and drain-source resistance voltage patterns at 10 G H z . It is clearly shown that in this case, by analogy with the correlation previously demonstrated between voltages and conver-sion gain, the occurrence of a drain-source voltage peak and a gate-source voltage dip around the short-circuit angle, the usual approximation to optimum L O loading, would seriously degrade the mixer performance of the transistor studied here. - 3 9 -Figure 14: Simplified FET equivalent circuit Table II: Typical element values Element Value units *. 7.8637 Q ** 0.29302 R, 7.08732 0.04031 nH LD 0.2069 0.1228 ciH 0.31203 pF 0.31017 c„ 0.391 0.01948 0.09327 *i 17.92754 138.5854 gm 0.06317 S X 0 ps -40-Figure 15: L O voltages for T = 1 at 10 G H z 0.60H 1 1 1 1 1 1 1 1 1 1 h 0.404 1 1 1 , 1 1 1 1 1 , , 1 0 30 60 90 120 150 180 210 240 270 300 330 360 Reflection coefficient angle (cleg) Fig. 15-a: Vcgs -vs- L O reflection coefficient angle Reflection coefficient angle (cleg) Fig. 15-b: Vrds -vs- L O reflection coefficient angle -41 -An improvement to our method could be achieved by a more realistic measurement of the large-signal S parameters. Our technique indiscriminately characterizes both FET ports with the same power level. More rigorous large-signal characterization methods can be found in the literature; yet, an attractive and practical alternative is to increase the test power level used to measure and SL2, both particularly important for the design of output networks. As we proceeded, the SU and S 2 i measurements gave realistic results in a 50 Q. system. However, the device gain considerably increases the RF power present at the output and a 0 dBm testing somewhat underestimates the proper large-signal depen-dence of 5 22 and S i2. For example, reciprocity could be applied to find the most realistic test power level. Referring to Fig. 16-a, represents the L O power measured on a 50 Q termination during the experiment of Section 3.1.1. Fig. 16-b depicts an impedance measurement where the power of the source is adjusted while measuring S22 and calculat-ing P2 until P2 = Pi. Then both S 1 2 and S 2 2 c a n be measured at that level. This method will not give the rigorous situation where all the harmonics are correctly reproduced in the drain circuit but will yield much closer results for the L O fundamental. Figure 16: Large-signal S parameter measurement diagrams P2 50 V D \7 \7 a b -42-4.3 Simulation details and accuracy Our results suggest that the range of validity of Equation (4) is limited only by the experimental conversion gain data available. The S parameters are easily measured on an automated system, but the conversion gain experiments are limited in the possible range of reflection coefficient magnitude (T) and L O frequency range by the insertion loss and the frequency response of the components available. The conversion gain meas-urements are performed manually and can be laborious, especially at high frequencies. To reduce the experimental burden, a minimum amount of data points should allow the widest conversion gain simulation range in the reflection coefficient and frequency space. A s is realized from Fig . 11, the dip region, with its steep slope, is much more prone to simulation errors. The small value of the mixing transconductance (gmMIX) at the minimum makes Equation (4) extremely sensitive to the drain-source resistance voltage which can become very large for a F E T subjected to a load with a high T. It is therefore important to have data of conversion gain extremes for the largest value of T possible. If the losses of the test components hinder the measurement of high T conversion gain extremes, then their values must be estimated to fix the combination of the drain-source resistance and gate-source capacitance voltages at T = 1 in the regression. Otherwise, the simulations are essentially limited (in the upper range) to the maximum measured T for accurate results. The frequency limitation in the accuracy of Equation (4) depends on the correlation between the frequency response of the L O voltages and the actual conversion gain extremes. Our data does not indicate a significant frequency dependence of the conver-sion gain extremes over that bandwidth while the L O voltages do vary slightly. - 4 3 -Consequently, the L O voltages combination for the highest reflection coefficient avail-able must be enforced over a frequency range to obtain the best overall fit. Based on these considerations, a very acceptable fit is obtained by actually using a relatively small amount of data. The conversion gain dependence on the phase of the reflection coefficient for three values of the coefficient's magnitude at a frequency where the error in predicting the angle corresponding to the conversion gain minimum (for the maximum reflection coefficient) is small ( 2 - 3 degrees) plus the extreme points (minimum and maximum conversion gain) at selected inband frequencies yield a good overall match of the reflection coefficient dependence for each test frequency. The econ-omy of data required (about 35 points here) is an attractive feature. Table III presents a set of data pertaining to six different samples of the NE70083 and one sample of the NE71084. Predicted and measured values of the reflection coefficient angle corresponding to the conversion gain extremes (also listed) are compared; the values of the "optimum" bias and of the parameters of Equation (4) yielding the best fit are also shown for each case. Consistency is observed among all these samples. The reflection coefficient phase angles for the minimum conversion gain are in fact very close to the conjugate of the measured S22 angles and are predicted with a worse case inaccu-racy of 8 degrees; for the maximum conversion gain, the angles deviate more but can tolerate larger error because of the flatness of the curve in that region. The minimum conversion gain decreases with R F frequency increase but as mentioned above, it may be caused more by inherent reflection coefficient magnitude variations at this point (also listed) than by true frequency response. The exponents of Equation (4) differ slightly, but - 4 4 -S A M P L E # F R E Q U E N C Y (GHz) 1.46 1.52 measured (dB) ©™,(°) 4 measured (dB) e ^ O 5 J meas calc meas calc CG m i „ meas calc meas calc 1 -8.6 -0.3 22.7 21.9 -166.4 -172.4 -9.7 -0.2 29.9 23.0 -159.8 -171.9 2 -8.5 0.8 20.9 23.4 -157 -171.7 -10.1 0.9 27.0 24.4 -163.8 -170.8 3 -8.5 0.1 24.8 23.3 -155.3 -171.9 -10.0 0.0 24.9 24.3 -172.4 -171.4 4 -8.1 0.5 21.5 21.4 -156.2 -170 -9.3 1.0 25.7 22.4 -164.0 -169.5 5 -8.5 0.5 23.4 N / A -155.1 N/A -9.3 0.9 27.6 N / A -162.9 N / A 71 -8.5 0.6 19.6 N / A -155.5 N / A -9.4 0.5 24.4 N / A -167.6 N / A 16* -12.9 0.7 21.6 N / A -153.6 N/A -16.9 -0.4 26.7 N / A 178.3 N / A 4^  S A M P L E # F R E Q U E N C Y (GHz) 1.59 2.1 measured (dB) e • (°)7 mmV ' e (°)8 measured (dB) 6 • (°)9 maxV > meas calc meas calc CG«in meas calc meas calc 1 -10.8 -0.4 31.7 24 -160.4 -171.6 -11.8 -0.5 35.7 31.5 -154.1 -168.6 -0.64 2 -12 0.8 28.7 25.5 -164.9 -170.8 -14.3 0.6 37.3 33.3 -160.4 -171.7 -0.36 3 -11.4 0.0 27.9 25.4 -169.1 -171 -12.1 -0.6 35.3 33.1 -155.9 -167.9 -0.61 4 -11.6 0.6 29.6 23.5 -172.5 -168.9 -12.2 0.6 36.4 30.8 -155.8 -165.5 -0.4 5 -11.6 0.5 28.2 N/A -169.2 N / A -12.9 0.0 35.9 N / A -163.1 N / A -0.34 71 N / A N / A N/A N/A N / A N / A -15.3 -0.2 35.3 N / A -170.5 N / A -0.29 16* -20.7 -0.3 28.3 N/A -170.1 N / A -25.3 -2.1 35.5 N / A -156 N / A -0.34 1:NE71084 2:NE70083,batch 1 3:T=.757 4:T = .825 5: T = .782 6: T= .817 7.r = .803 8:T=.792 9.r=.814 10.r=.825 S A M P L E # E Q U A T I O N P A R A M E T E R S T E G a(*10~2) n (*10"2) P 1 0.6 0.2 2.5 3.59 -1.24 -1.46 2 1.2 0.3 2.4 3.09 -0.55 -1.6 3 0.7 0.2 2.9 3.03 -1.01 -0.61 4 0.7 0.2 2.7 2.44 -0.69 -0.7 Table III: Upconverter data for several samples for FIF = 70 MHz are within an acceptable range given device variations (e.g. "optimum" bias). For the coefficients, patterns are observed for a and TJ. Coefficient a is reasonably constant for all the samples and rj is similar for each pair of sample with similar "optimum" bias. Coefficient p does not follow any particular pattern. A simplified version of Equation (4) (without the last term) was the next best approximation to Equation (7). It could be used advantageously for small bandwidth simulations. More calculated and measured curves of the conversion gain as a function of the L O reflection coefficient are presented in F ig . 17 for sample 3; Appendix E shows the simu-lation results over the full bandwidth. The maximum magnitude of the reflection coefficient is = 0.8 at each frequency across the band. The measured and calculated conversion gain curves agree quite closely in shape but there can be a considerable error for points within the dip, reaching almost 3 dB for the largest reflection coefficient. However, given the very steep slope of this notch and the inevitable measurement and simulation errors, these deviations are still relatively small. In fact, the error in predict-ing the phase angle of the conversion gain minimum at a particular frequency directly influences the magnitude of these deviations, which increase as the Q of the load does. Better match can be obtained despite these phase angles inaccuracies i f the regression is performed over smaller bandwidths and/or more data points used. In order to show the potential accuracy of the simulation part of the method, a worst case uncertainty of 5 degrees is assigned to all the measured reflection coefficient phase angles (precision of manual measurement technique and measurement uncertainty with an HP8510A, calculated from the equations presented in [12]) at several - 4 6 -Figure 17: C G -vs- L O reflection coefficient for sample 3 frequencies. The measured curve is then shifted by 5 degrees to the left. Using the same equation parameters as for F ig . 17, the conversion gain is resimulated. The new results are shown on F ig . 18 at 1.59 and 2.1 G H z for a reflection coefficient magnitude of = 0.8. The peak error in the dip is now about 1 dB. O f course, this is an arbitrary comparison. The curve could also be shifted 5 degrees to the right, in which case the fit would be even worse. But it shows the potential accuracy that can be expected without recalculating the regression. In addition, the uncertainty on each measured S parameter w i l l influence the accuracy of the phase angle prediction of the conversion gain minimum. A rigorous assessment of these uncertainties is not straightforward. Given the limitations of Touchstone for that purpose and the impracticality of the task, a simple procedure was devised which gives a feel for the sensitivity of the L O voltages on specific elements of the equivalent circuit when the S parameter uncertainties are considered. The measured S parameters and their uncertainties are entered as ranges in the O P T block of Touchstone for a single fre-quency. Each element of the best set (as obtained in Chapter 3) is perturbed in turn while keeping the others constant to find the particular range over which the error function cal-culated by Touchstone is below an arbitrary small value. The calculations must be per-formed at each desired frequency. The resulting variations in the locus and value of the L O voltages extremes can be determined for each element also with Touchstone. Typi-cally, each S parameter angle has a 4 degrees uncertainty and the magnitudes of Sii. S 2 i , S u and S22 have uncertainties of 0.06, 0.16, 0.007 and .04, respectively. - 4 9 -Figure 18: C G -vs- L O reflection coefficient including uncertainty 0 30 60 90 120 150 180 210 240 270 300 330 360 Reflection coefficient angle (deg) Fig. 18-a: mag = 0.8, F =1.59 GHz 0 -13-1 1 1 1 1 1 1 1 1 1 1 1 i 0 30 60 90 120 150 180 210 240 270 300 330 360 Reflection coefficient angle (deg) Fig. 18-b: mag = 0.8, F = 2.1 GHz -50-For the minimum conversion gain phase angle, the gate-drain, drain-source, and out-put capacitances give the largest variation, reaching 7 degrees for the drain-source resis-tance voltage and 6 degrees for the gate-source capacitance voltage, and its sign changes over the bandwidth; for the maximum conversion gain phase angle, the drain inductance could shift both L O voltages by up to 20 degrees. Such shifts w i l l indeed make a significant difference in the accuracy of the simulations. Likewise, the drain-source resistance voltage could be changed by up to 1 V by varying the drain-source resistance and the transconductance. This method is not absolutely rigorous since only one element is allowed to vary at any time but nevertheless it provides some insight into the uncer-tainties associated with the element values. The sensitivity shown to elements such as the gate-drain and drain-source capacitances supports the need to increase the measure-ment accuracy of S 1 2 andS 2 2 a s mentioned in Section 4.2. 4.4 Physical link between the LO voltages and conversion efficiency A scrutiny of the coefficients in Equation (4) (Table III) reveals that gmMIX is depen-dent directly on a power of the gate-source capacitance voltage (VCgs) and is corrected by two negative factors dependent on the drain-source resistance voltage (VRds). Intuitively, this corresponds well to the normal situation where VCgs predominantly controls the action of the transconductance but the presence of these corrective factors which "per-turb" the gate action cannot be the result of pure mathematical artifice: they should bear some relation to the physics of M E S F E T s . This section attempts to shed some light on the mechanisms involved and suggest a possible explanation. - 5 1 -4.4.1 Circuit - voltages relation Referring back to Fig . 9, the minimum and maximum of VRds simply correspond to series and parallel resonance at the drain of the F E T , while the minimum and maximum of VCgs are caused by extremes of negative and positive feedback. Over the bandwidth studied, this feedback appears to act as a self-regulator of the drain-resonance destructive interference by simultaneously creating a VCgs maximum. Consider the frequency response of the extremes of VRds, VCgs, and conversion gain (the L O voltages are depicted in Appendix F over a 1 to 12 G H z bandwidth). VRds has negative slopes for both. Based on Equation (4), this implies positive slopes for both the minimum and maximum conversion gain. However, VCgs's slopes are also negative and contribute to counteract VRds's; as apparent from Appendix F , a positive to negative feedback reversal even occurs around 5 G H z . Thus, a physically sound situation evolves from the combination of the frequency response of the two voltages, but it remains to be seen how much weight VCgs has at higher frequencies since the actual frequency response of the conversion gain extremes is not clear from our data. In this' context, our results reinforce the findings of Hirota & Ogawa [10] and Rauscher [13] in showing that feedback and resonances at the L O frequency, caused by the transistor's internal elements and package parasitics, directly influence the conver-sion gain behavior, but with the difference that a nonlinear circuit/device interaction is clearly present. Further study of the parasitics and feedback elements influence on VCgs and VRds based on the results of Section 4.3 reveals that VCgs is quite sensitive to the value of the gate-- 5 2 -drain capacitance (Cgd), the source resistance (Rs), and the source inductance (Ls). Rs causes its extremes to occur simultaneously with VRds's while 4 _ but mainly Cgdt can shift them apart appreciably; the latter also provides an increased gradient of the frequency response of the magnitude and phase angle locus of the maximum VRds and eventually causes the positive to negative feedback reversal for VCgs. Therefore, it appears that the behavior of the internal voltages is directly dependent on the proper balance between these elements. A rigorous parameter acquisition technique with accurate test fixture deembedding, accurate package model, wideband (18 GHz) S parameter - equivalent cir-cuit match, and several independent measurements would be necessary to unambiguously fix the value of each internal element with good certainty, but the efforts required are beyond practicality. 4.4.2 Transconductance - voltages interaction The nonlinear circuit/device interaction mentioned above could be explained by the drain-voltage induced pinch-off voltage shift, a short-channel M E S F E T D C phenomenon reported by many researchers [5, 14, 15] and judged important for best modelling accu-racy. Typical plots of the D C drain-source current as a function of the gate and drain voltages are shown in F ig . 19-a and -b for the F E T studied. In 19-b, the gate nonlinear region is located at pinch-off, whose shift as a function of the drain voltage is obvious. A t large values of the drain voltage, the curve becomes almost completely linear. A s a dynamic process, this shift would modify the second-order characteristic of the transfer function. When the corresponding transconductance is plotted, as in Fig . 19-c, its modu-lation by the drain voltage is serious. Now both the pinch-off and near 0 V regions are - 5 3 -being modified. Figure 19: Typical D C characteristics of NE70083 ID GnA) 76.10L 7.610 / d i v .0000 .0000 VD . 6 0 0 0 / d i v ( V) 6 .000 ID GnA) 72.00L 7.200 / d i v ,0000 Fig. 19-a: IDS -vs- VDD, = -1.0 - 0.25 - 1 . 4 4 0 VG . 1800 /d iv ( V) Fig. 19-b: 1^ -vs- VGG, VDD = 0.5 - 6.0 0 .1800 54 GM (mS) It is not clear to what extent this effect is modified by relaxation phenomena at microwave frequencies. However, the following observations appear to be more than purely coincidental. The study of these D C curves and of their possible relation to the equivalent circuit suggests that drain parallel resonance, where the drain-source resis-tance voltage (VRdt) is maximum and where the gate-source capacitance voltage (yCgs) and VRds are out of phase, would effectively reduce the drain current/gate voltage second-order nonlinearity to create the most severe conversion efficiency degradation: the posi-tive Vkds swing renders the pinch-off region progressively more linear while VCgs swings into it and the negative VRds swing makes the pinch-off region progressively more para-bolic but VCgs swings away from it. The effect can be sizeable even i f VRds does not swing out of the saturation region. The drain current waveform's second harmonic has - 5 5 -decreased: we claim that it is minimum there. A t the other extreme, drain series reso-nance, which corresponds to minimum drain voltage modulation of the drain current/gate voltage characteristics, would create the maximum conversion efficiency for the gate bias used. The 180 degrees phase shift naturally occurs at parallel resonance since all the current from the controlled source of the equivalent circuit essentially flows through the channel conductance from the source end. A s a further demonstration of this phenomenon, the mixing transconductance is derived from a well-known GaAs M E S F E T drain current expression [16] modified to include the pinch-off voltage shift effect. The following expression is used to calculate the transconductance which is Fourier analyzed: hs = P (V c (0 - VPf d + ^ ( 0 ) tanh(T VD (0) (11) where V/ = Vp(l + o(VD(0 - VDD0)); Vp is the pinch-off voltage measured at the drain voltage VDD0; VG(t) = VGG + Acos(cor), the gate voltage; and VD (0 = VDDo + Bcos(cor + <|>), the drain voltage phase shifted by (J) from VG{t). The second term of the series is S«i = P (1 + WDDd (A - cBVpe>«>) (12) which is minimum at <|) = K because Vp is negative. The complete derivation is presented in Appendix G . Equation (12) demonstrates for this simple model that a 180 degrees phase shift yields the maximum destructive interference from the drain voltage and tends to reconcile our approach with quasi-static models. The sensitivity of the second-order nonlinearity to the pinch-off voltage shift process - 5 6 -is obviously affected by the gate bias chosen. If the F E T is biased close to pinch-off, the drain current waveform is still strongly rectified regardless of the drain-source resistance voltage swing and the conversion gain range w i l l be small (see Section 4.1). However, as the gate bias increases (positively), the mechanism described above w i l l become more and more detrimental. This qualitatively agrees with the experimental observations and our simulation of the F E T upconverter behavior. If this phenomenon is actually responsible for the conversion gain behavior and i f the transconductance's voltage dependence can be considered constant over a large enough microwave frequency band, the frequency response of the drain-source resistance voltage renders a progressively decreasing transconductance modulation which implies a dimin-ishing conversion gain dip. A s mentioned above, the feedback on the gate-source capa-citance may counterbalance this but the necessary information to corroborate this hypothesis is not readily available. Actual simulations were performed using the curves of F ig . 19-c over a limited range of the drain voltage (1 to 5 V ) . The 180 degrees phase difference corresponded to the minimum mixing transconductance and the sensitivity to the gate bias as described above was verified, but the simulations failed to predict the degree of variation necessary to account for the observed conversion gain range. More data relevant to high-frequency current-voltage characteristics as obtained with Smith et al's technique [17], for instance, would be necessary to pursue further this idea. Nevertheless, this pinch-off voltage shift concept brings enough physical insight to support our simulations. - 5 7 -C H A P T E R 5: APPLICATIONS O F T H E M E T H O D 5.1 Drain network synthesis In this section, we briefly examine the mechanics of analyzing the performance of an upconverter using Touchstone. For example, a simple drain matching network without rejection specification is to be designed. 1) Frequency choice. A fixed IF of 280 M H z and an R F bandwidth of 100 M H z cen-tered at 1.95 G H z are selected. The L O range is thus 1.62 to 1.72 G H z and falls within the previously characterized bandwidth; however, a slightly wider range w i l l be used to study the conversion gain behavior. 2) Embedding impedances. The gate is broadband 50 O, the drain is short-circuited at IF, and a conjugate match is desired at R F . 3) A first approximation for the drain network can be calculated. Here, the initial interest is to match the drain of the F E T to a 50 Q load and disregard any L O fre-quency loading dependence. A Chebyschev polynomial realization with minimum ripple is calculated with a C A D circuit synthesis program. The resulting network is shown in F ig . 20. 4) Appendix H presents a sample Touchstone file used to calculate the IF and L O vol-tages plus the resulting upper sideband conversion gain. First, the matching net-work and all the scaling factors, parameters, and element values are input. - 5 8 -Figure 20: Matching network 1 8.68 nH 1.42 pF 70.93 nH 9.03 nH Using the T U N E mode, a first sweep gives both the IF voltages at 70 and 280 MHz for the drain short-circuited and the L O voltages over the bandwidth. VCgs(FlFy in Equation (5) of Appendix B is calculated (its value is 0.99 here), entered as thelFVOL parameter and the L O quantities are input for one frequency at a time, the file swept again, the calculated conversion gain recorded, and so on until the full bandwidth has been swept. The T U N E mode facilitates the adjustment of the drain network without rerunning the complete program. Any element can be changed and the same procedure repeated. The output return loss can be monitored simultaneously. Fig. 21 depicts the resulting conversion gain frequency response. In the band of interest, the conversion gain is about -3.4 dB with a slope of only 0.4 dB. Given that the 50 Q. conversion gain was about -1.8 dB and that matching the drain should give a 2 dB improvement, the degraded conversion gain in Fig. 21 is obviously due suboptimal L O reflection. -59-Figure 21: C G -vs- frequency with network 1 -2.8 -4.0J 1 1 1 1 1.85 1.90 1.95 2.00 2.05 2.10 Frequency (GHz) In fact, based on F ig . 17, the condition to achieve for optimum L O reflection is the largest magnitude of the reflection coefficient possible within a span of about 140 degrees around the series-resonance angle. This guideline can be used to facili-tate the design of a first iteration. 5) To improve the first design, another Chebyschev network but with a larger ripple (0.3 dB) to steepen its skirts is designed. Fig. 22 depicts the network while Fig . 23 shows its output return loss and the resulting conversion gain over the bandwidth. The conversion gain is now higher (-0.2 to -1.5 dB) but it shows a significant nega-tive slope (1 dB) and the return loss is only marginally acceptable. If better 50 £2 match is required for a specific application, an isolator could be connected in cas-cade with that network. - 60 -Figure 22: Matching network 2 44.49 nH ' 2 1 p F 4 pF 1,32 nH 98.21 nH Figure 23: C G and RL -vs- frequency with network 2 0.0 -0.5 d B -2.0 -2.5+. -3.0-1 . 1 . . i 1.85 1.90 1.95 2.00 2.05 2.10 Frequency (GHz) Fig. 23-a: C G -vs- frequency -61 -18 d B R L 9 84— 1.85 1.90 1.95 2.00 Frequency (GHz) Fig. 23-b: R L -vs- frequency 2.05 2.10 A s can be seen in this simple case, the model allows the selection and optimiza-tion of drain networks to obtain a desired upconverter performance. The above pro-cess can be continued to narrow down the best network prototype. A good improve-ment was already noted with the second iteration. The simulation results, depicted over a 250 M H z bandwidth, also suggest that it would be hard to maintain a good flatness over such a wide range and would therefore lead to a practical restriction on the useful and desirable L O tuning range. 5.2 Additional considerations in using the method 1) Gate loading at L O . The L O level and the gate termination used in the experiment must be carefully reproduced in the simulations, otherwise the model does not hold since the voltage - 6 2 -patterns would now be different. However, in view of the discussion of Section 4.4, it can be expected that if the gate were matched, the conversion gain range would become even larger. In this case, to maintain predictability, the practical solution would be to reduce the test L O power to create internal L O voltage levels at par with the original ones. 2) IF termination at drain and other small-signal impedances. For maximum gate-source capacitance voltage, the IF drain termination should ideally correspond to the conjugate of the output impedance. However, we have concluded in Section 4.1 that the termination at IF is causing a destructive interfer-ence with conversion gain due to the channel conductance. Therefore, the short-circuit cannot be varied without creating extra simulation uncertainty because it contributes to the large-signal solution by limiting the channel conductance contri-bution. Yet, both the gate loading at IF and the gate and drain loadings at RF can now be studied with this model and their influence on conversion gain assessed. For example, the gate can be matched at IF to increase conversion gain, and this improvement can be easily calculated; the RF gate termination resulting from the input IF/LO diplexer can also be included in the simulations for more accuracy. 3) Calculation of L O rejection. This is an important circuit performance variable that can be calculated with this method. The Touchstone file of Appendix H can also output the IS 2i 1 of the L O cir-cuit. Given the input L O and IF powers used experimentally, the rejection is simply - 6 3 -calculated as: Reju, (dB) = P,F+CG - \S21(FW)\-Pw (13) where C G is the conversion gain calculated from the IF /RF circuit, PIF is the input IF power, Pw the input L O power, and all the variables are in dB. Note that the value calculated is only valid for the particular IF power used in the experiment. 4) Limitations of characterization method on upconverter performance. The choice of the "optimum" bias and L O power has been shown previously to l imit somewhat the upper frequency and maximum output R F power performances of a given upconverter. For the former, the broadband 50 Q conversion gain is about 3 dB lower than that for the "maximum" bias value; given the frequency response of the F E T itself, this may cause marginally low conversion gain at higher frequencies. On the other hand, the maximum conversion gain obtained under optimum L O reflection conditions is reduced by less than 1 dB from the "maximum" bias value, and therefore this choice actually does not degrade appreciably the upconverter response. However, for its power handling capability, the relatively low third-order output intercept point and figure of merit obtained indeed make the transistor more suitable for a low- to medium-power intermediate stage of an upconversion chain. 5.3 Dual-gate FET This is a very interesting structure for many applications. Specifically, for mixers, the second gate allows the injection of L O directly without the need of an I F / L O diplexer since reasonable isolation already exists between the two gates. M M I C applications benefit greatly from its use. The topology of this transistor is very complex; the task of - 6 4 -equivalent circuit element acquisition is much more involved than with the single-gate F E T and an accurate physical representation is very difficult to obtain. Nevertheless, its understanding and use would increase appreciably i f a simplified design approach could be devised for nonlinear applications. A simplified equivalent circuit is shown in Fig . 24; its elements are extracted as before. Together, the two F E T parts can function in four distinct operational modes (each can operate in either linear or saturated mode); specifying the particular mode enables one to find which eiement(s) should be nonlinear. This requires thorough D C characterization and the acquisition of the parameters of a D C dual-gate F E T model such as in [18]. Even without considering the latter, more insight can be gained by studying the device in a manner similar to the single-gate F E T . Preliminary tests of conversion gain as a function of the L O reflection coefficient were performed at 1.50 G H z (F1F = 70MHz) with an N E C NE41137 dual-gate F E T , an U H F band device, for an L O power of 10 d B m . The F E T is biased with -0.95 V on the first gate, -0.83 V on the second gate, and 5.0 V on the drain. N o IF drain short-circuit was used and no attempt was made to reduce the level of the L O harmonics, which were already about -18 dBc. F ig . 25 depicts the results; the conversion gain range is only about 3 dB , and the curve is irregular (probably due to the varying IF impedance). For the minimum conversion gain locus, the reflection coefficient has a magnitude of 0.866 and its angle is 48.2 degrees; for the maximum conversion gain locus, the reflection coefficient magnitude is 0.823 and its angle is -131.9 degrees. With a L O reflection circuit as in F ig . 26, where the circuit diagram of F ig . 24 has been redrawn into an equivalent single-gate F E T configuration in which the source impedance appears as an active load, the gate-source capacitance (VCgs) - 6 5 -Cing2 gate 1 Cgdl Rl-2 drain Figure 24: Dual-gate FET equivalent circuit Figure 25: C G -vs- L O reflection coefficient at 1.5 G H z with T = 0.83 Reflection coefficient angle (deg) and drain-source resistance (VRdt) voltages of the two F E T parts are calculated (for a reflection coefficient magnitude of 1) and depicted in Fig. 27. A correlation is observed between the voltage patterns and the measured conversion gain: VRds2 and VCgs2 both peak at about 15 degrees below the measured conversion gain minimum angle and VRds2's minimum locus is very close to the measured conversion gain maximum angle; VCgsl and VRdsl both dip further away from the conversion gain minimum and are flat otherwise, but their amplitude variations are small. Despite these relatively large deviations (given our lack of "complete" experimental control of the upconverter behavior), the correlations observed suggest that our method could apply to this structure, although singling out a particular nonlinear mode is now more difficult. - 6 7 -gate 2 + VcgsS Cgd2 FET2 Cgs2 gri2x Ri2 \ Vcgs2 gate 1 Cgdl + Vcgsl Cgsl 50 gnl* Ril Vcgsl © Rdsl Rds2 Cds2 + Vrd Rl-2 Vrdsl Cdsl Rs Ls <7 Figure 26: Dual-gate FET L O reflection circuit Figure 27: L O voltages -vs- reflection coefficient at 1.5 GHz for T = 1 90 120 150 180 210 240 270 Reflection coefficient angle (deg) Fig. 27-a: Vcgsl -vs- reflection coefficient angle 360 0 30 120 150 180 210 240 Reflection coefficient (deg) Fig. 27-b: Vrdsl -vs- reflection coefficient angle 360 -69-0.28-j— 1 1 1 1 1 1 1 ^ Reflection coefficient angle (deg) Fig. 27-c: Vcgs2 -vs- reflection coefficient angle 0J , • , , , , , , , [ 0 30 60 90 120 150 180 210 240 270 300 330 360 Reflection coefficient angle (deg) Fig. 27-d: Vrds2 -vs- reflection coefficient angle -70-Reflection coefficient angle (deg) Fig. 27-e: Phase difference in FET2 -vs- reflection coefficient angle -71 -C H A P T E R 6: C O N C L U S I O N The method presented in this thesis allows conversion gain simulations of F E T upconverters over specific bandwidths using a few microwave measurements and three simple equivalent circuits. It is more suitable than Harmonic Balance-based models as a tool for practical design. Using the concept of LO-load dependent mixing transconduc-tance, commercial microwave circuit C A D tools can serve to simulate conversion gain with any particular drain network and allow the optimization of its parameters to obtain desired gain, flatness, and L O rejection over the complete bandwidth. The model w i l l be most useful for monolithic implementations lacking tuning capabilities. In reality, pure transconductance mixing is not feasible. The modulation of the drain current/gate voltage characteristics by the drain voltage involves an inevitable transconductance-channel conductance coupling; reactive pumping is also present but its contribution simply neglected. Our formulation therefore lumps these various small effects with the transconductance in an elegant fashion. From a more general point of view, this work has demonstrated the acute importance of the L O drain termination of a gate mixer in determining conversion efficiency. It has been shown that in general, neither the short- nor the open-circuit drain termination at the L O frequency w i l l cause conversion gain extremes. -72-REFERENCES [1] J. E . Sitch and P. N . Robson, "The performance of GaAs F E T s as microwave mixers", I E E E Proceedings, pp. 399 -400, March 1973 [2] S. Maas, "Microwave mixers", Artech House, 1986 [3] P. Harrop and T. A . C. M . Claasen, "Modelling of a F E T Mixer" , EL-14 , No. 12, pp.369-370,1978 [4] C . Camacho-Penalosa and C . S. Aitchison, "Analysis and design of M E S F E T gate mixers", I E E E M T T - 3 5 , No. 7, pp. 643-652, 1987 [5] W . Curtice and M . Ettenberg, " A nonlinear GaAs F E T model for use in the design of output circuit for power amplifier", I E E E M T T - 3 3 , No. 12, pp. 679-683, 1985 [6] R. Meierer, C . Tsironis, "Modelling of single- and dual-gate M E S F E T mixers", E L - 2 0 , No . 2, pp. 97-98, 1984 [7] A . Materka and T. Kacprzak, "Computer calculation of large-signal GaAs F E T amplifier characteristics", I E E E M T T - 3 3 , No. 2, pp. 129-134, 1985 [8] Y . Tajima, B . Wrona, and K . Mishima, " GaAs F E T large-signal model and its application to circuit designs", I E E E ED-28 , No. 2, pp. 171-175, 1981 [9] R. Pucel, R. Bera, and D . Masse, "Performance of G a A s M E S F E T mixers at X band", I E E E M T T - 2 4 , No . 6, pp. 351-359, 1976 [10] T. Hirota and H . Ogawa, " A novel Ku-band balanced F E T upconverter", I E E E M T T - 3 2 , N o . 7, pp. 679-683, 1984 [11] R. L . Vaitkus, "Uncertainty in the values of GaAs M E S F E T equivalent circuit elements extracted from measured two-port scattering parameters", I E E E C C H S S D C , pp. 301-308,1983 [12] HP8510A A N A owner manual, V o l . 1 , pp. 1-85 to 1-95 [13] C. Rauscher, " Frequency doublers with GaAs FETs" , I E E E M T T - S Digest, pp. 280-282, 1982 [14] T. Kawai and F J . Rosenbaum, "Simple analytical model of GaAs M E S F E T non-linear behaviour", I E E E M T T - S Digest, pp. 103-106, 1987 [15] T. Kacprzak and A . Materka, "Compact D C model of GaAs FETs for large-signal computer calculation", I E E E JSSC SC-18, No. 2, pp. 211-213, 1983 [16] W . Curtice, " A M E S F E T model for use in the design of GaAs integrated circuits", I E E E M T T - 2 8 , No. 5, pp. 448-456, 1980 [17] M . A . Smith et al, "RF nonlinear device characterization yields improved model-ing accuracy", I E E E M T T - S Digest, pp. 381-4,1986 - 7 3 -R .A. Minasian, "Modeling D C characteristics of dual-gate GaAs M E S F E T s " , I E E Proceedings, vol . 130, part I, No. 4, pp. 182-186, 1983 -74-APPENDIX A: THE CLASSICAL MIXER THEORY This appendix gives an overview of the mechanics of the classical mixer theory and makes a parallel between the conversion matrix and the interconnected equivalent cir-cuits which allows an intuitive representation of approximations made in this work. A - l : Mathematical formulation First, the time-domain solution of a F E T equivalent circuit must be obtained. The characterization of each nonlinear element of the circuit as a function of the controlling voltages can be performed by various methods: direct measurement, analytical models with parameters to be extracted from measured DC and R F data, or from S parameters measured at different bias voltages. F ig . A . l depicts the extrinsic F E T network to be analyzed. The embedding impedances are included at each port. The input voltage level and frequency are set and using a numerical iterative technique such as the Figure A . l : Nonlinear F E T equivalent circuit Cgd(Vg,Vd) Zg(w) + v 9 Cgs(Vg,Vd) Rds(Vg,Vd) gn(Vg,Vd)*Vg I Vd Cds(Vg,Vd) Zd(w) - 7 5 -Harmonic Balance method, the circuit is solved for the two controlling voltages Vg and Vd; this represents the large-signal or pump solution. Given the latter which implicitly includes contributions from all the defined nonlinear elements and the equations relating these elements to the voltages, the time dependence of each element can be calculated: its period is equal to that of the pump. Wi th <&p denoting the pump (LO) radian fre-quency, each defined nonlinear element (z,) can be expressed in a complex Fourier series as: *,-(0= iw**' (1) Now, assume that a small-signal v(t) of frequency u) is impressed on the F E T . B y the mixing action of z;(0> sideband currents ( = v (:) z ,(0) w i l l be created at frequencies: co„ = co + n (£>p (2) with n taking all integer values. We can now proceed to the small-signal solution of the mixer problem. Each of the Fourier components of Equation (1) can be included in the frequency-domain equivalent circuit as voltage-controlled current sources (for example). This is depicted in F ig . A.2. A loop analysis of this circuit considering all the different frequencies but where each transfer relation calculated (IF at gate to IF at drain, IF at gate to R F at drain, etc.) uses only the corresponding controlled sources (one per nonlinear element) then yields: [ £ ] = [Z m ] [ / ] + [Z,][/] (3) where [E] is the input signal(s) vector, [Z,] is the sideband termination matrix (diagonal), and [Zm] the results of the loop analysis. The row numbering is arbitrary and corresponds to frequency and port assignments. If the desired output frequency is the result of the subtraction of the L O frequency with v(t)'s frequency, then the complex conjugate of v(t) must be used for the calculation of the small-signal solution. Solving for a given side-band requires to calculate the corresponding term of [I] (here denoted by I„ , for output current). The available conversion gain CGm is expressed as: \I0\2Re[Z0]Re[Zin] CGm=4 — 2 (4) and holds for any desired sideband. Since the F E T has two ports and considering k sig-nals (input and sidebands) for the analysis, [Zm] has (2k)2 elements. For practical reasons the number of elements of the matrix (number of sidebands) is reduced. Generally, only the image, the R F and the IF are considered. - 7 6 -Figure A.2: FET equivalent circuit with element harmonics A-2: Equivalent circuit interconnections The conversion matrix can be represented by a series of cross-coupled frequency-selective equivalent circuits because the same I/V equations hold for both. First, Fig. A.3 shows the subdivided conversion matrix obtained from Fig. A.2 with only the IF and RF signals considered when its elements have been positioned to present more clearly the IF/RF port impedance relations. Fig. A.4 depicts the equivalent circuits representation of this matrix. Only the transconductance and the drain-source resistance (the main non-linearities of a MESFET) are included for simplicity. The source feedback is also neglected for this discussion. The use of these frequency-selective equivalent circuits allows a simple representation of the conversion matrix in frequency-domain C A D pro-grams. Various signal interactions can be visualized in a simple fashion. For instance, Fig. A.5 depicts the case of the lower sideband (LSB) to upper sideband (USB) interac-tion. As apparent, the USB can only be affected from the transconductance via two feed-back couplings: one at LSB generating an inverse conversion to IF, and one at IF creat-ing a new voltage component across the gate-source capacitance, which then perturbs USB. Likewise, LSB is perturbed following a similar path from the USB circuit How-ever, the drain-source resistance couples these two via the IF drain voltage. Clearly, with the good gate-drain isolation afforded by MESFETs, the low IF frequencies usually involved, and the proper IF drain termination, this perturbation is negligible. -77-Figure A .3: Conversion equations and diagram l'.IF port 1 port 2 4;RF 13 3«IF 14 Zt3 S7 \7 Zt4 S7 [E] = Z i l Z j 2 Z j 3 z Z 2 1 ^22 ^23 z Z 3 2 Z 3 3 z Z41 Z 4 2 Z 4 3 z, Z11 Z u Z i 2 z z 3 1 Z33 2 32 z Z 2 i Z23 Z ^ z z 4 1 Z 4 3 Z 4 2 z, 14 [ZLF] [ZIFIRF] [ZRF/IF] [Zgp] h + J L J lx h ' 2 + u Z.1 W2 W3 W4 Z,3 W2 ^4 H-MH / l ' 2 '3 / 4 • / l h In a similar fashion, the effect of the second LO harmonic on the upper sideband (USB) conversion can be visualized, and this is shown in Fig. A.6. In this case, the third-order characteristics of the FET is of interest, represented by the second harmonic of the nonlinear elements. Now, the lower sideband (LSB) and the USB are coupled by only one feedback via the transconductance, since 2 L O - LSB = USB, but they are cou-pled directly via the drain-source resistance by the same relation. With sizeable second harmonic levels, this will yield larger discrepancies, especially as the operating fre-quency is increased and as large drain voltage swings occur. Fig. A.7 depicts the conversion matrix and the resulting RF/TF circuit interconnec-tions that arise from the present method and its approximations. Apart from neglecting the influence of the LSB and of the drain-source resistance (because of the IF drain short-circuit), only the reverse transfer RF/TF coupling terms are omitted, an approxima-tion which is quite reasonable given the frequencies involved and the relatively good gate/drain isolation of MESFETs. -78-Figure A . 4 : Conversion equations circuit representation Figure A.5: LSB/USB interaction -79-Figure A.6: Second L O harmonic effects V Q U S I 31 VQIF If 8"1 gnO 9*> VdlF- , ©©0 4= VgLSI ©ffi©' VdLSB 000 i Figure A.7: Approximations of this method [E] = r [zfi to] v 8ir 0 v<or rdO ©4= sc 80-APPENDIX B: H I G H F R E Q U E N C Y S I M U L A T I O N I M P R O V E M E N T B - l : Arbitrary loading at R F For conceptual simplicity and ease of calculations, the case of gate and drain 50 Q, loading at the upper sideband frequency was chosen as a basis for determining the mix-ing transconductance and for subsequent simulations. This approach should be satisfac-tory when relatively low frequencies are being used since G a A s M E S F E T s have inherently good gate-to-drain isolation. However, in the general case and particularly at higher frequencies when the gate and drain terminations are not 50 Q , e.g. for conjugate matching, this representation is not accurate enough. The calculated S22 can be substan-tially different from the measured one when S 1 2 is finite and sizeable. Therefore, the "time-averaged" transconductance (the one corresponding to the first term of the tran-sconductance Fourier series) is added to the original IF /RF circuit. This is shown in Fig . B . l . The time-averaged transconductance is simply equal to the value obtained from the large-signal S parameter measurements. The correction to the mixing transconductance (gmMIX) is done as follows: In the circuit of F ig . 10, from Equation (3), IS211 is written as: \=I(FRF)X(ZG (1) where ZG and ZD are the gate and drain loading impedances, respectively. When consider-ing the circuit of F ig . B . l , l(FRFy = gmMIX'VCgs(FjF) (2) where VCgs is the gate-source capacitance voltage, so that \S2l\' = I(FRF)'Y(ZGZD,FRF) (3) N o w whenZ c =ZD =50 Q, IS 2il '= IS21I, and pmMix,• _ „mMix(V LO y LO\ X(50, 50,FRP) gm -gm (VCgs ,VRds ) y ( 5 0 5 0 F r f ) (4) The circuit of F ig . B . l can now be used with gmMfX' for any type of gate and drain ter-mination at R F . B-2: IF voltage scaling Again for simplicity in the calculation procedures with Touchstone, the gate-source capacitance voltage at IF (VCgs(F1F)) was fixed to 1 to determine Equation (7). In a realis-tic situation, the value of this voltage is dependent on the gate and drain impedances at IF and on its frequency response over a desired bandwidth. The original experiments lead-ing to the gmMIX expression were conducted at an IF of 70 M H z with the drain shoit-- 81 -circuited and a broadband 50 Q source. VCgs(F1F) is then corrected for the new IF fre-quency and gate/drain impedances: T / / T? \new loads ' VCgs(lQMHz)shor,-circuit -82-oo Cgd Cgol RF - 0 50 Vcgs; Rl Cgs g n * V c g s Rds gmmlx* r i V c 8 s ( Cds Ls V V Figure B . l : Modified RF/TF circuit for arbitrary loadings APPENDIX C: LISTING O F P R O G R A M T O C A L C U L A T E T H E BEST D A T A FIT 10 R E M 12/02/87 B A S I C P R O G R A M T O P E R F O R M M U L T I V A R I A B L E 20 R E M L I N E A R R E G R E S S I O N A N D F I N D T H E P A R A M E T E R S G I V I N G T H E 30 R E M M I N I M U M O F A N E R R O R F U N C T I O N B Y A G R I D S E A R C H . 35 R E M U S E S HP9836 C O M P U T E R W I T H B A S I C 3.0 M A T S T A T E M E N T S . 40 R E M U P T O 100 D A T A POINTS C A N B E I N P U T . 50 R E M N U M B E R O F D A T A POINTS M U S T B E L A R G E R T H A N N U M B E R O F 60 R E M V A R I A B L E S . 70 R E M F O R U P C O N V E R T E R M L X I N G T R A N S C O N D U C T A N C E A N A L Y S I S . 80 R E M D A T A N E C E S S A R Y : E X P E R I M E N T A L C O N V E R S I O N G A I N A N D 90 R E M C O R R E S P O N D I N G Vcgs, Vrds, A N D T H E I R P H A S E 100 R E M D I F F E R E N C E I N THIS O R D E R . 110 ! 120 O P T I O N B A S E 1 130 D E G 140 I N T E G E R J ,K, Choice 150 Nvar = 3 ! number of independent variables 160 ! dimensioning data arrays 170 D I M Coeff_arr(Nvar,Nvar), Yval_arr(Nvar) ,Reg_res(Nvar) 180 DIMData_arr(100,Nvar),Dum2_arr(10,100), Vrc_arr(100) 190 D I M Dum3_arr(10,10), Dum4_arr(10,10), Dum5_arr(10,l) 200 D I M Err_arr(100), Pol_coef(4), Index_kpt(5), Val_arr( 100,4) 210 ! 220 ! 230 B E E P 200, .2 240 I N P U T " E N T E R # O F D A T A POINTS ", Ndata 250 I N P U T " E N T E R N A M E O F D A T A F I L E ", File_name$ 255 I N P U T " E N T E R S21 T O G M M I X P R O P O R T I O N A L C O N S T A N T " , Sgm 260 ! 270 R E D I M Data_arr(Ndata,Nvar), Ord_arr(Ndata), Val_arr(Ndata,4) 280 R E D I M Est_arr(Ndata),Err_arr(Ndata),Vrc_arr(Ndata) 290 ! 300 ! reads data file 310 A S S I G N @Data_read T O File_name$ 320 E N T E R @Data_read;Val_arr(*) 330 A S S I G N @Data_read T O * 340 ! calculates gmmix and Vrds*cos(delta) 350 F O R J=l T O Ndata 360 Ord_arr(J)=Sgm*(10"(Val_arr(J,l)/20)) 370 Vrc_arr(J)=ABS(Val_arr(J,3)*COS(Val_arr(J,4))) 380 N E X T J 390 ! 400 Memse = 1 ! initial value for error function 405 ! main loop - 8 4 -410 F O R R=0 T O 1 S T E P 0.1 420 F O R L=2 T O 4 S T E P 0.4 430 F O R P= l T O 3 S T E P 0.4 440 DISP "R=";R;"L=";L;"P=";P 450 F O R J=l T O Ndata ! fills arrays for regression 460 Data_arr(J,l)=Val_arr(J,2rR 470 Data_arr(J,2)=Vrc_arr(J)X 480 Data_arr(J,3)=Vrc_arr(J)T 490 N E X T J 500 G O S U B Linreg ! go calculate regression 510 ! 520 IF Se < Memse T H E N ! stores parameters for min 530 Index_kpt(l)=R 540 Index_kpt(2)=L 550 Index_kpt(3)=P 560 Pol_coef(l)=Reg_res(l) 570 Pol_coef(2)=Reg_res(2) 580 Pol_coef(3)=Reg_res(3) 590 1 Pol_coef(4)=Se~0.5 600 Memse = Se 610 E N D IF 620 N E X T P 630 N E X T L 640 N E X T R 650 ! 660 P R I N T 670 P R I N T " B E S T C O M B I N A T I O N F O U N D IS: L= ";Index_kpt(l);"P="; Index_kpt(2);"R=";Index_kpt(3) 680 P R I N T 690 P R I N T " C O E F F I C I E N T S A R E : ";Pol_coef(l), Pol_coef(2), Pol_coef(3) 700 P R I N T " S T A N D A R D E R R O R :";Pol_coef(4) 710 G O T O 870 720 ! 730 Linreg: ! calculates the linear regression 740 M A T Dum2_arr = TRN(Data_arr) 750 M A T Dum3_arr = Dum2_arr * Data_arr 760 M A T D um4_arr = INV(Dum3_arr) 770 M A T Dum5_arr = Dum2_arr * Ord_arr 780 M A T Reg_res = Dum4_arr * Dum5_arr 790 ! 800 ! Calculates the standard error of estimate 810 M A T Est_arr = Data_arr * Reg_res 820 F O R J=l T O Ndata ! calculates the error function 830 Err_arr(J)=(Est_arr(J)-Ord_arr(J))/Ord_arr(J) 840 N E X T J - 8 5 -850 Se = DOT(Err_arr,Err_arr)/(Ndata-Nvar) 860 R E T U R N 870 E N D - 8 6 -APPENDIX D: E Q U I V A L E N T CIRCUIT E L E M E N T ACQUISITION W I T H T O U C H S T O N E 19/21/87 Fi le to fit an equivalent circuit to the measured Spar of a ! single-gate F E T circuit with simple parasitics for upconverter modelling V A R R g # 0 8.36680 15 R d # 0 7.52852 15 Rs # 0 3.45270 10 L g # 0 0.63350 1 L d # . 0 0.58499 1 L s # . 0 0.05455 .5 C i n # 0 0.23099 .7 Cout# 0 0.20792 .5 C l # 0 . 1 0.33006 .41 ! Cgs C2 # .01 0.02498 .07 ! Cdg C 3 # . 0 0.13315 .51 ! Cds R i # 0 17.40076 30 Rds # 150 161.12150 250 gm # .03 0.05023 .075 t = 0 ! drain load angles of maximum input reflection tetal = 57.2 ! ! coefficient @ 2.03 G H z and teta2 = 68.2 teta3 = 50.2 ! @ 1.39 G H z teta4 = 60.7 teta5 = 37.2 ! drain load angles of input reflection teta6 = 117.5 ! coefficient = 1 @ 2.03 G H z teta7 = 47.1 teta8 = 107.6 teta9 = 28.0 ! @ 1.39 tetalO =  127.1 tetal 1 =  34.6 tetal 2 = = 120.5 E Q N ! corresponding electrical lengths ea = (180-tetal)/2 eb = (180-teta2)/2 ec = (180-teta3)/2 ed = (180-teta4)/2 - 8 7 -ee = (180-teta5)/2 ef = (180-teta6)/2 eg = (180-teta7)/2 eh = (180-teta8)/2 ei = (180-teta9)/2 ej = (180-tetal0)/2 ek = (180-tetall)/2 el = (180-tetal2)/2 C K T s2pa 1 2 0 b:ne7001b ! measured S parameters def2p 1 2 nemod srl 1 2 r ' R g T L g ! equivalent circuit cap 1 0 c X i n fet 2 3 10 g'gm f t f=0 c g s X l ggs=0 r T R i cdg A C2 cdc=0 c d s X 3 rds'Rds srl 10 0 r~Rs F L s srl 3 4 r~Rd F L d cap 4 0 c 'Cout def2p 1 4 necktl ! reflection circuits to fix particular values of impedances necktl 1 2 tlin 2 4 z=50 e~ea f=2.03 shor 4 deflp 1 gamamaxl necktl 1 2 tlin 2 4 z=50 e"eb f=2.03 res 4 0 r=5.55556 deflp 1 gamamax2 necktl 1 2 t l i n 2 4z=50 e~ecf=1.39 shor 4 deflp 1 gamamax3 necktl 1 2 t l i n 2 4z=50e"edf=1.39 res 4 0 r=5.55556 deflp 1 gamamax4 necktl 1 2 tlin 2 4 z=50 e~ee f=2.03 shor 4 deflp 1 gammainl necktl 1 2 - 8 8 -tlin 2 4 z=50 e~eff=2.03 shor 4 deflp 1 gammain2 necktl 1 2 din 2 4 z=50 e'eg f=2.03 res4 0r=5.55556' • deflp 1 gammain3 necktl 1 2 tlin 2 4 z=50 e'en f=2.03 res 4 0 r=5.55556 deflp 1 gammain4 necktl 1 2 U i n 2 4z=50e*eif=1.39 shor 4 deflp 1 gammain5 necktl 1 2 tlin 2 4 z=50 e"ej f=1.39 shor 4 deflp 1 gammain6 necktl 1 2 tlin 2 4 z=50e A ekf= 1.39 res 4 0 r=5.55556 deflp 1 gammain7 necktl 1 2 t l i n2 4z=50e"elf=1.39 res 4 0 r=5.55556 deflp 1 gammain8 P R O C ! to calculate the error function for the S parameters moddif = necktl - nemod ratio = moddif / nemod O U T F R E Q sweep .15 2.480 .238 O P T ! goals for S parameters fit ratio mag[s l l ] = 0 ratio mag[sl2] = 0 ratio mag[s21] = 0 ratio mag[s22] = 0 - 8 9 -! goals for input reflection coefficient fit range 2.0299 2.0301 gamamaxl mag[s l l ] = gamamax2 mag[s l l ] = gammainl mag[s l l ] = gammain2 mag[s l l ] = gammain3 mag[s l l ] = gammain4 magfs l l ] = .11 .03 range 1.3899 1.3901 gamamax3 mag[s l l ] = 1.1 gamamax4 mag[s l l ] = 1.04 gammain5 mag[s l l ] = 1 gammain6 magfs l l ] = 1 gammain7 mag[s l l ] = 1 gammain8 mag[s l l ] = 1 - 9 0 -APPENDIX E : C O N V E R S I O N GAIN SIMULATIONS F O R S A M P L E 3 0 U ( ) 30 60 90 120 150 180 210 240 270 300 330 360 Reflection coefficient angle (deg) Fig. E-7: Mag = 0.8,0.6,0.3, F = 1.9 GHz, calculated - 9 6 -0 U<) 30 60 90 120 150 180 210 240 270 300 330 360 Reflection coefficient angle (deg) Fig. E-8: Mag = 0.8, 0.6, 0.3, F = 2 GHz, calculated - 9 7 -- • measured -a calculated 30 60 90 120 150 180 210 240 Reflection coefficient angle (deg) Fig. E-10: Mag = 0.6, F = 2.1 GHz 270 300 330 360 0 30 60 90 120 150 180 210 240 270 300 330 360 Reflection coefficient angle (deg) Fig. E - l l : Mag = 0.4,F = 2.1 GHz - 9 9 -APPENDIX F: F R E Q U E N C Y RESPONSE O F L O V O L T A G E S F O R T = 1 0.99-1 1 1 1 1 1 1 1 1 H 0.98 . 0.89 0 30 60 90 120 150 180 210 240 270 300 330 360 Reflection coefficient angle (deg) 9H 1 1 1 1 1 1 1 1 1 p 1 h Reflection coefficient angle (deg) Fig.F-l:Freq= 1 GHz - 1 0 0 -0.86 0 30 60 90 120 150 180 210 240 270 300 330 360 Reflection coefficient angle (deg) Fig. F-2: Freq = 3 GHz - 101 -- 102 --103-0.62 0.44-1 1 1 1 1 1 1 1 1 1 1 1 1 0 30 60 90 120 150 180 210 240 270 300 330 360 Reflection coefficient angle (deg) Reflection coefficient angle (deg) Fig. F-5: Freq = 9 GHz - 1 0 4 -0.60 0.56 0.52' 0.48 0.44 0.40-1 1 H 1 1 1 1 1 1 , , , i 0 30 60 90 120 150 180 210 240 270 300 330 360 Reflection coefficient angle (deg) 5H . , , , , , , , , , , , Reflection coefficient angle (deg) Fig. F-6: Freq = 10 GHz - 105-0.58 0.34-1 1 1 1 1 1 1 1 1 1 1 1 [ 0 30 60 90 120 150 180 210 240 270 300 330 360 Reflection coefficient angle (deg) 5 Reflection coefficient angle (deg) Fig. F-7: Freq = 12 GHz - 106-APPENDIX G : D E R I V A T I O N O F MIXING T R A N S C O N D U C T A N C E EXPRESSION F R O M A L I N E A R M O D E L In this appendix, I derive the expression for the second term of the Fourier series of the transconductance obtained form a quasi-static M E S F E T model [16]. The original drain-source current expression of reference [16] is slightly modified in this context and is written as: IDS = V(VG-Vp)2 (l + XVD)tmh(yVD) (1) where Vp is the terminal pinch-off voltage (the equivalent of VT of [16]), VG is the gate voltage, VD is the drain voltage, and where the other parameters have their usual mean-ing. The transconductance gm is defined as: gm = v. (2) and from (1), its expression is gm = 2p (yG - Vp) (1 + XVD) tanh(y VD) (3) N o w let Vp be replaced by Vp' = Vp(l + aAVD) to model the pinch-off voltage shift, in which AVD = VD - VDD0 (VDD0 is the drain bias voltage at which Vp is measured) and a is the linear pinch-off voltage shift factor. Expressing VG as VG(t) = VGG+Acos((at), where VGG is the gate bias, and VD as VD(0 = VDD0+Bcos(co/ +$), where 0 is the phase of VD(t) relative to VG(t), and inserting these in (3) gives: VGG + Acos (mt) - V - aVpBcos (at + <$) ^ 1 + X(Bcos(cor + + VDD0)^ tanh y(VDDQ + Bcos(cof + x 40) (4) Expanded as a complex Fourier series, gm(t) can be written as: gm(t)= X mkeiak' where (5) gmk = ±jgm(t)e-;°*'d cor (6) - 107 -A t this point, a simplification is necessary in equation (4) in order to carry out the integrations analytically. B y noting that tanh y(VDDQ + Bcos(u)t + <(>)) tanhjyV^Bo f + tanh yBcos((M + <(>) • l + tanh^yV^o tanh yBcos((£*t + <J))j (7) and i f the F E T is operated wel l in its current saturation region, then tanh|yVflBo = l so that (7) = l . For k = 1, Equation (4) is inserted in Equation (6) and g m i = n l[Vca +Acos(VO-Vp-aVpBcos{m + <(>)j [ l + \(yDD0 + Bcos(,w + <)>))) e'^dm (8) This integral can be separated in two parts: gm* = ^  J \VGG + ACOS(COO - VP - o%Bcos(ow + 4>)1 (1 + \VDD0)e-JCO,d<nt (9) g m * = n I [VcG + A C O S ( C 0 ? )-VP-*VPB cosC"' + *) \ } B cos(ow + *)] e-J<0,dm (10) With COS(GW) = (11) M * = -^U + WDDO)][A +Ae-2Ja* -cVpBe^-cVpBe-^-^ + Vcae-^-Vpe~iw\ dat (12) This is easily evaluated, and gives gmi = P (1 + WDDd (A -aVpBe'*) Likewise, gmf is evaluated using (11) and simply equals 0. Hence, (13) gmi = P (1 + kVDD0) (A - oVpBej*) (14) - 108-W e want to find the angle <{> at which gmx w i l l be rninimized, corresponding to the case of maximum mixing transconductance degradation due to the drain voltage. The modulus of gmx is: B y inspection, this term is maximum at <J> = TI and minimum at <j> = 0. However, since Vp is negative, gmx becomes minimum at <)> = %. Hence this simple formulation using a linear (gatewise) transconductance with a linear pinch-off shift factor shows that the calculated 7t phase shift between drain and gate voltages would lead to maximum drain voltage interference. Furthermore, it shows that a close correlation exists between a common quasi-static expression (Eq. (16)) and the mixing transconductance function we have experimentally obtained in this work, both involving the magnitude of the voltages and the cosine of their phase difference. (15) Expanding the rightmost bracketed term gives: A 2 - 2A cVpB cos<(> + c^VJtB 2 (16) - 1 0 9 -APPENDIX H : U P C O N V E R T E R S I M U L A T I O N W I T H T O U C H S T O N E 3/15/88 File to allow optimization of output circuit in the design of F E T upconverters by calculating the dependence of a mixing transconductance on L O voltages as well as matching and filtering at the chosen sideband. A l l the signals' equivalent circuits are considered here: an IF circuit to calculate the IF coupling on the gate cap, that subsequently scales the gmmix expression; an L O circuit which is used to calculate the internal driving voltages given the output circuit used and which links them to gmmix; an R F circuit which is used with a dummy input voltage source to calculate the conver-sion gain when the mixing source is included V A R R g = 7.8637 R d = .29302 Rs = 7.08732 L g = .04031 L d = .2069 L s = .1228 C i n = .31203 Cout = .31017 Cgs = .391 Cgd = .01948 Cds = .09327 R i = 17.92754 Rds = 138.5854 gm = .06317 11 = 1.316801 12 = 44.48747 13 = 98.21057 c l =6 c2 = .212947 ifvol = .9979 scal l = 1.3049 ! time-averaged transconductance ! drain matching network ! IF voltage coupling on Cgs at IF ! gmmix expression scaling factor exp l = .7 ! parameters of the gmmix expression exp2 = .2 exp3 = 2.9 - 110-coef1 = .030288 coef2 = -.01012858 coef i = -.00006069084 vcg = 1.504 ! calculated L O voltages vrd = 7.8 teta = 194.95 ! phase difference E Q N vrdc = -vrd * cos(teta) / 2 gmm = coefl * (vcg /2)**expl + coef2 * vrdc**exp2 + coef3 * vrdc**exp3 gmmix = gmm * ifvol * scal l C K T pic 1 0 H I c^cl ! matching network derived earlier ind 1 2 T12 ind 2 0 T13 cap 2 3 c~c2 def2p 1 3 matchnet srl 1 2 r^Rg T L g ! F E T common to IF, LO,and R F cap 1 0 c ' C i n vccs 2 3 5 10 m A gm a=0 r l=0 r2~Rds f=0 t=0 ! time-average source cap 2 5 c 'Cgs cap 2 3 c ' C g d cap 3 10 c 'Cds res 5 10 r"Ri srl 10 0 r 'Rs T L s srl 3 4 r~Rd T L d cap 4 0 c X o u t opamp 5 2 20 5 0 m= 1 a=0 r 1 =0 r2=0 r3=0 r4=0 f=0 t=0 ! cgs probing opamp 10 3 25 10 0 m=l a=0 r l=0 r2=0 r3=0 r4=0 f=0 t=0 ! rds probing vccs 50 3 0 10 m'gmmix a=0 r l=0 r2=0 f=0 t=0 ! mixing source def5p 1 20 25 50 7 comfet comfet 1 2 3 4 5 matchnet 5 6 match 6 match 4 def3p 1 2 3 lorefl ! circuit for L O voltages calc comfet 1 2 3 4 5 - I l l -short 5 match 4 match 3 def2p 1 2 ifcoup comfet 1 2 3 4 5 match 1 match 2 match 3 def2p 4 5 rfupc O U T ifcoup mag[s21] lorefl s21 lorefl s31 rfupc db[s21] rfupc db[s22] F R E Q step .07 .28 sweep 1.57 1.82 .05 sweep 1.85 2.1 .05 ! circuit for calculation of Vcgs at IF ! gate term at R F ! circuit for IF to R F conversion calc ! mag Vcgs at IF ! Vcgs, mag and phase at L O ! Vrds, mag and phase at L O ! conversion gain ! return loss at output ! IF frequencies ! L O band ! R F band - 112-

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                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            src="{[{embed.src}]}"
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                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
                            data-width="{[{embed.width}]}"
                            async >
                            </script>
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