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GaAs MESFETS and their applications in digital logic and digital to Analog conversion 1985

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GaAs MESFETS AND THEIR APPLICATIONS IN DIGITAL LOGIC AND DIGITAL TO ANALOG CONVERSION by IBRAHIM MOHAMED ABDEL-MOTALEB B.Sc. i n E l e c t r i c a l Engineering, Cairo U n i v e r s i t y , 1976; B.Sc. i n Phy s i c s , Cairo U n i v e r s i t y , 1979; M.Sc. U n i v e r s i t y of Manitoba, 1982. A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY IN THE DEPARTMENT OF ELECTRICAL ENGINEERING We accept t h i s t h e s i s as conforming to the req u i r e d standard THE UNIVERSITY OF BRITISH COLUMBIA November, 1985 © Ibrahim Mohamed Abdel-Motaleb, 1985 ?9 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives, it is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of B UctrioJ- |* * * t r T M j The University of British Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 Date NOV-jfts W2S~~ Dr. Lawrence Young ABSTRACT The purpose of the work described i n t h i s t h e s i s was to study the use of GaAs MESFETs i n d i g i t a l l o g i c and d i g i t a l to analog conversion. A part of t h i s work was to t e s t ideas by a c t u a l l y f a b r i c a t i n g GaAs MESFET devices i n our l a b o r a t o r y by implanting S i i n t o LEC SI GaAs. I n i t i a l l y , the Rockwell " i o n implanted planar process" was used. With t h i s process high source and d r a i n r e s i s t a n c e r e s u l t when the magnitude of the threshold voltage i s reduced. A recessed gate process was then t r i e d i n order to reduce the s e r i e s r e s i s t a n c e , but i t was d i f f i c u l t to c o n t r o l i n order to achieve an acceptable u n i f o r m i t y . Sadler's s e l f - a l i g n e d gate technique was then t r i e d but an acceptable y i e l d was found to be hard to achieve. Based on the experience w i t h the above methods, a S e l f A l i g n e d Gate Technique Using Polyimide (SAGUPI) was developed. Using t h i s technique i t was found to be p o s s i b l e to reduce the s e r i e s r e s i s t a n c e of the t r a n s i s t o r and achieve acceptable y i e l d s and u n i f o r m i t i e s . The c h a r a c t e r i s t i c s of devices f a b r i c a t e d using the i o n implanted planar process were measured. The t r a n s i s t o r I-V c h a r a c t e r i s t i c parameters, Schottky and ohmic contact parameters and implanted r e g i o n parameters were measured at room temperature and as a f u n c t i o n of temperature over the range from -80°C to 80°C. I t was found that no l a r g e change i n the speed of the c i r c u i t occurs over t h i s range. A new d i g i t a l l o g i c (the Common Drain FET L o g i c , CDFL) was developed f o r the a p p l i c a t i o n i n U l t r a High Speed Very Large Scale of I n t e g r a t i o n . The performance of the new l o g i c was compared w i t h that of other GaAs MESFET l o g i c using computer s i m u l a t i o n . The s i m u l a t i o n r e s u l t s showed that the i i CDFL has p o t e n t i a l f o r meeting the UHS VLSI requirements. Two 3 b i t D i g i t a l to Analog Converters (DAC) (one with MESFETS as current sources and the other wit h saturated r e s i s t o r s ) were developed. MESFETs gave b e t t e r current source c h a r a c t e r i s t i c s than saturated r e s i s t o r s . i i i TABLE OF CONTENTS ABSTRACT i LIST OF SYMBOLS v i LIST OF TABLES . i x LIST OF FIGURES x i LIST OF ACRONYMS x v i ACKNOWLEDGEMENTS x v i i i (1) INTRODUCTION 1 (2) REVIEW ON GaAs DEVICES AND TECHNOLOGIES 7 2-1 GaAs MESFETs 8 2-2 GaAs Saturated R e s i s t o r 12 2-3 GaAs Schottky diode 14 2-4 R e s i s t o r s 16 2-5 Major F a b r i c a t i o n Steps f o r Ion-implanted GaAs MESFETs 18 (a) Substrate P r e c l e a n i n g 20 (b) Ion Implantation 20 (c) Annealing 23 (d) Ohmic Contact M e t a l l i z a t i o n 26 (e) Schottky Contact M e t a l l i z a t i o n 26 ( f ) F i r s t and Second L e v e l of M e t a l l i z a t i o n 27 2-6 GaAs I . C s Technologies 28 (a) The Planar Ion-implanted Technique.. 28 i v (b) The Recessed Gate Technique 30 (c) The Pt Gate Technique 30 (d) S e l f - A l i g n e d Gate Techniques 32 ( i ) S e l f - A l i g n e d Implantation f o r n+ Layer Techniques (SAINT) 33 ( i i ) R e f r a c t o r y Metals S e l f - A l i g n e d Gate Techniques 36 (3) DEVICE AND CIRCUIT FABRICATION 40 3-1 The Chip Layout 40 3- 2 F a b r i c a t i o n Processes 44 (a) The Planar Ion-implanted Technique 45 (b) Recessed Gate Technique 58 (c) S e l f - A l i g n e d Gate Using Polyimide (SAGUPI) 64 (4) DC MEASUREMENTS 73 4- 1 Implantation Through S i 3 83 4- 2 Temperature Measurements 92 (5) COMMON DRAIN FET LOGIC (CDFL) 112 5- 1 Review Of GaAs D i g i t a l Logic Approaches 112 (a) Depletion Mode FET Logic 112 ( i ) The Buffered FET Logic (BFL) 112 ( i i ) Schottky Diode FET Logic (SDFL) 114 ( i i i ) SDFL With Push P u l l B u f f e r 117 ( i v ) Capacitor Coupled Logic (CCL) 117 (v) Feed Forward S t a t i c Approach (FFS) 120 v (b) Enhancement Mode FET Logic 120 ( i ) Directly Coupled FET Logic (DCFL) 120 (c) Quasi-normally-off approach 123 (1) Low Pinch-off FET Logic (LPFL) 123 ( i i ) Source Coupled FET Logic (SCFL) 126 5-2 The Common Drain FET Logic (CDFL) 128 5- 3 Fabrication Process And Experimental Results 137 (6) COMPUTER SIMULATION OF GaAs DIGITAL LOGIC 145 6- 1 The Deep Depletion Group (Group #1) . 147 6-2 Low Power Depletion Mode Logic (Group #2) 153 6- 3 Normally and Quasi-normally Off Mode Logic (Group #3) 155 (7) THREE BIT GaAs DIGITAL TO ANALOG CONVERTER (DAC) 160 7- 1 Fabrication Process and Measurement 164 7-2 Evaluation of the Saturated Resistor as a Load and a Current Source 171 (8) CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK 174 REFERENCES 177 APPENDIX(A) Computer Simulation Program of the CDFL Approach... 184 APPENDIX(B) Computer Simulation Programs for GaAs MESFET Logic Approaches • •••• 1**5 APPENDIX(C) Recipes for GaAs Fabrication Processes 1 9 4 v i LIST OF SYMBOLS a (m) channel thickness * a (m) effective channel thickness A (m2) area ** A (cm2/K2) effective Richardson constant C (F/ffl ) capacitance per unit area C (F) gate capacitance 8 C j (F) gate drain capacitance (F) gate source capacitance C (F) load capacitance d (m) pad length G (S) total conductance g (S) channel conductance d g (S) transconductance m I, (A) drain source current ds I. (A) saturation drain source current dsat Ij (A) forward bias current I (A) saturation current s (A/m2) forward current density J g (A/m2) saturation current density k Boltzmann's constant JJ, (m) length of the space between pads L (m) length of the source drain separation c L^ (m) transfer length N (cm - 3) electron concentration v i i n i d e a l i t y f a c t o r n' (cm - 3) peak im p u r i t y d e n s i t y (cm - 3) c o n c e n t r a t i o n of the i o n i z e d donor atoms P (W) power q (C) charge of the e l e c t r o n R Q ( Q ) contact r e s i s t a n c e R,j ( Q ) d r a i n r e s i s t a n c e R„ (Q) end r e s i s t a n c e (m) p r o j e c t e d range R g (Q) source r e s i s t a n c e RSH sheet r e s i s t a n c e R O V . ( Q ) sheet r e s i s t a n c e of the l a y e r d i r e c t l y under the contact R T ( Q ) t o t a l r e s i s t a n c e T^K^ temperature V . ( V ) drain-source voltage ds ( V ) forward voltage ( V ) f u l l s c a l e output voltage V • ( V ) g a t e - d r a i n voltage 8 d V ( V ) gate-source voltage gs ( V ) i n p u t voltage V ( V ) voltage swing m V Q ( V ) output voltage V p (V) p i n c h - o f f voltage V ( V ) s a t u r a t i o n voltage sat v i i i V k (V) t h r e s h o l d v o l t a g e W (m) pad width (m) d e p l e t i o n r e g i o n w i d t h W (m) gate width 8 (A/V2) transconductance parameter e (T/cm) p e r m i t t i v i t y T) {%) e f f i c i e n c y u (cm2/Vs) m o b i l i t y p (Q/cm) s p e c i f i c r e s i s t a n c e p c (Q/cm 2) contact s p e c i f i c r e s i s t a n c e Op (m) standard d e v i a t i o n i n p r o j e c t e d range (s) delay time $ '( i o n s / c m 2 ) f l u e n c e of the a c t i v a t e d atoms <j> (ions/cm 2) implanted dose <j)b (V) b a r r i e r height i x LIST OF TABLES Table(3-1) Implanted dose and energy; and the r e s u l t a n t t h r e s h o l d voltage 49 Table(3-2) E f f e c t of d i f f e r e n t treatments p r i o r to the d e p o s i t i o n of Table(4-1) Simulation parameters f o r 2p,m gate and f a t FET t r a n s i s t o r s from sample/M. 77 Table(4-2) S p e c i f i c ohmic contact r e s i s t i v i t y p c (ohm/cm2) 86 Table(6-1) T r a n s i s t o r s parameter used to simulate groups#l, 2, 3... 148 Table(6-2) S i m u l a t i o n r e s u l t s of GaAs d i g i t a l l o g i c 150 x LIST OF FIGURES Fig.(1-1) Steady s t a t e v e l o c i t y - f i e l d c h a r a c t e r i s t i c s f o r e l e c t r o n s i n S i and GaAs 2 Fig.(2-1) MESFETs s t r u c t u r e (a) d e p l e t i o n mode and (b) enhancement mode y Fig.(2-2) Saturated r e s i s t o r (a) s t r u c t u r e and (b) I-V c h a r a c t e r i s t i c s 13 Fig.(2-3) Schottky diode (a) s t r u c t u r e and (b) I-V c h a r a c t e r i s t i c s . 14 F i g . (2-4) Ion-Implanted r e s i s t o r 17 Fig.(2.5) Measured (from C-V measurements) and c a l c u l a t e d e l e c t r o n c o n c e n t r a t i o n p r o f i l e s f o r S, S i and Se implants 22 Fig.(2-6) E l e c t r o n c o n c e n t r a t i o n p r o f i l e s f o r SI GaAs samples implanted and annealed at 850°C f o r 30 minutes w i t h caps as i n d i c a t e d 24 Fig.(2 - 7 ) Ion-implanted planar process 29 Fig.(2-8) Plessey f a b r i c a t i o n process 31 F i g . (2-9) SAINT process 34 F i g . (2-10) TiW s e l f a l i g n e d gate process 38 Fig.(3-1) Chip mask layouts (a) r e g i s t r a t i o n marks, n, n + , and ohmic contact m e t a l l i z a t i o n ; (b) gate, f i r s t l e v e l m e t a l l i z a t i o n , v i a holes 41 F i g . (3-2) Chip layout 43 Fig.(3-3) Ion-implanted planar f a b r i c a t i o n process adapted at UBC. 46 x i Fig.(3-4) Photograph of a l i f t e d o f f S i ^ f i l m a f t e r annealing.... 50 Fig.(3-5) S i n g l e l i f t o f f procedure 53 Fig.(3-6) SEM micrograph of the t e s t and monitoring devices 55 Fig.(3-7) I-V c h a r a c t e r i s t i c s of (a) 2um gate and (b) f a t FET t r a n s i s t o r f a b r i c a t e d using the ion-implanted planar process 56 F i g . ( 3 - 8 ) V , and I histograms f o r sample #4 57 ° t h sat & r F i g . ( 3 - 9 ) Recessed gate process adapted at UBC 59 Fig.(3-10) I-V c h a r a c t e r i s t i c s of (a) 2 m̂ gate and (b) f a t FET t r a n s i s t o r s f a b r i c a t e d using the recessed gate process... 61 F i g . (3-11) V f c h and I t histograms f o r sample D7 63 Fig.(3-12) S e l f - a l i g n e d gate technique using polyimide (SAGUPI) 65 Fig.(3-13) I-V c h a r a c t e r i s t i c s of (a) 2 m̂ gate and (b) f a t FET 68 Fig.(3-14) V and I histograms f o r sample E7 69 Fig.(3-15) SEM micrograph f o r gate undercut a f t e r 0^ plasma e t c h i n g of polyimide 70 Fig.(4-1) ~ / I d s vs V g g f o r a f a t FET t r a n s i s t o r 75 Fig.(4-2) Experimental and simulated I-V c h a r a c t e r i s t i c s of (a) 2̂ m gate and (b) f a t FET t r a n s i s t o r s f o r sample #4 76 F i g . ( 4 - 3 ) Ln(I ) v s . V f o r a f a t FET 79 Fig.(4-4) Transmission Line Model (TLM) (a) p l o t of t o t a l contact to contact r e s i s t a n c e and (b) experimental measurements f o r o b t a i n i n g the t o t a l r e s i s t a n c e and the contact end r e s i s t a n c e value 80 x i i F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . F i g . 4-5) M o b i l i t y p r o f i l e s f o r sample #2 and sample #4 84 4-6) E l e c t r o n c o n c e n t r a t i o n p r o f i l e s f o r sample #2 and sample //4 85 4-7) and I a t histograms f o r sample #1 88 4-8) M o b i l i t y p r o f i l e f o r sample #1 90 4-9) E l e c t r o n c o n c e n t r a t i o n p r o f i l e f o r sample #1 91 4-10) V u vs. T 93 th 4-11) I v s . T 94 sat 4-12) B v s . T 95 4-13) g at V =0 V and V, =3 V vs. T 97 m gs ds 4-14) g u at V =0 V and V, =0 V vs. T 98 ' °d gs ds 4-15) l n ( J g ) vs T 100 4-16) n vs . T 101 4-17) $ b v s . T 102 4-18) C vs. T 103 gs 4-19) g at V =0 V and V J =0.05 V vs. T 104 °m gs ds 4-20) G at V =0 V and V 0 =0.05 V vs. T 105 gs ds 4-21) E l e c t r o n c o n c e n t r a t i o n v s . T 107 4-22) M o b i l i t y v s . T 107 4-23) M o b i l i t y at 100 nm vs. T 109 4- 23) Wd vs. T 110 5- 1) Schematic diagram of (a) BFL i n v e r t e r and (b) UFL i n v e r t e r 113 5-2) Schematic diagram of the SDFL i n v e r t e r 115 5-3) Schematic diagram of the SDFL i n v e r t e r w i t h push p u l l b u f f e r 115 x i i i Fig.(5-4) Schematic diagram of the CCL i n v e r t e r 118 F i g . (5-5) Schematic diagram of the FFS i n v e r t e r 119 Fig.(5-6) Schematic diagram of (a) DCFL and (b) buffered DCFL. 121 Fig.(5-7) Schematic diagram of the LPFL i n v e r t e r ; Types (a) 1-D, (b) 1-1, (c) 2, (d) 3-D, (e) 3-1, and ( f ) 4 124 Fig.(5-8) Schematic diagram of the SCFL i n v e r t e r 135 Fig.(5-9) Schematic diagram of the CDFL (a) buffe r c i r c u i t , (b) AND gate, and (c) OR gate; (d) I-V c h a r a c t e r i s t i c s of the bu f f e r c i r c u i t 129 Fig.(5-10) (a) Transfer c h a r a c t e r i s t i c s of the bu f f e r and (b) output of 8 successive stages of b u f f e r c i r c u i t s ; (....)V =0 s s V and (xxxx) V =-0.5 V 131 ^ ' ss Fig.(5-11) (a) Schematic diagram of the CDFL i n v e r t e r and (b) t r a n s f e r c h a r a c t e r i s t i c s 133 Fig.(5-12) (a) Schematic diagram of the CDFL buffered i n v e r t e r , and (b) t r a n s f e r c h a r a c t e r i s t i c s 135 Fig.(5-13) Two p o s s i b l e design methods using the CDFL approach 136 Fig.(5-14) Micrograph p i c t u r e f o r (a) b u f f e r c i r c u i t and i n v e r t e r ; (b) AND and OR gates 138 F i g . (5-15) Experimental and simulated t r a n s f e r c h a r a c t e r i s t i c s of the CDFL b u f f e r c i r c u i t w i t h V g s=-0.5 V; (b) experimental t r a n s f e r c h a r a c t e r i s t i c s f o r the b u f f e r w i t h V =-1 V.... 139 s s Fig.(5-16) Experimental and simulated t r a n s f e r c h a r a c t e r i s t i c s of the CDFL i n v e r t e r 141 x i v Fig.(5-17) Simulated high frequency response f o r (a) b u f f e r c i r c u i t and (b) CDFL i n v e r t e r 142 Fig.(6-1) vs. fan out f o r group #1 151 Fig.(6-2) Gffi v s . fan out f o r group #1 152 Fig.(6-3) vs. f an out f o r group //2 154 Fig.(6-4) G m v s . fan out f o r group #2 156 F i g . (6-5) vs. fan out f o r group #3 15b Fig.(6-6) G v s . fan out f o r group #3 159 m Fig.(7-1) 161 Fig.(7-2) Schematic diagrams of DACs developed by (a) [84] and (b) [85] 162 Fig.(7-3) Schematic diagram of 3 - b i t DAC w i t h (a) MESFETS and (b) Saturated r e s i s t o r s as current sources 165 F i g . (7-4) Micrograph p i c t u r e of DACs of (a) f i g ( 7 - 3 . a ) and 166 (b) f i g ( 7 - 3 . b ) Fig.(7-5) Output voltage of the 3 branches of the DAC of f i g ( 7 - 3 . a ) 168 Fig.(7-6) Output v o l t a g e of the 3 branches of the dac of f i g ( 7 - 3 . b ) 179 Fig.(7-7) Simulated high frequency response of the DAC 170 F i g . (7-8) (a) I-V c h a r a c t e r i s t i c s of a t r a n s i s t o r without gate 173 a c t i n g as a saturated r e s i s t o r and (b) same device a f t e r p u t t i n g down the gate metal xv LIST OF ACRONYMS BFL Buffered FET Logic CCL Capacitor Coupled Logic CDFL Common Drain FET Logic CMOS Complementary Metal Oxide Semiconductor DAC D i g i t a l to Analog Converter DCFL D i r e c t l y Coupled FET Logic FET F i e l d E f f e c t T r a n s i s t o r FFS Feed Forward S t a t i c I . C s Integrated C i r c u i t s JFET J u n c t i o n F i e l d E f f e c t T r a n s i s t o r LEC Liquid-Encapsulated C z o c h r a l s k i LPFL Low P i n c h - o f f FET Logic LSI Large Scale of I n t e g r a t i o n MESFET Metal Semiconductor F i e l d E f f e c t T r a n s i s t o r MOS Metal Oxide Semiconductor MOSFET Metal Oxide Semiconductor F i e l d E f f e c t T r a n s i s t o r NMOS n-channel MOS PMOS p-channel MOS PFM P o l y t e t r a - F l u o r o p r o p y l Methacrylate SAGUPI S e l f A l i g n e d Gate using Polyimide SAINT S e l f - A l i g n e d Implantation f o r n + l a y e r Technique xv i SCFL Source Coupled FET Logic SDFL Schottky Diode FET Logic SEM Scanning E l e c t r o n Microscope SOS Silicon-On-Sapphire UFL Unbuffered FET Logic VLSI Very Large Scale I n t e g r a t i o n x v i i ACKNOWLEDGEMENTS I would l i k e to thank Dr. L. Young f o r h i s guidance, support and the u n l i m i t e d time he provided f o r me during the course of t h i s work. Mr. S. Dindo i s thanked f o r h i s a s s i s t a n c e and co-operation. Messrs. D. Hui , W. Tang, K. Tan, P. Townsley, B. D u r t l e r , and M. Lenoble are a l s o thanked f o r t h e i r u s e f u l d i s c u s s i o n s . S p e c i a l thanks are d i r e c t e d to Dr. P. Janega and Mr. A. Leugner f o r t h e i r help i n s o l v i n g equipment problems and i n the i o n i m p l a n t a t i o n . Messrs. A. Mackenzie, L. K j o l b y , C. S h e f f i e l d and C. Dumont are a l s o s p e c i a l l y thanked f o r maintaining the l a b o r a t o r y equipment. Ms. C Stevenson, who typed the manuscript, i s thanked f o r her e f f o r t . x v i i i To my wif e Manal x i x 1 CHAPTER (1) INTRODUCTION Since Van Tuyl and L i e c h t i [1J reported the f i r s t GaAs d i g i t a l l o g i c i n 1974 using Metal semiconductor F i e l d E f f e c t T r a n s i s t o r s (MESFETS), great progress has been achieved i n the GaAs Integrated c i r c u i t s (I.C.s) area. The d r i v i n g f o r c e behind t h i s progress was the urgent need f o r U l t r a High Speed (UHS) I.C.s which can p o t e n t i a l l y be achieved by using GaAs because of the higher e l e c t r o n m o b i l i t y and the s e m i - i n s u l a t i n g property of the GaAs m a t e r i a l . The i n t r i n s i c e l e c t r o n m o b i l i t y of GaAs i s 8500 cm2/Vs compared to 1500 cm2/Vs f o r s i l i c o n [ 2 ] . A t y p i c a l GaAs MESFET t r a n s i s t o r w i t h channel doping c o n c e n t r a t i o n of about 2x10* 7 cm - 3 and has e l e c t r o n m o b i l i t y of about 4500 cm2/Vs compared to a t y p i c a l 800 cm2/Vs f o r s i l i c o n Metal Oxide Semiconductor (M0S) devices [ 3 ] . In a d d i t i o n to the higher m o b i l i t y , GaAs has a higher peak e l e c t r o n v e l o c i t y , F i g . ( 1 - 1 ) , which leads to a reduced t r a n s i t time between e l e c t r o d e s , i n t r i n s i c high-frequency c a p a b i l i t y [ 4 ] , and increased high frequency gain f o r microwave FETs. The high e l e c t r o n m o b i l i t y as w e l l as the peak e l e c t r o n v e l o c i t y are achieved at low e l e c t r i c f i e l d . Therefore, high speed of op e r a t i o n w i t h low power d i s s i p a t i o n can be achieved at the same time. The s e m i - i n s u l a t i n g property of GaAs makes i t p o s s i b l e f o r d i r e c t i s o l a - t i o n between devices on the same chip without the need f o r i s o l a t i n g i s l a n d s (as i n the case of S i ) . I t leads a l s o to a reduced c h i p p a r a s i t i c c a p a c i - tance which leads i n t u r n to a f a s t e r speed of o p e r a t i o n . 2 { Fig.(1-1) Steady state velocity-field characteristics for electrons and GaAs [6]. 3 To appreciate the advantages of GaAs, l e t us look back at the h i s t o r y of SI technology. Most of the e a r l y MOS work used p-type MOS (PMOS) because of the higher y i e l d of enhancement mode t r a n s i s t o r s with p channels as compared to n channels. However, to gain the advantage of the 2.5 times higher m o b i l i t y of e l e c t r o n s i n s i l i c o n compared to holes, the n-type MOS (NMOS) technology was developed. On the other hand, Complementary MOS (CMOS) was developed to achieve low power c i r c u i t s and the CMOS/silicon-on-sapphire (SOS) to take advantage of the low p a r a s i t i c capacitance of the semi- i n s u l a t i n g , SOS m a t e r i a l . The emerging question now i s whether i t i s worthwhile to spend a great deal of money and time on GaAs research to e x p l o i t the s i x times higher e l e c t r o n m o b i l i t y and the s e m i - i n s u l a t i n g property at the same time. The answer, I b e l i e v e , should be yes. InP has e l e c t r i c p r o p e r t i e s s i m i l a r to those of GaAs, t h e r e f o r e , i t i s considered as an a l t e r n a t i v e m a t e r i a l to produce I.C.s operating i n the g i g a b i t range. Maloney and Frey [5] have shown that the maximum switching frequency f o r u n i t y gain InP F i e l d E f f e c t T r a n s i s t o r s (FETs) at room temperature should be about 48% higher than that of GaAs FETs having the same dimensions. However, InP MESFETs have poor l o g i c performance due to: (a) low Schottky b a r r i e r height (0.5eV) [6] which leads to a reduced gate- d r a i n reverse bias voltage (b) r e l a t i v e l y large d r a i n current flow when the device i s pinched o f f [ 7 ] . InP f a b r i c a t i o n technologies f o r MESFETs and Metal Oxide Semiconductor F i e l d E f f e c t T r a n s i s t o r s (MOSFETs) are s t i l l i n t h e i r e a r l y stages. However, InP MOSFETs have great p o t e n t i a l f o r being used i n the future due to t h e i r low surface states density which w i l l make them f u n c t i o n properly at low 4 frequencies, < 5KHz (which i s not the case f o r GaAs MOSFETs). However, high y i e l d f a b r i c a t i o n techniques must be developed f o r InP before i t s advantages can be r e a l i z e d . GalnAs has higher low f i e l d m o b i l i t y and peak v e l o c i t y than GaAs, but i t has a very low Schottky b a r r i e r height (0.3eV) [ 6 ] . Since other m a t e r i a l s , which may have s i m i l a r c h a r a c t e r i s t i c s to GaAs, do not have a developed f a b r i c a t i o n technique, t h e i r chance of being used commercially i n the near f u t u r e i s very s l i m . Therefore, GaAs i s considered the best candidate, i n the near f u t u r e , f o r UHS I.C.s In terms of m a t e r i a l p r o p e r t i e s and f a b r i c a t i o n technology. The major area of a p p l i c a t i o n f o r GaAs, besides analog microwave a p p l i c a t i o n s , i s UHS I.C.s. This area covers the a p p l i c a t i o n i n high speed tr a n s m i s s i o n data systems, high speed s i g n a l p rocessing, s a t e l l i t e communications, high speed computers, and t e s t and measurement systems. The above a p p l i c a t i o n s need very complex systems, th e r e f o r e they need not only U l t r a High Speed (UHS) of operation but a l s o Very Large Scale of I n t e g r a t i o n (VLSI). Eden et a l . [3] have defined the p r i n c i p a l requirements f o r UHS-VLSI systems as: (a) very high d e n s i t y of i n t e g r a t i o n (low chip area per gate) (b) low power d i s s i p a t i o n (c) high speed of operation (very low gate time delay) (d) extremely low power - time delay product (e) very high process y i e l d ( s u f f i c i e n t to achieve acceptable chip y i e l d s ) These requirements are not l i s t e d here according to p r i o r i t y ; no p r i o r i t y i s 5 p o s s i b l e since a l l must be met at the same time to r e a l i z e high performance UHS-VLSI systems. S i based technology can meet requirements (a) and (e) due to the impressive advances i n l i t h o g r a p h y and f a b r i c a t i o n technology. However, i t i s hard f o r i t to meet the other requirements at the same time since higher e l e c t r o n v e l o c i t y i n S i requires higher f i e l d and consequently higher power d i s s i p a t i o n , see F i g . ( 1 - 1 ) . On the c o n t r a r y , GaAs req u i r e s lower f i e l d f o r high e l e c t r o n v e l o c i t y , t h e r e f o r e , requirements ( b ) , ( c ) , and (d) can be met at the same time. The other two requirements can be met i f appropriate l o g i c approaches and f a b r i c a t i o n techniques can be developed. However, the most important f a c t i s that the problems f a c i n g GaAs are design and t e c h n o l o g i c a l problems which can be solved i f enough money and e f f o r t are assigned to GaAs research. With S i , on the c o n t r a r y , the problems are due to basic p h y s i c a l l i m i t a t i o n s . The o b j e c t i v e of the work described i n t h i s t h e s i s was to study GaAs I.C.'s using i o n i m p l a n t a t i o n . The main achievements were: (a) The development of a f a b r i c a t i o n process. (b) The c h a r a c t e r i z a t i o n of MESFET t r a n s i s t o r s f a b r i c a t e d i n our l a b o r a t o r y using t h i s process. (c) The development of a new d i g i t a l l o g i c f a m i l y . (d) The development of a 3-bit d i g i t a l to analog converter. I n Chapter(2), the a n a l y s i s of GaAs MESFETs, Schottky diodes, saturated r e s i s t o r s , and r e s i s t o r s i s discussed. The saturated r e s i s t o r Is used i n t h i s work as a current source f o r the D i g i t a l to Analog Converter (DAC). An overview of GaAs f a b r i c a t i o n techniques i s given i n t h i s chapter. In 6 Chapter(3), the i o n implanted planar process, recessed gate process, and S e l f A ligned Gate Using Polyimide (SAGUPI) process are discussed. The DC and temperature measurements of GaAs MESFET are presented i n Chapter(4). An overview of the d i f f e r e n t GaAs l o g i c approaches i s presented i n the f i r s t s e c t i o n of Chapter(5). In the second s e c t i o n , the a n a l y s i s , f a b r i c a t i o n , and measurements of the Common Drain FET Logic (CDFL) approach are presented. A comparative study w i t h i n the GaAs MESFET l o g i c groups i s presented i n Chapter(5). The JFET Model of the SPICE.2G program [14] was used to simulate the performance of these approaches. In Chapter(7), the a n a l y s i s , f a b r i c a t i o n and measurement of two 3-bit DAC are discussed. In the second s e c t i o n of Chapter(7) the saturated r e s i s t o r i s evaluated as a current source. Conclusions and suggestions f o r fu t u r e work are discussed i n Chapter(8). 7 CHAPTER(2) REVIEW OF GaAs DEVICES AND TECHNOLOGIES D i f f e r e n t types and s t r u c t u r e s of t r a n s i s t o r s have been developed to r e a l i z e GaAs high speed I.C.s. Next to the Metal Semiconductor F i e l d E f f e c t T r a n s i s t o r (MESFET), the J u n c t i o n F i e l d E f f e c t T r a n s i s t o r (JFET) i s the most developed t r a n s i s t o r . JFETs have a higher gate b a r r i e r height than MESFETs. This makes them a t t r a c t i v e f o r use i n D i r e c t l y Coupled FET Logic (DCFL). Despite the need f o r an extra implant to give the p type r e g i o n , JFETs have higher gate capacitance than MESFETs because the j u n c t i o n area between the p + r e g i o n and a channel i s normally l a r g e r than the j u n c t i o n area between the gate metal and the channel i n MESFETs. The Metal Oxide Semiconductor F i e l d E f f e c t T r a n s i s t o r (MOSFET) and Metal I n s u l a t o r F i e l d E f f e c t T r a n s i s t o r (MISFET) were developed p r i m a r i l y f o r the use i n the DCFL (see Chapter(5)) where ( u n l i k e MESFETs) no excessive current would flow i f a p o s i t i v e voltage >0.8 V was a p p l i e d to the gate and consequently high voltage swing could be used. The main problem f a c i n g the above two types, besides the f a b r i c a t i o n d i f f i c u l t i e s , i s the oxide i n s t a b i l i t y and the high surface s t a t e density which made them impossible to work pr o p e r l y at D.C. Other GaAs t r a n s i s t o r s such as b i p o l a r , h e t e r o j u n c t i o n , and permeable base t r a n s i s t o r s have good p o t e n t i a l f o r f u t u r e a p p l i c a t i o n s ; however, high y i e l d and r e p r o d u c i b l e f a b r i c a t i o n techniques s u i t a b l e f o r a high l e v e l of i n t e g r a t i o n have not been developed as y e t . 8 2-1 GaAs MESFETS The two types of MESFETs used i n GaAs I.C.s are the d e p l e t i o n type, which has negative threshold v o l t a g e , and the enhancement type, with a p o s i t i v e threshold v o l t a g e . Fig.(2-1) shows the s t r u c t u r e of both d e p l e t i o n and enhancement MESFET t r a n s i s t o r s . The channel of the d e p l e t i o n one i s not f u l l y depleted at gate to source voltage V =0, t h e r e f o r e , a negative gate gs to source voltage i s required to deplete the channel and turn the t r a n s i s t o r OFF. While the channel of the enhancement t r a n s i s t o r i s f u l l y depleted at V = 0 , a p o s i t i v e gate to source voltage i s required to turn the t r a n s i s t o r gs ON. A f u l l y depleted channel at = 0 V req u i r e s the channel to be t h i n and l i g h t l y doped and t h i s leads i n turn to a higher channel r e s i s t a n c e . The maximum V voltage allowed ( f o r both d e p l e t i o n and enhancement gs modes) i s about 0.7 v o l t , otherwise an excessive current w i l l flow from the gate to the source. Therefore, the voltage swing of the enhancement mode t r a n s i s t o r s i s l i m i t e d to 0.7 v o l t s i n c e the lower value of the threshold voltage V ^ i s 0 V. A t i g h t c o n t r o l of the threshold voltage Is r e q u i r e d , i n t h i s case, to prevent the degradation of the swing v o l t a g e . 9 Fig.(2-1) MESFET structure (a) depletion mode and (b) enhancement mode; the shaded areas under the gates are the depletion region areas. (S = source, G = gate, and D - drain) 10 In general, d e p l e t i o n mode t r a n s i s t o r s operate at higher speed due to t h e i r l a r g e r voltage swing and lower channel r e s i s t a n c e . They are als o e a s i e r to f a b r i c a t e because l e s s t i g h t c o n t r o l on the threshold voltage i s re q u i r e d . Enhancement mode t r a n s i s t o r s have high s e r i e s r e s i s t a n c e , and low voltage swing. In s p i t e of t h i s , the enhancement mode t r a n s i s t o r has a great p o t e n t i a l since i t allows DCFL to be s i m p l i f i e d [38]. Many models f o r GaAs MESFETs have been developed over the l a s t f i f t e e n years. Some of them are a n a l y t i c a l models [8-11] and others are numerical models [12-13]. However, the MOS-like a n a l y t i c a l model [3] w i l l be considered i n t h i s d i s c u s s i o n because i t i s simple, s u i t a b l e f o r understanding the t r a n s i s t o r p h y s i c s , and used f o r c i r c u i t s i m u l a t i o n i n the SPICE2 program [14]. The steady s t a t e I-V c h a r a c t e r i s t i c s f o r a uniformly doped channel have been derived by Shockley [15]. According to t h i s theory the d r a i n current (assuming v = uE) i s I . - (WEW /aL )[(V - V . )V, - V 2. /2] ds g g gs t h ds ds (2-1) and the current saturates f o r V, > V = V - V , (2-2) ds sat gs th when the channel pinches o f f . The s a t u r a t i o n current then w i l l be I , , , , = B(V ~ V ) 2 (2-3) dsat gs th where 8 = yew /2aL (2-4) g g For an ion implanted channel, equation (2-3) i s s t i l l accurate w i t h 8 replaced by [47] 6 = W us/2a L (2-5) 1 g e f f g where a = R + 2/ap (2-6) ef f p For short channel t r a n s i s t o r s (L < 2um), the current saturates before the channel i s pinched o f f due to the e l e c t r o n v e l o c i t y s a t u r a t i o n . For enhancement mode t r a n s i s t o r s , expression (2-3) can be modified [16] f o r d r i f t f i e l d - v e l o c i t y s a t u r a t i o n by r e p l a c i n g uV /L = u(V - v ,)/L by v which r e s u l t s i n sat g gs th g s ^ s a t " ( W 2 a ) ( V g s - V t h > <2"7> For short channel d e p l e t i o n mode t r a n s i s t o r s , expression (2-3) i s s t i l l accurate [17] w i t h the replacement of B by 6„ = (2epv W /a(uV + 3v L )) (2-8) 2 s g p s g The FET transconductance expression i s g = dl,, /dV at constant V\ (2-9) m ds gs ds tak i n g V, > V , the transconductance w i l l be OS S3.C *m " d< e< Vgs " V t h > 2 ) / d V g s " 2 f 5< Vgs - Vth> < 2- 1 0> The channel conductance of a FET i s gJ = d l . /dV, at constant V (2-11) & d ds ds gs from equation (2-1), equation (2-11) w i l l be «d = 2 3 [ ( V g S " Vth> " V d s ] ( 2 " 1 2 ) 12 When V, tends to 0, equation (2-12) becomes ds *d = 2 3 ( V g s " Vth> <2"13> which i s s i m i l a r to equation (2-10) 2-2 GaAs Saturated R e s i s t o r s The saturated r e s i s t o r i s a two t e r m i n a l device which can be used as a load element f o r d i g i t a l l o g i c [18]. The s t r u c t u r e of t h i s device i s an n l a y e r , s i m i l a r to that of a MESFET, terminated by two n+ regions f o r ohmic contacts, F i g . ( 2 - 2 . a ) . The I-V c h a r a c t e r i s t i c of the saturated r e s i s t o r , shown i n F i g . ( 2 - 2 . b ) , i s s i m i l a r to that of a MESFET with f i x e d V value gs except that the current saturates due to the e l e c t r o n d r i f t v e l o c i t y s a t u r a t i o n rather than due to the pinch o f f of the channel. Assuming a uniformly doped channel, the s a t u r a t i o n current w i l l be I J = qW nv a (2-14) ds g s w h i l e the current i n the l i n e a r region can be obtained from I . = qW nauV, /L (2-15) ds g ds ch The high s a t u r a t i o n f i e l d of S i (20 kV/cm compared to 3 kV/cm i n GaAs) makes i t hard to f a b r i c a t e S i saturated r e s i s t o r s w i t h p r a c t i c a l dimensions, s i n c e a very small channel length i s required to get s a t u r a t i o n at a reasonably low v o l t a g e . Lee et a l . [18] have reported that the use of saturated r e s i s t o r has the f o l l o w i n g advantages over the use of MESFET load: (a) lower capacitance, (b) higher i n t e g r a t i o n d e n s i t y , Fig.(2-2) Saturated resistor (a) structure and (b) I-V characteristics 14 (c) b e t t e r parameter u n i f o r m i t y across the wafer, and (d) fewer f a b r i c a t i o n steps than a MESFET. For these reasons, one of our o b j e c t i v e s i s to evaluate t h i s device as a load and a current source. 2-3 GaAs Schottky Diode The Schottky diode has an ohmic contact to a h i g h l y doped l a y e r and a r e c t i f y i n g Schottky contact with a l i g h t l y doped l a y e r , F i g . ( 2 - 3 . a ) . The I-V c h a r a c t e r i s t i c of a Schottky diode i s shown i n Fig.(2-3.b). The s a t u r a t i o n current d e n s i t y i s governed by the equation J g = A T 2 exp(-q<j>bn/kT) (2-15) and the forward biased current d e n s i t y i s governed by J f = J s[exp(qV f/nkT) - 1] (2-16) or J - J [exp(qV./nkT)] (2-17) r s r f o r qV f » 3nkT. The s a t u r a t i o n current density J g can be obtained experimentally by e x t r a p o l a t i n g the current density from the l o g - l i n e a r region to i n t e r s e c t w i t h the l i n e V = 0. The i d e a l i t y f a c t o r n can be obtained from the r e l a t i o n n = ( q / k T ) ( d V / d ( l n ( J f ) ) ) (2-18) and the b a r r i e r height from ** -= (kT/q)ln(A T 2 / J ) (2-19) t>n s The b a r r i e r height values depend on the doping c o n c e n t r a t i o n , the semiconductor m a t e r i a l , and the contact metal [ 2 ] . For a given metal and 15 SCHOTTKYv* CONTACT [ n •OHMIC CONTACT (a) Fig.(2-3) Schottky diode (a) structure and (b) I-V characteristics 16 semiconductor, the b a r r i e r height, the reverse bias breakdown v o l t a g e , and the forward switching ON voltage decrease with the increase of the doping c o n c e n t r a t i o n , F i g . ( 2 - 3 . b ) . Optimum Schottky diodes have i d e a l i t y f a c t o r n close to u n i t j r , s a t u r a t i o n current d e n s i t y J g value as small as p o s s i b l e , b a r r i e r height as high as p o s s i b l e , and reverse bias breakdown voltage as high as p o s s i b l e . Clean surface between the metal and the semiconductor can lead to b e t t e r Schottky diodes assuming that s u i t a b l e doping concentration i s used. 2-1 R e s i s t o r s R e s i s t o r s i n mo n o l i t h i c I.C.s can be obtained by u t i l i z i n g the bulk r e s i s t i v i t y of a d i f f u s e d or implanted area, an e p i t a x i a l l a y e r , or a depos- i t e d t h i n f i l m ( u s u a l l y nichrome N i C r ) . In t h i s work r e s i s t o r s were made by i m p l a n t a t i o n . Since the GaAs substrate i s a s e m i - i n s u l a t i n g m a t e r i a l and can be converted to a conducting one by i m p l a n t a t i o n , a very wide range of sheet r e s i s t a n c e s (from l e s s than a hundred to s e v e r a l hundred thousand ohms per square) can be obtained by varying the i m p l a n t a t i o n dose and energy. The a b i l i t y to have t h i s wide range of sheet r e s i s t a n c e makes i t p o s s i b l e to f a b r i c a t e r e s i s t o r s with r e s i s t a n c e s ranging from a few ohms to s e v e r a l hundreds of kilo-ohms with p r a c t i c a l dimensions. The s t r u c t u r e of a r e s i s t o r , shown i n F i g . ( 2 - 4 ) , c o n s i s t s of a doped l a y e r terminated with two ohmic conta c t s . The r e s i s t a n c e of t h i s r e s i s t o r can be obtained from the r e l a t i o n R = R g H • (L/W) (2-20) where L i s the r e s i s t o r l e n g t h , W i s I t s width, and R i s the sheet an r e s i s t a n c e which i s obtained from the r e l a t i o n 17 n n + o s/V\A o Fig.(2-4) Ion-implanted r e s i s t o r . 18 R S H  = p / a ( 2 ~ 2 1 ) and P i s the s p e c i f i c r e s i s t a n c e and a i s the thickness of the r e s i s t o r implanted l a y e r . The r e s i s t a n c e of the ohmic contacts should be estimated added to the value r e s u l t i n g from equation (2-20). The width of the r e s i s t o r should be long enough that the r e s i s t o r - t o l e r a n c e percentage due to l i n e width v a r i a t i o n , mask misalignment or photographic r e s o l u t i o n becomes s i g n i f i c a n t . The r e s i s t o r length should not be too s m a l l , not only because of the r e s i s t o r t olerance percentage but al s o to avoid current s a t u r a t i o n as occurs i n saturated r e s i s t o r s . The minimum length at which no s a t u r a t i o n occurs can be obtained using the e m p i r i c a l r e l a t i o n L , = V /0.5 Mm (2-22) min max where V i s the maximum voltage drop across the r e s i s t o r In v o l t s . The 0.5 max f a c t o r i n equation (2-22) comes from the experimental observation that the current saturates at 0.5V/pm of the channel l e n g t h . 2-5 Major Ion Implanted F a b r i c a t i o n Steps f o r GaAs MESFETs The e a r l y GaAs MESFETs were d e p l e t i o n mode types; they were f a b r i c a t e d by the mesa f a b r i c a t i o n technology to be used as low noise microwave FETs [3 ] . In t h i s approach, i s o l a t i o n between devices was accomplished by etching a mesa through the e p i t a x i a l or the implanted l a y e r . Two l a y e r s of metal were used to interconnect the various c i r c u i t elements with a d i e l e c t r i c l a y e r to i s o l a t e the f i r s t and second l a y e r of metal. Connections between these two l a y e r s were accomplished through holes i n the d i e l e c t r i c . 19 At f i r s t , e p i t a x i a l techniques were used to form the a c t i v e l a y e r . Problems were found i n achieving the u n i f o r m i t y and r e p r o d u c i b i l i t y required f o r I.C.s. Although the use of ion i m p l a n t a t i o n ( i n the mesa technique) has solved the u n i f o r m i t y and r e p r o d u c i b i l i t y problems, i t has been unable to optimize more than one device on the same chip [19]. Using both i o n im p l a n t a t i o n and e p i t a x i a l techniques made i t p o s s i b l e to optimize more than one device, however, i t was hard to achieve an acceptable channel u n i f o r m i t y and y i e l d e s p e c i a l l y f o r LSI a p p l i c a t i o n s [ 3 ] . The i on i m p l a n t a t i o n of the dopant d i r e c t l y i n t o a s e m i - i n s u l a t i n g GaAs m a t e r i a l or a b u f f e r l a y e r has shown very good r e s u l t s i n terms of channel u n i f o r m i t y , r e p r o d u c i b i l i t y , and y i e l d . The i s o l a t i o n between adjacent devices i s d i r e c t l y achieved by the s e m i - i n s u l a t i n g (undoped) areas between them. B e t t e r i s o l a t i o n can be achieved by implanting these areas (undoped areas) with boron [20]. Several f a b r i c a t i o n techniques (other than the mesa) which u t i l i z e i o n - i m p l a n t a t i o n have been developed. Although each of them i s devoted to c o n t r o l or o p t i m i z a t i o n of one (or more) of the device parameters, such as threshold voltage or s e r i e s r e s i s t a n c e , they use i n general nearly the same f a b r i c a t i o n steps. These techniques w i l l be discussed i n the next s e c t i o n . Only the ion-implanted GaAs MESFET f a b r i c a t i o n technique w i l l be considered, s i n c e I t i s the most developed and the one we used i n our processes. The major steps of t h i s process can be summarized as: (a) substrate p r e c l e a n i n g , (b) i m p l a n t a t i o n of the channel and ohmic contact areas, 20 (c) p o s t - i m p l a n t a t i o n annealing, (d) ohmic contact metal d e p o s i t i o n and a l l o y i n g , (e) gate metal (metals) d e p o s i t i o n , and ( f ) f i r s t and second l e v e l m e t a l l i z a t i o n . (a) Substrate precleaning The precleaning s t a r t s with degreasing the wafer using hot solvents such as acetone, 2-propanol, methanol, and t r i c h l o r e t h y l e n e . These solvents are intended to d i s s o l v e away any grease or wax remaining a f t e r c u t t i n g , s h i p p i n g , and handling. Then the wafer i s etched to remove s e v e r a l hundreds to s e v e r a l thousands of angstroms to y i e l d a damage free surface. A s o l u t i o n w i t h a small concentration of bromine i n methanol can be used f o r t h i s purpose. The bromine serves the dual r o l e of being a strong o x i d i z i n g agent, and a l s o d i s s o l v i n g the o x i d a t i o n product to form s o l u b l e bromides. A mixture of H 202 and an a c i d or base can be used a l s o f o r etching the GaAs sur f a c e . In t h i s case, the oxide r e s u l t i n g from the r e a c t i o n with H 2 0 2 w i l l be d i s s o l v e d by the a c i d or the base used. S u l p h u r i c , n i t r i c , h y d r o c h l o r i c , and c i t r i c acids as w e l l as ammonia and sodium hydroxide are used f o r t h i s purpose [21]. Since the above etchants, as mentioned before, have an o x i d i z i n g nature, the wafer must be b o i l e d i n a concentrated a c i d such as HC1 f o r about 2 minutes to remove any residues of oxide. (b) Ion-Implantation C o n v e n t i o n a l l y , the i n t r o d u c t i o n of desired impurity atoms i n t o the l a t t i c e s i t e i n a semiconductor c r y s t a l (to form an n- or -p type m a t e r i a l ) i s achieved e i t h e r during the growth process ( e p i t a x i a l l a y e r ) or by thermal d i f f u s i o n . The thermal d i f f u s i o n technology f o r n-type dopants has not been 21 developed f o r compound semiconductors such as GaAs or InP. E p i t a x i a l techniques were the f i r s t to be used with GaAs, but they have had problems i n ac h i e v i n g the u n i f o r m i t y and r e p r o d u c i b i l i t y r e q uired f o r I.C.s [ 3 ] , The other a l t e r n a t i v e process i s to implant the dopant ions Into the GaAs su b s t r a t e . Morgan et a l . [22] have l i s t e d the advantages of i m p l a n t a t i o n as: (a) the doping l e v e l and the thickness of the implanted l a y e r can be e a s i l y c o n t r o l l e d , (b) the doping i s uniform and r e p r o d u c i b l e , (c) i t i s more d i r e c t i o n a l than the d i f f u s i o n , and (d) i t has the a b i l i t y to achieve doping p r o f i l e s which cannot be e a s i l y obtained by other techniques. M a t e r i a l s such as S, Se, and S i have been used s u c c e s s f u l l y as n-type dopants i n GaAs, while m a t e r i a l s such as boron and z i n c are used as p-type dopants. Our d i s c u s s i o n here w i l l be r e s t r i c t e d to the n-type dopants because no p-material w i l l be used i n our process. Fig.(2-5) shows the c a l c u l a t e d and the measured e l e c t r o n concentration p r o f i l e s f o r S, Se, and S i . From the f i g u r e one can see that a c t i v a t i o n of the implanted S atoms i s only 20%, and the depth of the implanted l a y e r i s much greater than expected from the S range s t a t i s t i c s . This broader thickness i s due to the d i f f u s i o n of the S during the post-implantation annealing. Fig.(2-5) Measured (from C-V measurements) and calculated electron concentration profiles for S, Si and Se implants [26]. 23 S i and Se measured e l e c t r o n concentration p r o f i l e s are q u i t e s i m i l a r to the c a l c u l a t e d ones [26]. This i n d i c a t e s that S i and Se have higher a c t i v a t i o n e f f i c i e n c i e s and lower d i f f u s i o n constants. S and Se need to be implanted at elevated temperatures to improve the a c t i v a t i o n e f f i c i e n c y while S i can achieve high a c t i v a t i o n while implanted at room temperature [23]. S i i s considered the best candidate f o r GaAs im p l a n t a t i o n since i t has low d i f f u s i o n constant, high a c t i v a t i o n , and no elevated temperature i s required during the i m p l a n t a t i o n . F o l l o w i n g the i m p l a n t a t i o n , the wafer must be annealed at 800 to 900°C to remove the c r y s t a l l i n e defects induced by the implanted i o n s . However, at such high temperatures (>600°C), GaAs i s subject to d i s s o c i a t i o n . Therefore, the wafer surface must be protected by an encapsulant, or annealed i n a s p e c i a l ambient (normally As overpressure) to prevent d i s s o c i a t i o n and i n h i b i t o u t d i f f u s i o n of the implanted i m p u r i t i e s . (c) Annealing Many m a t e r i a l s have been used as a cap f o r GaAs annealing. The most used m a t e r i a l s are S i 0 2 , S i 3 N l + , and A1N. S i 0 2 was the e a r l i e s t capping m a t e r i a l employed. The most serious problem with S i 0 2 i s the o u t d i f f u s i o n of the Ga through i t [24]. S i 3 N ^ can a l l e v i a t e t h i s problem, as w e l l as As o u t d i f f u s i o n and 0 2 i n d i f f u s i o n , provided i t has low 0 2 content. Yokayama et a l . [25] have observed lower trapping d e n s i t i e s f o r samples capped w i t h SigN^. The e l e c t r o n ' c o n c e n t r a t i o n density p r o f i l e s f o r samples capped w i t h S i 0 2 , S i 3 N H , and A1N are shown i n Fig.(2-6) [26]. The f i g u r e shows that the samples capped w i t h A1N have severe c a r r i e r d i f f u s i o n . These f a c t o r s have r e s u l t e d i n general aceptance of S i ^ . as a s u i t a b l e encapsulant m a t e r i a l . 24 Fig.(2-6) Electron concentration profiles for SI GaAs samples implanted and annealed at 850°C for 30 minutes [24]. 25 The thickness of the S i 3 N l + cap layer should not exceed 1000A, otherwise the f i l m w i l l crack during annealing. In a d d i t i o n to the encapsulation techniques, a number of capless annealing techniques have been developed. One of these techniques i s the proximity cap annealing developed by Mandal et a l . [27]. Mandal used a poli s h e d GaAs wafer i n mechanical contact with the implanted wafer i n the presence of a c o n t r o l l e d As vapor pressure. Both the p o l i s h e d GaAs wafer and the As vapor prevent any o u t d i f f u s i o n of As atoms from the implanted wafer. The second technique i s the capless annealing technique i n which an As over- pressure i s used to prevent any As o u t d i f f u s i o n . The source of the As overpressure can be InAs [28] or crushed h i g h - p u r i t y GaAs [29]. Due to the f a c t that both proximity cap annealing and capless annealing techniques use t o x i c gases and complicated systems, they are not a t t r a c t i v e techniques without i n d u s t r i a l i n f r a s t r u c t u r e support. The r a p i d thermal annealing technique can be a capless annealing technique. In our AG Associates system, no t o x i c gases are used. In t h i s technique, the sample temperature i s r a i s e d to around 950°C i n about 3 seconds and kept at t h i s temperature f o r about 5 seconds more and then cooled down before appreciable decomposition of the m a t e r i a l takes place. The GaAs wafer i s placed between two S i wafers i n an N 2 atmosphere during annealing. Argon arc [30] or halogen lamps [31] can be used as a source of heat. Some recent studies have employed l a s e r or e l e c t r o n beam i r r a d i a t i o n to anneal the l a t t i c e damage and a c t i v a t e implanted dopants i n GaAs [32]. Although high e l e c t r o n concentrations have been achieved f o r high dose 26 implants, m o b i l i t i e s have remained poor, and f o r low implant doses, low l e v e l s of a c t i v a t i o n have been observed so f a r . (d) Ohmic Contact M e t a l l i z a t i o n A f t e r a c t i v a t i n g the implanted areas, ohmic contact metals (AuGe or AuGe/Ni [25]) are deposited and a l l o y e d at a temperature of about 450°C. A l l o y i n g causes some Ge atoms to d i f f u s e i n t o the GaAs m a t e r i a l and form a very h i g h l y doped l a y e r . The contact between t h i s h i g h l y doped l a y e r and the AuGe a l l o y i s n o n - r e c t i f y i n g due to the low b a r r i e r height between them [2]. The a l l o y i n g time and the temperature vary from one l a b o r a t o r y to another. The surface of the a l l o y e d AuGe i s rough, however Ni can be deposited on the top before a l l o y i n g to improve the surface morphology. Measurements of the ohmic contact using the Transmission Line Model (TLM) theory [52] are discussed i n chapter ( 4 ) . (e) Schottky Contacts The Schottky contact required f o r the gate i s formed by d e p o s i t i n g the gate metal on the GaAs surface. Although most metals form a Schottky contact with GaAs, not a l l of them form an acceptable one. The requirements f o r an acceptable contact are (a) s u f f i c i e n t l y l a r ge b a r r i e r h eight, (b) ageing and temperature degradation r e s i s t a n c e , and (c) good adhesion between the metal and the semiconductor. A l was the f i r s t metal to be used f o r t h i s purpose. I t i s very simple to deposit and has low s p e c i f i c r e s i s t i v i t y . Ti/Pt/Au are the p r e f e r r e d Schottky metals e s p e c i a l l y f o r commercial production. In t h i s system, TI provides good Schottky contact while Au provides high e l e c t r i c a l 27 c o n d u c t i v i t y . Pt provides a good d i f f u s i o n b a r r i e r between the T i and the Au. ( f ) F i r s t and Second L e v e l of M e t a l l i z a t i o n To connect devices with each other, two l e v e l s of m e t a l l i z a t i o n are r e q u i r e d to enable crossovers. Implanted l a y e r s are p r e f e r a b l y not used as interconnects due to t h e i r high r e s i s t i v i t y . Very high doses (of about 1 0 1 5 cm 2) and energies (about lOOOkeV) give sheet r e s i s t a n c e s of about 80 ohms per square [89] compared to 0.025 ohm per square f o r a 1 ym sheet of A l . The two l e v e l s of m e t a l l i z a t i o n must be e l e c t r i c a l l y i s o l a t e d except when a contact between them i s r e q u i r e d . The i s o l a t i o n m a t e r i a l i s normally a d i e l e c t r i c such as S i 0 2 , S i 3 N j t , or polyimide. S i 0 2 and S i are the most used m a t e r i a l s f o r t h i s purpose, however A d i t y a et a l . [33] do not recommend using S i 3 N i t because i t may cause the degradation of the ohmic contacts and the channel. They a t t r i b u t e d t h i s to the c o l l i s i o n of the plasma molecules w i t h the surface of the wafer. They recommend the use of the polyimide f o r high q u a l i t y t r a n s i s t o r s . In g e n e r a l , polyimide has these advantages over both S i 0 2 and S i g N ^ (a) i t i s l a i d down by s p i n n i n g , (b) holes i n the polyimide can be opened using the developer of a p o s i t i v e p h o t o r e s i s t such as MF312 Shipley developer, t h e r e f o r e the development of the p h o t o r e s i s t and the etching of these holes can be done i n one step, (c) i t has lower d i e l e c t r i c constant l e a d i n g to lower s t r a y capacitance, and (d) i t i s r e s i s t a n t to nearly a l l chemical etchants. 28 Metals w i t h low r e s i s t i v i t y should be used f o r both l e v e l s of m e t a l l i z a t i o n . E l e c t r i c a l contacts between the two l e v e l s are achieved through holes etched i n the i s o l a t i n g d i e l e c t r i c . 2-6 GaAs I.C.s Technologies Four techniques w i l l be considered i n t h i s s e c t i o n : the planar ion-implanted, the recessed gate, the Pt gate, and the s e l f - a l i g n e d gate techniques. (a) The Planar Ion-implanted Technique The f i r s t approach i s the planar ion-implanted process developed by Rockwell i n 1979 [34]. Using t h i s approach, more than one device can be optimized at the same time by choosing the r i g h t doses and energy f o r the n and n+ i m p l a n t a t i o n as shown i n F i g . ( 2 - 7 ) . The value of the device parameters depend not only on the i m p l a n t a t i o n parameter, but al s o on the m a t e r i a l q u a l i t y . In order to achieve the re q u i r e d parameter u n i f o r m i t y and r e p r o d u c i b i l i t y using t h i s technique, " q u a l i f i e d " wafers must be used which s a t i s f y the f o l l o w i n g c o n d i t i o n s [ 6 ] : (a) high p u r i t y substrate w i t h l e s s than 5 x 1 0 1 5 cm - 3 donor and acceptor i m p u r i t i e s , (b) freedom from harmful c r y s t a l l i n e d e f e c t s , (c) high r e s i s t i v i t y (> 10' ohm-cm), (d) thermal s t a b i l i t y at the annealing temperature, and (e) high percentage a c t i v a t i o n of implanted i o n s . The f a b r i c a t i o n process s t a r t s with the wafer c l e a n i n g using hot solven t s and etchants f o r damaged l a y e r removal. Ion i m p l a n t a t i o n i s c a r r i e d 29 Planar GaAs IC fabrication steps Insulator deposition and masking for N- implant I Insulator / Photo resist i i i iu iEE^i i i (a) (b) (c) qlll l l , s N* Implant —^ S.I. GaAs - w - —4- Encapsulation and anneal . Multi-layer dielectric S.I. GaAs- Ohmic contact metallisation AuGe/Pt contact ^ Insulator <e) Schottky barrier and interconnect metallisation • r - . r , . , . . Schottky barrier JtfPVAugate \ , interconnect 3=1 I. GaAs- Second layer metallisation . Second level / mlerconnecl Insulator Cutaway view of a planar GaAs circuit fabrication with two localised implants. Planar GaAs I.C. _ H i First-second Second-level Second-level interconnect via ^interconnect insulator Substrate insulator \ Ohmic contact First level interconnect metal Fig.(2-7) Ion-implanted planar process [34]. 30 out through a S i 3 N i t l a y e r which w i l l be used as a cap f o r annealing a f t e r the im p l a n t a t i o n . Ohmic contact metals are deposited through openings i n the SigN^ l a y e r and then a l l o y e d at about 450°C f o r 2 minutes. Schottky contact metals are deposited to form the gate where Ti/Pt/Au metals are used for t h i s purpose. The same metals are used f o r the f i r s t and second l e v e l of m e t a l l i z a t i o n . S i 3 N l t i s used as an intermediate d i e l e c t r i c between the two l e v e l s of m e t a l l i z a t i o n . However, f o r high q u a l i t y devices, polyimide i s used as a d i e l e c t r i c . (b) Recessed Gate Technique At Plessey, another technique has been adopted i n order to c o n t r o l the pi n c h - o f f voltage ( F i g . ( 2 - 8 ) ) [ 6 ] . Monitor FETs were used to check the s a t u r a t i o n current before l a y i n g down the gate metals. I f the s a t u r a t i o n current value i s not acceptable, the channel i s etched to obt a i n the required current value which r e s u l t s , i n t u r n , i n the required p i n c h - o f f v o l t a g e . This technique ensures that the pinc h - o f f voltage l i e s w i t h i n a c e r t a i n range, but a t i g h t c o n t r o l may not be easy to achieve. The f a b r i c a t i o n steps can be summarized as: precleaning the sub s t r a t e , n i m p l a n t a t i o n , n + i m p l a n t a t i o n , ohmic contact metal d e p o s i t i o n and a l l o y i n g , gate mask p a t t e r n i n g and source d r a i n current measuring, channel etching f o r g e t t i n g the required s a t u r a t i o n c u r r e n t , gate metals d e p o s i t i o n , f i r s t l e v e l of m e t a l l i z a t i o n , intermediate d i e l e c t r i c d e p o s i t i o n , and second l e v e l of m e t a l l i z a t i o n . (c) Pt Gate Technique The t h i r d a l t e r n a t i v e to c o n t r o l the pinc h - o f f voltage i s the use of Pt n* implant I I I I I I I 1 1 00 n implant i I I I ! I J L (b) lap and anneal (c) (d) J L. FET and diode formation J L IW.IU ini. H^I .M w J Z L First level metallization J V. t3 -potyimide SbN. J Z L if) -Vias in potyimide ,—2nd level metallization <0> Fig.(2-8) Plessey fabrication process [6]. 32 gates. Pt reacts with GaAs at temperatures of 300-500°C and forms s e v e r a l compounds i n c l u d i n g PtGa, Pt^Ga, and Pt 2As [35-36]. Ga atoms d i f f u s e through the i n t e r m e t a l l i c l a y e r and the compound Pt As 2 forms adjacent to the GaAs. As the r e a c t i o n progresses, the Schottky contact c h a r a c t e r i s t i c changes from Pt-GaAs to PtAs^GaAs and the GaAs surface moves down leading to a reduction i n the channel thickness and consequently a r e d u c t i o n i n the pinch-off v o l t a g e . The r a t e by which the pinch-off voltage decreases depends on the s i n t e r i n g temperature and time. The f a b r i c a t i o n procedure for t h i s technique i s s i m i l a r to that of the ion-implanted planar technique except the gate metal should be Pt and should be s i n t e r e d f o r a s p e c i f i c period of time f o r threshold voltage c o n t r o l . Using t h i s method, Toyada et a l . [37] were able to c o n t r o l p r e c i s e l y the p i n c h - o f f voltage w i t h i n 0.1 v o l t for more than 10 wafers. (d) S e l f - A l i g n e d Gate Techniques One of the MESFET f a b r i c a t i o n problems i s to l a y down the gate metal a c c u r a t e l y between the source and the d r a i n regions and, at the l e a s t , to avoid h i t t i n g the source or the d r a i n . This r e q u i r e s that enough space should be l e f t between the source and the d r a i n . However, more space solves the problem of the gate alignment, but introduces the problem of having higher source and d r a i n r e s i s t a n c e s . Large distances between the source and the d r a i n can be t o l e r a t e d f o r t r a n s i s t o r s w i t h t h r e s h o l d voltages of large negative values because of t h e i r low channel r e s i s t a n c e (which i s not the case f o r enhancement mode devices or d e p l e t i o n mode devices with low negative threshold voltage values. 33 Therefore, some sort of s e l f - a l i g n i n g process must be used to a l i g n the gate a u t o m a t i c a l l y between the source and the d r a i n r e g i o n . The f i r s t GaAs s e l f aligned gate technique was developed by C a t h e l i n et a l . [ 6 ] . Then two more advanced techniques were developed; the f i r s t was the " s e l f a l i g n e d i m p l a n t a t i o n for n+ l a y e r " (SAINT) and the second was the s e l f a l i g n e d gate using r e f r a c t o r y metals or s i l i c i d e s . ( i ) S e l f - A l i g n e d Implantation f o r n+ Layer Technique (SAINT) The SAINT process, developed by Yamasaki [38], s t a r t s by forming the channel l a y e r then d e p o s i t i n g 1500A of SigN^ on the top of the wafer (see F i g . ( 2 - 9 ) ) . On the top of the SigN^ l a y e r a m u l t i l a y e r scheme i s formed. This scheme c o n s i s t s of 0.8 ym of p o l y t e t r a - f l u o r o p r o p y l methacrylate (PFM) r e s i s t , 0.3 urn of S i 0 2 , and 1350J p h o t o r e s i s t on the top. The top r e s i s t i s patterned and the S i 0 2 i s etched by a r e a c t i v e ion beam etching using CF l f-ffl 2. The bottom r e s i s t i s then etched using a r e a c t i v e i o n etching i n 0 2 d i s - charge. The top p h o t o r e s i s t on the top of the S i 0 2 l a y e r i s a l s o etched during the etch of the bottom one. This process r e s u l t e d i n an undercut s t r u c t u r e because of the r e s i s t a n c e of S i 0 2 to the 0 2 plasma. The amount of the undercut i s a f u n c t i o n of the etching time of the r e s i s t . The n+ implan- t a t i o n i s then c a r r i e d out using high dose and energy; the area under the undercut w i l l not be implanted by the n+ i m p l a n t a t i o n where i t i s protected by the S i 0 2 l a y e r . Next, a second l a y e r of S i 0 2 i s deposited. The S i 0 2 adhering to the side w a l l of the m u l t i l a y e r i s removed by immersing i n buf- fered HF f o r a few seconds while the S i 0 2 l a y e r on the top of the r e s i s t i s removed by l i f t i n g i t o f f In acetone. At t h i s p o i n t , the wafer i s covered with S i 0 2 except f o r the areas which were covered by the m u l t i l a y e r 34 M l 111 PHOTO- RESIST- • n 7 (a) n-IMPLANT TOP RESIST. S i 0 2 FPM ) RESIST ) Si 3 N 4 (b)TOP RESIST PATTERNING U l I It 111 '/j/// n nnnmunmm7T7_ (c) n + - IMPLANT (d)Si0 2 SPUTTERING Fig.(2-9) SAINT process. SOURCE DRAIN (f) OHMIC CONTACT FORMATION Fig.(2-9) Cont. 36 s t r u c t u r e , or i n other words, except f o r the gate areas. A f t e r annealing and a l l o y i n g the ohmic contact metals, the wafer Is etched i n CF^ plasma to etch the S i 3 N t t over the gate areas. The S I 0 2 l a y e r p r o t e c t s the other areas because the etching rate of i t i s 1/5 that of the SigN^ [38]. Gate metal i s then deposited. The metal w i l l be i n contact with the GaAs surface at the area predetermined by the m u l t i l a y e r s t r u c t u r e which i s a u t o m a t i c a l l y a l i g n e d between the n+ areas. E l e c t r o n beam lithography was used i n the SAINT process by Kato et a l . [39] to f a b r i c a t e short channel devices. In t h i s approach a four l a y e r m u l t i r e s i s t of negative p h o t o r e s i s t CMS, molybdenum, S i 0 2 , and p o s i t i v e p h o t o r e s i s t AZ 1470 were used. Using t h i s approach i t was p o s s i b l e to f a b r i c a t e a r i n g o s c i l l a t o r w i t h 0.3um gate length which r e s u l t e d i n a 16.7 ps delay per gate. ( i i ) R e f r a c t o r y Metals S e l f - A l i g n e d Gate Techniques The other s e l f - a l i g n e d gate technique developed by Abe et a l . [40] and others u t i l i z e s r e f r a c t o r y metals or s i l i c i d e s . The idea i s to perform the n+ i m p l a n t a t i o n w i t h the gate metal a c t i n g as a mask to protect the channel from the high dose i m p l a n t a t i o n . The sample i s then annealed with the gate i n p lace. The gate metal must be able to withstand the annealing temperature without degradation i n b a r r i e r height or i d e a l i t y f a c t o r of the contact. The f a b r i c a t i o n steps of t h i s technique can, using TiW or r e f r a c t o r y m e t a l , be summarized as (a) wafer p r e c l e a n i n g , (b) n-implantation, 37 (c) d e p o s i t i o n of TiW gates (TiW a l l o y i s 10:90wt.% Ti:W), (d) n+ i m p l a n t a t i o n , (e) S i 0 2 or S:L3Nlt d e p o s i t i o n and annealing, and ( f ) ohmic contact d e p o s i t i o n and a l l o y i n g . In t h i s approach, there i s d i r e c t contact between the gate metal and the n+ areas, therefore the n+ imp l a n t a t i o n energy should be high enough to bury the i m p l a n t a t i o n c a r r i e r c oncentration peak f a r from the sur f a c e . Abe et a l . [40] have shown that f o r an impla n t a t i o n dose of 1.7x10 1 3 ions/cm 2 and energy of 175 KeV the gate d r a i n breakdown voltage was about 6 v o l t s . Another approach f o r s o l v i n g the low drain-gate breakdown voltage i s the use of the T-gate s t r u c t u r e developed by Levy et a l . [41], Sadler et a l . [42] and others. The idea of t h i s s t r u c t u r e i s to have a dummy gate over the TiW which w i l l give a T-structure when the TiW i s etched i n CF4 plasma. The dummy gate metal should be r e s i s t a n t to the CF4 plasma e t c h i n g . The candidate metals are A l or N i . Fig.(2-10) shows the f a b r i c a t i o n steps of t h i s approach as described by Sadler which are: (a) wafer p r e c l e a n i n g , (b) channel implant, (c) TiW d e p o s i t i o n (by s p u t t e r i n g ) , (d) dummy gate metal d e p o s i t i o n (by o p t i c a l l i t h o g r a p h y ) , (e) etching the unmasked TiW using CF^ or CF l +0 2 plasma etching ( t h i s leads to the undercut as shown i n F i g . ( 2 - 1 0 . e ) ) , ( f ) n+ implant, (g) capping and annealing, 38 i 14 I 11 I 1 J1 I i I 1 H 1 11 AZ1450J — > n (a) n-IMPLANT TiW ^ S \ S \ \ \ \ \ ^ M \ \ ^ ^ ^ ( U A | Lip J OFF n n n i n n u 111 n i i i n TiW At n n* [~rT] n* (c) n*-IMPLANT Si 3 ^ n (d) ANNEALI NG AuGe/Ni J _ n n n (f) OHMIC CONTACT FORMATION Fig.(2-10) TiW self aligned gate process. 39 (h) ohmic contact metal d e p o s i t i o n and a l l o y i n g , ( i ) i m p l a n t a t i o n f o r the i s o l a t i o n between devices, ( j ) crossover d i e l e c t r i c d e p o s i t i o n , and (k) second l e v e l metal d e p o s i t i o n . Levy et a l . [41] has reported a t r a n s i t time delay of 25 ps and a power time delay product of 18 f j f o r a t r a n s i s t o r f a b r i c a t e d using t h i s technique. Sadler et a l . [42] have shown that TiW a l l o y e x h i b i t e d unstable Schottky diode c h a r a c t e r i s t i c s with short annealing c y c l e s at temperatures higher than 750°C, due to m e t a l l u r g i c a l r e a c t i o n between the T i , W, and GaAs. For t h i s reason, Yokayama et a l . [43] used TiW s i l i c i d e i n s t e a d . They claimed that no r e a c t i o n was n o t i c e d between the TiW s i l i c i d e and GaAs a f t e r 1 hour of annealing at 850°C, however they showed some i r r e g u l a r i t y i n b a r r i e r height and i d e a l i t y f a c t o r [44]. Tungsten s i l i c i d e s [44] or tantalum s i l i c i d e [45] can be used a l s o as a gate metal. In any case, i t i s d e s i r a b l e that the gate a l l o y or s i l i c i d e should have a thermal expansion c o e f f i c i e n t value close to that of the GaAs, s t a b l e diode c h a r a c t e r i s t i c s a f t e r annealing, and low r e s i s t a n c e i n order to be used i n t h i s s e l f - a l i g n e d gate technique. 40 CHAPTER(3) DEVICE AND CIRCUIT FABRICATION The f a b r i c a t i o n processes used i n our work w i l l be presented i n t h i s chapter. These processes include the ion-implanted planar technique, the recessed gate technique, and a new s e l f - a l i g n e d gate technique using polyimide, developed i n our l a b o r a t o r y . 3-1 The Chip Layout The software layout p a t t e r n was generated using the UBC CIF program. This p a t t e r n was cut on a 30x40 inc h r u b y l i t h using the c u t t e r program i n the PDP8E computer. The r u b y l i t h was sent to P r e c i s i o n Photomask Co. f o r photoreduction, step, and repeat. Masks f o r r e g i s t r a t i o n marks, channel implant, n + implant, ohmic contact m e t a l l i z a t i o n , gate m e t a l l i z a t i o n , f i r s t l e v e l of m e t a l l i z a t i o n , v i a holes between f i r s t and second l e v e l s of m e t a l l i z a t i o n , and second l e v e l of m e t a l l i z a t i o n were designed. The f i r s t four masks, shown i n F i g . ( 3 - 1 . a ) , were put on one photographic p l a t e and the second f o u r , shown i n F i g . (3-1.b), on another. The chip c o n s i s t s of f i v e major sec t i o n s (as shown i n F i g . ( 3 - 2 ) ) . The f i r s t s e c t i o n c o n s i s t s of 7 subsections which c o n t a i n : a 2pm gate length MESFET, a 4ym MESFET, a diode, 3 pads f o r measuring the sheet r e s i s t a n c e of th n+ implant, 3 pads f o r measuring the sheet r e s i s t a n c e of the n and n+ implant, and a f a t FET f o r mesuring the d r i f t m o b i l i t y and the c a r r i e r c o n c e n t r a t i o n p r o f i l e s of the channel. These subsections are l a b e l l e d A l , A2, A3, A4, A5, A6, and A7 r e s p e c t i v e l y . The second s e c t i o n (B) i s a 3 b i t if 3 E 3 Q • a o • a B 8 Ohmics n o i Reg. Marks. 0 a „ o i E3D8 r r S o f t &|j Ofl n i ) t o • a s flafl 11 Fig.(3-1) Chip masks layout (a) registration marks, n, n +, and ohmic contact metallization; (b) gate, f i r s t level metallization, via holes, and second level metallization. CM g L ^ G ^ - i l s t level 02nd n n U 3 W c • ^ • • • • • • • ^ • • • • • • • • • • 1 = 1 • • • • • IT Gates o • • • [Q] Holes f O O D • • D O O o • -a — • • • O O D • • • • • • • D D a n • „ a • Fig.(3-1) (b) CO Fig.(3-2) Chip layout. 44 DAC with 4um MESFETs used as current sources while the t h i r d (C) s e c t i o n i s a 3 b i t DAC but with saturated r e s i s t o r s as current sources i n s t e a d . The f o u r t h s e c t i o n (D) contains an i n v e r t e r (on the r i g h t ) and a buff e r c i r c u i t (on the l e f t ) f o r the CDFL. The f i f t h s e c t i o n (E) contains an OR gate (on the r i g h t ) and an AND gate (on the l e f t ) f o r the same l o g i c . 3-2 F a b r i c a t i o n Processes Three d i f f e r e n t techniques were used. These were the ion-implanted planar technique, the recessed gate technique, and the s e l f a l i g n e d gate technique using polyimide. The ion-implanted planar technique was used at the beginning to f a b r i c a t e devices w i t h threshold voltages around -1.0 V and to r e a l i z e the a b i l i t y to c o n t r o l the pin c h - o f f v o ltage using i on i m p l a n t a t i o n . However, unacceptable s e r i e s r e s i s t a n c e s were observed when |Vth| was reduced to l e s s than 0.5 V. These high r e s i s t a n c e s can be a t t r i b u t e d to the use of t h i n and l i g h t l y doped channels (which have l e d i n turn to the increase of the sheet r e s i s t a n c e ) and the d e p l e t i o n of most of the unmodulated channel due to the surface s t a t e s . The recessed gate technique was then attempted i n order to a l l e v i a t e t h i s problem; however, u n i f o r m i t y of the device parameters was not acceptable. The TiW s e l f - a l i g n e d gate was then t r i e d , but p o s s i b l e r e a c t i o n between the TiW and the GaAs r e s u l t e d i n an unacceptable y i e l d (see Chapter(2)). The SAINT process has not been t r i e d due to the process complexity and the requirement of a s o p h i s t i c a t e d m u l t i l a y e r r e s i s t . I nstead, a new s e l f a l i g n e d gate 45 technique using polyimide was developed. In t h i s technique, no r e f r a c t o r y metals or m u l t i l a y e r r e s i s t s were used. Therefore, nearly 100% production y i e l d was obtained f o r 3 samples. (a) The Ion-implanted Planar Technique The ion-implanted planar technique developed by Rockwell [3] was the f i r s t to be used. The f a b r i c a t i o n steps are shown s c h e m a t i c a l l y i n F i g . ( 3 - 3 ) . The s t a r t i n g m a t e r i a l was Cominco s e m i - i n s u l a t i n g LEC GaAs wafer. This was f i r s t degreased using acetone, 2-propanol, and t r i c h l o r o e t h y l e n e to d i s s o l v e any wax or grease remaining a f t e r shipping and handling. The wafer was then etched i n [21] 4H 2S0 t + : 1H 20 2 : 1H 20 by volume to remove the damaged layer (as discussed i n Chapter(2)). This step i s c r i t i c a l because i t could r e s u l t i n a very rough surface, t h e r e f o r e the temperature and the s o l u t i o n c oncentration must be c o n t r o l l e d . Another etching procedure can be used [93] where the wafer was immersed i n f i l t e r e d 1% Alconox f o r about 3 minutes and then etched i n SNH^OH : 2H 20 2 : 240H 20 by volume f o r 30 seconds (see App e n d i x ( C - l ) ) . The above s o l u t i o n r e s u l t e d i n the d i s s o l u t i o n of about 50nm of GaAs. P h o t o r e s i s t was used to patte r n the r e g i s t r a t i o n marks, then the wafer was dipped i n t o 10% HC1 f o r 1 minute to d i s s o l v e the n a t u r a l oxide. The r e g i s t r a t i o n marks were then etched i n t o the GaAs using 5% H 3P0 l t : 2.5% H 2 0 2 : 92.5% H 20 by volume f o r 70 seconds to d i s s o l v e about 80 nm of GaAs. 46 u A Z 1 4 5 0 J ^ ' HIllllUl 7 /{ (a) r>-IMPLANT n (b) n*-IMPLANT 11. 111 Wil l K i n * 1 Si 3 N W \ m T i ; , c , A N N E A U N | Au Ge (d)OHMIC C O N T A C T METAL DEPOSITION Fig.(3-3) Ion-implanted planar f a b r i c a t i o n process adapted at UBC. 47 Al N, n W/A n POLYIMIDE (e)GATE METAL DEPOSITION E E I - r ' i ^ r - . f g ) POLYIMIDE (f)lSi L E V E L METALLIZATION COATING ^J(h)2Dd L E V E L METALLIZATION F i g . (3-3) Cont. 48 The channel and the n+ l a y e r were formed by implanting S i 2 8 or S i 2 9 (Figs.(3-3.2) and (3-3.b). The doses and energies used are tabulated i n Table (3-1). P h o t o r e s i s t was used as an i m p l a n t a t i o n mask f o r both implants. Acetone was used to remove the p h o t o r e s i s t a f t e r the channel i m p l a n t a t i o n and hot negative m i c r o s t r i p r e s i s t ( P h i l i p A Hunt Chemical Corp.) or C*2 plasma (see Appendix(C-2)) were used to remove the residues of the p h o t o r e s i s t . These residues were hard to remove a f t e r the n + Implantation, e s p e c i a l l y i f high doses and energies were used. Annealing was the major problem i n the past where f u l l or p a r t i a l cap l i f t - o f f a f t e r annealing were t a k i n g place, F i g . ( 3 - 4 ) . The reason f o r the cap l i f t - o f f was the existence of some 0 2 atoms i n s i d e the d i e l e c t r i c or on the GaAs su r f a c e . An experiment has been performed to solve t h i s problem which includes the study of the e f f e c t of the treatment w i t h 0 2 plasma, ammonia plasma N 2 plasma, immersing i n buffered HF immediately before l o a d i n g , purging the chamber immediately a f t e r l o a d i n g , and f l u s h i n g the chamber with Ar before applying the gases (see Tab l e ( 3 - 2 ) ) . This experiment has shown t h a t , f o r s u c c e s s f u l annealing, the f o l l o w i n g steps are needed when de p o s i t i n g the SigN^ l a y e r : (a) n a t u r a l oxide must be etched, (b) the chamber must be purged to remove any dust entered during the loading of the samples, (c) the system must be flushed with Ar before admitting the gases, (d) no 0 2 treatment should be performed i n s i t u before d e p o s i t i n g the f i l m , and TABLE(3-1) Implanted doses and energies and the r e s u l t a n t threshold voltages n n+ U a f o r J , " C o in i** 1 A it v Walci V oainpXc It V t h Dose Energy Dose Energy 10 1 2/cm 2 keV 10 1 2/cm 2 keV (V) 344S8 l 2.24 125 4.8 125 -1 2 2.24 100 4.8 100 -2.5 3 1.6 100 4 100 -1.8 4 1.45 100 3.37 100 -1.35 A4 1.6 75 4 100 -0.65 175S52 A5 1.6 80 4 100 -1.2 B5 1.3 75 1.9 100 -0.6 C5 1.6 70 1.6 100 -1.0 D5 1.3 70 1.6 100 -0.5 E5 1.6 60 1.6 100 -0.6 175S53 F6 1.5 60 1.6 100 -0.6 175S54 C7 3.25 120 - - -0.6 D7 3.25 120 - - -0.6 E7 3.25 120 4.8 180 -2.5 50 Fig.(3-4) Photograph of S i 3 N t t l i f t - o f f a f t e r annealing. 51 TABLE(3-2) E f f e c t of d i f f e r e n t treatments p r i o r to the d e p o s i t i o n of SigN^ sample # Q>2 plasma treatment before S i 3 N 1 + d e p o s i t i o n Oxide removal p r i o r to the loa d i n g using HC1 Ammonia plasma pre- treatment N 2 plasma treatment System f l u s h i n g before d e p o s i t i o n S i 3 \ l i f t - o f f A l yes - - - yes yes B l yes - - - - yes CI - - - - yes p a r t i a l Dl - - - - - p a r t i a l Gl yes yes - - yes p a r t i a l HI - yes yes - yes no H2 - yes - yes yes no 52 (d) ammonia or ni t r o g e n plasma must be a p p l i e d to remove, i n s i t u , any residues of oxide. S u c c e s s f u l annealing was obtained a f t e r applying these steps. I t was found that the thickness of the SigN^ f i l m should not exceed 80 nm otherwise the f i l m w i l l crack. Annealing was performed i n N 2 atmosphere at 830°C f o r 25 minutes. The wafer was then cooled down and the Si3N4 was s t r i p p e d using concentrated HF. The next step was to lay down the ohmic contact metal. The a l l o y used i n our experiment was AuGe with 12% Ge by weight. The s i n g l e l i f t - o f f technique developed by IBM [46] was used. As shown i n F i g . ( 3 - 5 ) , AZ 1450J p h o t o r e s i s t was spun over the wafer at 4500 rpm, soft-baked at 70°C f o r 30 minutes, and then exposed using the appropriate mask f o r 1.5 minutes. The p h o t o r e s i s t was then soaked i n chlorobenzene f o r about 3 minutes. Chlorobenzene caused the top p h o t o r e s i s t l a y e r to be hardened against the developer which r e s u l t e d i n an undercut when developed, as shown i n F i g . ( 3 - 5 . e ) . This undercut made i t easy to remove the unwanted evaporated metal when the wafer was immersed i n hot acetone or another p h o t o r e s i s t s t r i p p e r . To ensure good ohmic contact the wafer was dipped i n t o buffered HF or 10% NH1+0H i n de-ionized water f o r about 30 seconds to remove any oxide which might have grown during previous steps. Immediately a f t e r t h a t , the wafer was loaded i n t o the evaporator (VEEC0) and the metal was evaporated. The AuGe was then l i f t e d o f f using hot acetone and a g i t a t e d i n an u l t r a s o n i c a g i t a t o r . The r e s u l t of the l i f t - o f f step i s shown i n Fi g . ( 3 - 5 . g ) . The exposed area clean substrate photoresist deposition UV-expoaure A 2. chXorobenzene soak modified layer photoresist development metal pattern' :EZL removal of photoresist metal evaporation n . undercutting of the unmodified photoresist Fig.(3-5) Single l i f t - o f f procedure. 54 ohmic contact was obtained by a l l o y i n g the AuGe i n N 2 atmosphere at 450°C f o r 5 minutes. A l was used f o r the gate contacts and both f i r s t and second l e v e l s of m e t a l l i z a t i o n . A s i n g l e l i f t - o f f technique was used a l s o f o r the A l deposi- t i o n . The f i r s t l e v e l of m e t a l l i z a t i o n was separated from the second one by a l a y e r of polyimide. S i j N ^ was used f i r s t , but i t caused damage to the channel. Annealing at 450°C could not cure t h i s damage. Therefore, polyim- ide PI 2550 from DuPont was used i n s t e a d . Polyimide, d i l u t e d with thinner ( 1 : 1 ) , was spun at 8000 rpm to give a la y e r of about 8000 A. The wafer was s o f t baked at 150°C f o r 30 minutes and then cooled down to room temperature. P h o t o r e s i s t AZ 1450J was spun over the polyimide, s o f t baked, and exposed. The wafer was then developed i n 1MF312 : 1H 20 s o l u t i o n by volume f o r about 1 minute to etch both the p h o t o r e s i s t and the polyimide i n one step. The wafer was then loaded i n t o the evaporator and the v i a holes were f i l l e d w i t h A l . A f t e r l i f t i n g o f f the unwanted metal, the polyimide was hard baked at 180°C f o r 2 hours to make i t r e s i s t a n t to the developer. F i n a l l y , the second l e v e l of m e t a l l i z a t i o n was deposited using the s i n g l e l i f t - o f f technique. Fig(3-6) shows a micrograph p i c t u r e of the t e s t and monitoring devices f a b r i c a t e d using t h i s technique. The I-V c h a r a c t e r i s t i c s of both a 2pm gate and a f a t FET t r a n s i s t o r s f a b r i c a t e d using t h i s technique are shown i n F i g . ( 3 - 7 ) . The transconductance fo r the 2 pm gate t r a n s i s t o r , w i t h threshold voltage of -2.4 V, was found to be 53 mS/mm which i s considered reasonable f o r these gate dimensions [47]. Good u n i f o r m i t y f o r both the thr e s h o l d voltage and the current s a t u r a t i o n across the wafer was observed. The standard d e v i a t i o n f o r V was Fig.(3-6) Micrograph p i c t u r e of the t e s t and monitoring devices. 56 10.00 < E 1.000 /div 0000 .0000 0 — 0-b - 1.0 - 1.5 - 2.C VDS .4000/div ( V) 4.000 1.000 < E 1000 0000 .0000 0 - J 4 • 0 — Lb VDS .5000/div ( V) 5.000 Fig.(3-7) I-V c h a r a c t e r i s t i c s of (a) 2um gate and (b) f a t FET t r n a s i s t o r s f a b r i c a t e d using the ion-implanted planar process. 57 10 e l 3 el CD 2 A l i o r 100 200 300 400 Isat(uA) 500 600 m Z3 Z • • • -—I • » -0-5 -1-0 -15 Vlh(V) Fig.(3-8) V and I histograms f o r sample /M. 58 found to be 35 mV f o r an average value of -1.38 V, F i g . ( 3 - 8 . a ) . The standard d e v i a t i o n f o r the s a t u r a t i o n current was 21 uA f o r an average value of 447 uA, F i g . ( 3 - 8 . b ) . The f a t FET was used i n t h i s study i n s t e a d of the 2pm gate FET i n order to reduce the e f f e c t of the s e r i e s r e s i s t a n c e , where i n t h i s case the channel r e s i s t a n c e was much higher than the s e r i e s r e s i s t a n c e . The good u n i f o r m i t y can be a t t r i b u t e d to the high q u a l i t y f o r the channel due to the s u c c e s s f u l annealing, (b) Recessed Gate Technique This process i s , i n general, s i m i l a r to the ion-implanted planar process except that the channel i s etched f o r the gate recess. The wafer was cleaned using the Rockwell precleaning procedure (see Ap p e n d i x ( C - l ) ) , then the r e g i s t r a t i o n marks were etched as explained i n the previous s e c t i o n . The channel was formed by implanting S i 2 ^ with a dose of 3.25x10 1 2 ions/cm 2 and energy of 120 keV (see F i g . ( 3 - 9 ) ) . For s i m p l i c i t y no n + l a y e r was formed where the n l a y e r was t h i c k enough and h i g h l y doped. 80 nm of SigN^ was deposited f o r annealing which was performed at 830°C f o r 25 minutes. AuGe was deposited and a l l o y e d at 450°C f o r 5 minutes. The gate was recessed by p a t t e r n i n g the p h o t o r e s i s t , as discussed before, then the wafer was dipped i n t o 10% HC1 to remove the oxide before i t was immersed i n a s o l u t i o n of 5% H 2P0 1 + : 2.5% H 2 0 2 : 92.5% H 20 by volume f o r 85 seconds to remove about 100 nm of GaAs. Removing the oxide r e s u l t i n g from the etching process was done by immersion i n t o buffered HF f o r 30 seconds immediately before loading Into the metal evaporator for gate metal d e p o s i t i o n . 59 AZ1450J- UUll l l l l (a) r>-IMPLANT n 11. [111 ill IJU 11 y. 'A n n A (b) n*-l MPLA N T 3 4 ^ . (c)ANNEALING r~ i _ Au Ge (d)OHMIC C O N T A C T METAL DEPOSITION (e) CHANNEL ETCHING Fig.(3-9) Recessed gate process adapted at UBC. 60 Al (f)GATE METAL DEPOSITION Al X ^ K ( g ) l S - t L E V E L p^j J ) METALLIZATION POLYIMIDE Al illllllllllllll! (h) POLYIMIDE COATING (i)2nd L E V E L METALLIZATION F i g . ( 3 - 9 ) Cont. 61 Fig.(3-10) I-V c h a r a c t e r i s t i c s of (a) 2um gate and (b) f a t FET t r a n s i s t o f a b r i c a t e d using the recessed gate process. 62 Fig.(3-10) shows the I-V c h a r a c t e r i s t i c s of a 2 ym gate and a fat FET t r a n s i s t o r f a b r i c a t e d using t h i s technique. As shown i n the f i g u r e , the f a t FET t r a n s i s t o r i s an enhancement-mode device while the 2 ym gate t r a n s i s t o r i s a d e p l e t i o n mode t r a n s i s t o r with a -2.5 v o l t t h r e s h o l d v o l t a g e . The b i g d i f f e r e n c e i n the threshold voltages i s b e l i e v e d to be due to a d i f f e r e n c e i n the amount of GaAs etched from the channel. Both t r a n s i s t o r s were f a b r i c a t e d on the same c h i p , but the etching rate was perhaps d i f f e r e n t due to the strong e f f e c t of the surface tension i n the case of short l i n e widths. The dependence of the etching rate on the gate dimensions may make i t harder to c o n t r o l the threshold voltage of more than one set of devices w i t h d i f f e r e n t gate lengths on the same chip. The transconductance f o r the 2 pm gate one was found to be 40 mS/mm which i s ne a r l y 25% l e s s than that of the ion-implanted planar process. This r e d u c t i o n i n the transconductance can be a t t r i b u t e d to the low e l e c t r o n m o b i l i t y due to the use of high doses to form the channel, see r e l a t i o n (1-10). The standard d e v i a t i o n f o r the threshold voltage was -1.15 V with an average value of -2.34 V as shown i n Fig.(3-11.a). The s a t u r a t i o n current u n i f o r m i t y was even worse, e x h i b i t i n g a standard d e v i a t i o n of 3.9 mA f o r an average value of 5.1 mA (Fig.(3-11.b). The s c a t t e r i n g of V , and I can be th sat a t t r i b u t e d to the nonuniform etching of the channel because of the etching r a t e s e n s i t i v i t y to the etchant temperature and conc e n t r a t i o n across the wafer. However more c o n t r o l l e d etching can be obtained, i t may be hard to achieve a u n i f o r m i t y s i m i l a r to that of the ion-implanted planar process. in oc o I— in in z < DC b a. UJ m z 5 - -1 -2 Vth -3 -4 UJ £0 z 6 4 2 0 8 10 l s a t (mA) Fig.(3-11) V and I histograms f o r sample D7. 64 (c) The S e l f - A l i g n e d Gate Using Polyimide (SAGUPI) In t h i s process, polyimide PI2550 from DuPont i s used as an intermediate l a y e r . A schematic diagram of the SAGUPI i s shown i n F i g . ( 3 - 1 2 ) . The process s t a r t s w i t h the regular c l e a n i n g procedure as discussed i n s e c t i o n ( 3 - 2 ( a ) ) . Channel i m p l a n t a t i o n of S i 2 8 or S i 2 9 was c a r r i e d out using AZ1450J p h o t o r e s i s t as a mask. The doses and energies used ranged from 1.61x10 1 2 to 3.25x10 1 2 ions/cm 2 and from 60 to 120 keV r e s p e c t i v e l y . A la y e r of S i 3 N l + was deposited (see Appendix(C-3)) to serve l a t e r as a cap f o r annealing. Polyimide (1 PI : 2 thinner by volume) was spun over the S i j N ^ l a y e r at 5000 rpm f o r 30 seconds, then s o f t baked at 180°C f o r 30 minutes to increase I t s r e s i s t a n c e to the p o s i t i v e r e s i s t developer (MF312). Dummy gates of A l were deposited over the polyimide using the s i n g l e l i f t o f f , described before i n t h i s Chapter. The unmasked polyimide was etched using 0 2 plasma (see Appendix(C-2)). A T-structure r e s u l t e d because of the r e s i s t a n c e of the dummy gate to the 0 2 plasma etch (see F i g . ( 3 - 1 2 . c ) ) . This undercut was used to protect the area underneath from being implanted with n + . This would allow about 300 nm space between the gate metal and the n + areas. A f t e r the n + i m p l a n t a t i o n , S i 0 2 was sputtered using Ar only (without 0 2) to reduce the r i s k of the polyimide being etched by 0 2 plasma (see Appendix(C-4)). A f t e r the S i 0 2 d e p o s i t i o n , the polyimide was d i s s o l v e d i n hot n-methyl-2-pyrrolidone to l i f t o f f the dummy gates as shown i n F i g . ( 3 - 1 2 . f ) . This step r e s u l t e d i n covering the whole wafer except the gate areas w i t h S i 0 2 . The wafer was then ready f o r annealing which was c a r r i e d out at 830°C f o r 25 minutes i n N 2 atmosphere. Holes f o r the ohmic contact metals (AuGe were etched i n the S i O ? and 65 1 I 1 1 I I 1 I I (a) AZU50J n- IMPLANT POLYIMIDE (b) S i 3 N 4 Al LIFTOFF Al POLYIMIDE (c) S i 3 N A - 7 Y,y,,,,,,,W?,,,,,,,y^ POLYIMIDE ETCHED USING 0 2 PLASMA (d) AZH50J n + IMPLANT Fig.(3-12) S e l f - a l i g n e d gate technique u s i n g polyimide (SAGUPI). 66 Fig.(3-12) Cont. 67 Si3N^ l a y e r s using buffered HF and C F 4 plasma r e s p e c t i v e l y (see Appendix(C-5)). A f t e r a l l o y i n g the AuGe at 450°C f o r 5 minutes the SigN^ over the gate areas was etched using CF^ plasma while the S i 0 2 served as a mask to pr o t e c t other areas. The gate metal was then deposited. The gates were i n contact w i t h the channel i n the areas which were not covered with S i 0 2 . F i n a l l y , the f i r s t and the second l e v e l of m e t a l l i z a t i o n was deposited as discussed i n the f i r s t s e c t i o n of t h i s chapter. Fig.(3-13) shows the I-V c h a r a c t e r i s t i c of a 2 p gate and a f a t FET t r a n s i s t o r f a b r i c a t e d using t h i s process. The transconductance f o r the 2 ym gate t r a n s i s t o r was 62 mS/mm which i s about 50% higher than that of the recessed gate t r a n s i s t o r and 17% higher than that of the ion-implanted planar t r a n s i s t o r . The increase of the g i n the present technique can be m a t t r i b u t e d to the reduction i n the s e r i e s r e s i s t a n c e and may be due to the re d u c t i o n i n the gate length due to the dummy gate undercut. In terms of u n i f o r m i t y , t h i s technique gave much b e t t e r u n i f o r m i t y than the recessed process. The u n i f o r m i t y could be s i m i l a r to that of the ion-implanted planar process, where i n both cases no channel etching has taken p l a c e . Fig.(3-14) shows the histogram of both V . and I . The r th sat f i g u r e s show a standard d e v i a t i o n of V ^ of -0.145 f o r an average of -2.62 V and I standard d e v i a t i o n of 240 uA f o r an average of 1.74 mA. sat The SAGUPI process d i f f e r s from the SAINT process i n that instead of the p h o t o r e s i s t (FPM or AZ) above the SigN^ to ob t a i n an undercut, we use polyimide. This has s e v e r a l advantages: 68 ID (mA) 20.00 2.000 /div .0000 .0000 ve -OU Start .OOOOV •top -a.eooov 8t«p - .OOOOV o v VDS .4000/dlv ( V) 4.000 Fig.(3-13) I-V c h a r a c t e r i s t i c s of (a) 2um gate and (b) f a t FET t r a n s i s t o r s f a b r i c a t e d using SAGUPI technique. 12 10 X* 8 -1 -2 -3 -A rth 'sat 2 (mA) Fig.(3-14) V , and I histograms f o r sample Fig.(3-15) SEM micrograph f o r gate undercut a f t e r 0 2 plasma etching p o l y i m i d e . (a) i t has greater heat r e s i s t a n c e , thus a l l o w i n g more choice of metal d e p o s i t i o n ; (b) i t i s more r e s i s t a n t to the s p u t t e r i n g process used to deposit S i 0 2 ; (c) the polyimide i s not p h o t o s e n s i t i v e , therefore a simple l i f t - o f f process can be used to deposit the dummy gate i n s t e a d of the m u l t i p l e l a y e r r e s i s t i n the SAINT process. As compared to the r e f r a c t o r y metal (or s i l i c i d e ) gate processes, the f i n a l gate m e t a l l i z a t i o n has to be i n good alignment with the holes etched f o r i t i n the SigN^ ( i n s t e a d of being i n place throughout). However, t h i s i s not too d i f f i c u l t s ince the overlap necessary to ensure covering the hole goes over the r e l a t i v e l y t h i c k S i 0 2 + S i 3 N l t and hence should not produce excessive e x t r a capacitance* The main advantage of the new technique over the r e f r a c t o r y metal one i s the lack of the requirements that (a) the gate should withstand the high temperature p o s t - i m p l a n t a t i o n anneal, (b) no r e a c t i o n should take place between the gate metal and the GaAs su b s t r a t e , (c) the thermal expansion of both the gate metal and the GaAs should be matched to avoid the gate l i f t i n g o f f during the annealing, (d) good adhesion must be ensured between the gate metal and both the GaAs wafer and the dummy gate, and (e) an extremely clean and 0 2 f r e e i n t e r f a c e between the gate metal and the GaAs m a t e r i a l must be ensured. The l a c k of these requirements gave more freedom i n choosing a gate m a t e r i a l s s t r u c t u r e to s a t i s f y the e l e c t r i c a l requirements of a good Schottky diode and low s e r i e s r e s i s t a n c e . Moreover, adhesion can be enhanced between 72 the polyimide and the SigN^ by using an adhesion promoter, such as VM-651 from DuPont, and between the dummy gate and the polyimide by etching the l a t t e r i n 0 2 plasma f o r 5 seconds to increase the roughness of the polyimide s u r f a c e . 73 CHAPTER(4) DC MEASUREMENTS In t h i s Chapter, the D.C. measurements and the temperature dependence of the d e p l e t i o n mode t r a n s i s t o r s are presented. Fat FETs, 2um gate t r a n s i s t o r s , and pads f o r ohmic contact and implanted l a y e r c h a r a c t e r i z a t i o n were used. T r a n s i s t o r parameters (V , , I , g , and g.), Schottky contact th sat m °d parameters ( i d e a l i t y f a c t o r n, s a t u r a t i o n current I g and b a r r i e r height <t>kn)> implanted l a y e r parameters (sheet r e s i s t a n c e R e , m o b i l i t y u, and c a r r i e r c o n c e n t r a t i o n p r o f i l e , N ( x ) ) , and ohmic contact parameters (contact s p e c i f i c r e s i s t a n c e p ) were measured. The sample y i e l d was measured by counting the c number of working devices and measuring the t r a n s i s t o r parameters ( v t n and I ) to t e s t f o r u n i f o r m i t y across the wafer. The t r a n s i s t o r I-V Sat c h a r a c t e r i s t i c s were simulated using Spice2.G [14] and these r e s u l t s were compared with the experimental ones. The s i m u l a t i o n parameters 6, R , R., C , C and V , were obtained s d gs gd th from the experimental r e s u l t s . 8 was determined from the r e l a t i o n I = &(V - V , - I • R ) (4-1) sat gs th sat s f o r the f a t FET and from r e l a t i o n (1-8) from the 2ym FET t r a n s i s t o r [17]. R and R, were c a l c u l a t e d from the channel sheet r e s i s t a n c e , measured s d using the t e s t pad s t r u c t u r e (A3), and the spacing between the gate and both the source and the d r a i n . The ohmic contact r e s i s t a n c e s were taken i n t o c o n s i d e r a t i o n i n c a l c u l a t i n g R and R,. The threshold voltages were measured s d from the square law r e l a t i o n of / l vs. V by e x t r a p o l a t i n g the l i n e a r S3, t §S 74 region to i n t e r s e c t with the V a x i s to give the value of V , , as shown i n gs th F i g . ( 4 - 1 ) . The gate capacitance (C ' = 2C = 2C ,) was measured with the HP 8 8® 8̂* 4275A Multi-Frequency LCR meter. Fig.(4-2) shows both the experimental and the simulated I-V curves of the 2ym and f a t FET t r a n s i s t o r s . The s i m u l a t i o n parameters are shown i n Table(4-1). The experimental and simulated curves c o i n c i d e d f o r the long gate t r a n s i s t o r . In case of the short gate one (2urn FET), the two sets of curves c o i n c i d e d i n the s a t u r a t i o n regions and deviated i n the l i n e a r r e g i o n s . The d e v i a t i o n became le s s n o t i c e a b l e f o r l a r g e r negative values of Vg g. These r e s u l t s are i n agreement with those obtained by others [48]. The d e v i a t i o n of the simulated curve from the experimental one i s due to the d i f f e r e n c e i n the s a t u r a t i o n mechanism of the current where the current saturates i n the case of short channel t r a n s i s t o r s (<2um) due to the e l e c t r o n v e l o c i t y s a t u r a t i o n while the program considers the s a t u r a t i o n to be due to channel pinch o f f . The chip y i e l d and the device parameter u n i f o r m i t y across the wafer were I n v e s t i g a t e d . The y i e l d was as high as 100% f o r most of the samples. The y i e l d was l e s s than 100% f o r some samples due to the d e s t r u c t i o n of t r a n s i s t o r s at the edge of the wafer during the f a b r i c a t i o n process. Although the y i e l d obtained i n our l a b o r a t o r y cannot be compared with that obtained by i n d u s t r i a l firms where a very l a r g e number of devices are f a b r i c a t e d on complete wafers, our r e s u l t s can s t i l l give an i n d i c a t i o n of the y i e l d . Sample#4 was chosen f o r ths study because i t was the biggest p i e c e , w i t h 18 t r a n s i s t o r s on i t . The u n i f o r m i t y of sample#4 was discussed i n Chapter(3). -2.000 Fig.(4-1) / I . v s . V f o r a f a t FET t r a n s i s t o r . 76 ID (•A) 10.00 1.000 /div .0000 V6 Start Stop Stap .7800V -1.2300V - .2300V 0 7 5 a—r-a .0000 VDS .4000/diV ( V) 4.000 ID (a) (UA) ve 500.OL Start .OOOOV Stop -1.2300V • Stap - .2B00V 50.00 /div .0000 .0000 VDS 4000/div ( V) 4.000 •(b) F i g . ( 4 - 2 ) Experimental and simulated I-V c h a r a c t e r i s t i c s of (a) 2um gate and (b) f a t FET t r a n s i s t o r s from sample//4 ( measured and simulated). 77 TABLE(4-1) Simulation parameters f o r 2 ym gate and f a t FET t r a n s i s t o r s from sample#4 Parameter 2 ym FET Fat FET R8<n> 68 62 R d(fl) 180 104 vth< v> -1.37 -1.32 e(A/v 2) 2 . 8 x l 0 1 3 2 . 5 x l 0 - l t c gs 100 fF 10.8 pF C A gd 100 fF 10.8 pF 78 Schottky contacts were c h a r a c t e r i z e d by measuring the s a t u r a t i o n current I , the i d e a l i t y f a c t o r n, and the b a r r i e r height <)>, . As discussed i n s bn s e c t i o n (2-3), &n(l^) vs. curves were p l o t t e d and ext r a p o l a t e d to i n t e r s e c t w i t h the l n ( I ^ ) a x i s to give I ( F i g . ( 4 - 3 ) ) . $ was then c a l c u l a t e d from the r e l a t i o n s [2] $ b n = (kT/q) l n ( A * * T 2 / J g ) (4-2) with A =50 cm~ 2K~ 2 [72]. n was obtained from the r e l a t i o n n = (q/kT)(dV/d(£n(If))) (4-3) The measured i d e a l i t y f a c t o r and b a r r i e r height f o r the t r a n s i s t o r Schottky contacts were 1.13 and 0.795 eV r e s p e c t i v e l y at room temperature. Test patterns A3, A4, and A5 were used to measure the implanted l a y e r sheet r e s i s t a n c e s and the ohmic contact s p e c i f i c r e s i s t i v i t y . The tr a n s m i s s i o n l i n e model (TLM) was used to o b t a i n the values of these parameters. The TLM was o r i g i n a l l y proposed by Shockley [49] and modified by others [50-51]. F i g . (4-4) shows a schematic diagram of 3 pads where SL1 are 12 are the the distances between the pads and d i s the length of the pads. The t o t a l r e s i s t a n c e between any two pads i s given by R T = 2R C + ( R S H • 1/W) (4-4) where R„ i s the ohmic contact r e s i s t a n c e , R__, i s the sheet r e s i s t a n c e of the l a y e r between the pads, and W i s the pad width. H a r r i s o n et a l . [50] show that contact r e s i s t a n c e i s equal to R c = ( RSK ' V W ) * c o t h ( d / L T ) ( 4 " 5 ) where R_v i s the sheet r e s i s t a n c e of the l a y e r under the pads and L i s the so c a l l e d t r a n s f e r l ength. 1^ i s given by Fig.(4-3) L n ( I ) vs V f o r a f a t FET. 80 ^ 200 - i/) 2 h d i 2 .(4-4) Transmission Line Model (TLM) (a) p l o t of t o t a l contact to contact r e s i s t a n c e and (b) experimental measurements f o r o b t a i n i n g the t o t a l r e s i s t a n c e and the contact end r e s i s t a n c e v a l u e s . 81 LT = / P c / R S K <4~6> P c i s the contact s p e c i f i c r e s i s t a n c e i n ohm-cm2. For d > 2 L T > r e l a t i o n (4.5) leads to RT = ( 2 R S K * V / W + ( RSH * 1 ) / W ( 4 _ 7 ) Reeves et a l . [51] considered a value of d of 50 urn greater than 2 L T > Therefore, the previous c o n d i t i o n was v a l i d i n our case where pads of 100 \m length were used. R e l a t i o n (4-6) i s p l o t t e d i n Fig.(4-4) f o r sample#4. The i n t e r s e c t i o n with the v e r t i c a l and h o r i z o n t a l axes give the values of R r and L r e s p e c t i v e l y , where 2 R c = 2 RSH ' V W <4"8> and L X = 2 RSK * L T / R S H ^ So l v i n g equations (4-8) and (4-9) together, one can get the value of R c u. SH Knowing the value of e i t h e r L̂ , or RgK» the other can be obtained from r e l a t i o n (4-9) and p from r e l a t i o n (4-5). c Rcv. can be taken to be equal to R c„ i f the s i n t e r i n g d i d not modify bis. oil s i g n i f i c a n t l y the l a y e r underneath. I f i t d i d , the measurement of the s o - c a l l e d contact end r e s i s t a n c e R^ i s required to ob t a i n the value of L̂ , from the r e l a t i o n [50] R C/R E = cosh(d/L T) (4-10) The c l a s s i c a l way of measuring R^ i s to apply constant current between two contacts and measure the p o t e n t i a l between one of these contacts and an opposite outside contact, as shown i n F i g . ( 4 - 4 ) . R w i l l be V/1. Reeves E 82 et a l . [51] have shown that R_ = 1/2(R1 + R2 + R3) (4-11) E where R l , R2, and R3 are the t o t a l r e s i s t a n c e s between pads (1 and 2) , (2 and 3) and (3 and 1) r e s p e c t i v e l y . The sheet r e s i s t a n c e of the implanted l a y e r s w i t h n, n + and n plus n + were measured and shown i n Table(4-2). The s p e c i f i c contact r e s i s t a n c e of our samples was measured and found to range from high values of about 1.8><10-3 ohm-cm2 from sample#2 to about 6.5 x l 0 - 1 + ohm-cm2 f o r sample E7. The high values might be due to the f a i l u r e to etch the na t i v e oxide immediately before d e p o s i t i n g the AuGe a l l o y . The low values of P £ are reasonable f o r the low i m p l a n t a t i o n doses used and agree with the r e s u l t s reported by others [51]. The reason f o r using such low n + i m p l a n t a t i o n i s the need to use t h i s l a y e r to c o n t r o l the r e s i s t o r s used i n the DACs and the i n v e r t e r . The C-V measurements were used to measure the doping and the m o b i l i t y p r o f i l e s of the channel i m p l a n t a t i o n . The f a t FET was used f o r t h i s purpose. Pucel et a l . [53] have shown that by measuring the gate capacitance C , and both the transconductance g m and the channel conductance G at very low d r a i n - source voltage (about 50 mV) one can get the m o b i l i t y and the c a r r i e r c o n c e n t r a t i o n p r o f i l e s of the channel i m p l a n t a t i o n . At a distance X from the su r f a c e , the corresponding m o b i l i t y can be obtained from M(X) = (g m/C ) ( L 2 /V ) 1 (4-12) 8 8 d S [1 - (R g + R d ) G ] Z and the c a r r i e r c o n c e n t r a t i o n N(X) - (C 3/qe)(dC/dV ) - 1 (4-13) gs 83 where X - e E W L (1 - g R )/C (4-14) r 0 g g °m s g and C i s the gate capacitance/unit area. The m o b i l i t y and c a r r i e r concentration p r o f i l e s are shown i n Fig.(4-5) and Fig.(4-6) r e s p e c t i v e l y . A m o b i l i t y of about 4500 cm2/Vs f o r a c a r r i e r c o n c e n t r a t i o n of about l x l O 1 7 ions/cm 3 was obtained. The a c t i v a t i o n percentage was roughly c a l c u l a t e d from the c a r r i e r c o n c e n t r a t i o n p r o f i l e . The p r o f i l e was considered to be gaussian since the S i d i f f u s i o n constant i s small [26]. Therefore, the fluence of the a c t i v a t e d atoms <K was c a l c u l a t e d from the r e l a t i o n [54]. - fijif (4-15) P where n' i s the peak c a r r i e r c oncentration and i s the projected standard d e v i a t i o n . The a c t i v a t i o n percentage ( e f f i c i e n c y ) i n t h i s case i s n = (4-16) where <t> i s the implanted dose [54]. The a c t i v a t i o n e f f i c i e n c i e s f o r samples #2 and #4 were 73 and 85% r e s p e c t i v e l y . The higher c a r r i e r c oncentration of sample#2 i s r e s p o n s i b l e f o r the lower a c t i v a t i o n percentage i t has [87]. In ge n e r a l , the a c t i v a t i o n percentages achieved are considered reasonable f or s i m i l a r dose values [87]. 4-1 Implantation Through S i ^ N u In some published work the dopant ions were implanted d i r e c t l y i n t o GaAs 84 Fig.(4-5) M o b i l i t y p r o f i l e s f o r sample#2 and samplefM. \ 85 — 1 1 1 — 1 ' ' • i • 0-10 0-14 018 0-22 0-26 X(um) Fig.(4-6) E l e c t r o n c o n c e n t r a t i o n p r o f i l e s f o r sample#2 and sample/M. TABLE(4-2) S p e c i f i c ohmic contact r e s i s t i v i t y p (ft/cm 2) Sample # i n+ p c ft/cm 2 Dose 10 1 2/cm 2 Energy keV Dose 10 1 2/cm 2 Energy keV 2 2.24 100 4.8 100 1.8x10" 3 3 1.6 100 4 100 2 x l O - 3 4 1.45 100 3.37 100 0 . 9 x K r 3 B5 1.3 75 1.9 100 1 . 9 x l 0 - 3 G6 - - 9.7 180 2.2xl0 _ 1* E7 3.25 120 4.8 180 6 x!0 - l t 87 through a l a y e r of S i 3 N l t [34]. The reason f o r implanting through a S i ^ l a y e r i s to protect the channel surface during the f a b r i c a t i o n . In t h i s study, the e f f e c t of i m p l a n t a t i o n through S i o n the device parameters was i n v e s t i g a t e d . Two samples were f a b r i c a t e d : the f i r s t (sample#l) was implanted through a 40 nm l a y e r of SigN^ while the second (sample#4) was implanted d i r e c t l y i n t o GaAs. Both samples were annealed at 830°C f o r 25 minutes with S i 3 N 4 caps 80 nm t h i c k . The i m p l a n t a t i o n dose and energy f o r the f i r s t one were 2.25*10 1 2 ions/cm 2 and 120 keV while the second i m p l a n t a t i o n dose and energy were 1.4x10 1 2 ions/cm 2 and 100 keV r e s p e c t i v e l y . The implanted dose and energy of sample//l was chosen to be high to make sure that enough dopant atoms have reached the bulk of the GaAs through the SigN^ l a y e r to get devices of about -1 V threshold v o l t a g e . The t h r e s h o l d voltage and the s a t u r a t i o n current u n i f o r m i t y were i n v e s t i g a t e d f o r both samples. The histogram of V , and I was shown i n th sat F i g . (4-7) f o r the f i r s t sample (sample//l) and F i g . (3-8) f o r the second sample (sample#4). The standard d e v i a t i o n of the threshold voltages were 336 mV and 35 mV f o r sample#l and sample//4 r e s p e c t i v e l y . For the s a t u r a t i o n c u r r e n t , the standard d e v i a t i o n s were 57 uA and 21 uA r e s p e c t i v e l y . As shown i n these f i g u r e s , both V , and I are more s c a t t e r e d i n the case of sample#l than th sat those of sample/M. The s c a t t e r i n g of these parameters ( i n case of sample#l) can be a t t r i b u t e d to the change i n the thickness of the SigN^ l a y e r across the wafer. The nonuniformity of the S i ^ ^ l a y e r has l e d to v a r i a t i o n i n the channel thickness across the wafer which has l e d i n turn to the s c a t t e r i n g of V and I values. A v a r i a t i o n of 10% i n the channel thickness leads to th sat 0 5 1 1-5 V th ( V > or hi 2 3 6 4 0-1 0-2 03 0-4 0-5 ' s a t { m A ) Fig.(4-7) V , and I histograms from sample//!. 89 20% v a r i a t i o n i n the t h r e s h o l d voltage and up to 35% i n the s a t u r a t i o n c u r r e n t . The m o b i l i t y and c a r r i e r c o n c e n t r a t i o n p r o f i l e s are shown i n Figs.(4-5) and (4-6) f o r sample#4 and i n Figs.(4-8) and (4-9) f o r sample#l r e s p e c t i v e l y . The m o b i l i t y p r o f i l e of the sample implanted through S i 3 d r o p s at the i n t e r f a c e between the channel and the s e m i - i n s u l a t i n g m a t e r i a l (SI) w h i l e i t r i s e s f o r the other sample. J e r v i s et a l . [89] have shown that the i m p l a n t a t i o n through S i 3 i n c r e a s e d the deep t r a p c o n c e n t r a t i o n . The drop of the m o b i l i t y p r o f i l e was c o r r e l a t e d to the deep t r a p , at the channel SI m a t e r i a l i n t e r f a c e [90] which confirm the r e s u l t s of [89] as w e l l as the i d e a that the i m p l a n t a t i o n through S i 3 may be r e s p o n s i b l e f o r g i v i n g low q u a l i t y d e v i c e s . Immorlica et a l . [90] have shown that devices w i t h low d r i f t m o b i l i t y i n the a c t i v e l a y e r - s u b s t r a t e i n t e r f a c e e x h i b i t s u b s t a n t i a l backdating, slow pulse response of d r a i n current to a p p l i e d gate voltage ( l a g e f f e c t ) , and premature s a t u r a t i o n of output power. Tang et a l . [91] have s t u d i e d the backgating of the samples used i n t h i s study. S i m i l a r r e s u l t s to that of [90] have been found. Implantation through S i 3 a l s o s h i f t s the c a r r i e r c o n c e n t r a t i o n peak c l o s e r to the surface which may lead to higher i d e a l i t y f a c t o r s , higher s a t u r a t i o n current and lower b a r r i e r height f o r the gate contact [2j due to the i n c r e a s e of the c a r r i e r c o n c e n t r a t i o n . I t w i l l a l s o l e a d to a higher gate capacitance due to the r e d u c t i o n i n the d e p l e t i o n r e g i o n thickness f o r the same reason. A f a t FET from sample#l with V = -1.1 V has a C value th gs at V = 0 of about 30 pf compared to 19.7 pf f o r sample#4 f a t FET t r a n s i s t o r 90 2 1000h I 1 1 1 1 0 0 8 0-12 0-16 0-2 0-24 0-28 X(um) Fig.(4-8) M o b i l i t y p r o f i l e f o r sample#l. Fig.(4-9) E l e c t r o n c o n c e n t r a t i o n p r o f i l e f o r sample//!. 92 w i t h V ^ = -1.38 which i s about 50% higher. Smaller d e p l e t i o n region thickness leads also to lower breakdown v o l t a g e . 4-2 Temperature Measurements The temperature dependence of MESFET c h a r a c t e r i s t i c s i s c l e a r l y important i n p r a c t i c e and al s o gives i n f o r m a t i o n of fundamental s i g n i f i c a n c e f o r the understanding of device o p e r a t i o n . Temperature measurements were c a r r i e d out i n our lab o r a t o r y on a f a t FET t r a n s i s t o r from sample#l. The range of measurement was from -80°C to +80°C. The implanted dose and energy used f o r sample#l are l i s t e d i n Table(3-1). The f a b r i c a t i o n process i s described i n a previous s e c t i o n of t h i s chapter. The gate length (L ) and width (W ) of the f a t FET are 120 and 180 um r e s p e c t i v e l y . 8 The square law r e l a t i o n of / I ^ s vs. V^ g was p l o t t e d over the temperature range using the HP 4145A semiconductor parameter anal y z e r . From t h i s r e l a t i o n both V , and I were determined. I t was found that V , increased th sat th w i t h temperature ( F i g . ( 4 - 1 0 ) ) , which agrees with the r e s u l t s obtained by others [55]. A 17% change i n V was observed over the range used i n the th experiment. The s a t u r a t i o n current increased a l s o w i t h temperature as shown i n F i g . ( 4 - 1 1 ) . The increase of V , and I with temperature can be th sat a t t r i b u t e d to the red u c t i o n i n the d e p l e t i o n region width at both the Schottky and SI channel junctions [55] which means an increase i n the e f f e c t i v e channel t h i c k n e s s . The values of 8 were then determined from the r e l a t i o n I = 8(V - V u - I • R ) 2 (4-17) sat gs th sat s 8 was found to decrease with temperature, F i g . ( 4 - 1 2 ) . A red u c t i o n of about 15% was observed over the temperature range. Lee et a l . [55] observed a 30% 93 Fig.(4-10) P l o t of V vs. T. 94 Fig.(4-11) P l o t of I v s . T. 2-8 k o. 2 6 2-4 ' V . 2-2 h - 8 0 - 4 0 0 4 0 8 0 T(C°) Fig.(4-12) P l o t of 8 vs. T. 96 decrease i n the value of 8 with temperature over a range from -50°C to 100°C for a 1 um gate t r a n s i s t o r . They a t t r i b u t e d the reduction i n 8 to the increase of the e f f e c t i v e channel thickness a* and the red u c t i o n of the m o b i l i t y where [9] 8 = W ey/2L a* (4-18) g g The device transconductance g and channel conductance g, were also m d measured. In the s a t u r a t i o n region at V , = 0, i t was found that g showed th °m le s s s e n s i t i v i t y to temperature, only about 2% change being observed. The t h e o r e t i c a l c a l c u l a t i o n s from the r e l a t i o n g = 28(V — V — I • R ) / [ l + 28(V - V - I «R )R ] (4-19) em gs th sat s 1 gs th sat s s agree with the experimental r e s u l t s as shown i n Fi g . ( 4 - 1 3 ) . From the above r e l a t i o n one can see that the two terms of the numerator (28 and (0 - V - I • R )) vary by nearly the same percentage i n opposite d i r e c t i o n s sat s r e s u l t i n g i n a constant value over the temperature range. With a denominator nearly equal to u n i t y , g^ i s expected to be constant over t h i s temperature range. In c o n t r a s t , g^ showed large s e n s i t i v i t y to temperature; a 20% v a r i a t i o n was observed, F i g . ( 4 - 1 4 ) . The c a l c u l a t i o n s from the simple model of g^ which i s d gs th gs tn s d were p l o t t e d , F i g . ( 4 - 1 4 ) , and found to be not i n very good agreement with the experimental r e s u l t s e s p e c i a l l y at low temperatures. A l l the measurements In the l i n e a r region such as g and the t o t a l conductance G d i d not match m e x a c t l y the simple t h e o r e t i c a l models. The Schottky contact s a t u r a t i o n current I was measured over the s 97 CALCULATED CD 0-4 0 2 -80 •AO 40 80 T(C°) Fig.(4-13) P l o t of g (at V =0 and V -3 V) v s . T. Ill u S 98 Fig.(4-14) P l o t of g, (at V =0 and V, -0 V) vs. T. 99 temperature range. I t was found to Increase w i t h temperature as shown i n F i g . ( 4 - 1 5 ) . This increase can be a t t r i b u t e d to the decrease of the d e p l e t i o n region width with temperature. I t can also be explained from the r e l a t i o n ** i J g = A • T exp(-g<)>bn/kT) (4-21) where T 2 i s the dominant temperature term. The i d e a l i t y f a c t o r n was c a l c u l a t e d from the r e l a t i o n (3-2). This c a l c u l a t i o n shows that n decreases with the increase of temperature, as shown i n F i g . ( 4 - 1 6 ) . The behaviour of n can be a t t r i b u t e d to the e f f e c t of the term 1/T i n the r e l a t i o n (4-2) where i t i s the dominant temperature term. The v a r i a t i o n of n with temperature agrees with that reported i n [2] for Au-Si c o n t a c t s . The b a r r i e r height $ , c a l c u l a t e d from r e l a t i o n (4-3), has shown an bn increase w i t h temperature of about 30% over the temperature range, F i g . ( 4 - 1 7 ) . This behaviour i s a t t r i b u t e d to the e f f e c t of the term T i n r e l a t i o n (4-3). The gate capacitance, and both the transconductance g^ and the t o t a l conductance G at V. = 0.05 V were measured to c a l c u l a t e the channel m o b i l i t y ds and the c a r r i e r c o n c e n t r a t i o n p r o f i l e . The gate capacitance at V = 0.0V gs was p l o t t e d against the temperature as shown i n F i g . ( 4 - 1 8 ) . The f i g u r e shows that C increases w i t h temperature which can be a t t r i b u t e d to the reduction g of the d e p l e t i o n region width where C = eA/W. (4-23) g a g and G i n the l i n e a r region are p l o t t e d i n Figs.(4-19) and (4-20) m r e s p e c t i v e l y . The c a l c u l a t e d values f o r were obtained from the r e l a t i o n 100 101 Fig. (4 -16) P l o t of n v s . T. 102 Fig.(4-17) P l o t of <|>. vs . T. Fig.(4-18) P l o t of C vs. T. x^x MEASURED •o C A L C U L A T E D - 8 0 -40 T(C ) 4 0 80 Fig.(4-19) P l o t of g m (at V g g=0 and Vdg=0.05 V) v s . T.  106 Fig.(4-21) Plot of electron concentration profile v s . T. 107 Fig.(4-22) P l o t of m o b i l i t y p r o f i l e v s . T. 108 g = d l j /dV = 2SV J (4-24) m ds gs ds and G from the r e l a t i o n G = V^'ds " 2 g [ ( V g s - V t h ) - V d s / 2 1 ( 4 " 2 5 M o b i l i t y and c a r r i e r concentration p r o f i l e s were c a l c u l a t e d from r e l a t i o n s (4-12), (4-13) and (4-14). The c a r r i e r c oncentration p r o f i l e s at d i f f e r e n t temperatures, shown i n F i g . ( 4 - 2 1 ) , are nearly i d e n t i c a l except at the i n t e r f a c e between the channel and the SI m a t e r i a l . The m o b i l i t y f a l l s r a d i c a l l y at the a c t i v e l a y e r SI m a t e r i a l i n t e r f a c e due to the high c o n c e n t r a t i o n of the deep trap l e v e l s In t h i s region (see s e c t i o n 4-1). However, at the temperature of the maximum emission rate from the trap c e n t r e s , the m o b i l i t y goes up at the i n t e r f a c e (or does not f a l l down very r a d i c a l l y ) due to the emission of c a r r i e r s from these centres [56]. In our case, the maximum emission r a t e has been found at 80°C [57]. Therefore, the c a r r i e r c oncentration d e n s i t y d i d not drop r a d i c a l l y at the i n t e r f a c e at 80°C. The m o b i l i t y p r o f i l e s , F i g . ( 4 - 2 2 ) , show that at the channel SI m a t e r i a l i n t e r f a c e the m o b i l i t y decreases except at 80°C due a l s o to the emission or c a r r i e r s from the trap centres at 80°C [56]. The m o b i l i t y at 100 nm was measured and p l o t t e d i n F i g . ( 4 - 2 3 ) . This Figure shows that the m o b i l i t y increases w i t h temperature to a maximum at 0°C, then decreases again. The same behaviour has been observed by others [56]. The d e p l e t i o n region width Wd, at V g g = 0 V, was c a l c u l a t e d from the r e l a t i o n (4-14). W, was observed to decrease with temperature, F i g . ( 4 - 2 4 ) , d due to the decrease of the b u i l t - i n p o t e n t i a l [55] as shown from the r e l a t i o n 109 Fig.(4-23) P l o t of the m o b i l i t y at 100 nm v s . T. 110 < 9 0 0 8 0 0 700 " ° 6 0 0 5 0 0 4 0 0 - 8 0 - 4 0 40 80 T(C°) Fig.(4-24) P l o t of W vs . T. I l l Wd - ' ( 2 e ( V b i - 2kT/q)/qN D) (4-26) The time delay f o r an i n v e r t e r can be expressed as [3] T . - 4C/33V (4-27) d L m where CT i s the load capacitance and V = V - V, . From r e l a t i o n (2-10). L K m gs th v '' r e l a t i o n (4-27) leads to T D = 2C L/3g m (4-28) Since i s ne a r l y constant w i t h i n the temperature range from -80°C to 80°C and i s expected to vary by about 9% only, F i g ( 4 - 1 8 ) , i s expected to be n e a r l y constant w i t h i n the same range. 112 CHAPTER(5) COMMON DRAIN FET LOGIC 5-1 Review of GaAs D i g i t a l Logic Approaches In the f i r s t s e c t i o n of t h i s chapter, previous GaAs l o g i c approaches are reviewed. In the second s e c t i o n , my new Common Drain FET Logic i s dis c u s s e d . During the past ten years many approaches have been developed f o r GaAs d i g i t a l c i r c u i t s . They can be c l a s s i f i e d i n t o three groups: (a) d e p l e t i o n mode FET l o g i c i n which only d e p l e t i o n type MESFETs are used, (b) enhancement mode FET l o g i c i n which enhancement type MESFETs are used as sw i t c h i n g t r a n s i s t o r s , and (c) quasi-normally-off l o g i c i n which t r a n s i s t o r s with a s l i g h t l y p o s i t i v e or s l i g h t l y negative or zero threshold voltage can be used. (a) D e p l e t i o n Mode FET Logic ( i ) The buffered FET Logic (BFL) BFL was the f i r s t GaAs l o g i c approach to be developed [ 1 ] . The l o g i c (as shown i n Fig.(5-1.a)) c o n s i s t s of two stages: the l o g i c a m p l i f i e r stage and the load d r i v e r / l e v e l s h i f t e r stage. The load d r i v e r stage i s used to s h i f t the output voltage l e v e l s of the l o g i c a m p l i f i e r to the same values of the input voltage l e v e l s i n order to be able to dr i v e the next stage. Van Tuyl et a l . [1] have used a threshold voltage of -2.5 v o l t s and low and high l o g i c l e v e l s of -2.5 and 0.5 v o l t s r e s p e c t i v e l y .  114 The main advantages of t h i s approach are: (a) operation at high speeds; (b) i n s e n s i t i v i t y to the pinch-off v o l t a g e . However, i t s u f f e r s from serious problems: (a) high power consumption; (b) low i n t e g r a t i o n density c a p a b i l i t y due to the use of a large number of elements w i t h large dimensions. The power d i s s i p a t i o n of the BFL can be reduced e i t h e r by reducing the thr e s h o l d voltage or by e l i m i n a t i n g the load d r i v e r source f o l l o w e r t r a n s i s t o r as shown i n Fig.(5-1.b) [58]. The new s t r u c t u r e i s c a l l e d the Unbuffered FET Logic (UFL). The red u c t i o n of the power d i s s i p a t i o n i n both cases w i l l be at the expense of the speed. Perea et a l . [59] have reported a Programmable Logic Array (PLA) using the BFL where they were able to achieve a maximum c l o c k i n g frequency of 2.2 GHz at 8 mW/gate. Yamamoto et a l . [60] have succeeded i n f a b r i c a t i n g an FM demodulator using t h i s l o g i c w i t h a speed of operation 20 times that of s i l i c o n devices. ( i i ) Schottky Diode FET Lo g i c (SDFL) Rockwell researchers developed the Schottky Diode FET l o g i c i n 1977 [61]. This l o g i c , as shown i n F i g . ( 5 - 2 ) , s h i f t s the l e v e l of the s i g n a l at the input by using two types of diodes. The switching diodes ( D l ) , which form the NOR s t r u c t u r e when used i n p a r a l l e l , and the s h i f t i n g diodes (D2) which are used to s h i f t the input l e v e l s . Low doses of impla n t a t i o n were used f o r the swi t c h i n g diodes to provide b e t t e r s w i t c h i n g c a p a b i l i t y while Fig.(5-2) Schematic diagram of the SDFL i n v e r t e r Fig.(5-3) Schematic diagram of the SDFL i n v e r t e r with p u l l p u l l b u f f e r . 116 higher doses were used for the s h i f t i n g diodes to make them able to carry large currents with an almost constant voltage drop. To reduce the occupied area/gate, the switching and the s h i f t i n g diodes were made very s m a l l , 1x2 ym 2 and 3x3 ym 2 r e s p e c t i v e l y . The SDFL approach has two advantages with respect to BFL: (a) i t occupies a smaller area per gate; (b) i t d i s s i p a t e s lower power However, i t s u f f e r s from these problems: (a) d i f f i c u l t i e s i n f a b r i c a t i n g the small diodes [62]; (b) poor fan-out c a p a b i l i t y because a very large current i s required to be d r i v e n i n t o the input of the next stage. The most serious problem that faces the SDFL approach i s (b) that i t r e s t r i c t s the fan-out to 1 which leads to the use of a la r g e number of gates to implement a c i r c u i t . The other a l t e r n a t i v e i s the use of a load t r a n s i s t o r w i t h large width to be able to supply the required c u r r e n t . In both cases, the l o g i c w i l l d i s s i p a t e a large amount of power and occupy a lar g e area. Eden et a l . [3] have reported 60ps and l.lmW/gate f o r a SDFL NOR gate with a swi t c h i n g t r a n s i s t o r gate length of lym, gate width of lOym and fan-in/fan-out of 2/1. More complex c i r c u i t s have been f a b r i c a t e d using the SDFL such as a high speed d i v i d e r c i r c u i t w i t h a maximum clock frequency of about 1.85GHz [63], a 320 gate l o g i c array with 184 ps time delay/gate measured by a 19 stage r i n g o s c i l l a t o r [64], and a 256 b i t RAM with access time of Ins and 267mW power consumption [65]. 117 ( i l l ) SDFL w i t h Push P u l l B u f f e r This approach was developed at Honeywell [66] to reduce the fan-out s e n s i t i v i t y of the SDFL by adding a push p u l l a m p l i f i e r at the output as shown i n F i g . ( 5 - 3 ) . Almost constant gate delay of lOOps/gate was obtained f o r fan-outs of 1 to 3 when t h i s b u f f e r was used. Using t h i s l o g i c , Vu et a l . [67] have f a b r i c a t e d a Schottky gate array with three options: unbuffered NOR gates, buffered NOR gates, and dual NOR/NAND gates. The y i e l d of t h i s chip was 70% f o r a 101 stage r i n g o s c i l l a t o r . The main problem with t h i s approach i s the high power d i s s i p a t e d and the large area occupied per gate compared to the o r i g i n a l SDFL. ( i v ) C a p a c itor Coupled Logic (CCL) Li v i n g s t o n e et a l . [68] have developed the CCL approach, F i g . ( 5 - 4 ) , where a coupling c a p a c i t o r Is used to s h i f t the s i g n a l l e v e l s at the input. The mechanism of the l e v e l s h i f t i n g using the coupling c a p a c i t o r has been described by L i v i n g s t o n e [69] as f o l l o w s . When node A i s high (=Vdd), node B i s clamped by the forward biased gate current of t r a n s i s t o r T l to about 0.5 V, and the c a p a c i t o r (or the reverse biased diode) i s charged through T2 of the previous stage to about 4.5 V when using 5 V supply. When node A moves to i t s low l o g i c l e v e l a p o r t i o n of the c a p a c i t o r voltage i s r e t a i n e d , t a k i n g node B to a negative v o l t a g e , beyond p i n c h - o f f , t u r n i n g the next stage OFF. When node A goes back to the high l e v e l , node B returns back to i t s high l e v e l value (0.5 V) causing the t r a n s i s t o r to turn ON. The coupling c a p a c i t o r can be replaced by a reverse biased Schottky diode which i s pr e f e r a b l e since i t r e q u i r e s the same f a b r i c a t i o n steps as used f o r the MESFETs. The coupling c a p a c i t o r Schottky diode s i z e should be Fig.(5-4) Schematic diagram of the CCL i n v e r t e r . 119 Fig.(5-5) Schematic diagram of the FFS i n v e r t e r . 120 l a r g e enough to be able to d r i v e the next l o g i c stage [69]. And t h i s , i n tur n , leads to the occupation of a large area/gate. The main disadvantage of t h i s l o g i c l i e s i n i t s i n a b i l i t y to operate at frequencies l e s s than 20 kHz. L i v i n g s t o n e et a l . [68] have shown that the c a p a c i t o r coupling mechanism for s h i f t i n g the l e v e l s does not work at low frequencies due to the leakage current of the coupling c a p a c i t o r and the f o l l o w i n g gate. They have shown also that the l o g i c needs to be i n i t i a l i z e d before proper operation can be proceeded. A time delay of 105 ps per gate f o r the CCL has been reported [70]. (v) Feed Forward S t a t i c Approach (FFS) The FFS approach, developed at Texas Instruments [71], i s a combination of the BFL and the CCL, as shown i n F i g . ( 5 - 5 ) . This approach has no low frequency l i m i t , d i s s i p a t e s power equal to that d i s s i p a t e d by the CCL, and has maximum switching frequency equal to that of the BFL. The FFS can operate at a speed 30% higher than that of the BFL with a 30% lower power d i s s i p a t i o n [71]. However, t h i s approach occupies large area/gate and d i s s i p a t e s high power (see Chapter(6)). A propagation delay of 59 ps and power d i s s i p a t i o n of 18.8 mW per gate f o r an FFS i n v e r t e r with t r a n s i s t o r s of lpm gate l e n g t h , 20pm gate width, and u n i t y fan-out have been reported [71]. (b) Enhancement Mode FET Logic ( i ) D i r e c t l y Coupled FET Lo g i c (DCFL) DCFL uses enhancement mode t r a n s i s t o r s as switching elements [72]. The load can be an enhancement mode t r a n s i s t o r , a d e p l e t i o n mode t r a n s i s t o r , a r e s i s t o r , a tunnel diode, or a saturated r e s i s t o r [16]. Only a d e p l e t i o n Fig.(5-6) Schematic diagram of (a) DCFL and (b) buf f e r e d DCFL. 122 mode t r a n s i s t o r load w i l l be considered i n t h i s d i s c u s s i o n ( F i g . ( 5 - 6 . a ) ) . The mechanism of operation of the DCFL i s s i m i l a r to that of the S i DCFL. I f the Input i s high (0.7 V), the switching t r a n s i s t o r T l turns ON and the output i s shorted to ground. I f node A i s low (0 V), the t r a n s i s t o r T l turns OFF and the output becomes shorted to Vdd i n s t e a d . The DCFL i s s e n s i t i v e to the fan-out, therefore the s t r u c t u r e of Fig.(5-6.b) was developed to reduce t h i s s e n s i t i v i t y . This s t r u c t u r e uses a b u f f e r c i r c u i t at the output to provide enough current to switch the next stages w i t h i n reasonable time. The advantages of t h i s l o g i c l i e i n the s i m p l i c i t y of i t s s t r u c t u r e and i t s extremely low power d i s s i p a t i o n which make i t very a t t r a c t i v e to VLSI a p p l i c a t i o n s . However, i t s u f f e r s from these problems: (a) the requirement f o r a t i g h t c o n t r o l on the pin c h - o f f voltage ( l e a d i n g to lower production y i e l d ) ; (b) high s e r i e s r e s i s t a n c e due to a t h i n or l i g h t l y doped channel; (c) low voltage swing due to the r e s t r i c t i o n on the high l e v e l voltage to 0.7 V, as discussed i n Chapter(2). This high r e s i s t a n c e i s one of the reasons f o r the low to medium speed of operation of t h i s l o g i c . Low voltage swing leads to low speed of operation and high p o s s i b i l i t y of f a l s e t r i g g e r i n g . The p i n c h - o f f voltage can be c o n t r o l l e d by using the Pt gate or the recessed gate technology while the s e r i e s r e s i s t a n c e can be reduced by using e i t h e r the s e l f - a l i g n e d gate or the Pt gate or the recessed gate technology (see Chapter(2)). Using a s e l f - a l i g n e d gate technique, K i e h l et a l . [82] have f a b r i c a t e d a DCFL r i n g o s c i l l a t o r with 16.1 ps/gate at 77K; the gate length (Lg) was lpm 123 while the gate width was 20ym. Other researchers have reported s i m i l a r delay time values using the same f a b r i c a t i o n technique [38,39,42]. (c) Quasi-normally-off Approaches ( i ) Low P i n c h - o f f FET Lo g i c (LPFL) The LPFL (Fig . ( 5 - 7 ) ) has been developed by N u z i l l a t et a l . [73], p r i m a r i l y to have an approach with low d i s s i p a t e d power and l e s s s e n s i t i t y to the p i n c h - o f f v o l t a g e . The advantages of the LPFL over the DCFL can be summarized as [73]: (a) low l o g i c l e v e l , almost equal to the ground p o t e n t i a l , i s used, and i s thus independent of the c h a r a c t e r i s t i c s of the elements, (b) no degeneration of the t r a n s f e r curve w i t h i n c r e a s i n g pinch-off v o l t a g e , (c) high l o g i c swing ( t y p i c a l l y 0.8 V ins t e a d of 0.5 V f o r the DCFL) with s l i g h t dependence on Vth, and (d) smaller s h i f t of the switching voltage (65% of Vth compared to 85% f o r DCFL). S i x a l t e r n a t i v e c o n f i g u r a t i o n s of the LPFL have been proposed, F i g . ( 5 - 7 ) . Types 2 and 4 F i g . ( 5 - 7 . c , f ) d i d not work p r o p e r l y , therefore the authors d i d not report t h e i r l o g i c l e v e l values. These two types have been als o ignored i n recent p u b l i c a t i o n s [74-75]. A complete study of the LPFL performance w i l l be presented i n Chapter(6). Comparing the LPFL with the DCFL and the SDFL [74-75], one can see th a t : Fig.(5-7) Schematic diagram of the LPFL i n v e r t e r ; types (a) 1-D, (b) 1-1, (c) 2, (d) 3-D, (e) 3-1, and ( f ) 4. CM 126 (a) LPFL i s more complex than DCFL, (b) i t d i s s i p a t e s higher power than DCFL without an equivalent gain i n the speed, and (c) i t does not achieve any s i g n i f i c a n t performance improvement over the SDFL, where the SDFL, i n a d d i t i o n to the use of d e p l e t i o n mode t r a n s i s t o r s , can operate at higher frequency f o r n e a r l y the same power d i s s i p a t i o n per gate, i n t e g r a t i o n d e n s i t y , and time delay power product. More than t h a t , LPFL may req u i r e the use of small diodes, has high s e r i e s r e s i s t a n c e , and r e q u i r e s a t i g h t p i n c h - o f f c o n t r o l (may not be as t i g h t as that required f o r the DCFL, but not as loose as that can be used f o r the d e p l e t i o n mode FET l o g i c ) . A d i v i d e r with a maximum toggle frequency of 2.8 GHz at power d i s s i p a t i o n equal to 15mW/gate and a 1 k b i t RAM with 1.1ns access time and power d i s s i p a t i o n of 850mW, have been r e a l i z e d using the LPFL [76]. ( i i ) Source Coupled FET Logic (SCFL) The source coupled FET l o g i c (SCFL) has been developed at Matsushita Corporation [77]. The basic SCFL i n v e r t e r c o n s i s t s of a d i f f e r e n t i a l a m p l i f i e r and two source f o l l o w e r b u f f e r s with diode l e v e l s h i f t e r s , as shown i n F i g . ( 5 - 8 ) . The main advantage of t h i s l o g i c , as reported by Katsu et a l . [77], i s the i n s e n s i t i v i t y to the threshold voltage v a r i a t i o n s . A v a r i a t i o n from -0.6 to 0.3 V can be t o l e r a t e d . This v a r i a t i o n i s wider than those accepted by the LPFL. Shimano et a l . [78] have shown experimentally that V .can vary from -1.0 to 0.2 V without degradation of the performance, th 127 The other major advantage of the SCFL i s the a b i l i t y to operate at very high speeds. Idda et a l . [79] have reported a time delay of 25 ps/gate for a MESFET of lum gate length and 10pm gate width. Although t h i s l o g i c has e l i m i n a t e d some of the problems, i t has introduced some others which can be summarized as: (a) the occupation of a very large area per gate, (b) the d i s s i p a t i o n of high power compared to the DCFL and the LPFL, and (c) the need f o r up to four power s u p p l i e s [79] . Comparing the DCFL, the SCFL achieves double the speed but d i s s i p a t e s twice the power, leading to the same power time delay product. While as a comparison to the BFL, one can see that both can work over nearly the same frequency range, d i s s i p a t e s i m i l a r amount of power, and are not s e n s i t i v e to V , • t h From the previous d i s c u s s i o n , i t i s n o t i c e d that the main problems ass o c i a t e d w i t h the use of d e p l e t i o n mode t r a n s i s t o r s are the occupation of a l a r g e area, the d i s s i p a t i o n of high power, and the n e c e s s i t y for. using very b i g diodes ( i n case of CCL and FFS) or very small diodes (as i n the case of SDFL and SDFL with push p u l l b u f f e r ) . On the other hand, the use of the normally and quasi-normally o f f t r a n s i s t o r s leads to l o g i c approaches which may r e q u i r e a t i g h t c o n t r o l on the threshold v o l t a g e , be s e n s i t i v e to the loading (as i n case of the DCFL), have a complex system (as i n the case of the SCFL and the LPFL), have low voltage swing (as i n the case of the DCFL and the LPFL), and use small diodes or occupy very l a r g e area. 128 Therefore, the development of a new l o g i c which can provide high y i e l d , high speed, low power d i s s i p a t i o n , and high i n t e g r a t i o n density i s req u i r e d . The Common Drain FET Logic (CDFL) approach was developed i n our laboratory i n order to attempt to meet these previous requirements. 5-2 The Common Dra i n FET Logic (CDFL) The new l o g i c , presented here, uses t r a n s i s t o r s w i t h d r a i n connected to the p o s i t i v e supply voltage, V,,; the source i s allowed to swing. Two basic dd c i r c u i t s were developed. The f i r s t i s the b u f f e r c i r c u i t and i s shown i n F i g . ( 5 - 9 . a ) . I t has two t r a n s i s t o r s ; the switching t r a n s i s t o r which i s a common d r a i n t r a n s i s t o r and the load t r a n s i s t o r w i t h the gate t i e d to the source. Because the input of the b u f f e r appears at the output without i n v e r - s i o n , an AND or an OR gate can be b u i l t using t h i s c i r c u i t , as shown i n Fi g . ( 5 - 9 . b , c ) . The buffe r c i r c u i t i s s i m i l a r to the i s o l a t i n g b u f f e r described by Hartgring et a l . [80]. The common d r a i n t r a n s i s t o r c h a r a c t e r i s t i c s can be derived from that of the common source t r a n s i s t o r (where the source voltage V i s constant [ 3 ] ) . gs For the common source t r a n s i s t o r , we may approximate the d r a i n source current by I . = 28[(V - V , )V, - V 2, 12} (5-1) ds gs th ds ds ' below s a t u r a t i o n where and, ds gs th ^ s ^ W 2 (5"3) at s a t u r a t i o n , where \y LOAD TRANSISTOR V S S " U* D V Vgd=-2.5V 1.5 2.0 V 1 0.5 1.0 V d s (SWITCHING TRANSISTOR) (d) V 2 2.5 Fig.(5-9) Schematic diagram of the CDFL (a) b u f f e r c i r c u i t , (b) AND gate and (c) OR gate; (d) I-V c h a r a c t e r i s t i c s of the b u f f e r c i r c u i t 130 V A > V ~ (5-4) ds gs th ' The I-V c h a r a c t e r i s t i c of common d r a i n t r a n s i s t o r s can be derived by s u b s t i - t u t i n g the r e l a t i o n V g s • V g . i + V d s < 5" 5' i n r e l a t i o n (5-1). The common d r a i n t r a n s i s t o r turns ON i f V g d > l V t J <5"6> and the d r a i n current w i l l be I . = 2B[(V . - V , )V. + V 2, 12] (5-7) ds gd th ds ds The t r a n s i s t o r w i l l be considered OFF i f V g d < l V t h l ( 5 " 8 ) and the corresponding d r a i n current w i l l be i n t h i s case equal to ^ s - ^ d s - ( V t h " V g d ) ] 2 ( 5 ' 9 ) The r e l a t i o n between I , and V, f o r the b u f f e r c i r c u i t i s shown i n ds ds F i g . ( 5 - 9 . d ) . The i n t e r s e c t i o n s of the load curve with the two curves, drawn from equation (5-7) and (5-9), give the 1 and 0 states of the l o g i c . Computer s i m u l a t i o n f o r the b u f f e r c i r c u i t (Appendix(A)) was done using the JFET model of the SPICE.2G program [14], The simulated t r a n s f e r c h a r a c t e r i s t i c i s shown i n Fig.(5-10.a). The s i m u l a t i o n shows t h a t , f o r i d e n t i c a l s w i t c h i n g and load t r a n s i s t o r s , the voltage gain ( G M = -dV /.dV̂ ) i s equal to 1 i n the range V ^ < V i n < V d d - V ̂ a p p r o x i m a t e l y . The s i m u l a t i o n of 8 successive stages of the b u f f e r , shown i n Fig.(5-10.b), shows that the 0 and 1 l e v e l s saturate to approximately V and V^ - V ̂  r e s p e c t i v e l y which 'in (a) 2 3 4 5 6 NUMBER OF STAGES (b) Fig.(5-10) (a) Transfer c h a r a c t e r i s t i c s of the b u f f e r and (b) output of 8 successive stages of b u f f e r c i r c u i t s ; (....)V =0 and ss (xxxx)V =-0.5 V. ss 132 agrees w i t h the r e s u l t s obtained from the t r a n s f e r c h a r a c t e r i s t i c . The 0 l e v e l w i l l saturate at 0 V i f a negative bias i s used instead of the ground p o t e n t i a l ( F i g . ( 5 - 1 0 . a ) ) . The r e s u l t shown i n the previous paragraph i s v a l i d only i f the slope i s e x a c t l y equal to 1 which may be hard to s a t i s f y p r a c t i c a l l y . I f i s not equal to 1, the l o g i c l e v e l s might be l o s t a f t e r a c e r t a i n number of stages. Therefore, an i n v e r t e r with a voltage gain greater than u n i t y was required to regenerate the o r i g i n a l values of the l o g i c l e v e l s and to b u i l d the negative l o g i c . The proposed i n v e r t e r , shown i n Fig.(5-11.a), has two stages; the input stage f o r s h i f t i n g the l o g i c l e v e l s from and 0 V to 0 V and -v" ̂ , and the output stage f o r i n v e r t i n g the s i g n a l . The advantage of t h i s i n v e r t e r are: (a) the use of only d e p l e t i o n mode t r a n s i s t o r s ; (b) the use of a r e s i s t o r f o r l e v e l s h i f t i n g i n s t e a d of diodes. The advantage of using r e s i s t o r s are: ( i ) s h i f t i n g c a p a b i l i t y can be changed without a change i n i t s s i z e because the r e s i s t a n c e value can be determined using the i m p l a n t a t i o n parameters; ( i i ) i t i s easy to f a b r i c a t e because no r e s t r i c t i o n s on the s i z e are imposed and l e s s f a b r i c a t i o n steps are required (no Schottky contacts are needed). In c o n t r a s t , the l e v e l s h i f t i n g c a p a b i l i t y of the diode v a r i e s with the v a r i a t i o n of i t s s i z e , t h e r e f o r e , smaller diodes (lx2ym 2 i n the case of the SDFL) should be used i f the s h i f t i n g c a p a b i l i t y i s required to increase without an increase i n the number of diodes. These very small diodes have very low y i e l d . On the other hand, i f high y i e l d with the same s h i f t i n g c a p a b i l i t y i s r e q u i r e d , a large number of diodes with large s i z e s must be 133 Fig.(5-11) (a) Schematic diagram of the CDFL i n v e r t e r and (b) t r a n s f e r c h a r a c t e r i s t i c s . 134 used. This leads to the reduction of the i n t e g r a t i o n c a p a b i l i t y of the l o g i c . A computer s i m u l a t i o n of the t r a n s f e r c h a r a c t e r i s t i c of the i n v e r t e r i s shown i n Fig.(5-11.b). The f i g u r e shows that the voltage gain of the i n v e r t e r i n 12.8. The s i m u l a t i o n program i s shown i n Appendix (A). The main problem of t h i s i n v e r t e r i s i t s poor f a n - i n and fan-out c a p a b i l i t i e s . S i m i l a r to the SDFL, a large current must be driven i n t o the input of the next stage. However, these problems can be e l i m i n a t e d i f the b u f f e r c i r c u i t , F i g . ( 5 - 9 . a ) , i s added to the i n v e r t e r to form the buffered i n v e r t e r of Fig.(5-12.a). The s i m u l a t i o n of the t r a n s f e r c h a r a c t e r i s t i c of the buffered i n v e r t e r i s shown i n F i g . ( 5 - 1 3 ) . The value of the voltage, gain pf t h i s i n v e r t e r i s s i m i l a r to that of the unbuffered one since the voltage gain of the b u f f e r c i r c u i t i s 1. The AND gate has a problem i n that i t cannot be used with a 1 l e v e l voltage higher than 0.8 V, otherwise, a massive current w i l l flow from the gate i f t r a n s i s t o r T 2 i s ON and T 3 i s OFF. This massive current w i l l not flow i n case of an OR c i r c u i t where the switching t r a n s i s t o r s are i d e n t i c a l to that of the b u f f e r . Therefore, i f a voltage swing l a r g e r than 0.5 V i s r e q u i r e d , the s t r u c t u r e (CDFL1) of Fig.(5-13.a) must be used. This s t r u c t u r e i s s i m i l a r to that of the SDFL. On the other hand, i f a voltage swing of 0.5 V i s needed, the s t r u c t u r e (CDFL2) of Fig.(5-13.b) can be used. The main advantage of the CDFL2 s t r u c t u r e i s that i t d i s s i p a t e s a very low amount of power, however, t h i s i s at the expense of speed. 135 Fig.(5-12) (a) Schematic diagram of the CDFL buffered i n v e r t e r , and (b) t r a n s f e r c h a r a c t e r i s t i c s . 136 Fig.(5-13) Two p o s s i b l e design methods using the CDFL approach. 137 Compared to the DSFL, the CDFL1 has the advantage of low s e n s i t i v i t y to the fan out and not using small diodes. A comparison between the CDFL and the other GaAs l o g i c scheme i s presented l a t e r i n Chapter(6). 5-3 F a b r i c a t i o n Process and Experimental R e s u l t s The f a b r i c a t i o n process used was the ion-implanted planar process described i n Chapter(3). Four l o g i c c i r c u i t s were f a b r i c a t e d ; b u f f e r c i r c u i t , an i n v e r t e r , 2 input AND gate, and 2 inputs OR gate. 2\im gate lengths were used to design these c i r c u i t s . This considerably long gate technology was used to avoid the very short channel f a b r i c a t i o n problems. Samples with d i f f e r e n t threshold voltages were f a b r i c a t e d . The t h r e s h o l d voltages v a r i e d from -2.5 V to -0.5 V. The ohmic contact region implantations (n+) were used to determine the value of the d i g i t a l to analog i n v e r t e r load r e s i s t o r . Therefore, low doses f o r n+ i m p l a n t a t i o n were used with the samples on which the i n v e r t e r was optimized. Other samples with very high n+ dose were f a b r i c a t e d f o r o p t i m i z i n g the b u f f e r , OR and AND gates. A SEM photograph of these c i r c u i t s i s shown i n F i g . ( 5 - 1 4 ) . The DC c h a r a c t e r i s t i c of the buffer and the unbuffered i n v e r t e r were measured using the HP 4145A semiconductor parameter anal y z e r . The t r a n s f e r c h a r a c t e r i s t i c of the buffer i s shown i n Fig.(5-15.a). The voltage gain G = - dV /dV. was found to be 1, which agrees with the s i m u l a t i o n r e s u l t , m o i Fig.(5-15.b) shows that the 0 l e v e l value saturates to 0 V i f a s u f f i c i e n t negative bias i s used instead of the ground p o t e n t i a l (or a low negative v o l t a g e ) assuming that the input i s 0 V. 138 Fig.(5-14) Micrograph p i c t u r e f o r (a) a b u f f e r c i r c u i t and i n v e r t e r ; (b) an AND and OR gate. 139 Fig.(5-15) Experimental and simulated t r a n s f e r c h a r a c t e r i s t i c s of the CDFL b u f f e r c i r c u i t with V =-0.5 V; (b) experimental t r a n s f e r ss c h a r a c t e r i s t i c s of the b u f f e r with Vgg=-1 V. 140 Fig.(5-15.b) (5-16) Experimental and simulated t r a n s f e r c h a r a c t e r i s t i c s of the i n v e r t e r . (v) I I 6 12 18 -10 TIME X 1 0 u ( S ) TIME x10 ( s) Fig.(5-17) Simulated high frequency response f o r (a) b u f f e r c i r c u i t and (b) CDFL i n v e r t e r 143 The i n v e r t e r t r a n s f e r c h a r a c t e r i s t i c i s shown i n F i g . ( 5 - 1 6 ) . The simu- l a t i o n parameters of Table(4-1), used f o r s i m u l a t i n g the 2um gate MESFET, were used to simulate the t r a n s f e r c h a r a c t e r i s t i c s and the high frequency response of both the b u f f e r c i r c u i t and the i n v e r t e r (see Appendix(A)). As shown i n Figs.(5-15) and (5-16), the simulated and the experimental curves are i n very good agreement. The small d e v i a t i o n between the curves of the b u f f e r c i r c u i t i s due to the d e v i a t i o n between the experimental and the simulated I-V curves of the t r a n s i s t o r at V > 0 V, as shown i n F i g . ( 4 - 2 ) . gs r The high frequency response of the b u f f e r i s shown i n Fig.(5-17.a). The time delay was 120 ps for a fan out of 1, t h e r e f o r e , i t i s expected to oper- ate at up to 8.3 GHz. The power d i s s i p a t i o n and the power-time delay product were 4 mW and 0.48 pJ per gate r e s p e c t i v e l y . For the i n v e r t e r , the high frequency response, shown i n Fig.(5-17.b), shows a time delay of 500 ps/gate or a speed of about 2 GHz. The power d i s - s i p a t i o n and the power time delay product (a b u f f e r c i r c u i t was used as a load c i r c u i t ) are 4 mW and 2.6 pJ per gate r e s p e c t i v e l y . Adding the b u f f e r to the i n v e r t e r , to form the buffered i n v e r t e r of Fig.(5-12.a), would r e s u l t i n a time delay of 620 ps, power d i s s i p a t i o n of 8 mW and power-time delay product of 4.96 pJ. Before e v a l u a t i n g the high frequency response, we have to take i n t o c o n s i d e r a t i o n two f a c t o r s : the f i r s t i s that 2 and 4 \m gate t r a n s i s t o r s (with large gate capacitance) were used; the second i s that these c i r c u i t s are not optimized. Using load t r a n s i s t o r s of shorter gate length w i l l improve the speed of the i n v e r t e r because i t reduces the values of C and gs C , while using t r a n s i s t o r s with lower |-V , | w i l l reduce the power 144 d i s s i p a t i o n and consequently the power time delay product. 145 CHAPTER(6) COMPUTER SIMULATION OF GaAs DIGITAL LOGIC PERFORMANCE Computer s i m u l a t i o n was done to compare the various GaAs l o g i c approaches i n c l u d i n g CDFL. Using the published data on devices f o r comparison was d i f f i c u l t , i f not impossible, due to the use of d i f f e r e n t t r a n s i s t o r s with d i f f e r e n t parameters for each case. The only a v a i l a b l e a l t e r n a t i v e was to simulate the performance of these l o g i c arrangements using the JFET model of the SPICE program [14]. The l o g i c approaches were c l a s s i f i e d i n t o three groups. The f i r s t was the deep d e p l e t i o n group with a thre s h o l d voltage of -2.5 V. The second group was the d e p l e t i o n mode one with a threshold voltage of -1 V. The t h i r d group was the normally and quasi-normally o f f group with threshold voltages ranging from -0.5 to 0.2 V. The f i r s t group l o g i c contained the CCL, FFL, BFL, and UFL. The second group contained the CCL, BFL, UFL, SDFL1, SDFL2, CDFL.II, and CDFL.12. SDFL1 Is the l o g i c of Fig.(5-2) [ 3 ] , while SDFL.12 i s the l o g i c of Fig.(5-3) [66]. CDFL.II and CDFL.12 are the CDFL buffered i n v e r t e r of Fig.(5-12.a) but with load t r a n s i s t o r widths of W and W /2 r e s p e c t i v e l y . W i s the gate width of g g g the switching t r a n s i s t o r . The CCL, BFL, and UFL were simulated with both the f i r s t and second group because they can be b u i l t with both threshold v o l t a g e s . The t h i r d group contained the SCFL, CDFL, LPFL (ID, I I , 3D, and 31), and CDFL.B. The LPFL (ID, 3D, I I , and 31) w i l l be l a b e l l e d as LP1D, LP3D, LP1I, and LP3I r e s p e c t i v e l y and the CDFL.B i s the b u f f e r c i r c u i t of Fi g . ( 5 - 9 . a ) . The b i a s i n g voltage values and the r e l a t i v e dimensions of the 146 other elements were taken from published data. The values of these parameters were then adjusted to give the optimum l o g i c c h a r a c t e r i s t i c s . The aim of t h i s study i s to compare the time delay, the loading e f f e c t on the t r a n s f e r c h a r a c t e r i s t i c , the power d i s s i p a t i o n , the power time delay product, and the i n t e g r a t i o n d e n s i t y c a p a b i l i t y of the simulated l o g i c . The s t r a y capacitance was not taken i n t o c o n s i d e r a t i o n because i t i s d i f f i c u l t to determine i t s value and only one or two stages are simulated. In a d d i t i o n to t h a t , the study i s a comparative one. However, the l o g i c w i t h l a r g e numbers of elements were expected to have higher s t r a y capacitance and consequently slower speeds. The i n t e g r a t i o n d ensity c a p a b i l i t i e s are determined by the area occupied by the l o g i c . This area i s measured i n u n i t s of equivalent t r a n s i s t o r areas based on the area of the switching t r a n s i s t o r . ' The s i z e of other t r a n s i s t o r s was c a l c u l a t e d from the r e l a t i v e area to the switching t r a n s i s t o r . The diodes s i z e s were a l s o c a l c u l a t e d from t h e i r areas r e l a t i v e to that of the swit c h i n g t r a n s i s t o r . R e s i s t o r s were considered to occupy h a l f the s w i t c h i n g t r a n s i s t o r area i f only one r e s i s t o r value i s used. I f more than one r e s i s t o r with \nore than one value were used, the s i z e of the r e s i s t o r w i t h the lowest r e s i s t a n c e value was considered to occupy h a l f the area of the switching t r a n s i s t o r . The s i z e of the other r e s i s t o r s were c a l c u l a t e d according to t h e i r values r e l a t i v e to the f i r s t one. The assumption that the r e s i s t o r s i z e i s h a l f that of the t r a n s i s t o r was c a l c u l a t e d from the minimum length and width that can be used without causing the s a t u r a t i o n of the e l e c t r o n v e l o c i t y and consequently the s a t u r a t i o n of the c u r r e n t , as w i l l be discussed l a t e r . 147 The s w i t c h i n g t r a n s i s t o r s , taken from [ 3 ] , were 1 um gate length, 10 um gate width, and 1 Mm spacing between the gate and both the source and the d r a i n . The o v e r a l l dimension of the t r a n s i s t o r was 5x10 \m. The minimum r e s i s t o r length i s the minimum length at which no current s a t u r a t i o n occurs. The s a t u r a t i o n occurs at 0.5 V/ym of the channel length (or the length of the source chain separation) [18]. The maximum b i a s i n g voltage was 5 V, t h e r e f o r e the minimum t r a n s i s t o r length should be 10 um. The minimum r e s i s t o r width i s the minimum dimension of the technology used (1 ym i n our c a s e ) . Taking i n t o c o n s i d e r a t i o n the areas of the ohmic contact, the r e s i s t o r dimension was considered to be about 2x10 ym approximately. The above c a l c u l a t i o n i s not very accurate because i t does not take i n t o c o n s i d e r a t i o n the spacing between the branches and the devices, r e l a t i v e o r i e n t a t i o n which may a f f e c t the o v e r a l l dimension of the l o g i c . However, i t can s t i l l give a good i n d i c a t i o n about the r e l a t i v e s i z e of each l o g i c . The area of the devices can a l s o be expressed, as a f i r s t approximation, by t h e i r widths r e l a t i v e to that of the s w i t c h i n g t r a n s i s t o r [81] since the gate length i s the same f o r a l l the t r a n s i s t o r s . The dimensions of the s w i t c h i n g t r a n s i s t o r used i n the s i m u l a t i o n for the three groups are t a b u l a t e d i n 7 a b l e ( 6 - l ) . R e l a t i v e dimensions of the elements and the b i a s i n g voltages f o r the l o g i c of the f i r s t , second, and t h i r d group are shown i n the s i m u l a t i o n programs i n Appendices ( B ) , (C), and (D). The schematic diagrams of the three .groups are shown i n Chapter(5). 6-1 The Deep D e p l e t i o n Group (Group#l) The power d i s s i p a t i o n f o r t h i s group i s g e n e r a l l y high. The d i s s i p a t e d 148 TABLE(6-1) T r a n s i s t o r s Parameters used to simulate groups #1, 2, and 3 Group # R (ft) s R d(fl) C ( f F ) gs C g d ( f F ) 8(A/V2) V t h ^ > 1 100 100 5 5 4.4xl0 - l + -2.5 2 200 200 5 5 7 xl0 - l t -1.0 3 400 400 5 5 1 x i o - 3 -0.5 400 400 5 5 1.4xl0- 3 0 149 power f o r the BFL, FFS, UFL, and the CCL are 28.1, 12.6, 9, and 7.2 mW/gate r e s p e c t i v e l y . The high power d i s s i p a t i o n of the BFL can be a t t r i b u t e d to the use of a large load d r i v e r source f o l l o w e r t r a n s i s t o r . Using a small load d r i v e r source f o l l o w e r t r a n s i s t o r can lead to lower power d i s s i p a t i o n s i n the case of the FFS (see Table(6-2)). The r a t i o between the power d i s s i p a t e d by the FFS and the BFL, i f the same t r a n s i s t o r dimensions were used, Is near that reported by Namordi et a l . [71]. E l i m i n a t i n g the load d r i v e r t r a n s i s t o r has l e d to the reduction of about 70% of the power i n case of the UFL. The CCL d i s s i p a t e s comparatively low amounts of power due to the use of only branches between and the ground and only one voltage source. The power time delay product f o r t h i s group i s shown i n Table(6-2). The BFL has the highest value (1.26 pJ) while the FFS and the UFL have nearly the same P . T A (0.63 pJ and 0.67 pJ r e s p e c t i v e l y ) . The CCL P.T i s the lowest d d (0.37 pJ) because of i t s low power d i s s i p a t i o n and low time delay. The r e l a t i v e area occupied by t h i s group are 9.6, 11.1, 6.1, and 4.1 W fo r the CCL, FFS, BFL, and the UFL, r e s p e c t i v e l y . The large area occupied by the FFS i s due to the use of a large number of elements; some of them have large dimensions. The large dimensions of the diode used with the CCL i s r e s p o n s i b l e f o r the occupation of a large area by the l o g i c . The time delays f o r u n i t y fan-out are 50, 55, 45, and 75 ps f o r the CCL, FFS, BFL, and the UFL r e s p e c t i v e l y ( F i g . ( 6 - 1 ) . The l o g i c l e v e l and the voltage gain ( F i g . ( 6 - 2 ) ) f o r these l o g i c s are not s e n s i t i v e to the l o a d i n g . The time delay s e n s i t i v i t i e s are 7.5, 17.5, 17.5, 32.5 ps for the CCL, FFS, BFL, and the UFL r e s p e c t i v e l y , F i g . ( 6 - 1 ) . Comparing the l o g i c s of t h i s group to each other one can see that the TABLE(6-2) Simulation results for GaAs d i g i t a l logic approaches Group Logic Power P'T Area Number of Logic l e v e l Time delay Voltage gain Time delay Voltage gain f (mW) (pJ) (W ) elements s e n s i t i v i t y (fanout " 1) (fanout - 1) s e n s i t i v i t y s e n s i t i v i t y 8 (high lev e l ) (PS) (PS) 1 CCL 7.2 0.36 9.6 3 OX 50 not available 12.5 not available FFS 12.6 0.7 11.1 7 OX 55 15.8 17.5 0 BFL 28.1 1.25 6.1 6 OX 45 14.9 17.5 0 UFL 9 0.675 4.1 6 OX 75 3.7 1.5 0 2 CCL 1 0.086 9.6 3 OX 88 not available 14 not available BFL 3.25 0.325 6.1 6 OX 100 14.75 10 0 UFL 1.5 0.225 4.1 6 OX 150 9 50 0 S0FL1 5 0.4 4.3 5 33X 80 7.3 95 2.02 SDFL2 6.25 0.468 12.5 8 13X 75 7.5 10 0.9 CDFL-I1 3.9 0.316 5.2 6 OX 80 8.5 7.5 0 CDFL-I2 3 0.27 4.7 6 OX 90 12.35 10 0 3 SCFL 4.7 0.235 24 11 OX 45 1.4 5 0 DCFL 0.1 0.007 2.5 2 5X 70 3 20 0.085 LP10 2.42 0.217 5 5 8X 90 4.4 15 0 LP1I 1.4 0.133 5 5 OX 95 4.1 32.5 0.23 LP3D 1 0.06 3.5 4 OX 65 1.5 30 0 LP3I 0.6 0.033 4 4 15X 55 1.4 not available not available CDFL-B 0.7 0.007 2 2 OX 10 1 5 0 Fig.(6-1) P l o t of x , vs. number of fan-outs f o r group#l. 152 20- X FFS 18- • BFL UFL 16- X X x 14- 12- 10- 8- 6- 4- 2- 0- 0 1 2 3 1 4 5 Number Of Fanouts Fig.(6-2) P l o t of G v s . number of fan-outs f o r groups1. 153 CCL cannot operate at frequencies l e s s than 20 kHz, the FF1 occupies the l a r g e s t area, the BFL consumes the l a r g e s t amount of power, and the UBFL i s the slowest and the most s e n s i t i v e to the l o a d i n g . Therefore, these l o g i c f a m i l i e s may not be able to meet a l l the requirements of UHS VLSI. 6-2 Low Power D e p l e t i o n Mode Logic (Group#2) The l o g i c of t h i s group d i s s i p a t e lower power than those of group#l due to the use of low pinch-off voltage (-1 V ) . The power d i s s i p a t i o n f o r the CCL, BFL, UFL, SDFL1, SDFL2, CDFL.II, and the CDFL.12 are 1, 3.25, 1.5, 5, 6.25, 3.95, and 3 mW/gate r e s p e c t i v e l y . The highest power was d i s s i p a t e d by the DSFL2 due to the use of more branches, 3, between the high and the low b i a s i n g voltage i n p a r a l l e l as shown i n F i g . ( 5 - 3 ) . SDFLl d i s s i p a t e s c o n s i d e r a b l y high power due to the use of large load t r a n s i s t o r (1.5 the swit c h i n g one). The BFL, CDFL.II, and CDFL.12 d i s s i p a t e moderate amounts of power compared to the other, while the CCL and the UBF d i s s i p a t e the lowest power i n t h i s group. As shown i n F i g . ( 6 - 3 ) , the time delays f o r the l o g i c s of t h i s group are higher than those of the f i r s t one. The time delay of the CCL, SDFLl, SDFL2, CDFL.II, and the CDFL.12 are 88, 80, 75, 80, and 90 ps r e s p e c t i v e l y . The time delay f o r the BFL and the UFL are 100 and 150 ps/gate r e s p e c t i v e l y which are higher than those of the r e s t . The delay time s e n s i t i v i t i e s to the loading are not so high compared to those of the f i r s t one except f o r the SDFLl and the UFL which have a s e n s i t i v i t y of 90, and 50 ps r e s p e c t i v e l y . The l e v e l s of the SDFLl were even completely l o s t f o r a fan out of 3. The reason f o r the high s e n s i t i v i t y i s 154 4 O o • X CCL BFL UFL SDFLl SDFL2 CDFL.I1 CDFL.I2 Number Of Fanouts Fig.(6-3) P l o t of i , vs. number of fan-outs f o r group#2. 155 the requirement f o r a very large current to be d r i v e n i n t o the next stage (as explained at the beginning of Chapter(4)). The P.f product i s shown i n Table(6-2). The CCL has the lowest P.T , d d w i t h 0.08 pJ while the SDFL2 has the highest of 0.468 pJ per gate. The CDFL.12 has 0.27 pJ/gate power time delay product. The l o g i c l e v e l s and the voltage gain s e n s i t i v i t y to the loading i s shown i n Table(6-2) and Fig.(6-4) r e s p e c t i v e l y . While most of the l o g i c s of t h i s group are not s e n s i t i v e to the l o a d i n g , the SDFL1 and SDFL2 are very s e n s i t i v e . They have G s e n s i t i v i t y of 2 and 0.9 r e s p e c t i v e l y . m As a c o n c l u s i o n , t h i s study has shown that the CCL has no proper D.C. c h a r a c t e r i s t i c s ; the UFL i s the slowest l o g i c ; the SDFL1 i s the most s e n s i t i v e l o g i c to the loading; the SDFL2 d i s s i p a t e s the highest power and occupies the l a r g e s t area per gate; and the BFL i s slower and occupies l a r g e r than the CDFL.II and CDFL.12. Therefore, the CDFL.I may be the other a l t e r n a t i v e which can provide high speed, low power d i s s i p a t i o n , and l e s s l o a d i n g e f f e c t at the same time. 6-3 Normally and Quasi-normally Off Mode Logic (Group//3) The l a s t group includes the normally and quasi-normally o f f l o g i c . The main problem f a c i n g t h i s group i s the low y i e l d of production due to the n e c e s s i t y f o r a t i g h t c o n t r o l of the threshold v o l t a g e . The main advantage i s that they d i s s i p a t e low power/gate (see T a b l e ( 6 - 2 ) ) . SCFL, CDFL, LP1D, LP1I, LP3D, LP3I, and CDFL.B d i s s i p a t e 4.7, 0.1, 2.42, 1.4, 1, 0.6, and 0.7 mW/gate r e s p e c t i v e l y . The DCFL d i s s i p a t e s the lowest power i n a l l GaAs l o g - i c s . The SCFL not only d i s s i p a t e s the highest amount of power compared to 20- • BFL 18- • 0 UFL SDFLl 16- o SDFL 2 • • • • CDFL.11 14- X CDFL.12 12- 10- 8- 5 -u • 6- 4- 2- 0- 1 1 1 1 I I I I I 1 0 1 2 3 4 5 Number Of Fanouts Fig.(6-4) P l o t of G vs. number of fan-outs f o r group//2. 157 the r e s t of t h i s group l o g i c , but i t occupies the l a r g e s t area per gate compared to a l l GaAs l o g i c s , as shown i n Table(6-2). The CDFL.B occupies the smallest area of a l l . The time delays f o r u n i t y fan-out f o r SCFL, DCFL, LP1D, LP1I, LP3D, LP3I, and CDFL.B are 45, 70, 90, 95, 65, 55, and 10 ps per gate r e s p e c t i v e l y w i t h time delay loading s e n s i t i v i t i e s of 5, 20, 15, 32.5, 30, not a v a i l a b l e , and 5 ps r e s p e c t i v e l y . This shows that the CDFL.B can provide the lowest time delay and loading s e n s i t i v i t y , F i g . ( 6 . 5 ) . The power time delay products, shown i n Table(6-2), shows that both DCFL and CDFL.B have the lowest P . T of about 0.07 pJ compared to 0.235 pJ f o r the SCFL. Table (6-2) d and Fig.(6-6) shows also that the DCFL, LPID, LP3D, and LP3I l o g i c l e v e l s are s e n s i t i v e to the lo a d i n g . Comparing these l o g i c f a m i l i e s to each other, one can see that the SCFL d i s s i p a t e s the l a r g e s t power and occupies the l a r g e s t area. The DCFL d i s s i p a t e s the lowest power, however i t i s s e n s i t i v e to the lo a d i n g . The LP1I and LP3D, LP3I l o g i c s are the most s e n s i t i v e to the loading and LP1D i s the slowest. On the other hand, the CDFL.B has the lowest time delay, the lowest P.T,» and occupies the smallest area per gate. 158 a E 200- 180- A • SCFL DCFL 160- • LP1D O LP1I 140- o LP30 120- 100- 80- • X LP3I CDFL.B 60- • * A A 40- 20- 0- x- — X — — —  X Number Of Fanoufs Fig.(6-5) P l o t of T , vs. number of fan-outs f o r group#3. 159 2 3 Number Of Fanouts Fig.(6-6) P l o t of G v s . number of fan-outs f o r group//3. m 160 CHAPTER(7) THREE BIT GaAs DIGITAL TO ANALOG CONVERTER (DAC) D i g i t a l to analog converters (DAC) provide an i n t e r f a c e between the d i g i t a l s i g n a l s of computer systems and the continuous s i g n a l of the analog world. The d i g i t a l input and the reference voltage combine to c o n t r o l the output which w i l l be i n t h i s case [92] V = K V c [ a . . 2 _ 1 + a - . 2 - 2 + ... + a .2~ n] + V (7-1) o f s L 1 2 n os as shown i n F i g . ( 7 - 1 ) . For most converters, the Input word i s i n e i t h e r binary or binary-coded decimal form. The converter output can be a v a i l a b l e as e i t h e r an output current or output voltage depending upon the design and the a p p l i c a t i o n requirements. In the current mode DAC, the voltage on the load t r a n s i s t o r s (current sources) remains e s s e n t i a l l y constant while the current path Is changed to e f f e c t a change i n the ouput voltage [82]. This type i s f a s t e r than the voltage mode DAC where the load t r a n s i s t o r s do not c o n t r i b u t e to the time delay of the converter since t h e i r capacitance need not be charged or discharged during the operation. When t h i s p r o j e c t s t a r t e d i n 1982, there had been no p u b l i c a t i o n of work on GaAs DACs [83]. L a t e r , two DACs were reported [84-85]. Saunier et a l . [84] have designed a DAC with a s t r u c t u r e s i m i l a r to that of the BFL as shown i n F i g . ( 7 - 2 . a ) . The a p p l i c a t i o n f o r t h i s converter was to c o n t r o l the gain of power dual gate FETs. The main disadvantage of t h i s converter i s the use 161 POWER V„ - K V F S [ J , 2"' • j , 2"* • . . . • 2 - » j * v w V0 . OUTPUT VOLTAGE K - GAIN V F S - FULL-SCALE OUTPUT VOLTAGE j , . ff-BIT INPUT WORD Vgj - OFFSET VOLTAGE V w - REFERENCE VOLTAGE I - CURRENT Fig.(7-1) Diagram of a d i g i t a l to analog converter [ 92]. 162 Fig.(7-2) Schematic diagrams of DACs developed by (a) [84] and (b) [ 8 5 ] . 163 a large number of elements e s p e c i a l l y diodes. The second converter, developed by Tektr o n i x [85], was a current mode type, t h e r e f o r e , i t i s expected to operate at higher frequencies. The disadvantages of t h i s converter l i e s i n I t s use of 3 power s u p p l i e s and the need f o r the complement s i g n a l s of the outputs as shown i n Fi g . ( 7 - 2 . b ) . In t h i s p r o j e c t , current mode DACs were designed, F i g . ( 7 - 3 ) . D e p l e t i o n mode t r a n s i s t o r s and diodes were used. The diodes allow current to flow i n t o the load r e s i s t o r but not In the opposite d i r e c t i o n . The width of the load t r a n s i s t o r s (current sources) Qj, Q 2, and Q 3 were scaled by the r a t i o 1:2:4 to provide current scaled by the same r a t i o . The swi t c h i n g t r a n s i s t o r s T j , T 2, and T 3 were also scaled by the same r a t i o i n order to provide equal r i s e and f a l l times f o r a l l branches. The operation mechanism of t h i s converter i s that when the switching t r a n s i s t o r (T^ f o r example) i s switched ON, the current of the load t r a n s i s t o r of the corresponding branch (Qj i n t h i s case) flows to ground through the switching t r a n s i s t o r . The voltage at the point A w i l l be about 0.2 V which i s not enough to switch the diode ON. On the other hand, i f t r a n s i s t o r T j i s o f f , the voltage at point A reaches causing the diode to switch ON and the current from t r a n s i s t o r Qj to flow through the load r e s i s t o r causing a voltage drop across i t . The voltage of point A can be adjusted to switch between V and a negative value i f a negative biased voltage i s used at node B. The layout of the 3-bit DAC i s shown i n F i g . ( 3 - 2 ) . As shown i n t h i s f i g u r e , the p u l l down t r a n s i s t o r s T j , T 2, and T 3 have gate lengths of 2 ym and gate widths of 20, 40, and 80 ym r e s p e c t i v e l y . The gate length of the 164 load t r a n s i s t o r s Q j , Q2» and Q 3 i s 4 ym and the gate widths are 10, 20, and 40 um r e s p e c t i v e l y . The diodes are made b i g enough to avoid any f a b r i c a t i o n problems which may r e s u l t i f very small dimensions were used. The diodes dimensions are 4*8, 4x16, and 4x22 f o r D p D 2, and D 3 r e s p e c t i v e l y . The same DAC has been redesigned with saturated r e s i s t o r s as current sources, see F i g . ( 7 - 3 ) . The same dimensions have been used f o r the diodes and the switching t r a n s i s t o r s (pulldown t r a n s i s t o r s ) T j , T 2, and T 3. The length of the saturated r e s i s t o r s ( s e p a r a t i o n between the two el e c t r o d e s ) was 4 urn and the widths were 6, 12, and 24 ym for R ,, R „ and R _ s a t l sat2 sat3 r e s p e c t i v e l y . The saturated r e s i s t o r s were used because of the p o t e n t i a l increase of the speed of the converter i t might be gained. The operation mechanism of t h i s DAC i s s i m i l a r to the DAC with t r a n s i s t o r s as current sources. Fig.(7-4) shows a micrograph p i c t u r e of both converters. 7-1 F a b r i c a t i o n process and measurement The DACs were f a b r i c a t e d on the same chip along with the CDFL gates and the monitoring devices. Therefore, the DC measurements of Chapter(2) apply to the t r a n s i s t o r s used i n the DACs. The ion-implanted planar f a b r i c a t i o n technique was used. Although a l l the f a b r i c a t e d samples contain both c o n v e r t e r s , only sample#2, sampleM, sample B5, and sample C5 have a second l e v e l m e t a l l i z a t i o n which allowed us to t e s t the converters. The doses and energies used f o r these samples are tabulated i n Table(3-1). The doses and energies of the n + i m p l a n t a t i o n were chosen to give r e s i s t a n c e from 200 to 300 ohms f o r the load r e s i s t o r of the converters. The sample was annealed at 830°C f o r 25 minutes with S i ^ as a cap. 165 Fig.(7-3) Schematic diagrams of d - b i t DAC with (a) MESFETs as cu r r e n t sources and (b) saturated r e s i s t o r s as current source. 166 167 AuGe was used for ohmic contacts where i t was a l l o y e d at 450 °C for about 5 minutes. A l was the choice f o r the gate, f i r s t , and second l e v e l of m e t a l l i z a t i o n . S i 3 N ^ was used at the beginning as a d i e l e c t r i c between the two l e v e l s of m e t a l l i z a t i o n , however i t caused the d e s t r u c t i o n of the channel. Then, sputtered S i 0 2 was t r i e d , but i t was hard to etch holes through i t using CF^ plasma (which i s not the r i g h t plasma for S i 0 2 ) . Although C 2Fg gas can be e a s i l y i n s t a l l e d , i t was not a v a i l a b l e at t h i s time. Buffered HF was not used f o r etching S i 0 2 because i t would etch the metal ( A l ) underneath. We d i d not proceed i n using S i 0 2 because of the f a c t that during s p u t t e r i n g the sample was subject to energetic atoms which may cause the same problem as S i 3 N 1 + does. Therefore, polyimide PI 2550 from DuPont was used Instead. This organic m a t e r i a l has b e t t e r p r o p e r t i e s than both S i j N ^ and S i 0 2 as a d i e l e c t r i c w i t h no sign of channel degradation when used. See Chapter(2) f o r more d e t a i l s about the f a b r i c a t i o n process. The DAC performances were tested by measuring the output from each i n d i v i d u a l branch. The measurements showed that the output voltages f o r both converters are scaled by the r a t i o 1:2:4, as shown i n Figs.(7-5) and (7-6), which i s the required r a t i o . Both converters gave nearly the same output when the saturated r e s i s t o r s dimensions were chosen to give nearly the same s a t u r a t i o n current as that of the t r a n s i s t o r s . The DAC performance was simulated using the parameters of the t r a n s i s t o r s of sample#4 (see T a b l e ( 4 - 1 ) ) . The time delay of the most s i g n i f i c a n t b i t (MSB) was found to be 100 ps when a load of 300 ohms was derived as shown i n F i g . ( 7 - 7 ) . This i n d i c a t e s that the converter can operate at a frequency of up to 10 GHz. The t o t a l D.C power d i s s i p a t i o n was 10 mW. 168 Fig.(7-5) Output voltage of the 3 branches of the DAC of Fig.(7-3.a) 169 Fig.(7-6) Output voltage of the 3 branches of the DAC of Fig.(7-3.b) 00 I ~4 TIME V(9) a. oo n> c (D 0 o i f (D CO o D CO (0 rt 3* (D a > 1 000E-01 2.0OOE-O1 3.00OE-O1 4.OO0E-O1 S.OOOE-0 OO 1.O0OE-1O 2.OOOE-10 3.O0OE-10 4.O0OE-10 5.O0OE-1O 6.0O0E-10 7.OO0E-10 B.OOOE-IO 9 OOOE-10 I.000E-09 .1. 1O0E-O8 1.200E-09 1.300E-09 1.4O0E-O9 1 .SOOE-09 1 600E-09 1.T00E-09 1.SOOE -09 1 .900E-09 .O0OE-O9 .100E-OB JOOE-09. .3O0E-O9 . 400E -OS SOOE -09 .SOOE-09 700E-09 .SOOE-09 .900E-09 .O00E-O9 t.033E-0» t.03SE-01 1 03SE-01 1.03SE-01 1.03SE-01 ».035E-Ot 1 043E-01 1 431E-01 2.2S8E-01 .170E-01 .756E-01 .149E-01 .aaiE-01 .247E-01 .263E-01 .273E-01 .279E-01 .2B3E-01 .2BSE-0t 3B6E-01 .2B7E-OI .404E-01 3.910E-01 2.B72E-01 1.B96E-OI 1.3I2E-01 1.044E-OI 1 036E-01 1.03SE-01 1.O35E-01 1.035E-01 171 7-2 E v a l u a t i o n of the saturated r e s i s t o r as a load and a current source The advantages of the saturated r e s i s t o r are s t a t e d i n Chapter(2). These advantages can be r e a l i z e d i f the saturated r e s i s t o r i s used as a load element f o r some l o g i c approaches which r e q u i r e large load current such as the SDFL. However, some problems may be faced i f i t was used as a load element for some other l o g i c approaches, such as the DCFL, or a current source device. The f i r s t problem we have faced w i t h the saturated r e s i s t o r was that very small dimensions must be used. This i s because the saturated r e s i s t o r conductance i s 2.5 times that of a t r a n s i s t o r with -1 V threshold v o l t a g e , assuming that both have the same channel l e n g t h . Therefore, the saturated r e s i s t o r width should be 1/10 that of the s w i t c h i n g t r a n s i s t o r i f the load s a t u r a t i o n current i s required to be 1/4 that of the s w i t c h i n g t r a n s i s t o r to o b t a i n an output pulse with equal f a l l and r i s e times. Using a switching t r a n s i s t o r with a width of 10 um requires a saturated r e s i s t o r width of 1 um» Therefore, an increase of 0.5 um on both sides of the device due to the p h o t o r e s i s t development leads to an increase of 100% i n the saturated r e s i s t o r width compared to only a 10% increase i n the switching t r a n s i s t o r width. This makes i t hard to s c a l e t h i s device. The i n s e n s i t i v i t y of the s a t u r a t i o n current to the channel length (space between the source and the drain) makes i t impossible to s c a l e the current by s c a l i n g the channel length to maintain reasonable dimensions. The increase of the channel length leads only to the increase of the s a t u r a t i o n voltage which i s 0.5V/um of the channel length (see C h a p t e r ( l ) ) . 172 The saturated r e s i s t o r may not give any advantage when used with the DCFL where the voltage swing i s about 0.5V and the s a t u r a t i o n voltage i s 0.5V/um, therefore i t w i l l act as an ordinary r e s i s t o r . Reducing the channel width to submicron dimensions w i l l reduce the s a t u r a t i o n voltage but the d i f f u s i o n of the dopant from the h i g h l y doped areas may cause a short c i r c u i t between the source and the d r a i n i f such very small dimensions are used. The mechanism of current s a t u r a t i o n of the saturated r e s i s t o r i s due to the e l e c t r o n v e l o c i t y s a t u r a t i o n . Therefore, the p o s s i b i l i t y of the e f f e c t of the negative conductance appearing i s high. Fig.(7-8.a) shows the I-V c h a r a c t e r i s t i c s of a gateless t r a n s i s t o r a c t i n g as a saturated r e s i s t o r where there i s an overshoot i n the c h a r a c t e r i s t i c . Fig.(7-8.b) shows the I-V c h a r a c t e r i s t i c of the same device a f t e r d e p o s i t i n g the gate. From these two Figures one can see that the e f f e c t of the negative conductance i s n e a r l y unnoticed with V = 0 V, while at V = 0.6 V, the I-V curve i s s i m i l a r to gs gs that of the saturated r e s i s t o r . This phenomenon can be a t t r i b u t e d to the f a c t that at V = 0.6V the d e p l e t i o n region width i s n e a r l y zero leading to gs a channel s i m i l a r to that of the saturated r e s i s t o r . The appearance of the negative conductance at the s a t u r a t i o n region does not make the saturated r e s i s t o r an i d e a l current source element. The lower s e n s i t i v i t y of the t r a n s i s t o r to the negative conductance can be a t t r i b u t e d to the nature of current s a t u r a t i o n which i s due to channel p i n c h - o f f or a mix between channel pinch-off and e l e c t r o n v e l o c i t y s a t u r a - t i o n . The negative c o n d u c t i v i t y e f f e c t becomes stronger i f the channel i s uniformly doped. The s o l u t i o n i s to implant at lower dose and higher energy 173 .0000 .0000 ID (•A) a . ooo .2000 /div .0000 .0000 VDS 1.000/dlv ( V) (a) 10.00 0- s - Q-2 0-0 -a ~>_ VDS 9.000 .5000/dlV ( V) ( b) Fig.(7-8) (a) I-V c h a r a c t e r i s t i c s of a t r a n s i s t o r without gate metal i n place a c t i n g as a saturated r e s i s t o r and (b) same device a f t e r p u t t i n g down the gate metal. 174 to get a nonuniform (Gaussian) d i s t r i b u t i o n . This method was used with the DAC. Ge n e r a l l y , the saturated r e s i s t o r has the disadvantages of (a) small diimensions must be used, (b) s e n s i t i v i t y to the surface damage, (c) s e n s i t i v i t y to the negative conductance, and (d) p o s s i b i l i t y of l a t e r a l d i f f u s i o n i f small channel length i s used to reduce the s a t u r a t i o n voltage value. 175 CHAPTER(8) CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK The main c o n t r i b u t i o n s from t h i s work were as f o l l o w s . (1) The f a b r i c a t i o n techniques of GaAs MESFETs by i o n i m p l a n t a t i o n i n t o SI LEC m a t e r i a l were s t u d i e d . I t was found t h a t : (a) i m p l a n t a t i o n of s i l i c o n dopant ions d i r e c t l y i n t o the GaAs s u b s t r a t e r e s u l t s In b e t t e r parameter u n i f o r m i t y and device q u a l i t y than i m p l a n t a t i o n through a S i j ^ f i l m . (b) A s e l f a l i g n e d gate technique using polyimide (SAGUPI) was developed. I t has the advantages of s i m p l i c i t y , high y i e l d and good parameter u n i f o r m i t y . (c) The temperature-dependence of t r a n s i s t o r parameters was i n v e s t i g a t e d . The r e s u l t s imply that the c i r c u i t time delay would be ne a r l y constant i n the temperature range from -80°C to 80°C. (2) Ways of implementing l o g i c f u n c t i o n s i n GaAs were s t u d i e d . A new l o g i c was proposed (CDFL) which was p r e d i c t e d to o f f e r high speed, low power d i s s i p a t i o n , low power-time delay product, and l e s s loading s e n s i t i v i t y . (3) A need e x i s t s f o r f a s t d i g i t a l to analog converters and analog to d i g i t a l c o n v e r t e r s . GaAs has the p o t e n t i a l to f i l l t h i s need. Two prototype DACs ' (one with MESFETs as current sources and the other w i t h saturated r e s i s t o r s ) were designed and f a b r i c a t e d . The two converters were tested at low frequencies and the high frequency response was simulated. The s i m u l a t i o n has shown that they w i l l be able to operate at frequencies up to 10 GHz. For future work the f o l l o w i n g i s suggested: (1) The SAGUPI technique should be a p p l i e d a l s o to f a b r i c a t e enhancement mode devices since reduction of s e r i e s r e s i s t a n c e i s even more important f o r 176 enhancement mode than f o r d e p l e t i o n mode devices. (2) Logic should be i n v e s t i g a t e d i n which the AND and OR gates are made w i t h CDFL but the i n v e r t e r s (needed to o b t a i n NAND and NOR gates) are made wi t h DCFL. The point here i s that the o v e r a l l number of devices would decrease and t h i s would increase the speed. This combined CDFL-DCFL approach could be r e a l i z e d w i t h GaAs MISFETs as w e l l as MESFETs and a l s o w i t h InP dev i c e s . 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S i at 08:18:53 on SEP 3, 1985 f o r C C i d - N A N Y Page 1 | * *M*«# A P P E N D I X ( A ) CONT. ««*«««««*««« 2 • • • • • • • CDFL BUFFER SIMULATION FOR NATCHING WITH 3 1800PS) 4 V I N - 3 0 P U L S E ( 3 . 0 V 0 . 0 0 V 400PS 200PS 200PS 600PS 5 VDD -4 0 DC 3 . 5 6 V S S - 0 1 DC 0 . 5 7 32 2 1 1 JM1 1 .0 OFF 8 J 1 4 3 2 JM1 1 .0 OFF 9 • • • • • • • • • • • • • • A * * * * * * * * * * * * * * * * 10 J 3 4 2 5 JM1 1 .0 OFF 11 J 4 5 1 1 JM1 1 .0 OFF 12 13 .MODEL JM1 N J F V T O - - 1 . 1 3 7 R S - 1 7 0 R D - 4 5 0 CGS - 0 4 0 F F C G D - 0 4 0 F F 14 • B E T A - 1 . 1 0 4 E - 3 15 .PLOT DC V ( 2 ) 16 . P L O T TRAN V ( 2 ) 17 .DC V I N 0 . 0 3 . 0 0 .1 18 .TRAN 60PS 1B00PS 19 .END L i s t i n g o f C D F L . S 2 a t 0 6 : 2 0 : 4 7 on SEP 3 , 1985 f o r C C i d - N A N Y Page 1 «««#«*# A P P E N D I X ( A ) CONT. ***««###*# 2 ***»••» CDFL INVERTER FOR EXPERIMENTAL : RESULTS MATCHING *** 3 V I N - 3 0 P U L S E O . O V 0 . 0 0 V 0 . 5 N S 0 . 5 N S 0 .5NS 1 .5NS 4 . 0 N S ) 4 VDD-4 0 DC 3 . 0 5 VSS 0 1 DC 3 . 0 6 R1 3 2 03K 7 32 2 1 1 JM2 1.0 OFF 8 J 3 4 5 5 JM3 1.0 OFF 9 J 4 5 2 0 JM1 OFF 10 J 5 4 5 6 JM1 1 .0 OFF 11 J 6 6 0 0 JM1 1 .0 OFF 12 .MODEL JM1 N J F V T O - - 1 . 1 3 7 R S - 1 7 0 R D - 4 5 0 C G S - 4 O F F CGD -40FF 13 • B E T A - 1 . 1 0 4 E - 3 14 .MODEL JM2 N J F V T O — 1 . 1 3 7 R S - 2 4 3 R D - 6 4 2 C G S - 2 8 F F CGD-2BFF 15 • B E T A - 0 . 7 7 E - 3 16 .MODEL JM3 NJF V T O — 1 . 1 3 7 R S - 3 4 0 R D - 9 0 0 C G S - 4 O F F C G D - 4 0 F F 17 • B E T A - 0 . 2 7 6 E - 3 IB .PLOT DC V ( 5 ) 19 . PLOT DC V ( 2 ) 20 .PLOT TRAN V ( 5 ) 21 .DC V I N 0 . 0 3 . 0 0 .1 22 .TRAN . I N S 4 .0NS 23 .END Appendlx(B) Computer Simulation Programs for GaAs MESFET Logic 185 L i s t i n g o f C C L . N a t 0 8 : 0 9 : 0 6 on S E P 3, 1965 f o r C C i d - N A N ? P a g e 1 f«#t«#«t*l A P P E N D I X * B ) CONT. f«#*##*«*# 2 •*** CCL FAN O U T - 3 •**• 3 .WIDTH OUT -80 4 V I N 4 0 PWL<0 1 0 . 5 N S 1 1 . ONS 5 1 .5NS 5 2NS 1 2 . 5 N S 1 5 +3.ONS 5 3 . 5 N S 5 4 .ONS 1 4 . 5 N S 1 5NS 5 5 . 5 N S 5 6NS l 6 . 5 N S 1) 6 VDD 1 0 DC 5 7 J 1 1 2 2 J M l 0.6 OFF 8 J 2 2 3 0 J M l 1 .0 OFF 9 D1 3 4 DIODE 1 .0 OFF 11 J3 1 S 5 J M l 0.6 OFF 12 J 4 5 6 0 J M l 1 .0 OFF 13 D2 6 2 DIODE 1 .0 OFF 14 • • • » * * • • • • * • * * * • * • * • * • • * • * • * * » • * • * * • * • * 15 J 5 1 7 7 J M l 0.6 OFF 16 J6 7 8 0 J M l 1 .0 OFF 17 D3 B 2 DIODE 1 .0 OFF 1 6 ••**..*.*.*•*.*•«***•••••••*••••••.*•*. 19 J 7 1 9 9 J M l 0.6 OFF 20 J 8 9 10 0 J M l 1 .0 OFF 21 D4 10 2 DIODE 1 .0 OFF 22 * * • • • * • • * * * • • • * * * • • * » » • * • • • • * * • • * • * • » • * 23 .MODEL JM1 N J F V T O - - 2 . 5 RS«100 R D - 1 0 0 C G S - 5 F F C G D - 5 F F B E T A - 4 . 4 E - 4 24 .MODEL DIODE D R S - 2 0 0 0 C J O - 1 0 0 F F V J - 0 . 7 7 E G - 0 . 7 7 1 S - 2 . 3 E - 1 4 25 .PLOT DC V ( 2 ) 26 .PLOT TRAN V ( 2 ) 27 .DC V I N 0 . 0 5 . 0 0 . 2 5 28 .THAN 50PS 6 .5NS 29 .END L i s t i n g o f B F L i . N a t 0 8 : 0 9 : 4 0 on SEP 3, 1985 f o r C C i d - N A N Y Page 1 «#*««#*« A P P E N D I X ( B ) CONT. f f t t i t t t * 2 •***« B F L FAN OUT-4 **** 3 V I N 4 0 P U L S E ( 0 . 5 V - 2 . 5 V O.SNS 0 .5NS 0 .5NS 0 . 5 N S 2 . 5 N S ) 4 VDD 2 0 D C - 5 . 5 V 5 VSS 0 1 D C - 4 . 5 V 6 J l 2 3 3 JM1 0 . 6 OFF 7 J 2 3 4 0 JM1 1 .0 OFF 6 J 3 2 3 5 JM1 1.0 OFF 9 J 4 7 1 1 JM1 1 .0 OFF 10 D l 5 6 DIODE 1 . 5 OFF 11 D2 6 7 DIODE 1 .5 OFF j2 »»**»*»»******»»»***•**•*******»**•*•** 13 J 5 2 8 8 JM1 0 . 6 OFF 14 J 6 8 7 0 JM1 1 .0 OFF 16 J 7 2 9 9 JM1 0 . 6 OFF 17 J 8 9 7 0 JM1 1 .0 OFF j g **»•*»**•»*********«**•*«•**•»******»»* 19 J 9 2 10 10 JM1 0 . 6 OFF 20 J 1 0 10 7 0 JM1 1 .0 OFF 22 J 1 1 2 11 11 JM1 0 . 6 OFF 23 J 1 2 11 7 0 JM1 1 .0 OFF 24 *•**••*•*••••***•*•••*••••••••••***•••• 25 .MODEL JM1 N J F V T O — 2 . 5 V R S - 1 0 0 R D - 1 0 0 C G S - 5 F F C G D - 5 F F B E T A - 4 . 4 E - 26 .MODEL DIODE D R S - 8 0 0 I S - 0 . 5 8 E - 1 4 C J O - 5 F F V J - 0 . 7 7 E G - 0 . 7 7 27 .PLOT DC V ( 7 ) 28 .PLOT DC V ( 3 ) 29 . P L O T TRAN V ( 7 ) 30 .DC V I N - 2 . 5 0 . 5 0 .1 31 .TRAN 50PS 2 . 5 N S 32 .END L i s t i n g o f BFL2 .N a t 08 :09:45 on SEP 3, 1985 f o r C C i d - N A N ? Page 1 #««**<H4 A P P E N D I Z ( B ) CONT. «««**#*«* 2 UFL FAN OUT- 3 •*•••* 3 V I N 4 0 PWL(0 -2.5 0.5NS -2.5 1.0NS 0.5 1.5NS 0.5 2NS -2.5 2.5NS 4 +-2.5) 5 VDD 2 0 DC-5 . 0V 6 VSS 0 1 DC»4V 7 J 1 2 3 3 JM1 1.0 OFF 6 J2 3 4 0 JK1 1.8 OFF 9 J3 7 1 1 JM1 0.5 OFF 10 D l 3 5 DIODE 0.8 OFF 11 D2 5 7 DIODE 0.8 OFF ,2 ••*••«.*.*..*•••••*«< 13 J 4 2 8 8 J M ! 1.0 OFF 14 J 5 8 7 0 JM1 1 .8 OFF , 5 • • • • • • • • • • • • • * • • • • * • « 16 J 6 2 9 9 JM1 1 .0 OFF 17 J 7 9 7 0 J M 1 1 .8 OFF IB 1 9 J 8 2 10 10 J M 1 1 .0 OFF 20 J 9 10 7 0 J M 1 1.8 OFF 2 1 a * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 22 .MODEL J M 1 N J F V T O — 2 . 5 RS«100 RD»100 CGS«5FF C G D - 5 F F B E T A - 4 . 4 E - 4 23 .MODEL DIODE D R S - 8 0 0 C J O - 0 5 F F I S - 0 . 5 B E - 1 4 V J - 0 . 7 7 E G - 0 . 7 7 24 . P L O T DC V ( 7 ) 25 .PLOT DC V ( 3 ) 26 .PLOT TRAN V ( 7 ) 27 .DC V I N - 2 . 5 0 . 5 0 . 3 26 .TRAN 50PS 2 . 5 N S 29 .END 187 L i s t i n g o f CCL a t 0 8 : 0 9 : 5 6 on SEP 3, 1985 f o r C C i d - N A N Y P a g e 1 4M* t A P P E N D I X ( B ) CONT. M i f f 2 * • • » • CCL PAN OUT-3 V t h — 1 V * •*• 3 V I N 4 0 PWL(0 1 0 .5NS 1 1 .0NS 5 1 .5NS 5 2NS 1 2 . 5NS 1 4 +3.ONS 5 3 .5NS 5 4.ONS 1 4 .BNS 1 5NS 5 5 . 5NS 5 6NS 1 6.5NS 1) 5 VDD 1 0 DC 3 6 J1 1 2 2 J M l 0.6 OFF 7 J2 2 3 0 J M l 1.0 OFF 8 D l 3 4 DIODE 1.0 OFF g •»»******«**««**«*•«*«*••«*««•**•»***»« 10 J3 1 5 5 J M l 0.6 OFF 11 J4 5 6 0 J M l 1.0 OFF 12 D2 6 2 DIODE 1.0 OFF 13 A * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 14 J5 1 7 7 J M l 0.6 OFF 15 J6 7 8 0 J M l 1.0 OFF 16 D3 8 2 DIODE 1.0 OFF 18 J7 1 9 9 J M l 0.6 OFF 19 J 8 9 10 0 J M l 1.0 OFF 20 D4 10 2 DIODE 1.0 OFF 2\ *»********««**»*••»*****»***»**»*»##*** 22 .MODEL J M l N J F V T O - -1.0 RS-200 RD-200 CGS-5FF CGD-5FF BETA-7.0E -4 23 .MODEL DIODE D RS-2000 C J O - 1 0 0 F F VJ-0.77 BG-0.77 IS-2.3E - 14 24 . P L O T DC V(2) 25 . P L O T TRAN V(2) 26 .DC V I N 0.0 5.0 0 . 2 5 27 .TRAN 50PS 6 .5NS 28 .END L i s t i n g o f B F L i a t 0 8 : 1 0 : 0 6 on SEP 3 , 1985 f o r C C i d - N A N Y Page 1 «*««« A P P E N D I X ( B ) CONT. «*##*« 2 • * » * • • BFL FAN O U T - 3 V t h — 1 V #*«***#* 3 V I N 4 0 P U L S E ( 0 . 5 V - 1 . 0 V 0 . 5 N S 0 . 5 N S 0 . 5 N S 0 . 5 N S 2 . 5 N S ) 4 VDD 2 0 D C - 3 . 0 V 5 VSS 0 1 D C - 1 . 6 V 6 J 1 2 3 3 J M l 0 . 6 OFF 7 J 2 3 4 0 J M l 1 . 0 OFF 8 J 3 2 3 5 J M l 1 .0 OFF 9 J 4 7 1 1 J M l 1 . 0 OFF 10 D1 5 6 DIODE 1 . 5 OFF 11 D2 6 7 DlODE 1 . 5 OFF 1 2 ,•*•.••••«•**•••*•••••••••**•***•••*•** 13 J 5 2 8 8 J M l 0 . 6 OFF 14 J 6 8 7 0 J M l 1 .0 OFF 15 16 J 7 2 9 9 J M l 0 . 6 OFF 17 J 8 9 7 0 J M l 1 .0 OFF 18 19 J 9 2 10 10 J M l 0 . 6 OFF 20 J10 10 7 0 J M l 1 .0 OFF 21 27 .MODEL J M l N J F V T O — 1 . 0 V RS-200 RD-200 CGS-5FF CGD-5FF B E T A - 7 . 0 E - 4 28 .MODEL DIODE D R S - 8 0 0 I S - 0 . 5 8 E - 1 4 CJO-5FF V J - 0 . 7 7 E G - 0 . 7 7 29 . P L O T DC V ( 7 ) 30 . P L O T DC V ( 3 ) 31 . P L O T TRAN V ( 7 ) 32 .DC V I N - 1 . 0 0 . 5 0 .1 33 .TRAN 50PS 2 . 5 N S 34 .END L i s t i n g o f B F L 2 a t 0 6 : 1 0 : 1 1 on SEP 3 , 1985 f o r C C i d - N A N Y Page 1 ####!!# A P P E N D I X ( B ) CONT. I««««*M## 2 • *•*•*•• OFL FAN O U T - 3 Vth«-1 V **••***• 3 V I N 4 0 PWL(0 - 1 . 0 0 . 5 N S - 1 . 0 1 .0NS 0 . 5 1 .5NS 0 . 5 2NS - 1 . 0 2 . 5 N S 4 1 .0 ) 5 VDD 2 0 D C - 2 . 8 V 6 VSS 0 1 D C - 1 . 2 V 7 J 1 2 3 3 J M l 1 .0 OFF 8 J 2 3 4 0 J M l 1.8 OFF 9 J 3 7 1 1 J M l 0 . 5 OFF 10 D1 3 5 DIODE 0 . 8 OFF 11 D2 5 7 DIODE 0 . 8 OFF 13 J 4 2 8 8 JM1 1 .0 OFF 14 J 5 8 7 0 JM1 1 .8 OFF 16 J 6 2 9 9 JM1 1 .0 OFF 17 J 7 9 7 0 J M l 1 .8 OFF 19 J 8 2 10 10 JM1 1 .0 OFF 20 J 9 10 7 0 J M l 1 .8 OFF 2 1 ••*•••••••••••••••*•••••••••••*•••••••*• 22 .MODEL JM1 N J F V T O — 1 . 0 R S - 2 0 0 R D - 2 0 0 C G S - 5 F F C G D - 5 F F B E T A - 7 . 0 E - 4 23 .MODEL DIODE D R S - B 0 0 C J O - 0 5 F F I S - 0 . 5 B E - 1 4 V J - 0 . 7 7 E G - 0 . 7 7 24 .PLOT DC V ( 7 ) 25 .PLOT DC V ( 3 ) 26 .PLOT THAN V ( 7 ) 27 .DC V I N -1 . 0 0 . 5 0 .1 28 .TRAN 50PS 2 . 5 N S 29 .END L i s t i n g o f S D F L l a t 0 8 : 1 0 : 3 6 on SEP 3 , 19B5 f o r C C i d - N A N Y Page 1 *###*«*« A P P E N D I X ( B ) CONT. ##«##••### 2 * •**••* S D F L l FAN OUT"3 **«*»«**«»* 3 V I N - 1 0 P U L S E ( 2 . 6 V 0 . 5 V 0 . 5 N S 0 . 5 N S 1.0NS 0 . 5 N S 3 . 5 N S ) 4 V D D - 5 0 DC 2 . 6 5 VSS 0 4 DC 2 . 0 6 D1 1 2 DIODE 7 D2 2 3 DIODE 4 . 5 B J l 3 4 4 J M l 0 . 7 0 OFF 9 J 2 6 3 0 J M l OFF 10 J 3 5 6 6 JM1 1 . 5 0 OFF 11 ****»*»•**« 12 D3 6 7 DIODE 13 D4 7 8 DIODE 4 . 5 14 J 4 6 4 4 J M l 0 . 7 OFF 15 16 D5 6 9 DIODE 17 D6 9 10 DIODE 4 . 5 18 J 5 10 4 4 J M l 0 . 7 OFF , g * • *» . * * • • • * • • • • * • • • • *« 20 D7 6 11 DIODE 21 D8 11 12 DIODE 22 J 6 12 4 4 J M l 0 . 7 OFF 23 24 .MODEL JM1 N J F V T O — 1 . 0 R D - 2 0 0 R S - 2 0 0 C G S - 0 0 5 F F C G D - 0 0 5 F F B E T A - 7 E - 4 25 .MODEL DIODE D R S - 7 3 0 C J O - 2 F F V J - 0 . 7 E G - 0 . 7 26 .PLOT DC V ( 6 ) 27 .PLOT TRAN V ( 6 ) 28 .DC V I N 0 . 0 2 . 6 0 . 2 5 29 .TRAN 50PS 3 . 5 N S 30 .END Listing of SDFL2.N at 08:10:44 on SEP 3, 1985 for CCid-NANY Page 189 1 «I4*#**# APPENDIX(B) CONT. #if««4#*« 2 ••*****• SDFL2 FAN OUT"3 *«•»»***** 3 VIN 3 0 PULSE(3V 0.5V 0.5NS 0.5NS 0.5NS 0.5NS 2.5NS) 4 VDD 2 0 DC 3.0 5 VSS 0 1 DC 2.0 6 Dl 3 4 DIODE 5 OFF 7 D2 4 5 DIODE 5 OFF 8 D3 5 6 DIODE 5 OFF 9 J1 6 1 1 J M 1 0.70 OFF 10 J2 7 6 0 J M 1 1.4 OFF 11 J3 2 7 7 J M 1 1.0 OFF 12 J4 2 7 8 JM1 1.4 OFF 13 J5 8 6 0 J M 1 0.5 OFF 15 D4 8 9 DIODE 5 OFF 16 D5 9 10 DIODE 5 OFF 17 Oi 10 11 DIODE 5 OFF 18 J6 11 1 1 J M 1 0.7 OFF 20 D7 8 12 DIODE 5.0 OFF 21 DB 12 13 DIODE 5.0 OFF 22 D9 13 14 DIODE 5.0 OFF 23 J7 14 1 1 J M 1 0.7 OFF 24 « * * * « * * » * « * » * * * * * * » « • * * * * * * * * » » * * • * « * * » » 25 D10 8 15 DIODE 5.0 OFF 26 D11 15 16 DIODE 5.0 OFF 27 D12 16 17 DIODE 5.0 OFF 28 J8 17 1 1 J M 1 0.7 OFF 29 *•*»***»*»•**»*»»»*»**•»*»***•*»******•* 30 .MODEL JM1 NJF VTO—1.0 RD-200 RS«200 CGS-005FF CGD-005FF BETA-7E-4 31 .MODEL DIODE D RS-800 CJO-5FF VJ-0.77 EG-0.77 IS".580E-14 32 .PLOT DC V(6) 33 .PLOT DC V(7) 34 .PLOT TRAN V(7) 35 .PLOT DC V(8) 36 .PLOT TRAN V(8) 37 .DC VIN 0.0 3 0.25 38 .TRAN 50PS 2.5NS 39 .END Listing of CDFL1.N at 07:29:41 on SEP 9, 1985 for CCid-NANY Page 1 «f«t«44« APPENDIZ(B) CONT. ««#4444««f 2 CDFL.II FAN OUT-3 **•*••** 3 VIN- 7 0 PULSE(2.5V 0.0V 0.2NS 0.2NS 0.2NS 0.2NS 1.0NS) 4 VDD-4 0 DC 2.5 5 VSS 0 1 DC 2.0 6 J7 4 7 3 JM2 1.0 OFF 7 J8 3 0 0 JM2 1 OFF 8 R1 3 2 3.OK 9 J2 2 1 1 JM1 0.7 OFF 10 J3 4 5 5 JM1 1.00 OFF 11 J4 5 2 0 JM1 OFF 13 J5 4 5 6 JM2 OFF 14 J6 6 0 0 JM2 OFF 16 J9 4 5 8 JM2 OFF 17 J10 8 0 0 JM2 OFF 1 B • • •***•• • • • • •*• • • • • • • • •**• •*•*• • • •***•»••• • • • • 19 J11 4 5 9 JM2 OFF 20 J12 9 0 0 JM2 OFF 21 ••**»*•*•*»**•»*********•»*•****•••••**»****• 22 .MODEL JM1 NJF VTO—1.0 RD-200 RS-200 CGS-5FF CGD-5FF BETA-7E-4 23 .MODEL JM2 NJF VTO--0.5 RS-400 RD-400 CGS-05FF CGD-5FF 24 *BETA-1.0E-3 25 .PLOT DC V(5) 26 .PLOT TRAN V(5) 27 .DC VIN 0.0 2.5 0.1 28 .TRAN 020PS 1.0NS 29 .END Listing of SCrL.M at 07:29:55 on SEP 9, 1985 for CCid-NANY Page 190 1 i i f l f l * APPENDIZ(B) CONT. «t«*f# 2 » • • * • • • s c P L FAN OUT-3 •***»**•* 3 VIN 5 0 PWLCO -1.2 1.0NS -1.2 2.ONS -2.4 3NS -2.4 4.ONS 4 • -1.2) 5 VSS 1 0 DC--5V 6 VREF 8 0 DC- -1.B 7 111 « 1 10* 8 R2 0 2 5R 9 R3 6 1 10K 10 R4 0 7 5K 11 R5 10 1 10K 12 Dl 3 4 DIODE 4.0 OFF 13 D2 9 10 DIODE 4.0 OFF 14 J1 0 2 3 JMl 1.0 OFF 15 J2 2 5 6 JMl 1.0 OFF 16 J3 7 8 6 JM1 1.0 OFF 17 J4 0 7 9 JMl 1.0 OFF 18 ••••••*•••••*•••*•**••*•••*••*••*•*••*•*•••***•••••• 19 R6 11 1 10K 20 R7 0 14 5R 21 RB 0 15 5R 22 J5 14 10 11 JM1 1.0 OFF 23 J6 15 8 11 JMl 1.0 OFF 24 25 R9 0 16 5R 26 R10 0 17 5R 27 R11 12 1 10R 28 J7 16 10 12 JM1 1.0 OFF 29 J8 17 8 12 JMl 1.0 OFF 30 31 R12 0 18 5R 32 R13 0 19 5R 33 R14 13 1 10R 34 J9 IB 10 13 JM1 1.0 OFF 35 J10 19 8 13 JMl 1.0 OFF 36 37 .MODEL JMl NJF VTO--0.1 RS-450 RD-450 CGS-5FF CGD-5FF 37.5 +BETA-1.4E-3 38 .MODEL DIODE D RS-B0 ZS-1.7E-13 CJO-225FF EG-0.77 VJ-0. 39 .PLOT DC V(4) 40 .PLOT TRAN V(4) 41 .DC VIN -2.4 -1.2 0.1 42 .TRAN 50PS 5.ONS 43 .END Listing of DCFL.N at 08:31:09 on SEP 9, 1985 for CCid-NANY Page 1 «I«*4I«« APPENDIZ(B) CONT. ####### 2 ***•*•*• DCFL FAN OUT-3 *•**»••*** 3 VIN 4 0 PULSE(0.7V -0.001 0.4NS 0.2NS 0.2NS 0.4NS 1.6NS) 4 VDD 2 0 DC-0.8 5 J1 2 3 3 JM2 1.6 OFF 6 J2 3 4 0 JM1 1.0 OFF 8 J3 2 5 5 JM2 1.6 OFF 9 J4 5 3 0 JMl 1.0 OFF 10 11 J5 2 6 6 JM2 1.6 OFF 12 J6 6 3 0 JM1 1.0 OFF 13 14 J7 2 7 7 JM2 1.6 OFF 15 J8 7 3 0 JM1 1.0 OFF 16 17 .MODEL JMl NJF VTO-0.200 RS-400 RD-400 CGS-5FF CGD-5FF BETA-1.5E-3 18 .MODEL JM2 NJF VTO--0.3 RS-400 RD-400 CGS-5FF CGD-5FF BETA-1.2E-3 19 .PLOT DC V(3) 20 .PLOT TRAN V(3) 21 .DC VIN 0 0.7 0.1 22 .TRAN 40PS 1.6NS 23 .END L i s t i n g o f LP1D a t 0 8 : 1 1 : 1 9 on SEP 3 , 1985 f o r C C i d - N A N Y Page 1 #«##### A P P E N O I Z ( B ) CONT. *«*##**« 2 ******** LP1D FAN O U T - 3 ********** 3 V I N 4 0 PWL(0 0 0 . 4 N S 0 0 . 6 N S 0 . 8 5 INS 0 . 8 5 1 .2NS 0 1 .6NS 0) 4 VDD 2 0 D C - 3 . 0 V 5 R1 2 3 10K 6 R2 6 0 3 . 3 R 7 D l 5 6 DIODE 1 .0 OFF 8 J1 3 4 0 JM1 1 .0 OFF 9 J 2 2 3 5 JM1 1 . 5 OFF J Q A * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 11 R3 2 7 10R 12 J 3 7 6 0 JM1 1 .0 OFF 1 3 ••••••*••••••••***••*•••••*••*•••• 14 R4 2 8 10K 15 J 4 8 6 0 JM1 OFF A * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 17 R5 2 9 10K 18 J5 9 6 0 JM1 OFF 20 .MODEL JM1 N J F VTO--.1 R S - 4 5 0 R D - 4 5 0 C G S - 5 F F C G D - 5 F F B E T A - 1 . 4 E - 21 .MODEL DIODE D R S - 4 0 0 C J O - 1 0 F F IS-1.16E-14 E G - 0 . 7 7 V J - 0 . 7 7 22 .PLOT DC V ( 6 ) 23 .PLOT DC V ( 3 ) 24 .PLOT TRAN V ( 6 ) 25 .DC V I N 0 0 . 8 5 0 . 0 5 26 .TRAN 40PS 1 .6NS 27 .END L i s t i n g o f L P 3 D a t 08:11 : 24 on SEP 3 , 1985 f o r C C i d - N A N Y Page 1 ####•## A P P E N D I X ( B ) CONT. *#««*## 2 »•**«* LP3D FAN O U T - 3 *********** 3 V I N 4 0 PWL(0 0 0 . 5 N S 0 0.9NS 0 . 7 5 1 .5NS 0 . 7 5 2 . 0 N S 0 2 . 5 N S 0) 4 VDD 2 0 D C - 3 . 0 V 5 R1 2 3 06K 6 R2 6 0 3.3K 7 D l 3 6 DIODE 2.0 OFF 8 J1 3 4 0 JM1 1.0 OFF 9 10 R3 2 5 06R 11 J3 5 6 0 JM1 1.0 OFF 12 13 R4 2 7 6R 14 J4 7 6 0 JM1 1 OFF 15 16 R5 2 8 6R 17 J5 8 6 0 JM1 1 OFF 18 19 .MODEL JM1 N J F V T O — 0 . 1 R S - 4 5 0 R D - 4 5 0 C G S - 5 F F C G D - 5 F F B E T A - 1 . 4 E - 20 .MODEL DIODE D R S - 4 0 0 C J O - 1 0 F F IS-1.16E -14 E G - 0 . 7 7 V J - 0 . 7 7 21 . P L O T DC V ( 6 ) 22 . P L O T DC V ( 3 ) 23 . P L O T TRAN V ( 6 ) 24 .DC V I N 0 0 . 7 5 0 . 0 5 25 .TRAN 50PS 2 . 5 N S 26 .END 193L L i s t i n g o f C D F L i a t 0 8 : 1 2 : 1 1 on S E P 3 , 1965 f o r C C i d - N A N Y P a g e 1 #«##i«t« A P P E N D I X ( B ) CONT. t« l **#«* 2 C D F L . B FAN O U T - 3 • * • * * * * • » * * 3 V I N - 3 0 P U L S E ( 2 . 5 V 0 . 0 0 V 20.0PS 100PS 100PS 200PS 8 0 0 P S ) 4 VDD-4 0 DC 2 . 5 5 V S S - 0 1 DC 0 . 5 0 6 J2 2 1 1 J M l OFF 7 J1 4 3 2 J M l OFF 8 9 J3 4 2 5 J M l OFF 10 1 i J4 5 1 1 J M l OFF 1 1 12 J 5 4 2 6 J M l OFF 13 J6 6 1 1 JM1 OFF 14 15 J7 4 2 7 J M l OFF 16 J M 7 1 1 J M l OFF 17 ****•**»**»*»»»»#****»»*»»*••** 18 .MODEL J M l N J F V T O - - 0 . 5 R D - 4 0 0 R S - 4 0 0 C G S - 0 5 F F C G D - 0 5 F F 19 + B E T A - 3 . 4 E - 3 20 .PLOT DC V ( 2 ) 21 .PLOT TRAN V ( 2 ) 22 .DC V I N 0 . 0 2 . 5 0 .1 23 .TRAN 20PS 8 0 0 P S 24 .END L i s t i n g o f F F L . N a t 0 8 : 0 9 : 2 5 on S E P 3 , 1985 f o r C C i d - N A N Y Page 1 «#*#*«** A P P E N D I Z ( B ) CONT. #««*#«««*« 2 **•* F F S FAN OUT-3 •*** 3 V I N 4 0 P U L S E ( 0 . 5 V - 2 . 5 V 0 . 5 N S 0 . 5 N S 0 . 5 N S 0 . 5 N S 2 . 5 N S ) 4 VDD 2 0 D C - 6 V 5 VSS 0 1 D C - 4 V 6 J 1 2 3 3 J M l 0 . 6 OFF 7 J 2 3 4 0 J M l 1 .0 OFF 8 J 3 2 3 5 J M l 0 . 2 5 OFF 9 J 4 7 1 1 J M l 0 . 2 5 OFF 10 D l 5 6 DIODE 0 . 3 OFF 11 D2 6 7 DIODE 0 . 3 OFF 12 D3 7 3 DIODE2 1 .0 OFF 13 14 J 5 2 8 8 J M l 0 . 6 OFF 15 J 6 8 7 0 J M l 1 .0 OFF , 6 • • •••*•••*•*•••••*•*< 17 J 7 2 9 9 J M l 0 . 6 OFF 18 J 8 9 7 0 J M l 1 .0 OFF 19 20 J9 2 10 10 J M l 0 . 6 OFF 21 J10 10 7 0 J M l 1 .0 OFF 22 • • • * • * • * • • •«• • • • • • * • • * •< 23 J 1 1 2 11 11 J M l 0 . 6 OFF 24 J 1 2 11 7 0 J M l 1 .0 OFF 25 26 . .MODEL J M l N J F V T O — 2 . 5 V R S - 1 0 0 R D - 1 0 0 C G S - 5 F F C G D - 5 F F B E T A - 4 . 4 E - 4 27 .MODEL DIODE D R S - 8 0 0 I S - 0 . 5 8 E - 1 4 CJO-5FF V J - 0 . 7 7 E G - 0 . 7 7 28 .MODEL DIODE2 D R S - 2 0 0 0 C J O - 1 0 0 F F I S - 2 . 3 E - 1 4 V J - 0 . 7 7 E G - 0 . 7 7 29 .PLOT DC V ( 7 ) 30 .PLOT TRAN V ( 7 ) 31 .DC V I N - 2 . 5 0 . 5 0 .1 32 .TRAN 50PS 2 . 5 N S 33 .END 193 L i s t i n g o f CDFL1 at 0 8 : 1 2 : 1 1 on SEP 3 , 1985 f o r C C i d - N A N Y P a g e 1 #####«#* A P P E N D I X ( B ) CONT. «««*«#«* 2 * •»*** C D F L . B FAN O U T - 3 * * ********* 3 V I N - 3 0 P U L S E ( 2 . 5 V 0 . 0 0 V 20.0PS 100PS 100PS 200PS 800PS) 4 VDD-4 0 DC 2 . 5 5 V S S - 0 1 DC 0 . 5 0 6 J 2 2 1 1 JM1 OFF 7 J 1 4 3 2 JM1 OFF 3 A * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 9 J 3 4 2 5 JM1 OFF 10 J 4 5 1 1 JM1 OFF 12 J 5 4 2 6 JM1 OFF 13 J 6 6 1 1 JM1 OFF 15 J 7 4 2 7 JM1 OFF 16 J M 7 1 1 JM1 OFF 17 ******************************* 18 .MODEL J W 1 N J F V T O — 0 . 5 R D - 4 0 0 R S - 4 0 0 C G S - 0 5 F F C G D - 0 5 F F 1 9 + B E T A - J . $ E - 3 20 .PLOT DC V ( 2 ) 21 .PLOT TRAN V ( 2 ) 22 .DC V I N 0 . 0 2 . 5 0 .1 23 .TRAN 20PS 800PS 24 .END L i s t i n g o f F F L . N a t 0 8 : 0 9 : 2 5 on SEP 3 , 1985 f o r C C L d - N A N Y Page 1 «*#*«#«* A P P E N D I X * B ) CONT. ########## 2 **•* F F S FAN OUT-3 **** 3 V I N 4 0 P U L S E ( 0 . 5 V - 2 . 5 V 0 . 5 N S 0 . 5 N S 0 . 5 N S 0 . 5 N S 2 . 5 N S ) 4 VDD 2 0 D C - 6 V 5 VSS 0 1 D C - 4 V 6 J 1 2 3 3 J M 1 0 . 6 OFF 7 J 2 3 4 0 JM1 1 .0 OFF 8 J 3 2 3 5 JM1 0 . 2 5 OFF 9 J 4 7 1 1 JM1 0 . 2 5 OFF 10 D l 5 6 DIODE 0 . 3 OFF 11 D2 6 7 DIODE 0 . 3 OFF 12 D3 7 3 DIODE2 1 .0 OFF 1 3 * * * * * * » » » * * » * * * » » * * * * * * * * * * * * * * * » * • » * * * * * 14 J 5 2 8 8 JM1 0 . 6 OFF 15 J 6 8 7 0 JM1 1 .0 OFF 17 J 7 2 9 9 JM1 0 . 6 OFF 18 J 8 9 7 0 JM1 1 .0 OFF 1 9 * * • * * » * * * * * * * * « * * * » * * * * * * * « * * * • » * * * » • * * * * 20 J 9 2 10 10 JM1 0 . 6 OFF 21 J 1 0 10 7 0 JM1 1.0 OFF 22 23 J 1 1 2 11 11 JM1 0 . 6 OFF 24 J 1 2 11 7 0 JM1 1.0 OFF 25 26 . .MODEL JM1 N J F V T O — 2 . 5 V R S - 1 0 0 R D - 1 0 0 C G S - 5 F F C G D - 5 F F B E T A - 4 . 4 E - 4 27 .MODEL DIODE D R S - 8 0 0 I S - 0 . 5 8 E - 1 4 C J O - 5 F F V J - 0 . 7 7 E G - 0 . 7 7 28 .MODEL DIODE2 D R S - 2 0 0 0 - C J O - 1 0 0 F F I S - 2 . 3 E - 1 4 V J - 0 . 7 7 E G - 0 . 7 7 29 .PLOT DC V ( 7 ) 30 .PLOT TRAN V ( 7 ) 31 .DC V I N - 2 . 5 0 . 5 0 .1 32 .TRAN 50PS 2 . 5 N S 33 .END APPENDIX(C) Recipes for GaAs Fabrication Processes 194 Appendix(C-l) GaAs PROCESSING TECHNOLOGY 1. PRECLEANING A. Degreasing a. 5 minutes in boiling trichlorethylene b. 5 minutes in boiling acetone c. 5 minutes in boiling 2-propanol B. Damaged Layer Etch a. immerse for 2 minutes in 41^ SÔ  : l ^ O j : lH^O by volume at room temperature. b. 3 to 5 minutes in boiling concentrated HC1 2. REGISTRATION MARKS A. Photo Resist Patterning a. spin photo resist at 4500 r.p.m. for 20 seconds b. soft bake at 70°C for 30 minutes c. expose photo resist (under appropriate mask) for 1.5 minutes at 10 mW/cm2 d. develop pattern in Shipley MF312 Developer for about 15 seconds e. hard bake at 125°C for 30 minutes (required only when etching S i 3 \ ) 195 Appendix(C-l) GaAs PROCESSING TECHNOLOGY - cont'd B. Registration Marks Etch a. 1 minute immersion in 10% HC1 b. 1 minute rinse in D.I. Ĥ O c 50 seconds immersion in 5Z H3P0H : 2.5% H 20 2 : 92.5% D.I. H20 d. 5 minutes rinse in D.I. Ĥ O C. Photo Resist Layer Removal a. immerse in warm acetone 3. n-IMPLANT A. Photo Resist Patterning a. repeat 2A above B. Implant a. implant using the appropriate dose and energy C. Photo Resist Removal a. immerse in warm acetone (this w i l l remove most of the photo res i s t ) ; to be certain of complete removal of the photo resist 196 Appendix(C-l) GaAs PROCESSING TECHNOLOGY - cont'd either of the following Is recommended: I. Oxygen Ashing (see Process(3-2)) II. Shipley's Microposit Remover 140 - immerse in remover 140 which is heated to about 100°C - immerse for 15 seconds in buffered H.F. 4. POST-IMPLANT ANNEAL A* S i ^ ^ Layer (see Process(3-3) B. Anneal in Mini-Brute a. anneal at 850°C for 25 minutes b. the following steps are recommended: i . place wafer at the edge of furnace for 5 minutes to warm i t up 11. push wafer Into the centre of the furnace for 25 minutes H i . after the required time interval in the furnace, pull wafer out to the edge of the furnace and leave It there for 5 minutes to cool down C. S1^NU Layer Removal a. Immerse in H.F. 197 Appendix(C-l) GaAs PROCESSING TECHNOLOGY - cont'd 5. DRAIN AND SOURCE CONTACTS A. Photo Resist Patterning a. repeat 2A but this time soak the wafer in chlorobenzene for 2 minutes after developing to obtain "overcharging" resist profile B. AuGe Deposition a. lay down 1500A thick layer of Au-Ge b. perform single l i f t - o f f in warm acetone to remove the unwanted metal c. i f b does not work, do l i f t - o f f in resist remover d. alloy in Mini Brute at 450°C for 2 minutes and check the contact. Alloy further i f ohmic contact i s not yet achieved 6. GATE METAL A. repeat 2A B. Immerse the wafer after developing into BHF for 15 seconds and then D.I. water for 15 seconds C. lay down ~ 2000A thick layer of AA D. repeat 4.B, 198 Appendix(C-2) 0 2 PLASMA ASHING FOR POLYIMIDE AND PHOTORESIST 1. Flush the system before loading 2. Load the samples 3. Purge the system with N2 for 3 minutes 4. Pump down the chamber 5. Set the parameters Oj flow = 200 pressure • 250 power - 200W T - 120°C tune m 60 load - 115 6. Wait 5 minutes for the parameters to stabilize and then apply the power 7. After finishing, turn the power off, the gas valve off, and the pressure valve off. 8. Pump the chamber down and unload the samples 199 Appendlx(C-3) Si 3N^ DEPOSITION 1. Turn ON the plasma machine and pump down. 2. Flush the system to get r i d of any gas residues. 3. Vent the chamber and raise the cover to load the samples. A. After loading, pump the chamber down again and set the temperature to 310°C 5. When the temperature reaches the set value, flush the chamber prior to the application of any gases. 6. Check the gas, temperature, pressure, power, tune and load setting for ammonia plasma which i s used to clean the GaAs surface before Si 3N 4 deposition 7. Ammonia plasma parameters should be: Ammonia " 37.6 SCCM power = 100W pressure - 500 mTorr temperature = 310°C tune « 69 load » 110 8. Before applying the plasma wait about 5 minutes for the gases and the pressure to stabilize then turn the power ON 9. After finishing, turn the power off, gas valve off, and pressure valve off 200 Appendix(C-3) Si3\ DEPOSITION - cont'd. 10. Check the settings for Si 3N H deposition. These are: Ammonia -37.6 SCCM Helium - 500 SCCM Silane - 550 SCCM pressure • 1500 mTorr power • 100W temperature • 310°C tune • 86 load - 103 11. Wait for the gases to stabilize and then apply the plasma, the rate of deposition w i l l be 170A/minute. 12. When finished, turn the power off, gases valves off, and pressure valve off. 13. Flush the system and unload the samples. 201 Appendix(C-4) Si0 2 DEPOSITION 1. After loading the sample, pump down the chamber to 1x10"* Torr. 2. Apply Ar only; the pressure should be 3.5*10~d Torr. 3. When the pressure stabilizes, apply the power (100W with reflected power of no more than 10W). 4. When finished, turn off the power and the gas and unload the sample. Appendix(C-5) S i 3 ^ ETCHING WITH CF^ PLASMA 1. Repeat steps 1-4 in process(3-2) 2. Set the parameters CF^ flow - 20 SCCM pressure • 500 mTorr power » 250W temperature - 100°C load - 79 tune - 115 3. repeat steps 6-8 in process(3-2)

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