UBC Theses and Dissertations

UBC Theses Logo

UBC Theses and Dissertations

Gallium arsenide materials and device fabrications Tan, Kim Wah 1986

Your browser doesn't seem to have a PDF viewer, please download the PDF to view this item.

Item Metadata


831-UBC_1986_A7 T36.pdf [ 4.43MB ]
JSON: 831-1.0096926.json
JSON-LD: 831-1.0096926-ld.json
RDF/XML (Pretty): 831-1.0096926-rdf.xml
RDF/JSON: 831-1.0096926-rdf.json
Turtle: 831-1.0096926-turtle.txt
N-Triples: 831-1.0096926-rdf-ntriples.txt
Original Record: 831-1.0096926-source.json
Full Text

Full Text

GALLIUM  ARSENIDE  MATERIALS  AND  DEVICE  FABRICATIONS  by KIM  WAH TAN  B. ENG. (HONS), McGILL UNIVERSITY, 1983  A  THESIS  SUBMITTED  IN PARTIAL FULFILMENT OF  THE REQUIREMENTS FOR THE DEGREE OF MASTER  OF APPLIED  SCIENCE  in THE F A C U L T Y DEPARTMENT  OF G R A D U A T E STUDIES  OF ELECTRICAL ENGINEERING  We accept this thesis as  conforming  to the required standard  THE UNIVERSITY  OF BRITISH COLUMBIA  MAY  ®  KIM  1986  W A H T A N , 1986  In p r e s e n t i n g requirements  this thesis f o r an  of  British  it  freely available  agree for  that  for  that  his  Library  shall  for reference  and  study.  I  for extensive  or  be  her  shall  copying of  g r a n t e d by  the  not  be  of  further this  this  The U n i v e r s i t y o f B r i t i s h 2075 Wesbrook P l a c e V a n c o u v e r , Canada V6T 1W5  Date  V^imv  Columbia  \°\g"b *  C^v  we e  my  thesis  a l l o w e d w i t h o u t my  £\ecVr> (,g\  thesis  It is  permission.  Department of  make  head o f  representatives. publication  the  University  the  copying or  f i n a n c i a l gain  the  that  p u r p o s e s may by  f u l f i l m e n t of  degree at  I agree  permission  department or understood  advanced  Columbia,  scholarly  in partial  c~  \  p  written  ABSTRACT The  purpose  fabrication  of  and  LEC  properties  of  GaAs  application  of  GaAs  the  work  layers  of  appears the der  that  Pauw  unetched found of  test  studies  the  effects  of  MESFETs  which  integration.  devices  on  the  measured. The as  to  containing  fabricated  Improved  unfortunately samples.  of  position  not We  of  The  MESFETs, ion  activation  and  the  may  naturally, devices of  device  give  point  were  fabricated  of  was  the  because  of  subsequently  the  forced  planned.  ii  Schottky  part  is  that  it  on  and  van  etched  and  characteristics involved  studies is  in the threshold voltage  of  problem and  behind.  use  for  their  by  in  The  were  topic  difficulty to  of  surface  diodes  the work  located  devices  the  here  characteristics.  a  way  be concentrated at  device  scatter  become  dislocations  ghost  conclusive were  on  in  materials  the  away  implantation  of  device  circuits. One  etching  GaAs.  part  and in  speed  of  MESFETs  technology  in high  using  dislocations  would,  leave  implanted  limitations  effects LEC  aspects  and other defects can sometimes  dislocations  Arrays  certain  ion  chief  on the etched sample. The second  the  study  of  semi-insulating  was  substrates.  to  fabrication  presently  structure  crosses  because  the  The  ion-implanted  impurities  important  way  are  starting  surface. A  was  properties  GaAs.  involved  the  work  material  semi-insulating  of  this  large  characteristics  etching The  in  such  results  accurately  fewer  scale  a  were etching  samples  than  Table of  Contents  ABSTRACT LIST Of  ;  "  FIGURES  v  LIST OF FIGURES  vi  LIST OF T A B L E S  vii  ACKNOWLEDGEMENTS 1.  INTRODUCTION  2.  GAAS 2.1  viii 1  GROWTH  AND  FABRICATION TECHNOLOGY  4  Introduction  2.2 Crystal  4  Growth  5  2.3 Planar Fabrication Technology 2.3.1  Ion  9  Implantation  11  2.3.2 Annealing  14  2.3.3 Ohmic Contacts  15  2.4 Present Problems 3.  '.  EFFECTS OF REMOVAL CHARACTERISTICS 3.1  OF  SURFACE  16  LAYER  ON  DEVICE 1?  Introduction  3.2 Diagnostic  1  Pattern  „_  18  3.3 Device Fabrication A n d Experimental Procedure 3.4 Schottky  Metal Evaluation  18 „  .21 21  3.5 Implant Layer Characterisation 3.5.1  Doping  Profile  3.5.2 Sheet Resistance  27 „  3°  3.5.3 Drift Mobility Profile  32  3.6 Device Performance 3.7 Backgating 4.  35  Effects  EFFECTS OF DISLOCATION O N  7  3  DEVICE CHARACTERISTICS  .„  9  .43  4.1 Introduction  -43  4.2 Literature Survey  44  4.3 Experiment  -49  4.3.1  Mask Design  .49  4.3.2 Fabrication Procedures  50  4.3.3 Measurement  62  4.4 Results  A n d Discussions  .65  4.5 Discussions 5.  CONCLUSION AND  S U G G E S T I O N S FOR FUTURE WORK  7 3  76  REFERENCES  7  8  APPENDIX  8  6  A  iv  LIST Of  FIGURES  Figure 1.1.  Page Electron GaAs  velocity  as  a  function  of  electric  field  in  and Si  2  2.1.  Schematic  of  Bridgman  growth  6  2.2.  Schematic  of  LEC G a A s  2.3.  Rockwell's  planar fabrication process  2.4.  SAINT  3.1.  Test mask  32.  Position  3.3.  Characteristics of  the forward diode current  .23  3.4.  Characteristics of  the reverse diode current  .25  3.5.  Transient  3.6.  Typical  growth  8 11  fabrication process  12  layout  19  of the samples  on the wafer  20  27  in the reverse diode current doping  profiles  of  samples  468s126A  and  468s126D  29  3.7.  Sheet  31  3.8.  Drift mobility and doping  3.9.  Current  resistance of the implant  voltage  profile  characteristics  of  34 MESFETs  T 1 , T2, T3  and T4  36  3.10.  Measurement  set-up  for the backgating  3.11.  Normalised  3.12.  Drain current versus  4.1.  Threshold voltage versus distance to obtained by Miyazawa et al  drain current versus  backgate  normalised gate  v  experiment  40  voltage  .41  _  voltage nearest .  .42 dislocation .47  LIST OF  FIGURES  Figure  Page  4.2.  MESFET  array  51  4.3.  Schematic of  4.4.  Fabricated MESFET  array  4.5.  Micro-photograph  of  registration marks  left behind  the fabrication process  4.6.  Position of  4.7.  Typical  MESFET  48  I . and d  i/l . versus d  52 63  the  etched  sample  with  the 65  sample 429s122G on wafer l-V  66  characteristics V  g  of  the  same  .67 MESFET  in  figure  4.7  68  4.9.  Plot of  V  4.10.  Histogram  4.11.  Dislocation density versus  4.12.  Threshold voltage  4.13.  Plot of M E S F E T threshold voltage versus a dislocation obtained by Winston et al  t h g  versus  V  69  t h f a  of threshold voltage  versus  70  threshold voltage  .71  distance to nearest dislocation  vi  proximity  72  to .73  LIST OF  TABLES  Table  P a  1.  Range statistics  2.  Summary  of  characteristics 3.  Summary  4.  Detailed  of  for Si  Schottky  into G a A s metallisation  14 and  implanted  „ MESFETs  9e  layer 24  characteristics  fabrication steps  38 „  vii  55  ACKNOWLEDGEMENTS I would  like to  thank  my  support, patience and guidance like  to  thank  Dr.  laboratory. Thanks  P. are  Yanega also  supervisor  Dr.  L.  during the course of for  his  extended to  Young  Tang, D.  Kato, H. Pang, D. Wong and S. Chan for their invaluable  viii  his  continual  this work. I would  encouragement W.  for  and  help  also  in  Hui, P. Townsley, discussions.  the H.  1. INTRODUCTION Increasing microwave  demand  devices; for  voice  recognition  GaAs  [1]. G a A s 1.  Its  and  to  exploited for higher  interconnect devices  GaAs  direct satellite  6  times  available  parasitic  device isolation  3. The  low  field  compared  at  with  Si  inherent  and  logic  processing,  has  stimulated  in that  and  continuous interest  in  [2];  mobility  provide  which  the  electron  (figure  1.1)  allows  (SI) a  than  GaAs  natural  drift the  than for Si. This  advantages  silicon  can  be  substrate way  for  reduces isolating  of  GaAs  velocity  high  saturation  lowers  over  Si  saturates  power  in  velocity  dissipation.  include the ability  to  at higher temperatures and better resistance to radiation.  problems  poor  substrate  compound  material  makes  than those  of  of  Early epitaxial the  technology  GaAs  devices  unpredictable impurity  [3]. Better  eliminated  the  compensates  shallow  material  [4]. The  SI  years  ago, G a A s  researchers are faced with  and device uniformity. The fact its  processing  and  synthesis  that  more  GaAs  is a  complicated  Si.  techniques. The  residual  treatment has  electron  digital  simple.  voltages  with Si  high  signal  semi-insulating  capacitances  However, as  from  in  speeds.  readily  4. Other  circuits  broadcasting  higher  making  as  speed  example, in real-time  to be reached at lower  work  high  is electronically superior to Si 5  2. The  for  were  buffer  fabricated layer  substrate.  Some  concentration control  need donor  of to  was  and  impurity  on used  availabilty  surface  purer  1  layers  isolate of  the  the  dope  conversion  GaAs  due to GaAs  Si)  wafers  formed  using  active  layer  substrate  include  during  thermal  crystal  growth  incorporation during  (like that of  to  problems  intentionally  levels  buffer  with  Cr.  The  rendering the has  made  Cr  GaAs direct  2  E ikv/ca)  Figure  1.1: Electron Velocity A s  A  Function Of  Electric Field  In G a A s  and  Si [5] implantation for the formation Although, the substrate  requirements  performed GaAs. is  purity  here  is  of the active layer feasible.  of  for  the  GaAs  direct ion-implantation  concerned  with  processing  Specifically, (1), the activation  particularly  logic  which  large  scale  important  increasingly  complex and  a  Some  problem.  for  is the key to integration  substrate  enhancement  very (LSI)  process  large scale for  GaAs  has  are very and  is  devices  which are known to f o l l o w  is  a W-shaped  improved, the  severe. The  fully used  (2),  in  commonly  as  of  direct  the substrate to  coupled  opposed  circuits  attributed  variation across  of  controllable. This  integration (VLSI) as [6].  work  materiars- problems  not  dense, the non-uniformity  non-uniformity  been  to  become can be  dislocations  the wafer  [7],  3 In  chapter  technology  will  development  of  effects effects  of  a  of  5, a  future work  be  brief  GaAs  surface  field  description  given  two  GaAs  problems  growth  and  associated  fabrication with  the  circuits will be identified. In  chapter 3, the  etch  be  studied.  Chapter  look  the  GaAs  crystals  effect  summary  and  of  integrated  dislocations  semiconductor chapter  2, a  of  will in  transistor the  will be presented.  results  (MESFET) obtained  4  will on  discrete  characteristics. and  some  into  the  metal  Finally,  suggestions  in for  2. G A A S  2.1  al.  [8]  first  in  Bridgman been  GaAs  1974.  It  wafers.  integrated was  produced  GaAs  with  LEC  include the use In  to  TECHNOLOGY  size  and  round  over  Bridgman  magnetic  crystal shape  of  of  fabrication  using  throughput  and  techniques  make  the  thin  threshold devices with  the  active voltage because  example  increasing  the  GaAs  availabilty wafers  3  has  inch  made  improvements  undoped  Cr  Tuyl  large  in  GaAs  SI have  undoped to  SI  direct  layer.  can  now  the  growth  growth  et  doped  complexity  of  impurity  LEC  Van  and the change  diameter  [10]. Lower  on  buffer  field during crystal  defects  directly  the dopant  impurity  uniform  with  by  be  routinely technology  [9] and the  content the  and  addition the  preferred  large  substrate  GaAs.  selectivity  reduces  of  reported layers  requiring no epitaxial  wafers  Ion-implantation control  (LEC)  was  epitaxial  ICs on  pullers. Current  of  reduce  GaAs  Czochralski  (IC)  using  are based  technology  Undoped  good  then,  demonstrated. They  ion-implantation  circuit  made  Since  liquid-encapsulated  for  FABRICATION  INTRODUCTION The  of  GROWTH AND  a  it  cost.  possible  diffusion layer  of  of  can  the  to  which  buffered  substrate  the  aid of  be  achieved. the  an  and  to  the  In  rapid  implant  area  GaAs of  logic  making  good  still  has  in  for  based  4  transistor  seconds.  (BFL)  This  the doping good on  enhancement  logic  higher  annealing  and  in  device  depletion transistors  high transconductance. Depletion  effect  planar  a  thermal  needed  are  mask, good  addition,  layer  of  extent  reasonably  implant  active  emergence an  provides  could prevent the control of  difficulty  field  SI  form  cure  MESFETs  voltage  to  The  uniformity. Most  threshold in  area  implantation  lower  the  profile. With  implant  ion  into  devices, Schottky  5  diode  field  effect  transistor  cause power dissipation  logic  problems  (SDFL),  require  in densely  In the next section we will  discuss  level  shifting  and  could  packed circuits [2].  the development  of  GaAs  crystal  growth.  22  CRYSTAL Until  Bridgman usually one  recently, most  growth  made  end  specific  GROWTH  of  of the  SI  GaAs  was  [11], the polycrystalline quartz. T o promote crucible  to  the  orientation, a seed of  crucible where the melt  is  made  by  GaAs  the  melt  Bridgman  is  contained  crystallisation, the melt other.  that  In  order  orientation is  to  placed  •RNDOW  O O O O O O O O O O  at  boat  is cooled  from  a schematic  FUWNACt 8  O O O O O O O O  Figure 2.1: Schematic  DISTANCE  FURNACE•  Of Bridgman  Growth  GaAs  of  the end of  FURNACE T R A V E L -  FURNACE A  In  in a  achieve  first cooled. Figure 2.1 gives  FURNACf A  process.  [11]  of  a the the  6 Bridgman  growth  Bridgman  grown  manufacturing equipment  GaAs  it  silicon  is  true  they are plagued  Si  mentioned donor  above,  level  800°C  [13].  or  As  causing  at  a  because  Cr  the  a  was  when  30  to  of  in  the  channel  the  hold the when  to  melt  to  is  created  of layer  formed  either  by  a n-type  buffer  layer  Cr-free  epitaxial SI  property art  pyrolytic undoped  LEC  SI  of  associated can now  pullers  grow  nitride  known  as is  with  cooling  required to  tend to on  or  post  just  Ga  the  site.  the  As  shallow  the  anneal surface,  reduces electron scattering  The  direct  temperatures  implant  beneath  impurity  used.  by  dope  introduced impurity, Cr,  during  increased was  a  subjected to  SI  EL2 carbon  Cr are no  longer  be attained without  undoped  (PBN)  substrates, the  which  more  channel  [14].  can  be  ion-implantation  into  GaAs.  GaAs  boron  donor  abundant  of  [12].  and  is  compensate  is  longer  buffer  problems  processing  slower  Cr  melt  present  or  epitaxial  The  effective  lower  due  from  substrates  have  stress  material  Cr  because  cost  round  the intentionally  an  deep  to  the  Consequently,  the  large  the slice to convert to n-type. In addition, Cr also  mobility  SI  a  standard  generally  donor  minutes  deficit  on  the  obtained  [4].  are used  added  achieving  of  less  slices  Cr redistribution as  Si  Si. However  higher, for a  of  shallow  surface  result,  of  such as  that  is  created by  accumulates of  which  much  wafers  with the problem donors  to  relies  Bridgman  density  shallow  with  deterrent  technology  Fused quartz boats GaAs  a  because  that  dislocation  compensate  are  technology  for  Although uniform  apparatus. Characteristically, D-shaped  SI  crucibles property  and and is  high  [15].  purity  believed  Although  to  shallow the  issue  because  Cr. The present  extremely  compensating  an  pure be  ingots Ga the  acceptors  identity  of  the  state by  and  using As.  result  of  the EL2  of  In a  most is  not  7 established, there  is  that  defect  the  antisite  annealing  is  involved  affected by The pulling  LEC  silicon  ingots  process  elements  when  pressure  of  by  resulting  of  suppressed  by  used  at  temperatures  inert  the  gas  in that  a  a  loss  or  melt, typically growth freezing  by  by  for  Cominco) LEC  the  freezing, the flatness  is  PBN  of  is  to  given  liquid-solid by  is  strongly  is  2  method  made  dissociate  B 0  to  into  caused the  the  its  by  used  original  constituent  the high  the  for  name  vapour implies,  to cap the melt. To prevent  3  or  the  Ne.  growth  The  BjO  liquid remains  on  chamber layer  }  the  is  has  GaAs  an  as  it  from the solidified but still hot crystals. The  the  also  has  an  incorporation  of  content of  LEC  growth  is  formed  2  involves  figure  seed  is  the  then  be  B  high  the seed  a  and  purity  of  can  be  Si  pressure  minimise as  it is  Melbourn  a purer charge GaAs  slowly  crystal  as  the  seed  melt which  per hour. A  kept  on  [19].  into the  22. The  must  C,  inserting  interface. T o  interface  3  effect  in situ because  10 millimeters  spinning  B 0  using  2  in  be  400°C. As  the B O j layer  liquid-solid  obtained  to  Ar  that  growth  of  studies  post-growth  concentration  encapsulant,  3  as  crucible. The  at speeds  LEC  at  Bj0  2  charge  (ESR)  during  Czochralski  have  over  B O j encapsulant  Essentially,  graphite  the  layer of  such  film  required orientation through in  EL2  of  tends  2  (as  obtained.  GaAs  increasing the H 0  GaAs  pullers  variation  Specifically,  The  level  resonance  formed  heated over 4 0 0 ° C . This  the  ingot.  site  [18], Modifications  preventing A s  HjG* content  Ga  spin  [17].  a  through  an  advantage  crystalises  a  an inert molten  bubbling  pressurised added  it is  uses  is  electron  Midgap  because  arsenic  LEC growth from  on  [16].  process  from  As  melt composition  Czochralski  As  evidence  is  pulled  by  out  of  of  progressive  forces  flat  possible.  pulled out  the  GaAs  thermal as  the  contained  schematic  grows  of  is  of  the  during This melt  8  Figure 22:  Schematic  Of  LEC G a A s  and often, the crucible is simultaneously Despite boules have  with found  pressure  LEC  all  the  uniform that  Towards  by  SI  Martin  al. [21] et  al.  in  still  boules  technique exhibit et  is  crystal  not  grown  confirmed only  at  technology,  possible. in  a seed to tail  [22]  [18]  counter rotated.  advances  properties  undoped  the wafer. Holmes observed  recent  Growth  PBN  the tail end, the distribution becomes  seed  et by  of  section  more diffuse  the of  of  al.  [20]  the  high  in resistivity.  the W - s h a p e d the  Thomas  crucibles  increase  growth  EL2 the  Across profile boule.  and uniform.  9 2.3 P L A N A R The and  FABRICATION two  junction  dominant  field  GaAs  fabricate  than  proposed  by  al. [24]  GaAs  possible.  device  in  1966  types  and  (JFET).  The  Schottky  the  JFET. The  and  layer. Bipolar of  order  to  achieve  the  the  MESFET  MESFET  is  by  far  gate  much  transistor.  the  degree  latter  of  a  digital  controlled  fabrication  and  viable  higher  analog  of  such  planar  like  the  a process  fabrication  throughput  fabrication  than  one  [28]. Direct  technology.  earlier  It  epitaxial  et  also  demonstrated  are  The  former  requires  can  be  sophisticated  heterojunction needed. of  GaAs the  at  must  ion-implantation provides  techniques  better which  gate  others,  exist.  Rockwell  ICs  1K  multiplexer, among  technology used  first  are  integration  converter and 8:1  reproducible  technology,  requirements a  to  to  Hooper  GaAs  demonstrated, for example at a recent conference [27], such as array, 12 bit  was  fabricated by on  the  easier  MESFET  transistors  [26]  but  is  GaAs  molecular beam epitaxy to grow the G a A s - A I G a A s In  are  transistors  bipolar  implantation  (FETs)  subsequently  heterojunction  ion  transistors  its  in  epitaxial  two  using  transistor  because  [23]  [25]  field effect  junction  a GaAs  The  fabricated  PN  Mead  homojunction  based  effect  the  using  TECHNOLOGY  Planar  meets is  the  the key  selectivity help  to  to and  reduce  device fabrication cost. Planar active  processes  layer and the SI  implant  is  ions  the  process  Rockwell  Conventional high  to  ion  implantation  for isolation  f o l l o w e d by  [29] are used to  MESFETs  gate  on  substrate  used activation is  etch. H or B  have  rely  source  as  and  those gate  to  the  formation  [28] except that  an isolation  create a damage  illustrated in figure such  for  2.3, the SI  produced  by  drain series  implant layer is the  for  used  if or  the  a blanket a  *MESA'  isolation. In for  Rockwell  resistances  of  isolation. process  which  limit  Planar GaAs IC fabrication steps Insulator deposition and masking lor N- implant Insulator / Photo resist  r—Slr-.ll.  Encapsulation and anneal .M ultilayer dielectric  Onmic contact metallisation AuGe/Pt contact Insulator  tatl  y  ii.c«A»—  — I  Scbottky barrier and interconnect metallisation , Schottky barrier jVPVAwgaie •interconnect x  f»)  I G»As — Second layer metallisation .(mutator  Cutaway view of a planar GaAs circuit fabrication •ftth I localised implant*. Planar GaAs I.C. _ ., . rirst-second Second-level Beconotevei interconnect via ^Interconnect (mutator Substrate •mutator  first tarn! Interconnect metal  Figure 2.3: Rockwell's  Planar Fabrication Process  11  the  speed  and  resistances, the  a  the  high  tranconductance  concentration  gate. S e l f - a l i g n e d  with  extremely  gate  low  self-aligned  implantation  illustrated  figure  [31].  in  Other  SAG  ION  to  uses  N  a  and  implantation  (ie  use  ion  distribution of the  LSS  derived  for  for  injection of  used materials to dope G a A s  To  diffusion  the  commonly  implantation  the dopant  theory  as  to  gates  The  process  'align' the  because  gate  the  gate  GaAs.  by  Hence, given  and  Sn  is  a  substrate)  are the  most  to  know  information is  and  density  -  R  and  Shiott  the given  [34]. It  according  to the  is LSS  the dose  2  £_ ] 2  <o >  (2.1)  2  p  dose, x  a  )  p  the  the  depth  standard  and the energy  into  deviation of  an  compiled by  Gibbon et al. [35] to  for  GaAs  is  given  obtain R  in table  p  1. This  the  surface, R  in  the  p  the  projected  implant, the resulting  can be calculated with the equation above  into  important  depth. This  target. The dopant  (x  implant  range,  Si, Se, S  Lindhard, Scharff  p  projected  into  n-type.  exp[  the  ions  effectively, it  o |/(2jr)  4> is  energetic  in nature and can be written as,  N(x) =  Si  metal  a function of  developed  an amorphous  is Gaussian  doping  0  profile  resistances.  [33], is deposited before annealing.  over  where  gate  to  devices  (SAINT)  dummy  refractory  adjacent  fabricate  source  technology  2  dominates  theory  to  to  parasitic  IMPLANTATION  Ion  by  gate  these  immediately  are used  layer  +  reduce  placed  Si0 /resist  use  [32] or PtAu  is  To  techniques  drain  for  processes  metal, like T i W  2.3.1  2.4  region  (SAG)  gate  [30].  and  mean range.  implant  and range  statistics  data  c . Range  statistics  data  p  particular  set  of  statistics  is  12  I .-!n>iuTiiioi | (a) I KTO-S<l  (b)  Snua I  BUST MTTtailK  (0  I  1  s  E •idj ifurrci  IIC carrtn  nn«Limti»  ILJi tWCt  SMII  T  -ttulMTIOt  Figure 2.4: SAINT Fabrication Process [31]  13 given ions  because are used It  is  has  also  [36]  in  a  have  Gaussian  the  been found  lateral  shown that function  standard  is  the  lateral  2  7  this  this  thesis,  of  the  masking  distribution  silicon  28  complex  distribution  error  material, there  function. Furukawa is  function.  et  al.  the product of  The  r  (x - R ) 1 * ] - erfc[ 2  exp[)  2  lateral  distance  diffusion  capacitance, especially the extent of  for  distribution  a is  following:  deviation and the rest  above. This  the  edge  complementary  * — (  to  used  implant.  near the  the resulting  and  the  V  that  dependence  N(x) = —  y  process  for the active channel  represented by  where  fabrication  in  the  lateral diffusion  p  the  implant of  a  ]  (2.2)  oy/2  }  edge  the variables  the  case  a  from  of  of  (  _  y  SAG  can  have  of  the  the same  increase  MESFET.  It  the is  o  mask,  meaning  gate  its as  parasitic  speculated  is also orientation dependent [37].  that  14  Table  1: Range Statistics  Energy  Projected  Lateral  Range  Standard  Standard  Deviation  Deviation  (micron)  (micron)  (micron)  60  0.0507  0.0294  0.0399  80  0.0677  0.0370  0.050B  100  0.0B50  0.0442  0.0615  120  0.1025  0.0510  0.0717  150  0.1291  0.0607  0.0666  ANNEALING Annealing  and  GaAs  Projected  UeV)  2.3.2  Data For Silicon 28 Into  to  activate  annealing, which  is necessary the is  implant.  typically  one of the following  after ion implantation to repair lattice  steps  To  keep  the  performed at  surface  intact  temperatures  during  greater  than  damage furnace 800°C  can be taken;  1. Encapsulating the surface with a dielectric. 2. A s  over-pressure.  3. Covering the sample with a slice of The  most  S i N . Sometimes 3  4  common  dielectric  a combination  of  GaAs.  encapsulants both materials  on  GaAs  are  SiO,  and  has  been used to reduce  15 stress. to  Stress  affect  capless  the  profile  annealing  vacancy In  introduced  so  that  proximity  As  occur  lamps  GaAs  are used  the  the  to  with  furnace these  conditions,  techniques  can  However,  rapid  variations  than furnace annealing  2.3.3 OHMIC  be  because  a  stress  is  used to  on  top  shown  eliminated  on  of  overpressure  been  minimise  predominantly  techniques  implants  gallium  sites.  the wafer  during  in  arsenic  to  be  annealing  to  newer  than  the  annealing  in a few  Hence,  techniques. efficiency  best  [39], lasers, arc  and dopant  annealing.  activation  figures  can  sharper  What  is  in  short  profile diffusion  the  achieved  result  lamps  seconds. The  a  of  if uniform heating  ohmic  mixture n-type  a smooth  contact  The  is  that  profile  more,  newer with  larger  under  annealing  the  DC  is  furnace.  parameter  is not achieved [40].  important  12%Ge:88%Au  GaAs.  contact  Ni  is  responsible  (0.8eV) regardless  the  for  evaporated  height  fabrication  common on  top  ohmic of  the  [41].  for  will  any  most  current  emission, Schottky  mechanism barrier  is  often  is obtained  thermionic  dominant  density.  constant  are  contact  of  mechanisms  [42]. The  doping  essentially  good  for  three  semiconductor  and  has  CONTACTS  system  tunneling  higher  eutectic  The  the  thermal  Achieving  Au-Ge  arsine  anneal  optimised  contact  is  placed  anomalous' impurity  longer  obtained  A  slice  annealing  This  activate  rapid thermal annealing  time prevent  during  process.  [38].  overpressure  will  supplies  during  loss.  so-called  normally  dopant  Si  annealing, the  minimise  annealing  the  amphoteric  presumably  or halogen  of  encapsulants  where an arsine  annealed  In  by  depend  observed  flow  in  a  metal  field emission  on  the  on  n-type  of the metal used. It  barrier  and  height  GaAs  is  is therefore not  16 possible The is  to  reduce the  normal to  strategy  dope  the  barrier height  used  GaAs  to  by  achieve  sufficiently  proper  good  high  choice  ohmic  enough  of  the  metal  alone.  to  n-type  GaAs  contacts  so  that  tunneling  becomes  dominant. During  alloying  from  the  sites  [43]. Since  region  Ge  formed  is  presents  A u - G e , Ga  eutectic A u - G e  is  barrier  of  mix  acts  near  decreased  a donor  Two  prevalent  implantation Residual  of  and  impurities  and they  surface. A s  making  the  Ga  a  the  GaAs  surface  occupying  sites, a heavily  result, the width  tunneling  problems  the wafer  more  probable.  activation. and  with  One  defects  aspect appear  can affect the activation of  manufacturers  to  should  be  Another  present  in  yields  removed. the of  deviate of  characterised.  wafer. circuits by  know  if  aspect  in the VLSI  dislocations  than on  of to  MESFET  and  Ge  vacant  Ga  doped  of  the  n-type  potential  Interfacial  top of  be  oxide  to  ingot  problems  is  the  level  because  cent  device  of  the  problems  device  are  ingot  concentrated  layer  the  affect  5 per  the  technology  implanted dopant. It  the  Dislocations  more  current  and reproducibility from  device  effects  on  from  PROBLEMS  non-uniformity  cannot  into  out  a further barrier to current flow.  2.4 PRESENT  the  diffuses  as  the  diffuses  at  is  is  MESFETs  [44]. Hence, it be  of  the  ion  surface. surface to  substrate  dislocations  and  will  threshold is  in  interest  starting  uniformity  properties  the  the  vital  limit  voltage that  understood  the and  3. EFFECTS  OF R E M O V A L  OF SURFACE  LAYER  ON  DEVICE  CHARACTERISTICS  3.1  INTRODUCTION Commercially  and  mechanically  our  presumably published paper  on  has  is  they  etch  that  surface  this  this  etch  improves  (100)  GaAs  of  drives  impurities  etching  For  alignment  and  it  also  like Cu, Mg  an  is  to  [45]  isolation  as  in  role for  *MESA'  include has  by  a  variety  of  H S 0 : H , 0 : H 0 , NaOH:H,0 J  4  J  J  been found to  be  etchants. and  2  dependent on  of  of  a  1-2jzm  activation  annealed more  before uniform [46]  so  the  fabrication surface  Etching  of  the The  2  the etch rate and  for  normally  [47]. The G a A s  NH OH:H Oj:HjO. 4  been  abstract  device  etching.  Some  etched  is  etch.  patterning  can  device  has  better  a  this,  reason  to the surface  in  reactions  of  by  layer  producing  proceeds by oxidation-reduction-complexing be  in an  damaged  and Mn  used  spite  little  obtained  essential  widely  but  are sometimes  addition  chemically  fabrication. The  removed by a surface  plays  example,  He  wafers  in  been  subjected  characteristics  a subsurface  wafers.  that they can be subsequently  technology.  device  topic. However, recently Dzioba  LEC  Surface  already  frequently  before  performed. Annealing,  substrate, also  mask  are  on etched samples. G a A s  is  have  quality mirror finish. In  device  reported the presence  etch  wafers  into a high  a  that  percentage an  to  GaAs  polished  understanding  manufacturers  on  available  common  surface etchants  resulting  surface  the specific  etchant  used. Most concentrated example  in  of on  the the  Schottky  work effects or  on  the  after  ohmic  the  surface active  contacts,  17  it  treatment layer  is  well  has  of been  reported  GaAs  has  formed. For that  a  light  18  surface  etch  electrical  performed  characteristics  surface  layer  Si-implant fabricated  of  removal  and on  just  to  the contacts  on  device  prior  the  LEC  Schottky  (100)  evaporation  [48]. In this  characteristics  undoped  metal  study  metallisation, were  GaAs  improves  the effects  the  profile  investigated.  wafers.  The  the of a  of  the  Devices  wafers  were  were  not  annealed before etching.  32  DIAGNOSTIC The  test  test  pattern  patterns  important the  are  with  was  based  commonly  fabrication  pattern  pattern  PATTERN  data  that  of  incorporated  on  important  on  process  device  Immorlica  into  steps  al. [49]. These  fabrication  can  dimensions  et  be  is  masks  collected. A  given  in  so  that  layout  figure  of  3.1. The  contains: 1. A  Schottky  diode, D1, to  evaluate  the  doping  profile  and  gate  metallisation. 2.  Four  etch on device  different  mobility  T3, known  profile of  4. A  van  as  the active  der Pauw cross  to  monitor  the  effects  is  used  of  the  the  FATFET,  layer to  also  to  obtain  the  [50].  measure  the  sheet  resistance  and  Hall  [51].  3.3 DEVICE FABRICATION AND The  devices  by  on  55. The wafer  page  Cominco  were  supplied  table  T1-T4,  characteristics.  3. MESFET drift mobility  MESFETs,  before  EXPERIMENTAL  fabricated  Ltd. The  etching.  was  fabrication  first  The  on  undoped steps  diced and  etchant  PROCEDURE LEC  used  (100)  are  listed  pre-cleaned to  used  was  GaAs  step  wafer  in Table lb  4  in the  5NH OH:2HjO :240H O. 4  2  2  19  Tl  • •  (10x500um)  T3  If t  ~ j | ^  EP  T2  Schottky  (10X200UBI)  diode  (100x4lOum)  Figure  3.1: Test  Mask  Layout  (I00x200um)  20  Approximately  2/tm  etchant  has  which  of an  rate  was  determined  The  rest  of  the  GaAs etch  with  was  rate the  fabrications  removed  of  aid  2000 of  steps  the used  in  a  fresh  angstroms Tencor are  per  of  the  minute. This  Alpha  as  mixture  listed  Step  200  in  table  etch  profiler. 4.  The 12  implant  energy  and  dose  were  fixed, they  were  80  keV  and  3.37  X  10  2 ions  per c m  respectively.  Samples up of  two  to  2*im  a  paragraph. no  visible  468s 126A  quadrants  of  surface  It  its  as  depicted  slice 468s 126. Sample  etch  retained  surface  and 468s 126D  using  the  mirror-like  damage  was  after  introduced. There  SECONDARY  Figure 3.2: Position  468s 126D  procedures surface  Of  in figure has  been  described the  etch  were  in  also  the  Wafer  no  made  subjected  indicating  FLAT  The Samples On The  are  32  above that  abnormal  21  features  in the dark  laboratory,  field  samples  A l s o , a fresh  have  solution  rate decreases  with  3.4 SCHOTTKY  METAL  The  image to  of  be  of  the surface. Based  pre-cleaned  the etchant  was  to  between  extremely  sensitive  to  nature  of  frequently  been  breakdown Schottky  their  barriers  analysing  the  to  investigate  GaAs  Schottky  metal  diodes  height  of  heights, or  (0)  model. The model  =  SA  featureless  etch.  because  etch  its  and  factors,  MESFET  ideality  current  in  caused  contacts  that  gates  by  can  metal  been  it  has  evaluated  currents used  to  (n)  accordance as  were  with  the  or  form  include TiW, and  factor  is  processing  be  leakage  have  the current, I,  and  Consequently,  damage  ideality  expresses  semiconductor  Schottky  ** I  each time  interface.  systems  and  diode  the  a  surface  characteristics  Metal  for  barrier  the  barrier  voltages.  The  emission  used  electrical  measuring  a  EVALUATION formed  by  experience in the  time.  contact  The  produce  used  Schottky  steps.  on  Al.  derived  by  thermionic  [42]:  qv T exp 2  (-  — KT  )[exp  1]  (3.1)  nkT  ** where V ,  T,  Boltzmann's respectively. 3.1  k,  S  and  constant, the If  the  can be rewritten  diode  A  are  Schottky is  the  voltage  contact  slightly  applied, the  temperature, the  area and the Richardson  forward  biased, V  >  3kT/q,  constant equation  as: qv  I  =  I exp(  )  s  nkT  where  (3.2)  22  ** I  I  is  =  the  SA  of  -  2  Schottky  characteristic ideality  <3* T exp(  a  — kT  diode  typical  )  (3.3)  saturation  forward  current.  biased  factor can be determined using  n  The  diode  is  current  given  the following  voltage  in figure  (l-V)  3.3. The  relation:  =  (3.4) AkT  where  A  is  the slope  y-intercept, I ,  of  kT =  n,  tn( SA  4> and  samples  468s126A  evaluate  n  current was applied. A  and  V  plot. With  can be evaluated as  the  value  of  the  follows:  the  current  equations the diode reverse  Table 2 gives a summary  )  (3.5)  2  468sl26D  <j> are  of  — § ^ — T  leakage  and  defined as plot  versus  i  q  The  m(l)  the barrier height  g  <t>  the  (1^)  were 3.4  of  all  the  measured. and  3.5  Schotty  The  diode  equations  respectively.  current when a voltage  biased  contacts  current  of the diode characteristics  is  of given  The  used  to  leakage  -2.5 volts in figure  measured.  on  was 3.4.  IF  (mA)  Figure 3.3: Characteristics  Of  The Forward Diode  Current  Table 2: Summary  Of  Schottky  Metallisation  And  Implanted  Layer  Characteristics  Sample  n Scatter  in n  <P (eV)  i n 4>  Scatter i  (MA)  L  Scatter W  in  I  (A)  0  Scatter W,  in  W  i n W,  "peak Scatter  (  c  in  m  UQ/n)  Scatter  in  n  V  M  R  R  P  -  V  E  A  g  (cm /V-s) 2  H  Scatter  in  u  (%)  Scatter  i n T?  468S126D  (UNETCHED)  (ETCHED)  1 .31  1 .79  0.18  0.28  0.72  0.70  0.03  0.05  10.77  13.71  1.10  1 .30  1957  2160  11 1  0  (A)  Scatter  7J  L  468s126A  H  s  K  )  90  3406  3623  229  231  3886  3627  165  166  3.26  2.69  0.42  0.18  4349  4406  204  385  12.24  15.86  1 .4  1 .1  25  IF  (nA)  MARKER (-2.5000V . -2.060nA .  .0000  .5000 /div  -5.000 -3.000  VF  Figure 3.4; Characteristics Of  .3000/div  ( V)  0000  The Reverse Diode Current  26  0000 .0000  500.0 TIME  Figure 3.5: Transient  50.00/div  (  S)  In The Reverse Diode Current  27  A routines in  of  the  The  current  that  occured  was  sample. This the  contacts. The  value  smaller  slightly  of  poorer  immediately  after  a  of on  evident  when  n the  and  the  is  not  of  the  avoid  the  measurement large  measurement  measuring  sample  leakage that  characteristics  damage  uniformity  into  the  transient  was  started.  small  leakage  3.5.  diode  surface  surprising  diode  received  were  obtained  a  larger  while  surface  on  the  etch. etched  damage caused by the etchant. The be  detected using  characteristics  because  was  has  introduced cannot  the  current  also  chemical etches  Schottky  deteriorated after are not  known  for  layer  will  resistance,  Hall  uniformity.  2.5 IMPLANT LAYER In  this  The expresses  They  and drift  DOPING  CHARACTERISATION  section  evaluated.  mobility  2.5.1  to  can be ascribed to surface  the etch. This  be  done  especially  average  incorporated  was  depicted in figure  <f> was  of  their  was  parameters. This  The  nature  time  the  transient  Hence,  wait  all  current as  that  seconds  30  the  include  electronic  doping  profile was  evaluated  the carrier density, N ( x )  A,  of  the  profile, the  sheet  active  PROFILE  doping  N(x)  C,  the  characteristics  mobility.  c  where  electrical  =  3  -  q  charge  and  c  using  the C - V  [42] technique which  as,  av —  are  (3.6)  the  capacitance, the  Schottky  and the permittivity respectively. C  contact  area, the  is related to the depth  28  of the profile, x  by,  cA C(x)  A work  much  of  surface  slightly  is  present  volt.  profiles The of  implant  dose  LCR  profile  in  and energy  addition Labs  keV, did gate  to  the  not  allow  voltage  all the  zero  other  diode  LCR  the peak  used. In  from  is  to  meter  is  the  carrier  up  deeper  sample,  into  the  of  and 468s126D.  on  etched  the  wafer.  It  a  at  a  is  the  problem power  are  10  the  using  to  obtain  HP  9816  a  the  HP  doping  computer,  a  box.  directly related to the  because  it  depth  of  energy,  within the  the  profile  16 and  the  etched  Figure  3.6  gives  10  in Table sample the  per  cm  sheet  (W,  3  2. Compared on  typical  the  carrier  and  W  0  with the  average  profile  can be seen that activation was the  0.25  MESFETs.  1 MHz  result, the  on  However,  the  with  lay  a  in  breakdown  profiled  region. A s  diode  of  peak  be  the  a gate  implant  to  and  evident  by  low  used  carrier concentration  the  prevents  obtained, the small  implant  468s126A  current  is  and an electrically shielded  concentration  substrate.  metal  the profiles  depletion  the  This  not  included  respectively) were recorded and summarised unetched  forward  limited  15 when  the  of  the surface, the  measured  set  because  scanned from  usually  was  and  volt.  hand  experimental  probe station  depth of  energy  The  close  in active channels  the  voltage  but the resultant  constraint  used  of  gate  3.6 which were  the  diode. This  meter.  Wentworth  biased  on  zero  the semiconductor  scanning  depth  at  profile very  in figure  capacitance  4275A  implant  given  the  The  The  over  profile  voltage  states. To  forward  improvement  doping  zero  layer  function difference between  usually  80  (3.7)  depletion  presence is  = — x  on  went  samples  generally  concentration  higher and  DISTANCE (urn)  Figure 3.6: Typical Doping Profile Of  Samples 468s 126A and 468s 126D  30  subsequently profiles  percentage  because  surface using  the  cannot  the be  peak  activation  carrier  2.5.2  SHEET  sheet  Pauw's  The  sheet  activation  calculated  and  its  depth  efficiency, can  be  from  the  from  the  evaluated  in the next section.  RESISTANCE  The der  be  concentration  determined. The  the van der Pauw cross  cannot  resistance  method  with  resistance  of  the  the aid  implanted of  is written as  the  layer was  van  der  evaluated  Pauw  cross  using  van  (figure  3.1).  [51],  \  R  =  (  i  where  HP  voltage  4145A  measure  Table This  )  resistance  because  pair  of  analyser  electrodes, C  (SPA)  was  and  used  D.  The  to  both  chosen the  A  a function of  applied current is  given  was  B  of  obtained  der  Pauw  arbitrarily and should  not  have any  resistance  the  the value van  sheet  and  defined as  is  essentially  when  cross  constant  was  bearing as  can  3.7.  smaller  sheet  of  the  of  sample  resistance  directly from  uniformity was  other  as  resistance  electrodes  current was  profiles  the  parameter  sheet resistances  follows  at  and source the current.  sheet  in figure  2. A  doping  of  reading  The  8  A B  measured  between  500MA. This  be seen  I  3.7. The sheet  current  the  )  semiconductor  plot  in figure  on  2  the voltage  A  the  (  >  is the current applied between adjacent electrodes, A and B, and  I^g the  n  3  the  etched  higher  468s 126A was  and 468s 126D  obtained  for  the  are given  etched  carrier concentration observed  sample.  In  addition,  also better on the etched substrate.  the  sheet  in  sample. in the  -resistance  31  R5  (OtJ)  MARKER ( 500-OuA  .  4.03E+03.  5.000 E+03  .5000 /div  ,0000 250.0  50.00/div  12  Figure 3.7; Sheet  The In  this  probe to  case,  mobility the  station. A  the  current der  Hall  sample  was  sample magnetic  using  of  250MA  Pauw  cross  an  was  Alpha  *H  < s AC> R  where  BI  placed 0 to  on  The Implant  using a  02  Scientific  applied  the  Of  measured  field of  monitored. The Hall mobility  'BD  also  was  also  while  Resistance  the  probe  Laboratories  in  MJJ is given by  the  van  holder  tesla was  between the  voltage  750.0  (uA)  der Pauw instead  cross. of  the  applied perpendicular magnet.  opposite  ends  remaining  two  A  constant  of  the  ends  van was  [60],  (3.9)  32 Vgp, (figure  B  and  R  is  g  3.1), the "voltage  the  measured  field applied and the sheet The 7] is  activation  defined  current  applied  between  resistance  between  electrodes  electrodes  A  and  C  B and D, the  magnetic  using  and  respectively.  efficiency, TJ, can  be  calculated  the  R„ S  n  as;  N V  where  - D  (3.10)  is  D  the  implant  concentration which  dose  and  can be evaluated  the  N  using  undepleted  the following  sheet  carrier  relation,  1 N  =  (3.11) (qM R ) H  As  s  a result, equation 3.10  can be rewritten  as,  1 n  =  (3.12) (DqM R ) H  The  Hall  equations  3.9  obtained  were  the  removal  for  direct ion  s  mobility and  of  respectively. The  3.12  slightly the  higher  surface  efficiency were average  value  on the etched sample layer  resulted  in  a  of  (Table  marginally  determined both  using  parameters  2), implying better  that  substrate  implantation.  2.5.3 DRIFT MOBILITY Because  and the activation  the  PROFILE  drift  the  channel, it  can  be  An  approximate  M  value  mobility used can  to be  (u)  is  assess  a function the  obtained  of  quality using  the  the  of  the  traps  present  implanted  technique  in  layer.  invented  by  33  Pucel and Krumn  the n  [50] which expresses  g L  as:  2  m  V  =  (3.13)  g as where  g ,  Cg,  L,  m  capacitance  and  and  drain  V^  are  s  source  the  transconductance,  voltage  respectively.  gate  All  the  needed to obtain the u profile were performed on F A T F E T measured  using  together. T o across  the  undepleted  the  LCR  measure drain  the  and  channel was  profile  corresponding profile was  of  seen  of  1^  u  is  from al.  u  [52]. It  substrate that  towards been  because  of  not  case.  smaller. This  It  the  constant. The g  is  in  figure  also  T3. The electrodes  50mv  plotted. The  the  the  voltage  figure, the  characteristics peak  mobility  u was  (Table 2).  implant  not  of  voltage.  same  same  tied  applied  a particular  to  a  peak  from  that  the  damage  annealed  at  away  the  agrees  surface  with the result  profiles  M  the active [53].  and  decrease  layer  Although,  known could  for be  certain caused  obtained on the etched  at by  sample.  this the  decreases of  a  point inferior  Lee et  towards  substrate  why  peak  the  interface  higher  observed on the etched sample, its average is  was  plot at that  3.8. On  was  cross-section at  m  a function of  given  suggested  discrepancy  characteristics  that  gate  measurements  source  used. Only  so  the substrate. This  been  concentration was was  as  increases  has  has  was  and  in all the F A T F E T s tested. The average  profile  the peak  drain  electrodes  profile  calculated from the profiles The  the  SPA  m  essentially  the  doping  with  g , the  source  is defined as the slope A  meter  length,  carrier mobility  this  Schottky  is  the  diode  Figure 3.8: Drift  Mobility  A n d Doping  Profile  00  35  3.6 DEVICE In  PERFORMANCE  characterising  parameters:  the 1$  K,  K-factor, the saturation transconductance  MESFETs  the  on  a n c  ss  is  given  9-  They  m  voltage  listing  of  in appendix  saturation  gate  '  MESFETs, are  we  measured  the  region, is  the  threshold  drain current with zero applied gate  respectively. A  the four parameters Above  fabricated  the program  following  voltage,  voltage  used  for  the  and the  determining  A.  the  dependence  essentially  quadratic  of  and  drain can  be  current  of  written  as  [42]:  J  d  "  K  (  g " th>  V  V  with the K-factor  K  defined  2  '  ( 3  1 4 )  as.  =  (3.15)  2aL where  W is  the  gate  the drift mobility and The  Ij-V  d  drain-source the gate of  the  g  slope  the the slope  of of  e  the  of  gate  length, a  2.5  of  volts.  all  the  The  V ^  when the drain current is the 1^  the  channel  thickness  u  the permittivity.  characteristics  voltage  voltage  width, L  as  a  versus V g  function of  MESFETs in  the  were  measured  program  is  5 u A . The K - f a c t o r Vg  plot. The g  plot between a gate  m  voltage  defined  is the is of  for  a as  square  defined 0 and  as -0.1  volt. All 3. Figure the test  the DC  parameters  3.9 gives a plot  of  measured the l-V  structure. On all the M E S F E T s  on  the  MESFETs  for each of  are  listed  the M E S F E T s  except T3 the following  in table  (T1-T4) trends  on  were  36  ID  ID (DA)  (mA) •  2.000  1.500  VG-OV  VC-OV  .2000 /div  .1300 /div  VC—0.7V  '  VO.-0.4V  .5000/div  VC.-0.4V  VC—0.6V  'y  VC.-O.OV  VDS  If  • If  VC.-0.fV  .0000 .0000  VG«-0.*V  ( V)  .0000fc5.000 .0000  vc.-o.8v •  •  1  '  •  VDS  .—1  1  .5000/div  T1  •  •  ( V)  '  5.000  T2  ID (UA)  300.0 30.00 /div  vg.-o.rv -0.4V  VB.-O.CV •-0.6V WB'-O.IV  .0000 .0000  VDS  .5000/div  ( V)  5.000  .0000 .0000  T3  Figure 3.9: Current Voltage  *6«-0.0V VDS  .5000/div  ( V)  5.000  T4  Characteristics  Of M E S F E T  T l , T 2 , T 3 and T4  37  observed on the sample  that  has  received a surface  removal  before device  fabrications: 1.  w  a  2. I^gg 3. g_  rnore negative  s  became became  4. K-factor Although  the  larger  larger  became  MESFETs  larger  tested  were  characteristics, it can still  be  the  prior  surface  layer  characteristics. and  the  Since  the  channel was  unetched etched  just  sample  sample  to  device  K-factor  doping  implies  that  designed  with  inferred from the results  is  deeper on the  (from  not  the  to  etched sample  profiles), a higher implanted  improved  u/a  in comparison  also  3.15)  with  obtained  has  of  device  (equation  K-factor  channel  transistor  that the removal  fabrication  proportional  optimal  better  on  the the  transport  characteristics. The Vj.^ *dss  became P  r e s e n t  speculate  more -  misalignment.  the  As  followed the trend of  negative  covered  mask, the  gates of  T3  This,  that  completely  test  of  dss  can  gate  the  other transistors  on the unetched sample  smaller  channels by  the  be  seen  of  the  T3  K-factor  of  FATFET  gates. in  does  and  This  figure not  3.1  overlap  g  T3  have  m  on  can  gives  channel  the other M E S F E T s . Hence, a slight misalignment  in the channel of  MESFET  of  the  prompted  468s 126A result  which its  despite  T3 not being entirely covered.  from a as  but  smaller us  were a  its  to not  slight  layout  of  the  much  as  the  can in fact result  Table 3: Summary  MESFET  Of MESFET Characteristics  Vth  K-factor  (V)  Um/V ) 2  Idss (A)  Gm (ms/mm)  T1  468S126A  Ave. Sdev.  468S126D  Ave. Sdev.  - 0 . 82  1 .7 7 E 3  1 . 1 7 E - •3  •3. 91  0. 29E3  0 . 3 0 E - •3  0 ..75  - 1 . 21  1 .8 7 E 3  2. 3 8 E - •3  5. ,99  0 . 31  0 . 18E3  0 . 5 5 E - •3  0 .,56  - 0 . 74  9. 89E2  5. 3 6 E - •4  4.,65  0 . 13  0. 75E2  1 . 7 4 E - •4  1 .20 .  - 0 . 98  1. 0 7 E 3  9 . 9 3 E - -4  7..25  0 . 17  2. 04E2  1. 9 1 E - -4  6..82  - 2 . 67  23 . 6 0  1. 2 3 E - -4  1 .01 ,  1. 2 5  22 . 7 3  0 . 6 8 E - -4  0.. 4 5  - 1 . 12  2. 05E2  2 . 6 0 E - -4  1 .84 ,  0 . 12  0. 30E2  0 . 5 5 E - -4  0,. 2 5  - 0 . 79  7. 20E2  4 . 6 8 E - -4  1 .,9 4  0 . 14  1 .0 2 E 2  1. 5 9 E - -4  0,. 5 3  8. 1 0E2  9 . 0 9 E - -4  3 .18  0 . 87E2  2. 17E- -4  0 .51  0. 1 1  MESFET T2 468S126A  Ave. Sdev.  468S126D  Ave. Sdev.  MESFET  T3  468S126A  Ave. Sdev.  468S126D  Ave. Sdev.  MESFET T4 468S126A  Ave. Sdev.  468S126D  Ave. Sdev.  -1 . 08 0 . 19  39 2.7 B A C K G A T I N G  EFFECTS  Backgating electrode space  on  region  voltage  Backgating  effect  a  negative  applied,  The  voltage  backgate  the  drain  the  current.  channel  degrade  can  the  traps  as  possible the  underlying  layer  with  device  devices  with  voltage  is not  material  [56]  for and  substrate negative  pinched-off.  instance, the g  ions  [59]  such or  as  a  and  negatively  B  the  biased  low  include  of  p-type  presence  effects  [58], a  at  effects a  p-type  Schottky  is defined  are first  seen. It can be increased by  H, O  m  slow  [55]. backgating  at which backgating  always  test  structure  in figure 3.10. A s MESFET  T2  The  backgating  and  measurement  shown  using  sidegate. The side gate  observed.  using  guard  contact  isolation  ring  around  between  pad  C  of  is 400Mm effects  cannot location  be  were  effects. This  compared, those can clearly be  (normalised  with  I .  the  van  der  this  Pauw  from the MESFET  both  samples  were  the  experiment  at  on  etched wafer  is  the  in figure plotted  3.11 as  as  to  function  from  the surface etch  the  show  vary  same  less  relative  backgating  where the normalised a  the  T2.  found  approximately  is  were taken  structure  the effects of  devices  seen )  for  away  on  detected. But, when  set-up  in the figure, the measurements  region to region. Hence, an overall trend of  current  completely  the  [60].  The shown  responsible  nearby  modulates  [57]. The threshold voltage, V ^ g , for backgating  In practice, V ^ g  the  a  sufficient  device performance. For  mechanisms  the the backgate  implants  to  characteristics [54] and the frequency dependence of  in  conversion  voltage  With  be  frequency have both been attributed to backgating The  applied  interface between the channel and the  affects  can seriously  in l-V  of  characteristics.  at the  subsequently  backgate  drift  the  MESFET  charge  which  is  of  the  drain  backgate  40  V(SIDEGATE)  V(DRAIN-SOURCE)  Figure 3.10: Measurement  Set-up  For The Backgating  Experiment  voltage. From voltage  plot  (normalised  becomes voltage. charge  more This region  backgating. layer  the  is  impurities  In  of  percent  with  v" ),  evidence at  the  undoped  dependent  on  like carbon.  given  tn  pronounced  as  the  supports active LEC the  change  the  layer GaAs  in  in  gate  figure  versus 3.12,  voltage  claim  that  substrate substrate,  compensation  1^  of  normalised  the  backgate  approaches the  existence  interface the the  the  is  width  of  EL2  level  of  gate effect  threshold a  space  reponsible this and  for  depletion residual  .500 E+00  468*i26D  1500 /div  468s126A  00001 i -2B.00  i  i  VB  i  1  1  1_  4.000/div  *  0  ( V)  »  B.000  Backgate Voltage  3.11: Normalised Drain Current Versus Backgate Voltage  42  A  468S126D  X  468S126A  0.1  0.2  0.3  0.4  0.5  0.6  0.7  0.8  0.9  Normalized Gate Voltage  Figure 3.12: Drain Current Versus  Normalised 6ate  Voltage  4. EFFECTS  4.1  OF DISLOCATION ON  [61],  of  GaAs  cathodoluminescence  variation been  [64]  and  correlated  dislocation than  10  the  of  complexity  question.  It  the formation  GaAs  substrates  activation  GaAs  [65].  wafers  using  SEM-EBIC  bulk  resistivity  [63], These  variation  phenomena  across  can range  voltage  of  the  structure  threshold of  the  the  and  generally  characteristics this  on  the  from  voltage  dislocation  proximity  to the  held  was a  to  have  wafer. 10  to  4  dislocation  scatter  of  not  channel  been  of  centre, or  threshold  The more  the  that effect  whether the  dislocations  density  density local  [67].  and  dislocation  be is  the  dislocation  [68,69]. In to  diodes  MESFETs  of  an  addition,  dependent an  on  on  ambiguity  scatterings. dislocations is  not  local  structure The  become  emitting  of  their  found  adverse  dislocation  proximity  voltage  voltage.  43  the  [70]. Clearly, there  is  determine  of  that  doping  by  been  threshold now  time  in agreement  also  pattern  reliability  and light  that  affected  has  origin  long  possible  characteristics  influence  opinion  help  shown  the  are  a  the  and  in lasers  electrical  the  have  but the exact  study  for  has  thus  to the origin of the MESFET The  increases,  known  MESFETs  MESFET  scatter  ICs  performance  recently  affects  studies  threshold  been  only  of  GaAs  dark-line defects  density. However,  controls  density  device  has  efficiency  voltage  the  of  on  of  published  threshold  of  photo-absorption  and 3"  dislocations  [66]. Work  as  observed  2  important cause  been  photoluminescence  dislocation  in 2"  has  per c m .  5  effects  with  wafers  [62],  infrared  density  As  The  CHARACTERISTICS  INTRODUCTION Non-uniformity  of  DEVICE  of  method  affect  device  known. The object dislocation dislocation used  density, pattern  involved  the  44  design,  the  200Mm  x  fabrication 146/xm.  dislocation nearest  After  centres.  Following sections  4.3  discussed  of  taken of  MESFETs  the sample  for  variations  of  time  that  was  density  were  array  of  etched  and  obtained  to  distance with  the  pitch reveal  to  the  aid  of  after the etch.  a  literature  survey  will  be  and experimental  these  it was  as  10  per c m ' does  of  the  is  significant  given.  results  In  will  the etch pits  be  where  diameter of [21]. The  a  across  partial  line  a G a A s wafer  relief  to  wafer  believed then that  a hexagonal  a SI  pit  meets  follows  density  less pronounced towards  a  it after an A / B  dislocation  dislocation  quality.  not  were  One  of  the  it has  been well  and  dislocation  until  1982 that  studied  a dislocation  channel  the  [71]. This  density  as  is  high  not affect device characteristics.  on  done. The etch creates  the active  resistivity  boule, it was  The dislocation variation across counting  substrate  of  the substrate. Although  a GaAs  parameters  commonly  for the formation  on  there  the length of  because  4  into G a A s  requirements  some  along  a  MESFET  SURVEY  is the homogeneity  variation  as  a  sample  dislocation  introduction,  implantation  requirements  point  of  respectively.  stringent  3 X  local  the  and 4.4, fabrication procedures  Direct  known  measurement  measurement,  centre  this  2.2 LITERATURE  places  the  Exact  dislocation  micro-photographs  and  on  growth. Jordan et al. [74] has  and  the surface  it. The  and  the tail end of  can be obtained  [72] or molten KOH  its  the  radial  of  dislocation  a W-shaped  increases  the axial  G a A s wafer  [73]  etch  the wafer density  by is  at the  along  the  variation near the seed  end  W-shaped  variation  ingot. Dislocations  stress  which  arise  become  are  formed  during  crystal  theoretically predicted the W - s h a p e d  variation  45  using  a  thermo-eiastic  which  are  typically  dislocation  and  sinks  those  for  atmosphere  a  point  nm  hundred  defects.  free  This  often  in  region  in SI  used  size  creates  what  reduce a  its  a  GaAs  wafers. Terashima  vertical  Bj0  dislocation  GaAs  wafers  high  3  magnetic  encapsulating  density  hardening  generation  as  field  et  al. [9]  during  layer  through this  pits  In  can  also  reduce  the  atoms  to  of 10  increase  10  G a A s , no degradation of  high  resistivity,  the compensation of  it  is  of  19  seems [78]  surprising  dislocation to  be  using  that  dependent  Van  der  Pauw  (100) oriented undoped SI found spot  a  act  a as  Cotterell  W-shaped  to  10  variation  on  susceptor  G a A s wafer  cm  was  3  is of  to  with  obtained.  density  resistance  it 3  melt  et al. [77]  dislocation  cm  al. [76]  true  of  to  that  the very  In  is  used,  is  obtained  in  is found.  to a  of  SI  GaAs  can be changed variation  estimates  found be  the  by  should of  the  dislocations. Thus  closely  follow  resistivity  used. Brozel  resistivity  variation  whereas  oriented wafer  Blunt using  that  variation  technique  M-shaped  similarly  by  and C, with deep levels, like Cr  measurement  method GaAs  per  fi-cm,  balance  the  per  and  8  However  on  et  reduce  the  crystal's  Hall mobility  the resistivity  density.  to  on  Although  atoms  levels, like Si  [4,15]. This sensitive  not  the  10  shallow  the  dislocations. X  Osaka  technique, a 2"  etched  In  and  a window  1000  7  and EL2  the  striations. Shimada  as  propogation  concentration, 5  The  contain  centres  as  growth  low  using  [10]. The  and  In-alloyed  known  networks  cells  dislocation  is  cell  have been made to reduce the dislocation density  temperature gradient. Using  Impurity  in  [70]. The  because  temperature fluctuations which produce growth heated the  appear  around the dislocation centres [75].  scatter  have  few defect  Many attempts its  model. Dislocations  et  across  al. a  et al. [71] the  dark  method. The reason for the different profiles obtained is not known.  46 Leakage  current  in undoped SI of  G a A s wafers  Cr-doped  because  in  measured  SI  GaAs  compensate  did  substrates,  shallow  illumination  [79]. The same  wafers  Cr-doped  under  donors  not  after  the  a  measurement  result  there are  gave  in  still  a  along  similar  plenty  sinking  M-shaped  of  action  profile  the diameter  profile. This Cr  of  atoms the  is  left  to  dislocation  centres. High GaAs al.  resolution  wafers  [80]  using  0.65eV 'and lightly  doped  inversely  other  SI  and  is  is  growth  substrates  through  wafers  diffusion  etch  which  heat  showed  W-shaped two  due to  in  bands,  in both  with  the  and  regions  on  SI  is  one  etch pit  and  density  other band  postulated  where  at  undoped  level. The  variation  EL2  profile [22]. Tajima et  appeared  the EL2  density  that  emission  coincides  generated  or  the  whole  involving  shown  improve  to  more  shows  smaller more  thermal treatment during  after in  result  improve can  ingot.  As-vacancy  uniform  device  the  the  uniformity  obtained  either  improvement  is  [81]. Illuminated intensity  annealing  comparision  be  The  [82]. HB with  photoluminescence  to  is be  dislocation  LEC  and  characteristics  line grown  of by  leakage  GaAs For  about current,  have  all  crystals  are  example, HB  cathodoluminescence of  HB  crystal  LEC  annealing  brought  variation  crystals.  SI  is  due  at to  a the  growth.  inhomogeneous  affects  an  can  cathodoluminescence  uniform  dislocation. This  treatment same  been  wafers  are  1jim  that  band  pit  the  and  The  found  be  and  resistivity  GaAs  known  0.8eV, consistently  the  bulk  generally  at  low.  Post  individual  at  believed to  microdefects  density  the well  GaAs. The 0.6eV  related to  to  GaAs  follows  absorption  photoluminescence  the  distribution  due  also  infrared  dislocation  density  characteristics. Nanishi  et  distribution al. [83]  across  have  shown  GaAs that  47  MESFETs  fabricated  on  high  dislocation  regions  have  higher  drain  source  current and a larger negative threshold voltage than those fabricated on  low  dislocation  and  regions.  Wang  et  al.  transconductance  vary  also  the threshold voltage  found that  proximity  to  20-30jjtm  away  (figure  a  dislocation. exhibit  4.1). Below  scatter. so-called  This  directly with  this  critical  denuded  photoluminescence  a  critical distance  [63]  and  showed  etch pit of  MESFETs  lower  zone  [84]  less  was  than  voltage  a  in  agreement  surrounding  a  et  critical  than  with  those also  the  dislocation  cathodoluminescence studies  distance  i IX  away  shows  more  radius  [62], Recent  01  >•  I  —«-  so  •+-  100 Distance town Etch Pit, (ym)  -0.1 -02  Figure 4.1: Threshold Voltage Versus Distance T o Nearest Obtained By Miyasawa et al. [85]  of  revealed  02  0  of  further  0.3  > • f  al. [85]  influenced by their  distance, threshold voltage is  mobility  density. Miyasawa  MESFETs  threshold  that  Dislocation  the by work  48  by  Ishii  et  al. [72] has  influenced  by  cell  region,  a  strongly  scatter  was  shown  network  for  threshold  structure. At  networked  small  that  structure  randomly  a  voltage  high  was  threshold  found  networked  scatter  and  structure  scatter  threshold  voltage  despite  matters, the threshold voltage  also  found  the  used  [86]. Winston  MESFET  reported  cm  dislocation  group and  to  strong  resistivity  and  SEM-EBIC  and this  of  fifth  uniformity  Cottrell atmosphere  that  other  types  high  scatter was  annealing  correlation  method  between  the  studies  those  In-alloyed  an implanted  layer  with  of  a dose  conventional of  GaAs formed  5 x 10  12  GaAs  wafers.  neutral  EL2 in  device properties and suggested  may  of  free  concentration  be  more  wafers  undoped  SI  important from GaAs  etch pit density  displayed showed  little  two  three  types  formed  at  high  One  mobility  between of  the  suppliers  crystals.  and Hall  correlation  that  than  these  dislocation  to be due to the temperature  formed. Dislocations whereas  of  et al. [90] using  two  [61]  of  60keV  the local  has been postulated  were  at  correlation between the  any  and  dislocation  in controlling  uniformity. Tamura  showed  dislocations  implant  that  concentration  existence  dose  find  completely  one  is a key factor  the  parameters. exist  reduced  EL2  not  carrier concentration  et al. [89] showed  the  implant  its  and its proximity to a dislocation.  .28 28 (7 Si)  silicon  the substrate  showed  al. [87] did  the sheet  was  2  Dobrilla  that  et  on  et al. [88] using  that  a direct  per  dependent  threshold voltage  Hyuga  by  be  strongly  voltage  dislocation density. To complicate to  is  temperature  at which have  formed at low temperature do not.  a  49  4.3 EXPERIMENT This  experiment  Invariably, device  involved the fabrication of  the fabrication  characteristics  process  measured.  inhomogeneity, the process to  this, we  length  MESFETs.  laboratory by  by  An  better  Si N }  of  attempt  [91]. In Si N 3  In  is  impossible  order um  in  of  which  deposited  length  the difficulty  channel  to  1*im  ones  obtain  good  to gate  at  the  beginning avoided  in  gate  width  decided  to  length  this  formed  step was  achieve  gate  in  was  involved  narrow  position. We  regards  2um  and  channel  surface. This  and  substrate  performed  active  gate  and  at  obtaining provide 2um  use  better  yields.  uniformity  for the  lithography.  size, a  The  the  registration  mask  array  of  between  spacing  makes is  pattern  effects  of  dislocation  pitch  200*im  x  networks 146/xm  occupied by the three 80Mm squares  distance  pattern  mark,  and ohmic  MESFET  a nominal  drain. This  designed  microscopic  the area is  gives  The  implant  look  transistor.  10/im which gate  was  work  study, the  conventional optical  to  used. The bulk the  this  of  the  to the  be minimised. With process  because  shorter  of  fabrication  GaAs  MESFETs.  inhomogeneity  influence  was  of  DESIGN  hundred  probe  at  layer  active  the  shorter gates using  MASK  mask  that  4  Short  the  of  Furthermore, it  or  must  earlier  layer.  4  instead  few  induced scatter  protect the sensitive  definition  gates  4.3.1  the  four  a  introduce some study  fabrication procedures  uniform  To  simple  through  fabrication to  in our  a  W. Tang  implanting  of  a  chose  will  dense arrays  of  B  the  drain  and  source  4/zm between the gate  alignment depicted  the  in  of  the  Figure  channel  gate 42  implant,  metal  was  used  to  pads  is  and  source  mask  easier.  below. Pattern pattern  a  C  contact, and pattern D the gate. For economical  the  A  is n  +  reasons,  50 all the fabrication levels were placed on the same  mask.  2.3.2 FABRICATION PROCEDURES An figure  overview  of  the fabrication process  4.3. The details Step  also  1  etched  removal  of  of the process  removes  the  remove  the  top  the  surface  oxide  schematically  illustrated in  are listed in Table 4.  grease  to  is  from 500A  layer  the of  and  samples.  the  the  The  surface.  samples  This  were  ensures  'disordered' region  the  right  under  the  higher  the surface. Steps  2  of  the  ievels  to  applies to  etch  mask.  fabrication, proper repeat steps  7  To  resist  2 to 7 till  later resist  Steps  8  to  the  registration  ensure  easier  development a good  pattern  resist  necessary  alignment  must  be  pattern  in  for  later  obtained. It is  is  stages  of  advisable  obtained. This  advice  to also  development.  13  involve  laying  down  the  resist  mask  for  ions  were  used  to  selective  28 implantation channel tilted the  of  n-type.  7°  away  substrate  channeling  the  channel  During from appear  [92]. T o  uniformity  of  the  fundamental  axis. An  ion its  regions. implantation,  <100>  amorphous minimise implant, implant  Si  axis  to  to  the  planar the dose  the  (100)  any  sample of  <110>  incoming  channeling  orientated  and  make  sample  direction. This ions, also  preventing to  was rotated 20° 12 3.37 x 10 at 80keV was  increase from used.  the was made axial the the  + • • • • + . - • • • • .+• •lt • • •••• • • • • T +  • •  •• + • LTJ + • LXI  C D  + • ' • • . • •  + •  m •••• • • • • T • • • + • • • • + • • • •••• • • • • T • LTD + C O • • +• • • • • • • • • LTD T B  C  Figure 42: M E S F E T  Array  52  SI GaAs  (A)  Wafer  pre-clean  SI GaAs  (B)  R e g i s t r a t i o n mark e t c h  'A  UP. 1  N-CHANNEL  I  SI GaAs  (C)  Opening windows f o r i o n - i m p l a n t a t i o n  Figure 4.3: Schematics  Of The Fabrication  Process  53  SI GaAs  (D)  E n c a p s u l a t i o n and a n n e a l i n g  N-CHANNEL SI GaAs  (E)  O p e n i n g windows f o r gold-germanium  //  A  !  contacts  H-CHANNEL SI GaAs  (F)  E v a p o r a t i o n o f g o l d germanium Figure 4.3: Continued  i  54  ///// j  N-CHANNEL  j  SI GaAs  (G)  L i f t o f f of p h o t o - r e s i s t , and a l l o y i n g  j  N-CHANNEL SI GaAs  (H)  e v a p o r a t i o n of aluminium.  Figure 4.3: Continued  J  55  Table 4: Detailed Fabrication  No  Process  1.  Pre-implant  Steps  Description cleaning  a. Degrease 5  minutes  rinse  each  in  warm  trichloroethylene,  acetone  and  iso-propanol. b. G a A s Soak  etch  for 4 minutes  in  phosphate). 15 seconds  1% filtered alconox (monosodium Dl  H 0  rinse and N  2  2  blow  dihydrogen  dry.  c. Oxide etch Immerse H 0 2  2.  for 30 seconds  rinse and N  2  blow  in  1H O :5NH OH;240DI H 0 , 15 seconds 2  2  4  2  Dl  dry.  Clean 2 minutes acetone rinse, 2 minutes  iso-propanol  rinse and N  blow  2  dry.  3.  Resist Spin for  coat Shipley  AZ1400-30  20 seconds  resist  (approximately  at 4500  rotations  1.7jim thick). Soft  per  minute  bake at 9 5 ° C  25 minutes.  4.  Registration  mark  level  exposure  1 minute under ultra violet (UV) light  (Karl-Suss  (RPM)  MJB3).  for  56  Develop Develop time  in  50%  Shipley  Microposit  is approximately 45  Registration Rinse  for  developer.  Developing  seconds.  mark etch 1 minute  in  10%HCL, 1 minute  5%H P0 :2.5%H 0 :92.5%DI 3  MF312  4  2  2  H 0, 2  5  minutes  in Dl in  H 0 , 50 seconds  Dl  2  H 0 2  and  N  2  in  blow  dry.  Resist Soak  removal in warm  acetone.  Clean 2 N  minutes 2  blow  Resist Spin  warm  acetone  rinse, 2  minutes  iso-propanol  and  dry.  coat Shipley  AZ1400-30  resist  bake at 9 5 ° C  for 25 minutes.  Channel  exposure  level  1 minute under UV  at 4500  RPM  for  light.  Develop Rinse  rinse  in 50% Shipley  Microposit  MF312 developer.  20  seconds.  Soft  57  Channel 28  Si  implant  at 80keV  and dose of  3.37 x  10  acetone. 0  plasma  12  per c m . J  Resist removal Soak  in  warm  2  200W, 200SCCM  of  O,,  120°C,  250mTorr for 25 minutes.  Clean 2  minutes  Nj blow  Si N 3  surface 500mTorr  at  4  acetone  rinse, 2  with  3  minutes  100W,  for  NH 5  plasma  at  100W,  minutes. Without  37.6SCCM  of  NH ,  500SCCM  3  4  Channel  of  and  of  NH ,  of  vacuum  3  deposit  He, 550SCCM  (about  of  800A).  implant anneal for 25 minutes  furnace  way  rinse  37.6SCCM  breaking  5%SiH /He, 3 0 8 ° C , 1500mTorr for 7 minutes  825°C  iso-propanol  dry.  Preclean 308°C,  warm  for  5  out, place  under flowing  minutes. Push  sample  at  edge  N, gas. Place  sample of  into  the  sample  at  edge  furnace. On  furnace  for  5  CF ,  125°C,  minutes  the  before  removing from the furnace.  Si,N, removal Freon  plasma  minutes.  at  200W,  200SCCM  of  4  500mTorr  for  4  58  18.  Clean 2 N  19.  20.  minutes 3  blow  Resist  warm  acetone  Shipley  95°C  for 25 minutes.  Ohmic  level  AZ1400-30  4500  for  20  seconds.  Bake  at  H 0  and  light.  in chlorobenzene.  Develop in 50% MF312 developer.  Oxide etch  N  3  for  blow  Ohmic  15 seconds  in  1NH OH:10HjO , 30 seconds 4  dry.  metal evaporation  1500A of  25.  and  exposure  for 2.5 minutes  Rinse  24.  RPM  rinse  Chlorobenzene soak  Rinse  23.  at  iso-propanol  coat  Spin  Soak  22.  minutes  dry.  1 minute under UV  21.  rinse, 2  Au-Ge.  Liftoff Soak  in warm  acetone and  agitate.  2  in DI  2  59  26.  Alloy 2 minutes at 4 5 0 °  27.  Ohmic  in flowing  N  Resist Spin  gas.  contact  Check drain source current at V  28.  2  gs  =2.5  volts.  coat Shipley  AZ1400-30  at  4500  RPM.  Soft  bake  at  95°C  for  25  minutes.  29.  Gate  level  exposure  1 minute under UV  30.  Chlorobenzene soak Soak  31.  for 2.5 minutes  in 50% MF312 developer.  Oxide etch Rinse  for  and N  33.  in chlorobenzene.  Develop Rinse  32.  light.  Gate  2  15  blow  metal  2000A of  seconds dry.  evaporation Al.  in  1NH OH;10DI 4  H 0 , 30 2  seconds  in Dl  H 0 2  60  34.  Liftoff Soak  35.  DC  in warm  acetone and  agitate.  measurements  The MESFET  DC  characteristics can now  be  measured.  61  To is  prevent  required to  dopants) Si N 3  atoms  loss  repair  a Si N 3  was  4  As  lattice  film  4  chosen  during  of  Si0  [93]. Furthermore, a  deposited  (PECVD) S i N 3  damage  about  over  a high temperature  2  as  well  800A  was  because  it  good  to  electrically activate  used  to  encapsulate  more  plasma  film can be easily  4  (which  as  is  quality  ( 8 2 5 ° C ) anneal  the  surface.  to  gallium  impermeable  enhanced  and quickly  the  chemical  vapour  deposited using  the  Plasma-Therm. Early  attempts  dissociation. work  on  The  the  exposing  resulting  sample  the  depositing  to anneal with S i , N film  had  implanted  the  Si N 3  4  to  The  film. The  was  annealing  introducing Samples wafers After  procedure  to  make  annealing,  sure the  abandoned.  NH  3  plasma  3  solved  minutes  of  removed  this  NH  the  Brute  described  in  step  16  surface  between  the  sandwiched the  Si N 3  film  Si N 3  film  4  between film  4  was  furnace  was  did  removed  the  pieces  layer  surface in  of  [94].  flowing to  during  by  freon  plasma.  2  surface.  clean  crack  N.  avoid  GaAs  not  by  before  oxide  followed  and  two  problem  plasma  3  its  hence, further  between the film and the G a A s Mini  4  resulted in  remove;  We  the  that Si N  5  to  in  strain  sometimes  the encapsulant  impossible  to  performed  excessive  were  be  sample  and promoted better adhesion Annealing  was  as  4  silicon  annealing. 10%  HF  solution can also be used. For soaked  ohmic in  metal  ( A u - G e ) and  chlorobenzene  for  chlorobenzene hardened the surface 'overhang' process  was  in  the  metal  2.5  minutes  of  the resist  resist  which  (Al)  liftoff, the resist  before  developing.  and upon  was  found  was The  development, an  to  aid  the  liftoff  [95].  Ohmic soak  produced  gate  metal, A u - G e ,  the sample  in  is  evaporated  1NH OH;10H 0 4  2  in  step  mixture prior to  24.  It  is  important  evaporation. This  to  mixture  62  helps  remove  the  surface  oxide  layer  and  during  developement.  This  same  soak  metal  deposition.  has  been  shown  before  Schottky  It  contact  resist  was  that  also  that  was  not  performed  the  removed  prior  1NH OH;10HjO  evaporation  gave  better  diode  performed  in the Mini  Brute furnace  gate  treatment  4  metal  to  characteristics  [47]. Alloying alloying was to  temperature was  used  to  check  determine  there is  if  the drain  there  final  gate  few  metal.  characteristics  of  complete  the  of  415°C  is  a  the  source channel  and  fabrication  Here the  no  duration was  current. This or  is  alloying  MESFETs  of  the photograph  flanked  by  regions  that  is  are  the  is  the edge formed  for  given  very  is  to  the  obtain  the  if  of  Schottky  deposition, fabrication  measurement. A  all  method  deposition  the  is  photograph region  at  array  is  the wafer. The MESFET  because  SPA  futile  in figure 4.4. The dark  of  2  simple  fabrication  36, involve  metal  ready  N . The  pads.  needed  gate  now  MESFETs  the top  placed on the same  are  is  in flowing  2 minutes. The a  not. Further  steps, 30 to  gate. A f t e r  a fabricated array of  4.3.3  and  no channel between the drain and source  The the  was  fabrication  levels  are  mask.  MEASUREMENT Measurements  were  performed using  semiconductor  parameter  probe  station  was  placed  as  light  shield.  This  a  because  the  automatic Precautions  channel  prober were  is  analyser in an is  taken  is  make  for  sure  Labs  ensuring  had  the  probe  box  4145A  station. The  which  also  acted  reliable  measurements  to  Since  sensitive  probes that  computer, a HP  shielded  extremely  available, the to  a Wentworth  electrically  important  current not  and  a HP9816  to  probes  be  light.  manually  were  an  moved.  applied  with  63  Figure 4.4: Fabricated MESFET  light  and consistent  varied as  much as  Only The  the  threshold  drain  and  saturation  pressure 25mv  source, region.  to Two  voltage. In  the first  voltage  which  at  due to  threshold voltage  the  on each set  of  the  measured  ensure  that  techniques  as  source  fabricated  with  the were  method, the threshold drain  pads  the threshold  voltage  pressure.  voltage  was  of  Array  2.5  devices  volts  applied  MESFETs  were  used  determine  to  voltage  current was  was  was  measured.  between  operating the  defined as  5 M A with  2.5  volts  in  the the  threshold the gate applied  64  between  the  drain  and  source current versus was  defined  as  at  zero  gate  is  the  drain  Both the  and  volts  current  was  also  the threshold voltage HP9816  before the  To samples  corresponding Cominco  to to  the  at  a  line  etched  trial  gate  between  the  was  in  The  was  runs  molten  KOH  molten  first  placed  using  etch  time  registration (figure  marks  4.5).  MESFETs  These  on  MESFET  obtained  the  features  were  taken  and the nearest  using  ohmic were  micro-photographs  micro-photographs the  metallisation and  the  and  s s  (I^gg  the  second  source  pads.  program  of  used  is  about  at  was  gate  used  5  taken 100X  micro-photographs.  pits at  etch  of  KOH  placing  sample  was  2  by  the  etch  are  still  clearly  deduce  of  amount  H 0.  the  the  pit  from a 200/im x 200|xm square area centred on the  location  MESFET  and the etch pit  The  done  it with a lid and  magnification. The  dislocation  etch  was  minutes, the  pads  to  etch  samples)  removed  and  reveal  in a nickel crucible, then a  dummy  of  to  KOH  removed from the oven, cooled and rinsed in Dl MESFET  drain  /I^  voltage In  here  A.  an  The  gate  measured. The  it  an  through  voltage).  were placed in the crucible before covering oven. After  drawn  appropriate  beads in  drain  device characteristics with dislocations, the  dislocations.  (from  the zero  transistor  in Trail. The sample  pre-determined  at  in appendix  be  root  assumed. The threshold voltage  applied  correlate the measured have  square  were computed and stored onto the hard disk  next  similar to the one given  method, a  intercept of  O-Vl^gg  source  second  was  zero current  voltage  technique, 2.5  the  gate voltage  the  to  source. In  but  the  outlined of  array.  the The  distance  between  densities  were all  density MESFET.  was  calculated  65  Figure 4.5: Micro-photograph  Of Etched Sample  With Registration  Marks  Left  Behind 4.4 RESULTS The  AND  slice  DISCUSSIONS tested,  Cominco  Limited.  MESFETs  fabricated  radius columns two  quadrant,  Its  429s122G,  position  have  over-etched  were by  from  the wafer  on the sample, which gates  of transistors, about  columns  on  is  included  Cominco.  is  perpendicular  to  wafer is  as  Three  study other  depicted  roughly the  800 in number, were in this  429s122  because samples  by  in figure 4.6.  the size  major  supplied  of  <110>  a 1.7cm flat.  10  measured. However, only the sample sent  to  was  Cominco  slightly were  66  completely hexagonal same  is  making  or  of a  leave  The  locations a  of  the  'ghost* of  is  the  trace  KOH  etch meet  devices  behind  of  original  the  to pin point their original  148 devices  the devices were not  non-existent  molten  where dislocations  o v e r - e t c h e d , no  Figure 4.7. At which  at  it impossible Out  rest  pits  time  sample  over-etched.  gate.  saturation  A  used  in this  tested  typical  drain source  ideal in M E S F E T s .  4.5). But, when  devices  is  for the same  left  behind  were  functional. The  of  poor  gate  characteristic  definition  is  shown  voltages, the drain current is  Shown in figure 4.8 are I .  and / I . versus  a  PRIMARY  429s122G  Figure 4.6: Position O f  FLAT  Sample  429s 122G O n  Wafer  in  constant V  g  transistor.  SECONDARY  a  141  a curves  reveal  position.  study,  l-V  ideally  the surface, and at the (figure  either because MESFET  should  FLAT  67  ID  (UA)  500.0.  50.00 /div  .0000 .0000  ,5000/div  VDS  Figure 4.7; Typical MESFET  The of  threshold  ways. Two  uniformity  voltage  techniques  of V ^  Vg  curve  versus  Vg  curves  those  of V ^ j ^ ,  -1.86  volts. The  t  [83],  n  transistors  commonly  used  Characteristics  can by  be  determined in a  number  experimenters working  on the  were investigated. The first,  f c  versus  of  l-V  and  [87]. V ^ e  average  standard  the  second,  values  a  of  were  the former  deviations  of  was  V^^, found is  V^^  a  5.000  ( V)  was to  -1.71  based on the  obtained be  volts  less  0.19 volt respectively. In the saturation region, 1^, can be written  as:  from  negative  and the  and V ^ ^ j ^ are  1^  0.18  than  latter volt  is and  68  Figure 4.8: l  J  where  d  s  K  (  and  d  v  Versus  g ' th v  K=MeW/(2aL)  permittivity,  the  )  n,  e,  width,  the  is  used  they  can be  now  seen  histogram  on  Of  because  W,  the threshold voltage  and length  theoretically  distribution is was  L  gate  gave  in figure 4.9. Furthermore,  of  The Same M E S F E T  In Figure 4.7  ( 4  respectively. Although, from  g  2  with  gate  V  given  obtained.  a  a  as  and  the the  correct,  good is  1 )  mobility, channel values  approximation  to  computationally  in figure 4.10. G o o d  -  depth will  v  the  *. b  be a  s  n  simpler.  A  distribution of  Figure 4.9: Plot Of V  t h g  Versus  V  t h b  CO  Figure 4.10: Histogram Of Threshold  Voltage  X 4  I 8  1  '  "  '  I 12  1  1  '  '  I  •  -  16  Dislocation Density [ x10 etch pits cm' ] 4  1  Figure 4.11: Dislocation Density Versus Threshold Voltage  20  -1  X  X  X  X  X  X X  *  X  n  X X X  -2-  -2.5  I 10  •  I 20  '  I 30  1  I 40  1  I 50  Distance To Nearest Dislocation [ jttm ]  Figure 4.12: Threshold Voltage Versus Nearest Distance T o A  Dislocation  60  73  A appears greater  plot  of  dislocation  density  from the plot that than  and  is lower  1.3 x 10 per c m . Below s  drop  more  per  number  of  MESFETs, this  1.3  x  10  MESFETs  a plot  pointed  point  out  with dislocation  dislocation  2  is  density  probably  regions.  to the nearest  no definitive  in regions  due  From  density  to  the  the  same  and V ^ was also  with small  set  of  obtained and  no evidence of any effect  distance  V.. . th  in  in et  surrounding of  Miyazawa was  dislocation  to to  figure  to  be  dislocation  influence,  lower  density  V ^ variation. Since  on  in  found  are obtained  no correlation  a  dislocation.  The plot  of  a  dislocation  obtained  by  4.13. This  within  is  in  the existence  which  commonly  known  also observed by Chin et al. [62] using  Winston  is as  of  a  with  sinks  dopants. MESFET  voltage  the  20-30/um  Cottrell  directly  in the vicinity  et  algebraically the  is  act as  between  threshold  disagreement  dislocation  regions  dislocations  threshold  et al. [87].  high  in the higher activation of implanted  al. [85]. He found pits,  density  et al. [83] and Winston  found  high  et al. [87] also  etch  of  and impurities, purer regions  resulting  distance  reproduced  cylinder  of  activation  proximity  Miyazawa  those  influence  before, V ^  defects  Winston  nearest  the  for the observed  dislocations  its  on  with  Better  reponsible  and  those  has on MESFET  results  agree  regions.  of  in  cm  4.11. It  DISCUSSIONS  voltage  for  available  in figure  in threshold voltage  is depicted in figure 4.12. It shows  Our  As  pits  of distance  from a dislocation  4.5  etch  5  shown  in regions  this  1  trend can be detected. The abrupt than  is  al.  versus [87]  results radius  lower.  is of  area  Such  atmosphere,  cathodoluminescence.  V ^  a  was  74  -0.6  >"°  7  UJ  «-0J r-  •  *  ! !  i I  •  V •-e 7«e v n • i-»>  L i !  t  o  I-OB |-o.»  r v « i >v  Ii!  -1.0  10  »  !  I  SO  40  80  60  70  SO  SO 100  GATE-INT DISTANCE. «m  Figure 4.13: Plot  Of  MESFET  Threshold Voltage  Obtained By Winston It V ^ is  has  and  its  obtained  dislocation have  MESFET  proximity for  a  2"  to  nearest  wafer  etch  an  [87].  pit  can  be obtained when  Since  distances.  Dislocation  correlation between  is  more  This  in the case  means  that  such  negative  inevitable that algebraically  a localised area, such as V.,  To A  et al. [87]  erroneous  a dislocation  density regions, it is  smaller  done for  been suggested that  Proximity  MESFET a  plot  at  high  lower V ^  will  when  a  plot  is  here, no correlation between  and its proximity to a dislocation should be obtained.  75  To higher  summarise, MESFETs  than  area, M E S F E T on  its  th-  x  10  5  per  proximity to  electrical  statement V  1.3  cm  fabricated in regions with 2  appear  to  have  a dislocation was  not  lower  on the effects of  In  found to  characteristics. Unfortunately, from  can be made  dislocation  the  a  have  data  dislocation networks  density localised  any effect  available, on  no  MESFETs  5. CONCLUSION AND The the  aim  surface  of  layer  2fxm  of  first the  thesis  and  characteristics of The  this  S U G G E S T I O N S FOR FUTURE WORK  also  was  the  to  influence  ion implanted G a A s part  top  of  this  layer  work  of  study of  of  dislocations  the removal  of  on  the  electrical  of  approximately  MESFETs.  found  the  the effects  that the removal  starting  substrate  supplied  by  Cominco  resulted in: 1. A  higher activation efficiency in the  2. Improved transistor current, transconductance threshold voltage 3.  An  and  was  4. Less  was  all  layer  lower  with  from drift  the  in  magnitude  better  electron  effect when  results  mobility  probably due to poor  backgating  increased  voltage  saturation while  the  negative.  concluded  measurements. The  measurements  K-factor  implanted  characteristics. This K-factor  characteristics. The zero gate  became more ion  implant.  of  Hall  mobility  obtained from  Schottky  MESFETs  transport  the  and  FATFET  diode characteristics. in  approximately  the  same  location on the sample were compared. Clearly, a after  a  more surface  surface (as In  suitable  substrate  removal.  However,  confirmed by the poor  the  second  part  of  investigated and the following 1. MESFETs  It  this  direct the  etch  Schottky work,  findings  ion  left  behind  effects  dislocation  density  affects  in regions  with  dislocation  density  larger  influence on MESFET  to  a  desirable  of  dislocations  were  device  than  characteristics.  1.3 x  10  per  cm  have  any  5  2  voltage.  dislocation  threshold  less  made:  that  Proximity  obtained  diode characteristics).  the  were  implantation was  appears  have more negative threshold 2.  for  centre  voltage.  76  was  not  found  to  77  Unfortunately, dislocation  it  is  not  networks  known  from  the  results  have  any  effect  on  for  this  thesis  suggests  the  of  scatter  this of  section MESFET  whether threshold  voltage. The directed  work  in the following  1. Cominco's growers  done  the  wafer  resulted  procedures  are  also  efforts  would  be  best  top  layer  areas:  Although  should  that  removal  be  used. The  in  of  a  better  studied  2nm  approximately  substrate, wafers  because  possibility  of  different  exists  that  from  growth  such  an  other and  etch  of  crystal  polishing  may  not  be  necessary. 2. The  surface  before  and  after  impurities and surface damage using spectroscopy 3. T o x  the  etch should  such techniques as  (SIMS) and Auger  electron spectroscopy  study  of  10* etch pits  the effects  per  cm  2  should  dislocation be  used  be  investigated  secondary  mass  (AES).  networks, substrates  because  ion  for  dislocation  with  1-5  networks  are  more clearly defined. 4. The dose  effects  and energy 5.  Also,  of  dislocations  should  be  investigated  with  different  implants. for  further  work  an  reduce the time required to measure the  automatic MESFETs.  prober  would  drastically  REFERENCES  1.  A . E. Pyne and P. C. ICs," Gallium Arsenide Phys. ] pp. 7-12, 1984.  Newman," The commercial prospects of G a A s and Related Compounds [ Conf. Ser.-lnst.  2.  J . V. Dilorenzo, A . S. Jordan, A. R. Von Neida and P, O'Connor, "Substrate Quality: How Important for Future GaAs ICs?," Semi-insulating III—V Materials, pp. 308-334, Warms Springs, Oregon, 1984.  3.  D. C. Look, P. W. Yu, J . E. Ehret. Y. K. Yeo, and R. Kwor, "A Detailed Si G a A s Substrate Study: Conversion and M E S F E T Properties," Semi-Insulating l l l - V Materials, pp. 372-374, Nottingham, 1982.  4.  G. M. Martin, J . P. Farges, G. Jacob, and "Compensation Mechanism in GaAs," J . A p p l . Phys., pp. 2840-2852, 1980.  5.  R. E. Williams, Gallium Arsenide Processing House Inc., Dedham, Ma., 1984.  6.  R. Zuleeg, "Is G a A s Ready No. 4, pp. 263-265, 1984.  7.  Y. Nanishi, S. Ishida, S. Miyasawa, "Characterisation of Semi-Insulating G a A s Substrates for G a A s ICs," Rev. of the Electrical C o m m . Laboratories, V o l . 33, No. 1, 1985.  8.  R. L. Van Tuyl and C. GaAs MESFETs," IEEE pp. 269-273, 1974.  9.  K. Terashima, T. Katsumata, F. Orito, and T. Fukuda, "Veritcal Magnetic Field Applied LEC Apparatus for Large Diameter Growth," Jpn. J . A p p l . Phys., Vol. 23, No. 5, pp. L302-L304, 1984.  10.  M . Puseaux and S. Martin, "Growth and Characterisation of Large Dislocation-Free G a A s Crystals for Integrated Circuits Applications," Semi-Insulating l l l - V Materials, pp. 118-125, Warms Springs, Oregon, 1984.  11.  P. F. Lindquist and W. M . Ford, "Semi-Insulating GaAs Substrates," G a A s FET Principles and Technology. J . V. Dilorenzo ed., pp. 5-114, Artec house, Wahshington, 1982.  12.  R. N. Thomas, H. M . Hobgood, G. W. Elridge, P. L. Barret, L. B. T a , and S. K. Wang, "High-Purity LEC Growth and Direct Implantation of G a A s Monolithic Microwave Circuits," Semiconductors and Semimetals, R. K. Willardson and A . C. Beer eds., V o l . 20, pp. 1-87, A c a d e m i c Press, New York, 1984.  For VLSI?,"  IE  J . P. Hallais, V o l . 51, No. 5,  Techniques, pp.  Aust. &  19, Artech  IREE Aust., V o l .  4,  L. Liechti, "High-speed Integrated Logic with J . Solid-State Circuits, Vol. S C - 9 . No. 5,  78  79  13.  A . M. Huber, G. Morillot and N. T. Linh, "Chromium Profiles in Semi-Insulating G a A S After Annealing with a S i N Encapsulant," A p p l . Phys. Lett., Vol. 34, No. 12, pp. 858-859, 1979. 3  4  14.  C. A. Evans Jr., V. R. Deline, T. W. Sigmon and A . Lidow, "Redistribution of Cr During Annealing of Se-implanted GaAs," A p p l . Phys. Lett., V o l . 35, No. 3, pp. 291-293, 1979.  15.  D. E. Holmes, R. T. Chen, K. R. Elliot, C. G. Kirkpatrick and P. W. Yu, "Compensation Mechanism in LEC G a A s : Importance of Melt Stoichiometry," IEEE Microwave Theory and Techniques, Vol. M T T - 3 0 , No. 7, pp. 949-954, 1982.  16.  S. Makram-Ebeid, P. Langlade and G. M. Martin, "Nature of EL2: the Main Native Midgap Electron Trap in VPE and Bulk GaAs,' Semi-Insulating l l l - V Materials, pp. 184-203, Warms Springs, Oregon, 1984.  17.  D. E. Holmes, K. R. Elliot, R. "Stoichiometry-Related Centres in Materials, S. Makram-Ebeid and Publishing, Nantwich, UK., 1982.  18.  J . Osaka, T. Kobayashi and H. Nakanishi, "Growth of Semi-Insulating G a A s Single Crystal by LEC Method," Rev. of the Electrical C o m m . Laboratories, V o l . 33, No. 1, pp. 146-155, 1985.  19.  H. Emori, T. Kikuta, T. Inada, T. Obokata and T. Fukuda, "Effect of Water Content of Bj0 Encapsulant on Semi-Insulating LEC GaAs Crystal," Jpn. J . A p p l . Phys., V o l . 24, No. 5, pp. 1291-1293, 1985.  T. Chen and C. G. Kirkpatrick, LEC GaAs," Semi-Insulating lll-V B. Tuck eds., pp. 19-27, Shiva  3  20.  R. N. Thomas, H. M. Hobgood, G. W. Elridge, D. L. Barrett and T. T. Braggins, "Growth and Characterisation of Large Diameter Undoped Semi-Insulating GaAs for Direct Ion Implanted FET Tehcnology," Solid-State Electron., V o l . 24, pp. 387-399, 1981.  21.  D. E. Holmes, R. T. and Undoped LEC pp. 419-421, 1983.  22.  G. M. Martin, G. J a c o b , G. Poliblaud, A. Goltzene, and C. Schwab, "Identification and Analysis of Near-Infrared Absorption Band in Undoped and Cr Doped Semi-Insulating GaAs Crystals," Gallium Arsenide and Related Compounds [ Conf. Ser.-lnst. Phys. ] pp. 281-286, 1980.  23.  C. A . Mead, "Schottky Barrier Gate IEEE, V o l . 54, pp. 307-308. 1966.  24.  W. W. Hooper and W. I. Lehrer, " A n Epitaxial GaAs Transistor," Proc. IEEE, V o l . 55, pp. 1237-1238, 1967.  Chen and J . Yang, "EL2 Distribution in Doped GaAs," Appl. Phys. Lett., V o l . 55, No. 10,  Field  Effect  Transistor,"  Proc.  Field-Effect  80  25.  K. C. Vaidyanathan, R. A . Jullens, C. L. Anderson, and H. I. Dunlap, "Planar Ion-implanted GaAs Bipolar Devices in GaAs," Solid-State Electron., V o l . 26, No. 78, pp. 717-721, 1983.  26.  H. Kroemer, "Heterostructure Bipolar Circuits," Proc. IEEE, V o l . 70, No. 1, pp.  27.  "GaAs  28.  R. Zucca, B. Welch, R. Eden, and S. Long, "GaAs Technology/Statistical Analysis of Device Performance,' Electron Devices, V o l . E D - 2 7 , No. 6, pp. 1109, 1980.  29.  R. Esfandiari, M. Feng, and H. Kanber, "Proton Implantation Isolation for Microwave Monolithic Circuits," IEEE Electron Devices Lett., Vol. E D L - 4 , No. 2, pp. 29-31, 1983.  30.  T. Onuma, A. Tamura, T. Uenoyama, H. Tsujii, K. Nishii, and H. Yagita, "High-Transconductance Enhancement-Mode GaAs MESFET Fabrication Technology," IEEE Electron Devices Lett., V o l . E D L - 4 , No. 11, pp. 409-411, 1983.  31.  K. Yamasaki, T. Mizutani, and N. Kato, "GaAs Technology: SAINT," Rev. of the Electrical V o l . 33, No. 1, pp. 122-129, 1985.  32.  R. A . Sadler and L. F. Eastman, "High-Speed Logic Self-aligned Submicrometer-Gate GaAs MESFET's," Devices Lett., V o l . E D L - 4 , No. 7, pp. 215-217, 1983.  33.  D. A . A l l a n , "Stability of Schottky Barriers at High Temperatures for Use in G a A s M E S F E T Technology,' IEE Proceedings, V o l . 133, Pt. I, No. 1, pp. 18-48, 1986.  34.  J . Lindhard, M. Scharff, and H. Heavy Ions Ranges," Mat. Fys. pp. 1-42, 1963.  35.  J . F. Gibbons, W. S. Statistics. 2nd ed., Pennsylvania, 1975.  36.  S. Furukawa, H. Matsumura, Considerations on Lateral Spread Phys., No. 11, pp. 134-142, 1972.  37.  C. P. Lee, "Influence of Substrates GaAs FET Devices and Integrated Materials, S. Makrurn-Ebeid and B. publishing, Nantwick, UK., 1982.  IC  Symposium,"  Transistors 13-25, 1982.  and  Integrated  Monterey, California, 1985. Digital IC IEEE Trans.  Self-Aligned MESFET Comm. Laboratories,  at 300K with IEEE Electron  E. Schiolt, "Range Concepts and Medd. Dan. Vid. selsk., V o l . 33,  Johnson, and S. W. Dowden, Hutchison  Mylroie, Projected Range and Ross, Stroudburg,  and H. Ishiwara, of Implanted Ions,"  "Theoretical Jpn. J . A p p l .  on the Electrical Properties of Circuits," Semi-Insulating lll-V Tuck eds., pp. 324-335, Shiva  81  38.  J . Kasahara, Y. Kato, Impurites in GaAs," pp. 2275-2279, 1983.  M. Arai, and N. J. Electrochem.  39.  J . Narayan and O. W. Holland, Ion-Implanted Semiconductors," J. pp. 2913-2921, 1984.  40.  M. H. Badawi and J . Mun, "Halogen Lamp Annealing MESFET Fabrication," Electron. Lett., V o l . 20, No. 3, pp.  41.  D. Allan and S. C. Thorp, T h e Characteristics of GaAs NiAuGe Contact A l l o y with an S i 0 Overlayer for Use in an Ion Implanted MESFET Technology," Physica, No. 1298, pp. 445-449, 1985.  "Rapid Appl.  Watanabe, "Ion Soc., V o l . 130,  Implanted No. 11,  Thermal Annealing Phys., V o l . 56, No.  of 10,  of G a A s for 125-126, 1984.  2  42.  S. M. Sze, Physics of Semiconductor John Wiley & Sons, New York, 1981.  Devices,  pp.  245-361, 2nd  ed.,  43.  W. T. Anderson, Jr., A. Christou and J . E. Davey, "Development of Ohmic Contacts for G a A s Devices Using Epitaxial GE Films,' IEEE J . S o l i d - S t a t e Circuits, V o l . S C - 1 3 , No. 4, pp. 430-435, 1978.  44.  R. C. Eden and E. M. Welch, "Ultra high speed GaAs VLSI: Approaches, Potential and Progress," VLSI Electronics: Microstructure Science. N. Einspruch ed., pp. 109-162, Vol. 3, Academic Press, New York. 1981.  45.  S. Dzioba, C. Miner, T. Lester and B. MacLaurin, "Evaluation of Etched (100) GaAs," 167th Meeting Of The Electrochemical Society, Toronto, Ontario, 1985.  46.  M . Oshima, K. Watanabe and S. Miyazawa, "Chromium and Manganese Redistribution in Semi-Insulating GaAs," J . Electrochem. Soc., V o l . 131, No. 1, pp. 130-135, 1984.  47.  W. Kern "Chemical Etching of Silicon, Germanium, Gallium Arsenide, and Gallium Phosphate," R C A Review, V o l . 39, pp. 278-308, 1978.  48.  T . H. Miers, "Schottky Contact Fabrication for G a A s MESFETs," Electrochem. Soc., V o l . 129, No. 8. pp. 1795-1799, 1982.  49.  A . Immoriica, Jr., D. Decker and W. Hill, "A Diagnostic Pattern for G a A s FET Material Development and Process Monitoring," IEEE Trans. Electron Devices, V o l . E D - 2 7 , No. 12. pp. 2285-2291, 1980.  50.  R. A . Pucel and C. F. Krumm, "Simple Method of Measuring Drift Mobility Profiles in Thin Semiconductor Films," Electron. Lett., V o l . 12, No. 10, pp. 240-242, 1976.  51.  L. J . van der Pauw, "A Method of Measuring Specific Resistivity and Hall Effect of Discs of Arbitrary Shape," Philips Res. Repts., V o l . 13, No. 1, pp. 1-9, 1958.  J.  82  52.  K. Lee, M. Shur, K. Lee, T. Vu, P. Roberts and M . Helix, "Low Field Mobility in G a A s Ion-Implanted FETs," IEEE Trans. Electron Devices, V o l . E D - 3 1 , No. 3, pp. 390-393, 1984.  53.  R. H. Wallis and P. R. Jay, "Deep Levels and Electron Mobility Near the Active Layer-Substrate Interface in GaAs MESFETs," Semi-Insulating lll-V Materials, S. Makram-Ebeid and B. Tuck eds., pp. 344-351, Shiva Publishing, Nantwick, UK., 1982.  54.  T. Itoh and H. Yanai, "Experimental Investigations of Interface Traps in G a A s Planar Devices by DLTS and PITs Methods," Gallium Arsenide and Related Compounds [ Conf. Ser.-lnst. Phys. ] pp. 537-545, 1980.  55.  A . Zylbersztejn, G. Bert and G. Nuillat, "Hole Traps and their Effects in G a A s M E S F E T s " , Gallium Arsenide and Related Compounds [ Conf. Ser.-lnst. Phys. ] pp. 315-325, 1980.  56.  C. P. Lee, S. J . Lee, and B. M. Welch, Backgating Effect in G a A s MESFETs," IEEE V o l . E D L - 3 , No. 4, pp. 97-98, 1982.  57.  H. Tranduc, P. Rossel, J . Graffeuil, C. A z i z i , G. Nuzillat, and G. Bert, "Substrate and Interface Effects in G a A s FETs," Revue De Physique Appliquee, V o l . 13, pp. 655-659, 1978.  58.  D. C. D'Avanzo, "Proton Isolation for G a A s Integrated circuits," IEEE Microwave Theory and Techniques, V o l . M T T - 3 0 , No. 70, pp. 955-962, 1982.  59.  A. Blum and L. Flesner, "Use of a Surrounding p-Type Ring to Decrease Backgate Biasing in G a A s MESFETs," IEEE Electron Devices Lett., V o l . EDL-6, No. 2, pp. 97-99, 1985.  60.  C. P. Lee and M. F. Chang, "Shielding of Backgating Effects in G a A s Integrated Circuits," IEEE Electron Devices Lett., V o l . E D L - 6 , No. 4, pp. 169-171, 1985.  61.  Y. Tokumaru and Y. Okada, "SEM-EBIC Investigations Semi-Insulating Undoped LEC-GaAs," Jpn. J . A p p l . Phys., V o l . No. 5, pp. L364-L366, 1985.  62.  A . K. Chin, A . R. Von Neida Cathodoluminescence Study of Electrochem. Soc., V o l . 129. No.  63.  W. Heinke and H. J . Queisser, "Photoluminescence at Dislocation GaAs," Phys. Rev. Lett., V o l . 33, No. 18, pp. 1082-1084, 1974.  64.  T. Matsumura, T . Obokata and T. Fukuda, Microscopic Uniformity in Semi-Insulating GaAs," V o l . 57, No. 4, pp. 1182-1185, 1985.  "Carrier Electron  Injection Devices  and Lett.,  of 24,  and R. Caruso, "Spatially Resolved Semi-Insulating GaAs Substrates," J . 10, pp. 2386-2388, 1983. in  Two-Dimensional J . Appl. Phys.,  83  65.  M . Brozel, I. Grant, R. Ware and D. Stirland, "Direct Observation of the Principal Deep Level (EL2) in Undoped Semi-Insulating GaAs," Appl. Phys. Lett., V o l . 42, No. 7, pp. 610-612, 1983.  66.  P. Petroff and R. L. Hartman, "Defect Structure Introduced During Operation of Heterojunction G a A s Lasers," A p p l . Phys. Lett., V o l . 23, No. 8, pp. 469, 1973.  67.  T. Honda, Y. Ishii, S. Miyazawa, H. Yamazaki, and Y. Nanishi, "The Influence of Dislocation Density on the Uniformity of Electrical Properties of Si implanted L E C - G a A s , " Jpn. J . A p p l . Phys., vol. 22, no. 5, pp. L270-L272, 1983.  68.  R. Lee, A . Hunter, R. Bryan, H. Olsen, H. Winston and R. Beaubien, "Threshold Uniformity of M E S F E T s Fabricated on G a A s and In-alloyed GaAs substrates," 1984 GaAs IC Symposium's Technical Digest, pp. 45-48, IEEE Publishing Services, New York, 1984.  69.  S. Miyazawa, Y. Ishii, S. Ishida and Y. Nanishi, "Direct Observation of Dislocation Efffects on Threshold Voltage of a G a A s Field Effect Transistor," A p p l . Phys. Lett., V o l . 43, No. 9, pp. 853-855, 1983.  70.  Y. Ishii, S. Miyazawa and S. Ishida, "Threshold Voltage Scattering of G a A s M E S F E T s Fabricated on L E C - G r o w n Semi-Insulating Substrates," IEEE Trans. Electron Devices, V o l . ED-31, No. 6, pp. 800-804, 1984.  71.  R. Blunt, S. Clark and D. Stirland, "Dislocation Density Resistance Variation A c r o s s Semi-Insulating G a A s Wafers," Electron Devices, V o l . E D - 2 9 , No. 7, pp. 1039-1044, 1982.  72.  M . Abrahams and C. J . Buiocchi, "Dislocations and Precipitates in G a A s Injection Lasers," J . A p p l . Phys., V o l . 37, No. 5, pp. 1973, 1966.  73.  J . Angilello, R. Potemski Dislocations in (100) G a A s pp. 2315, 1975.  74.  A . Jordan, R. Caruso and A . Von Neida, "A Thermoelastic Analysis Of Dislocation Generation In Pulled G a A s Crystals," The Bell System Tech. Journal, V o l . 59, No. 4, pp. 594-617, 1980.  75.  A . H. Cottrell, Dislocation A n d Plastic Oxford University Press, London, 1953.  76.  J . Osaka, H. Kohda, T. Koyabashi and K. Hoshikawa, "Homogeneity of Vertical Magnetic Field Applied LEC G a A s Crystal," Jpn. J . Appl. Phys., V o l . 23, No. 4, pp. L195-L197, 1984.  77.  T. Shimada, T. Obokata and T. Fukuda, Characteristics of Undoped Semi-Insulating Dislocation Density," Jpn. J. Appl. pp. L441-L444, 1984.  and G. Woolhouse, "Etch Wafers," J . A p p l . Phys., V o l .  Flow  In  and IEEE  Sheet Trans.  Pits on 46, No. 5,  Crystals.  1st  ed.,  "Growth and Resistivity G a A s Crystals with Low Phys., V o l . 23, No. 7,  84  78.  M . Brozel, I Grant, R. Ware, D. Stirland and M. Skolnick, "Direct Observation of Fine Structure in the Concentration of the Deep Donor [EL2] and its Correlation with Dislocation in Undoped Semi-Insulating GaAs," J . Appl. Phys., V o l . 56, No. 4, pp. 1109-1118, 1984.  79.  T. Matsumura, H. Emori, K. Terashima and T. Fukuda, "Resistivity, Hall Mobility and Leakage Current Variations in Undoped Semi-Insulating G a A s Crystal Grown by LEC Method," Jpn. J . A p p l . Phys., Vol. 22, No. 3, pp. 154-156, 1983.  80.  M . Tajima, "Characterisation of Nonuniformity GaAs by Photoluminescence Spectroscopy," Vol. 21, No. 4, pp. L227-L229, 1982.  81.  D. Rumsby, I. Grant, M. Brozel, E. Foulkes and R. Behavior of Annealed LEC GaAs," Semi-Insulating pp. 165-171, Warms Springs, Oregon, 1984.  82.  A . K. Chin, I. Camlibel, R. Caruso, M. Young and A. Von Neida, "Effects of Thermal Annealing on Semi-Insulating undoped GaAs Grown By the LEC Technique," J . A p p l . Phys., V o l . 57, No. 6, pp. 2203-2209, 1985.  83.  S. Miyazawa and Y. Nanishi, "Characteristics Of Semi-Insulating G a A s Substrates for G a A s ICs," Jpn. J . A p p l . Phys., V o l . 22, Supplement 2 2 - 1 , pp. 419-429, 1983.  84.  F - C . Wang and M. Bujatti, "Experimental Correlation Between Substrate Properties and G a A s M E S F E T Transconductance," IEEE Electron Devices Lett., V o l . E D L - 5 , No. 6, pp. 188-190, 1984.  85.  S. Miyazawa and F. Hyuga, "Proximity Effects Of Dislocations on GaAs MESFET Threshold Voltage," IEEE Trans. Electron Devices, V o l . ED,-33, No. 2, pp. 227-232, 1986.  86.  Y. Nanishi, H. Yamazaki, T. Mizutani and S. Miyazawa, "Characterisation of L E C - G r o w n Semi-Insulating G a A s for Integrated Circuits Applications," Gallium Arsenide and Related Compounds [ Conf. Ser.-lnst. Phys. ] pp. 7-12, 1981.  87.  H. Winston, A . Hunter, H. Olsen, R. Bryan E f f e c t s on the Threshold Voltage of G a A s A p p l . Phys. Lett., V o l . 45, No. 4, 1984.  88.  F. Hyuga, H. Kohda, H Nanishi, T. Kobayashi and K. Hoshikawa, "Electrical Uniformity for Si-Implanted Layer of Completely Dislocation-free and Straition Free GaAs," A p p l . Phys. Lett., V o l . 47, No. 6, pp. 620-622, 1985.  89.  P. Dobrilla and J . Blackmore, " G a A s Field Effect Transistor Properties, as Influenced by the Local Concentration of Midgap Native Donors and Dislocations," A p p l . Phys. Lett., V o l . 47, No. 6, pp. 602-604, 1985.  in Semi-Insulating LEC Jpn. J . A p p l . Phys.,  Ware, lll-V  "Electrical Materials,  and R. Lee, "Substrate Field Effect Transistor,"  85  90.  A . Tamura and T. Onuma, "Experimental Correlation Between EPD and Electrical Properties in Undoped LEC A s - G r o w n Semi-Insulating G a A s Crystals," Jpn. J . A p p l . Phys., V o l . 24, No. 4, pp. 510-511. 1985.  91.  W. Tang, "Semi-Insulating Gallium A r s e n i d e - Deep Trapping Levels, Dislocations and Backgating," M . A . Sc. Thesis, UJ3.C, pp. 38-67, 1984.  92.  J . Kasahara, H. Sakurai, T. Suzuki, M . Arai and N. Watanabe, "The Effects of Channeling on LSI-Grade Uniformity of G a A s - F E T s By Ion Implantation," 1985 G a A s IC Symposium's Technical Digest, pp. 37-40, IEEE Publishing Services, New York, 1985.  93.  F. Eisen, C. Kirkpatrick and A. Asback, "Implantation Into G a A s FET Principles and Technology. J . DiLorenzo, ed., Artec Washington, 1982.  GaAs," House,  94.  I. M . A b d e l - M o t a l e b , "GaAs M E S F E T s and their Applications in Logic and Digital to Analog Conversion," Ph. D. Thesis, pp. 45-58, 1985.  Digital U.B.C.,  95.  A . Fathimulla, "Single-step L i f t - o f f Process Using Chlorobenzene Soak On AZ4000 Resists," J . Vac. S c i . Technol. V o l . B3, No. 4, pp. 25-27, 1985.  APPENDIX  A  16 I SET MASS ST0RA6E UNIT TO HARD DISK. 20 MASS STORAGE IS •:HP9133,700" 30 Dill CurH253.lnttn.K3I >,Ieqrt(31 ), Idas! 100 >,Vtha( 100 >,Vthb( 100 ) ,6n(100),File1«[101,File2SI101,File3(I10],File4«[10] 40 1NTE6ER M,J,K 50 REAL V1.V2.U 60 L_vel—9.9999 70 t SEMICONDUCTOR PARAMETER ANALYSER IS ON INTERFACE SELECT CODE 7 B0 ! AT PRIMARY ADDRESS 17. 90 Spe-717 100 P-31 110 INPUT "ENTER THE DATA FILE NUMBER",H 120 Filel«-"F_VTHA"*VAL«(M> 130 File2«-"F_VTHB"1VAL»(M) 140 File3S-"F_IDSS"lVAL»(M) 150 File4t-"F_TRAN"&VAL«(M> 160 CREATE BOAT Filel»,4 170 CREATE BOAT File2«,4 180 CREATE BDAT File3C,4 190 CREATE BOAT File4t,4 200 I OPEN DATA PATH TO FILES. 210 ASSI6N »Path_l TO Filelt 220 ASSI6N ePath_2 TO File2» 230 ASSI6N »Peth_3 TO FU«3* 240 ASSI6N «Path_4 TO File4» 250 K-0 260 Measure=J"0 270 t SET SPA TO USER MODE. 280 OUTPUT Spa;"US" 290 I SET MEASUREMENT INTE6RATI0N TIME (IT2>. AUTO CALIBRATION (CAl), 300 ( AND BUFFER CLEAR. 310 OUTPUT Spa;"IT2 CAl BC" 320 ) SCAN 6ATE V0LTA6E FROM -2.5V TO .5V USING A STEP OF .IV. 330 FOR Vos—25 TO 5 STEP 1 340 Vl-Vgs/10 350 • CONNECT SOURCE TO SMU1. DRAIN TO SMU2 AND 6ATE TO SMU3. 360 OUTPUT Spa."DVl,l.e,2E-3" 370 OUTPUT Spa;"OV2,1,2.5,2E-2" 380 OUTPUT Spai'DVS.l.'iVli'.lE-S" 390 I TR166ER CURRENT MEASUREMENT OF SMU2. 4C0 OUTPUT Spe;"TI2" 410 1 ENTER MEASUREMENT DATA INTO THE STRING. CUR«. 420 ENTER Spa:Curt 430 PRINT J,Curt 440 I CHECK TO SEE IF THE MEASUREMENT IS NORMAL. 450 IF CurSIl.UO'N" THEN 460 BEEP 470 60T0 Problem 480 ELSE  86  87  490 J-J+l 500 I TAKE VALUE OF NORMAL STRING. 510 KJ>«VAL<Cur«[43> 520 END IF 530 NEXT Vgs 540 I CHECK CHANNEL BY MONITORING LAST POINT OF CURRENT ARRAY. 550 IF KPK-5.E-E THEN 560 60TO Channel 570 END IF 580 ! CHECK 6ATE BY MDNIT0RIN6 FIRST POINT OF CURRENT ARRAY. 590 IF 1(1 )>-5.E-E THEN E00 GOTO 6ate 510 ELSE B20 K-K+l 630 I CALCULATE THE THRESHOLD V0LTA6E USING THE FIRST METHOD. IT IS 640 ! THE 6ATE VOLTAGE UALUE WHEN THE DRAIN CURRENT IS 5.E-B. B50 FOR J-l TO P 6B0 IF I(J)>-5.E-E THEN 670 60TO Uoltl 680 ELSE 690 60T0 Nextl 700 END IF 710 Next 1:NEXT J 720 Uoltl :Vthe(K )—2.5+.1»< J-l >-. 1»< (I< J >-S.E-6 )/(I< J >-I< J-l )>) 730 END IF 740 ! STORE DRAIN CURRENT UHEN GATE VOLTAGE IS BU.(IDSS) 750 IdssCK )-I(2E ) 7B0 I CALCULATE THE TRANSCONOUCTANCE (ITS UNIT IS IN MS/MM) 770 I AND STORE INTO ARRAY. 780 6«< K >-< I (27 )-I < 2S > >»7.143E+S 790 ! TAKE THE SQUARE ROOT OF THE DRAIN CURRENT UALUES. B00 FOR J-l TO P 610 I»qrt<J>-SQR(KJ>> 820 PRINT J.Iaqrt(J) 830 NEXT J 840 I CALCULATE THE THRSHOLD VOLTAGE USING THE SECOND METHOD. 850 ! IT IS THE X-INTERCEPT VALUE OF THE LINE PASSIN6 THROUGH 860 t SQUARE ROOT IDSS AND .1•{SQUARE ROOT IDSS) IN THE SQUARE 870 I ROOT ID VERSUS VGS PLOT. 880 Il-SQR(Idss(K>> 890 FOR J-l TO P 900 IF Isqrt(J )>-.1»I1 THEN 910 60T0 Volt2 920 ELSE 930 60TO Next2 940 END IF 950 Next2 NEXT J 9G0 Volt2:v2—2.S+.1«( J-l >-.l*((Iaqrt( J)-.1«I1 ))/(Iaqrt( J)-I»qrt< J-l )> 970 PRINT V2 ;  88  980 Vthb<K >-V2/.9 990 Question=DISP "DEVICE t IS",K 1000 PAUSE 1010 LINPUT "ARE THERE ANYMORE MEASUREMENTS TO BE TAKEN' Y OR N",In* 1620 IF In*-"Y" THEN 1030 SOTO Measure 1040 ELSE 1050 IF In»-"N" THEN 1060 60T0 Finish 1070 ELSE 1080 SOTO Question 1090 END IF 1100 END IF 1110 Channel^OISP 'POOR OR NO CHANNEL" 1120 PAUSE 1130 60T0 Large.vel 1140 Sate^DJSP 'POOR 6ATE OR VTH < -2.5 VOLTS" 1150 PAUSE 1150 60T0 Laree_vel 1170 Problei-rOISP "ERROR IN MEASUREMENT" 1190 PAUSE 1190 ! STORE LARGE VALUES INTO ARRAYS IF MEASUREMENT CANNDT 1200 I BE DONE. 1210 Lar e_vel-K-K+1 1220 VthalK )-L_val 1230 VthbtK )-L_val 1240 Idss(K )-L_val 1250 6n(K>-L_val 1260 SOTO Question 1270 Finish^DISP "THE t OF DEVICES MEASURED IS",K 12B0 ! STORE ,K, THE • OF DEVICES MEASURED INTO ALL THE 1290 ! FILES. 1300 OUTPUT ePath_l;K 1310 OUTPUT »Path_2;K 1320 OUTPUT #Path_3;K 1330 OUTPUT •Path_4;K 1340 t STORE DATA ARRAYS INTO THEIR RESPECTIVE FILES. 1350 OUTPUT tPath_l;Vtha<• ) 13S0 OUTPUT •Peth_2;Vthb<« ) 1370 OUTPUT fPath_3;Idss(• ) 1380 OUTPUT #Path_4;6m(• ) 1390 1 STOP OUTPUT FROM SMU1, SMU2 AND SMU3. 1400 OUTPUT Spe."DV1;DV2;DV3" 1410 ! CLOSE DATA PATH TO THE FILES. 1420 ASS16N ePath_l TO • 1430 ASSI6N »Peth_2 TO • 1440 ASS16N »Path_3 TO • 1450 ASSI6N #Path_4 TO • 1460 END 0  


Citation Scheme:


Citations by CSL (citeproc-js)

Usage Statistics



Customize your widget with the following options, then copy and paste the code below into the HTML of your page to embed this item in your website.
                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            async >
IIIF logo Our image viewer uses the IIIF 2.0 standard. To load this item in other compatible viewers, use this url:


Related Items