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Ion implanted GaAs Mesfet technology Lowe, Kerry Steven 1983

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ION IMPLANTED GaAs MESFET TECHNOLOGY by KERRY STEVEN LOWE B.A.Sc, The U n i v e r s i t y of B r i t i s h Columbia, 1981 A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE i n THE FACULTY OF GRADUATE STUDIES i n the Department of E l e c t r i c a l Engineering We accept t h i s t h e s i s as conforming to the required standard THE UNIVERSITY OF BRITISH COLUMBIA August 1983 ® Kerry Steven Lowe , 1983 In presenting t h i s thesis i n p a r t i a l f u l f i l m e n t of the requirements for an advanced degree at the University of B r i t i s h Columbia, I agree that the Library s h a l l make i t f r e e l y available for reference and study. I further agree that permission for extensive copying of t h i s thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. I t i s understood that copying or publication of t h i s thesis for f i n a n c i a l gain s h a l l not be allowed without my written permission. Department of E/ecfnca I Engineering The University of B r i t i s h Columbia 1956 Main Mall Vancouver, Canada V6T 1Y3 Date ABSTRACT The a v a i l a b i l i t y of high q u a l i t y s e m i - i n s u l a t i n g GaAs substrates i s e s s e n t i a l to the development of GaAs metal semiconductor f i e l d e f f e c t t r a n s i s t o r (MESFET) in t e g r a t e d c i r c u i t s . Problems have been encountered w i t h h o r i z o n t a l Bridgman grown substrates s i n c e , f o r example, these must be doped w i t h Cr to make then s e m i - i n s u l a t i n g and the Cr tends to d i f f u s e during device processing. Undoped s e m i - i n s u l a t i n g GaAs substrates can be grown by the L i q u i d Encapsulated C z o c h r a l s k i (LEC) technique and allow the p o s s i b i l i t y of forming a c t i v e regions by the process of implanting dopants d i r e c t l y i n t o the s u b s t r a t e . The purpose of t h i s t h e s i s was to develop at the U n i v e r s i t y of B r i t i s h Columbia a GaAs MESFET technology based on d i r e c t i o n i m p l a n t a t i o n and to develop methods to assess undoped LEC substrates f o r Cominco L i m i t e d , T r a i l , B.C. A t e s t device array c o n s i s t i n g of s t r u c t u r e s f o r process, m a t e r i a l , and device c h a r a c t e r i z a t i o n was designed and then f a b r i c a t e d on Cominco wafers by a d i r e c t i m p l a n t a t i o n process. Measurements on the t e s t device array elements showed that t h i s i n i t i a l process could be used to produce MESFET's o p e r a t i o n a l up to 3." GHz and that the t e s t device array w i l l be u s e f u l f o r monitoring future process developments and improvements. In a d d i t i o n , a channel conductance deep l e v e l t r a n s i e n t spectroscopy system, a photocurrent deep l e v e l t r a n s i e n t spectroscopy system, and a novel MESFET d r a i n current h y s t e r e s i s a n a l y s i s system were developed to examine deep l e v e l s i n GaAs and deep l e v e l t rapping e f f e c t s i n GaAs MESFET's. i i TABLE OF CONTENTS Page ABSTRACT i i LIST OF TABLES v LIST OF FIGURES v i ACKNOWLEDGEMENTS v i i i 1. INTRODUCTION 1 2. OVERVIEW OF GaAs MESFET TECHNOLOGY 3 2.1 I n t r o d u c t i o n 3 2.2 Device Considerations 3 2.3 Substrate Considerations 6 2.4 Process Considerations 8 3. THE TEST DEVICE ARRAY 9 3.1 D e s c r i p t i o n 9 3.2 F a b r i c a t i o n 13 3.2.1 Substrate Preparation 13 3.2.2 S e l e c t i v e Ion Implantation 14 3.2.3 Post Implant Anneal 15 3.2.4 M e t a l l i z a t i o n 15 4. MEASUREMENTS ON THE TEST DEVICE ARRAY 21 4.1 A c t i v e Layer E v a l u a t i o n 21 4.2 Gate M e t a l l i z a t i o n E v a l u a t i o n 31 4.3 Ohmic Contact M e t a l l i z a t i o n E v a l u a t i o n 35 4.4 MESFET Eva l u a t i o n 35 5. DEEP LEVEL TRANSIENT SPECTROSCOPY (DLTS) 40 5.1 Basic P r i n c i p l e s 40 5.2 Channel Conductance DLTS 43 5.3 Photocurrent DLTS 50 5.4 Measurements 53 i i i Page 6. HYSTERESIS-FREQUENCY SPECTROSCOPY 66 6.1 Theory 66 6.2 Apparatus 73 6.3 Measurements 75 7. SUMMARY AND CONCLUSION 79 REFERENCES 81 APPENDIX A Substrate Compensation Considerations 85 APPENDIX B Some Ion Implantation Processes Used f o r 88 GaAs MESFET F a b r i c a t i o n APPENDIX C Some Deep Levels i n GaAs Detected by DLTS 89 i v LIST OF TABLES Page 3.1 Test device array s t r u c t u r e s 9 4.1 A c t i v e l a y e r p r o p e r t i e s 30 4.2 M e t a l l i z a t i o n p r o p e r t i e s 33 4.3 MESFET y i e l d 36 4.4 Device parameters of 3 un MESFET's 39 5.1 Deep l e v e l s detected by CDLTS 54 5.2 P r o p e r t i e s of Cominco GaAs 60 5.3 Deep l e v e l s detected by PDLTS 64 v LIST OF FIGURES Page 2.1 GaAs MESFET 4 2.2 Comparison of a c t i v e l a y e r formation processes 7 3.1 Layout of the t e s t device array 11 3.2 The masks f o r the t e s t device array 12 3.3 F a b r i c a t i o n sequence f o r the t e s t device array 17 4.1 Experimental arrangement used f o r van der Pauw measurements .... 22 4.2 Experimental arrangement used f o r C-V measurements 24 4.3 Experimental arrangement used f o r d r i f t m o b i l i t y p r o f i l i n g 26 4.4 A c t i v e l a y e r sheet r e s i s t a n c e values f o r wafer 27 sec t i o n s f a b r i c a t e d 4.5 C-V p l o t f o r sample 123-S131(R1-C5) 28 4.6 C a r r i e r d e n s i t y and d r i f t m o b i l i t y p r o f i l e f o r 29 sample 123-S131(R1-C5) 4.7 Schottky diode current-voltage p l o t f o r 32 sample 123-S131(R1-C5) 4.8 SEM photograph (2000x mag.) f o r 3 un MESFET 34 sample 123-S131(R2-CS) 4.9 !DS~ VDS c h a r a c t e r i s t i c s f o r 3 un MESFET 37 sample 123-S131(R1-C5) 4.10 I G S ~ V G S c h a r a c t e r i s t i c s f o r 3 un MESFET 38 sample 123-S131(R1-C5) 5.1 Basic p r i n c i p l e of DLTS t r a n s i e n t generation 42 5.2 Basic p r i n c i p l e of dual channel boxcar sampling of 43 DLTS t r a n s i e n t 5.3 Block diagram of channel conductance DLTS arrangement 46 5.4 Sample holder used f o r DLTS measurements 47 v i Page 5.5 Block diagram of photocurrent DLTS arrangement 52 5.6 A CDLTS spectrum f o r 3 um MESFET sample 123-S131(R1-C5) 55 5.7 A CDLTS spectrum f o r 3 um MESFET sample 43-S10(R2-C6) 56 5.8 A CDLTS spectrum f o r 3 um MESFET sample 51-T132(R1-C3) 57 5.9 A c t i v a t i o n energy p l o t f o r traps detected by CDLTS 58 5.10 I-V c h a r a c t e r i s t i c s f o r 3 um MESFET sample 51-T132(R1-C3) 59 5.11 A PDLTS spectrum f o r sample 63-T42(A) 61 5.12 A PDLTS spectrum f o r sample 82-S14(A) 62 5.13 A c t i v a t i o n energy p l o t f o r traps detected by PDLTS 63 5.14 Comparison of trap signatures 65 6.1 I o n i z a t i o n of traps i n the d e p l e t i o n region due to the 67 sweep of gate voltage w i t h a sawtooth waveform 6.2 The d i f f e r e n c e (AL) between the normalized d e p l e t i o n width .... 72 when VQ changes from zero to -1/2 V M as a f u n c t i o n of normalized sweep frequency 6.3 Experimental arrangement f o r h y s t e r e s i s measurements 74 6.4 I-V c h a r a c t e r i s t i c s f o r MESFET 45-S93 (R4-C3) 76 6.5 Hy s t e r e s i s spectra f o r MESFET 45-S93(R4-C3) 77 6.6 A c t i v a t i o n energy p l o t f o r MESFET 45-S93(R4-C3) as 78 obtained by h y s t e r e s i s and CDLTS measurements v i i ACKNOWLEDGEMENTS I would l i k e to thank my su p e r v i s o r , Dr. L. Young, f o r h i s guidance and encouragement during the course of my work. I am g r a t e f u l to Mr. J i L i j i u and Dr. W. Lau f o r t h e i r numerous help-f u l d i s c ussions and f o r t h e i r work on the h y s t e r e s i s technique. Dr. N. Tar r , now at Carleton U n i v e r s i t y , Ottawa, i s thanked f o r h i s work on device f a b r i c a t i o n and the DLTS system and Mr. D Hutcheon f o r prepar-in g the t e s t device array masks. The a s s i s t a n c e of Messrs. D. Madge and R. North of Optotek L i m i t e d , Ottawa i n implanting the wafers i s appreciated as i s Mr. G. Needham of Cominco L i m i t e d , T r a i l , B.C., who supplied the GaAs wafers. Several others have aided t h i s work and are acknowledged. These i n d i v i d u a l s i n c l u d e Drs. D. Smith, and R. Koyama, Mr. M. Major, Messrs. F. Berry, A. Leugner, F. Kschischang, W. Tang, and F. Wan. I al s o thank G a i l Schmidt f o r typing the manuscript and I am indebted to W. Tang f o r h i s as s i s t a n c e i n preparing the f i g u r e s . F i n a n c i a l support was provided by the B r i t i s h Columbia Science Council and by NSERC. v i i i 1 1. INTRODUCTION Gallium arsenide metal semiconductor f i e l d e f f e c t t r a n s i s t o r s (GaAs MESFET's) have shown considerable p o t e n t i a l f o r use i n high speed d i g i t a l and mon o l i t h i c microwave i n t e g r a t e d c i r c u i t s ( I C ' s ) . For example, 8-12 GHz three and four stage a m p l i f i e r s have been i n t e g r a t e d (Wisseman et a l . , 1983) and la r g e s c a l e (> 1 0 3 gates) d i g i t a l c i r c u i t s r e a l i z e d (Eden, 1981), but before such IC's can become commercially v i a b l e and others of greater complexity developed, improved substrate growth and device f a b r i c a t i o n techniques are req u i r e d . One GaAs MESFET process technology (others are dicussed i n Chapter 2) that appears very promising i n v o l v e s the use of m u l t i p l e s e l e c t i v e i o n im p l a n t a t i o n d i r e c t l y i n t o undoped s e m i - i n s u l a t i n g GaAs substrates grown by the L i q u i d Encapsulated C z o c h r a l s k i (LEC) method. The o b j e c t i v e s of t h i s t h e s i s were to develop at the U n i v e r s i t y of B r i t i s h Columbia a GaAs MESFET technology based on d i r e c t i o n i m p l a n t a t i o n and i n conjunction w i t h Cominco L i m i t e d , T r a i l , B.C. (a s u p p l i e r of undoped LEC substrates) to develop methods to assess t h e i r GaAs f o r s u i t a b i l i t y i n device f a b r i c a t i o n . A t e s t device array c o n s i s t i n g of s t r u c t u r e s f o r pro-cess, m a t e r i a l , and device c h a r a c t e r i z a t i o n was designed. Undoped LEC sub-s t r a t e s were obtained from Cominco and used to f a b r i c a t e the array by a d i r e c t i o n i m p l a n t a t i o n process. Measurements were then performed on the array elements to assess the f a b r i c a t i o n s . To f u r t h e r a s s i s t i n m a t e r i a l and process development three techniques f o r c h a r a c t e r i z i n g deep l e v e l s i n GaAs were i n v e s t i g a t e d as deep l e v e l s play an important r o l e i n substrate compensation (Appendix A) and can al s o cause 2 degraded device behaviour. The three techniques were channel conductance deep l e v e l t r a n s i e n t spectroscopy f o r c h a r a c t e r i z i n g deep l e v e l s i n implanted m a t e r i a l , photocurrent deep l e v e l t r a n s i e n t spectroscopy f o r c h a r a c t e r i z i n g deep l e v e l s i n s e m i - i n s u l a t i n g m a t e r i a l and a novel technique f o r character-i z i n g deep l e v e l s which cause the commonly observed e f f e c t of h y s t e r e s i s (looping) i n GaAs MESFET I-V c h a r a c t e r i s t i c s . Chapter 2 gives a b r i e f overview of GaAs MESFET technology. Chapter 3 describes the t e s t device array and the d i r e c t i m p l a n t a t i o n process used i n i t s f a b r i c a t i o n while Chapter 4 describes the measurements performed to assess the f a b r i c a t i o n s . Chapter 5 describes the operation of and measure-ments performed w i t h the DLTS systems and Chapter 6 the operation of and measurements performed with the h y s t e r e s i s a n a l y s i s system. Chapter 7 gives the summary and conclusions of t h i s t h e s i s . 3 2. OVERVIEW OF GaAs MESFET TECHNOLOGY 2.1 I n t r o d u c t i o n Integrated c i r c u i t s capable of operating at speeds i n excess of 1 GHz are needed i n microwave communication systems, high speed computers, o p t i c a l f i b r e systems, and high speed t e s t equipment. I t i s becoming i n c r e a s i n g l y d i f f i c u l t to e x t r a c t more speed from S i devices and i t i s doubtful whether S i IC's can s a t i s f y these needs. GaAs IC's have a two to s i x times p o t e n t i a l speed advantage over S i IC's due i n part to GaAs's higher e l e c t r o n m o b i l i t y . Furthermore, since GaAs substrates may be grown i n a s e m i - i n s u l a t i n g s t a t e w i t h r e s i s t i v i t y near 1 0 8 ten (compared w i t h a t h e o r e t i c a l 1 0 5 tan f o r Si) and the GaAs r e t a i n s i t s high r e s i s t i v i t y a f t e r device processing, GaAs IC's can have low i n t e r - d e v i c e p a r a s i t i c capacitances and simple i n t e r - d e v i c e i s o l a t i o n s t r u c t u r e . 2.2 Device Considerations GaAs MESFET's were proposed by Mead (1966) and f i r s t r e a l i z e d by Hooper and Lehrer (1967). They are the most widely used t r a n s i s t o r i n GaAs IC's. (Other choices includ e j u n c t i o n f i e l d e f f e c t t r a n s i s t o r s (JFET's) and metal i n s u l a t o r f i e l d e f f e c t t r a n s i s t o r s (MISFET's)). The bas i c s t r u c t u r e of a GaAs MESFET c o n s i s t s of an n-type channel on a s e m i - i n s u l a t i n g GaAs su b s t r a t e , source and d r a i n ohmic contacts and a metal gate contact which forms a Schottky j u n c t i o n w i t h the channel ( F i g . 2.1). The gate to source voltage governs the depth of the gate d e p l e t i o n region and hence the conductance of the channel. As the gate voltage i s decreased, the d e p l e t i o n F i g . 2.1 GaAs MESFET 5 region expands and the channel conductance i s reduced u n t i l e v e n t u a l l y the channel becomes pinched-off. The maximum voltage on the gate (with respect to the source) required to cause pinch-off i s c a l l e d the threshold voltage V^ , and i s negative f o r a d e p l e t i o n (normally on) MESFET and p o s i t i v e f o r an enhancement (normally o f f ) MESFET. The f i r s t GaAs MESFET IC was reported by Van Tuyl and L i e c h t i (1974). The c i r c u i t was a NAND/NOR l o g i c gate and i t operated three times f a s t e r than the f a s t e s t S i l o g i c gate (at that time) thus demonstrating the high speed p o t e n t i a l of GaAs IC's. The s t r u c t u r e and operation of a GaAs JFET i s -si m i l a r to that of the MESFET except that i n a JFET a p +n j u n c t i o n gate i s used. MESFET's have been pr e f e r r e d over JFET's because JFET's have a l a r g e r gate sheet r e s i s t a n c e and are more d i f f i c u l t to f a b r i c a t e . Since the f i r s t GaAs JFET IC was reported by Notthoff and Zuleeg (1975), only r e l a t i v e l y coarse gate length JFET IC's have been reported ( i . e . 1.3 ym by Kato et a l . , 1981) while 0.5 um gate length MESFET IC's have been f a b r i c a t e d (Barna and L i e c h t i , 1979, Yamasaki et a l . , 1982). JFET's have a higher gate to channel b u i l t - i n voltage than MESFET*s ( t y p i c a l l y 1.4 V f o r JFET's to 0.8 V f o r MESFET's) and so (Lehovec and Zuleeg, 1980) can accommodate a l a r g e r forward bias and thus i n d i g i t a l c i r c u i t s permit a l a r g e r l o g i c voltage swing and noise margin, but again as pointed out by Lehovec and Zuleeg (1980) t h i s advantage of JFET's over MESFET's w i l l disappear i f power supply l e v e l s i n d i g i t a l c i r c u i t s are below 0.7 V as w i l l be required f o r u l t r a - l a r g e s c a l e (>10 5 gates) c i r c u i t s . GaAs MISFET's have an i n s u l a t i n g f i l m between the gate and channel. The i n s u l a t o r must give good i s o l a t i o n , low surface s t a t e d e n s i t y , and long term device 6 s t a b i l i t y . Several d i e l e c t r i c s have been t r i e d , as reviewed by Boyd (1981), but a s a t i s f a c t o r y i n s u l a t o r has not been found. 2.3 Substrate Considerations Semi-insulating GaAs substrates have been grown by the horizontal Bridgman technique since the early 1960's. GaAs i s synthesized i n a quartz boat with elemental Ga and As vapour inside a furnace. The GaAs melt i s then cooled by slowly moving the boat away from the furnace. P r i o r to cooling Cr i s added to the melt. The Cr introduces a deep l e v e l i n GaAs which compen-sates the shallow impurities found to contaminate the melt (Martin et a l . , 1980). In the LEC substrate growth technique a GaAs melt i s contained i n a quartz or p y r o l i t i c boron n i t r i d e (PBN) c r u c i b l e . The melt i s encapsulated with B^Oj- To grow a GaAs ingot a seed i s immersed into and then slowly pulled from the melt. The LEC technique was used more than twenty years ago by Metz et a l . (1962) but commercial LEC c r y s t a l growth equipment has only recently been available (1979). An a t t r a c t i v e feature of the LEC method i s that round wafers are pro-duced compared to the D shaped wafers produced by the Bridgman method. A second feature of the LEC method i s that semi-insulating wafers may be repro-ducibly attained without the need for i n t e n t i o n a l Cr doping as shallow impurities i n t h i s material are compensated v i a an i n t r i n s i c deep l e v e l formed during c r y s t a l growth (Appendix A). n -epi S I GaAs (a) n -eP' / / / / / epi-buffer / / / / / / S I GaAs (b) ~p _ n_- implant \/ / 7 / / / epi-buffer// / / / / S I GaAs (C) n j_irnplant _ _ _ j S I GaAs F.ig. 2.2 Comparison of a c t i v e l a y e r formation processes (a) E p i t a x i a l growth (b) E p i t a x i a l growth on b u f f e r l a y e r (c) Implantation i n t o b u f f e r l a y e r (d) D i r e c t i o n i m p l a n t a t i o n 8 2.4 Process Considerations D i f f i c u l t i e s encountered with Bridgman substrates (such as the degrad-a t i o n of a c t i v e l a y e r p r o p e r t i e s due to Cr impurity d i f f u s i o n , Udagawa et a l . , 1980) lead to the development of GaAs MESFET f a b r i c a t i o n processes i n which high r e s i s t i v i t y e p i t a x i a l b u f f e r l a y e r s are grown on a substrate and a c t i v e l a y e r s formed by a second e p i t a x i a l growth ( F i g . 2.2b) or by i o n imp l a n t a t i o n i n t o the b u f f e r l a y e r ( F i g . 2.2c). With LEC substrate's, how-ever, a c t i v e l a y e r formation by d i r e c t i o n i m p l a n t a t i o n ( F i g . 2.2c) appears p o s s i b l e (Welch et a l . , 1980). A t t r a c t i v e features of d i r e c t i o n i m p l a n t a t i o n i n c l u d e : high through-put (no e p i t a x i a l growth r e q u i r e d ) , the f a c t that s e l e c t i v e i m p l a n t a t i o n may be performed ( i n which only c e r t a i n parts of a wafer are implanted) a l l e v i a -t i n g the need f o r i n t e r - d e v i c e i s o l a t i o n procedures ("planar" technology), and the f a c t that m u l t i p l e and m u l t i p l e s e l e c t i v e implantations may be per-formed. Recently reported d i r e c t i m p l a n t a t i o n processes are summarized i n Appendix B. 9 3. THE TEST DEVICE ARRAY 3.1 Description A test device array designed for use i n evaluating GaAs integrated c i r c u i t processing and material properties i s i l l u s t r a t e d i n F i g . 3.1. Included i n the array, which i s p a r t l y based on that of Immorlica et a l . (1980), are a Schottky diode for c a r r i e r density p r o f i l i n g , van der Pauw cross structures for use i n H a l l e f f e c t measurements, (David and Buehler, 1977), a long gate MESFET ("fat FET") for d r i f t mobility p r o f i l i n g , pads for checking substrate i s o l a t i o n and ohmic contact resistance, a structure for measuring gate metal resistance, and a set of narrow gate length MESFET's (1-10 um) f o r use i n device characterization (Table 3.1). Table 3.1 - Test Device Array Structures STRUCTURE NAME PURPOSE DESCRIPTION 1 Schottky diode n-implant c a r r i e r density p r o f i l i n g Gate dimension=100x200 um 2 Substrate i s o l a -t i o n pads Test of substrate i s o l a t i o n (Ohmic) metal pads on SI substrate Pad dimension=100xl00 um Pad separations=40,20,10 um 3 van der Pauw cross Measurement of H a l l mobility and sheet resistance of n-implant Length of cross=200 um Width of cross=40 um 4 van der Pauw cross Measurement of H a l l mobility and sheet resistance of n +-implant Length of cross=250 um Width of cross=40 um ...continued 10 STRUCTURE NAME PURPOSE DESCRIPTION 5 Ohmic contact pads Measurement of ohmic contact r e s i s t a n c e Ohmic metal pads on implanted l a y e r Pad dimension=100xl00 ym Pad separations=40,20,10,5 ym 6 Gate metal s t r u c t u r e Measurement of gate metal sheet r e s i s t a n c e Number of squares=50 7 S p l i t gate MESFET Device C h a r a c t e r i z a -t i o n Gate length=4 ym , 8 Fat FET D r i f t m o b i l i t y p r o f i l i n g Long gate MESFET Gate dimension=100x200 yea 9 1 jjn MESFET Device c h a r a c t e r i z a -t i o n Gate width=200 ym 10 2 ym .. .. 11 3 ym " .. .. 12 4 ym .. .. 13 4 ym •• ., 14 6 ym .. .. 15 8 m " •• •• •• •• 16 10 ym " .. 17 Dual gate MESFET •• Gate length=4 ym 18 MIM c a p a c i t o r Test of d i e l e c t r i c p r o p e r t i e s 19 Coarse r e g i s t r a -t i o n mark Mask alignment a i d Six masks were designed f o r use i n f a b r i c a t i n g the array v i a a m u l t i p l e d i r e c t s e l e c t i v e i o n im p l a n t a t i o n approach ( r e g i s t r a t i o n etch mask, F i g . 3.1 Layout of the t e s t device ar r a y F i g . 3.2 The masks f o r the t e s t device array (a) R e g i s t r a t i o n marks (b) n-implant (c) n -implant (d) Gate metal (e) Ohmic contacts ( f ) 2nd l a y e r metal 13 n-implant mask, n +implant mask, ohmic contact m e t a l l i z a t i o n mask, gate metal-l i z a t i o n mask, and second l e v e l m e t a l l i z a t i o n mask). To prepare the masks, designs were entered i n t o the U.B.C. Computing Centre's Amdahl using a pro-gram w r i t t e n by G. Cheng. The f i l e s were then downlinked to a PDP8e i n the E l e c t r i c a l Engineering Department and a r u b y l i t h master cut under c o n t r o l of t h i s program. The r u b y l i t h was sent to P r e c i s i o n Photomask, Quebec, f o r f a b r i c a t i o n of the photographic (stepped and repeated) masks. To reduce pro-duction costs the required s i x p a t t e r n were grouped i n t o two masks as shown i n F i g . 3.2. With t h i s arrangement about 150 r e p l i c a t i o n s of the 1.0 x 3.3 mm array can be made on a 50 mm diameter wafer. 3.2 F a b r i c a t i o n 3.2.1 Substrate Preparation S e m i - i n s u l a t i n g GaAs wafers were obtained from Cominco L i m i t e d i n order to carry out an i n i t i a l f a b r i c a t i o n run of the t e s t device a r r a y . The wafers were LEC grown and undoped. The diameter of each wafer was 50 mm, the thickness 0.50 mm, and the c r y s t a l o r i e n t a t i o n (100). The process used to f a b r i c a t e the wafers began w i t h the f o l l o w i n g precleaning procedure ( F i g . 3.3a). 1. A three part degreasing c o n s i s t i n g of a 5 minute t r i c h l o r e t h y l e n e bath, a 5 minute b o i l i n g acetone bath, and f i n a l l y a 5 minute b o i l i n g isopropanol bath. 2. An etch to remove any work damage introduced during wafer sawing and p o l i s h i n g . The etch consisted of a 3 minute immersion i n i l H ^ O ^ l H ^ r l H ^ followed by a 10 minute DI water r i n s e . 14 3. A n a t i v e oxide etch c o n s i s t i n g of a 10 minute immersion i n b o i l i n g concentrated HC1 followed by a 10 minute DI water r i n s e . 3.2.2 S e l e c t i v e Ion Implantation Following c l e a n i n g , an S i O 2 f i l m of 0.6 ym thickness was deposited on the wafers to serve as a mask i n the s e l e c t i v e i o n i m p l a n t a t i o n process ( F i g . 3.3b). A Perkin-Elmer 3140 RF s p u t t e r i n g system was used w i t h an S i 0 2 t a r -get. The s p u t t e r i n g gases were Ar, 34 m i l l i t o r r , and 0 2, 4 m i l l i t o r r . ( 0 2 helps preserve the sto i c h i o m e t r y of the f i l m s ) . For a forward power of 150 W the d e p o s i t i o n r a t e was found to be about 0.15 ym/hr. In the next process step, windows were opened i n the S i 0 2 to permit the etching of r e g i s t r a t i o n marks i n the substrates ( F i g . 3.3c). These marks are necessary i n order to l o c a t e those regions of the wafer which have been implanted. The f o l l o w i n g procedure was used: 1. A p h o t o r e s i s t procedure (using the r e g i s t r a t i o n mark mask) c o n s i s t i n g of p h o t o r e s i s t d e p o s i t i o n ( S h i p l e y AZ1350J), a 30 minute 70° bake, mask alignment and exposure using a Kasper a l i g n e r , p h o t o r e s i s t development, a 10 minute DI water r i n s e , and f i n a l l y a 60 minute 120°C bake. 2. An SiO2 etch c o n s i s t i n g of a 5 minute immersion i n a buffered oxide etch (NH^+HF) and an immersion i n acetone to remove the p h o t o r e s i s t . 3. A substrate etch c o n s i s t i n g of a 1 minute immersion i n 10% HC1, a 1 minute DI water r i n s e , a 50 s immersion i n 5% HgPO^ 2.5% H 2 0 2 ( t o remove approximately 0.1 yn of the s u b s t r a t e ) , and a 5 minute DI water r i n s e . Next, a second set of windows were opened i n the S i 0 2 to define the regions of the wafers to be implanted ( F i g . 3.3d). This was accomplished 15 using the p h o t o r e s i s t procedure (with the n-implant mask) and the S i 0 2 etch procedure described above. 2 9 S i was implanted at an energy of 100 keV to a dose of 3 x l 0 1 2 c m - 2 ( F i g . 3.3e). The implantations were done by Optotek L i m i t e d , Ottawa, using an E x t r i o n 200 (s i n c e f a c i l i t i e s were not yet a v a i l -able at U.B.C). To reduce f a b r i c a t i o n time and complexity n + implantations and second l e v e l m e t a l l i z a t i o n were not done. ( n + i m p l a n t a t i o n i s used to reduce ohmic contact r e s i s t a n c e . Second l e v e l m e t a l l i z a t i o n i s used to achieve low r e s i s t a n c e i n t e r c o n n e c t s ) . 3.2.3 Post-Implant Anneal Following i m p l a n t a t i o n the implant mask was s t r i p p e d using a 10 minute buffered oxide etch. An S i 0 2 l a y e r , 0.17 um t h i c k , was then deposited (by RF sputt e r i n g ) to serve as an anneal cap ( F i g . 3.3f). Annealing was done i n a M i n i Brute furnace i n the f o l l o w i n g manner: 1. The furnace temperature was set to 850° and gas flow 14 l i t e r / m i n u t e N 2 and 1 l i t e r / m i n u t e H 2 e s t a b l i s h e d . 2. The wafers were placed at the f r o n t of the furnace f o r 5 minutes. 3. The wafers were placed at center of the furnace f o r 20 minutes. 4. The wafers were placed at the f r o n t of the furnace f o r 5 minutes to complete the anneal. The encapsulant was then s t r i p p e d using buffered oxide etch ( F i g . 3.3g). 3.2.4 M e t a l l i z a t i o n In the next stage, ohmic m e t a l l i z a t i o n , the s i n g l e step l i f t o f f technique of Hatzakis (1980) was used. The f o l l o w i n g steps were performed: 16 1. Degreasing (as described i n Section 3.2.1), 2. P h o t o r e s i s t d e p o s i t i o n , Shipley AZ1350J, ( F i g . 3.3h), 3. A prebaking at 70°C f o r 30 minutes, 4. Ohmic contact mask alignment and exposure ( F i g . 3 . 3 i ) , 5. A soaking i n 26.0°C chlorobenzene f o r 2 minutes followed by p h o t o r e s i s t development. (The chlorobenzene increases the str e n g t h of the top l a y e r ( F i g . 3.3j) to the developer so that an undercut edge p r o f i l e ( F i g . 3.3k) r e s u l t s upon p h o t o r e s i s t development.) 6. Thermal evaporation of AuGe (88% Au, 12% Ge) to thickness of 300 nm using VEECO VE400 ( F i g . 3.31). 7. Removal of unnecessary metal by immersion i n acetone, l i f t o f f , ( F i g . 3.3m). The ohmic contacts were then a l l o y e d f o r 1 minute i n a M i n i Brute furnace preheated to 450°C (to create an n + region beneath the c o n t a c t s ) . In the f i n a l process step, gate m e t a l l i z a t i o n , the l i f t o f f procedure was used w i t h the gate metal mask. In t h i s process A l was deposted to 0.5 um thickness by thermal evaporation using a VEECO VE400 ( F i g . 3.3n). S I GaAs ( Q ) Wafer pre c l e a n //////// SiO? ////////////// S I GaAs (b) Implant mask d e p o s i t i o n \\\ A \ r e s i s t \ \ w \ w ///V ///SiO?////////////// S I GaAs ( C ) Etch of r e g i s t r a t i o n marks \ \ \ W / / / / , w / / / LlAl resist  S1O2// SI GaAs ( ( j ) Opening of windows f o r implant F i g . 3.3 F a b r i c a t i o n sequence f o r the t e s t device a r r a y 1 i I 18 • N_ implant j SI GaAs //SiO?//// (e) Implantation ///////////Si02 ////////////////// i N implant ' S I GaAs ( f ) Encapsulation and annealing |_N_ implant S I GaAs — r I -1 (g) Wafer clean \ \ \ \ \ \ \ \ \ r e s i ! S T \ \ \ \ \ \ \ \ \ \ \ x-\ Li^J j N implant j S I GaAs ( h ) P h o t o r e s i s t d e p o s i t i o n F i g . 3.3 cont'd. exposed area V N X \ \\ \l k\\\\l N\res is i \ \ I n implant ! SI GaAs ( 1 ) P h o t o r e s i s t exposure modified layer \ \ w w \ J L\ rpqist \ \ \\\ [_N implant SI GaAs 1 t Chlorobenzene soak f \ W \ [ ' p e s i s t . A |\\ 1 :_ N jrnpbnt « SI GaAs (k) P h o t o r e s i s t development |\\\| j_ N jmpj.qnt _ _ J S I GaAs ( L) Source-drain m e t a l l i z a t i o n •Fig. 3.3 cont'd. N jmpLant J SI GaAs ( i T l ) Removal of p h o t o r e s i s t gate N implant S 1 GaAs r i (n) Gate m e t a l l i z a t i o n F i g . 3.3 cont'd. 21 4. MEASUREMENTS ON THE TEST DEVICE ARRAY 4.1 A c t i v e Layer E v a l u a t i o n To assess the d i r e c t i m p l a n t a t i o n and annealing process described i n Sections 3.2.2 and 3.2.3 the f o l l o w i n g p r o p e r t i e s of the implanted regions were examined: sheet r e s i s t a n c e , H a l l m o b i l i t y , a c t i v a t i o n , c a r r i e r d ensity p r o f i l e , and d r i f t m o b i l i t y p r o f i l e . Sheet r e s i s t a n c e , H a l l m o b i l i t y , and a c t i v a t i o n measurements were made using the van der Pauw cross ( s t r u c t u r e #3, F i g . 3.1). Samples were placed i n a magnetic f i e l d B (0.2T) d i r e c t e d normal to the cross ( F i g . 4.1a). An Alpha S c i e n t i f i c 7500-W magnet and power supply were used. A current I (200 uA) was e s t a b l i s h e d between opposite terminals of the cross ( i . e . between terminals B and D, F i g . 4.1b) using a HP 6186B current source and the H a l l voltage V^ across the other terminals ( i . e . between terminals A and C) measured (with a Fluke 8050 v o l t m e t e r ) . Average H a l l m o b i l i t y UJJ was then c a l c u l a t e d using A. R BI s (4.1) where R g i s the a c t i v e l a y e r sheet r e s i s t a n c e (van der Pauw, 1958). To determine R g a current I' (0-1 mA) was e s t a b l i s h e d across adjacent terminals (A and D) ( w i t h no a p p l i e d magnetic f i e l d ) and the voltage V across the other terminals (B and C) measured. R was then c a l c u l a t e d using s (van der Pauw, 1958) holder sample (a) CURRENT SOURCE D MAGNET POWER SUPPLY ( b ) B F i g . 4.1 Experimental arrangement used f o r van der Pauw measurements (a) Apparatus (b) van der Pauw cross 23 R IT fti2 XL I' (4.2) A c t i v a t i o n , n, was estimated using measured sheet electron concentration 1 , n = = (4 implanted dose Dq u^Rg where q i s the elementary charge and D the implanted dose. Ca r r i e r density p r o f i l e s were determined by the capacitance-voltage technique i n which the capacitance of a Schottky diode (structure #1, F i g . 3.1) was measured as a function of reverse bias, V, and the p r o f i l e , N(x), then given by (e.g. Sze, 1981) N ( X ) = _ J L _ [ M ^ f 1 (4.4 A ? dv J q eA'' where e i s the p e r m i t t i v i t y of GaAs (~ 1.16 x 10" 1 0 F/m), A the diode area and x the depth below the surface (x = eA/C). C which was measured with a 1 MHz capacitance meter (Boonton 71A) was recorded under PDP8e computer con-t r o l using the system of Boyd (1980) and program MESCV written by J i L i j i u . The arrangement used to perform the p r o f i l i n g s i s shown i n F i g . 4.2. D r i f t mobility p r o f i l e s were measured with the f a t FET's (structure #8, F i g . 3.1) using the method of Pucel and Krumm (1976). A f a t FET was biased i n i t s l i n e a r region ( V D g = 50 mV) and the modulation i ^ i n i t s drain current r e s u l t i n g from the a p p l i c a t i o n of a'small-signal gate-source voltage SAMPLE HOLDER 24 CAP-METER b i a s Out X A-D-C D-V-M LXJ O DC LU OFFSET VOLTAGE SUPPLY D-A-C-PDP 8/e COMPUTER F i g . 4.2 Experimental arrangement used f o r C-V measurements 25 v (20 mV D M C) recorded as a f u n c t i o n of the DC gate-source bias V„ c. D r i f t gS KJMo (JO m o b i l i t i e s P R(x) were then c a l c u l a t e d using * n ( x ) = C V ^ ( 4 ' 5 ) DS gs where L i s the gate length and C the gate capacitance (determined by C-V measurements). v ^ g was derived from a sine wave generator (IEC F63) while a l o c k - i n a m p l i f i e r (PAR 5204) was used to provide an output p r o p o r t i o n a l to i , / v . The apparatus used to implement the p r o f i l i n g s i s shown i n F i g . 4.3. Q gS Sheet r e s i s t a n c e values are tabulated i n F i g . 4.4. A t y p i c a l C-V p l o t i s shown i n F i g . 4.5 and c a r r i e r d ensity and d r i f t m o b i l i t y p r o f i l e i n F i g . 4.6. Table 4.1 summarizes the a c t i v e l a y e r parameters. From the r e s u l t s the f o l l o w i n g comments can be made: 1. D r i f t m o b i l i t y i s seen to increase towards the s u b s t r a t e . This behaviour has been shown by Immorlica et a l . (1981) to c o r r e l a t e w i t h good RF per-formance i n t h e i r i o n implanted GaAs power MESFET's while devices which di s p l a y e d a decreasing d r i f t m o b i l i t y p r o f i l e were found to e x h i b i t slow pulse response of d r a i n current to ap p l i e d gate voltage and premature s a t u r a t i o n of output power. 2. L i u et a l . (1980) have c a l c u l a t e d the t h e o r e t i c a l implant range Rp and st r a g g l e ARp f o r 100 KeV S i i m p l a n t a t i o n i n t o GaAs to be 86 nm and 38 nm r e s p e c t i v e l y , so that i t appears that broadening has occurred during annealing. VOLTAGE SUPPLY VOLTAGE SUPPLY + -SIGNAL GENERATOR! sample 1 L _ _ J 10 ,1M 10 < 0-1P* i n LOCK-IN AMPLIFIER 1 output 1K -A/VV-ref 4.3 Experimental arrangement used f o r d r i f t m o b i l i t y p r o f i l i n g K J 3 (a) (b) ( c ) ( d ) R3 R2 R l R3 R2 R l R l 2.0 3.1 R2 . 1.8 1.8 1.5 R3 1.3 1.5 1.5 1.6 R4 2.2 1.4 1.3 1.3 R5 4.0 1.5 1.4 1.3 1.3 R6 1.9 1.6 1.3 1.3 2.6 R7 > 1.4 1.5 3.2 0.6 27 (b),(e),(d) C l C2 C3 C4 C5 1.7 3.5 3.1 9.4 4.8 > > 1.1 0.4 9.0 1.2 1.3 2.9 4.4 5.5 4.4 > 0.5 1.5 1.2 1.2 0.8 1.2 2.2 2.4 2.6 2.6 4.0 3.6 C l C2 C3 C4 C5 C6 C7 C8 C9 CIO C l l C12 2.6 3.1 4.1 5.8 0.7 > > 2.9 1.2 1.4 1.4 1.5 1.6 2.0 2.8 2.6 5.6 0.6 1.1 1.0 1.3 1.2 1.2 2.9 2.2 C l C2 C3 C4 C5 C6 C7 C8 C9 CIO C l l R3 4.2 3.2 2.8 2.1 R2 0.8 0.8 0.9 1.4. 1.9 1.8 R l 0.8 0.8 0.8 0.7 0.8 0.8 1.7 C2 C3 C4 C5 C6 C7 C8 F i g . 4.4 A c t i v e l a y e r sheet r e s i s t a n c e values f o r wafer s e c t i o n s f a b r i c a t e d ( i n kx/a , ? =R *10 W o ) (a) Wafer 94-S13 (b) Wafer 43-S10 (c) Wafer 123-S131 S (d) Wafer 51-T132 50 AO LLI o z I ° 30 20--A -3 -2 -1 GATE VOLTAGE[V] F i g . 4.5 C-V p l o t f o r sample 123-S131 (R1-C5) I 1 — i 1 * ~ 50 100 150 200 250 DEPTH ( nm) F i g . 4.6 C a r r i e r d e n s i t y and d r i f t m o b i l i t y p r o f i l e f o r sample 123-S131 (R1-C5) 30 Table 4.1 - A c t i v e Layer P r o p e r t i e s Sample 43-S10 (R2-C6) 123-S131 (R1-C5) 51-T132 (R1-C3) Sheet Resistance, R ' s [koy D] 1.3 1.3 0.8 H a l l M o b i l i t y , ^ [cm 2/Vs] 3.3x10 3 3.3x10 3 3.6x10 3 Percent A c t i v a t i o n , n [%] 49 50 74 Peak Doping, N Q [cm" 3] 1.5x10 1 7 1 . 6 x l 0 1 7 1.9x10 1 7 Implant Range, R^ [nm] 102 100 107 Implant Staggle, ARp [nm] 69 54 69 3. A c t i v a t i o n s obtained can be compared to those of Immorlica et a l . (1980) f o r 3 x 1 0 1 2 c m - 2 S i implants who report n's from 67-74%. 4. The average R g f o r wafer 51-T132 i s lower than of wafers 43-S10 and 123-S131. (The f i r s t number i n the wafer desi g n a t i o n s p e c i f i e s the ingot from which the wafer was cut while the second number s p e c i f i e s the wafer p o s i t i o n w i t h respect to e i t h e r the seed S or t a i l T of the i n g o t ) . This r e s u l t may r e f l e c t the f a c t that ingot 51 was found by Cominco to be thermally unstable showing a r e s i s t i v i t y drop from 1.8x10 8 tan to l . l x l O 1 * tan f o l l o w i n g a 30 minute 850°C anneal. 31 4.2 Gate M e t a l l i z a t i o n E v a l u a t i o n To assess the gate m e t a l l i z a t i o n process described i n Section 3.2.4 the f o l l o w i n g p r o p e r t i e s were examinated: curre n t - v o l t a g e c h a r a c t e r i s t i c s , b a r r i e r h eight, i d e a l i t y f a c t o r , (gate metal) sheet r e s i s t a n c e , l i t h o g r a p h i c d e f i n i t i o n . then derived from the forward c h a r a c t e r i s t i c s since f o r V>3kT/q Schottky diode current density J i s approximated by: where A* i s an e f f e c t i v e Richardson constant (A*=8.7 A c m - 2 K - 2 f o r n type GaAs, Crowell et a l . , 1965) T the diode temperature, and k Boltzmann's con-stant so that Schottky diode current-voltage c h a r a c t e r i s t i c s were measured on a Tektronix 577 curve t r a c e r . B a r r i e r heights (4.6) (4.7) and dV (4.8) n = 2.30 kT * d(logJ) where J i s an extrapolated current d e n s i t y at zero bias ( F i g . 4.7). Gate 32 F i g . 4.7 Schottky diode c u r r e n t - v o l t a g e p l o t f o r sample 123-S131 (R1-C5). 33 metal sheet resistances Rg^ were estimated by measuring the resistance between the terminals of the gate metal structure (structure #6, F i g . 3.1) (by a current voltage technique). Photolithographic d e f i n i t i o n of the gate m e t a l l i z a t i o n was checked using a scanning electron microscope (SEM). Table 4.2 l i s t s values of b a r r i e r height, i d e a l i t y factor and sheet resistance. An SEM photograph of a 3 p MESFET (structure #11, F i g . 3.1) i s shown i n F i g . 4.9. The following comments can be made: 1. The high i d e a l i t y factors obtained may be a r e s u l t of improper cleaning p r i o r to m e t a l l i z a t i o n as Miers (1982) has found that i d e a l i t y factors varied from 1.08 to 1.33 depending on surface treatment. 2. B a r r i e r heights obtained are consistent with the commonly accepted values for metals on n-type GaAs (see, for example, Sze, 1981). 3. The gate length of the 3 un MESFET i s close to 4 ym and the gate d e f i n i t i o n i s poor i n d i c a t i n g the need for an improved mask alignment technique. Table 4.2 - M e t a l l i z a t i o n Properties Sample 43-S10 (R2-C6) 123-S131 (R1-C5) 51-T132 (R1-C3) Schottky Barrier Height, ^ [eV] 0.74 0.73 0.73 Schottky B a r r i e r I d e a l i t y Factor, n 1.3 1.4 1.3 Gate Metal Sheet Resistance, R [Q/D] 0.2 0.2 0.2 Ohmic Contact Resistance, R c [mjjcm2] 0.27 0.32 0.22 10 pm F i g . 4.8 SEM photograph (2000X mag.) f o r 3um MESFET sample 123-S131 (R2-C5) 35 4.3 Ohmic Contact M e t a l l i z a t i o n E v a l u a t i o n To assess the ohmic contact m e t a l l i z a t i o n process described i n Section 3.2.4 measurements were made of s p e c i f i c ohmic contact r e s i s t a n c e by the method of Berger (1972). The r e s i s t a n c e r „ between adjacent ohmic contact pads i and j ( s t r u c t u r e #5, F i g . 3.1) was measured and (the contact r e s i s t a n c e of a pad) determined by a l i n e a r r e g r e s s i o n of R r. . = 2R + — I . (4.9) i j c w i j where £ i s the separation between pads i and j and w i s the width of the pads. Values obtained f o r s p e c i f i c contact r e s i s t a n c e are l i s t e d i n Table 4.2. Since f o r microwave FET's s p e c i f i c contact r e s i s t a n c e s of 1 0 - 5 tan2 or l e s s are d e s i r a b l e (Gupta et a l . 1983) ohmic contacts of lower r e s i s t a n c e are re q u i r e d . Use of the high dose n + implant under source and d r a i n regions ( i . e . mask C F i g . 3.2) should r e c t i f y the s i t u a t i o n . 4.4 MESFET E v a l u a t i o n To t e s t the operation of the devices produced i n the f a b r i c a t i o n s , c h a r a c t e r i s t i c s of the narrow gate MESFET's ( s t r u c t u r e #9-12, 14-16, F i g . 3.1) were checked on a Tektronix 577 curve t r a c e r . From these measurements i t was found that o p e r a t i o n a l 2-10 um devices can be produced but that improved p h o t o l i t h o g r a p h i c t o o l s are required to produce the 1 um devices (Table 4.3). (A device was deemed o p e r a t i o n a l i f i t showed !_„ s a t u r a t i o n 36 and could be pinched-off to 100 pA). F i g . 4.9 shows a t y p i c a l Ing~V] c h a r a c t e r i s t i c and F i g . 4.10 a I„„ ~V r Q c h a r a c t e r i s t i c . Table 4.3 - MESFET Y i e l d Wafer 94-S13 43-S10 123-S131 51-T132 T o t a l # Devices 27 26 25 17 95 10 voi Gate .70 .50 .84 .88 .72 8 " .52 .38 .76 .94 .62 6 " .48 .23 .80 .76 .54 4 •• .59 .50 .72 .71 .62 3 " .59 .46 .76 .76 .63 2 " .48 .35 .64 .76 .54 1 " 0 0 0 .12 .02 TOTAL .48 .35 .65 .71 .53 Table 4.4 l i s t s the DC c h a r a c t e r i s t i c s of various 3 pm MESFET's. The AC behaviour of three of these devices (123-S131 R1-C8, 51-T132 R1-C6, and 43-S10 R2-C5) were checked over the frequency range 2-5 GHz on a HP8409 network analyzer (at Microtel P a c i f i c Research, Burnaby, B.C.) and found to have a cutoff frequency of about 3 GHz. This r e s u l t i s reasonable considering the high ohmic contact resistance and large gate-source separation (~ 4 pm) i n the devices. The t h e o r e t i c a l cutoff frequency for an i n t r i n s i c 3 pa MESFET having no p a r a s i t i c components i s about 10 GHz (Pucel et a l . , 1975). 38 Fig."4.10 I -V c h a r a c t e r i s t i c s f o r 3 pm MESFET sample 123-S131 (R1-C5) 39 Table 4.4 - Device Parameters of 3 um MESFET's Sample 43-S10 43-S10 123-S131 123-S131 51-T132 51-T132 (R2-C5) (R2-C6) (R1-C5) (R1-C8) (R1-C6) (R1-C3) "^DSAT @ V D S = 4 V [mA] 13 13 16 15 19 19 VGS @ ^ S " 1 0 0 * [-v] 2.74 - 2.97 2.54 3.10 3.12 VGS @ ^ S " 1 0 * [-v] 3.14 2.82 3.19 2.74 3.30 3.34 VGS @ ^ S " 1 * [-v] - 3.55 3.35 2.91 3.44 3.48 Gm @ V D S = 4 V [mA/V] 5 6 5 6 8 8 To check MESFET d r a i n current s t a b i l i t y 3 ym device 123-S131 (R1-C5) was biased at Vpg=lV and a gate voltage a p p l i e d of s u f f i c i e n t magnitude (V_C«-3V) to reduce I _ to 100 uA. I .f o l l o w i n g the a p p l i c a t i o n of the gate voltage ;was then monitored on a chart recorder. I was found to be s t a b l e to w i t h i n ±5% of 100 pA over a period of 30 minutes a r e s u l t that d i f f e r s from those Itoh and Yanai (1980) and Itoh et a l . (1981) who reported d r a i n current d r i f t s of 20-40% ( a t t r i b u t e d to Cr trapping l e v e l s ) f o r MESFET's formed by epitaxy on Bridgman su b s t r a t e s . 40 5. DEEP LEVEL TRANSIENT SPECTROSCOPY 5.1 Basic P r i n c i p l e s Since i t s i n t r o d u c t i o n by Lang (1974), deep l e v e l t r a n s i e n t s p e c t r o -scopy (DLTS) has proven a very u s e f u l technique f o r i n v e s t i g a t i n g deep l e v e l s i n semiconductor devices. I t enables a non-destructive e v a l u a t i o n of the energy l e v e l E^ , and e l e c t r o n (hole) capture cross s e c t i o n o"n( o^) of the major deep st a t e s i n a sample. Deep l e v e l concentrations may a l s o be determined. DLTS i s based on the modulation and measurement of the d e p l e t i o n region capacitance C(t) of a pn j u n c t i o n or Schottky diode. To analyze, f o r example, a p +n diode f o r m a j o r i t y c a r r i e r traps i n the n r e g i o n , sample temperature T i s v a r i e d and a voltage V(t) a p p l i e d ( F i g . 5.1). During period t g - t ^ traps i n the undepleted n region are f i l l e d w i t h e l e c t r o n s . When the bias i s changed from V 1 to V 2 the d e p l e t i o n region width expands from Wj^  to W3 while the capacitance drops from to Cy Traps at a depth between W3 and Wj^  which were f i l l e d are now emptied at a ra t e dependent on the trap's energy l e v e l and e l e c t r o n capture cross s e c t i o n . The release of trapped c a r r i e r s r e s u l t s i n a r e l a x a t i o n of the d e p l e t i o n width from Wg to the steady s t a t e value W2 and hence a r e l a x a t i o n of the capacitance from C 3 to C 2. The t r a n s i e n t s i g n a l S(t) i s processed w i t h a dual channel boxcar averager. The choice of boxcar sampling times t ^ and t 2 f i x e s the so c a l l e d r a t e window RC of the system (Eq. 5.12). When the decay constant T of S(t) i s equal to the ra t e window, the output of the boxcar r e g i s t e r s a maximum. As the sample temperature i s scanned, a DLTS spectrum of S ( t 1 ) - S ( t 2 ) versus T i s obtained ( F i g . 5.2). I f more than one type of deep l e v e l i s present i n DLTS TRANS IENT S(T) W, v( t )H + n + (a) • h i -v ' ( t ) - p* + n i r (b) v ( t ) H F i g . 5.1 Basic p r i n c i p l e of DLTS generation (a) Steady s t a t e (b) Trap f i l l i n g (c) Trap emptying 42 F i g . 5.2 B a s i c p r i n c i p l e of dual channel boxcar sampling of DLTS t r a n s i e n t 43 the sample, s e v e r a l peaks w i l l appear i n the spectrum. By s e l e c t i n g various rate windows and repeating the temperature scan a f a m i l y of DLTS spectra are obtained from which trap data may be c a l c u l a t e d (as described i n Section 5.2). 5.2 Channel Conductance DLTS Channel conductance DLTS (CDLTS) i s a u s e f u l technique to assess the deep l e v e l s i n the channel of a MESFET ( A l d e r s t e i n , 1976). A small d r a i n to source voltage ( V n «50 mV) i s a p p l i e d . V i s set to zero to allow e l e c t r o n Do CJO traps i n the channel to be f i l l e d . V_ c i s then stepped to V 0 (Va,<Vo<0). The (JO (J 1 (J gate d e p l e t i o n region widens and a t r a n s i e n t channel current develops due to the release of el e c t r o n s from the expanded d e p l e t i o n region. An expression f o r the channel conductance t r a n s i e n t may be derived f o r a MESFET of gate length L, gate width Z, and zero gate voltage channel depth a. I t i s assumed that a uniform a c t i v e l a y e r shallow donor de n s i t y N^ e x i s t s and that a s i n g l e e l e c t r o n trap of den s i t y N^ , i s present. Neglecting the r e s i s t a n c e of the unmodulated channel regions, the conductance of the MESFET G(t) i s Zola-X ( t ) ] G(t) = =4 (5.1) where a i s the c o n d u c t i v i t y of the a c t i v e l a y e r and X^(t) i s the gate deple-t i o n region depth measured from the zero gate bias value. I f at time t=0 the gate bias i s stepped from 0 to and the steady s t a t e conductance f o r la r g e (J 44 t i s G Q ( w i t h a corresponding d e p l e t i o n depth of X ^ ) , then the conductance d i f f e r e n c e s i g n a l AG(t) (AG(t) = G Q-G(t) ) i s Za[X,(t)-X, ] AG(t) ! - ^ (5.2) Since X^(t) can be assumed to be given by 2eV G 1/2 X d U ) = ^ q[N D+N T(l-exp-t/T)] * ( 5 * 3 ) where i i s a time constant, one f i n d s that X H ( t ) 1 1 / 9 4 — = [ r ? ( 5 - 4 ) D O T / / N 1 ' N ^ e X p ( " t / T ) Now i f N^,«Np Eq. (5.4) becomes X (t) N exp(-t/ T) H f — " 1 + J L 2 N ( 5 ' 5 ) Ado Z BD so Eq. (5.2) can be w r i t t e n as z ° x ^ NT AG(t) = 2 L N d ° 1 exp(-t/T) (5.6) 45 which i s the des i r e d expression f o r the channel conductance t r a n s i e n t . A block diagram of the CDLTS system of t h i s t h e s i s i s shown i n F i g . 5.3. The d r a i n voltage to the FET i s derived from a regulated power supply while the p e r i o d i c gate bias i s supplied by an IEC F33 pulse generator. A small r e s i s t o r R (10 n) converts the channel current i n t o a voltage s i g n a l which i s subsequently a m p l i f i e d by a PAR 113 a m p l i f i e r . The output from the a m p l i f i e r goes to the input of a PAR 162/165 dual channel boxcar arrangement. The boxcar output goes to the Y channel of an HP 7044A X-Y p l o t t e r . The X channel of the p l o t t e r records the thermocouple voltage of the sample. The sample i s housed i n a l i g h t t i g h t chamber. The chamber, which was adapted f o r use from a previous study ( L e s t e r , 1982) i s i l l u s t r a t e d i n F i g . 5.4. A f t e r the chamber i s evacuated to a pressure of l e s s than 10 t o r r , sample temperature i s lowered to 100 K v i a l i q u i d n i t r o g e n c o o l i n g . A power t r a n s i s t o r i s used to heat the sample. A copper-constantan thermocouple, soldered to the device package, i s used to monitor the temperature. where A^ i s the a m p l i f i e r gain and where i t i s as sumed that R«[G(t)] - 1. The output of the boxcar V Q (as a f u n c t i o n of temperature T) can then be express-ed as The input s i g n a l t r a n s i e n t V.(t) to the boxcar i s given by V ± ( t ) = A ARG(t)V. DS (5.7) V Q(T) = A B [ V . ( t l ) (5.8) VOLTAGE SUPPLY chamber—T sample I thermocouple — I R=10 out PULSE GENERATOR X-Y PLOTTER AMPLIFIER trig BOXCAR out n F i g . 5.3 Block diagram of channel conductance DLTS arrangement Liquid N 2 cryostick I^ig. 5.4 Sample holder used f o r DLTS measurements 48 where A_ i s the voltage gain of the boxcar. Then from Eq.'s (5.6) and (5.7) Eq. (5.8) can be r e w r i t t e n as A.A^RZ oV__NTX V T ) " 2LN [exp(-t 2/T) - expC-t/x)] (5.9) The temperature dependence of V Q i n Eq. (5.9) can be derived from the temperature dependence of T. From the p r i n c i p l e of d e t a i l e d balance the time constant ( r e c i p r o c a l emission rate) f o r an e l e c t r o n trap can be shown to be T = (o n v n N c ) - l e x p [ J ^ ] (5.10) where o"n i s the capture cross s e c t i o n , v n the thermal v e l o c i t y of e l e c t r o n s , E c the conduction band energy, and N £ the conduction band de n s i t y of s t a t e s . A trap l e v e l of s i n g l e degeneracy i s assumed. Since v ^ and N £ vary markedly w i t h T, Eq. (5.10) i s more a p p r o p r i a t e l y expressed as t = ( o ^ 2 ) " 1 e x p ( ^ 2 ) (5.11) where y i s equal to 2 . 2 8 x l 0 2 0 c m - 2 s - 1 K - 2 f o r e l e c t r o n traps i n GaAs and to 1 . 7 x l 0 2 1 c m - 2 s - 1 k - 2 f o r hole traps i n GaAs (M a r t i n et a l . , 1977, Mitonneau et a l . , 1977). For a c e r t a i n value of x, c a l l e d x m, V Q peaks. By d i f f e r e n t i a t i n g Eq. (5.9) w i t h respect to T and s e t t i n g the r e s u l t equal to zero one f i n d s that 49 t r t 2 V = On t l / t 1 ( 5 ' 1 2 ) which i s defined as the rate window RC of the CDLTS scan. Since the tempera-ture T m corresponding to the peak i n V q i s obtained from the DLTS spectrum ( F i g . 5.2) and t ^ and t 2 are known, one may w r i t e F —E m n m v k l ' m If a second spectrum i s obtained f o r a d i f f e r e n t rate window, a and E -E„ r n c T are uniquely determined. U s u a l l y s e v e r a l scans are made and a p l o t of l o g T 2 x versus 1/T ( a c t i v a t i o n energy p l o t ) made. Trap parameters are then given by E c - E T = 2.30 km (5.14) a n d a n = ( Y l O b ) _ 1 ( 5 ' 1 5 ) where m and b are the slope and i n t e r c e p t , r e s p e c t i v e l y , of the best l i n e a r f i t to the above p l o t . The concentration of a trap i s derived from the height V Q ( T m ) of the CDLTS peak. From Eq. (5.9) N^ , can be c a l c u l a t e d as 2LN_V n(T ) - t - t A B DS do m m 50 where x m i s given by (5.12). I f the a c t i v e region of a MESFET i s formed by i o n im p l a n t a t i o n the assumption of a uniformly doped channel region i s v i o l a t e d . Nevertheless, Eq.'s (5.14) and (5.15) can s t i l l be expected to give a reasonable estimate of E -E_, and a i n most cases. Since the c o n d u c t i v i t y of an implanted chan-c i n n e l can be taken to be p r o p o r t i o n a l to an average N n i t i s i n t e r e s t i n g to note that Eq. (5.16) reveals that N^ , may be c a l c u l a t e d simply from a know-ledge of X^ Q (which can be deduced from a capacitance voltage measurement). 5.3 Photocurrent DLTS Photocurrent DLTS (PDLTS) i s a u s e f u l technique to assess the deep l e v e l s i n a s e m i - i n s u l a t i n g sample (Fairman et a l . , 1979, Hurtes et a l . , 1978). The device s t r u c t u r e that i s used i n PDLTS c o n s i s t s of two c l o s e l y spaced ohmic contact pads. A bias V i s e s t a b l i s h e d between the pads and the sample i s i l l u m i n a t e d w i t h bandgap l i g h t . E l e c t r o n / h o l e p a i r s are generated which populate traps i n the sample. I f the sample i s i l l u m i n a t e d f o r a s u f f i c i e n t l ength of time the current flow between the pads approaches a steady s t a t e value i . I f the sample contains a trap of de n s i t y N T, the occupation of the trap n,j, during steady s t a t e i s given by s e +a v p _ i n = N [ l + n . P P ) (5.17) T T e +a v n s p n n where e /e , a /a , v /v , and n/p are the el e c t r o n / h o l e r a t e constant, n p n p n p capture cross s e c t i o n , thermal v e l o c i t y and con c e n t r a t i o n , r e s p e c t i v e l y 51 (Hurtes et a l . , 1978). When the l i g h t i s removed (at t=0) the current does not immediately f a l l to i ^ (the leakage flow) but instead g r a d u a l l y decays to t h i s l e v e l due to the slow release of trapped c a r r i e r s . The decay current i p ( t ) I s given by i ( t ) = C { e n n T ( t ) + e p [ N T - n T ( t ) ] } (5.18) where n^ , i s the d e n s i t y of occupied t r a p s , C i s a constant dependent on contact geometry (Martin and B o i s , 1978) and where i^has been neglected. I f i t i s assumed that i p ( t ) decays e x p o n e n t i a l l y w i t h time constant x and that n^,(0) i s equal to n^ , Eq. (5.18) becomes s M O = C e n N T [ ( l - r - ^ P ) " 1 - (!+!») ^ e x p ^ ) . (5.19) v n n p For an e l e c t r o n trap a »a and f~ 1 =e » e so that n p n p i ( t ) = C x - ^ e x p ^ ) . (5.20) A block diagram of the photoconductance DLTS (PDLTS) system of t h i s t h e s i s i s shown i n F i g . 5.5. The system u t i l i z e s the same apparatus as the CDLTS arrangement of F i g . 5.3 except that a type ME7021IR l i g h t e m i t t i n g diode (900 nm, l ' . O mW @100 mA) mounted on the sample chamber i s used to chamber ,p sample thermocouple PULSE GENERATOR syn tr ig X-Y PLOTTER AMPLIFIER BOXCAR out n Fdg. 5.5 Block diagram of photocurrent DLTS arrangement N3 53 i l l u m i n a t e the sample through a window ( F i g . 5.4). The t r a n s i e n t s i g n a l input V_^(t) to the boxcar i s V ± ( t ) = A AR i ( t ) (5.21) while the boxcar output V (T) derived from Eq. (5.20) i s o - t l - t 2 V q ( T ) = A ^ R C x - ^ ^ x p ^ ) - e x p ( — ) ] (5.22) where A., A„ and R are as defined p r e v i o u s l y . I f V (T) i s d i f f e r e n t i a t e d A B o w i t h respect to T and the r e s u l t set equal to zero TFFI i s found to s a t i s f y ( I t o h and Yanai, 1981) (1 - ^ ) e x p £ i ) = (1 - - ^ ) e x p h ^ ) . (5.23) m m m m Once T i s c a l c u l a t e d , a and E -E„, can be determined from Eq. (5.13) as i n m n c I CDLTS. 5.4 Measurements CDLTS measurements were made with the system described i n Section 5.2 to o b t a i n i n f o r m a t i o n on the deep l e v e l s i n the channel region of the MESFET's f a b r i c a t e d i n Chapter 3. 3 pm MESFET's were examined over the temperature range 100-350 K w i t h r a t e windows 1-100 ms. 54 CDLTS spectra f o r devices 123-S131 (R1-C5), 43-S10 (R2-C6), and 51-T132 (R1-C3) are shown i n Fig.'s 5.6-5.8. Three e l e c t r o n t r a p s , l a b e l l e d CE1, CE2, and CE3 are resolved i n each sample. The a c t i v a t i o n energy p l o t (or DLTS "s i g n a t u r e " , M a r t i n et a l . , 1977) of each trap i s shown i n F i g . 5.9. Table 5.1 l i s t s data on trap energy, cross s e c t i o n , and concentration c a l c u l a t e d v i a Eq.'s 5.14-16. Trap concentrations i n 51-T132 (R1-C3) ( e s p e c i a l l y CE1) are lower than i n the other two devices. In a d d i t i o n the I -V c h a r a c t e r i s t i c s of 51-T132 (R1-C3) show l e s s h y s t e r e s i s than that of 123-S131 (R1-C5) (or 43-S10 R2-C6) (compare F i g . 4.9 w i t h F i g . 5.10) suggesting that one or more of these traps are responsible f o r h y s t e r e s i s . Table 5.1 - Deep Levels Detected by CDLTS Label A c t i v a t i o n Energy [eV] Log ( a n [ c m 2 ] ) x @ 300 [us] K N T [ 1 0 1 6 c m - 3 ] 43-S10 (R2-C6) 123-S131 (R1-C5) 51-T132 (R1-C3) CE1 0.50 ±0.01 -12.8 77 2.5 2.5 0.5 CE2 0.27 ±0.02 -16.3 27 1.0 0.5 0.3 CE3 0.20 ±0.01 -17.2 13 0.5 0.4 0.3 To i n v e s t i g a t e s e m i - i n s u l a t i n g p r o p e r t i e s , substrate samples were prepared so that PDLTS measurements could be made. On each sample AuGe ohmic contact pads were defined. The separation of the pads was 50 um and the width of each pad 250 ym. 55 CE1 150 200 250 TEMPERATURE [K] Fig. 5.6 A CDLTS spectrum for 3 p i MESFET sample 123-S131 (R1-C5) CE1 Rate window = 25 ms Gate v o l t a g e = 0 to -2 V p u l s e CE3 CE2 57 L , , , 200 250 300 TEMPERATURE [K] Pig. 5.8 A CDLTS spectrum for 3 pm MESFET sample 51-T132 (R1-C3) CE1 1000/T [K-'] F i g . 5.9 A c t i v a t i o n energy p l o t f o r traps detected by CDLTS 59 60 PDLTS measurements were conducted using the system described i n Section 5.3. The temperature range i n v e s t i g a t e d was 100-330K. Rate windows were v a r i e d from 1 ms to 50 ms. An in t e r - p a d bias of 4 V and a l i g h t i n t e n -s i t y s u f f i c i e n t to give a peak photocurrent of 500 nA (at room temperature) were used. A PDLTS spectrum f o r sample 63-T42(A) i s shown i n F i g . 5.11. Five deep l e v e l s l a b e l l e d PI to P5 are re s o l v e d . The PDLTS spectrum f o r sample 82-S14(A) shown i n F i g . 5.12 shows the same f i v e l e v e l s but the r e l a t i v e concentration (peak height) of the PI to P2 l e v e l i n t h i s sample i s apparent-l y higher. Of note i s the f a c t that ingot 82 ( l i k e 51) was found by Cominco to be thermally unstable upon 850°C anneal (Table 5.2). Trap signatures are shown i n F i g . 5.13 and trap data l i s t e d i n Table 5.3. Table 5.2 - P r o p e r t i e s of Cominco GaAs Wafer Obtained From Cominco Wafer Assessed By Cominco R e s i s t i v i t y Before Anneal [tan] R e s i s t i v i t y A f t e r Anneal [ tan] 43-S10 43-S7 9.6 X 10 7 1.8 - 2.1 x 1 0 7 45-S93 45-S96 3.9 X 10 7 1 x 1 0 7 69-T42 63-T27 1.2 X 10 7 8 - 9 x 1 0 6 94-S13 94-S22 2.0 X 10 5 1.9 x 1 0 7 123-S131 123-S195 - 2.8 x 1 0 7 51-T132 51-T181 1.8 X i o 8 1.1 x 10 4 82-S14 82-S11 4.3 X 10 8 6.1 x 7.1 x 1 03 X10 P4 P3 P5 100 200 TEMPERATURE [Kl P i g . 5.11 A PDLTS spectrum f o r sample 63-T42(A) (Rate window = 10 TEMPERATURE [K] F i g . 5.12 A PDLTS spectrum f o r sample 82-S14(A) (Rate window = 10 ms) ON IS3 1000/T [K-'l •Fig. 5.13 A c t i v a t i o n energy p l o t f o r traps detected by PDLTS 64 Table 5.3 - Deep Levels Detected By PDLTS Label A c t i v a t i o n Energy [eV] T @ 300 K [s] Log( a n[cm 2]) Log( a p[cm 2]) PI 0.87 7.5 x 10-3 -8.6 -9.5 P2 0.50 7.3 x 1 0 - 3 -13.8 -14.6 P3 0.59 6.1 x 10-6 -10.3 -11.1 P4 0.38 5.3 x 1 0 - 6 -12.7 -13.5 P5 0.32 4.6 x 10-9 -12.6 -13.5 PDLTS and CDLTS trap signatures are compared i n F i g . 5.14 along w i t h v a r i o u s l e v e l s from the review of Mar t i n et a l . (1977) and Mitonneau et a l . (1977). P o s s i b l e a s s o c i a t i o n s are PI with EL12, P2 w i t h EL3, P3 with EL4, P4 w i t h HL6 and P5 with EL8. EL2, a very commonly reported trap i n bulk GaAs (Appendix A) was not detected i n t h i s work. CE1, CE2, and CE3 could not be i d e n t i f i e d w i t h any of the l e v e l s from the reviews (which report on traps detected by DLTS i n bulk and/or e p i t a x i a l GaAs) or with any of the PDLTS l e v e l s suggesting that the CDLTS l e v e l s are introduced during the implanta-t i o n annealing process. (A s i m i l a r conclusion has been made by Rhee et a l . , (1982) who detected a 0.52 eV e l e c t r o n trap i n S i implanted GaAs not detected i n the s u b s t r a t e ) . The complete l i s t of traps of M a r t i n and Mitonneau i s given i n Appendix C along w i t h the r e s u l t s of subsequent DLTS studies review-ed by t h i s author. 66 6. HYSTERESIS-FREQUENCY SPECTROSCOPY 6.1 Theory A u s e f u l procedure to study the h y s t e r e s i s e f f e c t seen i n the I-V c h a r a c t e r i s t i c s of GaAs MESFET's i s to vary the voltage sweep frequency. For sweep frequencies f » x - 1 (where T i s the time constant of the traps causing h y s t e r e s i s ) traps cannot respond to the change i n voltage so current looping can be expected to be n e g l i g i b l e . For sweep frequencies f « x - 1 traps can completely f o l l o w the change i n voltage so current looping can again be expected to be n e g l i g i b l e . Therefore, f o r a sweep frequency f « T - 1 current looping should be a maximum. Hystere s i s i n MESFET d r a i n current vs. gate voltage (I^-Vg) c h a r a c t e r -i s t i c s i s analyzed w i t h the f o l l o w i n g approximations and assumptions. We assume that there i s only one donor-electron trapping l e v e l i n the a c t i v e region of the t r a n s i s t o r . I t s concentration i s N^, where NT<<NQ ( N Q i s the shallow donor concentration of the n-type a c t i v e r e g i o n ) . Both traps and doping are taken to be uniform. When the d e p l e t i o n region i s expanded to i n c l u d e occupied and, hence, n e u t r a l t r a p s , t h e i r concentration i s assumed to s t a r t decaying e x p o n e n t i a l l y (as e l e c t r o n s leave them). As shown i n F i g . 6.1(a), a saw-tooth waveform i s used to sweep V^ l i n e a r l y from zero to -V , i . e . , V = -V t / t , where V i s the amplitude and J m G m m m t i s the period of the saw-tooth waveform. V_ i s assumed to r e t u r n to zero m o so r a p i d l y that the occupation of the traps i n the d e p l e t i o n region i s f r o z e n during t h i s process. (a) V 6 F R O M 0 T O -V, m (b) O + + +• + O O + + + + • • + + + + • W Wr, V G F R O M - V m T O 0 i ( 0 (d) + W m I O N I Z E D D O N O R T R A P N E U T R A L D O N O R T R A P S H A L L O W D O N O R F i g . 6 . 1 I o n i z a t i o n of traps i n the d e p l e t i o n r e g i o n due to the sweep of gate v o l t a g e w i t h a saw-tooth waveform (a) Saw«tooth v.Taveform (b) Concentration of i o n i z e d donors f o r V from 0 to - V (c) I o n i z a t i o n i n Schottky gate d e p l e t i o n r e g i o n (d*f Concentration of i o n i z e d donors f o r from *-V ;to 0. 68 The d e p l e t i o n width at zero gate b i a s , , corresponds to the b u i l t - i n voltage V ^ . For negative gate b i a s e s , the d e p l e t i o n width i s always greater than and the traps i n s i d e can hence be considered to be completely i o n i z e d , so that W. - • b l 1 where e i s the p e r m i t t i v i t y of the semiconductor. As the gate voltage changes from zero to V_, the d e p l e t i o n width increases to W ( F i g . 6.1b). The space charge concentration N(x) i n the region < x < W can be expressed as N(x) = N D + 6(x) , (6.2) where 6(x) i s the i o n i z e d trap concentration w i t h i n t h i s d e p l e t i o n r e g i o n . The r e l a t i o n between the d e p l e t i o n width W and the gate voltage can be found by s o l v i n g W V / N(x) xdx = - / G - dV . (6.3) W. o q x Since « N^, 6(x) i n Eq.(6.2) w i l l be much smaller than Np. Hence an i t e r a t i v e method can be used. At f i r s t , the i o n i z e d traps i n the d e p l e t i o n region < x < W are ignored, i . e . , the second term of Eq. (6.2) i s neglected. From Eq. (6.3). 69 2eV V N n V_ 1 / 2 n D m D T m Eq. (6.4) i s a f i r s t approximation to the r e l a t i o n between W and V . G The moment t at which po s i t i o n W starts to deplete can be obtained from Eq. (6.4) C = ( 2 W " ~ ^ N ^ N l ) Sn ' ( 6 ' 5 ) m m D T A better approximation of N(x) at V i n the region W. < x < W can then be made. Since the concentration of the neutral traps i n this region i s considered to be decaying exponentially, 6(x) of Eq. (6.2) can be expressed as 600 - » T ( l - e X p (- ( ^ - - I S l J ^ - J t . J / x ) ) . (6.6) m m m D T qN D The time when the gate voltage changes to V„ i s -V„t /V and the moment when G G m m pos i t i o n x depleted i s estimated with Eq. (6.5). Hence, N(x) can be obtained by s u b s t i t u t i n g Eq. (6.6) i n t o Eq. (6.2). This new N(x) i s substituted i n t o Eq. (6.3) the solu t i o n of which i s a closer approximation of the r e l a t i o n between the depletion width W and the gate voltage and can be written as qN V N N V t t qN^ V, . q D b i D T r ( G m n r r m r „ 9 4 D b i D ^ n x 70 VG „ NT • ~ \T t i" ^ ' ( 6 * 7 ) m D T qN D 1 / 2 N T V b ± N D By s e t t i n g L = w( ) , a = ^ - j - ^ - and 3 = — ^ p r ^ - , Eq. (6.7) can be m D T m D T s i m p l i f i e d to L 2 - 3 " a ( e x p ( ! ^ )) ( e x P ( - ^ ( L 2 ^ ) ) - ! ) ^ - - - ^ ( l - a ) . (6.8) m m m L, which i s r e f e r r e d as the normalized d e p l e t i o n width l a t e r , can be e s t i -mated as a f u n c t i o n of V„/V and t /T by using Newton-Raphson i t e r a t i o n . ti m m When the gate v o l t a g e reaches ~V m, the d e p l e t i o n width i s defined as W m w h i c h can be obtained by s u b s t i t u t i n g -V m t o V ^ i n Eq. (6.7). We now c o n s i d e r the r e t u r n of the gate voltage from -V to zero ( F i g . 6.1cf). The r e l a t i o n between the d e p l e t i o n width W' and the gate voltage c a n be obtained s i m i l a r l y by s o l v i n g W W' V / N(x) xdx = - / G - dV _ \ 7 1 (6.9) m Since the trap occupancy i s assumed to be frozen during t h i s process, N(x) can be obtained by s u b s t i t u t i n g Eq. (6.6) to Eq. (6.2) w i t h V Q = -Vm» The s o l u t i o n of Eq. (6.9) i s 71 L . 2 - I / 2 - a ( e x p ( - ^ ) ) ( e * p ( ^ (L 2-g) )-exp ( ^  ( L ' 2 - B ) ) ) i - - (l+ ^ ) m m (6.10) where qN D 1 / 2 L = w r — — i m m v 2 ev m and qND 1 " m L' can then be c a l c u l a t e d as a f u n c t i o n of V_/V and t / x. G m m The extent of h y s t e r e s i s observed i n the I - V c h a r a c t e r i s t i c s i s D G defined as the d i f f e r e n c e (Alp) between the current 1^ (when the gate voltage changes from zero to V„) and I' (when the voltage returns to t h i s V a f t e r G D L» reaching - V m ) . With the preceding f o r m u l a t i o n , the h y s t e r e s i s can be i n t e r p r e t e d as a consequence of the i n e q u a l i t y of L and L' at the same gate voltage because since 1^ i s considered to be p r o p o r t i o n a l to the channel width, AI-. i s p r o p o r t i o n a l to AL = L-L'. AL at V = - V has been u CJ Z m c a l c u l a t e d as a f u n c t i o n of x/t f o r d i f f e r e n t concentrations of deep l e v e l m traps ( F i g . 6.2a). F i g . 6.2b shows f i v e more curves of AL (at V g = - V m) vs. x/t w i t h d i f f e r e n t V values. These r e s u l t s suggest that the p o s i t i o n m m of the maximum of the curve, AL vs. T^ m> does not depend s i g n i f i c a n t l y on the values of N m and V i n the i n d i c a t e d range. The maxima of these curves 1 m which correspond to the maximum extent of h y s t e r e s i s at the i n d i c a t e d c o n d i t i o n s always occur at x/t =0.4. The occurrence of a maximum l o g i c a l l y m f o l l o w s the two q u a l i t a t i v e c o n s i d e r a t i o n s : (1) i f t - 1 « x the traps i n the F i g . 6.2 The d i f f e r e n c e ( L) between the normalized d e p l e t i o n width when V changes from zero to -W2 as a f u n c t i o n of n o r m a l l i z e d sweep frequency (a) f o r d i f f e r e n t N T (b) f o r d i f f e r e n t Vffi 73 d e p l e t i o n region can completely i o n i z e and (2) i f t - 1 » x the traps cannot respond to the sweep i n voltage and remain n e u t r a l . In both cases no h y s t e r e s i s r e s u l t s . AIQ can be measured experimentally by sampling and comparing the current 1^ and I' at the same V~. The r e s u l t a n t p l o t of Al,, vs. sweep frequency ( l / t m ) w i l l be r e f e r r e d to as an I-V h y s t e r e s i s spectrum (IVHS) by analogy w i t h DLTS. Since Al i s p r o p o r t i o n a l to AL, the frequency at which the spectrum peaks gives the time constant of the traps x * 0.4 t = (2.5f ) - l (6.11) m m In a d d i t i o n , the energy l e v e l of the traps can be estimated by measuring time constants at d i f f e r e n t temperatures and using Eq. (5.11). 6.2 Apparatus The system shown i n F i g . 6.3 was assembled to record the frequency behaviour of MESFET I^-V- h y s t e r e s i s . Waveform generator 1 (Servomex LF51) generates a voltage ramp to c o n t r o l the frequency of the (saw-tooth) waveform generated by waveform generator 2 (IEC F63) and a l s o d r i v e s the X-axis of a X-Y p l o t t e r (Moseley 135). The saw -tooth waveform i s input to the gate of the MESFET sample and a comparator. The other input of the comparator i s connected to a DC supply used to adjust the at which d r a i n current i s sampled. Two pulses are derived from the output of the monostable m u l t i v i b r a t o r s (MC 74121) and used to t r i g g e r the two LF398 sample and holds. Hence I n and I' are measured at a desired V„ and input to a d i f f e r e n t i a l F i g . 6.3 Experimental arrangement f o r h y s t e r e s i s measurements 75 a m p l i f i e r . The output, a voltage p r o p o r t i o n a l to AI^ i s sent to the Y-axis of the p l o t t e r . 6.3 Measurements To t e s t the h y s t e r e s i s model and apparatus, measurements were conducted on 30 ym MESFET 45-S93 R4-C3 as t h i s device (which was processed by Tektronix Corp., Beaverton, Oregon) di s p l a y e d prominent h y s t e r e s i s ( F i g . 6.4). A V m of IV, Vpg of 0.5V and sweep frequency range of 0-1 KHz were used. Sample temperature was v a r i e d from 300-350 K (using a Stratham SD6 oven). IVHS spectra are shown i n F i g . 6.5 r e v e a l i n g that A l ^ does indeed peak at a c e r t a i n frequency. The a c t i v a t i o n p l o t obtained from the IVHS spe c t r a ( c a l c u l a t e d v i a Eq.'s 6.11, 5.11) i s shown i n F i g . 6.6. A l s o shown i n F i g . 6.6 i s the a c t i v a t i o n p l o t f o r the sample determined by CDLTS measurements. I t i s evident that the IVHS and CDLTS data agree ( i . e . both r e v e a l the presence of a 0.4 eV ( e l e c t r o n ) trap) thus showing the usefulness of the IVHS method f o r studying h y s t e r e s i s i n GaAs MESFET's. • F i g . 6.4 I - V c h a r a c t e r i s t i c s f o r MESFET Do Do 45-S93 (R4-C3). Gate b i a s step = -0.5 V 77 FREQUENCY (Hz) F i g . 6.5 H y s t e r e s i s s p e c t r a f o r MESFET A 5 - S 9 3 ( R 4 - C 3 ) 78 F i g . 6.6 A c t i v a t i o n energy p l o t f o r MESFET 45-S93 (R4-C3) as obtained by h y s t e r e s i s and CDLTS measurements 79 7. SUMMARY AND CONCLUSION; The purpose of t h i s t h e s i s was to develop a GaAs MESFET process technology and t o o l s to assess GaAs and i n t h i s respect the f o l l o w i n g c o n t r i b u t i o n s have been made: 1. A GaAs MESFET f a b r i c a t i o n process based on d i r e c t s e l e c t i v e i o n im p l a n t a t i o n i n t o undoped LEC GaAs was developed which i s capable of producing 2-10 un MESFET's o p e r a t i o n a l to 3 GHz. 2. A t e s t device array was designed f o r use i n process, m a t e r i a l , and device c h a r a c t e r i z a t i o n and techniques f o r using the array demonstrated. The array should be u s e f u l f o r f u t u r e process development at U.B.C. and once a s u i t a b l e process has been e s t a b l i s h e d f o r r o u t i n e substrate monitoring by Cominco. 3. A channel conductance DLTS system was constructed and i t s use i n assessing a c t i v e l a y e r q u a l i t y shown. 4. A photocurrent DLTS system was constructed and i t s use i n monitoring substrate q u a l i t y demonstrated. 5. A technique f o r determining the deep l e v e l s responsible f o r h y s t e r e s i s i n GaAs MESFET's was developed. Several suggestions f o r f u r t h e r work are made: 1. Although the process developed was shown to be capable of producing o p e r a t i o n a l MESFET's improvements are required before GaAs MESFET IC's can be s u c c e s s f u l l y produced. In p a r t i c u l a r i t i s suggested that f o r fu t u r e GaAs MESFET f a b r i c a t i o n s that n + source-drain implants be used, that improved p h o t o l i t h o g r a p h i c equipment be obtained, and that 80 gate-source and drain-source spacings be minimized. The use of SigN^ f o r the encapsulant (now p o s s i b l e w i t h the recent a c q u i s i t i o n of a Plasmatherm PK1250) may improve a c t i v a t i o n as Eis e n et a l . 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(1976), "Study of E l e c t r o n Traps i n n-GaAs Grown by Molecular Beam Epit a x y , " J . Appl. Phys., £7, 2558. 29. Lehovec, K. and Zuleeg, R. (1980), "Analysis of GaAs FET's f o r Integrated Log i c , " IEEE Trans. E l e c t r o n Devices, ED-27, 1074. 30. L e s t e r , T.P. (1982), "A New Photon Counting Sensor Operating i n the Above-Breakdown Regime," Ph.D. Thesis, UBC. 31. L i u , S.G., Douglas, E.C., Wu, C P . , Magee, C.W., Narayan, S.Y., J o l l y , S.T., Kolondra, F., and J a i n , S. (1980), "Ion Implantation of S u l f u r and S i l i c o n i n GaAs," RCA Review, 41, 227. 32. Maki, D.W., E s f a n d i e r i a n d , R. and S i r a c u s a , M. (1981), " M o n o l i t h i c Low Noise A m p l i f i e r s , " Microwave J . , _24, 103. 33. M a r t i n , G.M., Mitonneau, A., Micea, A. (1977),"Electron Traps i n Bulk and E p i t a x i a l GaAs C r y s t a l s , " E l e c t r o n . L e t t . , JL3, 191. 34. M a r t i n , G.M. and B o i s , D. (1978), "An New Technique f o r the Spectroscopy of Deep Levels i n I n s u l a t i n g M a t e r i a l s A p p l i c a t i o n to the Study of Semi-I n s u l a t i n g GaAs," i n Semiconductor C h a r a c t e r i z a t i o n Techniques, P.A. Barnes ed., Electrochem. Soc. P r o c , 78-3, 32. 35. M a r t i n , G.M., Forges, J.P., Jacob, G. and H a l l a i s , J.P. (1980), "Compensation Mechansisms i n GaAs," J . Appl. Phys., _5_1, 2840. 36. M a r t i n , G.M., Jacob, G., Paiblaud, G., Galtzene, A. and Schwab, C. (1981), " I d e n t i f i c a t i o n and A n a l y s i s of Near-Infrared Absorption Bands i n Undoped and Cr Doped Semi-Insulating GaAs C r y s t a l s , " Defects and Radiation E f f e c t s i n Semiconductors, I n s t . Phys. Conf. S e c , 59, 281. 37. Mead, C.A. (1966), "Schottky B a r r i e r Gate F i e l d - E f f e c t T r a n s i s t o r , " Proc. IEEE, 54, 307. 38. Metz, E.P.A., M i l l e r , R.C. and Mozelsky, R. (1962), J . Appl. Phys., 33, 2016. 39. M i e r s , T.H. (1982), "Schottky Contact F a b r i c a t i o n f o r GaAs MESFET's," J . Electrochem. S o c , 129, 1795. 40. Mitonneau, A., M a r t i n , G.M. and Mircea, A. (1977), "Hole Traps i n Bulk and E p i t a x i a l GaAs C r y s t a l s , " E l e c t r o n . L e t t . , 13, 366. 41. N o t t h o f f , J . and Zuleeg, R. (1975), IEEE I n t . E l e c t r o n Devices Mtg. Dig. Tech. Papers 624. 42. P u c e l , R.A., Haus, H.A. and S t a t z , H. (1975), "S i g n a l and Noise P r o p e r t i e s of GaAs Microwave F i e l d E f f e c t T r a n s i s t o r s , " i n L. M a r t i n , Ed., Advances i n E l e c t r o n i c s and E l e c t r o n P h y s i c s , 38, Academic, New York, 195. 84 43. P u c e l , R.A. and Krumm, C.F. (1976), "Simple Method of Measuring D r i f t M o b i l i t y P r o f i l e s i n Thin Semiconductor Films," E l e c t r o n . L e t t . , 12, 240. 44. Rhee, J.K., Bhattacharya, P.K. and Koyama, R.Y. (1982), "Deep Levels i n Si-Implanted and Thermally Annealed Semi-Insulating GaAs:Cr," J . Appl. Phys., 53, 3311. 45. Sze, S.M. (1981), Physics of Semiconductor Devices, Wiley, New York. 46. Tserng, H.Q., Macksey H.M. and Nelson, S.R. (1981), "Design, F a b r i c a t i o n , and C h a r a c t e r i z a t i o n of M o n o l i t h i c Microwave Power FET A m p l i f i e r s , " IEEE Trans. E l e c t r o n Devices, ED-28, 183. 47. Udagawa, T., Higashiura, M. and Noko n i s i , T. (1980), " R e d i s t r i b u t i o n and Va p o r i z a t i o n of Cr Impurities i n Semi-Insulating GaAs," i n Semi-I n s u l a t i n g I I I - V M a t e r i a l s , Nottingham 1980, 108. 48. Van der Pauw, L . J . (1958), "A Method f o r Measuring S p e c i f i c R e s i s t i v i t y and H a l l E f f e c t of Discs of A r b i t r a r y Shape," P h i l . Res. Rep., _13, 1. 49. Van T u y l , R.L. and L i e c h t i , C.A. (1974), "High-Speed Integrated Logic wit h GaAs MESFET's," IEEE J . S o l i d - S t a t e C i r c u i t s , SC-9, 269. 50. Welch, B.M., Shen, Y., Zucca, R., Eden, R.C. and Long, S.I. (1980), "LSI Processing Technology f o r Planar GaAs Integrated C i r c u i t s , " IEEE Trans. E l e c t r o n Devices, ED-27, 1116. 51. Wisseman, W.R., Macksey, H.M., Brehm, G.E. and Sounier, P. (1983), "GaAs Microwave Devices and C i r c u i t s w i t h Submicron Electron-Beam Defined Features," Proc. IEEE, _71_> 667. 52. Yamasaki, K., Hamane, Y. and Kurumada, K. (1982), "Below 20 ps/Gate Operation w i t h GaAs Saint FETs at Room Temperature," E l e c t r o n . L e t t . , 18, 592. 53. Yuba, Y., Gamo, K. and Nambo, S. (1982), "Deep Levels i n Implanted and Laser Annealed GaAs Studied by Current and Capacitance-Transient Measurements," GaAs and Related Compounds, I n s t . Phys. conf. Ser., 63, 221. 54. Z y l b e r s z t e j n , A., Ber t , G. and N u z i l l o t , G. (1979), "Hole Traps and t h e i r E f f e c t s i n GaAs MESFETs," Gallium Arsenide and Related Compounds, I n s t . Phys. Conf. Ser., 45, 315. 85 APPENDIX A - Substrate Compensation Considerations The deep l e v e l believed to be responsible f o r compensating undoped LEC GaAs i s the so c a l l e d EL2 l e v e l ( Martin et a l . , 1977). This l e v e l which i s commonly detected i n GaAs i s a deep donor w i t h a thermal a c t i v a t i o n energy E^ of 0.75 eV below E c or more p r e c i s e l y (Martin et a l . , 1980) E c-E T(EL2) = 0.759 - [2.37 x 1 0 - V l ] T eV . I f EL2 does govern the compensation i n undoped LEC GaAs one may w r i t e from charge n e u t r a l i t y p + N, + + N + = n + N ~ ( A . l ) a ad a where n, p, N, +, N,"t and N - are the d e n s i t i e s of e l e c t r o n s , h o l e s , i o n i z e d J" r d dd a shallow donors, i o n i z e d deep EL2 donors, and i o n i z e d shallow acceptors, r e s p e c t i v e l y . To solve t h i s equation f o r n at room temperature one may assume that N J +«N, and N ~ «N .N/JT i s c a l c u l a t e d from d d a a dd N d d N d d = 1 + exp[(E F-E T)/kT] ( A , 2 ) where E„ i s the Fermi energy while n and p are governed by r n = N c exp[-(E c-E F)/kT] (A.3) 0 86 p = N exp[-(E -E )/kT] (A.4) v r v where N , N i s the e f f e c t i v e d e n s i t y of st a t e s i n the conduction, valence c' v J ' band. (N =4.7x10 1 7 c m - 3 and N =7.0x10 1 8 c m - 3 Sze, 1981). S u b s t i t u t i o n of c v (A.2) to (A.4) i n t o ( A . l ) y i e l d s n 2 + n(N -N.) - n. 2 N L _ = - exp[(E -E )/kT] (A.5) n 2 + n(N - N J - N J J ) - n . 2 n ° a d dd l Eq. (A.5) can then be solved f o r n (and p found from n^2=pn) and the conditions to achieve s e m i - i n s u l a t i n g behaviour determined. Johnson et a l . (1983), f o r example, have considered the case where N—11^=10 ^ cm - 3 a r l ( j j r ^ _ E^,=Eg/2 and found that s e m i - i n s u l a t i n g behaviour ( i . e . 10 6cm~" 3<n,p<10 8cm - 3) i s obtained when i s between 1.5x10 1 5 c m - 3 and 5 x l 0 1 8 c m - 3 which agrees w i t h the EL2 concentrations measured by o p t i c a l absorption by M a r t i n et a l . ( l 9 8 l ) . The o r i g i n and chemical nature of the EL2 l e v e l i s a subject of current debate. A Ga defect i s beli e v e d to be in v o l v e d but i t i s not c l e a r whether the defect c o n s i s t s of a s i n g l e Ga vacancy, a complex, or an a n t i s i t e defect but the a s s o c i a t i o n of the l e v e l to oxygen (a long held b e l i e f ) has r e c e n t l y been disproved by Huber et a l . (1979). The prevading b e l i e f i s that EL2 i s an a r s e n i c a n t i s i t e d e f e c t , A S g a (Lagowski et a l . 1982). I t has been found that the r e s i s t i v i t y of LEC GaAs depends c r i t i c a l l y on melt composition (Holmes et a l . , 1982). I f an a r s e n i c f r a c t i o n of 0.48 to 0.51 i s used, n type wafers of r e s i s t i v i t y above 10^ ton r e s u l t . I f , however, the a r s e n i c f r a c t i o n drops below 0.475 p type substrates of much lower 87 r e s i s t i v i t y emerge. These r e s u l t s are c o n s i s t e n t with the theory that i n a As r i c h melt a l a r g e number of Ga vacancies w i l l be present tending to favour EL2 formation. At high a r s e n i c f r a c t i o n s , >0.52, a l a r g e concentration of EL2 can be expected thus causing a drop i n r e s i s t i v i t y which was another observed r e s u l t . 88 APPENDIX B - Some Ion Implantation Processes Used For GaAs MESFET F a b r i c a t i o n Organization/ Reference A c t i v e Layer Implant Anneal Comments Species Energy Dose Temp. Time Cap F u j i t s u 28 S i 250 4.5x10 1 2 850 15 K i t a h a r a et a l . (1980) Hewlett-Packard 2 9 S i 230 5.5x10 1 2 850 30 S i 0 2 Hornbuckle and Van Tuyl (1981) Hughes 2 8 S i 100 5x10^2 850 30 S i 0 2 Maki et a l . (1981) NEC Furutsuka et a l . (1981) 3 0 S i 50 2.3x10 1 2 800 20 S i 0 2 -1.6x10 1 2cm 2 dose i s used to achieve enchance-ment devices. Rockwell S i 400 2.2x10 1 2 850 30 S i 3 ^ -implant i s done through 1100 A S i 3 N 1 + l a y e r . Welch et a l . (1980) -S 350KeV 1 0 1 3 c m - 2 n+ implant used a l s o . Texas I n s t r . Tserng et a l . (1981) 28 S i 850 30 -capless p r o x i m i t y anneal done. Westinghouse D r i v e r et a l . (1981) 2 9 S i 29S1 125 325 2x10 I 2 5x10 1 2 860 S i 3 N 4 -implants done through 1000 A Si 3N1+ l a y e r . 89 APPENDIX C - Some Deep Levels i n GaAs Detected by DLTS Reference Label Electron/ Em log a Association Material Hole [eV] [cm2] Lang and Logan E 0.86 -13.5 — Epi ( :LPE) Cr l e v e l (1975) E 0.89 -12.7 EL 2 Epi < I V P E ) H 0.78 -15.3 HL1 Epi ( :LPE) Cr l e v e l B H 0.71 -13.9 HL2 Epi :LPE) H 0.52 -15.5 HL3 Epi < :LPE) Fe l e v e l H 0.44 -13.5 HL4 Epi ( ;LPE) Cu l e v e l A H 0.40 -12.7 HL5 Epi ( ;LPE) Hasegawa et a l . H 0.58 -18.7 HL1 Epi ( ;LPE) (1975) H 0.64 -15.4 HL2 Epi < :LPE) H 0.44 -17.3 — EPI :LPE) Lang et a l . M4 E 0.48 -12.6 EL4 Epi ;MBE) (1976) M3 E 0.30 -13.8 EL7 Epi ;MBE) Ml E 0.19 -13.3 EL10 Epi ;MBE) Martin et a l . ELI E 0.78 -14.0 Bulk (1977) EL2 E 0.825 -12.9 Epi :VPE) EL3 E 0.575 -12.9 Epi ;VPE) EL4 E 0.51 -12.0 Epi ^MBE) EL5 E 0.42 -12.9 Epi :VPE) EL 6 E 0.35 -12.8 Bulk EL7 E 0.30 -14.1 Epi :MBE) EL8 E 0.275 -14.1 Epi ^VPE) EL9 E 0.225 -14.2 Epi ;VPE) EL10 E 0.17 -14.7 Epi :MBE) EL11 E 0.17 -15.5 Epi :VPE) EL12 E 0.78 -11.3 Epi :VPE) ELI 4 E 0.215 -15.3 Bulk EL15 E 0.15 -12.2 Epi EL16 E 0.37 -17.4 Epi :VPE) Mitonneau HL1 H 0.94 -13.4 Epi ^VPE) Cr l e v e l et a l . (1977) HL2 H 0.73 -13.7 Epi (LPE) HL3 H 0.59 -14.5 Epi ;VPE) Fe l e v e l HL4 H 0.42 -14.5 Epi ( V P E ) Cu l e v e l HL5 H 0.41 . -13.0 Epi 1 ;LPE) HL6 H 0.32 -13.3 Epi ( ;VPE) HL7 H 0.35 -14.2 Epi < ;MBE) HL8 H 0.52 -15.5 Epi ( ;MBE) 90 Reference Label Electron/ Erji log a Association Material Hole [eV] [cm2] Mitonneau HL9 H 0.69 -13.0 Epi (VPE) et a l . (1977) HL10 H 0.83 -12.8 Epi (VPE) cont'd HL11 H 0.35 -14.9 Bulk HL12 H 0.27 -13.9 Epi (LPE) Martin et a l . S2 0.74 -14.2 EL2 Bulk (HB) (1978) S3 0.57 -12.3 EL3 Bulk (HB) S4 0.35 -14.3 EL5 Bulk (HB) S5 0.34 -13.6 EL6 Bulk (HB) SI 0.80 -13.7 HL1 Bulk (HB) S6 0.27 -13.7 HL12 Bulk (HB) Fairman et a l . 0.48 -13.2 Bulk (HB) (1979) 0.48 -11.2 Bulk (HB) 0.35 -13.0 Bulk (HB) 0.22 -14.7 Bulk (HB) 0.75 -10.9 Epi (VPE) 0.55 -14.2 Epi (VPE) 0.55 -13.0 EL3 Epi (VPE) 0.46 -12.7 Epi (VPE) 0.34 -12.5 Epi (VPE) Zylbersztejn H 0.96 -12.8 HL1 Epi (VPE) et a l . (1979) H 0.71 -14.2 HL2 Epi (VPE) Jer v i s et a l . EL 2 Epi (LPE) (1979) HL2 Epi (LPE) HL5 Epi (LPE) EL2 Epi (implanted) HL2 Epi (implanted) HL3 Epi (implanted) HL4 Epi (implanted) HL5 Epi (implanted) HL7 Epi (implanted) EL7 Bulk (implanted) HL1 Bulk (implanted) HL3 Bulk (implanted) HL5 Bulk (implanted) Itoh and Yanai 0.75 -13.6 EL 2 Epi (VPE) (1981) 0.61 -11.8 EL3 Epi (VPE) 0.94 -13.3 HL1 Epi (VPE) 0.62 -14.1 HL3 Epi (VPE) 0.41 -14.9 HL4 Epi (VPE) Reference Label E l e c t r o n / Em l o g a A s s o c i a t i o n M a t e r i a l Hole [eV] [cm 2] Fairman et a l . E 0.26 -11.7 Bulk (HB) (1981) H 0.30 -13.2 HL12 Bulk (HB) E 0.34 -13.4 EL6 Bulk (HB) E 0.51 -12.0 EL4 Bulk (HB) E 0.65 -13.0 Bulk (HB) H 0.90 -13.7 HL1 Bulk (HB) E 0.15 -13.1 Bulk (LEC) H 0.30 -13.2 HL12 Bulk (LEC) E 0.34 -13.4 EL6 Bulk (LEC) E 0.60 -12.0 EL3 Bulk (LEC) E 0.65 -13.0 Bulk (LEC) H 0.90 -13.7 HL1 Bulk (LEC) Yuba et a l . 0.88 -12.3 ELI Bulk (HB) (1982) 0.54 -12.9 EL3 Bulk (HB) 0.48 -13.2 HL4 Bulk (HB) 0.34 -12.4 EL6 Bulk (HB) Rhee et a l . E 0.90 -11.7 Bulk (1982) H 0.85 -12.9 Bulk H 0.73 -16.3 Bulk H 0.17 -21.4 Bulk E 0.52 -17.9 Bulk (implanted) E 0.17 -22.3 Bulk (implanted) E 0.21 -20.5 Bulk (implanted) H 0.84 -12.9 Bulk (implanted) H 0.15 -22.2 Bulk (implanted) 

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