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Fabricating silicon mesh bolometers for BAM 2000

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F A B R I C A T I N G SILICON M E S H B O L O M E T E R S F O R B A M By Karen Chen B. Sc. (Physics) University of British Columbia, 1997 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF T H E REQUIREMENTS FOR T H E D E G R E E OF M A S T E R OF SCIENCE in T H E FACULTY OF GRADUATE STUDIES DEPARTMENT OF PHYSICS AND ASTRONOMY We accept this thesis as conforming to the required standard T H E UNIVERSITY OF BRITISH COLUMBIA February, 2000 © Karen Chen, 2000 In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of Physics and Astronomy The University of British Columbia 6224 Agricultural Road Vancouver, B.C., Canada V6T 1Z1 Date: Abstract Silicon membranes have been fabricated and etched into mesh structures using both wet and C l 2 plasma etching. The most repeatable process involoved wet etching triple bonded wafers with a buried oxide layer. A recipe to build Si meshes, with a grid spacing of 375 /im and leg cross-sections of 5 /im by 30 /im, from 5 /im thick membranes is described. The meshes are supported by 4 legs that are each 30 (j,m wide and 1 mm long. Also, the resistivity of thin gold films was measured for temperatures ranging from 4.2 K to 300 K. It was found that the ideal thickness, that leads to a sheet resistance of at 300 mK for of 5/im by 385/im gold lines, was 150 A. A bolometer building process that incorporates the gold evaporations with the mesh building procedure is given, although preliminary attempts to produce bolometers have been unsuccessful. ii Table of Contents Abstract ii Table of Contents iii List of Tables vi List of Figures vii Acknowledgments ix 1 Introduction 1 1.1 Bolometers 2 1.2 Impedance Matching to Free Space 4 1.3 Thermal Properties of the Bolometer 9 1.4 Responsivity 13 1.5 Noise • • 15 1.6 Bolometer Design and Constraints 20 2 Silicon Micromachining Basics 26 2.1 Photolithography 26 2.1.1 A Note on Mask Making 29 2.2 Wet Si Etchants 30 2.3 Plasma Etching 33 2.4 Metallization 34 iii 2.4.1 Metal Lift-off Process 36 3 Fabricating the Mesh Structure 38 3.1 Using Etch Stop Layers to Form Thin Membranes and Meshes 38 3.1.1 Heavily Boron Doped Si 39 3.1.2 Buried Oxide Layer 44 3.2 Forming Mesh Structures via Plasma Etching 47 3.2.1 Etching Mesh Structures 48 4 Resistivity Measurements of Thin Gold Films 51 4.1 The Resistivity of Thin Metal Films 51 4.2 Preparation of Thin Gold Films 53 4.2.1 Preliminary Test Runs 55 4.3 Au on Si 58 5 Conclusions 63 5.1 First Attempt at Using This Recipe to Build Bolometers 66 Bibliography 72 A Cleanroom Process Recipes 75 A . l RCA Clean* 75 A.2 Oxidation Recipe for a 0.3 jum Oxide Layer * 76 A.3 Boron Diffusion * 77 A.4 General Photolithography * 78 A.5 Metal Lift-off ** 79 A.6 The ECR PlasmaQuest System * 80 A.7 Ashing Photoresist with the Technics Plasma Etch II 81 iv A.8 E-Beam Evaporation Using the Balzers Evaporator ** 82 A.9 Thermal Evaporation in the B A M Lab Bell Jar 83 A. 10 Anisotropic Si Etch: EDP or T M A H * 84 A. 11 Oxide Etch: HF * 84 B Si Wafers and Processing Chemicals Suppliers 85 C N T D Ge Thermistors 86 v List of Tables 1.1 Specific Heats of Materials Commonly Used for Bolometers 13 1.2 Thermal conductance to the heat sink at 270 mK 24 1.3 Heat capacity of bolometer components at 270 mK 25 2.1 Etch rates and selectivity ratios for T M A H and EDP 33 3.1 BOX wafer specifications 45 4.1 Room temperature resistance of thin gold films on two different substrates. 56 C l Fitted values of R 87 vi List of Figures 1.1 Schematic drawing of the 1998 B A M bolometers 3 1.2 Infinite transmission line with a resistive short 6 1.3 A schematic diagram of the bolometer and the equivalent thermal circuit. 11 1.4 I-V curves for the bolometer used in the 1998 B A M flight 16 1.5 Modeling bolometer response to cosmic ray hits 17 1.6 Block drawing of bolometer noise sources 19 1.7 The number of cosmic ray hits during the 1995 B A M flight 21 1.8 The silicon micromesh bolometer design 23 2.1 Basic steps to photolithography 27 2.2 Bloated lines on masks generated with linotronic films 30 2.3 Hole geometries produced from wet etching silicon 31 2.4 Metal Lift-off lithography 37 3.1 First free standing mesh made from a heavily doped Si membrane . . . . 43 3.2 Thicker free standing mesh made from a heavily doped Si membrane . . 44 3.3 Free standing mesh made from a 6.5 //m Si membrane 46 3.4 Free standing mesh plasma etched from a 2.2 //m Si membrane 50 4.1 Gold path for thin film resistivity tests 54 4.2 Resistivity of gold films on different substrates 57 4.3 Resistivity of thin gold films at various temperatures 61 4.4 Film thickness dependence of the resistivity of thin gold films 62 vii 5.1 Basic steps to build a micromesh bolometer 65 5.2 Bolometer holder assembly 66 5.3 The bolometer at the output of a Winston cone 67 5.4 Gaps between the gold film and protective oxide 71 C . l I-V curves for NTD Ge thermistors at various temperatures 88 C.2 R(T) 89 C.3 Temperature sweep of thermistor biased with a constant current 90 C.4 Thermistor resistance vs applied magnetic field at 30 mK 91 C.5 Thermistor resistance vs applied magnetic field at 300 mK 92 viii Acknowledgments This thesis could not have been completed without the help of many people. In partic- ular, much of this work involved extensive use of cleanrooms at both UBC and at SFU. A special thanks must go to those at SFU: Bill Woods, Eva Czyzewska and especially Glenn Chapman for providing expert advice on silicon micromachining. During this project's initial stages, Glenn spent countless hours going over micromachining techniques with me and continued to provide useful advice for the duration of this work. Bill and Eva were indispensable for their knowledge and hands-on experiences with the finicky cleanroom equipment and also for sharing humorous stories during long work days in the cleanroom. Here at home, Mark Halpern gave me the opportunity to design and build a novel bolometer. This was a cool yet daunting project, but Mark was a great supervisor who was always encouraging and ready to give helpful advice on any problem, thesis related or not. Colin Borys and Chris Padwick should also be commended for managing to drag me out of my shell. I would also like to thank Mitzi for being the first person to actually ask to proofread this work while it was being written and for providing many stylistic comments. Saving the best for last, thanks to Chris White for always being there to console me when I was suffering from thesis woes and to celebrate with me after cleanroom breakthroughs. He always knows when to bring me chocolate. ix Chapter 1 Introduction The Balloon-borne Anisotropy Measurement (BAM) is designed to measure the tem- perature fluctuations, or anisotropies, in the cosmic microwave background (CMB) at medium angular scales. Such measurements can provide information about the basic nature of our universe, including its age, density and geometry. Unfortunately, these anisotropies from the CMB mean temperature of 2.7286 K are small; the signal level is a mere ^ « 10 - 5 . To be able to detect such small differences in temperature across the sky, any experiment must have very sensitive detectors. What makes B A M unique from other balloon-borne CMB experiments is the sensitive differential Fourier trans- form spectrometer (FTS), previously used to measure the CMB intensity spectrum from a sounding rocket [1, 2]. Housed within a cryostat at ~ 2 K so that there are no warm moving parts, the FTS measures the difference in intensity between two 0.7° regions of the sky separated by 3.6°. Each optical output of the spectrometer is independently coupled to a bolometric detector, held at 0.27 K, that measures the total power, inci- dent on it. Thus, each bolometer returns an interferogram proportional to the brightness difference between the two input beams [3]. This thesis describes a program to build novel detectors sensitive enough for the B A M experiment which are less sensitive to cosmic rays and could be frequency tunable. By using common micromachining methods many bolometers of this type could be made in one production cycle. The rest of this chapter is devoted to a brief discussion of bolometer theory and design. Chapter 2 describes the micromachining techniques that 1 Chapter 1. Introduction 2 were used in the fabrication process. Chapters 3 and 4 describe experiments to construct the substrate and absorption layer components of the bolometer while the final chapter describes a possible process to bui ld a fully functional bolometer. 1.1 Bolometers Bolometers are broadband thermal radiation detectors commonly used in astronomical applications to detect far infrared and millimeter wavelength radiation. They can be placed at the receiving end of a horn as the B A M experiment does, or at the end of a waveguide or in a focal plane, where the incident radiation wi l l be absorbed. The detection is made by measuring the the temperature changes in the absorbing material. They are different from other thermal radiation detectors in that they rely on a thermis- tor whose electrical resistance is heavily dependent on temperature. Once the incident power is absorbed, the temperature of the detector element rises causing a change in the thermistor resistance R. If a constant current or voltage is applied, the change in R can be measured (since it is easier to amplify small voltages, the B A M experiment uses the constant current configuration). Thus, the output of the detector is directly proportional to the bolometric intensity of the radiation incident on it . Some examples of thermistors include carbon resistors, heavily doped Ge and ion implanted Si [4]. For semi-conductor materials and superconducting films near T c , dR/dT < 0, while for metals, dR/dT > 0. Composite bolometers are composed of several key components that can be individ- ually tailored to provide optimal performance for various applications. In contrast, in monolithic bolometers, a l l the components are integrated into one structure so that the thermistor element is part of the substrate structure [4]. Those previously used on B A M , as shown in Figure 1.1, are composite bolometers consisting of a radiation absorbing bis- muth layer on a sapphire support structure and a neutron transmutation doped ( N T D ) Chapter 1. Introduction 3 Figure 1.1: A schematic drawing (not to scale) of the 1998 B A M composite bolometer, suspended inside a copper ring: a) nylon support legs b) sapphire substrate, c) thin bismuth film, d) N T D Ge thermistor, and e) brass electrical leads. germanium thermistor [5]. The bolometer is suspended wi th in a copper r ing by 4 twisted pairs of nylon surgical threads. For an effective bolometer, the radiation absorber should have a large absorptivity over the desired frequency range and be of an appropriate size for the optical system. A s well, the thermistor's electrical resistance should have an strong temperature dependence and have low electrical noise. The supporting substrate should not only be mechanically rigid and have a large thermal conductivity so that it remains isothermal during operation, but also, it should be thermally isolated from its surroundings. The mechanical support for the device should have low thermal conduc- t ivi ty and provide a weak link to the heat sink. A l l of the above components should have a low heat capacity to reduce the thermal time constant of the device. The next four sections wi l l briefly describe how the bolometer responds to incident electromagnetic waves. Chapter 1. Introduction 4 1.2 Impedance Matching to Free Space When radiation is incident on the bolometer, its initial function is to absorb as much power as it can and dissipate it thermally. Since the absorber is typically a thin metallic film, whose thickness is much thinner than a mm wavelength, deposited on a dielectric substrate, the optical properties of this system are easily described by comparing the bolometer to a resistive short in a transmission line. The reader is directed to Ulrich's article on the far infrared properties of metallic mesh structures [6] for greater detail. Imagine a transmission line composed of two slightly separated parallel conductors along the ^-direction connected by an AC source. There is a capacitance C and induc- tance L per unit length of the wires. As the circuit is driven by an AC signal, the time varying current produces a counter emf dV proportional to the inductance, which in turn produces a current dl since the wires are also coupled by their capacitance. That is, dV = ^ d z = -Ldz%, (1.1) oz ot dl = —dz = -Cdz^-. (1.2) oz ot These two equations lead to the following coupled differential equations, Differentiating (1.3) with respect to z and (1.4) with respect to t gives, d2V d2I dz2 dtdz' Chapter 1. Introduction 5 and d2I d2V - C ^ - (1-6) dzdt dt2 ' Substitution of (1.5) into (1.6), or vice versa leads to two second order differential equations that are easily recognized as one dimensional wave equations for the voltage and the current: d2V d2V = L C ^ , (1.7) dz2 dt2 ' d2I d2I 2 The propagation speed of the current and voltage down the line is just v  — 1/LC or, 1 (1-9) The solution to (1.7) is a superposition of two traveling waves, V{z,t) = V- + V+, (1.10) where V_ = V-(t + z/v) describes a wave moving to the left and V+ — V+(t — z/v) describes a wave moving to the right. To find I(z,t), use (1.3) and differentiate V(z, t) with respect to z, then integrate with respect to t. This gives I{z,t) = \ ( V + - V . ) . (1.11) vL In order to get the characteristic impedance of the transmission line Zt, one only needs to take the ratio between V and / for either of the traveling waves. Then, Chapter 1. Introduction 6 If the line is terminated by a load whose impedance matches Ze, then the signal will not be reflected by the load, but instead, all the power will be transferred to the load. Now consider a resistive load with impedance ZL shorting an infinite transmission line as in Figure 1.2. Since the load acts like an impedance in parallel with the line, the equivalent impedance ZT of the circuit becomes, ZT = - £ % r . (1.13) Z L Figure 1.2: Infinite transmission line with a resistive short. A signal, I0 traveling down the line, once encountering the short, will be partially reflected, IR, and partially transmitted, IT past the load to the remainder of the line. The voltage 14, is the sum of the reflected and transmitted waves, that is, V0 = Vt- Vr. (1.14) What is of interest is the power dissipated in the load. The current through the load IL is given by: Chapter 1. Introduction 7 h = ^ , (1.15) AL IL = h + I r - I t (1-16) (1.17) Vo Vr + Vt Zt Zt where V~L=Vt since the drop across the load is the same as the drop across the rest of the line. Substituting (1.14) into (1.15) and (1.17) leads to, K = _ V r ^ E ± ^ ( 1 . 1 8 ) £L ^L^I The ratios Vr/V0 and Vt/V0 are useful quantities called the reflection and transmission coefficients p and r respectively and r — p = 1. From (1.18), 2 Z l (1.20) 1ZL + Zt The fractional reflected power is the ratio JPR = PR/P0, where PR = V?/Zt is the power in the reflected wave and P0 = V2/Zt is the power in the source signal. It can be immediately seen that PR- % = P 2 . (1-21) Similarly, the fractional transmitted power PT — r2. From conservation of energy, the power dissipated through the load, PL is PL = l - p 2 - r 2 (1.22) Chapter 1. Introduction 8 Combining (1.19), (1.20) and (1.22) lead to the following equation for PL in terms of ZL and Zt, ^ - ( J r r i (L23) The value of ZL which maximizes (1.23) can be found with first year calculus, Ze{Ze - 2ZL) = 0. (1.24) dPL dZL Thus, A quick check with the second derivative shows that ZL = Z^/2 is in fact the max- imum. Clearly, to maximize the power dissipated in the load, its impedance should be half the transmission line impedance. Returning to (1.19), (1.20) and (1.22), one finds that half of the signal power is dissipated in the load, while a quarter is reflected arid the remaining quarter is in the rest of the line. Electromagnetic waves traveling through free space and encountering the absorbing layer of the bolometer at normal incidence can be thought of as signals encountering parallel admittances on a transmission line. In fact, this optics system is completely analogous to the shorted transmission line described above, and one only has to replace V with the electric field Ex, I with the magnetic field By, L with /x0 and finally C with e0. Then, the wave equations for the optics case is just the results of Maxwell's equations for the electric and magnetic fields traveling through free space: d2Ex d2Ex ~dz2~ = £ofi°-W> ( L 2 6 ) Chapter 1. Introduction 9 a*. " at* • [ } The propagation speed is just v = = c which is the speed of light in a vacuum. The impedance of free space, ZQ is given by (1.12) with the proper substitutions, giving Z0 = M (1.28) = 377 a So, for the bolometer to absorb the maximum amount of power, its absorbing medium should have an impedance of Zboio = Z0/2 = 188.5 Q. If the absorbing medium consists of a metallized mesh made up of N x iV leg segments with each leg having an impedance Zi, the impedance of the entire mesh, Zmesh,, can be calculated. If a voltage is applied from one side of the mesh to the other, there are iV legs in series and N legs in parallel so that = Zt. (1.30) Therefore, each metallized leg of the absorbing grid in our bolometer should have an impedance of 188.5 Q. The above works well for meshes with a grid spacing much less than the wavelengths being detected and so it is possible to build frequency tuned bolometers [16]. 1.3 Thermal Properties of the Bolometer As the bolometer absorbs power from some radiant source P 7 = PQ + Pi(t), where P0 is time independent and P\{t) is the time dependent part, the temperature of the bolometer Chapter 1. Introduction 10 will vary, TB = T 0 + Ti(t). The electrical power input to the constant current biased thermistor varies since the resistance depends on TB. To first order, PR = I2R(T0) + I2 (dR/dT)Ti(t). Some power will be stored in the heat capacity, Pc = CdTB/dt — CdTi/dt while the rest flows through a thermal link with conductance, G(T), to the heat sink held at temperature T S . To first order, PG = G(T)(T0 - T S ) + %TX. The thermal circuit is sketched in Figure 1.3 and can be written as: P. + P^O + ^WT.J + ^T,) = G(TJ(T„-Ts) + G D T 1 + C ^ - . (1.31) GD = dP/dT is the dynamical thermal conductance which arises since the thermal conductivity changes rapidly with T at low temperatures. From the time independent terms of (1.31) one arrives at the steady state heat flow equation where the bolometer is in thermal equilibrium with the heat sink and a constant background power loading P0. P0 + I2R(T0) = G(T0)(T0-TS) (1.32) The time dependent terms give W ) - C ^ = T1(t)(GD-I2^). (1.33) Thus, the temperature change 7\ is influenced by the thermal feedback from the thermistor element. Defining 1 d R n *A\ a=RdT> ( L 3 4 ) (1.33) can be rewritten as Pi(t) - C ^ = Tx{t)(GD - aP0). (1.35) Chapter 1. Introduction 11 \ ^R(T 0) + r(dPx/dT)T1(t), P(t)=P0+ ?,(!) dT, dt G(T)(TB - T s) / / / / / / / / / / / / Legs Wires r d T . u dt Heat sink Figure 1.3: A schematic diagram of the bolometer and the equivalent thermal circuit. Chapter 1. Introduction 12 The quantity GD — OLP0 is sometimes called the effective thermal conductance Ge. For neutron transmutation doped (NTD) germanium thermistors, a < 0 and so Ge > Go- Rewriting (1.33), the resulting first order differential equation is just, dT C^- + GeT1(t) = P1(t). (1.36) If the radiant power is constant, Pi(t) = 0, with the initial condition Ti(0) = T", X" >Ta, then the solution to (1.36) is simply Ti(t) = T'e'^K The time it takes for the bolometer temperature to decay to 1/e of its peak value is r = C/Ge. This quantity is called the characteristic thermal time constant of the device. For a sinusoidal power input P\(t) = pelult, the solution to (1.36) is ™ = G ^ C E " < L 3 7 ) Both C and G depend on the physical properties of the material and its tempera- ture. The heat capacity is a product of the body's mass m and the specific heat «(T), where K(T) = 7 T + 3T* for metals and K{T) = BT3 for insulators. Here, 7 is the electronic contribution to the material's heat capacity and B is the lattice contribution due to phonons. Table 1.1 shows estimated specific heats for materials typically used in bolometer construction. The thermal conductance is proportional to the cross-sectional area A through which the heat flows, and inversely proportional to the length /, so that G = k(T)A/l, where k(T) is the thermal conductivity of the material. However, since for some materials k(T) depends rapidly on T, especially at low T, it is common to define and use the average thermal conductance, G = [TSk(T)dT (1.38) Chapter 1. Introduction 13 Material 7 (J/cm 3 K 2 ) (J/cm 3 K 4 ) K(0.270) (J/cm 3 K) Pd 1.1 x IO"3 1.1 x 10~5 2.97 x 10~4 Au 6.8 x IO"5 4.5 x IO"5 1.92 x 10~5 Ge 2.0 x IO"9 3.0 x IO"6 2.93 x IO - 7 Brass 9.7 x IO"5 7.9 x IO"6 2.63 x 10~5 Bi 3.8 x 10~7 5.3 x IO"5 1.15 x 10~6 Ti [7] 1.6 x 10~5 1.2 x 10~7 4.32 x 10~6 Si [8] 2.1 x IO"5 6.8 x IO - 6 8.78 x IO"8 Si0 2 [9] - 3.7 x 10~5 7.28 x IO"7 Table 1.1: Estimated specific heats for materials commonly used in bolometers. «(T) = jT + BT3 (from [10] unless otherwise noted.) At cryogenic temperatures, most of the thermal transport in insulators is carried by phonons and k(T) oc T 3 . On the other hand, in pure metals, electrons carry most of the heat current and k(T) oc T. In this last proportionality there is a nearly universal value for how the proportionality constant scales with electrical conduction given by the Wiedemann-Franz law, = CoT. (1.39) C — 25 nWf2/K 2 is the Lorentz constant and a = cr(T) is the electrical conductivity. This relation allows one to calculate the thermal conductivity of a metal after measuring its electrical conductivity at temperature T. 1.4 Responsivity The absorbed power responsivity of a bolometer is denned to be the change in voltage per watt of absorbed signal power, i.e., SA — V\/P\. Since Vi = I{dR/dT)T\ and given Chapter 1. Introduction 14 (1.36), one can write Another useful quantity that is more easily measurable is the electrical responsivity, SE — V/PE, which characterizes how the bolometer responds to changes in the electrical power dissipated in the thermistor. Rewriting (1.40) in terms of the voltage V across the resistor, Assuming there is no radiant power on the bolometer (although the result is valid if there is a constant background power loading P0 [11]) and using dV = d(IR) = Rdl+IdR and dP = d(IV) = 2VdI + PcxdT = GdT, one can solve for dV and dl. Letting Z = dV/dl, Solving for G, dV = Rdl + VadT (1.42) - aP G = aP^±4 (1-45) Z - R = !2dA^±A, (1.46) dT Z - R v ' and substituting (1.45) into (1.41), Chapter 1. Introduction 15 SE — Z - R 2IR (1.47) I-V curves for one of the composite sapphire chip bolometers we made for the 1998 B A M flight are graphed in Figure 1.4. The resistance R — V/I depends on the temperature (as can be seen from the upper two curves of the bolometer held at slightly different tempera- tures.) and on the radiative load (comparing the lower two curves for the bolometer held at the same temperature). Thus, if the bolometer is cooled to its operating temperature and one measures its I-V curve, SE can be determined for various bias currents. As well, once R{T) is known, G(T) can be calculated from (1.46). By changing the bias current with a large step function and observing the resulting voltage change, one can measure r and hence arrive at a value for C. To determine the time constant of the same bolometer used in the 1998 B A M flight, we examined the detector response to 3 normalized cosmic rays hits. The optical system and electronics of the experiment was modeled and fitted to the 3 cosmic rays. The solid line in Figure 1.5 is the model with a time constant of ~5.5 ms, which seems to fit the detector response fairly well. The tail end of the response is set by filters in the electronics which were not included in the model. 1.5 Noise It is useful to scale the various noise sources in a bolometer by the appropriate sensitivity and express the quadrature sum as the noise equivalent power, or NEP. This is the incident power which produces a signal equal to the noise in a one Hz bandwidth. The dominant sources of noise in bolometers, as shown in in Figure 1.6, include Johnson noise, amplifier noise, and phonon or thermal fluctuation noise. For greater detail on the noise terms presented here, the reader is directed to Mather's articles [12, 13]. Other Chapter 1. Introduction 16 i i i i I i i i i I i i r J i i i i I i i i i I i i i i L_ 0 10 20 30 Bias Current (nA) Figure 1.4: I-V curves for one of the sapphire and NTD Ge chip bolometers used in the 1998 B A M flight. Bolometer cooled to T=0.263 K and looking at a cold load calibrator (*), bolometer cooled to T=0.269K and looking at the same cold load (•), bolometer cooled to T=0.269 K looking at the room (x). Solid lines are not fits but are just to lead the eye. Chapter 1. Introduction 17 Figure 1.5: Modeling the 1998 flight bolometer's response to cosmic ray hits to de- termine the thermal time constant. The lines are for the model with r = 4ms( ), r = 5.5ms(—), r = 6ms (-• • •) and three different cosmic ray hits (A,0,x) occurring at t = 0. Chapter 1. Introduction 18 contributions to the noise include cosmic rays and microphonics. In simple bolometer theory, the Johnson noise, from voltage fluctuations in the resis- tive thermistor element arises in the form NEP] — Vj/S2 = AkBTR/S2. However, this ignores the electrothermal feedback since the bias current does work on the Johnson noise source. Since any increase in Vj increases the temperature of the bolometer, which lowers the resistance and decreases the output voltage, the Johnson noise is actually reduced by as much as 60% [12]. This can be described by the equivalent Johnson noise source, V'j = Vj{Z + R)/2R = y/\kBTR{Z + R)/2R. Thus, combined with (1.47), NEP] = 4 k B T p ( ^ ± ^ 2 . (1.48) The noise in the first stage of amplification, at the amplifier input, is described by NEP2 = (V2 + (IaR)2)/S2. In order for the noise in the amplifier to be unimportant, the temperature TN at which the NEPa = NEPj should be less than the operating temperature of the bolometer. Because the bolometer is connected to a heat sink at temperature Ts via an average thermal conductance G, there are energy fluctuations in the bolometer caused by traveling phonons or electrons. When the system is in thermal equilibrium, the noise fluctuations are described by, NEP2honon = AkBT2G. (1.49) If there is a large responsivity S, then both NEPj and NEPa become negligible, and the phonon noise term dominates the total NEP of the bolometer. Another concern in balloon borne CMB experiments is the bolometer's sensitivity to cosmic ray hits in the upper atmosphere. These hits leave power spikes in the data and are a major source of noise. Figure 1.7 shows the number of cosmic ray hits during the Chapter 1. Introduction 19 To Pre-amplifier with noise: i NEPa2= Va2 + (IaR)2 Figure 1.6: Block drawing of bolometer noise sources. Chapter 1. Introduction 20 1995 B A M flight. The float altitude was 41.5 km and remained at that position for 4 hours, for which 8.7% of the data was lost due to cosmic rays. Notice that there are many cosmic ray hits in every minute of the flight, posing a large data editing problem. An improvement then would be to reduce the geometric cross-section (also lowering the total heat capacity) of the radiation absorber without compromising the sensitivity of the device. 1.6 Bolometer Design and Constraints On its previous two flights, B A M used bolometers that were individually hand-made (see Figure 1.1) with a 200 A layer of evaporated bismuth on a solid sapphire chip suspended by surgical nylon threads. The thermistor element was a 250 /im cube of neutron trans- mutation doped (NTD) germanium whose resistance near 0.3 K is heavily dependent on temperature. This was glued to the non-metallized side of the sapphire with a trace amount of epoxy. The electrical connection consisted of 0.0003" diameter brass leads which were indium soldered to gold pads on opposing sides of the NTD Ge chip. Several improvements can be made to this bolometer design. As previously mentioned, these detectors are subject to cosmic ray hits whose effects can be reduced by decreasing the geometric cross-section of the device. This can be achieved by fabricating web or mesh structures that have grid spacings suitable to the appropriate wavelengths to be measured. Previously, the B A M bolometers used solid sapphire chips and NTD Ge thermistors which have volumes of 3.1 x 108 jum3 and 1.7 x 107 jttm3 respectively. A 16 mm2 mesh with 40 /mi wide and 5 /im thick lines effectively reduces the cosmic ray cross-section by a factor of ~20. Reducing the volume of the mesh further does not significantly reduce the cross-section to cosmic rays due to the presence of the thermistor. Also, the current composite bolometers are individually hand-made, leading to devices Chapter 1. Introduction 120 F = i 1 r I 100 CD +-> •S 80 cu cu OH P o u 40 cd PH O • i—t 6 § 20 u n 1 1 r n 1 r T 1 1 1 r _1 I I I I I I I I I I I I 1 L J I l_ 10 20 30 Alt i tude (km) 40 Figure 1.7: The number of cosmic ray hits during the 1995 flight. [14] Chapter 1. Introduction 22 with slightly different characteristics depending on the craftsmanship, and having a longer production time. It would be preferable to build many bolometers, all with identical characteristics, in one production cycle. This is possible if one applies micromachining techniques to bolometer construction. Such improvements have already been made by Mauskopf et al. using a S13N4 mem- brane lpm thick etched into a spiderweb pattern [15]. Generally, however, S13N4 pro- cessing capabilities are less accessible whereas most cleanrooms support basic silicon processing techniques. If Si wafers are used, one could also develop tuned bolometers that are frequency selective [16]. Thus, it is of interest to build micromesh bolometers from easily obtainable silicon wafers. The proposed design is shown in Figure 1.8. The center grid will be patterned from a free-standing silicon membrane held in place to a surrounding silicon frame (the heat sink) by four silicon legs. A thin (~200 A) metal layer will be evaporated onto the grid area to act as the radiation absorber, while the NTD Ge thermistor is glued to the center of the mesh on the side opposite the gold layer. Two brass electrical leads will run from the thermistor to gold contact pads located on the Si frame. From the previous noise and responsivity discussions, one can design a bolometer optimized for the B A M experiment. The maximum noise at the bolometer input is NEPmax = 10 _ 1 6 W /Hz5 . Since this quantity is dominated by the phonon noise, (1.49) gives an upper limit for the thermal conductance to the heat sink, held at 0.27 K, to be G — 2.48 x 10~9 W / K . The thermal conductivities of brass and silicon are 2 x 10 - 3 W/cmK [9] and 2.4 x IO - 5 W/cmK [17] respectively (see Table 1.2). If the same NTD Ge ther- mistors are used on the mesh bolometers, then the two 4 mm long, 0.0003" diameter brass leads dominate the thermal conductance with GBrass = 4.5 x 1 0 _ 9 W / K . This exceeds the noise budget and leads to a total NEPBrass = 1.4 x 1 0 _ 1 6 W / H z 2 . A sim- ilar calculation for 4, 1 mm long Si support legs does not add significantly to the total Chapter 1. Introduction 23 Figure 1.8: The proposed Si micromesh bolometer design to detect the CMB. The entire device is 10 mm2. The bolometer element is an NTD Ge thermistor with ~4mm long brass electrical leads while the absorbing layer consists of a Au grid with R = 188 Q/O. Chapter 1. Introduction 24 thermal noise if the cross-sectional area of each leg does not exceed 150 p,m2. This up- per limit contributes Giegs = 1.44 x 10 - 9 W / K and brings the phonon noise total to NEPphonon = 1.55 x 10- 1 6 W /Hz2 at 270mK. The value of k for thin legs of Si is less than the bulk value since the mean free path of the phonons is greater than the leg di- mensions [17]. If this was not the case then the Si support legs would have to undergo ion bombardment to destroy the crystal structure. It is possible to reduce the total phonon noise by increasing the length of the brass wires or by forming gold contact lines on the substrate to which the thermistor could be attached. Material k(0.27) (W/cmK) Dimensions (cm) A/i (cm) # G270mK (W/K) w or r t e Brass ^support leg Si&uZfc 2.0 • 10~3 2.4 • 10-5[17] ~ 4 •IO" 4 3.8 • IO"4 3.0 • IO"3 3.0 • IO"3 5.0 • IO"4 5.0 • IO"4 0.4 0.1 0.1 1.1 • 10~6 1.5 • IO"5 1.5 • IO"5 2 4 4 4.5 • IO"9 1.4- IO"9 ~ 2•10~8 Simes/i leg Au m e s / j ieg 2.4 • 10-5[17] 1.8 • IO"3 3.0 • IO"3 5.0 • IO"4 5.0 • 10~4 1.5 • IO - 6 0.4 0.4 3.75 • 10"6 1.9- IO"9 1 1 9.0 • IO" 1 1 3.4 • IO" 1 2 Table 1.2: Estimated thermal conductance at 270 mK, for bolometer components with the listed dimensions. Values of k from [9] unless otherwise noted. To keep the thermal time constant lower than r = 5.5 ms, the total heat capacity of the bolometer cannot exceed Cmax = 0.0055 x 6.0 x 10~9 J /K= 3.3 x 10~ n J /K . Using the data in Table 1.1, one can estimate the heat capacity of each bolometer component, at 270 mK as shown in Table 1.3. Clearly the thermistor and brass leads dominate the heat capacity of the entire device, however the total heat capacity is well below Cmax and r « 2 ms. When determining the particular dimensions of the remaining bolometer components, the only constraint is to keep the cross section of the support legs under 150 /ma2. From researching micromachining techniques, fabricating Si membranes with thicknesses of the Chapter 1. Introduction 25 order of a few microns seemed fairly common. So, the initial thickness of the support legs was taken to be 5 /mi, leading to a width of 30 pm. Material K Dimensions (cm) Volume # (J/ccK) w or r I t (cc) (J/K) Pd 2.97 • IO"4 0.025 0.025 2.0 • IO"6 1.25 • IO"9 2 7.43 • IO" 1 3 Au 1.92 • 10~5 0.025 0.025 2.5 • IO"5 1.56 • 10~8 2 6.00 • IO" 1 3 NTD Ge 2.93 • 10~7 0.025 0.025 0.0275 1.72 • IO"5 1 5.03 • IO" 1 2 Brass 2.63 • IO"5 3.8 • IO"4 0.4 - 1.82 • 10- 7/2 2.9 • IO"9 2 4.80 • IO" 1 2 Bi * 1.15- IO"6 3.0 • IO"3 0.4 2•IO" 6 22 6.07 • IO" 1 4 Au 1.92 • IO"5 5.0 • IO"4 0.4 2•IO" 6 4.0 • IO" 1 0 22 1.69 • IO" 1 3 Ti * 4.32 • IO"6 5.0 • IO"4 0.4 5•IO" 7 1.0- 10~10 22 9.50 • IO" 1 5 ^support 8.78 • IO"8 3.0 • IO"3 0.1 5.0 • IO"4 1.5- IO"7 4 5.27- IO" 1 4 Simes/i leg 8.78 • IO"8 3.0 • IO"3 0.4 5.0 • IO"4 6.0 • IO"7 22 1.16- IO" 1 2 Si0 2 * 7.28 • IO"7 3.0 • IO"3 0.4 3.0 • 10~5 3.6 • IO"8 22 5.77 • IO" 1 3 Table 1.3: Estimated heat capacities of bolometer components at 270 mK with the listed dimensions. The first three materials form the thermistor element. Materials marked with * are not used in the final bolometer design. Several constraints were considered in the initial mesh structure design. The overall size of the mesh needs to be at least the area of the optical output of the Winston cones (9.6 mm2) and have a suitable grid spacing to absorb millimeter wavelengths. The mesh was chosen to be a square with 16 mm2 and a grid spacing of 385 /mi. The widths of the mesh legs were kept at 30 pm, to remain consistent with the width of the support legs. The thickness of the mesh should be the same as that of the support legs. These dimensions are not at all engraved in stone and, as will be seen in later chapters, the structural dimensions were varied, but kept within the noise parameters, as different micromachining processes were performed. The dimensions of the Au absorbing layer are addressed in Chapter 4 as is the question of whether or not to include an insulating Si02 layer and a Ti adhesion layer. Chapter 2 Silicon Micromachining Basics Micromachining techniques provide a reproducible process for fabricating three dimen- sional microstructures from single crystal silicon wafers (SCS). Here the basic processes involve photolithography, anisotropic etching and metallisation. Note that all process parameters and recipes used in this thesis are included in more detail in Appendix A. 2.1 Photolithography Photolithography uses photoemulsion techniques to create three dimensional structures from a substrate. A masking layer of light sensitive photoresist is exposed with UV light to a particular pattern from which structures can be defined. These structures are commonly formed by subtractive or additive pattern transfers as illustrated by Figure 2.1. In the subtractive method, the film to be patterned is first grown or deposited onto the SCS. Then, the pattern is etched into the film using photolithograpy. The additive process involves the same lithographic steps, but in the reverse order; that is, the masking resist layer is first patterned on the SCS followed by the film deposition. Afterwards, the photoresist layer is stripped, lifting off the undesired film deposits and leaving the desired pattern behind. The two processes could be used to reach identical final states, but more often, they lead to two different final states as in Figure 2.1. Generally, the subtractive method is used more often in SCS processing, but in both cases, photolithography defines the shape and the precision of the final structure. 26 Chapter 2. Silicon Micromachining Basics 27 Figure 2.1: Basic steps to additive or subtractive photolithography. (a)Grow or deposit the film to be patterned. (b)Apply photoresist. (c)Soft bake. (d)The mask is aligned and exposed. (e)The exposed resist is removed. (f)Hard bake. (g)The exposed film is etched or (g') another layer is deposited, (h)Photoresist removal. Chapter 2. Silicon Micromachining Basics 28 Figure 2.1 shows the cross-section of a wafer during the basic eight steps of pho- tolithography when used as either part of a subtractive or additive pattern transfer process. Step (a) shows a SCS wafer with a thermally grown layer of Si02 that is ready to be patterned. First, a thin layer of photoresist, a few microns thick, is spun unto the wafer as in (b). The resulting resist thickness depends on the type of resist, time and rotational speed. After the wafer is lightly baked at 100°C (c) to promote resist adhesion and to remove solvents in the resist, a mask (analogous to a negative in photography) is precisely aligned to the wafer. The wafer is then exposed to ultraviolet light through the mask as in (d). The resist which is exposed to the UV light is polymerised and then removed in the developer (e), while the unexposed portions remain. Then in (f), the wafer is baked again, this time at 120°C to harden the remaining resist. The exposed areas are then inspected under the microscope. If there are resist residues on the oxide or other resist defects, then the photoresist is stripped in acetone, and steps (a) through (f) are repeated. Once it is determined that the pattern is correctly masked into the resist layer, step (g) is performed, (g) shows the result of a subtractive process where the wafer is placed into a wet or dry etch process so that the exposed areas of the oxide are etched. On the other hand, an additive process, such as metallisation, is shown in (g') where a metal has been deposited over the entire surface. The remainder of the photoresist is then removed in acetone leaving the desired pattern etched into the oxide (h) or patterned onto it with another material (h'). Depending on the purpose of the etched layer the patterned film could be the final structure desired, or it could act as a mask for additional processes such as doping or etching of the silicon substrate. During the photolithography process the mask and wafer must remain dust free. If either have defects such as dirt or cracks, then the photoresist exposure will be compro- mised. Unwanted pinholes in the photoresist layer will be transferred to other layers in subsequent processes. As a preventive measure, all procedures are performed in a Class Chapter 2. Silicon Micromachining Basics 29 100 cleanroom, on wafers and samples that have been cleaned first with acetone, then deionized water and finally, methanol. Before certain processes such as oxidation and doping, wafers must been cleansed thoroughly with an RCA clean. The RCA cleaning procedure removes trace metals, organics and surface oxides from the wafer, as described in Appendix A. 2.1.1 A Note on Mask Making Each layer of patterning requires a mask (analogous to a negative in photography) that will expose the photoresist to UV light in the regions to be removed. These high resolution masks, drawn with the computer design tool XKic, define the device onto the wafer. XKic allows all the different masks, or layers, of the design to be drawn on the same layout and can distinguish between each layer so that if desired, any number of layers can be shown. From the XKic designs, either a . GIF file or individual postscript files of each layer are created. . CIF files can be professionally transfered to 5" chrome emulsion masks, while postscript files are printed onto linotronic films which are usually used in printing companies as proofs. The linotronic films are then used as a negative to transfer the pattern onto 5" Kodak photographic emulsion plates. Two important aspects arise when making masks. First, the final mask image can be either a positive or a negative of the design. Secondly, one must note which way the emulsion is facing so that the proper image, not a mirrored one, is patterned on the wafer at the end. The image should be such that the emulsion is face down on the wafer when exposing the photoresist. Theoretically, the highest resolution of the linotronic film output is 5080 dpi or 5 pm resolution. Unfortunately, 10 pm lines on the linotronic films are actually bloated as in Figure 2.2. As a result, darkened areas of the mask are generally bloated by ~10 pm on each side. Thus if greater resolution is desired, laser or E-Beam written chrome masks Chapter 2. Silicon Micromachining Basics 30 are used. The choice to use emulsion masks at all is because they are at least 30 times cheaper in cost to purchase. Figure 2.2: Dark lines appear bloated on the printed masks as can be seen from the resolution marks. The left resolution mark (~50 /im wide) is a scanned image of the printed mask, while the right is a scaled image of the original mark (30 pm wide) from the postscript file of the computer design. Note that the edges of the marks are actually sharp and the fuzziness in the right hand pattern is a result of the bitmap graphics on this page. 2.2 Wet Si Etchants Once the photolithographic steps are completed, the silicon wafer is ready for further processing. For example, the wafer can be etched to create 3D structures. Silicon may be etched either isotropically or anisotropically with various wet etchants. The degree of etch selectivity for an etchant to etch silicon over other materials, determines the appropriate masking material. Figure 2.3 shows various hole geometries common to silicon etches. Isotropic etches, in c), produce holes which drastically undercut the masking material since the etch proceeds in all directions. On the other hand, anisotropic etches proceed along silicon's crystalline planes, for example, etching < 100 > and < 110 > planes much faster then the < 111 > plane. In this case, as shown in a), < 100 > wafers will have etched grooves with sloped walls bounded by the < 111 > plane, inclined at 54.75°, with a minimal amount of mask undercutting. Chapter 2. Silicon Micromachining Basics 31 < 1 0 0 > Surface orientation (a) <1 10> Surface orientation (b) V (C) Figure 2.3: Etched hole geometries commonly used in micromechanical devices. The shaded regions indicate the masking material, a) Anisotropic etching on < 100 > surfaces, b) Anisotropic etching on <110> surfaces, c) Isotropic etching. Chapter 2. Silicon Micromachining Basics 32 A common anisotropic etchant is Ethylene diamine pyrocatecol (EDP) diluted with water. This etchant is highly selective and attacks silicon but not Si02, A l , Au or heavily boron doped Si. Thus any of these materials may be used either as a masking layer or an etch stop layer. When comparing selectivities, SiC»2 is the safer choice as a masking layer during long duration etches in EDP. Previous tests [18] on SCS have shown that the EDP etch rate of the < 100 > plane varies from 61 //m/hr to 100 /zm/hr over the surface of the wafer during a long (>6 hours) etch. The etch rate depends heavily on fluid flow, temperature and etchant freshness. The fluid flow over a wafer in the EDP reactor varies from top to bottom, and left to right, hence etch rates across the wafer also vary. This is problem when one is timing the etch in order to reach a specific etch depth. Preferably, an etch stop layer is used so that it is unnecessary to monitor the progress of the etch. If the wafer is constantly pulled from the EDP reactor in order to check the etch depth, the repeated temperature change between the EDP and the deionized water rinse tends to crystallize a white Si based substance onto the etched areas. It is thought that the dissociated pyrocatecol molecules form bonds with excess Si atoms and subsequently crystallize into the white compound at room temperature [19]. Although these white deposits are removable with buffered HF, their presence interferes with subsequent etches and leaves the underside of the Si membrane roughened and uneven. Therefore when using EDP the micromachine 3D structures, it is important to employ some sort of etch stop layer such as heavily boron doped Si or Si02. Another anisotropic silicon wet etchant is tetramethylammonium hydroxide (TMAH), which has a slower etch rate (see Table 2.1) when compared to EDP. However, TMAH does etch heavily doped Si so that doped areas can also be micromachined. A detailed review of these and other anisotropic and isotropic etchants may be found in [20]. Chapter 2. Silicon Micromachining Basics 33 Silicon Etchant Temperature (°C) T M A H 80 T M A H 90 EDP 95 Etch rate of < 100 > Si (//m/hr) 40 65 60-100 Selectivity ratios Si: S i0 2 Si: B doped Si (1020 atoms/cc) Si: B doped Si (1021 atoms/cc) 1190:1 27:1 100:1 800:1 20:1 92:1 >2000:1 >500:1 >500:1 Table 2.1: Estimated etch rates and selectivity ratios for T M A H and EDP[21]. 2.3 Plasma Etching Dry or plasma etching is a common alternative to etch silicon selectively over other materials. In plasma etching, corrosive liquids are replaced with plasmas that can etch via three processes: sputtering, chemical reaction and ion-enhanced etching. In sputtering, substrate atoms are forcibly ejected from the surface by the impinging ions, while chemical reactions rely on the reactivity of the surface atoms to those in the plasma. Both these processes are relatively slow when performed separately, but increased etch rates are observed when performed together [22]. This latter is the condition for ion-enhanced etching. The most widely accepted model for this phenomenon is that the slow chemical reactions at the surface provide a larger sputtering yield to impacting ions. The energy provided by the impacting ions subsequently goes into the reaction layer and increases the formation of volatile products which desorb from the surface. Anisotropic etching of silicon is possible with Cl plasmas. Although the etch rate is faster, the more common fluorine based chemistries are typically isotropic, unless cryo- genically cooled or side-wall passivation polymers are introduced into the system [23]. Successful anisotropic etching of Si with Cl has been performed by Juan and Pang [23, 24]. The typical dry etching recipe requires high microwave and RF power coupled with high chamber pressure and a reasonable high flow of pure Cl gas. Chapter 2. Silicon Micromachining Basics 34 In this work, all attempts to plasma etch silicon were with a PlasmaQuest electron cyclotron resonance (ECR) source coupled with an RF field through chlorine gas. The ECR source couples a 2.45 GHz microwave power source with electrons accelerated by a magnetic field to large velocities. The Lorentz force causes the electrons to circulate around the magnetic field lines with the cyclotron frequency given by w = eB/me. For a magnetic field strength of 875 gauss, w = 2.45 GHz. As the energy coupling becomes resonant, the electrons ionize the gases present in the chamber. In the process chamber, the wafer is RF biased to control the energy of the the impinging ions across the plasma sheath. The etchant gases are continuously fed into the chamber through mass flow controllers while a turbo pump regulates the chamber pressure. The wafer is cooled to process temperatures with a back flow of He and water cooling lines. These process parameters as well as the microwave and RF power are controlled via computer. 2.4 Metallization Thin metal films can be grown onto a substrate with a variety of methods. Common procedures include thermal evaporation and electron beam (E-Beam) evaporation. The former process involves heating and melting the metal on a resistance heater so that the evaporated atoms collect on the surface of the substrate. The metal source is usually placed into a tungsten boat or wrapped around a tungsten wire filament. A current is passed through the boat or wire, heating it and the source until the source begins to evaporate. The rate at which the metal condenses on the substrate depends on the amount of current passing through the boat and on the height above the boat at which the substrate is placed. E-beam evaporations involve a similar process except the source is heated via a beam Chapter 2. Silicon Micromachining Basics 35 of electrons. Here, the current is passed through an isolated filament and the ejected electrons are directed, with magnetic fields, towards the metal contained in a crucible. This deposition method is useful for materials with higher boiling points, like plat- inum (3800 °C) and titanium (3260 °C) that cannot be evaporated in tungsten resistance heaters, but require crucible s. Again, the rate of deposition depends on the location of the substrate, the current flowing through the tungsten wire, and the resulting energy in the E-beam. The deposition takes place within an evacuated bell jar, typically at pressures < 3/xtorr. The substrate is cleaned inside the chamber during evacuation with a plasma discharge. A high voltage rod in the chamber discharges electrically, ionizing all the gases in the chamber. The walls and substrate are bombarded by the highly ionized air and all excess materials are ejected off their surfaces. Usually, the evacuated chamber is backfilled with Argon gas and subsequently ionized. Because Ar is a noble gas and the atoms are heavier, the plasma scrubs the substrate more efficiently and leaves a cleaner surface. If only air is present during the discharge in the chamber, hydrogen or oxygen atoms can still cling or bond to stray molecules (eg. hydrocarbons) on the substrate without removing them from the surface. The easiest method to measure the deposition rate as well as the thickness of the metal film is with a crystal thickness monitor. This device measures the frequency of oscillation of a quartz crystal which is placed as close to the substrate as possible. As materials are deposited onto the crystal, the frequency of oscillation changes slightly depending on the thickness of the film. Using this device during deposition, it is possible to monitor the deposition rate (and to control the rate by adjusting the current through the boat or wire) and measure the thickness of film to within a few angstroms. Once the desired thickness is achieved, the evaporation can be stopped immediately with a manually controlled mechanical shutter that is moved in front of the substrate. Chapter 2. Silicon Micromachining Basics 36 2.4.1 Metal Lift-off Process To metallize detailed structures onto the substrate, slightly modified additive photolithog- raphy, sometimes called the metal lift-off process, is used. The changes to the lithography process (as shown in Figure 2.4) occur during the photoresist exposure and development stages, before the metal is deposited. Prior to the soft bake and exposure to UV light, the wafer can be soaked in a hardening solution so that the upper portion of the photoresist layer becomes more resistive to the developer as indicated by the heavier Crosshatch in (b). Once baked and exposed (c), the polymerised regions are removed in the developer (d). Letting the wafer soak in the developer (e) for an extra 2-3 minutes overdevelops the lower unhardened portions of the resist, leaving the upper portions to form a small overhang. The opening remains the same thickness as what was on the mask, but the overdevelopment ensures that the final metallized pattern (f) is not in physical contact with the resist layer. This allows an easy removal of the resist (g) in acetone. Note that in Figure 2.4, the photoresist layer has been drawn thicker for clarity and is not drawn to scale. In fact, we do not always overdevelop the resist so that we can strip out the Si02 layer and deposit the metal directly onto the Si. Chapter 2. Silicon Micromachining Basics 37 (e) Resist over-development (f) Metal deposition (g) Resit removal Figure 2.4: Modified additive photolithography for a metal lift-off process. See text for details. (Not drawn to scale) Chapter 3 Fabricating the Mesh Structure The main goal of this work is to produce bolometers that would be less susceptible to cos- mic ray hits, but remain as sensitive to microwaves as the B A M sapphire chip bolometers. Consequently, a large part of this work involves investigating micromachining techniques which would lead to a thin free standing mesh held in place by a few supports with low thermal conductance. While it is possible to obtain whole Si wafers of thicknesses down to 2 /im, it is much easier and cheaper to work with regular wafers (with thicknesses ~ 450 fim) that are less fragile. In this case, it is necessary to remove the majority of the wafer thickness over a small area to leave a thin membrane, surrounded by a thicker frame for handling. From the suspended thin membrane, the bolometer substrate can be denned into a mesh structure like that of Figure 1.8. This chapter details various attempts, via wet etching, to construct suspended mem- branes ranging in thickness from 2 /xm to ~100 /im. The subsequent steps to micro- machine the mesh structures via wet etching and plasma etching are also examined for meshes of various dimensions. The suppliers from whom the wafers were purchased are listed in Appendix B. 3.1 Using Etch Stop Layers to Form Thin Membranes and Meshes It is easiest to thin the wafer in small areas with an anisotropic wet etch. Square openings made into one side of a < 100 > wafer will etch into the wafer leaving straight but sloped side walls and will only stop at the etch-stop layer if one is present as a part of the wafer. 38 Chapter 3. Fabricating the Mesh Structure 39 The result is a thin square membrane with a frame which is as thick as the original wafer. One possible method to stop the wet etch is to have the membrane layer be of material that will not be etched. This can be achieved by depositing the bolometer substrate material directly onto the Si wafer as Mauskopf et. al. do by depositing a uniform layer of Si3N4 to a specific thickness [15]. Due to a lack of facilities, this was not an option for us. One could however, heavily dope the wafer with boron atoms prior to back- etching. Since heavily doped Si is not etched by EDP, but can be etched with TMAH, the membranes can be defined with an EDP etch, and the square grid structures with the TMAH. A different approach to the problem involves processing a triple-layered wafer rather than a simple double-side polished wafer. Commercially available triple-layered wafers have an additional layer of oxide between the bulk (handle) wafer and the membrane (device) layer. Thus, the thin membrane is already present and the bulk wafer may be removed in EDP with the intermediate oxide layer acting as the etch-stop layer which can be removed at a later step. While these processes seems fairly straight-forward, the question of how to regulate the thickness of the membrane remains unresolved. Boron doping generally penetrates the wafer to a depth of 5 /im, but the concentration of the doping drops off with the depth, so the thickness is variable. The second method involving a buried intermediate layer is more promising as the device layer thickness can be specified to the wafer manufacturer. The following sections describe the experiments performed to evaluate both methods. 3.1.1 Heavily Boron Doped Si Silicon wafers can be doped by baking them in a furnace at high temperatures next to an activated boron source. The source ejects boron atoms which lodge themselves into the silicon crystal structure. A subsequent oxidation step drives the boron atoms into Chapter 3. Fabricating the Mesh Structure 40 the wafer and also forms protective oxide layers for the later E D P and T M A H etches. Initially, 3 single side polished (SS) wafers and 3 double side polished (DS) wafers were cleaned in a series of hot baths containing hydrogen peroxide wi th ammonium hydroxide, buffered hydrofluoric acid, and finally hydrogen peroxide wi th hydrochloric acid. This cleaning procedure removes organic materials, native oxides and metals from the surfaces of the wafers and should be performed immediately prior to placing the wafers in the furnace for doping and oxidation. Once cleaned, the wafers were loaded into a furnace boat, containing boron sources. Two wafers were placed on either side of each source wi th the the polished surfaces facing the source. Dummy scrap wafers were placed in the unused boat slots next to the extra boron sources. The boat was slowly pushed into the furnace after which the furnace was ramped to an operating temperature of 975 °C. The boron diffusion was stopped 40 minutes after the temperature stabilized. The furnace temperature was then ramped down to 750°C and the boat slowly pulled out. The target doping concentration was 10 1 9 atoms/cc, but the actual average concentration for the six wafers was determined from 4-probe resistance measurements to be ~ 10 1 8 atoms/cc. This was thought to be an acceptable doping level to act as an etch stop layer so the wafers were removed from the boron furnace boat and placed into the oxidation boat. The boat was then slowly pushed into the furnace and oxidized in a wet oxygen environment. A 0.3 pm layer was grown onto the wafers. Each wafer was then processed individually wi th various micromachining steps in order to find a repeatable process that would lead to the desired free standing grid structure (with a grid spacing of 385 pm and 35 pm wide lines) held to the support frame by 4 legs, 1 m m long, running diagonally from the outside corners of the mesh to the frame. For the first SS wafer, large open areas were patterned and etched into the unpolished Chapter 3. Fabricating the Mesh Structure 41 side for 6.75 hours in EDP. It was believed that the etch would proceed through the wafer, forming sloped sidewalls until it encountered the heavily boron doped Si where the EDP would cease etching. When the wafer was pulled from the solution, it was observed that for the majority of the open areas, there was a thin membrane of uneven thickness that transmitted reddish wavelengths. However in some locations, the membranes had either been etched through or had many tiny pinholes. This was attributed to uneven doping levels across the wafer. Next, the polished side of the wafer was patterned to create the mesh structure. Since E D P does not etch the doped membrane, the wafer was placed in a hot bath of T M A H instead. Due to lack of foresight, the T M A H proceeded to etch the membrane from both sides and as a result, the membranes were eaten through before the mesh was well defined. The second SS wafer was patterned to open up the back windows but for unknown reasons, the doped layer was insufficient as an etch stop layer and the etch ate through the entire wafer after 6.5 hours. It was suspected that the boron source was the culprit because the DS wafer on the other side of the same source also exhibited strange reactions to conventional etches. With this DS wafer, the oxide on the doped side of the wafer would not etch in HF (possibly some kind of borosilicate glass was formed) so the mesh pattern could not be defined into the membrane. This was not investigated further and we proceeded with the second DS wafer. It was thought that the middle oxidation step could be skipped if the mesh was first patterned, and then the backside opened up and etched. In this manner, the EDP would only attack the open areas from the back, and would not laterally etch the mesh legs. The boron doped side of the second DS wafer was successfully patterned and etched in T M A H however the back side was not etched in EDP. It was unclear how it would be known when the meshes were released from the back silicon because the etch could not be monitored. Also, because the support legs of the mesh were diagonal, they would be Chapter 3. Fabricating the Mesh Structure 42 etched away by the E D P . So this step-saving idea was abandoned and we returned to the original plan. The last DS wafer was opened up in the back and etched for 6.75 hours. Some membranes were etched through, but the majority were intact and transmitted red light evenly. The wafer was cleaned, reoxidized and the doped side patterned for the mesh. After 42 minutes in the T M A H , a few grids were defined and held in place by the support legs and the back oxide. The wafer was pulled from the bath and the oxides removed wi th a 10 minute dip in H F . O f the 54 devices patterned into it, only 2 membranes led to free standing meshes. The rest of the devices were either under etched or over etched. Figure 3.1 is a scanned photo of one of the meshes. Clearly, these were not entirely etched to completion and there is s t i l l residual Si to be removed from the backside of the mesh. However, the result seemed promising. One reason that more than half the grids were lost was due to the fact that the 4 mesh support legs were patterned to be diagonal instead of square and so were being laterally etched by the T M A H . This could be remedied by remaking masks with a grid design like that of Figure 1.8. A new mask was made and printed on linotronic film. The mesh consisted of 35 pm wide lines with a 385 pm grid spacing and four, 1 m m long, square support legs arranged as in Figure 1.8. The unpolished side of the wafer was patterned and etched in E D P , for 6.75 hours, to open up large square windows as before. However, in this instance, the membranes seemed rather thick and did not transmit red light. The second oxidation step used before to protect the back side of the membrane was skipped so that the membrane could be thinned out as the mesh was defined. Once the polished side had been patterned for the mesh structure, the wafer was placed in T M A H for a total of 3.25 hours. Because the T M A H etchant is clear, the progress of the etch could be monitored without pull ing the wafer from the bath. After the first 2.5 hours, the etch seemed to be progressing unevenly across the entire wafer and Chapter 3. Fabricating the Mesh Structure 43 Figure 3.1: First free-standing Si mesh made by back etching a wafer to a heavily boron doped Si etch stop layer. The mesh defining etch was not quite complete as there is still some leftover Si on the backside of the grid area. The outside Si frame is not shown. even across individual membranes. Approximately 1/3 of the devices located randomly across the wafer, had already etched completely through from the back side, while the remaining membranes were wholly intact, that is, the mesh structures could be seen etched into the membrane, but the backside was not yet cleared out. When the etch was stopped, there were 2 fully intact and free-standing meshes, while 12 other devices required a longer etching period. The wafer was diced and the other chips were etched individually in the T M A H , until their grids were fully released from the back silicon. Pictures were taken of some of these free standing meshes. While the etched mem- brane appears cleaner than those in Figure 3.2, the uneven etch from one side of the membrane to the other cannot be ignored. The wider legs in the lower left hand side are a result of an uneven membrane thickness. The mask that defined the lines were all 35 pm wide, but since the etch progresses at a sloped angle, the backside of the legs are much wider. Thus the difference in width is an indication of a difference in the membrane Chapter 3. Fabricating the Mesh Structure 44 thickness from the lower left hand side to the upper right hand side of the mesh. When examined with a profilometer, the thickness of the membranes were close to 90 pm at the thickest regions. Clearly this is not a repeatable nor controllable process. The thickness of the membrane cannot be predetermined and the quality of the resulting grids are vari- able. This method of mesh fabrication is not at all useful for building bolometers with controlled dimensions and so it was abandoned. Figure 3.2: A mesh and it surrounding Si frame from the second successful attempt to make free standing meshes from a doped Si membrane. The uneven etching is apparent from the wider legs in the lower left hand corner as compared to the upper right hand corner. The membrane was measured to be as thick as ~90 pm. 3.1.2 Buried Oxide Layer Because of the demands of the silicon integrated circuits technology, newer wafers are now available which have insulator layers sandwiched between two single crystal silicon layers. Such wafers consist of a regular handle wafer 450-500 pm thick, bonded to an insulating material such as silicon nitride or silicon dioxide. A second Si wafer is bonded to the Chapter 3. Fabricating the Mesh Structure 45 insulator and polished down to the desired device layer thickness. These wafers can be purchased with a variety of specifications including handle and device layer thicknesses, crystal orientations and resistivities, as well as the type of insulator material and its thickness. We were able to acquire three types of these triple layer wafers that had buried oxide (BOX) layers. Their specifications are given in Table 3.1. Because we were ordering in small quantities, we purchased < 100 > wafers that had appropriate device layer thicknesses and that were readily available from stock inventory. Device Layer Handle Wafer BOX thickness P thickness P thickness (pm) (ficm) ( H (ficm) (pm) 2.25 10-20 381 10-20 0.2 6.5 20-30 375 10-20 0.2 5.0 150-250 525 2-30 1.0 Table 3.1: Relevant specifications for the three BOX wafers used in this work. Initially, only the BOX wafers with 6.5 pm thick device layers were cleaned and oxi- dized. Then, while protecting the topside of the wafer, square openings were etched into the backside for 7 hours in EDR Because of the buried oxide layer, there was no worry of over etching. Once the etch was complete, the BOX layer was protected with photoresist while the front side was patterned and etched into a mesh. The mask used was identical to that used in the previous runs with the boron doped wafers. The grid was made up of lines 35 pm by 375 pm, supported by 4 legs 35 pm wide and 1 mm long. After ten minutes in EDP, the etch was complete and the wafer was pulled from the etchant and rinsed with DI water. Immediately after the rinse, the wafer was placed into HF to remove all the oxides to free the mesh. After 10 minutes in HF, the wafer was dipped vertically into beakers of DI water as a rinse. Finally, the wafer was heat dried in an open oven since Chapter 3. Fabricating the Mesh Structure 46 the N 2 air gun would likely blow the meshes out. Water spots were minimal, but these could be avoided in later runs with an isopropanol rinse and letting the wafer air dry. With this process, 15 free standing Si meshes were successfully fabricated from a single wafer that had been patterned for 42 individual devices. Figure 3.3: Free standing mesh made from a BOX wafer with a device layer 6.5 /xm thick. The low yield was mostly due to two problems. First, the surface tension on the BOX layer as the wafer was removed from the DI water rinse popped many meshes free. The thin oxide membrane is quite stressed when it is stretched out over large open areas and cracks and buckles in many places. The surface tension of the DI water rinse increases the stresses and occasionally breaks one of the corner support legs so that the oxide can curl and relieve the stresses. There was no obvious solution to this problem except to keep the wafer vertical when removing it from liquids and to remove the oxide layer as quickly as possible. The second problem occurred while the wafer was being diced. Merely scribing the wafer with a diamond tip did not provide an adequate fault line to break the wafer along the desired paths. Instead, the wafer tended to crack at the boundaries of the Chapter 3. Fabricating the Mesh Structure 47 etched windows where the wafer had been entirely etched through. This problem can be easily solved by patterning and etching dicing grooves into the backside during the etch to open up the back windows. As a test of the robustness of the meshes, a 0.001" brass wire was glued with epoxy to the central pad region meant for the NTD Ge thermistor. A light tap of the wire into a tiny ball of Miller-Stevenson 907 epoxy was all that was required to attach the wire. Once the wire was glued down, it was possible to pick up the entire chip, mesh and frame, by the wire. Presumably, attaching a NTD Ge thermistor would be equally as easy. Next we moved to the BOX wafers with 2.25 pm membranes since thinner support legs would provide lower thermal conductance to the heat sink and reduce the thermal noise. Unfortunately the previously described surface tension problems increased once the membrane was etched. We then investigated the possibility of using the 6.5 pm membranes and designing the mesh to have 8 support legs with reduced widths of 5 pm. This also did not have the structural support necessary to withstand the surface tension of liquids prior to oxide removal. This whole problem can be avoided by using plasma etching to micromachine the mesh structure. This possibility is examined in the next section. 3.2 Forming Mesh Structures via Plasma Etching In order for plasma etching to be an improvement over wet etching, both the Si etch as well as the masking material removal must be performed in dry environments. Once the mesh is etched the membrane cannot ever be immersed in any liquids. Prior to the Si etch though, when the full membrane is still intact, the chip can still be immersed so that patterning of the membrane is possible. Chapter 3. Fabricating the Mesh Structure 48 Valid masking materials for a Cl based plasma etch include Si0 2 , metals and pho- toresist. While the removal of most metals requires soaking the sample in some solvent, photoresist can be ashed away with an oxygen plasma. Clearly, this was the simplest choice to mask with, given the current UBC cleanroom facilities. Cl based plasma etching could take place in the PlasmaQuest ECR etcher while the resist could be ashed off using the Technics Plasma Etch II etcher. 3.2.1 Etching Mesh Structures Several attempts to plasma etch mesh structures from a 2.25 /xm membrane showed some promising results. Unfortunately, there was not enough time to pursue this further. A brief description of the attempts to etch Si with a C l 2 plasma is described here. The handle portion of a BOX wafer with a 2.25 um device layer, was patterned and etched to open up the back windows. Before the etch reached the etch stop layer, the wafer was removed and diced so that the chips could be etched individually. Once the etch reached the BOX layer for all the chips, all the oxides were immediately stripped in an HF bath to reduce the stress on the Si membranes. Then, photoresist was spun onto the topside of 5 free standing membranes and which were subsequently patterned with a mesh structure with 8 support legs, 5 /mi wide. One chip was then placed into the PlasmaQuest ECR etcher. Following the recipe in Juan and Pang's article, the chip was etched with the following process parameters for 10 minutes: Microwave power: 1000 W RF power: 100 W DC bias: 72 V Pressure: 15.3mTorr Chapter 3. Fabricating the Mesh Structure 49 C l 2 flow rate: 8.7 seem BCI3 flow rate: 2.1 seem The result is shown in Figure 3.4. The etch appeared to have proceeded from the center of the membrane outwards and the mesh was not fully released. Only the central portion of the membrane had been fully etched through so that the mesh was supported by a frame formed by the remaining outer portions of the membrane. The masked area of the sample was entirely blackened. The blackened portions could not be removed in solvents, but could be easily scratched off with tweezers. It was unclear whether the black material was burnt photoresist, or the "black grass" of etched Si pillars [22]. It is possible that the photoresist layer was sputtered off during the etch and the underlying Si was being etched in those areas. The support wafer on which the sample had been placed in the chamber had turned cloudy gray and it was assumed that some sort of oxide had been deposited onto the wafer. This deposit could be wiped off with a little DI water and alcohol. The area of the support wafer that was under the sample remained shiny and clean. An exact repeat of the above process on a second sample had slightly different results. The membrane was not etched through in the center although it appeared from the coloured fringes that the etch was progressing from the center outwards. The masked areas were a cloudy gray colour while the support wafer was now blackened. A third membrane was etched for twice the length of time, under the same conditions. When removed from the chamber, the mesh was nearly fully defined in all areas. However, when the mesh was placed into a Flouroware chip holder, the mesh was pulled out of the frame due to static between the Si and the plastic holder. Clearly the thinner support legs were quite fragile and it would be quite difficult to attach a thermistor to the mesh. Chapter 3. Fabricating the Mesh Structure 50 Figure 3.4: Free standing mesh plasma etched from a BOX wafer with a device layer 2.2 pm thick and legs 5 pm wide. Although the first and third result seemed promising, the unknown properties of the black material and the unpredictable appearances of the cloudy gray deposits remain problematic. However, plasma etching remains an attractive option if these problems could be resolved, either by turning to fluorine based plasmas or by finding an alternate masking layer. It was decided that wide-legged meshes were acceptable and would not compromise our noise budgets. So, the meshes would be fabricated from the thicker 5.0 pm membranes, using wet etching as in Section 3.1.2. Chapter 4 Resistivity Measurements of Thin Gold Films As described in Chapter 1, the absorbing layer of the bolometer should have a resistance of 188.5 f2 per leg at the operating temperature of 270 mK. Any metal film deposited to this sheet resistance will work as an absorbing film. However, it is also desirable to select a metal that has a low heat capacity as compared to the other bolometer components. At 270 mK, recalling Table 1.1, both gold and bismuth are good candidates as absorbers. While bismuth begins to exhibit excess heat capacity at slightly lower temperatures due to nuclear quadrapole moments, and has a tendency to oxidize when exposed to air and humidity, the resistivity of gold is much lower than that of the semi-metal and so requires a thinner film. If the gold film is too thin (<100 A), it may be discontinuous since the gold atoms tend to clump together to form island structures as the film is grown. The basic theory on the resistivity of thin metal films, and how the appropriate film thickness for our bolometers can be determined is outlined in this chapter. 4.1 The Resistivity of Thin Metal Films The electrical resistivity of bulk materials arises due to electron-phonon collisions and electrons scattering off of lattice impurities and dislocations. Because phonons are ther- mal excitations in the crystal lattice, the phonon scattering component of the resistivity. pp is temperature dependent and dominates at temperatures > 4 K. On the other hand, the resistivity due to electron-impurity and dislocations scattering, pi is temperature in- dependent and can be considered a rough measurement of the material's purity. Because 51 Chapter 4. Resistivity Measurements of Thin Gold Films 52 these two components are independent of each other, the total resistivity p can be written as their sum. The electrical properties of thin metal films are slightly different from those of the bulk metal. Once the film thickness, t, becomes much smaller than the bulk mean free path of the electrons, other scattering effects like surface scattering and grain boundary scattering must be considered. Generally, one observes that pi oc 1/t [25]. Surface scattering is due to the scattering of the electrons off of the film's surfaces. Consequently, when the bulk electron mean free path, A 0 is much larger than the film thickness, the resistivity-temperature dependence is a strong function of the film thick- ness. On the other hand, in the grain scattering model, electrons scatter off of grain boundaries. Grain boundaries can be thought of as parallel partially reflecting planes randomly distributed throughout the film. The average grain diameter, d, is the average distance between planes and is usually taken to be equal to the film thickness. Here, the scattering mechanism is temperature independent and only adds a constant offset to the temperature-resistivity curve. This offset is called the residual resistivity p(0) of the film, and is an indication of defect density and sample purity. Studies on a variety of metals including aluminum and gold, by De Vries [26, 27] and van Attekum [25], have shown that the latter process is likely the dominating contribution to the residual resistivity at temperatures < 4.2 K. De Vries found that the resistivity could be described by the following simplified equation, derived from grain scattering theory. P = PP + Pi (4.1) Pfiim = (1.39a + l)pbuik (4.2) Chapter 4. Resistivity Measurements of Thin Gold Films 53 where a = (Xa/d)(R/l — R). Here R is the grain boundary reflection coefficient. Since the phonon contribution to the resistivity can be measured and found from the Bloch-Gruneisen relation pp oc T5/Q6D, (for gold, 0£> = 171K) and the quantity pX0 is considered a constant for all temperatures with the generally accepted value 9.6 x 10~12f2cm2 [26], one can calculate X0 for a given gold film and fit for a value of R. 4.2 Preparation of Thin Gold Films Evaporating gold directly onto glass-like substrates usually produces films that are flaky and do not adhere well to the substrate. However, a thin intermediate layer (~ 50 A) of chromium or titanium usually forms a good adhesion layer for gold. This is possibly because chrome and titanium both form thin oxide layers which stick to the insulator, while the upper metallic layer forms a good bonding surface for the gold. For our pur- poses, titanium is favoured over chromium because Ti has a lower magnetic contribution to the heat capacity. The magnetic contribution remains constant at low temperatures and therefore remains large, dominating the heat capacity at low T. However, if gold is evaporated directly onto a very clean Si substrate without oxides, the gold film adheres quite well. In this case one must worry about whether the Si will "freeze out" electrically at 300 mK or remain electrically conductive. Previous measure- ments [18] showed that for doping concentrations under 1018 atoms/cc, Si does in fact freeze out below 4.2 K. To ensure that the correct resistance was evaporated onto the membrane, various film thicknesses of gold were evaporated onto Si substrates in a known pattern and 4 wire DC resistance measurements from 4.2 K to 300 K were made. As test samples, thin lines of titanium and gold were deposited, Figure 4.1, onto spare individual Si chips (some with oxide overlayers, some without) using metal lift-off techniques and an E-beam evaporator Chapter 4. Resistivity Measurements of Thin Gold Films 54 *as described in Chapter 2 and Appendix A. The geometry of the lines were defined by a mask design such as that in Figure 4.1. The electrical connections, for 4-wire resistance measurements, were made to the outer rectangular pads by attaching electrical leads with conductive silver epoxy. Figure 4.1: Gold meander path used for thin film resistivity tests. Once the metals were deposited to the desired thickness and outfitted with leads, individual samples were attached to a probe and slowly lowered into a liquid 4 He dewar and cooled to 4.2 K. During the cooling, the resistance was measured with an HP 34401A multimeter while the temperature was measured with a calibrated diode. The diode, supplied with a constant current source of 50 pA, has a linear voltage-temperature relation given by T = vmode - 1-1938 (4.3) -0.00245 in the temperature range 40 K < T < 300 K. The samples are mounted onto the probe with Emerson Cumming 2580FT Stycast Chapter 4. Resistivity Measurements of Thin Gold Films 55 which has a smaller thermal expansion coefficient than silicon. Thus only a little stycast should be used to bond the silicon to the probe, otherwise the silicon may crack once cooled. 4.2.1 Preliminary Test Runs The first Si chips used were from two different cleaned wafers with Si02 overlayers 0.3 pm and 0.5 pm thick respectively. Two different substrates were used to test whether the thin film resistivity would depend on the underlying surface. Oxides grown under slightly different conditions may have differing surface roughness. The surface roughness will directly affect how the gold film forms as it is evaporated onto the surface. Photoresist was spun onto all the samples and patterned using the metal lift-off technique. The test path, similar in geometry to Figure 4.1 was 3.115 cm long and 50 /rniwide. For the titanium evaporation, all the samples were mounted on the stationary stage in the Balzers E-Beam evaporator. Unfortunately, the crystal monitor is mounted at the very top of the chamber, while the stationary stage holding the samples is at the midpoint. This discrepancy in height can be accomadated for by setting the tooling factor on the thickness monitor controller to ~ 150 %. Once ~60 A of Ti was deposited, the samples were removed. The gold evaporations were carried out in a thermal evaporator where the crystal monitor could be placed directly beside the samples for a more accurate thickness mea- surement. One sample of each type of wafer was mounted into the chamber. The bell jar was evacuated and the air was ionized by a high voltage discharge. Once the chamber pressure was at 2.9 pTovv, 50 A of gold was evaporated onto the samples. This was re- peated for the other samples so that there were gold films 150 A, 200 A, and 250 A thick on both types of substrates. Once the photoresist was removed in an ultrasonic bath of acetone, electrical leads Chapter 4. Resistivity Measurements of Thin Gold Films 56 were attached to the contact pads under microscope. Initial 4-wire measurements of the room temperature resistance showed that indeed the quality of the underlying layer partly determined the resistivity of the film. Two of the samples had open paths, because the lines had been accidentally scratched while the electrical leads were being attached. Au Resistance (Q) of film thickness on substrate (A) ±2 A 0.3/im SiC»2 0.5 pm S i0 2 50 - 10150 150 4060 - 200 2136 1235 250 1596 1036 Table 4.1: Room temperature resistance of thin gold films on two different substrates. (-) indicates the gold paths that were open. The resistivity of the thicker films at lower temperatures is plotted in Figure 4.2. Though the thickness of the film did not seem to affect the resistivity of gold for the substrate with the thicker oxide, the effect of the substrate is quite apparent. The * and A points correspond to the 0.3/imSiC»2 substrate samples with 200 A and 250 A thick gold films respectively, while the x and • points correspond to the 0.5 /xmSi0 2 substrate samples with 200 A and 250 A thick gold films respectively. The residual resistivity is much higher for the films on the thinner oxide. From this, it was concluded that to get the correct absorber sheet resistance, resistivity measurements would have to be performed for each wafer immediately prior to the absorber deposition. By using the 200 A Au on 0.3 pm S i0 2 data as a rough estimate of the thin film resistivity and extrapolating to T = 300mK, the sheet resistance is only 2Q./U. So, a 375 pm long leg, 50 pm wide (the size of the mesh legs) would only have a resistance of ~ 16 f l To increase the resistance to 188.5 Q, the thickness of the gold film would Chapter 4. Resistivity Measurements of Thin Gold Films 57 Figure 4.2: Resistivity vs temperature for gold films with thicknesses: 200 A (x,*) and 250 A (•, A) on 2 different substrates. See text for details. Chapter 4. Resistivity Measurements of Thin Gold Films 58 have to be a mere 17 A thick. Such a thin film is likely to be discontinuous. A better alternative is to decrease the width of the path from 50 pm to 5 pm. Another important test for these films is to examine how well they hold up in a hot EDP bath. Although EDP does not etch gold, it will slowly etch titanium. Another Si chip (with a 0.3 pm layer of Si02, cut from the same wafer used for the resistivity measurements) was coated with 60 A of Ti and 200 A of Au. It was then placed in a bath of EDP held at 95 °C for 10 minutes. When the sample was removed and rinsed, the metal layers were gone and flakes of the gold film could be seen floating in the EDP solution. The gold would have to be evaporated directly onto the Si. 4.3 Au on Si Anticipating the complete bolometer fabrication process, it is necessary to evaporate 5 pm wide lines onto 30 pm wide legs, which is a little tricky. The Si mesh cannot be defined prior to the gold mesh deposition because photolithography must be used to pattern the gold mesh and it is difficult to spin an even photoresist layer onto an already defined Si mesh structure. Furthermore, since the gold must be evaporated directly onto the Si, the Si0 2 must be removed from the topside of the membrane for the Au path. Only enough of the protective oxide is removed to define the Au pattern, so that the remaining oxide can be patterned to define the Si mesh. In this case, the metal lift-off technique cannot be used. If there is an overhang in the resist layer, than the oxide etch will be too wide. That is, the gold layer will be the correct width, but the subsequent patterning of the oxide layer to define the mesh structure would be compromised. Therefore, only standard photolithography can be used. A BOX wafer with a 5 pm device layer was oxidized and etched to open up the back windows. After 6 hours, the wafer was removed, and the unetched outside edges of the Chapter 4. Resistivity Measurements of Thin Gold Films 59 wafer were trimmed and diced into 1 cm2 samples. Each of these was patterned with a new meander path design that was 3.390 cm long and 5/imwide. After the photoresist was exposed and developed, the samples were placed into HF for 3 minutes to etch away the oxide. The resist layer was left intact on the samples which were now ready for the gold evaporation. Before gold was deposited onto the samples, two cleaned pieces of Si, cut from the same wafer as the samples, were placed into the bell jar to test the adhesion of gold to Si. Once the chamber was evacuated to 8 //Torr, it was back filled with Ar gas and ionized with the discharge rod. The Si pieces were subjected to the plasma scrubber for 15 minutes, after which the chamber was evacuated once more. Once the pressure reached 2.8//Torr, a 200 A layer of gold was deposited onto the samples. The adhesion was quite good as the gold film could not be lifted off with scotch tape. However, the film could still be easily scratched off with tweezers. One of the samples was then placed in hot EDP for 10 minutes. The gold film did in fact protect the Si from the etchant. The meander path samples were subsequently placed in the evaporator and gold was evaporated under the same above conditions. Three samples had complete gold lines, and had films with thicknesses of 152 A, 173 A, and 202 A. These 3 samples were mounted onto the probe and lowered into the 4He dewar for resistance measurements. Unfortunately, the 173 A sample cracked as it was being cooled in the dewar. The data is graphed in Figure 4.3 which includes the resistivity of bulk gold (solid line) [28] for reference. One can also see that the resistivity of thin gold films at absolute zero is not in fact zero, but there is a residual resistivity. In Figure 4.4 the resistivity is graphed against the inverse of the film thickness and shows that pi oc 1/t with a non-zero intercept. We do not believe that p = 0 at finite thicknesses. Perhaps the steep slope of p vs 1/t for thin films can be attributed to grain boundary scattering since the films may be slightly discontinuous. Once the film thickness is greater than 250 A, the film becomes continuous Chapter 4. Resistivity Measurements of Thin Gold Films 60 and the film behaves like the bulk material. For one gold mesh leg 375 /imlong, 5 /xmwide to have the desired resistance of 188.5 fi, Rn = 188.5 0(5/375) = 2.5 fi/D. From Figure 4.4, this corresponds to a thickness of t = 152 A. This is the thickness of gold that should be deposited onto the Si membrane. Chapter 4. Resistivity Measurements of Thin Gold Films 61 Figure 4.3: Resistivity vs temperature for gold films with thicknesses: 152 A (A) (closest to target resistivity), 173 A (•) and 202 A (x). The solid line is the bulk resistivity of gold [28]. Chapter 4. Resistivity Measurements of Thin Gold Films n 1 1 r n 1 1 1 1 1 1 1 1 1 i r O I 6 •§ 2 o 0 0.003 _1 I L_ 0.004 _i i i_ _i i i i i i i i_ 0.005 1/t (1/A) 0.006 0.0( Figure 4.4: Resistivity vs. inverse film thickness at T=0 K. Chapter 5 Conclusions With the micromachining techniques developed in the earlier chapters, one is now in a position to combine the successful processes into a bolometer fabrication procedure. In particular, it is possible to etch the support structures and deposit the desired absorbing layers. The recommended process is presented here. A silicon mesh, as in Figure 1.8 with a thin gold absorption layer, could be fabricated following the steps in Figure 5.1. First, a custom ordered buried oxide (BOX) silicon wafer, which consists of a 1 //m silicon oxide layer sandwiched between a 5 thick silicon layer and a 525/xm silicon handle wafer, is cleaned and thermally oxidized (a). Next, a 1cm square opening is removed from the handle wafer in EDP (b). Before the etch reaches the BOX layer, the etch is stopped and gold is evaporated onto both sides of the wafer. A gold mesh is patterned on top and gold contact pads, 2 mm x 3 mm, on the bottom for the thermistor electrical leads (c). The rest of the opening in the handle wafer is then etched to completion (d). The top oxide layer is then patterned to reveal the final mesh pattern (e), after which, the mesh is patterned into the thin silicon layer, (f). The mesh is then released when all the oxides are removed in HF (g). Finally, a prepared NTD Ge thermistor is glued onto the mesh while the brass leads are glued to the gold contact pads on the outer silicon frame (h). There are two logistical reasons to stop the back etch before the EDP reaches the etch stop layer (steps (b) to (d)). Firstly, it is easier to work with the whole wafer when the membrane area is still thick. The photolithography steps to define the gold 63 Chapter 5. Conclusions 64 mesh pattern can be performed without worrying about membranes popping out due to surface tension. The second reason deals with timing and the juggling act of working at two cleanroom facilities. It takes roughly 1.5 hours to pattern the oxide on the wafer to open up the back windows, while the etch itself takes a little more than 7 hours to proceed through the full thickness of the handle wafer. The subsequent photolithography process to define the gold mesh pattern takes another 1.5 hours. However, the photolithography processes for both the back window and gold mesh patterning must be performed in the SFU cleanroom since their mask aligner can handle 4" wafers and has double side alignment capabilities. The latter is very important since it ensures that the gold mesh pattern is properly centered over the membrane and will subsequently be properly aligned with the Si mesh. So, in theory, one could do all three process in a 10 hour workday at SFU without stopping the etch midway as previously described. However, one must remember that at the end of the 7+ hour EDP etch, the membranes will be very delicate and fragile during the subsequent patterning process and one will most likely be too fatigued to perform the delicate work involved in the next patterning step. This is not the best working combination and nothing is gained by it. Stopping the etch midway allows one to work with a more robust wafer and with a more alert frame of mind. Although Figure 5.1 only shows the cross section of one device on the wafer, each 4" wafer can hold at least 40 individual detectors, leaving ample room for alignment marks and wafer dicing lines. Clearly, many bolometer designs of differing dimensions can be made on one wafer at once. Once the thermistor is attached and the leads soldered to the gold contact pads, the bolometer can be mounted into modified copper holders which are compatible with the B A M dewar coldstage. The Si frame can be soldered to a flexible support made from gold plated 0.005" copper sheet metal bent as in Figure 5.2. The sheet metal provides rigid support but allows for thermal contraction of the bolometer during cooling. The Chapter 5. Conclusions 65 (a) Thermal oxidation (b) Back etch in EDP (c) Deposit absorber and contact pads Silicon yA Oxide Silicon Metal (d) Finish back etch (e) Pattern top oxide for Si mesh (f) Etch mesh structure in EDP 1 zzzzzzzzzzzzzz (g) Release mesh structure from oxides flflfiflfififli (h) Attach thermistor and leads Figure 5.1: Basic steps to building a micromesh bolometer (not to scale). See text for details. Chapter 5. Conclusions 66 support is soldered to a ring against which the Winston cone is mounted (see Figure 5.3). Figure 5.2: Bolometer holder assembly. The bolometer (top piece) is soldered to a flexible copper support (center) that is mounted to the copper ring (bottom) which is compatible with the dewar coldstage. 5.1 First Attempt at Using This Recipe to Build Bolometers The above recipe was tried on one wafer. As before, a BOX wafer was first cleaned in a series of hot baths containing hydrogen peroxide with ammonium hydroxide, buffered hydrofluoric acid, and finally hydrogen peroxide with hydrochloric acid. This cleaning procedure removes organic materials, native oxides and metals from the surfaces of the wafers and thus should be performed immediately prior to being place in the furnace for oxidation. Once clean, the wafers are thermally oxidized at 1100 °C as in Appendix A.2. First in a thin dense oxide is grown in a dry oxygen environment. Subsequently, the bulk of Chapter 5. Conclusions 67 Figure 5.3: The bolometer is placed at the output of a Winston cone. The raised central portion of the bolometer is the radiation absorbing region. the oxide is grown in a wet oxygen environment where water vapour is present. Then, a secondary thin layer of dry oxide is grown on top. This dry-wet-dry oxide sandwich is more chemically resistant to the silicon etchants and ensures that there are no pinholes in the oxide. Because oxides grown in a wet atmosphere tend to be less dense, defects and pinholes are more likely to appear unless thicker oxides are grown. On the other hand, wet oxides grow much faster than dry oxides. It takes 40 minutes to grow 0.3 //min a "wet" furnace and 3 hours in a "dry" furnace. The dry-wet-dry sandwich cuts down on the growth time and produces oxide films adequate for protection against the EDP etchant. The baking temperatures and growth times given in the appendix form an oxide layer ~ 0.3 /xm thick. Note in Figure 5,1 that the oxide layers on both sides of the wafer are the protective masking layers for all subsequent silicon etching steps. As a result, both sides of the Chapter 5. Conclusions 68 wafer must be protected during all photolithography processes, either with photoresist, or by floating the wafer on the buffered HF etchant so that only one side is etched at a time. Since the bolometer will be fabricated from the 5 pm device layer on the wafer, an appropriately sized portion of the handle wafer must be removed. Square windows, 7 mm x 7 mm, are patterned, via photolithography, into the oxide on the backside of the wafer. Because the Si etchant is anisotropic, the resulting sloped walls will form a smaller square opening at the membrane, 6 mm x 6 mm in size. At the same time that the windows are pattered, 50 pm wide scribe lines which traverse the length of the wafer are also patterned into the photoresist. These scribe lines provide defined fault lines along which the wafer can be broken to isolate individual devices. It was found previously that without etched scribe lines, the wafer tended to crack at the boundaries of the etched windows instead of cracking along the surface scribe lines made with a diamond tipped scriber. Also, alignment marks on the mask, under each square opening, provide easy alignment for subsequent masks. Note however, this requires a mask aligner with back side alignment capabilities. Once the oxide has been patterned, the exposed silicon is etched in a hot bath of ethylene diamine pyrocatecol (EDP). The etch is allowed to proceed for 6 hours and is subsequently stopped before the etch is allowed to reach the etch stop layer. The remaining layer of Si (~ 150 pm thick) can be removed at a later time after most of the other processes are completed. The radiation absorbing gold layer should be deposited in a grid pattern which will lie directly on top of the Si mesh. In order for the film to be of a reasonable thickness, the grid is made up of 5 pm wide lines, 150 A thick. The grid spacing is 0.375 mm. Ideally, the supporting Si would also have 5 pm wide legs, but because of the fragility of the mesh as discussed in Chapter 3, this proved infeasible. Instead, the design uses Chapter 5. Conclusions 69 30 pm wide legs since they are mechanically stronger and robust once the buried oxide layer has been removed. As a result, the thinner gold lines must be defined first with photolithography. The gold mesh cannot be deposited after the Si mesh has been etched into a free standing mesh because the mesh does not provide an adequate solid surface to spin on an even film of photoresist. Because of the decision to evaporate gold directly onto Si described in Chapter 4, the metal lift-off technique was not used, and the standard additive photolithography technique was used instead. In this work, this step was only performed on two individual devices instead of the whole wafer, although presumably in practice, one would use the entire wafer. Photoresist was spun only onto the topside of the wafer (leaving the backside clean for the second Au deposition). After exposure and development, they are floated on buffered HF for 3.5 minutes to etch away the exposed oxide on the topside. The chips were not immersed as there was no protective resist coating on the backside. The resist on the topside is left on to await the Au deposition. The two devices were then placed in the thermal evaporator and Au was deposited to a thickness of 150 A. After the evaporation, the chamber was vented and the devices were turned over and placed onto a premade aluminum support. The support design was precisely made so that gold would be evaporated only onto two ellipsoidal areas to form two gold pads on the backside of the Si frame. Because the size and orientation of the gold contact pads is noncritical, this simpler method of deposition was preferred over going through the more time-consuming photolithographic method. The contact pads consisted of 500 A Cr adhesion layer with ~ 1000 A Au. This double layer typically forms robust pads that can be easily soldered to and are more resistant to light scratches. Note that the total heat capacity of the outer frame is not an issue so evaporating Cr as part of the contact pads is likewise not an issue. After all the depositions, the photoresist on the topside was lifted off in acetone with Chapter 5. Conclusions 70 an ultrasonic cleaner. After a rinse in DI water, the Au mesh structures were examined under a high power microscope and found to be intact. Unfortunately, a meander path was not included in the mesh deposition run, so we were unable to measure the resistance of the gold mesh. A meander path should be included in future gold evaporations. At this point, the remaining portions of the handle thickness in the back windows can be removed in EDP. The chips were held on edge in a custom built teflon chip holder and immersed in EDP for approximately 2.5 hours. Unfortunately, the area between the gold mesh lines and the surrounding oxides were not completely sealed. There were gaps in some areas between the gold film and the oxide well walls (the area in the dashed circles in Figure 5.4). As a result, the EDP managed to reach the Si membrane through these joints and undercut the protective oxide layer. After the 2.5 hour etch, all that remained of the membrane layer were small squares so that it was impossible to define the mesh structure. This problem could be avoided in the future by depositing a layer of evaporated Si0 2 over the gold mesh and the existing oxide as a protective layer. This oxide coating would then be removed in the final HF etch when the Si mesh is released from the BOX layer. In conclusion, we have determined a repeatable process to construct Si meshes from from BOX wafers with 5 uxn device layers and have developed a process to determine the necessary film thickness for a gold absorber. A recipe has been developed from which bolometers can be made. Chapter 5. Conclusions 71 gaps SiC>2 Gold film Figure 5.4: Gold film evaporated onto Si with surrounding silicon dioxide walls. The film does not seal with the oxide walls (region indicated by the dashed circles) and there are gaps between the gold film and oxide. Bibliography H.P. Gush and M. Halpern. A cooled submillimeter fourier transform spectrometer flown on a rocket. Rev. Sci. Instrum, 63(6):3249-3260, 1992. H.P. Gush, M. Halpern, and E. Wishnow. Rocket measurement of the cosmic- background-radiation mm-wave spectrum. Phys. Rev. Let, 65(5):537-540, 1990. G.S. Tucker, H.P. Gush, M. Halpern, I. Shinkoda, and W. Towlson. Anisotropy in the microwave sky: Results from the first flight of the balloon-borne anisotropy measurement (BAM). Astrophys. J., 475:L73-76, 1997. P.M. Downey, A.D. Jeffries, S.S. Meyer, R.Weiss, F.J. Bachner, J.P. Donnelly, W.T. Lindley, R.W. Mountain, and D.J. Silversmith. Monolithic silicon bolometers. Ap- plied Optics, 23(6):910-914, 1984. E.E. Haller, K . M Itoh, J.W. Beeman, W.L. Hansen, and V.I. Ozhogin. Neutron transmutation doped natural and isotopically engineered germanium thermistors. Instrumentation in Astronomy VIII, SPIE 2198:630-637, 1994. R. Ulrich. Far-infrared properties of metallic mesh and its complimentary structure. Infrared Physics, 7:37-55, 1967. R.J. Corruccini and J.J. Gniewek. Specific Heats and Enthalpies of Technical Solids at Low Temperatures. National Bureau of Standards, 1960. N. Pearlman and P.H. Keesom. Atomic heat of Si below 100 K. Phys. Rev., 88:398- 405, 1952. O.V. Lounasmaa. Experimental Principles and Methods Below IK. Academic Press, 1974. D.C Alsop, C. Inman, A.E. Lange, and T. Wilbanks. Design and construction of high-sensitivity infrared bolometers for operation at 300 mK. Applied Optics, 31(31):6610-6615, 1992. P.L. Richards. Bolometers for infrared and millimeter waves. J. Appl. Phys., 76(l):l-24, 1994. J.C. Mather. Bolometer noise: nonequilibrium theory. Appl. Opt, 21(6):1125—1129, 1982. 72 Bibliography 73 [13] J.C. Mather. Bolometers: Ultimate sensitivity, optimization, and amplifier coupling. Appl. Opt, 23(4):584-588, 1984. 14 !5 16 !7 18 !9 20 21 22 23 24 25 26 27 28 C. Padwick. Cosmic ray hits during the 1995 bam flight. Unpublished, 1996. P.D. Mauskopf, J.J. Bock, H. Del Castillo, W.L. Holzapfel, and A.E. Lange. Composite infrared bolometers with Si3N4 micromesh absorbers. Applied Optics, 36(4):765-771, 1997. A. Goldin M.S. Kowitt, D.J. Fixsen and S.S. Meyer. Frequency selective bolometers. Applied Optics, 35:5630-5635, 1996. H. Moseley. Thermal conductivity of Si. Private communication, 1998. Karen Chen. Fabricating bolometers using micromachining techniques. Undergrad- uate Thesis, 1997. E. Czyzewska. Pyrocatecol deposits. Private communication, 1997. Kurt Petersen. Silicon micromachining. Proc. IEEE, 70:420, 1982. W. Woods. Si etchant selectivities. Private communication, 1997. G.S. Oehrlein and J.F. Rembetski. Plasma-based dry etching techniques in the silicon intgrated circuit technology. IBM Journal of Research and Development, 36(2):140-157, 1992. W.H. Juan J.W. Weigold and S.W. Pang. Dry etching of deep Si trenches for released resonators in a C l 2 plasma. J. Electrochemical Society, 145(5):1767-1771, 1998. W.H. Juan and S.W. Pang. Control of etch profile for fabrication of Si microsensors. Journal of Vacuum Science and Technology, A14(3): 1189-1192, 1996. G.C. Verkade P. van Attekum, P.H. Woerlee and A.A.Hoeben. Influence of grain boundaries and surface debye temperatures on the electrical resistance of thin gold films. Physical Review B., 29(2):645-650, 1984. J.W.C. De Vries. Temperature-dependant resistivity measurements on polycrys- talline S i0 2 covered thin gold films. Thin Solid Films, 150:201-208, 1987. J.W.C. De Vries. Temperature and thickness dependence of the resistivity of thin polycrystalline aluminum, cobalt, nickel, palladium, silver and gold films. Thin Solid Films, 167:25-32, 1988. D. E. Gray. American Institute of Physics Handbook. McGraw-Hill, 1972. Bibliography [29] W. Woods. Cleanroom process batch sheets. Unpublished, 1997. [30] A. Schmalz. Standard cleanroom operating procedures. Unpublished, 1999. [31] H . Noh. I-V curves of NTD Ge thermistors. Unpublished, 1999. Appendix A Cleanroom Process Recipes * Recipes adapted from Bill Woods' "Process Batch Sheets" [29]. ** Recipes adapted from Al Schmalz's "Cleanroom Standard Operating Procedures" [30]. A . l R C A Clean * 1. Organics clean: In a clean beaker, heat to 80 °C: 1000 mL deionized (DI) water, 150 mL NH 4 OH and 150 mL H 2 0 2 . 2. When temperature is stabilized, soak wafers for 10 minutes. 3. Rinse in DI water for >3 minutes. 4. Native oxide strip: Place wafers in room temperature container with 1500 mL DI water and 150 mL buffered HF for 30 seconds. 5. Rinse in DI water for >3 minutes. 6. Metals: In a clean beaker, heat to 80 °C: 1050 mL DI water, 175 mL HC1 and 175 mL H 2 0 2 . 7. When the temperature is stabilized, soak wafers for 10 minutes. 8. Rinse in DI water for >15 minutes. 9. Spin dry the wafer or use a N 2 air gun. 75 Appendix A. Cleanroom Process Recipes 76 A.2 Oxidation Recipe for a 0.3 pm Oxide Layer * 1. Prior to oxidation, all wafers must be RCA cleaned. 2. Ramp the furnace temperature to 800 °C. There should be a 4scfh flow of N 2 gas through the furnace. 3. Load wafers into proper boat and push the boat into the furnace at <4"/min. 4. Ramp the temperature up to the desired oxidizing temperature (usually 1100 °C). 5. Dry oxidation: Once the temperature is stabilized proceed with a dry oxidation for 10 minutes. N 2 flow rate: Oscfh, 0 2 flow rate: 4scfh. 6. Wet oxidation: Proceed with wet oxidation for 30 minutes. 0 2 gas is bubbled through boiling water at ~0.5 scfh with the N 2 flow rate of 4 scfh. 7. Dry oxidation: Repeat the dry oxidation step. 8. Shut off the oxygen flow, the nitrogen flow rate remains at 4 scfh. Ramp down the temperature to 400 °C. 9. When the furnace temperature is <800°C, pull the boat from the furnace at <4"/min. 10. Once wafers are cool, compare their colour to an oxide colour chart. A blue to blue-green colour when looked face on indicates a thickness ~0.3-0.325 pm. Appendix A. Cleanroom Process Recipes 77 A.3 Boron Diffusion * 1. Prior to oxidation, all wafers must be RCA cleaned. 2. Ramp the furnace to 800 °C. N 2 flow rate: 10 scfh. and 0 2 flow rate: 0. 3. Load the wafers into the boat so that there are 2 wafers per boron source with the polished side facing the source. Place dummy wafers in unused slots. Push the boat into the furnace at <4"/min. N 2 flow rate: 5 scfh. and 0 2 flow rate: 5 scfh. 4. Ramp furnace to operating temperature of 975 °C. N 2 flow rate: 10 scfh. and 0 2 flow rate: 0. 5. Diffusion Leave at operating temperature for desired time. 40 minutes produces a doping concentration of ~ 1018 atoms/cc. N 2 flow rate: 10 scfh. and 0 2 flow rate: 0. 6. Ramp down the furnace temperature to 400 °C. Once all the furnace zones are < 800 °C, the boat can be removed at <4"/min. N 2 flow rate: 5 scfh. and 0 2 flow rate: 5 scfh. 7. Return furnace to idle. N 2 flow rate: 0.5-1.0 scfh. and 0 2 flow rate: 0 scfh. Appendix A. Cleanroom Process Recipes 78 A.4 General Photolithography * 1. On the less critical side of a clean wafer, spin SC??? photoresist for 30 sec at 4000 rpm. (// this side does not need protection, skip this step and proceed to step 3. 2. Soft bake at 100 °C for 5 minutes. 3. Spin photoresist onto the other side of the wafer for 30 sec at 4000 rpm. 4. Soft bake: Soft bake at 100 °C for 25 minutes. 5. Alignment and exposure: Exposure times may vary depending on the type of mask being used and on the underlying substrate. If exposure times are unknown, perform exposure tests on scrap wafers. Align the wafer to the mask. For Kodak photoemulsion masking plates and ther- mally grown silicon oxide, expose the resist with 10mW/cm 2 of UV light for 20 seconds. For chrome on soda lime glass masks, the exposure time is ~8 seconds. 6. Develop: Develop the wafer in Shipleys MF 319 developer for 35-45 seconds. 7. Rinse in DI water for >3 minutes and dry with N 2 gun. 8. Hard bake: Bake for 20 minutes at 120 °C. 9. Inspect for resist defects or mask misalignments. If there are no problems, proceed with subsequent process (eg. oxide etch and doping). Otherwise, strip the resist with acetone and repeat the above steps. Appendix A. Cleanroom Process Recipes 79 A.5 Metal Lift-off ** 1. Spin AZ4210 photoresist onto wafer for 40 seconds at 4000 rpm. This should produce a film ~2.1 pm thick. 2. Soft bake: Soft bake the wafer on a temperature controlled hotplate for 1 minute at 100°C. 3. Soak the sample in AZ300MIF developer for 2 minutes. The goal here is to harden the top portion of the photoresist layer so that the unexposed areas are less sus- ceptible to the AZ400K developer. Rinse in DI water and dry with N 2 gun. 4. Exposure: Expose the resist for 50 seconds to UV light through a chrome on sodalime mask at an intensity of 4 mW/cm 2 (The exposure time may vary depending on mask type, if unsure, run a few exposure tests.) 5. Create overhang: Develop in 1:3, AZ400K-.DI water for 2 minutes. The goal here is to slightly overdevelop the resist so that the hardened top layer of the resist is slightly undercut. Rinse in DI water and dry. 6. Inspect the resist for defects. If all is well, metallize the sample to the desired thickness. 7. Lift-off Strip the photoresist in straight A Z 4 0 0 K or acetone in an ultrasonic cleaner. Appendix A. Cleanroom Process Recipes 80 A . 6 The E C R PlasmaQuest System * Refer to Standard Operating Procedure (SOP) for detailed instructions for this system. 1. Open the appropriate gas cylinders located in or beside the gas cabinets. 2. Open the mass flow controller valves and turn on the water chiller, RF supply and microwave power switches. 3. Login to computer and set up the appropriate recipe for etch times, chamber pres- sure, gas flow rates and microwave power. 4. Load samples into load lock and begin the recipe. 5. Once the microwave power is on, manually turn on the RF power, and set it to the desired DC bias. Turn it off when the microwave power switches off. 6. When the recipe is complete, and the samples have returned to the load lock, vent the chamber and remove the samples. 7. Repeat for other samples. When finished, pump out the load lock and log off the computer. 8. Follow the steps outlined in the SOP to close and vent the gas lines. Appendix A. Cleanroom Process Recipes 81 A.7 Ashing Photoresist with the Technics Plasma Etch II 1. Close chamber valve on front of etcher and ensure all gas lines are closed. 2. Vent the chamber (with the vent switch) and load samples. 3. Close lid and open chamber valve to pump down the chamber to <20mTorr. 4. Set temperature controller to 50° C. 5. Open the oxygen gas line and adjust the flow meter until the pressure reaches ~ 250 mTorr. 6. When the pressure is stable, ignite the plasma. 7. Turn on RF power to 150 W for 10 minutes. 8. Turn off RF power, close oxygen line and chamber valve. Vent chamber to remove samples. Appendix A. Cleanroom Process Recipes 82 A.8 E-Beam Evaporation Using the Balzers Evaporator ** 1. Vent chamber and load samples onto stand, directly above the source. 2. Pump down chamber with roughing pump until the pressure is below 7 x IO - 3 Torr. 3. Close the valve to the roughing pump and open the valve to the cryopump. Note: the cryopump must be cooled to ~ 12-13K beforehand. 4. Turn on the high voltage power supply and water flow to the electron guns 15 minutes prior to evaporation. Set the crystal growth monitor settings for density and z-factor. The tooling should be set to 150 % since the crystal is mounted on the bell jar ceiling, above the sample stage. 5. Once the pressure is below 3 x 10 - 6 Torr, evaporation may begin. Ensure that all emission dials are set to zero and turn on the electron guns. Slowly ramp up the emission current until the beam visibly melts the surface of the source. Align the beam to the centre of the source. Typically, an emission current of 0.4 A and 0.7 A will melt Au and Ti sources respectively and produce film growth rates of 1.2 A/s. Use the shutter to start and finish the evaporation. 6. Once the evaporation is complete, slowly turn down the emission current, then turn off the electron guns. Allow the source and samples to cool for 30 minutes before venting the chamber. Appendix A. Cleanroom Process Recipes 83 A.9 Thermal Evaporation in the B A M Lab Bell Jar 1. Vent chamber and load samples onto stand, directly above the source. Move the crystal growth monitor as close to the samples as possible. 2. Pump down the chamber and turn on the high voltage glow discharge rod. Once the pressure is < 3 x 10 - 2 Torr, turn on the diffusion pump heater. Be sure that there is water flowing through the cooling lines to the diffusion pump and the crystal growth monitor. 3. When the pressure is < 7 x 10 _ 3Torr, close the roughing pump line and begin pumping on the diffusion pump. When the thermocouple on the heater reads > 2.5 mV and the diffusion pump pressure is ~ 10 - 3 Torr, open the gate valve to the chamber. 4. Backfill the chamber with Argon gas once the pressure has dropped to 10 - 5 Torr. Run the discharge again, maintaining the pressure at ~ 3.5 x 10 - 2 Torr and leaving the Argon plasma on for ~15 minutes. Pump out the chamber again as before. 5. When the pressure is below 3 x 10 - 6 Torr, the evaporation may begin. Turn on the filament and ramp up the current until the source begins to melt. Use the shutter to control the film thickness. 6. Once the evaporation is complete, turn down the filament current and wait for the source and sample to cool. 7. Close the chamber gate valve. Turn off the diffusion pump heater but continue to pump on the oil until cool. At this point, the chamber may be vented and the samples removed. Appendix A. Cleanroom Process Recipes 84 A. 10 Anisotropic Si Etch: E D P or T M A H * 1. Heat fresh etchant in a beaker with a reflux condenser to operating temperature. EDP: 95 °C, TMAH: 85 °C. 2. Ensure that the wafer is appropriately masked with a material that is not etched in by the etchant (SiO"2 or gold are good masking materials). 3. Once the etchant temperature is stable, place the wafer into solution. The EDP etch rate is on average ~70 //m/hour, while T M A H etches at ~40 /xm/hour, so time the etch accordingly. Do not remove the wafer until etch is complete. 4. Remove the wafer and immediately rinse with DI water for >5 minutes. 5. Dry with N 2 gun or rinse with isopropanol and heat dry in oven. A . 11 Oxide Etch: H F * 1. The sample is first patterned with photoresist using photolithography. 2. After the hardbake and inspection, place the sample in Transene buffered HF solu- tion. This solution etches thermally grown oxide at ~0.1/im/min. Time the etch accordingly to avoid undercutting the photoresist. Note: Since Si is hydrophobic, one can tell by eye when the etch is complete since the etched areas will "dewet" once the HF reaches the underlying Si. 3. Rinse the sample for 5 minutes in running DI water, and dry with N 2 gas. Appendix B Si Wafers and Processing Chemicals Suppliers Single side and double side polished wafers: Silicon Sense #217-110 Daniel Webster Hwy Nashua, New Hampshire 03060-5252 B O X wafers: SiBond L.L.C. (no longer in business) 501 Pearl Dr. P.O. Box 8 St. Peters, Mo 63376 SEH America 4111 N.E. 112th Ave. Vancouver, Wa 98682-6776 Processing Chemicals: Transene Co. Inc. 10 Electronics Ave Davers, Ma 01923 85 Appendix C N T D Ge Thermistors The detector response to temperature changes depends entirely on how the thermistor's resistance responds to temperature changes. A steep resistance-temperature function over the operating temperature range is most desirable. Typically, doped semiconductors, such as Si or Ge, exhibit this electrical behaviour. The type of dopant and doping concentration determine the useful operating range for bolometers. For example, silicon chips doped with arsenic and phosphorous and metallized with bismuth, have been used as monolithic bolometers [4]. The thermistors used in this project are ultra pure germanium chips that have been neutron transmutation doped (NTD) to a doping concentration suitable for use at 300 mK by Haller et al. [5]. After the NTD process, the Ge crystals were thermally annealed at 400 °C to remove crystal lattice damage from the energetic neutrons, and to move dopant atoms to crystal lattice sites. Finally, to form electrical contacts, the two opposing surfaces are highly doped with boron and subsequently metallized with 100 A Pd and 4000 A Au. Previously, the Haller thermistor chips that are currently being used as part of the B A M bolometers, have been characterized and found empirically to have a resistance that is described by R{T) = RaeVW, where Ra and TQ are constants with values of 200 Q and 49 K respectively. 86 (Cl) Appendix C. NTD Ge Thermistors 87 Because the thermistor elements are individually diced from a large sample their physical dimension vary to within tens of microns and hence R0 may vary from element to element. This effect is probably insignificant and characterizing one thermistor should indicate how the rest will operate. Electrical connections were made to one thermistor element with indium solder and 0.0003" diameter brass wires. The wires were then soldered to posts and the chip was glued to a fiberglass base with epoxy. To test the feasibility of using our bolometers in quantum well experiments, one thermistor was sent to Daniel Tsui's lab in Princeton University where several tests were performed by Noh to characterize the thermistor response to temperature changes and to applied magnetic fields [31]. The results are graphed in Figures C.1-C.5. By fitting the slopes of the curves in Figure C.3 at zero bias current for the different temperatures, one can deduce a resistance-temperature relationship using ( C l ) . The fitted slopes are given in Table C l . Temp (mK) R (MQ) 23 7637 64 7138 93 4879 152 2729 202 860 297 80 Table C l : Fitted values of R at I = 0 and V = 0. In Figure C.2, we fit the last three data points to ( C l ) (assuming the thermistor freezes out below 150 mK) and calculate the values for the coefficients R0 and T 0 to be, R0 = 2300 and T 0 = 32.8. The value of R is roughly an order of magnitude larger than expected. This could be due to the experimental setup, but the matter was not pursued. Appendix C. NTD Ge Thermistors 88 ~~i 1 1 1 1 1 r T=23 mK 0.1 > -0.1 T=64 mK T=93 mK ! / .< / / I i T=150 mK / T=200 mK !\ 11 / / / ' » i / y h T=300 mK _i i i_ _i i i i_ -1x10" -5x10 -10 0 Current (A) 5x10" 10" Figure C l : I-V curves for NTD Ge thermistors at various temperatures [31]. Appendix C. NTD Ge Thermistors 89 (7 1 i I I I I I I I I I , I I I 1 1— 0.1 0.2 0.3 Temperature (K) Figure C.2: R(T) calculated from the last 3 data points in Table C l . (x) Data, (-) Fit. Appendix C. NTD Ge Thermistors 90 Figure C.3: Temperature sweep of a thermistor biased with a constant current of 0.5 nA (-) and 1.0 nA (--) with no applied magnetic field.[31] Appendix C. NTD Ge Thermistors 91 Figure C.4: Thermistor resistance vs applied magnetic field strength at T=30 mK. The thermistor is biased with a constant current of 0.5 nA (-) and 1.0 nA (--). [31] Figure C.5: Thermistor resistance vs applied magnetic field strength at T=300 mK. The thermistor is biased with a constant current of 0.5 nA (-) and 1.0 nA (--). [31]


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