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A single phase Al₀ 3Ga₀ 7As/GaAs heterojunction resistive-gate charge-coupled device Wohlmuth, Walter Anthony 1992

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A SINGLE PHASE A103GamAs/GaAs HETEROJUNCTIONRESISTIVE-GATE CHARGE-COUPLED DEVICEbyWALTER ANTHONY WOHLMUTHB.A.Sc., The University of British Columbia, 1990A THESIS SUBMI 1 I ED IN PARTIAL FULFILMENT OFTHE REQUIREMENTS FOR THE DEGREE OFMASTERS OF APPLIED SCIENCEinTHE FACULTY OF GRADUATE STUDIESDEPARTMENT OF ENGINEERING PHYSICSWe accept this thesis as conformingto the required standardTHE UNIVERSITY OF BRITISH COLUMBIASeptember 1992© Walter Anthony Wohlmuth, 1992In presenting this thesis in partial fulfilment of the requirements for an advanceddegree at the University of British Columbia, I agree that the Library shall make itfreely available for reference and study. I further agree that permission for extensivecopying of this thesis for scholarly purposes may be granted by the head of mydepartment or by his or her representatives. It is understood that copying orpublication of this thesis for financial gain shall not be allowed without my writtenpermission.Department of 	5,,,1at rJEE 1.1C1 P gys%cSThe University of British ColumbiaVancouver, CanadaDate 	oc-r.	 112.DE-6 (2/88)AbstractThe design, fabrication, and evaluation of a 128 pixel, single phase A10.3GavAs/GaAsheterojunction resistive-gate charge-coupled device (HRGCCD) is described. TheHRGCCD has a higher operating speed and a larger charge handling capacity incomparison to the conventional buried channel, resistive-gate GaAs charge-coupled device(GaAs RGCCD). The higher operating speed of HRGCCDs is due to the higher electronmobility and velocity in an AlGaAs/GaAs heterojunction in contrast to a GaAshomojunction. In addition, the HRGCCDs can be integrated with high-speed on-chip highelectron mobility transistors (HEMTs). The larger charge handling capacity of a HRGCCDis the direct result of the higher electron density in a HRGCCD in comparison to a GaAsRGCCD. A quantum mechanical model is used to calculate the carrier density in atriangular potential well formed at the interface between an undoped AlGaAs layer and anundoped GaAs layer. This model is coupled to a solution of Poisson's equation in bulkAlGaAs to determine the total carrier density in a HRGCCD for different layer andmaterial specifications. This model is used to aid in the design of the HRGCCD. Thefabrication of the HRGCCD required six mask levels employing 405 nm contactphotolithography with a 1.0 tim design rule. Developments in the process technologypreviously employed at TRIUMF were required to create the HRGCCDs. Thesedevelopments included a standard chlorobenzene-aided photoresist lift-off process todelineate r.f. magnetron sputtered Cr:SiO islands and a dry etch process to createiiinterconnect vias. Two process runs of HRGCCDs, with differing layer parameters, werefabricated and evaluated at 4.33 MHz and at 50 MHz. The HRGCCDs tested at 50 MHzexhibited a charge transfer efficiency in excess of 0.99, and a dynamic range in excess of 50dB with a linear response over a 40 dB input signal range.iiiTable of ContentsAbstract 	  iiTable of Contents 	  ivList of Tables 	  viList of Figures 	  viiList of Symbols 	Acknowledgements1. INTRODUCTION 	  12. DEVICE THEORY AND OPERATION 	  122.1. AlGaAs/GaAs Heterojunctions 	  122.2. Design of the HRGCCD's Active Layers 	  162.3. Operation of the HRGCCD 	  26	3. DEVICE FABRICATION   323.1. Ohmic Contact Formation 	  32	3.2. Device Isolation     34	3.3. Cermet Deposition     353.4. Gate Metal Deposition 	  403.5. Interlayer Dielectric and Via Formation 	  403.6. Second Level Metallization 	  44iv4. DEVICE CHARACTERIZATION 	  475. SUMMARY AND PROSPECTS FOR FUTURE WORK	  525.1. Summary 	  525.2. Considerations for Future Work 	  54BIBLIOGRAPHY 	  55APPENDIX A: Program Listing for the Carrier DensityCalculations 	  63APPENDIX B: The HRGCCD Fabrication Procedure 	  70APPENDIX C: HRGCCD Bonding Configuration 	  78List of TablesTable I: A summary of different GaAs based CCDs 	  8Table II: The n-A10.3GavAs layer parameters for the HRGCCDs 	  18Table III: The signals applied to the HRGCCD and theircorresponding voltage levels 	  31Table IV: The settings used for the CF4:02 and 02 reactiveion etches 	  43Table V: The charge transfer efficiency of HRGCCDs from runs A07 and A08 . . . . 49viList of FiguresFigure 1.1: The potential distribution along the channel of a GaAs CGCCD 	  3Figure 1.2: The potential distribution along the channel of a GaAs RGCCD 	  6Figure 1.3: A schematic diagram of; (a) a HRGCCD, (b) the on-chip HEMTcircuit 	  9Figure 2.1: The energy band diagram of an n-AlGaAs layer and an undoped GaAslayer; (a) not in contact, with the vacuum level chosen as the point ofreference, (b) in contact, under zero bias conditions   13Figure 2.2: The energy band diagram of a HRGCCD 	  20Figure 2.3: The measured and theoretical capacitances of Schottky-barrier diodesfrom the A07 and A08 process runs 	  25Figure 2.4: (a) The input stage of a HRGCCD. The surface potential distributionwhen the 44 clock is at: (b) 0.0 V, (c) -4.0 V 	  27Figure 2.5: (a) A portion of the transport region of a HRGCCD. The surfacepotential distribution at time: (b) t=to, (c) t=t i, and (d) t=t2. (e) Thevoltages applied to the transport electrodes   28Figure 2.6: A diagram of the output stage of a HRGCCD, and the on-chipHEMTs 	  30Figure 3.1: An overview of the HRGCCD fabrication procedure 	  33viiFigure 3.2: Deposition of the cermet and gate metal using, (a) the unaided, and (b)the chlorobenzene-aided photoresist lift-off process 	  36Figure 3.3: A photograph displaying gate metal electrodes placed on top of cermetfilm which contains wings 	  37Figure 3.4: A photograph of the sidewall profile of AZ4210, 2.1 p.m photoresistemploying, (a) the unaided, and (b) the chlorobenzene-aided photoresist lift-off process   38Figure 3.5: A photograph of the sidewall profile of overexposed AZ4210, 2.1 p.mphotoresist 	  39Figure 3.6: The three-step reactive ion etch process used to form the interconnectvias 	  42Figure 3,7: A photograph of completed interconnect vias. The vias areapproximately 4 pm square separated by a gap approximately 4µm long . . . 43Figure 3.8: A photograph of the entire HRGCCD. The bonding pads are 96 pmsqu are 	  45Figure 3.9: A photograph of the input section of the HRGCCD 	  45Figure 3.10: A photograph of a portion of the transport region of a HRGCCD . . . 	  46Figure 3.11: A photograph of the output section of a HRGCCD 	  46Figure 4.1: A photograph of the input and output waveforms of a HRGCCDoperated at 4.33 MHz 	  48AliFigure 4.2: A photograph of the output waveform of a HRGCCD operated at 4.33MHz. There are 100 nS per division on the horizontal scale and 200 mV perdivision on the vertical scale   48Figure 4.3: The measured and theoretically calculated frequency response of aHRGCCD operated at 50 MHz 	  50Figure 4.4: The frequency response of a HRGCCD operated at 50 MHz with theinput signal attenuated in steps of 10 dB 	  51Figure 4.5: The linearity of the HRGCCD response for a 12.5 MHz input signal . . . 51ixList of SymbolsAll energies are referenced to the Fermi level energy unless otherwise stated.A 	 area of a Schottky-barrier contact padB	insertion lossBo 	 insertion loss normalization factorc, 	 capacitance of a Schottky-barrier dioded	 thickness of the undoped AlGaAs layerD	2-dimensional density of statesE0 	fh st energy level in the 2-dimensional electron gas, referenced to the bottomof the potential well at the AlGaAs/GaAs interfaceE1	second energy level in the 2-dimensional electron gas, referenced to thebottom of the potential well at the AlGaAs/GaAs interfaceEc 	 conduction band energyEa 	 conduction band energy at the doped/undoped AlGaAs interface, referencedto the bottom of the potential well at the GaAs/AlGaAs interfaceEf 	 Fermi level energyEn	 Fermi level energy, referenced to the bottom of the potential well at theAlGaAs/GaAs interfaceEg 	 band gap energyEmu, 	 minimum conduction band energyEv 	valence band energyE 	 conduction band energy at an arbitrary point along the x-axisf 	 input signal frequencyfc	operating frequency of the HRGCCDsFs	 urface electric fieldi 	 integer indexk 	 Boltzmann's constanteffective mass of electrons in GaAsnd	density of ionized donors in the depletion region underneath a Schottky-barrier electrodeof	density of free carriers in the doped AlGaAsnm	maximum density of carriers in the 2-dimensional electron gasns	density of carriers in the 2-dimensional electron g&sNe 	effective density of states in the conduction bandNd	 density of donor impurities in the doped AlGaAsNd+	density of ionized donor impurities in the doped AlGaAsN, 	 number of single electrode transfers in the HRGCCDq 	 electronic chargetotal chargethickness of the doped AlGaAs layerT 	 absolute temperatureVg 	applied bias to a Schottky-barrier electrode\ Toff	 pinch-off voltage of the HRGCCDVt 	 thermal voltage, kTxix)(minyYo, YiAEcAEdAE,EAlGaAs —EGaAsXA1GaAs —XGaAshdepth in the HRGCCDlocation of the minimum in the conduction band energya dummy variable for integrationShubnikov-de Haas constantsconduction band discontinuitydonor level energy referenced from the conduction band energyvalence band discontinuitypermittivity of AlGaAspermittivity of GaAsefficiencyan arbitrary point along the x-axisspace charge densitySchottky-barrier heightelectron affinity of AlGaAselectron affinity of GaAsreduced Planck's constantxiiAcknowledgementsI would like to express my thanks to my thesis supervisors, Dr. Maurice LeNobleand Dr. Tom Tiedje for their assistance and counsel. I would also like to thank Mr. JohnV. Cresswell for co-supervising this project and for his guidance and judgments.I thank Dr. Maurice LeNoble, Mr. John V. Cresswell, Dr. Richard R. Johnson, andDr. Douglas Bryman for offering me the opportunity to work on this project at TRIUMF.I am especially indebted to Mr. David Webster and Mr. Raymond Bula for theirassistance, patience, and time in the microelectronics lab at TRIUMF.I would also like to extend my thanks to Miles Constable, Beverly Wilson, NaomiShibaoka, and Yvonne Langley for their help in technical aspects of this project.1. INTRODUCTIONThe gallium arsenide charge-coupled device (GaAs CCD) was originally proposedby Schuermeyer et al. in 1972[1], and consists of an array of metal-GaAs Schottky-barrierelectrodes separated by small, dielectric filled gaps. This structure is known as a capacitive-gate CCD (CGCCD). A GaAs CGCCD was first demonstrated by Kellner et al. in 1977[2],with a charge transfer efficiency (CTE) of 0.98 at frequencies between 5 kHz and 1 MHz[2].Since then, attempts have been made to increase the CTE and the operating frequency ofa GaAs CGCCD for the purpose of ultra-high frequency signal processing[3,4]. In 1981,Cohen et al.[3] demonstrated the operation of a GaAs CGCCD at a frequency of 1 GHzwith a CTE of 0.994, and in 1984, Sovero et al.[5] reported a GaAs CGCCD with a CTEof 0.999 at 1 GHz.Potential wells, also termed energy troughs, may form within the GaAs CGCCDactive layer, underneath the gaps, due to a non-monotonically varying potential along thedielectric/GaAs interface[6,7]. The energy troughs capture a small quantity of charge froma passing charge packet. The trapped charge may be released from the energy troughs aftera period of time or may be lost through recombination, resulting in greater charge transferinefficiency and subsequent CCD performance loss[7,8].1A schematic illustration of a portion of the transport region of a GaAs CGCCD isshown in Figure 1.1(a). The GaAs CGCCD active layer thickness is typically greater than1 p.m and the active layer doping density is usually between 10 15 to 1016 cm-3[9]. Theelectrodes are separated by gaps approximately 1 gm long. The transport electrodes areidentified as 401, 44A, 402, and 4)2A. A non-monotonic potential distribution along thechannel of a GaAs CGCCD, in single phase operation, is shown in Figures 1.1(b) and1.1(c), to demonstrate charge trapping by energy troughs. Initially, a charge packet is shownto reside underneath the 44A electrode when the voltage signals applied to the transportelectrodes are such that 4)1A > 4)1 4)2A > 4)2, as displayed in Figure 1.1(b). In Figure1.1(c), the signals applied to the electrodes change, from their initial values to 4)2A > 4)2> 44A > 4)1, by the application of a clock pulse to the 44 and 41A electrodes. Thecharge packet will be transferred to the potential well formed underneath the 4)2Aelectrode, as shown in Figure 1.1(c). Some of the charge from the charge packet is trappedin the energy troughs formed between the 4)1 and 431A, and the 4)1A and 4)2 electrodesresulting in decreased charge transfer efficiency.Deyhimy et al.[7] developed a two-dimensional electrical analogue of a GaAsCGCCD to investigate the relationship between the spacing of the CGCCD Schottky-barrierelectrodes and the relative magnitude of the energy trough. They found that the relativemagnitude of the energy trough was reduced as the gap length was reduced[7]. Colbeth etal.[9] showed that the magnitude of the energy troughs in a GaAs CGCCD is proportionalto the active layer doping density and inversely proportional to the active layer thickness[9].21611//4112 WI A I 	 rIr _I 	 r 	 rAir.n—GaAs 1••••■--- 	1 111:11charge packetNenergy troughs(b 0(I)2A 	 cl)1A 	 1,2A 	 c1)1O O O O O O 1 um            ti	 Semi—insulating GaAs substrateIdistancetrapped charge/energy troughsdistancecharge packetx( c)Figure 1.1: The potential distribution along the channel of a GaAs CGCCD.They found that a GaAs CGCCD with an electrode spacing of 1 gm, an active layer dopingdensity of 7.040' cm 3, and an active layer thickness of 0.90 gm possessed a CTE in excessof 0.999[9]. Colbeth et al. demonstrated that the doping density of the active layer of aGaAs CGCCD should be between 10 15 - 1016 cm-3, for an active layer thickness ranging from0.35 gm to 0.90 gm, to achieve CTEs greater than 0.99[9]. Metal-semiconductor field-effect3transistors (MESFETs), which are monolithically integrated with the GaAs CGCCD,typically require thin, highly doped active layers for optimal perforrnance[10,11,12]. Sincethe GaAs CGCCD requires relatively low doping levels and a thick active layer incomparison to conventional GaAs MESFETs, the performance of the on-chip MESFETswill be compromised[13].Song et al.[14] proposed a recessed gap GaAs CGCCD in 1989. They found that byrecessing the gaps, the effect of energy troughs on GaAs CGCCD performance is reducedand the compatibility of the GaAs CGCCD with on-chip MESFETs is increased, becausea recessed gap GaAs CGCCD can be fabricated on thin, highly doped active layers[14].Song et al.[14] fabricated recessed gap GaAs CGCCDs with a GaAs active layer thicknessbetween 0.135 and 0.285 pm, a GaAs active layer doping density between 1.2 and 2.0.10 17cm', and recessed gaps between 0.05 and 0.13 pm deep. These devices were operated ata clock frequency of 12 MHz, demonstrating C 1 Es approaching 0.9999[14]. Difficulties infabrication of recessed gaps, uniformity of the etch across the wafer, and reduced fringingfields in the gap region were identified as the main problems with this design[14].An increased compatibility with on-chip MESFETs and an elimination of energytroughs is obtained from the GaAs resistive-gate CCD (RGCCD). The first GaAs RGCCDwas demonstrated by Higgins et al. in 1982[10]. In 1984, Sovero et al.[15] operated a GaAsRGCCD at frequencies ranging from 1 MHz to 4 GHz with a CTE of 0.99 at 2.5 GHz[15].4The GaAs RGCCD has short transport electrodes separated by wide gaps. Theelectrodes are usually placed on top of a thin layer of conductive cermet material thatcovers the surface of the GaAs active layer in the transport region of the GaAsRGCCD[16,17]. The cermet material used for a GaAs RGCCD is a metal-insulatorcomposite[10,16,18]. A cermet film can be modelled as a distributed resistance/capacitancestructure[19]. LeNoble et al.[18] developed a transmission line model of the cermet/GaAsinterface to investigate the surface potential variation in the gaps of a GaAs RGCCD. Theyshowed that the surface potential distribution in the gaps of a GaAs RGCCD is monotonicfor all frequencies. The formation of energy troughs between the electrodes is suppressedbecause the surface potential variation is monotonic. Due to the suppression of energytroughs in GaAs RGCCDs, these devices can be fabricated on thin, highly doped activelayers enabling compatibility with a MESFET process[10].A schematic illustration of a portion of the transport region of a GaAs RGCCD isshown in Figure 1.2(a). The GaAs active layer thickness is typically less than 1 p.m, and theactive layer doping density is usually 10 17 cm 3[9,16,18]. The resistive-gate electrodes areseparated by gaps greater than 1 long[9,18]. A monotonic potential distribution alongthe channel of a GaAs RGCCD, in single phase operation, is shown in Figures 1.2(b) and1.2(c), to demonstrate the suppression of energy troughs. Initially, a charge packet is shownto reside underneath the (1)1A electrode when the voltage signals applied to the transportelectrodes are such that 101A > 431 (102A > 4)2, as displayed in Figure 1.2(b). In Figure1.2(c), the signals applied to the electrodes change, from their initial values to c132A > 4)25> 1 urn 	 n—GaAs0.2 um1 UrnSemi—insulating GaAs substrate T-Tcharge packet(b)> c13.1A > (1)1, by the application of a clock pulse to the 4)1 and (131A electrodes. Thecharge packet will be transferred to the potential well formed underneath the (132Aelectrode, as shown in Figure 1.1(c). The monotonic surface potential variation in the gapssuppresses the formation of energy troughs, resulting in low charge loss.(1)2A (13.1 43.1A (I)2 43.2A (1)10 0 0 0 0 0(a)V/A--2 2 	 V A 	 1////1 	 IZ/A 	 DTI	 Viii1-111---- 	Cermetdistance(c)charge packetdistance xFigure 1.2: The potential distribution along the channel of a GaAs RGCCD.6Improvements in AlGaAs/GaAs heterojunction fabrication technology have enabledthe realization of heterojunction AlGaAs/GaAs CCDs. These devices have two significantoperational advantages over GaAs CCDs. The main advantages are: increased operatingspeed and increased dynamic range. The increased device speed is a result of two primaryfactors. Heterojunction AlGaAs/GaAs CCDs can be monolithically integrated with highelectron mobility transistors (HEMTs). HEMTs have superior transport characteristicscompared to conventional MESFETs due to higher electron mobility and higher electronvelocity in A1GaAs/GaAs heterojunctions than in GaAs homojunctions[20,21]. Theincreased dynamic range of a heterojunction AlGaAs/GaAs CCD is a result of higher carrierdensities. The carrier density in an AlGaAs/GaAs CCD can be up to 2.0. 1012 cm-2[22],while the highest carrier density in a GaAs CCD is approximately 2.0.10 11 cm -2[9,18].Liu et al.[23] fabricated the first heterojunction CGCCD (HCGCCD) in 1979. Thedevice used a layer of A10.22Ga0.78As placed on top of a semi-insulating GaAs substrate.Milano et al.[24,25] created a modified AIGaAs/GaAs HCGCCD in 1982, that exhibited aCTE of 0.98 at 6 kHz and 0.9 at 100 kHz.The extension of the GaAs RGCCD to heterojunction materials was suggested byMilano et al. in 1983[25], but not realized. Song et al.[26] demonstrated the operation ofthe first AlGaAs/GaAs heterojunction RGCCD (HRGCCD) in 1991. The device exhibiteda CTE of 0.999 for frequencies between 10 MHz and 1 GHz[26].7Figure 1.3(a) displays a schematic representation of a HRGCCD. The input andoutput ohmic contacts of the HRGCCD are labelled I/O and 0/P, and the Schottky-barrierelectrodes, which control charge injection and charge extraction in the HRGCCD, arelabelled Gl, G2, and G3. The on-chip HEMT circuitry which senses the presence of acharge packet at the 0/P node of the HRGCCD is comprised of a reset HEMT and aHEMT amplifier. R/G is the gate electrode and R/D is the drain electrode of the resetHEMT. B/D is the drain electrode, B/S is the source electrode, and B/0 is the outputelectrode of the HEMT amplifier. A schematic diagram of the on-chip HEMT circuit isgiven in Figure 1.3(b).The different CCDs described in this chapter are summarized in Table I. The activelayer thickness, the active layer charge density, the electrode spacing and the on-chiptransistor technology are listed for each of the CCDs.Device Thickness Charge Density ElectrodeSpacingTransistortechnologyCGCCD > 1µm 1 - 3.1010 cm -2 5 1µm MESFETrecessed gapCGCCD < 0.3 gm 2.1011 cm-2 5. 1µm MESFETRGCCD < 1 gm 2.1011 cm -2 > 1µm MESFETHCGCCD < 0.2 gm 1012 cm-2 5 1 µm HEMTHRGCCD < 0.2 gm 1012 cm -2 > 1µm HEMTTable I: A summary of different GaAs based CCDs.8G1I/O0 0 0 0G2 	 41 	 41A 4)2 	 42A 410 	 0 	 0 	 0 	 oCerrnet42A G30 	 00/P R/G R/D	  ° 	 f n-A1GaAs- 0.2 urn	 Undoped A1GaAs SpacerGaAs Buffer< 0.2 urn0.004 urnB/D B/0Legend:- Schottky barrier metallization- ohmic contact metallizationAMA - isolated regions- cermet0 o B/sR/D B/Db 	R/GB/SThere are a variety of applications that can employ HRGCCDs. These applicationsinclude: electrooptical signal processing for spectrum analyzers[27], optical matrixmultipliers[28,29], video signal processing[30,31,32], optical imaging systems[9,33,34], andbeam forming systems for radar and sonar systems[35].A 128 pixel, single phase HRGCCD was fabricated at the Tri-University MesonFacility (TRIUMF, Vancouver, Canada) for application in a 500 MHz transient digitizersystem[36,37,38]. This system will become part of the rare kaon decay spectrometer forExperiment number 787 at Brookhaven National Laboratories (BNL, New York,U.S.A)[39,40,41].The design, fabrication, and evaluation of HRGCCDs fabricated at TRIUMF will bepresented. A description of the AlGaAs/GaAs heterojunction and the design of aHRGCCD will be given in Chapter 2. A self-consistent solution of Schrodinger's andPoisson's equations aided in the design of the HRGCCD. The technique used to inject andsense charge in the HRGCCD, and the clocking scheme applied to the transport electrodesof the HRGCCD, will also be detailed in Chapter 2. In chapter 3, the fabrication of aHRGCCD and the modifications of the process technology previously employed atTRIUMF will be presented. The modifications included: the development of achlorobenzene-aided photoresist lift-off process to reduce the formation of wings in a r.f.magnetron sputtered cermet film, and the development of a reactive ion etch process toobtain a high degree of etch anisotropy for the purpose of forming interconnect vias.10Device performance measurements and tests will be described in Chapter 4. The tests wereused to characterize the HRGCCD die, and the measurements were used to determine theCTE, the dynamic range, and the linearity of the response of the devices. A summary andconsiderations for future work will be presented in Chapter 5.112. DEVICE THEORY AND OPERATIONA quantum mechanical model will be developed in section 2.1. to calculate thecarrier density in the triangular, quantum mechanical, potential well. In section 2.2, thequantum mechanical model will be coupled to a solution of Poisson's equation in the bulkAIGaAs to determine the capacitance-voltage (C-V) profile of a Schottky-barrier. Thetheoretical C-V profile will be compared to measured C-V profiles of Schottky-barrierdiodes fabricated with the HRGCCDs. The injection, transport and detection of charge ina HRGCCD will be described in section 2.3.2.1. AlGaAs/GaAs HeterojunctionsA triangular, quantum mechanical, potential well is formed when a doped AlGaAslayer is grown on top of an undoped GaAs layer, due to the different electron affinities ofGaAs and AIGaAs[22]. The well extends from the AlGaAs/GaAs interface into theundoped GaAs layer. The energy band diagram of an n-AIGaAs layer and an undopedGaAs layer is displayed in Figure 2.1, E c is the conduction band energy, Ev is the valenceband energy, Ef is the Fermi level energy, En is the Fermi level energy referenced to thebottom of the potential well, Eg is the energy band gap, AE c is the conduction banddiscontinuity, .6,Ev is the valence band discontinuity, XAIG,A, is the electron affinity of AIGaAs,and XGaAs is the electron affinity of GaAs.12(a) z(b)E g,AIGaAsE v,A1GaAs 	Eg,GaAsAE,2DEGE,EfE,E f IX AlGaAs	vacuum level 		E c,A1GaAs 		E f,A1GaAs  	 X GaAsAE,Ec,GaAsEf,GaAsEv,GaAsAIGaAs GaAsFigure 2.1: The energy band diagram of an n-AIGaAs layer and an undoped GaAslayer; (a) not in contact, with the vacuum level chosen as the point of reference, (b) incontact, under zero bias conditions.Free electrons in the doped AIGaAs layer diffuse into the lower energy GaAs layer andbecome trapped in the potential well. Electron motion in the well is quantized in the z-direction, defined in Figure 2.1, because the de Broglie wavelength of the electrons in thewell is larger than the width of the well[22,42]. The quantization of electron motion resultsin the formation of a two-dimensional electron gas (2DEG) within the potential well. Theexistence of a 2DEG at the AIGaAs/GaAs interface has been experimentally verified usingShubnikov-de Haas magnetoresistance oscillation measurements, and cyclotron resonance13measurements[43].Stern et al.[44] have calculated the discrete energy levels in the 2DEG by solvingSchrodinger's wave equation for a triangular potential well. The energy levels are given by2 11 2 	 2E = 	 — 3 	 q F + 1452m * 	 2 	 s 1 4"i = 0,1,2,-- (1)Here, h is the reduced Planck constant, m* is the effective mass of the electrons in GaAs,and Fs is the surface electric field. F s is related to the carrier density (n a) in the 2DEG byGauss's law[22]eabisf's = qns 	 (2)where e GaAs is the permittivity of GaAs. By substituting the surface electric field, fromequation (2) into equation (1), the energy levels in the 2DEG can be written as2ET = y i n.: i = 0,1,2,-- (3)The Shubnikov-de Haas constants, yo and y l , have been approximated by Linh et al.[45] tobe 1.16.10 -9 eV•cm4/3 and 1.49.109 eV•cm 4/3 respectively.14The carrier density in the 2DEG can be expressed asE1 Cons = D f  dE 	Eo + e kT	 El + e kTq(E-Efl )	 q(E - Efl )	+ 2 f 	dE 	 (4)using Fermi-Dirac statistics and assuming that only the first two energy levels in thepotential well are populated with electrons. Here, En is the Fermi level energy referencedto the bottom of the potential well, k is Boltzmann's constant, T is absolute temperature,and D is the two-dimensional density of states of the electron gas which is[22]D = g m* - 3.24.1013 cm -2 V -1701 2.Applying the identityf 	 1 +e	 -1n(1 +CY)to equation (4), ns can be written asq(Efi -E0) 	q(Efi - E1))1n_ D kT 	÷e kT	 +e kTSubstituting E0 and E1 from equation (3) into equation (7) yields(5)(6)(7)q (En -y o ns213))( 	 q (Ell - y ins213)kT	 + e 	kT	 )1 (8)This equation establishes a relationship between En and n s which will be used in the15development of a theoretical model of the C-V profiles of Schottky-barrier diodes fabricatedwith the HRGCCDs.2.2. Design of the HRGCCD's Active LayersThe design of the active layers for the HRGCCDs and the development of atheoretical model to determine the C-V profile of a Schottky-barrier diode is presented inthis section. The theoretical C-V model was developed by solving Poisson's equation in thebulk AlGaAs, to find the conduction band energy and the carrier density as a function ofthe bias applied to a gate electrode, and coupling this solution to the equation for thecarrier density in the 2DEG, equation (8), developed in the previous section. TheHRGCCDs consist of, from bottom to top: an undoped, liquid-encapsulated Czochralskigrown, semi-insulating <100> GaAs substrate, a 1 undoped GaAs buffer layer, a 40 Aundoped Al0.3Ga0.7As spacer layer, a uniformly doped n-A10.3GacoAs active layer designedto produce a pinch-off voltage of -1.4 V, and a 100 A, 1.1018 cm -3, uniformly doped n+-GaAs cap layer.The 100 A GaAs cap layer is used to aid in the formation of ohmic contacts for theHRGCCD. This layer is removed after the ohmic contacts have been formed and thereforewill not be considered in the solution of Poisson's equation.16An undoped AlGaAs spacer layer is commonly placed in between the doped AlGaAsand the GaAs buffer layer to spatially separate the impurities in the doped AlGaAs layerfrom the 2DEG. This layer reduces impurity scattering of electrons in the 2DEG[46], andlessens the probability of electron tunnelling from the 2DEG to the doped AlGaAs layer.Shur found that the optimal spacer layer thickness is between 40 and 100 A[46].The thickness of the uniformly doped n-A10.3Ga0.7As layer was calculated to producea pinch-off voltage (Voff) of -1.4 V for different active layer doping densities. Voff can befound from the following relationship[47]AE qN d t2Voff = - -where 41b is the Schottky-barrier height, Nd is the doping density of the n-A10.3Ga0.7As layer,t is the thickness of the n-A10.3Ga0.7As layer, and EAG,A., is the permittivity of A10.3Ga0.7As.The terms ch, DES, and EAGaAs were taken to be 0.7 V, 0.241 eV, and 1.06.10 -12 F/cm2[48],respectively, in the calculations. The n-Al 0.3Ga07As layer parameters for the two HRGCCDruns, A07 and A08 described in this work, are summarized in Table II. The Schottky-barrier height was determined to be 0.85 volts for the A07 devices and 0.92 volts for theA08 devices by using the Richardson-Dushman equation[49,50] for charge transport acrossa Schottky-barrier junction and neglecting series and contact resistances.(9)q 	 2eAlcaAs17Process Run Layer Thickness (A) Doping Density (cm -3)A08 1100 2 • 1017A07 800 4 • 1017Table II: The n-A10.3GacoAs layer parameters for the HRGCCDs.Delagebeaudeuf and Linh modelled the transport characteristics of an AlGaAs/GaAsheterojunction[45]. Their model assumed that all of the donor atoms in the doped A1GaAslayer were ionized and free electrons did not exist in the doped AlGaAs layer. Lee etal.[51] showed that these assumptions are invalid. They produced a model of anAlGaAs/GaAs heterojunction which took into account the incomplete ionization of electronsin the doped AlGaAs layer and the existence of free electrons in the doped AlGaAs layer.However, in their approach the carrier density in equation (8) was linearized with respectto the Fermi level energy. Their model does not accurately predict the experimentallyobserved capacitance-voltage characteristics of a Schottky-barrier diode when the appliedbias approaches zero[52,53]. Eskandarian[54] developed a mixed quantum mechanical andclassical model of the transport characteristics of an AlGaAs/GaAs heterojunction whichmodels the experimentally observed capacitance-voltage characteristics of a Schottky-barrierdiode reasonably well over a wide range of applied biasses. This model couples thequantum mechanical model of the AlGaAs/GaAs interface developed by Stern et al.[44] toa solution of Poisson's equation in the A1GaAs layers. Eskandarian's model is used in thiswork to determine the density of electrons in a HRGCCD as a function of the bias appliedto a Schottky-barrier electrode.18The one-dimensional Poisson equation in the bulk AIGaAs isd2 (E c - E)_ 	 p 	 q(N; - n1) 	 (10)	dx 2 	e AlGaAs	 eAlGaAswhere p is the space charge density in the AIGaAs layers, Nd+ is the ionized donor densityin the doped AIGaAs layer, o f is the free electron density in the doped AIGaAs layer, andx refers to depth in the HRGCCD, as shown in Figure 2.2. The density of ionized donorsin AIGaAs is given by[54]	Nd Nd-(Ec -Er AEd)	 (11)1 +2e 	 kTthrough-the application of Fermi-Dirac statistics and assuming that there is only one donorlevel in Al0.3Ga0.7As, 0.006 eV below the conduction band edge[55]. This assumption is validfor an Al content in AIGaAs of less than 0.22[55]. For Al contents in excess of 0.22, asecond donor level exists between 0.05 and 0.100 eV below the conduction band edge[55].This second donor level was neglected in this work to simplify the solution of Poisson'sequation. In equation (11), E c is the conduction band energy referenced to the Fermi levelenergy El', and GlEd is the donor level energy referenced from the conduction band energy.A closed form approximation for o f is[56]nI 	 (E, -Et)1 +4e kT(12)19where Nc is the effective density of states in the conduction band of AlGaAs and is takento be 6.988.1017 cm -3[57].E fEvx 	 t	 X num	 0 — dFigure 2.2: The energy band diagram of a HRGCCD.20Equation (10) can be integrated analytically by multiplying both sides of the equation by2[d(k-E1)1dxand integrating with respect to x from the undoped AlGaAs/GaAs interface to a point ()in the doped AlGaAs layerd2(Ec -E,) d(E -E,)E.	2 f 	 dx = f  21) d(k 	Et-E)+ f 	 d(Ec-E1) . (14)dx	-d	 x2 	 AEC-Et./ AIGaAs	 E. £ AIGaAsHere, d is the thickness of the undoped AIGaAs spacer layer, 	 is the conduction bandenergy at x= E, and Ea is the conduction band energy at the doped/undoped AIGaAsinterfaceEIS = Ak-Efl -Since the doping density of the undoped A1GaAs layer is small in comparison to the dopedA1GaAs layer, the electric field at the undoped/doped AIGaAs interface is approximatelythe same as the electric field at the undoped AIGaAs/GaAs interface and is givenby[54]Ecs2 	 q nI 	 • o  d(E, Ef) — 	s _2Ak-Efl eAlGaAs	 e A1GaAs(16)Substituting equations (11) and (12) into equation (10) and integrating with respect to xyields the following equation(13)q nsd 	 (15)eAlGaAs21(EC-Ef- AEd) -(E,-E1) -[d(k-E1)}2 _2qNdkT 2 +e 	kThl +4Nc	4 +e 	kT in£A1GaAs (Ecs-Ef-AEd) N d 	-(E„-E1)2 +e 	kT 4 +e 	kT (17)qnseAlGaAsThe conduction band energy (E c-E1) in the bulk AIGaAs is found as a function of the2DEG carrier density (n s). When charge neutrality exists within the bulk AIGaAs (Nd+ =nf), the 2DEG carrier density is a maximum[54]. The maximum 2DEG carrier density (n m)is found by calculating the conduction band energy under charge neutrality conditions andsubstituting the conduction band energy into equation (8). An arbitrary value between 0and nm is chosen for n s. Equation (8) is used to find Efi which is substituted into equation(15) to find Em . The minimum conduction band energy (Emm) is found by setting the lefthand side of equation (17) to zero, substituting Em into equation (17) and solving for E c-Ef.Equation (17) is rewritten in terms of dx and numerically integrated to find the location ofthe minimum (Xmin) in the conduction band energy. Knowledge of the location and valueof the minimum in conduction band energy enables the conduction band energy (4b-Vs) atthe Schottky-barrier metal/doped AIGaAs interface (x=t) to be found by integratingequation (17) with respect to x from x=xmm to x=t and solving for E c-Ef at x=t.22The ionized donor density (nd) in the depletion region below a Schottky-barrier gateelectrode, is calculated by integrating Nd+ with respect to x from the edge of the depletionregion (x=xn,in) to the Schottky-barrier electrode/doped AIGaAs interface (x=t)nd = f N d+ dx	 (18)This equation was integrated numerically by substituting equations (11) and (17) intoequation (18). The solution of equation (18) establishes a relationship between n d and Vgwhich was used to find the theoretical capacitance of the Ti-Pt-Au Schottky-barrier diodesfabricated with the HRGCCDs. The program used to find the conduction band energy andthe ionized donor density as a function of the bias applied to a Schottky-barrier gateelectrode is given in Appendix A.The electrons in the 2DEG are screened from the gate electrode by the space chargein the region extending from x=0 to x=x„, i„ as a result of charge neutralityX minns f N d+ dx = 0	 (19)The charge in the GaAs buffer layer and in the semi-insulating GaAs substrate has beenneglected in equation (19). Consequently, the total gate capacitance (C,) of a Schottky-barrier diode is23andaQ -gCt(Vg) W aA a Vgwhere Q is the total gate charge of the diode and A is the gate area taken to be 10 -4 cm2 .The theoretical and measured capacitances of the Ti-Pt-Au Schottky-barrier diodesassociated with the A07 and A08 process runs are shown in Figure 2.3. The agreementbetween measurement and theory is reasonable for the A07 and A08 devices except for anapparent voltage displacement between the measured and the theoretical curves for the A08devices. The displacement is a result of a thinner active layer supplied by the vendor (1000A instead of 1100 A) which has caused the measured C-V profile to shift.(20)2416cexp — measured capacitancecth — theoretical capacitance1412-10 -Li.a)08-C 6-Q4-2-0—2.0 0.010cexp — measured capacitancecth — theoretical capacitancea)C 4-002-0U8-6-  0000 cexpOcth     O0  0I 0XA080—2.0•—1.5 	 —1.0 	 —0.5Applied Bias (V)00Figure 2.3: The measured and theoretical capacitances of Schottky-barrier diodes fromthe A07 and A08 process runs.252.3. Operation of the HRGCCDFor the HRGCCD to operate successfully the following sequence of events mustoccur: (1) charge injection, (2) charge transport, and (3) charge detection. An analogsignal applied to the input of the HRGCCD is transformed into a series of discrete chargepackets within the HRGCCD. The charge packets are subsequently transferred through theHRGCCD using a single phase clocking scheme applied to the transport electrodes 4)1A,431A, (1)A, and (1)2A. The charge packets arriving at the output of the HRGCCD aretransformed into analog voltages by the on-chip HEMTs.The input stage of the HRGCCD consists of an input ohmic contact (I/O) and twoSchottky-barrier control electrodes (G1 and G2). G1 is a.c. coupled to the 4)1 clock whichvaries from -5.0 to 0.0 V, and G2 is held constant at 0.0 V. A schematic representation ofthe input stage of the HRGCCD, and an illustration of the charge injection process ispresented in Figure 2.4. An analog input signal ranging from 0.0 to 0.3 V is applied to theI/O node of the HRGCCD. Charge is injected into the potential well formed underneaththe (1)1A electrode when the bias applied to the G1 electrode and the 431 clock is 0.0 V, asshown in Figure 2.4(b). When the 44 clock swings negatively, the charge under the 4)1Aelectrode is transferred into the potential well formed underneath the (1)2A electrode,creating a discrete charge packet in the first pixel of the HRGCCD, as displayed in Figure2.4(c). The magnitude of the charge packet injected into the transport region of theHRGCCD is a function of the analog input signal. The nominal voltages applied to the26nu.TOw-Acharge packet -input stage of the HRGCCD are listed in Table III, on page 31.G1 	 G2 	 01 	 01A 	 02 	 02A 	 01I/o 	 0 	 0 	 0 	 0 	 0 	 0 	 0V A 	 A V A V A V A 	 V Ai   Cermet(a)Undoped A1GaAs Spacern—A1GaAsGaAs Buffer A                    ( b )  charge transport                                                                                                                                                                                                                          Ow-                       distance	 Xdistance 	 XFigure 2.4: (a) The input stage of a HRGCCD. The surface potential distributionwhen the 1)1 clock is at: (b) 0.0 V, (c) -4.0 V.An illustration of the charge transport process is shown in Figure 2.5. The chargepackets are transferred from the input stage to the output stage of the HRGCCD by theapplication of a single phase clock, as shown in Figure 2.5(e). Initially, at time t=t o, acharge packet resides underneath the 4)2A electrode when the voltages applied to thetransport electrodes are such that 4)2A > 4)2 4)1A > 4)1. The discrete charge packetis transferred to the potential well formed underneath the 4)1A electrode, at time t=t1,271////1 	 1," A f77Z 	 [7.1 	 F7Z —2 Plll Cermet(a)(b)00Oci!)aoeis00t = t 10Za)a)ag 0O0CL(c)charge packet4)2 	 4) 2 A 	 4)1 	 4) 1 A 	 4)2 	 4) 2 A 	 4)1O O O O O On—A1GaAsGaAs BufferUndoped A1GaASpacer Layerdistancet = t odistance x(d ) t	 t 2distanceV2 A4)24) 1 A4)1t0 	 1 	 t2Figure 2.5: (a) A portion of the transport region of a HRGCCD. The surface potentialdistribution at time: (b) t=to, (c) t=ti, and (d) t=t2. (e) The voltages applied to thetransport electrodes.t28when the voltages applied to the transport electrodes change from their initial values to(131A > (I)1 432A > (132. The charge packet is transferred to the next cI32A electrode, attime t=t2, when the voltages applied to the transport electrodes return to their initial values.The nominal voltages applied to the transport electrodes of the HRGCCDs are presentedin Table III, on page 31.The output stage of the HRGCCD consists of a Schottky-barrier control electrodeG3, an output ohmic contact 0/P, a reset HEMT, and a HEMT amplifier as shown inFigure 2.6. The 0/P node is connected to the source contact of a reset HEMT and theinput gate of a HEMT amplifier. The 0/P node is precharged to the drain voltage of thereset HEMT by applying a positive voltage pulse to the reset gate (R/G) on the rising edgeof the 44 clock. The pulse turns the reset HEMT on, causing the 0/P node to precharge.The reset HEMT is turned off when the reset gate returns to its minimum value, causingthe 0/P node to float at its precharged value. When a charge packet arrives at the final(1)2A electrode of the HRGCCD, it passes through the potential well formed underneaththe G3 control electrode on the negative transition of the 4)1 clock. The electrons in thecharge packet accumulate on the parasitic capacitance (CoR) on the 0/P node causing anegative voltage displacement to occur at the output node (B/O) of the HEMT amplifier.The voltage at the B/O node contains feedthrough components of the reset gate pulse andthe clock, as displayed in Figure 2.6. A summary of the voltages applied to the output stageof the HRGCCD is presented in Table III.29B/0Active Region charge packetHRGCCDclockR/Greset pulsefeedthroughB/OR/G R/D41A 	 112 	 02A 	 G3 	 0/PVACerinetC0/PB/SSemi—insulating GaAs substrate0 B/DFigure 2.6: A diagram of the output stage of a HRGCCD, and the on-chip HEMTs.30Applied Signals Voltage Level(V)I/O 0.0 to 0.3G1 -5.0 to 0.0G2 0.04)1 -5.0 to 0.04)1A -4.0 to 1.04)2 -2.04)2A 0.0G3 0.0R/D 5.0R/G 0.0 to 3.0B/D 12.0B/S 0.0Table III: The signals applied to the HRGCCD and theircorresponding voltage levels.313. DEVICE FABRICATIONThe fabrication of the HRGCCD required six mask levels employing a 1.0 microndesign rule. The masks provided the patterns for the fabrication of the ohmic contacts, theproton isolation implants, the cermet deposition, the gate and transport electrodemetallizations, the interconnect vias, and the second level metallization. Conventional 405nm contact photolithography was used to transfer the mask patterns to the photoresist onthe wafer. An overview of the HRGCCD fabrication procedure is presented in Figure 3.1.3.1. Ohmic Contact FormationThe formation of the ohmic contacts, to the HRGCCD and the supporting HEMTcircuit, was the first step in the HRGCCD fabrication procedure. The wafer was initiallycleaned and degreased using a series of solvent solutions which included acetone,trichloroethylene and isopropanol. A nominal 1.1 thick film of Hoechst CelaneseAZ4110, positive photoresist, was patterned on the wafer using the ohmic contact mask.The ohmic contact metallization was accomplished by depositing a 550 A thick layer of Au-Ge (12 % wt. Ge) using thermal evaporation, and sequentially depositing a 100 A thicklayer of Ni, and a 1500 A thick layer of Au using e-beam evaporation at a pressure of 840Torr. The unwanted metal was removed using the photoresist lift-off method[58] in acetonewith the aid of ultrasonic agitation. Ohmic contacts were formed by alloying the deposited32Ohmic ContactFormation semi—insulating substrate• ••Opp.• io •Legend:	 a	active layersbuffer layersemi—insulating substrate	 t:	— Ohmic Metal— Isolation— Cermet Film— Gate Metal— Dielectric— 2 nd. level metalProton IsolationImplantsactive layers	t t	buffer layer	tt	• ••.4'.,.•••• I •	tt	ttactive layersbuffer layersemi—insulating substrate	t 	Cermet Deposition4Ia WA :4 gonolaactive layersbuffer layersemi—insulating substrateGate MetalDepositionDielectricInterconnect Vias2 nd. LevelMetallizationactive layersbuffer layersemi—insulating substrate	tt	• ••buffer layersemi—insulating substratemetals to the doped GaAs and AlGaAs layers following the photoresist lift-off procedure.The alloy was performed at 395 °C for 10 seconds with a Heatpulse 2210 rapid thermalanneal (RTA) system. The doped GaAs cap layer was removed by the developer solution,AZ400K:H20 (1:4 vol.). The etch rate of GaAs exposed to AZ400K:H20 was found to be70 -± 20 A per minute.3.2. Device IsolationMultiple energy proton isolation implants were used to isolate the active region ofthe HRGCCD[59]. Ion implantation damages the crystal lattice, creating electron trappingcentres which renders the damaged regions insulating[59]. Isolation using mesa etching wasnot employed because the surface profile of the wafer would be non-planar, makingsubsequent contact photolithography difficult. A nominal 6.2 thick film of HoechstCelanese AZ4620, positive photoresist, was used to protect the active regions of the deviceduring the implantation process. A postbake was performed after the photoresist wasdeveloped to further harden the photoresist, providing extra protection of the active regionsduring the implantation process. Two sequential proton implants of 1) 35 keV and 2) 200keV, at fluences of 1.10 13 cm -2 were used to isolate the active region of the HRGCCD. Thephotoresist was stripped off in 1-methyl-2-pyrrolidone (1M2P), with the aid of ultrasonicagitation, after the isolation implants were completed.3433. Cermet DepositionA nominal 2.1 pm thick film of Hoechst Celanese AZ4210, positive photoresist, waspatterned on the wafer using the cermet mask. The transport region of the HRGCCDs wascovered with a nominal 2000 A Cr:SiO (45:55 at. wt. %) cermet film. A 500 A Ti:W (30:70at. wt. %) layer was placed on top of the cermet to provide adhesion and to form an ohmiccontact to the gate metal electrodes. The Cr:SiO and Ti:W films were r.f. magnetronsputtered from four inch composite targets at a pressure of 5 mTorr. The unwanted cermetwas removed using the photoresist lift-off method in acetone with the aid of ultrasonicagitation.A chlorobenzene-aided photoresist process was employed to achieve an overhangprofile in the AZ4210 photoresist[60]. This process was utilized to reduce the formationof 'wings' in the cermet film The term 'wings' usually refers to material protruding fromthe edges of a deposited film, as shown in Figure 3.2(a). In the unaided photoresist lift-offprocess, a cermet film deposited on photoresist is typically continuous, because thedeposition coats the photoresist sidewalls. During the lift-off process, the cermet filmcoating the sidewalls breaks in an irregular manner resulting in the formation of wings.Subsequent metallizations which are required to step over the irregular cermet edge profilemay fail, causing the device to be inoperable. Figure 3.3 illustrates the failure of the metalelectrodes to step over a cermet film which has wings. This failure can be avoided bysoaking the photoresist covered wafer in chlorobenzene, which causes the removal of low35a)Legend:Wings— Gate Metal— Cermet— AZ4210 ResistUndercut resist(b )"/-7 JA11112111111 	 AFigure 3.2: Deposition of the cermet and gate metal using, (a) the unaided, and (b) thechlorobenzene-aided photoresist lift-off process.molecular weight resin and residual solvents from the upper layers of the photoresist[60].The action of the developer on these upper layers is retarded, resulting in the formation ofan undercut sidewall profile in the photoresist[60], as shown in Figure 3.2(b). In thechlorobenzene-aided photoresist process, the deposited cermet film will typically bediscontinuous because the undercut photoresist sidewall profile shadows the deposition.3618 iiirons4.84 Kx 8.85 Ku 8/18/92 11:375.675 Microns 	 pCURRAN 111E7 NanonetricsX: -8.289 nn R: 368.8 degY: -8.762 nn T: 45.8 degFigure 3.3: A photograph displaying gate metal electrodes placed on top of cermet filmwhich contains wings.A chlorobenzene-aided photoresist process was developed for the AZ4210photoresist. It was found, through experimentation, that a 20 minute, room temperature,chlorobenzene soak following a 30 minute, 70° C softbake produced a suitable overhangprofile for the AZ4210 photoresist. The sidewall profiles of AZ4210 photoresist employingthe unaided and chlorobenzene-aided photoresist lift-off processes are displayed in Figure3.4. The photoresist islands are 4 gm wide and the overhang of the chlorobenzene-aidedphotoresist is between 0.25 and 0.5 Lim. Interference fringes can be seen in the sidewall3718 Nicrons •■■■■•■1•■■•--4.38 Kx 8.85 Ku 8/18/92 . 14:325.675 Microns 	 pDURAN IIIEZ Hanonetricsprofile of the unaided photoresist, as displayed in Figure 3.4(a).a)...18 Microns5.33 Kx 8.85 Ku 8/21/92 9:195.675 Microns	 p	 .CURRAN IIIEZ Hanonetrics(b )Figure 3.4: A photograph of the sidewall profile of AZ4210, 2.1 Lim photoresistemploying, (a) the unaided, and (b) the chlorobenzene-aided photoresist lift-offprocess.38CURRAN IIIEZ tianonetricsThe interference fringes are standing waves patterns in the photoresist caused bydiffraction and reflection of the imaging beam used to transfer the mask pattern to thephotoresist[61]. Standing wave patterns also cause notches to form in the edges of thephotoresist, as displayed in Figure 3.5. Interference fringes and notches are less pronouncedin the chlorobenzene-aided photoresist process because the upper layers of the photoresisthave been modified[60].Figure 3.5: A photograph of the sidewall profile of overexposed AZ4210, 2.1photoresist.The optimum exposure and develop times of the photoresist were different for theunaided and the chlorobenzene-aided photoresist processes, due to the effect ofchlorobenzene on the upper layers of photoresist. The optimum exposure and developtimes were found, through experimentation, to be 25 seconds and 130 seconds, respectively,for an imaging wavelength of 405 nm and a power density of 5.0 mW/cm 2 .393.4. Gate Metal DepositionThe Schottky-barrier gates and transport electrodes were deposited after the cermetislands were formed. A nominal 1.1 p,m thick film of AZ4110 was patterned on the waferusing the gate metal mask. The gate metal deposition was accomplished by sequentially e-beam evaporating a nominal 500 A thick layer of Ti, a 100 A thick layer of Pt and a 3000A thick layer of Au at a pressure of 8.10 -6 Torr. The unwanted metal was removed usingthe photoresist lift-off method in 1M2P with the aid of ultrasonic agitation. After the lift-offprocess, a CF4:02 reactive ion etch (RIE) was used to remove the Ti:W in between thetransport electrodes.3.5. Interlayer Dielectric and Via FormationA 1µm thick film of Du Pont PYRALIN PI2556 polyimide was used as theinterlayer dielectric[62]. The polyimide was imidized in a temperature controlled convectionoven. The oven temperature was initially held at 100°C for 15 minutes, it was then rampedup to and held at 250 °C for 90 minutes, and subsequently ramped down to a temperatureof less than 100°C over a period of an hour. The 250°C maximum temperature of theoven, in this process, was below the 360°C eutectic temperature of the ohmic contacts[63],and the 500°C anneal temperature of the proton isolation implants[64].40The interconnect vias between the first and second level metallization were formedby using a multilevel patterning process. A thin, 500 A thick layer of Ti was deposited onthe polyimide using e-beam evaporation at a pressure of 8406 Torr. A 1.1 gm thickphotoresist film was subsequently patterned on the Ti layer. The vias were formed by usinga three-step reactive ion etch process shown in Figure 3.6.A CF4:02 etch was used to remove the Ti in the photoresist openings, transferringthe via mask in the photoresist to the underlying Ti. The polyimide in the openings of theTi layer and the photoresist was etched with 0 2. Finally, a CF4:02 etch was performed toremove the remaining Ti, completing the formation of the interconnect vias in thepolyimide. Figure 3.7 shows a photograph of completed interconnect vias.A conventional plasma etch chamber, a Technics Planar Etch plasma etching system,was originally used at TRIUMF to form interconnect vias for earlier devices. It was foundthat greater etch anisotropy was required to minimize lateral etching of the 512, 4 gmsquare vias needed for the HRGCCDs. To accomplish this a reactive ion etching processwas developed using a 13.56 MHz Plasma-Therm 2406 reactive ion etch system. Reactiveion etching offers substantial etch anisotropy since the etch proceeds more rapidly in thedirection of the applied electric field[65]. Experiments were done to determine the effectof the flow rates of CF4 and 02, the power density, the chamber pressure, duration of theetch, temperature of the substrate holder, and ratios of CF4 to 02 on the different RIEs.A summary of the RIE parameters used to fabricate the HRGCCDs is given in Table IV.41Ti removal etchCompletedvia formationVACF4 /0 2 RIE=ZZ /7///7/// =Z2Z2ZVACF4 	 2 RIETi patterning etchV. 44 	 /A 	 ■, 	 V A0 2 RIEPolyimide anda)Legend: 	 (/)(/)(/)a)- P12556 Polyimide 	 00.4photoresist etch - First Level Metal 	 4:1•■-•a)I A I 	 A' iiuiiy Arr- TitaniumV A 	 VA 	 rA 	 V A 0- AZ4110 Photoresist1 Micron18.81 Kx	 1.08 K11 12/85/98 14:831.664 Microns	 x 	 .CERAM IIIEZ ManonetricsX:-14.878 nn R: 293.8 degY: 9.422 nn T: 45.8 degFigure 3.7: A photograph of completed interconnect vias. The vias are approximately4 pm square separated by a gap approximately 4 p.m long.Plasma Parameters Settingspower density 400 mW/cm 2temperature 30°CCF4 flow rate (CF4:02) 100 sccm02 flow rate (CF4:02) 10 sccm02 flow rate (02) 100 seempressure (CF4:02) 150 mTorrpressure (02) 50 mTorrbase pressure < 2 mTorrTable IV: The settings used for the CF 4:02 and 02 reactive ion etches.433.6. Second Level MetallizationThe second level metallization was the final step in the HRGCCD fabricationprocedure. A 2.1 p.m thick film of AZ4210 photoresist was patterned on the wafer usingthe second level metal mask. The second level metallization was formed by sequentiallydepositing a nominal 1000 A thick layer of Ti and a nominal 5000 A thick layer of Au usinge-beam evaporation at a pressure of 840' Torr. The Ti layer was used to provide adhesionbetween the first and second level layers of Au. The unwanted metal was removed usingthe photoresist lift-off method in acetone with the aid of ultrasonic agitation.Photographs of a completed HRGCCD fabricated at TRIUMF are displayed inFigures 3.8, 3.9, 3.10, and 3.11. A photograph of the entire HRGCCD is displayed inFigure 3.8. The active region of the HRGCCD is 50 vm wide by 2584 p.m long. The entireHRGCCD die is 950 pm by 3340 pm. A photograph of the input section of the HRGCCDis displayed in Figure 3.9. The I/O contact pad is 20 vm long, the G1 electrode is 2 pmlong, the G2 electrode is 10 pm long and the (1)1 electrode is 2 p.m long. The separationbetween I/O and G1 is 2 pm. The G1 to G2 and G2 to 431 gaps are both 1 pan long. Aportion of the transport region of a HRGCCD is displayed in Figure 3.10. The transportelectrodes are 2 pm long and approximately 100 vm wide. The interelectrode gaps are 3p.m long. The output stage of a HRGCCD is displayed in Figure 3.11. The G3 electrodeis 2 p.m long. All of the on-chip HEMTs employ 2 p.m technology. The detailed HRGCCDfabrication procedure is given in Appendix B.44Figure 3.8: A photograph of the entire HRGCCD. The bonding pads are 96square.Figure 3.9: A photograph of the input section of the HRGCCD.45Figure 3.10: A photograph of a portion of the transport region of a HRGCCD.Figure 3.11: A photograph of the output section of a HRGCCD.464. DEVICE CHARACTERIZATIONThe HRGCCD die from the A07 and A08 process runs were characterized usingautomated d.c. and a.c. tests. The operation of a HRGCCD is demonstrated at a frequencyof 4.33 MHz. Insertion loss measurements were performed to find the CTE, the dynamicrange, and the linearity of the HRGCCD response at an operating frequency of 50 MHz.The HRGCCD die were d.c. and a.c. probed on an Electroglass 1304X, automatedprobe station to find the functional devices. These devices were then bonded in a 0.45 inchsquare, 28 pin, 28LCC package, as shown in_ Appendix C, and prepared for furtherevaluation.A qualitative demonstration of a HRGCCD operating at 4.33 MHz, is shown inFigures 4.1 and 4.2. The input (upper) and output waveforms (lower) are displayed inFigure 4.1. In 128 clock cycles, the charge packet is transferred from the input to theoutput stage of the HRGCCD resulting in the 30 pS delay between the input and outputwaveforms. The output waveform shows little dispersion indicating near unity CTE. Adetailed illustration of the HRGCCD output waveform is shown in Figure 4.2. Thefeedthrough of the reset and clock pulses are evident in the output waveform.47111.010m4IIINkilINNIUMMINIIIIIIIiIIIIIIN1141111•11111111111oxte'v 	 I Figure 4.1: A photograph of the input and output waveforms of a HRGCCD operatedat 4.33 MHz.Figure 4.2: A photograph of the output waveform of a HRGCCD operated at 4.33MHz. There are 100 nS per division on the horizontal scale and 200 mV per divisionon the vertical scale.48The CTE of the HRGCCDs fabricated at TRIUMF was determined using theinsertion loss technique[66,67]. A Hewlett Packard HP-8753A network analyzer and a HP-85046 s-parameter test set were used for these measurements. The CTE was calculated byfitting the equation[66],B = 20LOG[Boexp -Nt (1 	 -coif).fc(21) to the measured insertion loss. A is the insertion loss in decibels, B o is a normalizationfactor, N, is the number of single electrode transfers through the HRGCCD (256 for the128 pixel HRGCCD in single phase operation), n is the charge transfer efficiency, f is theinput signal frequency, and fc is the HRGCCD clock frequency. The measurements wereperformed using an input signal ranging from 300 kHz to 25 MHz and a HRGCCD clockfrequency of 50 MHz. The calculated CTE of five HRGCCDs from the A07 and A08 runsare listed in Table V.Process RunA07 0.998A07 0.991A07 0.999A08 0.995A08 0.990Table V: The charge transfer efficiency of HRGCCDs from runs A07 and A08.49Insertion Loss Measurementsefficiency = 0.999251 	 I 	 t 	 I5 	 10 	 15 	 20Input Signal Frequency (MHz)Figure 4.3 displays the measured and theoretically calculated insertion loss, for theHRGCCD from the A07 process run which exhibited a CTE of approximately 0.999. TheCTE of this HRGCCD is in agreement with the results previously obtained by Song etal. [26].Figure 4.3: The measured and theoretically calculated frequency response of aHRGCCD operated at 50 MHz.The measured dynamic range of the HRGCCD from process run A07 that exhibiteda CTE of 0.999, is shown in Figure 4.4. This device exhibited a dynamic range in excess of50 dB with an essentially linear response over a 40 dB input signal range, as shown inFigure 4.5. The observed deviation from linearity is attributed to the nonlinear relationshipbetween the injected signal charge and the input signal amplitude. This is caused by thevoltage dependence of the input capacitance between the control electrodes (G1 and G2)501 	 I 	 I 	 I5 	 10 	 15 	 20Input Signal Frequency (MHz)0 25and the input ohmic contact (1/0){68].Figure 4.4: The frequency response of a HRGCCD operated at 50 MHz with the inputsignal attenuated in steps of 10 dB.10(1)- 10Eo —30 -cr,—40—50 -0—60 I 	 1 	 1 	 I—50 	 —40 	 —30 	 —20 	 —10	0Input Signal Attenuation (dB)Figure 4.5: The linearity of the HRGCCD response for a 12.5 MHz input signal.O515. SUMMARY AND PROSPECTS FOR FUTURE WORKThe design, fabrication and evaluation of a 128 pixel, single phase HRGCCD wasdescribed in this work, and is summarized in section 5.1. Proposals for the continuingdevelopment of these devices are given in section 5.2.5.1. SummaryThe design and operation of a 128 pixel, single phase HRGCCD was explained inChapter 2. A quantum mechanical model of the triangular potential well formed at anundoped AlGaAs/GaAs interface was developed and coupled to a solution of Poisson'sequation in the bulk AlGaAs to determine the carrier densities in a HRGCCD as a functionof the active layer parameters and the applied bias. The carrier densities in the HRGCCDwere used to calculate the capacitance-voltage profile of a Schottky-barrier diode fabricatedalong with the HRGCCD. The theoretical capacitance-voltage profile was compared withmeasured capacitance-voltage profiles of Schottky-barrier diodes fabricated with theHRGCCDs. The agreement between the measured and theoretically computed capacitance-voltage profiles are reasonable. The difference between measurement and theory for theA08 devices is caused by variations in the active layer thickness of the wafers supplied bythe vendor.52The charge injection, transport, and detection processes in a HRGCCD were alsodescribed in Chapter 2. An analog input signal, applied to the input ohmic contact of theHRGCCD, causes a discrete charge packet to form within the input stage of the HRGCCD.A single phase clock, applied to the transport electrodes of the HRGCCD, is used totransfer the charge packet from the input stage to the output stage of the HRGCCD. Thecharge packet is sensed at the output stage of the HRGCCD by a HEMT amplifier, whichconverts the charge into an analog voltage signal.The fabrication of the HRGCCD was presented in Chapter 3. Six mask levels,employing a 1 p.m design rule, were used in the fabrication procedure. The mask patternswere transferred to photoresist placed on the wafer with conventional 405 nm contactphotolithography. The six mask steps in the fabrication procedure consist of; the formationof Au/Ge-Ni-Au ohmic contacts, the proton isolation implants, the Cr:SiO cermet filmdeposition, the Ti-Pt-Au gate metal deposition, the interlayer dielectric and via formation,and the Ti-Au second level metallization. The development of a chlorobenzene-aidedphotoresist process for Hoechst Celanese AZ4210 photoresist, and a three-step reactive ionetch process to form interconnect vias were also described in this chapter. Thechlorobenzene-aided photoresist process was developed to reduce the formation of wingsin the cermet film. The reactive ion etch process was developed to obtain an anisotropicand uniform etch across the wafer, enabling the interconnect vias to be precisely formed.53The fabricated HRGCCDs were characterized in Chapter 4. Measurements wereperformed on packaged HRGCCDs to find the CTE, the dynamic range, and the linearityof the response of the HRGCCDs operated at 50 MHz. The CTE was in excess of 0.99 forall of the devices tested, the dynamic range was in excess of 50 dB, and a linear responseover a 40 dB input signal range was obtained.5.2. Considerations for Future WorkImprovements to the HRGCCDs considered in this work can be obtained by usingdifferent active layer profiles and materials. The layer structure of the HRGCCD can bemodified to reduce the number of defects in the wafer and to increase the operating speedand dynamic range of the HRGCCDs. Defects in the wafers can be reduced byincorporating a superlattice of alternating AlGaAs and GaAs layers between the substrateand the GaAs buffer layer[69]. Different layer profiles and different materials can be usedto increase the operating speed and the dynamic range of HRGCCDs. The carrier densitiesand the mobility of the HRGCCD can be enhanced by planar doping[17,70] or deltadoping[71,72] the doped AlGaAs layer, or using indium phosphide based materials. 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Tessmer, K-H.G. Duh, P. Ho, M-Y. Kao, P.M. Smith, J.M. Ballingall,S-M. Liu and A.A. Jarba, W-Band Low-Noise InAIAs/InGaAs Lattice -Matched HEMT's,IEEE Electron Device Letters, vol.11, #1, Jan. 1990, p.59-62.62APPENDIX A: Program Listing for the Carrier Density CalculationsThis is the MATHCAD, version 3.1 for Windows, file used to calculate thecarrier densities in the HRGCCDs as a function of the bias applied to aSchottky-barrier diode. The carrier densities were found by using a quantummechanical model of the triangular potential well at the AIGaAs/GaAs interfacecoupled to a solution of Poisson's equation in the bulk AIGaAs.All references to equations in this file are directed to the work done byEskandarian[54].1. Defining the constants:doping density 	 Nd := 2.1017 	cmA(-3)-doped AIGaAs layer thickness 	 d =1100- 10-8 	cmundoped AIGaAs layer thickness 	 t :=40.10-8 . 	 cmSchottky-barrier height 	 4* :=.92 	 Vpermittivity of the AIGaAs 	 E :=-- 1.06.10-12 	 F/cmconduction band discontinuity 	 AEC := 0.28 	 eVdonor level energy 	 AEd : = 0.006 	 eVelectronic charge 	 q := 1.602.10-19 	Cthermal voltage, kT/q 	 Vt := 0.0259 	 eVeffective density of states 	 Nc := 6.988-10 17 	 cm^(-3)two-dimensional density of states 	 D := 3.24.1013 	eVA(-1)*cm^(-2)Shubnikov-de Haas constant 	 yo := 1.16. 10-9 	eV*cm^(4/3)Shubnikov-de Haas constant 	 71 := 1.49.10-9 	eVwcmA(4/3)632. Defining the variables:All energies are referenced to the Fermi level unless otherwise stated.EO 	 the first energy level in the 2DEG referenced to the bottom ofthe triangular potential well.El 	 the second energy level in the 2DEG referenced to the bottomof the triangular potential well.EC 	 the conduction band energy.ECg 	 the conduction band energy at the Schottky metal/AIGaAsinterface.ECt, Eg, 	 dummy variables used to find ECg.ECgateECi 	 the conduction band energy at the GaAs/AIGaAs interfacereferenced to the bottom of the triangular potential well.ECm 	 the minimum conduction band energy in the bulk AIGaAs.ECml, ECm2, dummy variables used to find ECm.Em, ECrootECs 	 the conduction band energy at the doped/undoped AlGaAsinterface.Es 	 a dummy variable used to find ECs.ECmax 	 the conduction band energy at the AIGaAs/GaAs interfacewhen the 2DEG carrier density is a maximum.ECmaxO 	 the conduction band energy at the AIGaAs/GaAs interface,referenced to the bottom of the traingular potential well,when the 2DEG carrier density is a maximum.F 	 a dummy variable for integration.Qt	the charge within the bulk AIGaAs.ns 	 the carrier density in the 2DEG.nb	the carrier density in the bulk AIGaAs.xm 	 the distance between the minimum conduction band energyin the bulk AIGaAs and the doped/undoped AIGaAs interface.p	 the space charge density in the bulk AIGaAs.a dummy variable for integration.643. Determining the maximum 2DEG carrier density:The maximum 2DEG carrier density (nm) is found by assuming that theminimum conduction band energy (ECm) is equal to the conduction bandenergy of the bulk AIGaAs. The conduction band energy of the bulk AIGaAsis obtained by assuming that charge neutrality exists within the bulk AIGaAs.Therefore, Poisson's equation in the bulk AIGaAs can be written as;p = 0 = Nd+ - nfwhere Nd+ is the ionized donor density and of is the free electron density.By solving Poisson's equation for ECmax the following expression is obtained:ECmax :=Vt.ln    0.5• —Ne•exp lAEd\	.NT+ (0.25-	 - (0.25- Nc )Nd	 Vt /	 Nd	 Nd    ECmax = 0.0417072	 eVThe conduction band energy is assumed to be constant in the bulk AIGaAstherefore, the derivative of the conduction band energy with respect to the depthin the bulk AIGaAs is zero (d(EC)/dx = 0) and the left hand side of equation (4) iszero. The maximum carrier density in the AIGaAs is found by numericallysolving equations (4) and (5) simultaneously.a := 2.E.Nd. Vtb := 4. NcNdc :=1n (2+ exp / ECmax- AEd)) /4+ expVtLECmax\ ) b1 Vt   An initial guess of the carrier density in the 2DEG (ns) and the conductionband energy (ECmaxO) is required to solve equations (4) and (5) simultaneously.ns 1.10 11 crn^-2	 ECmaxO : _ .2 eVNote: the variable ECmax is not the same as ECmaxO.GivenIn	 1+ exp2 ,ECmaxO- yo.ns 3+ exp2ECmaxO- y i .ns 3 ns =0Vt Vt Vt.D65                                 ECmax0 + ns- -t - AEC              2 + exp AEC - AEd - ECmax0 - q.ns-   4 + exp               vt    Vt                                            - ns=0nm' = Find( ns ,ECmax0)\ECmnm = 5.49914583.10 11 cm^-24. Calculating the conduction band energy (Ecs) at the undoped/dopedAIGaAs interface for a given 2DEG carrier density (ns)Ecs is found by subtracting the conduction band energy at the GaAs/AIGaAsinterface (ECi) and the linear drop in the conduction band energy acrossthe undoped AIGaAs layer (q*net/E) from the conduction band discontinuity.Before Ecs can be found ECi must be found as a function of ns. This is doneby calculating E0 and El as a function of ns and then solving equation (5)numerically to find ECi.maxi = 100i .. maxiECO := .5 eVGivenIn 1 + exp + exp 'ECO El ns =0ECO- E0)Vt	)Vt )) Vt- D11ECM(E0 , El , ns) = Find(ECO)ns. := nm. tanh 3• 	maxi2E0 i : = yo - (nsi) 32El i : = y i - (ns i) 366ECi i := ECf0 (E0 i , El i , ns i)E 	 qCs. :=DEC - ECi.5. Calculating the minimum conduction band energy (ECm) in the bulk AIGaAs.ECm is calculated for a given ns by setting the left hand side of equation (4)to zero, and then numerically solving the resultant equation for ECm.The solution of equation (4) produces two roots ECm1 and ECm2.Finding the first root of equation (4).rl 2. q.Nd.—VtEC = .5 	 eVGivenr1+ i—.ine2 2 + exp S EC - Ed) \ (4 + exp 1 - EC \ bVt	 Vt ro-o            ECminl(e2, FO) := Find(EC)e2i -q•ns i 2     ECs i - AEd))4 + expVtECSi bVtro i .= 2 + exp ECml i 	(e2i,F0)Finding the second root of equation (4).EC :=.01 	 eV67Given /2 + exp /EC - AEd\	 + expVt FO/-EC b F 11 +	 lne2 Vt „      -o      EC - ECrootlECmin2(e2, FO,ECrootl ) :=Find(EC)ECm2i = ECmin2(e2 i  ro i , ECml i)Choosing the correct root.ECmi := max1 ECml iECm2t	 i6. Calculating the distance (xm) from the point in the bulk AlGaAs where theconduction band energy is a minimum to the undoped/doped AIGaAs interface.Equation (4) is integrated from ECs to ECm to find xm.F( EC , e2, FO) :=1 + Fl -lne2 (2 + exp (EC- AEd\ \ /4 exp /- EC) bVt	 /	 Vt ro    ECs. ECm .I1 2- T dT    0 ,\IF[ (ECm i + T2) , e2i , rod7. Calculating the applied bias (Vg) for a given ns:Equation (4) is used to find the conduction band energy (ECg) at theSchottky metal/AIGaAs interface.ECt := 268GivenVF[ (ECm + T2) , e2, TO• 0ECgate(ECm, e2, T0, d, xm) : = Find(ECt)ECgi = ECgate (ECm i , e2i , TO i , d, xmi)Vg is found from the relationship:Vgi : = - ECgi8. Calculating the ionized donor density (nb) caused by the bias (Vg) appliedto a Schottky-barrier diode.nb is calculated by integrating the space charge density (p) in the doped AIGaAsfrom the edge of the depletion region to the AIGaAs/metal interface.p(EC ) = q. exp /EC - AEd \Nd. 	 Vt2 + exp EC - AEdVt     VEg - Em2. t• p(Em + T2)    Che22-F (Em + t2 , e22, TOO)Qt(Em, Eg, e22, roo) :=     • 0   nb. := —1 . Qt(ECm i , ECgi , e2i ,T0 i)q4ECt - ECm2.- ( d - xm). )12=069APPENDIX B: The HRGCCD Fabrication ProcedureOhmic Contact Formation1. General Clean-up3 min. in warm acetone, immersed in an ultrasonic(U/S) bath3 min. in hot clean trichloroethylene3 min in hot clean acetone3 min. in hot clean iso-propanoldry wafer with N22. Photolithographydispense AZ4110, 1.1 pm, positive photoresist, onto waferspin wafer at 4000 rpm for 20 sec.softbake wafer at 90°C for 30 min.allow wafer to cool for 3 minalign wafer with 'ohmic contact' maskexpose wafer with 405 nm, 5 mW/cm 2 light for 16 sec.spray develop photoresist using AZ400K:H 20 (1:4), for 90 sec.rinse wafer in deionized H2O for 1 min3. Evaporationthermal evaporate:550 A of Au-Ge (12% weight Ge)at a pressure of 840 6 Torrsequentially e-beam evaporate:200 A of Ni1500 A of Auat a pressure of 8406 Torr4. Photoresist Lift-off and Cleaning10 min. in hot lift-off acetone3 min. in hot, new lift-off acetone immersed in an U/S bath3 min. in warm acetone immersed in an U/S bath3 min. in hot clean trichloroethylene3 min. in hot clean acetone3 min. in hot clean iso-propanoldry wafer with N25. Inspect pre-RTA current voltage characteristics of the contacts6. Rapid Thermal Anneal10 sec. RTA at 395°C in a N2 ambient7. Inspect current-voltage characteristics of the contactsDevice Isolation1. General Clean-up3 min. in warm acetone immersed in an U/S bath3 min. in hot clean trichloroethylene3 min. in hot clean acetone3 min. in hot clean iso-propanoldry wafer with N22. Photolithographydispense AZ4620, 6.2 gm, positive photoresist, onto waferspin wafer at 4000 rpm for 20 sec.softbake wafer at 90°C for 30 min.allow wafer to cool for 3 min.align wafer with 'isolation' maskexpose wafer with 405 nm, 5 mW/cm2 light for 60 sec.spray develop photoresist using AZ400K:H 20 (1:4), for 90 sec.rinse wafer in deionized H2O for 1 min.postbake wafer at 120°C for 15 min.allow wafer to cool for a minimum of 3 min713. Isolation Implantsimplant H+ atoms at 200 keV, 1.10 13 cm -2implant H+ atoms at 35 keV, 1.10 13 cm-24. Photoresist stripping and cleaning15 min. in hot lift-off 1-methyl 2-pyrrolidone(1M2P)5 min. in hot, new lift-off 1M2P immersed in an U/S bath5 min in hot lift-off acetone immersed in an U/S bath3 min in warm acetone immersed in an U/S bath3 min. in hot clean trichloroethylene3 min. in hot clean acetone3 min. in hot clean iso-propanoldry wafer with N25. Inspect current-voltage characteristics of isolated andunisolated regionsCermet Deposition1. General Clean-up3 min. in warm acetone immersed in an U/S bath3 min. in hot clean trichloroethylene3 min. in hot clean acetone3 min. in hot clean iso-propanoldry wafer with N22. Photolithographydispense AZ4210, 2.1 tim, positive photoresist, onto waferspin wafer at 4000 rpm for 20 sec.softbake wafer at 70°C for 30 min.allow wafer to cool for 3 min.soak wafer in chlorobenzene for 20 min.dry wafer with N2align wafer with 'cermet' maskexpose wafer with 405 nm, 5 mW/cm2 light for 25 sec.spray develop photoresist using AZ400K:H 20 (1:4), for 90 sec.rinse wafer in deionized H2O for 1 min.dry wafer with N2723. Sputterr.f. magnetron sputter 2000 A Cr:SiO (45:55 at. wt %)set:argon flow rate: 50 sccmbase pressure: 5 mTorrinput power to target: 200 Wattsd.c. target bias: -230 Vr.f. magnetron sputter 500 A Ti:W (30:70 at. wt %)set:argon flow rate: 50 sccmbase pressure: 5 mTorrinput power to target: 100 Wattsd.c. target bias: -140 V4. Photoresist stripping and cleaning10 min. in hot lift-off acetone5 min. in hot, new lift-off acetone immersed in an U/S bath3 min. in warm acetone immersed in an U/S bath3 min. in hot clean trichloroethylene3 min. in hot clean acetone3 min. in hot clean iso-propanoldry wafer with N25. Measure cermet height and inspect current-voltage andcapacitance-voltage characteristics of the cermet diodestructuresGate Metal Deposition1. General Clean-up3 min in warm acetone immersed in an U/S bath3 min. in hot clean trichloroethylene3 min. in hot clean acetone3 min. in hot clean iso-propanoldry wafer with N22. Photolithographydispense AZ4110, 1.1 rim, positive photoresist, onto waferspin wafer at 4000 rpm for 20 sec.softbake wafer at 90°C for 30 min.allow wafer to cool for 3 min.align wafer with 'gate metal' maskexpose wafer with 405 nm, 5 mW/cm 2 light for 16 sec.spray develop photoresist using AZ400K:H 20 (1:4), for 90 sec.rinse wafer in deionized H2O for 1 min.dry wafer with N23. Evaporationsequentially e-beam evaporate:500 A of Ti100 A of Pt3000 A of Auat a pressure of 840 -6 Torr4. Photoresist Stripping and cleaning15 min. in hot lift-off 1M2P5 min. in hot, new lift-off 1M2P in an U/S bath5 min. in hot lift-off acetone immersed in an U/S bath3 min in warm acetone immersed in an U/S bath3 min. in hot clean trichloroethylene3 min. in hot clean acetone3 min. in hot clean iso-propanoldry wafer with N25. Reactive Ion Etchprecondition plasma chamber with a CF 4:02 plasma for 20 min.reactive ion etch unwanted Ti:W with CF 4:02 for 2 min.set:CF4:02 flow rate: 100:10 sccmbase pressure < 2 mTorrpressure: 150 mTorrpower density: 400 mW/cm2temperature: 30°C746. Measure cermet height, inspect current-voltage and capacitance-voltage characteristics of FETs and check the quality of thegates with a scanning electron microscope(SEM)Interlayer Dielectric and Via Formation1. General Clean-up3 min. in warm acetone immersed in an U/S bath3 min. in hot clean trichloroethylene3 min. in hot clean acetone3 min. in hot clean iso-propanoldry wafer with N22. Deposit and cure polyimidedispense Du Pont PI-2556 polyimide onto waferspin wafer at 4000 rpm for 60 sec.softbake wafer at 105°C for 15 min. in a forced air ovenramp up and hold the oven temperature at 250°C for 90 min.ramp down the oven temperature to below 100°Callow wafer to cool for 3 min.3. Evaporatione-beam evaporate:500 A of Tiat a pressure of 8406 Torr4. Photolithographydispense AZ4110, 1.1 gm, positive photoresist, onto waferspin wafer at 4000 rpm for 20 sec.softbake wafer at 90°C for 30 min.allow wafer to cool for a minimum of 3 min.align wafer with 'interlayer dielectric' maskexpose wafer with 405 nm, 5 mW/cm 2 light for 16 sec.spray develop photoresist using AZ4001C:H 20 (1:4), for 90 sec.rinse wafer in deionized H 2O for 1 min.5. Reactive Ion Etchprecondition plasma chamber with a CF4:02 plasma for 20 min.reactive ion etch exposed Ti with CF 4:02 for 3 min.set:flow rates of CF4:02: 100:10 sccmbase pressure < 2 mTorrpressure: 150 mTorrpower density: 400 mW/cm 2temperature: 30°Creactive ion etch exposed polyimide and photoresist with 02for 8 min.set:flow rate of 02 to 100 sccmbase pressure < 2 mTorrpressure: 50 mTorrpower density: 400 mW/cm 2temperature: 30°Creactive ion etch remaining Ti with CF4:02 for 4 min.set:flow rate of CF4:02 to 100:10 sccmbase pressure < 2 mTorrpressure: 150 mTorrpower density: 400 mW/cm 2temperature: 30°C6. Measure polyimide height and check the quality of the vias with a SEMSecond Level Metallization1. General Clean-up3 min. in warm acetone immersed in an U/S bath3 min. in hot clean acetone3 min. in hot clean iso-propanoldry wafer with N22. Photolithographydispense AZ4210, 2.1 p,m, positive photoresist, onto waferspin wafer at 4000 rpm for 20 sec.softbake wafer at 90°C for 30 min.allow wafer to cool for a minimum of 3 min.align wafer with 'second level metal' maskexpose wafer with 405 nm, 5 mW/cm2 light for 16 sec.spray develop photoresist using AZ400K:H 20 (1:4), for 90 sec.rinse wafer in deionized H2O for 1 min3. Evaporationsequentially e-beam evaporate:1000 A of Ti5000 A of Auat a pressure of 8.106 Torr4. Photoresist Stripping and cleaning15 min. in hot lift-off acetone5 min. in hot, new lift-off acetone immersed in an U/S bath3 min. in warm acetone immersed in an U/S bath3 min. in hot clean acetone3 min. in hot clean iso-propanoldry wafer with N2APPENDIX C: HRGCCD Bonding ConfigurationC aHRGCCD Dieb_ .. 	 . 	 _ 	 ._ . .. 	 ... _ . 	 • — 	 . _ . ._ . .	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A.• 	 C.A.' 	 ....4t• k•Ak. t•te.. 	 ‘e.•t.e. 	 *.t.t.o., . _ .. . _Ribbon Size:0.0005" x 0.003"Gate Wires:0.0008"1 - No Connection2 - (I)1A3 - No Connection4 - c1)15 - No Connection6 - G27 - Input Ohmic8 - G19 - No Connection10 - No Connection11 - No Connection12 - No Connection13 - No Connection14 - No Connection15 - Ground16 - No Connection17 - No Connection18 - No Connection19 - No Connection20 - Amplifier Drain21 - Amplifier Output22 - Amplifier Source23 - Reset Drain24 - Reset Gate25 - G326 - (1)227 - No Connection28 - cl)2AUniversity of British ColumbiaVancouver, B.C., CanadaDesigned by: 	 J. CrewmenDrawn by: 	 B. WilsonChecked by: 	 J. CresswellRef. Dwgs.: Rev Date Loc Revision: BY App'dTolerances Unless Otherwise Specified:Fractional Dimensions: ±	Angular Dimensions:Decimal Dimensions: 	 ± 	 Surface Finish:Approved by 	 J. CresswellRoot Filename:5V1Drawing List:DL—XXXXScale: 	 NoneDate: 	 02/10/92TRIUMFHRGCCD BondingConfigurationMaster Disk No.:MD—XXXXDrawing No.:A-99Rev.:C b a      

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