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A single phase Al₀ 3Ga₀ 7As/GaAs heterojunction resistive-gate charge-coupled device Wohlmuth, Walter Anthony 1992

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A SINGLE PHASE A1 03 Ga mAs/GaAs HETEROJUNCTION RESISTIVE-GATE CHARGE-COUPLED DEVICE by WALTER ANTHONY WOHLMUTH B.A.Sc., The University of British Columbia, 1990 A THESIS SUBMI 1 I ED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTERS OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES DEPARTMENT OF ENGINEERING PHYSICS  We accept this thesis as conforming to the required standard  THE UNIVERSITY OF BRITISH COLUMBIA September 1992 © Walter Anthony Wohlmuth, 1992  In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission.  Department of  	5,,,1at rJ EE 1.1C1  The University of British Columbia Vancouver, Canada  Date  DE-6 (2/88)  	oc-r.  112.  P gys%cS  Abstract  The design, fabrication, and evaluation of a 128 pixel, single phase A1 0.3 GavAs/GaAs heterojunction resistive-gate charge-coupled device (HRGCCD) is described. The HRGCCD has a higher operating speed and a larger charge handling capacity in comparison to the conventional buried channel, resistive-gate GaAs charge-coupled device (GaAs RGCCD). The higher operating speed of HRGCCDs is due to the higher electron mobility and velocity in an AlGaAs/GaAs heterojunction in contrast to a GaAs homojunction. In addition, the HRGCCDs can be integrated with high-speed on-chip high electron mobility transistors (HEMTs). The larger charge handling capacity of a HRGCCD is the direct result of the higher electron density in a HRGCCD in comparison to a GaAs RGCCD. A quantum mechanical model is used to calculate the carrier density in a triangular potential well formed at the interface between an undoped AlGaAs layer and an undoped GaAs layer. This model is coupled to a solution of Poisson's equation in bulk AlGaAs to determine the total carrier density in a HRGCCD for different layer and material specifications. This model is used to aid in the design of the HRGCCD. The fabrication of the HRGCCD required six mask levels employing 405 nm contact photolithography with a 1.0 tim design rule. Developments in the process technology previously employed at TRIUMF were required to create the HRGCCDs. These developments included a standard chlorobenzene-aided photoresist lift-off process to delineate r.f. magnetron sputtered Cr:SiO islands and a dry etch process to create ii  interconnect vias. Two process runs of HRGCCDs, with differing layer parameters, were fabricated and evaluated at 4.33 MHz and at 50 MHz. The HRGCCDs tested at 50 MHz exhibited a charge transfer efficiency in excess of 0.99, and a dynamic range in excess of 50 dB with a linear response over a 40 dB input signal range.  iii    Table of Contents  Abstract  ii  Table of Contents  iv  List of Tables  vi  List of Figures  vii  List of Symbols Acknowledgements  1. INTRODUCTION  1  2. DEVICE THEORY AND OPERATION 2.1. AlGaAs/GaAs Heterojunctions 2.2. Design of the HRGCCD's Active Layers 2.3. Operation of the HRGCCD 3. DEVICE FABRICATION 3.1. Ohmic Contact Formation 3.2. Device Isolation 3.3. Cermet Deposition 3.4. Gate Metal Deposition 3.5. Interlayer Dielectric and Via Formation 3.6. Second Level Metallization iv  12 12 16 26 32 32 34 35 40 40 44  4. DEVICE CHARACTERIZATION  47  5. SUMMARY AND PROSPECTS FOR FUTURE WORK  52  5.1. Summary 5.2. Considerations for Future Work  52 54  BIBLIOGRAPHY  55  APPENDIX A: Program Listing for the Carrier Density Calculations  63  APPENDIX B: The HRGCCD Fabrication Procedure  70  APPENDIX C: HRGCCD Bonding Configuration  78  List of Tables  Table I: A summary of different GaAs based CCDs  8  Table II: The n-A1 0.3 Ga vAs layer parameters for the HRGCCDs  18  Table III: The signals applied to the HRGCCD and their corresponding voltage levels  31  Table IV: The settings used for the CF4 :0 2 and 02 reactive ion etches  43  Table V: The charge transfer efficiency of HRGCCDs from runs A07 and A08 . . . . 49  vi  List of Figures  Figure 1.1: The potential distribution along the channel of a GaAs CGCCD  3  Figure 1.2: The potential distribution along the channel of a GaAs RGCCD  6  Figure 1.3: A schematic diagram of; (a) a HRGCCD, (b) the on-chip HEMT circuit  9  Figure 2.1: The energy band diagram of an n-AlGaAs layer and an undoped GaAs layer; (a) not in contact, with the vacuum level chosen as the point of reference, (b) in contact, under zero bias conditions  13  Figure 2.2: The energy band diagram of a HRGCCD  20  Figure 2.3: The measured and theoretical capacitances of Schottky-barrier diodes from the A07 and A08 process runs  25  Figure 2.4: (a) The input stage of a HRGCCD. The surface potential distribution when the 44 clock is at: (b) 0.0 V, (c) -4.0 V  27  Figure 2.5: (a) A portion of the transport region of a HRGCCD. The surface potential distribution at time: (b) t=to , (c) t=t i , and (d) t=t2 . (e) The voltages applied to the transport electrodes 28 Figure 2.6: A diagram of the output stage of a HRGCCD, and the on-chip HEMTs  30  Figure 3.1: An overview of the HRGCCD fabrication procedure  33  vii  Figure 3.2: Deposition of the cermet and gate metal using, (a) the unaided, and (b) the chlorobenzene-aided photoresist lift-off process  36  Figure 3.3: A photograph displaying gate metal electrodes placed on top of cermet film which contains wings  37  Figure 3.4: A photograph of the sidewall profile of AZ4210, 2.1 p.m photoresist employing, (a) the unaided, and (b) the chlorobenzene-aided photoresist liftoff process 38 Figure 3.5: A photograph of the sidewall profile of overexposed AZ4210, 2.1 p.m photoresist  39  Figure 3.6: The three-step reactive ion etch process used to form the interconnect vias  42  Figure 3,7: A photograph of completed interconnect vias. The vias are approximately 4 pm square separated by a gap approximately 4µm long . . . 43 Figure 3.8: A photograph of the entire HRGCCD. The bonding pads are 96 pm squ are  45  Figure 3.9: A photograph of the input section of the HRGCCD  45  Figure 3.10: A photograph of a portion of the transport region of a HRGCCD . . . 	 46 Figure 3.11: A photograph of the output section of a HRGCCD  46  Figure 4.1: A photograph of the input and output waveforms of a HRGCCD operated at 4.33 MHz  48  Ali  Figure 4.2: A photograph of the output waveform of a HRGCCD operated at 4.33 MHz. There are 100 nS per division on the horizontal scale and 200 mV per division on the vertical scale 48 Figure 4.3: The measured and theoretically calculated frequency response of a HRGCCD operated at 50 MHz  50  Figure 4.4: The frequency response of a HRGCCD operated at 50 MHz with the input signal attenuated in steps of 10 dB  51  Figure 4.5: The linearity of the HRGCCD response for a 12.5 MHz input signal . . . 51  ix  List of Symbols  All energies are referenced to the Fermi level energy unless otherwise stated. A B    area of a Schottky-barrier contact pad    insertion loss  Bo    insertion loss normalization factor  c,  capacitance of a Schottky-barrier diode    thickness of the undoped AlGaAs layer  d   D  2-dimensional density of states  E0	fh st energy level in the 2-dimensional electron gas, referenced to the bottom of the potential well at the AlGaAs/GaAs interface E 1	second energy level in the 2-dimensional electron gas, referenced to the bottom of the potential well at the AlGaAs/GaAs interface Ec  conduction band energy  E a  conduction band energy at the doped/undoped AlGaAs interface, referenced to the bottom of the potential well at the GaAs/AlGaAs interface  Ef    Fermi level energy  En  Fermi level energy, referenced to the bottom of the potential well at the AlGaAs/GaAs interface  E g  band gap energy  Emu,  minimum conduction band energy  Ev	valence band energy  E  conduction band energy at an arbitrary point along the x-axis  f  input signal frequency  fc	operating frequency of the HRGCCDs Fs	surface electric field i  integer index  k  Boltzmann's constant effective mass of electrons in GaAs  n d	density of ionized donors in the depletion region underneath a Schottkybarrier electrode o f	density of free carriers in the doped AlGaAs n m	maximum density of carriers in the 2-dimensional electron gas ns	density of carriers in the 2-dimensional electron g&s N e	effective density of states in the conduction band Nd Nd +	density  density of donor impurities in the doped AlGaAs of ionized donor impurities in the doped AlGaAs  N,  number of single electrode transfers in the HRGCCD  q  electronic charge total charge thickness of the doped AlGaAs layer  T  absolute temperature  Vg	applied bias to a Schottky-barrier electrode \ To ff  pinch-off voltage of the HRGCCD  Vt  thermal voltage, kT xi  x  depth in the HRGCCD  )(min  location of the minimum in the conduction band energy  y  a dummy variable for integration  Yo, Yi  Shubnikov-de Haas constants  AEc  conduction band discontinuity  AEd  donor level energy referenced from the conduction band energy  AE,  valence band discontinuity  EAlGaAs —  permittivity of AlGaAs  EGaAs  permittivity of GaAs efficiency an arbitrary point along the x-axis space charge density Schottky-barrier height  XA1GaAs  —  electron affinity of AlGaAs  XGaAs  electron affinity of GaAs  h  reduced Planck's constant  xii  Acknowledgements  I would like to express my thanks to my thesis supervisors, Dr. Maurice LeNoble and Dr. Tom Tiedje for their assistance and counsel. I would also like to thank Mr. John V. Cresswell for co-supervising this project and for his guidance and judgments.  I thank Dr. Maurice LeNoble, Mr. John V. Cresswell, Dr. Richard R. Johnson, and Dr. Douglas Bryman for offering me the opportunity to work on this project at TRIUMF.  I am especially indebted to Mr. David Webster and Mr. Raymond Bula for their assistance, patience, and time in the microelectronics lab at TRIUMF.  I would also like to extend my thanks to Miles Constable, Beverly Wilson, Naomi Shibaoka, and Yvonne Langley for their help in technical aspects of this project.  1. INTRODUCTION  The gallium arsenide charge-coupled device (GaAs CCD) was originally proposed by Schuermeyer et al. in 1972[1], and consists of an array of metal-GaAs Schottky-barrier electrodes separated by small, dielectric filled gaps. This structure is known as a capacitivegate CCD (CGCCD). A GaAs CGCCD was first demonstrated by Kellner et al. in 1977[2], with a charge transfer efficiency (CTE) of 0.98 at frequencies between 5 kHz and 1 MHz[2]. Since then, attempts have been made to increase the CTE and the operating frequency of a GaAs CGCCD for the purpose of ultra-high frequency signal processing[3,4]. In 1981, Cohen et al.[3] demonstrated the operation of a GaAs CGCCD at a frequency of 1 GHz with a CTE of 0.994, and in 1984, Sovero et al.[5] reported a GaAs CGCCD with a CTE of 0.999 at 1 GHz.  Potential wells, also termed energy troughs, may form within the GaAs CGCCD active layer, underneath the gaps, due to a non-monotonically varying potential along the dielectric/GaAs interface[6,7]. The energy troughs capture a small quantity of charge from a passing charge packet. The trapped charge may be released from the energy troughs after a period of time or may be lost through recombination, resulting in greater charge transfer inefficiency and subsequent CCD performance loss[7,8].  1  A schematic illustration of a portion of the transport region of a GaAs CGCCD is shown in Figure 1.1(a). The GaAs CGCCD active layer thickness is typically greater than 1 p.m and the active layer doping density is usually between 10 15 to 10 16 cm -3 [9]. The electrodes are separated by gaps approximately 1 gm long. The transport electrodes are identified as 401, 44A, 402, and 4)2A. A non-monotonic potential distribution along the channel of a GaAs CGCCD, in single phase operation, is shown in Figures 1.1(b) and 1.1(c), to demonstrate charge trapping by energy troughs. Initially, a charge packet is shown to reside underneath the 44A electrode when the voltage signals applied to the transport electrodes are such that 4)1A > 4)1 4)2A > 4)2, as displayed in Figure 1.1(b). In Figure 1.1(c), the signals applied to the electrodes change, from their initial values to 4)2A > 4)2 > 44A > 4)1, by the application of a clock pulse to the 44 and 41A electrodes. The  charge packet will be transferred to the potential well formed underneath the 4)2A electrode, as shown in Figure 1.1(c). Some of the charge from the charge packet is trapped in the energy troughs formed between the 4)1 and 431A, and the 4)1A and 4)2 electrodes resulting in decreased charge transfer efficiency.  Deyhimy et al.[7] developed a two-dimensional electrical analogue of a GaAs CGCCD to investigate the relationship between the spacing of the CGCCD Schottky-barrier electrodes and the relative magnitude of the energy trough. They found that the relative magnitude of the energy trough was reduced as the gap length was reduced[7]. Colbeth et al.[9] showed that the magnitude of the energy troughs in a GaAs CGCCD is proportional to the active layer doping density and inversely proportional to the active layer thickness[9]. 2  cl)1A  (I)2A O  O  1,2A  c1)1  O  O  O  rIr _I  r  O  1611//4112 WI A I  1  n—GaAs ti  1 um  rAir. ••••■---  	1  111:11  Semi—insulating GaAs substrate  I charge packet  (b  0  N  energy troughs distance  trapped charge /  ( c) charge packet  energy troughs  x  distance  Figure 1.1: The potential distribution along the channel of a GaAs CGCCD.  They found that a GaAs CGCCD with an electrode spacing of 1 gm, an active layer doping density of 7.040' cm 3 , and an active layer thickness of 0.90  gm  possessed a CTE in excess  of 0.999[9]. Colbeth et al. demonstrated that the doping density of the active layer of a GaAs CGCCD should be between 10 15 - 10 16 cm -3 , for an active layer thickness ranging from 0.35 gm to 0.90 gm, to achieve CTEs greater than 0.99[9]. Metal-semiconductor field-effect 3  transistors (MESFETs), which are monolithically integrated with the GaAs CGCCD, typically require thin, highly doped active layers for optimal perforrnance[10,11,12]. Since the GaAs CGCCD requires relatively low doping levels and a thick active layer in comparison to conventional GaAs MESFETs, the performance of the on-chip MESFETs will be compromised[13].  Song et al.[14] proposed a recessed gap GaAs CGCCD in 1989. They found that by recessing the gaps, the effect of energy troughs on GaAs CGCCD performance is reduced and the compatibility of the GaAs CGCCD with on-chip MESFETs is increased, because a recessed gap GaAs CGCCD can be fabricated on thin, highly doped active layers[14]. Song et al.[14] fabricated recessed gap GaAs CGCCDs with a GaAs active layer thickness between 0.135 and 0.285 pm, a GaAs active layer doping density between 1.2 and 2.0.10 17 cm', and recessed gaps between 0.05 and 0.13 pm deep. These devices were operated at a clock frequency of 12 MHz, demonstrating C 1 Es approaching 0.9999[14]. Difficulties in fabrication of recessed gaps, uniformity of the etch across the wafer, and reduced fringing fields in the gap region were identified as the main problems with this design[14].  An increased compatibility with on-chip MESFETs and an elimination of energy troughs is obtained from the GaAs resistive-gate CCD (RGCCD). The first GaAs RGCCD was demonstrated by Higgins et al. in 1982[10]. In 1984, Sovero et al.[15] operated a GaAs RGCCD at frequencies ranging from 1 MHz to 4 GHz with a CTE of 0.99 at 2.5 GHz[15].  4  The GaAs RGCCD has short transport electrodes separated by wide gaps. The electrodes are usually placed on top of a thin layer of conductive cermet material that covers the surface of the GaAs active layer in the transport region of the GaAs RGCCD[16,17]. The cermet material used for a GaAs RGCCD is a metal-insulator composite[10,16,18]. A cermet film can be modelled as a distributed resistance/capacitance structure[19]. LeNoble et al.[18] developed a transmission line model of the cermet/GaAs interface to investigate the surface potential variation in the gaps of a GaAs RGCCD. They showed that the surface potential distribution in the gaps of a GaAs RGCCD is monotonic for all frequencies. The formation of energy troughs between the electrodes is suppressed because the surface potential variation is monotonic. Due to the suppression of energy troughs in GaAs RGCCDs, these devices can be fabricated on thin, highly doped active layers enabling compatibility with a MESFET process[10].  A schematic illustration of a portion of the transport region of a GaAs RGCCD is shown in Figure 1.2(a). The GaAs active layer thickness is typically less than 1 p.m, and the active layer doping density is usually 10 17 cm 3 [9,16,18]. The resistive-gate electrodes are separated by gaps greater than 1 long[9,18]. A monotonic potential distribution along the channel of a GaAs RGCCD, in single phase operation, is shown in Figures 1.2(b) and 1.2(c), to demonstrate the suppression of energy troughs. Initially, a charge packet is shown to reside underneath the (1)1A electrode when the voltage signals applied to the transport electrodes are such that 101A > 431 (102A > 4)2, as displayed in Figure 1.2(b). In Figure 1.2(c), the signals applied to the electrodes change, from their initial values to c132A > 4)2 5  > c13.1A > (1)1, by the application of a clock pulse to the 4)1 and (131A electrodes. The charge packet will be transferred to the potential well formed underneath the (132A electrode, as shown in Figure 1.1(c). The monotonic surface potential variation in the gaps suppresses the formation of energy troughs, resulting in low charge loss.  --2 2  (a)  (1)2A 0  (13.1 0  43.1A 0  (I)2 0  43.2A 0  (1)1 0  V/A  V A  1////1  IZ/A  DTI  Viii  1-111----	Cermet  > 1 urn  n—GaAs  Semi—insulating GaAs substrate  1 Urn  0.2 um  TT -  charge packet  (b) distance  charge packet  (c) distance  x  Figure 1.2: The potential distribution along the channel of a GaAs RGCCD.  6  Improvements in AlGaAs/GaAs heterojunction fabrication technology have enabled the realization of heterojunction AlGaAs/GaAs CCDs. These devices have two significant operational advantages over GaAs CCDs. The main advantages are: increased operating speed and increased dynamic range. The increased device speed is a result of two primary factors. Heterojunction AlGaAs/GaAs CCDs can be monolithically integrated with high electron mobility transistors (HEMTs). HEMTs have superior transport characteristics compared to conventional MESFETs due to higher electron mobility and higher electron velocity in A1GaAs/GaAs heterojunctions than in GaAs homojunctions[20,21]. The increased dynamic range of a heterojunction AlGaAs/GaAs CCD is a result of higher carrier densities. The carrier density in an AlGaAs/GaAs CCD can be up to 2.0. 1012 cm-2[22], while the highest carrier density in a GaAs CCD is approximately 2.0.10 11 cm -2 [9,18].  Liu et al.[23] fabricated the first heterojunction CGCCD (HCGCCD) in 1979. The device used a layer of A1 0.22Ga0.78As placed on top of a semi-insulating GaAs substrate. Milano et al.[24,25] created a modified AIGaAs/GaAs HCGCCD in 1982, that exhibited a CTE of 0.98 at 6 kHz and 0.9 at 100 kHz.  The extension of the GaAs RGCCD to heterojunction materials was suggested by Milano et al. in 1983[25], but not realized. Song et al.[26] demonstrated the operation of the first AlGaAs/GaAs heterojunction RGCCD (HRGCCD) in 1991. The device exhibited a CTE of 0.999 for frequencies between 10 MHz and 1 GHz[26].  7  Figure 1.3(a) displays a schematic representation of a HRGCCD. The input and output ohmic contacts of the HRGCCD are labelled I/O and 0/P, and the Schottky-barrier electrodes, which control charge injection and charge extraction in the HRGCCD, are labelled Gl, G2, and G3. The on-chip HEMT circuitry which senses the presence of a charge packet at the 0/P node of the HRGCCD is comprised of a reset HEMT and a HEMT amplifier. R/G is the gate electrode and R/D is the drain electrode of the reset HEMT. B/D is the drain electrode, B/S is the source electrode, and B/0 is the output electrode of the HEMT amplifier. A schematic diagram of the on-chip HEMT circuit is given in Figure 1.3(b).  The different CCDs described in this chapter are summarized in Table I. The active layer thickness, the active layer charge density, the electrode spacing and the on-chip transistor technology are listed for each of the CCDs.  Device  Thickness  Charge Density  Electrode Spacing  Transistor technology  CGCCD  > 1µm  1 - 3.10 10 cm -2  5 1µm  MESFET  recessed gap CGCCD  < 0.3 gm  2.1011 cm -2  5. 1µm  MESFET  RGCCD  < 1 gm  2.1011 cm -2  > 1µm  MESFET  HCGCCD  < 0.2 gm  1012 cm-2  51  µm  HEMT  HRGCCD  < 0.2 gm  1012 cm -2  > 1µm  HEMT  Table I: A summary of different GaAs based CCDs.  8  G1 I/O  G2  41  0  0  41A 4)2 0 0  42A 41 o  42A G3 0 0 0/P R/G R/D  0 0 0 0  Cerrnet   °  f  n-A1GaAs - 0.2 urn  Undoped A1GaAs Spacer < 0.2 urn GaAs Buffer  B/D  Legend:  AMA  B/0 0  -  Schottky barrier metallization  -  ohmic contact metallization  - isolated regions -  0.004 urn  cermet  R/ D  B/D  R/G b  B/S  o  B/ s  There are a variety of applications that can employ HRGCCDs. These applications include: electrooptical signal processing for spectrum analyzers[27], optical matrix multipliers[28,29], video signal processing[30,31,32], optical imaging systems[9,33,34], and beam forming systems for radar and sonar systems[35].  A 128 pixel, single phase HRGCCD was fabricated at the Tri-University Meson Facility (TRIUMF, Vancouver, Canada) for application in a 500 MHz transient digitizer system[36,37,38]. This system will become part of the rare kaon decay spectrometer for Experiment number 787 at Brookhaven National Laboratories (BNL, New York, U.S.A)[39,40,41].  The design, fabrication, and evaluation of HRGCCDs fabricated at TRIUMF will be presented. A description of the AlGaAs/GaAs heterojunction and the design of a HRGCCD will be given in Chapter 2. A self-consistent solution of Schrodinger's and Poisson's equations aided in the design of the HRGCCD. The technique used to inject and sense charge in the HRGCCD, and the clocking scheme applied to the transport electrodes of the HRGCCD, will also be detailed in Chapter 2. In chapter 3, the fabrication of a HRGCCD and the modifications of the process technology previously employed at TRIUMF will be presented. The modifications included: the development of a chlorobenzene-aided photoresist lift-off process to reduce the formation of wings in a r.f. magnetron sputtered cermet film, and the development of a reactive ion etch process to obtain a high degree of etch anisotropy for the purpose of forming interconnect vias. 10  Device performance measurements and tests will be described in Chapter 4. The tests were used to characterize the HRGCCD die, and the measurements were used to determine the CTE, the dynamic range, and the linearity of the response of the devices. A summary and considerations for future work will be presented in Chapter 5.  11  2. DEVICE THEORY AND OPERATION  A quantum mechanical model will be developed in section 2.1. to calculate the carrier density in the triangular, quantum mechanical, potential well. In section 2.2, the quantum mechanical model will be coupled to a solution of Poisson's equation in the bulk AIGaAs to determine the capacitance-voltage (C-V) profile of a Schottky-barrier. The theoretical C-V profile will be compared to measured C-V profiles of Schottky-barrier diodes fabricated with the HRGCCDs. The injection, transport and detection of charge in a HRGCCD will be described in section 2.3.  2.1. AlGaAs/GaAs Heterojunctions  A triangular, quantum mechanical, potential well is formed when a doped AlGaAs layer is grown on top of an undoped GaAs layer, due to the different electron affinities of GaAs and AIGaAs[22]. The well extends from the AlGaAs/GaAs interface into the undoped GaAs layer. The energy band diagram of an n-AIGaAs layer and an undoped GaAs layer is displayed in Figure 2.1, E c is the conduction band energy, E v is the valence band energy, Ef is the Fermi level energy, En is the Fermi level energy referenced to the bottom of the potential well, E g is the energy band gap, AE c is the conduction band discontinuity, .6,E v is the valence band discontinuity, XAIG,A, is the electron affinity of AIGaAs, and XGaAs is the electron affinity of GaAs. 12    X AlGaAs 	vacuum level    E c,A1GaAs f,A1GaAs  	E  (a)  z    AE,  X GaAs  Ec,GaAs  E g,AIGaAs  Ef,GaAs Ev,GaAs  E v,A1GaAs AE,  Eg,GaAs 2DEG  E, Ef  (b)  E fI  E,  AIGaAs GaAs  Figure 2.1: The energy band diagram of an n-AIGaAs layer and an undoped GaAs layer; (a) not in contact, with the vacuum level chosen as the point of reference, (b) in contact, under zero bias conditions. Free electrons in the doped AIGaAs layer diffuse into the lower energy GaAs layer and become trapped in the potential well. Electron motion in the well is quantized in the zdirection, defined in Figure 2.1, because the de Broglie wavelength of the electrons in the well is larger than the width of the well[22,42]. The quantization of electron motion results in the formation of a two-dimensional electron gas (2DEG) within the potential well. The existence of a 2DEG at the AIGaAs/GaAs interface has been experimentally verified using Shubnikov-de Haas magnetoresistance oscillation measurements, and cyclotron resonance 13  measurements[43].  Stern et al.[44] have calculated the discrete energy levels in the 2DEG by solving Schrodinger's wave equation for a triangular potential well. The energy levels are given by  E =  2  11  —3  2 m *  2  2  2  	 q F + 1 45 s1  4"  i  = 0,1,2,--  (1)  Here, h is the reduced Planck constant, m* is the effective mass of the electrons in GaAs, and F s is the surface electric field. F s is related to the carrier density (n a) in the 2DEG by Gauss's law[22] eabisf's  = qn s  (2)  where e GaAs is the permittivity of GaAs. By substituting the surface electric field, from equation (2) into equation (1), the energy levels in the 2DEG can be written as 2  ET = y i n.:  i  = 0,1,2,--  (3)  The Shubnikov-de Haas constants, y o and y l , have been approximated by Linh et al.[45] to be 1.16.10 -9 eV•cm 4/3 and 1.49.10 9 eV•cm 4/3 respectively.  14  The carrier density in the 2DEG can be expressed as E1  Co  f  2D ns = D f q(E-Efl )  E o + e kT dE  	+  E  	dE q(E - Efl )  l +  e  (4)  kT  using Fermi-Dirac statistics and assuming that only the first two energy levels in the potential well are populated with electrons. Here, En is the Fermi level energy referenced to the bottom of the potential well, k is Boltzmann's constant, T is absolute temperature, and D is the two-dimensional density of states of the electron gas which is[22] D = g70 m* - 3.24.10 13 cm -2 V -1 1 2.  (5)  Applying the identity  f	 1  -  (6)  1n(1 +CY)  +e  to equation (4), n s can be written as  n  q(Efi -E0) kT  _ D kT 	÷e  	q(Efi  +e  - E1 ))1  (7)  kT  Substituting E0 and E 1 from equation (3) into equation (7) yields  q (En -y o ns213))( kT  +e  q (Ell - y i ns213 )  	kT  )1  (8)  This equation establishes a relationship between En and n s which will be used in the 15  development of a theoretical model of the C-V profiles of Schottky-barrier diodes fabricated with the HRGCCDs.  2.2. Design of the HRGCCD's Active Layers  The design of the active layers for the HRGCCDs and the development of a theoretical model to determine the C-V profile of a Schottky-barrier diode is presented in this section. The theoretical C-V model was developed by solving Poisson's equation in the bulk AlGaAs, to find the conduction band energy and the carrier density as a function of the bias applied to a gate electrode, and coupling this solution to the equation for the carrier density in the 2DEG, equation (8), developed in the previous section. The HRGCCDs consist of, from bottom to top: an undoped, liquid-encapsulated Czochralski grown, semi-insulating <100> GaAs substrate, a 1 undoped GaAs buffer layer, a 40  A  undoped Al0.3 Ga0.7As spacer layer, a uniformly doped n-A10.3 GacoAs active layer designed to produce a pinch-off voltage of -1.4 V, and a 100  A, 1.10 18 cm -3, uniformly doped n+-  GaAs cap layer.  The 100 A GaAs cap layer is used to aid in the formation of ohmic contacts for the HRGCCD. This layer is removed after the ohmic contacts have been formed and therefore will not be considered in the solution of Poisson's equation.  16  An undoped AlGaAs spacer layer is commonly placed in between the doped AlGaAs and the GaAs buffer layer to spatially separate the impurities in the doped AlGaAs layer from the 2DEG. This layer reduces impurity scattering of electrons in the 2DEG[46], and lessens the probability of electron tunnelling from the 2DEG to the doped AlGaAs layer. Shur found that the optimal spacer layer thickness is between 40 and 100 A[46].  The thickness of the uniformly doped n-A1 0.3 Ga 0.7As layer was calculated to produce a pinch-off voltage (V off) of -1.4 V for different active layer doping densities.  Voff  can be  found from the following relationship[47]  Voff =  AE qN d t 2 -  -  q  (9)  2 e AlcaAs  where 41b is the Schottky-barrier height, Nd is the doping density of the n-A10.3 Ga0.7As layer, t is the thickness of the n-A10.3 Ga0.7As layer, and EAG,A., is the permittivity of A10.3 Ga 0.7As. The terms ch, DES, and EAGaAs were taken to be 0.7 V, 0.241 eV, and 1.06.10 -12 F/cm 2 [48], respectively, in the calculations. The n-Al 0.3 Ga 07As layer parameters for the two HRGCCD runs, A07 and A08 described in this work, are summarized in Table II. The Schottkybarrier height was determined to be 0.85 volts for the A07 devices and 0.92 volts for the A08 devices by using the Richardson-Dushman equation[49,50] for charge transport across a Schottky-barrier junction and neglecting series and contact resistances.  17  Process Run  Layer Thickness (A)  Doping Density (cm -3)  A08  1100  2 • 10 17  A07  800  4 • 1017  Table II: The n-A10.3 GacoAs layer parameters for the HRGCCDs. Delagebeaudeuf and Linh modelled the transport characteristics of an AlGaAs/GaAs heterojunction[45]. Their model assumed that all of the donor atoms in the doped A1GaAs layer were ionized and free electrons did not exist in the doped AlGaAs layer. Lee et al.[51] showed that these assumptions are invalid. They produced a model of an AlGaAs/GaAs heterojunction which took into account the incomplete ionization of electrons in the doped AlGaAs layer and the existence of free electrons in the doped AlGaAs layer. However, in their approach the carrier density in equation (8) was linearized with respect to the Fermi level energy. Their model does not accurately predict the experimentally observed capacitance-voltage characteristics of a Schottky-barrier diode when the applied bias approaches zero[52,53]. Eskandarian[54] developed a mixed quantum mechanical and classical model of the transport characteristics of an AlGaAs/GaAs heterojunction which models the experimentally observed capacitance-voltage characteristics of a Schottky-barrier diode reasonably well over a wide range of applied biasses. This model couples the quantum mechanical model of the AlGaAs/GaAs interface developed by Stern et al.[44] to a solution of Poisson's equation in the A1GaAs layers. Eskandarian's model is used in this work to determine the density of electrons in a HRGCCD as a function of the bias applied to a Schottky-barrier electrode.  18  The one-dimensional Poisson equation in the bulk AIGaAs is  d 2 (E c - E 	dx 2  )  _  p    q(N; - n1)  e AlGaAs    (10)  e AlGaAs   where p is the space charge density in the AIGaAs layers, Nd+ is the ionized donor density in the doped AIGaAs layer, o f is the free electron density in the doped AIGaAs layer, and x refers to depth in the HRGCCD, as shown in Figure 2.2. The density of ionized donors in AIGaAs is given by[54] Nd 	Nd  -(Ec -Er AEd)  1 +2e  (11)  kT  through-the application of Fermi-Dirac statistics and assuming that there is only one donor level in Al0.3 Ga0.7As, 0.006 eV below the conduction band edge[55]. This assumption is valid for an Al content in AIGaAs of less than 0.22[55]. For Al contents in excess of 0.22, a second donor level exists between 0.05 and 0.100 eV below the conduction band edge[55]. This second donor level was neglected in this work to simplify the solution of Poisson's equation. In equation (11), E c is the conduction band energy referenced to the Fermi level energy El', and GlEd is the donor level energy referenced from the conduction band energy. A closed form approximation for o f is[56]  nI  (E, -Et)  1 +4e  19  kT  (12)  where N c is the effective density of states in the conduction band of AlGaAs and is taken to be 6.988.10 17 cm -3 [57].  Ef  Ev  x   t  X num  0  —d  Figure 2.2: The energy band diagram of a HRGCCD.  20  Equation (10) can be integrated analytically by multiplying both sides of the equation by  d(k-E1)1 2[  (13)  dx  and integrating with respect to x from the undoped AlGaAs/GaAs interface to a point () in the doped AlGaAs layer  	2  f  	-d  d 2 (Ec -E,) d(E -E,) x2    dx  Et  E.  dx  =f  f	 £  Ec-E d( -E)+ 21) d(k 1  )  .  (14)  E. AIGaAs  AEC-Et./ AIGaAs  Here, d is the thickness of the undoped AIGaAs spacer layer,  is the conduction band  energy at x= E, and E a is the conduction band energy at the doped/undoped AIGaAs interface EIS =  Ak-Efl -  q nsd  (15)  e AlGaAs  Since the doping density of the undoped A1GaAs layer is small in comparison to the doped A1GaAs layer, the electric field at the undoped/doped AIGaAs interface is approximately the same as the electric field at the undoped AIGaAs/GaAs interface and is given by[54] Ecs  I Ak-Efl  2	 o • d(E, Ef)  e AlGaAs  q ns —  _  2  (16)  e A1GaAs  Substituting equations (11) and (12) into equation (10) and integrating with respect to x yields the following equation 21  (EC-Ef- AEd) 2 +e	kT  [d(k-E1)}2 _2qNd kT hl £ A1GaAs  (Ecs -Ef-AEd) 2 +e	kT  -(E,-E1) +  -  +e	kT 4Nc	4 in N d	-(E„-E1) 4 +e	kT  (17)  qns e AlGaAs  The conduction band energy (E c-E 1) in the bulk AIGaAs is found as a function of the 2DEG carrier density (n s ). When charge neutrality exists within the bulk AIGaAs (Nd + = n f), the 2DEG carrier density is a maximum[54]. The maximum 2DEG carrier density (n m ) is found by calculating the conduction band energy under charge neutrality conditions and substituting the conduction band energy into equation (8). An arbitrary value between 0 and n m is chosen for n s . Equation (8) is used to find Efi which is substituted into equation (15) to find E m . The minimum conduction band energy (E mm ) is found by setting the left hand side of equation (17) to zero, substituting E m into equation (17) and solving for E c-Ef. Equation (17) is rewritten in terms of dx and numerically integrated to find the location of the minimum (Xmin ) in the conduction band energy. Knowledge of the location and value of the minimum in conduction band energy enables the conduction band energy (4b-Vs) at the Schottky-barrier metal/doped AIGaAs interface (x=t) to be found by integrating equation (17) with respect to x from x=xmm to x=t and solving for E c-Ef at x=t.  22  The ionized donor density (n d ) in the depletion region below a Schottky-barrier gate electrode, is calculated by integrating  Nd +  with respect to x from the edge of the depletion  region (x=xn, in ) to the Schottky-barrier electrode/doped AIGaAs interface (x=t)  nd  = f N d dx +  (18)  This equation was integrated numerically by substituting equations (11) and (17) into equation (18). The solution of equation (18) establishes a relationship between n d and V g which was used to find the theoretical capacitance of the Ti-Pt-Au Schottky-barrier diodes fabricated with the HRGCCDs. The program used to find the conduction band energy and the ionized donor density as a function of the bias applied to a Schottky-barrier gate electrode is given in Appendix A.  The electrons in the 2DEG are screened from the gate electrode by the space charge in the region extending from x=0 to x=x„, i„ as a result of charge neutrality X min  ns  f  N d+   dx = 0  (19)  The charge in the GaAs buffer layer and in the semi-insulating GaAs substrate has been neglected in equation (19). Consequently, the total gate capacitance (C,) of a Schottkybarrier diode is  23  and  aQ - aA Ct(Vg) W a Vg  (20)  g  where Q is the total gate charge of the diode and A is the gate area taken to be 10 -4 cm 2 . The theoretical and measured capacitances of the Ti-Pt-Au Schottky-barrier diodes associated with the A07 and A08 process runs are shown in Figure 2.3. The agreement between measurement and theory is reasonable for the A07 and A08 devices except for an apparent voltage displacement between the measured and the theoretical curves for the A08 devices. The displacement is a result of a thinner active layer supplied by the vendor (1000  A instead of 1100 A) which has caused the measured C-V profile to shift.  24  16 14  cexp — measured capacitance cth — theoretical capacitance  1210 Li.  a)  0 C  Q  86420 —2.0  10  0.0  cexp — measured capacitance cth — theoretical capacitance  I  0  8-  X  6a) C  0 0 0  U  0  0 0  cth  0  cexp  O  4-  0  O  2-  0  A08 •  0 —2.0  —1.5  —1.0 Applied Bias (V)  —0.5  00  Figure 2.3: The measured and theoretical capacitances of Schottky-barrier diodes from the A07 and A08 process runs.  25  2.3. Operation of the HRGCCD  For the HRGCCD to operate successfully the following sequence of events must occur: (1) charge injection, (2) charge transport, and (3) charge detection. An analog signal applied to the input of the HRGCCD is transformed into a series of discrete charge packets within the HRGCCD. The charge packets are subsequently transferred through the HRGCCD using a single phase clocking scheme applied to the transport electrodes 4)1A, 431A, (1)A, and (1)2A. The charge packets arriving at the output of the HRGCCD are transformed into analog voltages by the on-chip HEMTs.  The input stage of the HRGCCD consists of an input ohmic contact (I/O) and two Schottky-barrier control electrodes (G1 and G2). G1 is a.c. coupled to the 4)1 clock which varies from -5.0 to 0.0 V, and G2 is held constant at 0.0 V. A schematic representation of the input stage of the HRGCCD, and an illustration of the charge injection process is presented in Figure 2.4. An analog input signal ranging from 0.0 to 0.3 V is applied to the I/O node of the HRGCCD. Charge is injected into the potential well formed underneath the (1)1A electrode when the bias applied to the G1 electrode and the 431 clock is 0.0 V, as shown in Figure 2.4(b). When the 44 clock swings negatively, the charge under the 4)1A electrode is transferred into the potential well formed underneath the (1)2A electrode, creating a discrete charge packet in the first pixel of the HRGCCD, as displayed in Figure 2.4(c). The magnitude of the charge packet injected into the transport region of the HRGCCD is a function of the analog input signal. The nominal voltages applied to the 26  input stage of the HRGCCD are listed in Table III, on page 31. I/o    G1  G2  01  01A  02  02A  01  0  0  0  0  0  0  0  V A  V Ai  V A  A  V A V A  Cermet n—A1GaAs  (a)  GaAs Buffer  Undoped A1GaAs Spacer  T  nu.  A charge transport  (b  )  Ow-  distance  A  X  charge packet -  Ow-  distance  X  (a) The input stage of a HRGCCD. The surface potential distribution when the 1)1 clock is at: (b) 0.0 V, (c) -4.0 V. Figure 2.4:  An illustration of the charge transport process is shown in Figure 2.5. The charge packets are transferred from the input stage to the output stage of the HRGCCD by the application of a single phase clock, as shown in Figure 2.5(e). Initially, at time t=t o , a charge packet resides underneath the 4)2A electrode when the voltages applied to the transport electrodes are such that 4)2A > 4)2 4)1A > 4)1. The discrete charge packet is transferred to the potential well formed underneath the 4)1A electrode, at time t=t1, 27  4)2 O  4) 2 A  4)1  O  O  1////1  1," A  —2 Plll  (a)  4) 1 A  Cermet  4)2  4) 2 A  4)1  O  O  O  f77Z  [7.1  F7Z  n—A1GaAs GaAs Buffer Undoped A1GaA Spacer Layer ao  (b)  0 0 O  t = to  eis  ci!)  0  0 distance  (c)  charge packet  a) 0 a)  t = t1  a 0 Z g O 0  CL  distance  x  (d )  t  distance V 2A 4)2 4) 1 A 4)1  t 0  t2  1  t  Figure 2.5: (a) A portion of the transport region of a HRGCCD. The surface potential distribution at time: (b) t=to , (c) t=t i , and (d) t=t2 . (e) The voltages applied to the transport electrodes. 28  t  2  when the voltages applied to the transport electrodes change from their initial values to (131A > (I)1 432A > (132. The charge packet is transferred to the next cI32A electrode, at time t=t2, when the voltages applied to the transport electrodes return to their initial values. The nominal voltages applied to the transport electrodes of the HRGCCDs are presented in Table III, on page 31.  The output stage of the HRGCCD consists of a Schottky-barrier control electrode G3, an output ohmic contact 0/P, a reset HEMT, and a HEMT amplifier as shown in Figure 2.6. The 0/P node is connected to the source contact of a reset HEMT and the input gate of a HEMT amplifier. The 0/P node is precharged to the drain voltage of the reset HEMT by applying a positive voltage pulse to the reset gate (R/G) on the rising edge of the 44 clock. The pulse turns the reset HEMT on, causing the 0/P node to precharge. The reset HEMT is turned off when the reset gate returns to its minimum value, causing the 0/P node to float at its precharged value. When a charge packet arrives at the final (1)2A electrode of the HRGCCD, it passes through the potential well formed underneath the G3 control electrode on the negative transition of the 4)1 clock. The electrons in the charge packet accumulate on the parasitic capacitance (C oR) on the 0/P node causing a negative voltage displacement to occur at the output node (B/O) of the HEMT amplifier. The voltage at the B/O node contains feedthrough components of the reset gate pulse and the clock, as displayed in Figure 2.6. A summary of the voltages applied to the output stage of the HRGCCD is presented in Table III.  29  HRGCCD clock  R/G reset pulse feedthrough B/O  R/G R/D 41A  112  02A  G3  B/D  0  0/P  VA Cerinet Active Region  B/0  C 0/P charge packet  B/S Semi—insulating GaAs substrate  Figure 2.6: A diagram of the output stage of a HRGCCD, and the on-chip HEMTs.  30  Applied Signals  Voltage Level(V)  I/O  0.0 to 0.3  G1  -5.0 to 0.0  G2  0.0  4)1  -5.0 to 0.0  4)1A  -4.0 to 1.0  4)2  -2.0  4)2A  0.0  G3  0.0  R/D  5.0  R/G  0.0 to 3.0  B/D  12.0  B/S  0.0  Table III: The signals applied to the HRGCCD and their corresponding voltage levels.  31  3. DEVICE FABRICATION  The fabrication of the HRGCCD required six mask levels employing a 1.0 micron design rule. The masks provided the patterns for the fabrication of the ohmic contacts, the proton isolation implants, the cermet deposition, the gate and transport electrode metallizations, the interconnect vias, and the second level metallization. Conventional 405 nm contact photolithography was used to transfer the mask patterns to the photoresist on the wafer. An overview of the HRGCCD fabrication procedure is presented in Figure 3.1.  3.1. Ohmic Contact Formation  The formation of the ohmic contacts, to the HRGCCD and the supporting HEMT circuit, was the first step in the HRGCCD fabrication procedure. The wafer was initially cleaned and degreased using a series of solvent solutions which included acetone, trichloroethylene and isopropanol. A nominal 1.1 thick film of Hoechst Celanese AZ4110, positive photoresist, was patterned on the wafer using the ohmic contact mask. The ohmic contact metallization was accomplished by depositing a 550 A thick layer of AuGe (12 % wt. Ge) using thermal evaporation, and sequentially depositing a 100 layer of Ni, and a 1500  A thick  A thick layer of Au using e-beam evaporation at a pressure of 840  Torr. The unwanted metal was removed using the photoresist lift-off method[58] in acetone with the aid of ultrasonic agitation. Ohmic contacts were formed by alloying the deposited 32  active layers  Ohmic Contact Formation  	t  	tt  semi—insulating substrate  ••  Proton Isolation Implants    .  •Opp • io  •  •.4'.,. ••  •••  •  a  active layers buffer layer  Legend:  semi—insulating substrate t:   Cermet Deposition  t  buffer layer  — Ohmic Metal  	tt tt  active layers buffer layer  — Isolation I  •  — Cermet Film  semi—insulating substrate 	t  — Gate Metal — Dielectric  Gate Metal Deposition  active layers buffer layer semi—insulating substrate 	tt  Dielectric Interconnect Vias  buffer layer semi—insulating substrate 4I  2 nd. Level Metallization  a WA :4 gonola  active layers buffer layer semi—insulating substrate  •  • •  — 2 nd. level metal  metals to the doped GaAs and AlGaAs layers following the photoresist lift-off procedure. The alloy was performed at 395 °C for 10 seconds with a Heatpulse 2210 rapid thermal anneal (RTA) system. The doped GaAs cap layer was removed by the developer solution, AZ400K:H 20 (1:4 vol.). The etch rate of GaAs exposed to AZ400K:H 2 0 was found to be 70 -± 20 A per minute.  3.2. Device Isolation  Multiple energy proton isolation implants were used to isolate the active region of the HRGCCD[59]. Ion implantation damages the crystal lattice, creating electron trapping centres which renders the damaged regions insulating[59]. Isolation using mesa etching was not employed because the surface profile of the wafer would be non-planar, making subsequent contact photolithography difficult. A nominal 6.2 thick film of Hoechst Celanese AZ4620, positive photoresist, was used to protect the active regions of the device during the implantation process. A postbake was performed after the photoresist was developed to further harden the photoresist, providing extra protection of the active regions during the implantation process. Two sequential proton implants of 1) 35 keV and 2) 200 keV, at fluences of 1.10 13 cm -2 were used to isolate the active region of the HRGCCD. The photoresist was stripped off in 1-methyl-2-pyrrolidone (1M2P), with the aid of ultrasonic agitation, after the isolation implants were completed.  34  33. Cermet Deposition  A nominal 2.1 pm thick film of Hoechst Celanese AZ4210, positive photoresist, was patterned on the wafer using the cermet mask. The transport region of the HRGCCDs was covered with a nominal 2000 A Cr:SiO (45:55 at. wt. %) cermet film. A 500 A Ti:W (30:70 at. wt. %) layer was placed on top of the cermet to provide adhesion and to form an ohmic contact to the gate metal electrodes. The Cr:SiO and Ti:W films were r.f. magnetron sputtered from four inch composite targets at a pressure of 5 mTorr. The unwanted cermet was removed using the photoresist lift-off method in acetone with the aid of ultrasonic agitation.  A chlorobenzene-aided photoresist process was employed to achieve an overhang profile in the AZ4210 photoresist[60]. This process was utilized to reduce the formation of 'wings' in the cermet film The term 'wings' usually refers to material protruding from the edges of a deposited film, as shown in Figure 3.2(a). In the unaided photoresist lift-off process, a cermet film deposited on photoresist is typically continuous, because the deposition coats the photoresist sidewalls. During the lift-off process, the cermet film coating the sidewalls breaks in an irregular manner resulting in the formation of wings. Subsequent metallizations which are required to step over the irregular cermet edge profile may fail, causing the device to be inoperable. Figure 3.3 illustrates the failure of the metal electrodes to step over a cermet film which has wings. This failure can be avoided by soaking the photoresist covered wafer in chlorobenzene, which causes the removal of low 35  Wings  a)  Legend: — Gate Metal — Cermet  Undercut resist  (b  — AZ4210 Resist  )  "/7 -  JA11112111111  A  Figure 3.2: Deposition of the cermet and gate metal using, (a) the unaided, and (b) the  chlorobenzene-aided photoresist lift-off process.  molecular weight resin and residual solvents from the upper layers of the photoresist[60]. The action of the developer on these upper layers is retarded, resulting in the formation of an undercut sidewall profile in the photoresist[60], as shown in Figure 3.2(b). In the chlorobenzene-aided photoresist process, the deposited cermet film will typically be discontinuous because the undercut photoresist sidewall profile shadows the deposition. 36  18 iiirons  4.84 Kx 8.85 Ku 8/18/92 11:37 p 5.675 Microns CURRAN 111E7 Nanonetrics  X: -8.289 nn R: 368.8 deg Y: -8.762 nn T: 45.8 deg  Figure 3.3: A photograph displaying gate metal electrodes placed on top of cermet film which contains wings.  A chlorobenzene-aided photoresist process was developed for the AZ4210 photoresist. It was found, through experimentation, that a 20 minute, room temperature, chlorobenzene soak following a 30 minute, 70° C softbake produced a suitable overhang profile for the AZ4210 photoresist. The sidewall profiles of AZ4210 photoresist employing the unaided and chlorobenzene-aided photoresist lift-off processes are displayed in Figure 3.4. The photoresist islands are 4 gm wide and the overhang of the chlorobenzene-aided photoresist is between 0.25 and 0.5 Lim. Interference fringes can be seen in the sidewall 37  profile of the unaided photoresist, as displayed in Figure 3.4(a).  a)  ... 18 Microns 5.33 Kx 8.85 Ku 8/21/92 9:19 . p 5.675 Microns CURRAN IIIEZ Hanonetrics  (b  )  -18 Nicrons •■■■■•■1•■■• 4.38 Kx 8.85 Ku 8/18/92 . 14:32 p 5.675 Microns DURAN IIIEZ Hanonetrics  Figure 3.4: A photograph of the sidewall profile of AZ4210, 2.1 Lim photoresist employing, (a) the unaided, and (b) the chlorobenzene-aided photoresist lift-off process.  38  The interference fringes are standing waves patterns in the photoresist caused by diffraction and reflection of the imaging beam used to transfer the mask pattern to the photoresist[61]. Standing wave patterns also cause notches to form in the edges of the photoresist, as displayed in Figure 3.5. Interference fringes and notches are less pronounced in the chlorobenzene-aided photoresist process because the upper layers of the photoresist have been modified[60].  CURRAN IIIEZ tianonetrics Figure 3.5: A photograph of the sidewall profile of overexposed AZ4210, 2.1  photoresist.  The optimum exposure and develop times of the photoresist were different for the unaided and the chlorobenzene-aided photoresist processes, due to the effect of chlorobenzene on the upper layers of photoresist. The optimum exposure and develop times were found, through experimentation, to be 25 seconds and 130 seconds, respectively, for an imaging wavelength of 405 nm and a power density of 5.0 mW/cm 2 . 39  3.4. Gate Metal Deposition  The Schottky-barrier gates and transport electrodes were deposited after the cermet islands were formed. A nominal 1.1 p,m thick film of AZ4110 was patterned on the wafer using the gate metal mask. The gate metal deposition was accomplished by sequentially ebeam evaporating a nominal 500 A thick layer of Ti, a 100  A thick layer of Au at a pressure of 8.10  -6  A thick layer of Pt and a 3000  Torr. The unwanted metal was removed using  the photoresist lift-off method in 1M2P with the aid of ultrasonic agitation. After the lift-off process, a CF 4 :0 2 reactive ion etch (RIE) was used to remove the Ti:W in between the transport electrodes.  3.5. Interlayer Dielectric and Via Formation  A 1µm thick film of Du Pont PYRALIN PI2556 polyimide was used as the interlayer dielectric[62]. The polyimide was imidized in a temperature controlled convection oven. The oven temperature was initially held at 100°C for 15 minutes, it was then ramped up to and held at 250 °C for 90 minutes, and subsequently ramped down to a temperature of less than 100°C over a period of an hour. The 250°C maximum temperature of the oven, in this process, was below the 360°C eutectic temperature of the ohmic contacts[63], and the 500°C anneal temperature of the proton isolation implants[64].  40  The interconnect vias between the first and second level metallization were formed by using a multilevel patterning process. A thin, 500  A thick layer of Ti was deposited on  the polyimide using e-beam evaporation at a pressure of 840 6 Torr. A 1.1 gm thick photoresist film was subsequently patterned on the Ti layer. The vias were formed by using a three-step reactive ion etch process shown in Figure 3.6.  A CF4 :0 2 etch was used to remove the Ti in the photoresist openings, transferring the via mask in the photoresist to the underlying Ti. The polyimide in the openings of the Ti layer and the photoresist was etched with 0 2 . Finally, a CF4 :0 2 etch was performed to remove the remaining Ti, completing the formation of the interconnect vias in the polyimide. Figure 3.7 shows a photograph of completed interconnect vias.  A conventional plasma etch chamber, a Technics Planar Etch plasma etching system, was originally used at TRIUMF to form interconnect vias for earlier devices. It was found that greater etch anisotropy was required to minimize lateral etching of the 512, 4 gm square vias needed for the HRGCCDs. To accomplish this a reactive ion etching process was developed using a 13.56 MHz Plasma-Therm 2406 reactive ion etch system. Reactive ion etching offers substantial etch anisotropy since the etch proceeds more rapidly in the direction of the applied electric field[65]. Experiments were done to determine the effect of the flow rates of CF4 and 0 2, the power density, the chamber pressure, duration of the etch, temperature of the substrate holder, and ratios of CF 4 to 0 2 on the different RIEs. A summary of the RIE parameters used to fabricate the HRGCCDs is given in Table IV. 41  CF 4  2  RIE  Ti patterning etch V 44 .  /A  0  ■,  2  V A  RIE Legend:  a)  (/) (/) (/)  a)  Polyimide and photoresist etch  I A  I  V A  A'  iiuiiy  VA  rA  Arr  V A  - P12556 Polyimide  0  - First Level Metal  0.4 4:1 •■-•  - Titanium  0  - AZ4110 Photoresist  CF 4 /0 2 RIE Ti removal etch  =ZZ  /7///7///  =Z2Z2Z  VA  Completed via formation  VA  a)  1 Micron 18.81 Kx	 1.08 K11 12/85/98 14:83 1.664 Microns x . CERAM IIIEZ Manonetrics  X:-14.878 nn R: 293.8 deg Y: 9.422 nn T: 45.8 deg  Figure 3.7: A photograph of completed interconnect vias. The vias are approximately 4 pm square separated by a gap approximately 4 p.m long.  Plasma Parameters  Settings  power density  400 mW/cm 2  temperature  30°C  CF4 flow rate (CF4 :02 )  100 sccm  0 2 flow rate (CF4 :02 )  10 sccm  0 2 flow rate (0 2)  100 seem  pressure (CF4 :0 2 )  150 mTorr  pressure (0 2 )  50 mTorr  base pressure  < 2 mTorr  Table IV: The settings used for the CF 4 :0 2 and 0 2 reactive ion etches.  43  3.6. Second Level Metallization  The second level metallization was the final step in the HRGCCD fabrication procedure. A 2.1 p.m thick film of AZ4210 photoresist was patterned on the wafer using the second level metal mask. The second level metallization was formed by sequentially depositing a nominal 1000  A thick layer of Ti and a nominal 5000 A thick layer of Au using  e-beam evaporation at a pressure of 840' Torr. The Ti layer was used to provide adhesion between the first and second level layers of Au. The unwanted metal was removed using the photoresist lift-off method in acetone with the aid of ultrasonic agitation.  Photographs of a completed HRGCCD fabricated at TRIUMF are displayed in Figures 3.8, 3.9, 3.10, and 3.11. A photograph of the entire HRGCCD is displayed in Figure 3.8. The active region of the HRGCCD is 50 vm wide by 2584 p.m long. The entire HRGCCD die is 950 pm by 3340 pm. A photograph of the input section of the HRGCCD is displayed in Figure 3.9. The I/O contact pad is 20 vm long, the G1 electrode is 2 pm long, the G2 electrode is 10 pm long and the (1)1 electrode is 2 p.m long. The separation between I/O and G1 is 2 pm. The G1 to G2 and G2 to 431 gaps are both 1 pan long. A portion of the transport region of a HRGCCD is displayed in Figure 3.10. The transport electrodes are 2 pm long and approximately 100 vm wide. The interelectrode gaps are 3 p.m long. The output stage of a HRGCCD is displayed in Figure 3.11. The G3 electrode is 2 p.m long. All of the on-chip HEMTs employ 2 p.m technology. The detailed HRGCCD fabrication procedure is given in Appendix B. 44  Figure 3.8: A photograph of the entire HRGCCD. The bonding pads are 96 square.  Figure 3.9: A photograph of the input section of the HRGCCD. 45  Figure 3.10: A photograph of a portion of the transport region of a HRGCCD.  Figure 3.11: A photograph of the output section of a HRGCCD. 46  4. DEVICE CHARACTERIZATION  The HRGCCD die from the A07 and A08 process runs were characterized using automated d.c. and a.c. tests. The operation of a HRGCCD is demonstrated at a frequency of 4.33 MHz. Insertion loss measurements were performed to find the CTE, the dynamic range, and the linearity of the HRGCCD response at an operating frequency of 50 MHz.  The HRGCCD die were d.c. and a.c. probed on an Electroglass 1304X, automated probe station to find the functional devices. These devices were then bonded in a 0.45 inch square, 28 pin, 28LCC package, as shown in_ Appendix C, and prepared for further evaluation.  A qualitative demonstration of a HRGCCD operating at 4.33 MHz, is shown in Figures 4.1 and 4.2. The input (upper) and output waveforms (lower) are displayed in Figure 4.1. In 128 clock cycles, the charge packet is transferred from the input to the output stage of the HRGCCD resulting in the 30 pS delay between the input and output waveforms. The output waveform shows little dispersion indicating near unity CTE. A detailed illustration of the HRGCCD output waveform is shown in Figure 4.2. The feedthrough of the reset and clock pulses are evident in the output waveform.  47  111.010m4IIINkilINNIUMMINIIIIIIIiIIIIIIN1141111•11111111111  oxte'v  I  Figure 4.1: A photograph of the input and output waveforms of a HRGCCD operated  at 4.33 MHz.  Figure 4.2: A photograph of the output waveform of a HRGCCD operated at 4.33 MHz. There are 100 nS per division on the horizontal scale and 200 mV per division on the vertical scale.  48  The CTE of the HRGCCDs fabricated at TRIUMF was determined using the insertion loss technique[66,67]. A Hewlett Packard HP-8753A network analyzer and a HP85046 s-parameter test set were used for these measurements. The CTE was calculated by fitting the equation[66], B = 20LOG[Bo exp -Nt (1  -coif).  (21)  fc  to the measured insertion loss. A is the insertion loss in decibels, B o is a normalization factor, N, is the number of single electrode transfers through the HRGCCD (256 for the 128 pixel HRGCCD in single phase operation), n is the charge transfer efficiency, f is the input signal frequency, and f c is the HRGCCD clock frequency. The measurements were performed using an input signal ranging from 300 kHz to 25 MHz and a HRGCCD clock frequency of 50 MHz. The calculated CTE of five HRGCCDs from the A07 and A08 runs are listed in Table V.  Process Run A07  0.998  A07  0.991  A07  0.999  A08  0.995  A08  0.990  Table V: The charge transfer efficiency of HRGCCDs from runs A07 and A08.  49  Figure 4.3 displays the measured and theoretically calculated insertion loss, for the HRGCCD from the A07 process run which exhibited a CTE of approximately 0.999. The CTE of this HRGCCD is in agreement with the results previously obtained by Song et al. [26].  Insertion Loss Measurements efficiency = 0.999  I 1 t I 10 15 5 20 Input Signal Frequency (MHz)  25  Figure 4.3: The measured and theoretically calculated frequency response of a HRGCCD operated at 50 MHz.  The measured dynamic range of the HRGCCD from process run A07 that exhibited a CTE of 0.999, is shown in Figure 4.4. This device exhibited a dynamic range in excess of 50 dB with an essentially linear response over a 40 dB input signal range, as shown in Figure 4.5. The observed deviation from linearity is attributed to the nonlinear relationship between the injected signal charge and the input signal amplitude. This is caused by the voltage dependence of the input capacitance between the control electrodes (G1 and G2) 50  and the input ohmic contact (1/0){68].  0  1 I I I 10 5 15 20 Input Signal Frequency (MHz)  25  Figure 4.4: The frequency response of a HRGCCD operated at 50 MHz with the input signal attenuated in steps of 10 dB.  10 O  (1) -  10  E  o —30 cr  ,  —40  0  —50 —60 —50  I 1 1 I —40 —30 —20 —10 Input Signal Attenuation (dB)  0  Figure 4.5: The linearity of the HRGCCD response for a 12.5 MHz input signal. 51  5. SUMMARY AND PROSPECTS FOR FUTURE WORK  The design, fabrication and evaluation of a 128 pixel, single phase HRGCCD was described in this work, and is summarized in section 5.1. Proposals for the continuing development of these devices are given in section 5.2.  5.1. Summary  The design and operation of a 128 pixel, single phase HRGCCD was explained in Chapter 2. A quantum mechanical model of the triangular potential well formed at an undoped AlGaAs/GaAs interface was developed and coupled to a solution of Poisson's equation in the bulk AlGaAs to determine the carrier densities in a HRGCCD as a function of the active layer parameters and the applied bias. The carrier densities in the HRGCCD were used to calculate the capacitance-voltage profile of a Schottky-barrier diode fabricated along with the HRGCCD. The theoretical capacitance-voltage profile was compared with measured capacitance-voltage profiles of Schottky-barrier diodes fabricated with the HRGCCDs. The agreement between the measured and theoretically computed capacitancevoltage profiles are reasonable. The difference between measurement and theory for the A08 devices is caused by variations in the active layer thickness of the wafers supplied by the vendor.  52  The charge injection, transport, and detection processes in a HRGCCD were also described in Chapter 2. An analog input signal, applied to the input ohmic contact of the HRGCCD, causes a discrete charge packet to form within the input stage of the HRGCCD. A single phase clock, applied to the transport electrodes of the HRGCCD, is used to transfer the charge packet from the input stage to the output stage of the HRGCCD. The charge packet is sensed at the output stage of the HRGCCD by a HEMT amplifier, which converts the charge into an analog voltage signal.  The fabrication of the HRGCCD was presented in Chapter 3. Six mask levels, employing a 1 p.m design rule, were used in the fabrication procedure. The mask patterns were transferred to photoresist placed on the wafer with conventional 405 nm contact photolithography. The six mask steps in the fabrication procedure consist of; the formation of Au/Ge-Ni-Au ohmic contacts, the proton isolation implants, the Cr:SiO cermet film deposition, the Ti-Pt-Au gate metal deposition, the interlayer dielectric and via formation, and the Ti-Au second level metallization. The development of a chlorobenzene-aided photoresist process for Hoechst Celanese AZ4210 photoresist, and a three-step reactive ion etch process to form interconnect vias were also described in this chapter. The chlorobenzene-aided photoresist process was developed to reduce the formation of wings in the cermet film. The reactive ion etch process was developed to obtain an anisotropic and uniform etch across the wafer, enabling the interconnect vias to be precisely formed.  53  The fabricated HRGCCDs were characterized in Chapter 4. Measurements were performed on packaged HRGCCDs to find the CTE, the dynamic range, and the linearity of the response of the HRGCCDs operated at 50 MHz. The CTE was in excess of 0.99 for all of the devices tested, the dynamic range was in excess of 50 dB, and a linear response over a 40 dB input signal range was obtained.  5.2. Considerations for Future Work  Improvements to the HRGCCDs considered in this work can be obtained by using different active layer profiles and materials. The layer structure of the HRGCCD can be modified to reduce the number of defects in the wafer and to increase the operating speed and dynamic range of the HRGCCDs. Defects in the wafers can be reduced by incorporating a superlattice of alternating AlGaAs and GaAs layers between the substrate and the GaAs buffer layer[69]. Different layer profiles and different materials can be used to increase the operating speed and the dynamic range of HRGCCDs. The carrier densities and the mobility of the HRGCCD can be enhanced by planar doping[17,70] or delta doping[71,72] the doped AlGaAs layer, or using indium phosphide based materials. The conduction band discontinuity of InAlAs/InGaAs is larger than that of AlGaAs/GaAs, resulting in better confinement of the carriers in the 2DEG of a InAIAs/InGaAs/InP system[73,74]. The superior confinement properties of InAlAs/InGaAs/InP systems enable the 2DEG to have higher carrier densities and mobilities than AlGaAs/GaAs systems.  54  BIBLIOGRAPHY  [1]. F.L. Schuermeyer, R.A. Belt, C.R. Young and J.M. Blasingame, New Structures for Charge-Coupled Devices, Proceeding of the IEEE, vol. 60, Nov. 1972, p. 1444-1445. [2]. W. Kellner, H. Bierhenke and H. Kniepkamp, A Schottky Barrier CCD on GaAs, 1977 International Electron Device Meeting Technical Digest, p.599. [3]. R.C. Eden and I. Deyhimy, GaAs Integrated Circuits and Charge-Coupled Devices (CCDs) for High-Speed Signal Processing, SPIE vol. 180 Real-Time Signal Processing II, 1979, p.182-189. [4]. M.J. Cohen, GaAs Charge Coupled Devices for High Speed Signal Processing Applications, 1981 International Electron Device Meeting Technical Digest, p.622-625. [5]. E.A. Sovero, R. Sahai, W.A. Hill and J.A. Higgins, Microwave Frequency GaAs ChargeCoupled Devices, Proceedings of the 1984 IEEE GaAs IC Symposium, p.101-104. [6]. R.H. Walden, R.H. Krambeck, R.J. Strain, J. McKenna, N.L. Schryer and G.E. Smith, Bell Systems Technical Journal, vol.51, 1972, p.1635. [7]. I. Deyhimy, R.C. Eden and J.S. Harris Jr., GaAs and Related Heterojunction ChargeCoupled Devices, IEEE Transactions on Electron Devices, vol. 27, #6, June 1980, p.11721180. [8]. G.L. Hansell, GaAs Schottky-Barrier Charge-Coupled Devices, PhD Thesis, Massachusetts Institute of Technology, 1982, p.7-15. [9]. R.E. Colbeth, D.V. Rossi, J-I. Song and E.R. Fossum, GHz GaAs CCD's: Promises, Problems and Progress, SPIE Symposium on Electronic Imaging: Advanced Devices and Systems, Proc. SPIE 1071, paper 10.  55  [10]. J.A. Higgins, R.A. Milano, E.A. Sovero and R. Sahai, Resistive Gate GaAs Charge Coupled Devices, Proceedings of the 1982 IEEE GaAs IC Symposium, p.49-52. [11]. I. Deyhimy, R.J. Anderson, R.C. Eden and J.S. Harris Jr., Charge-Coupled Devices in Gallium Arsenide, IEE Proceedings, vol.127, Pt.I, #5, Oct 1980, p.278-286. [12]. I. Deyhimy, R.J. Anderson, S. Lane, GaAs CCD, 1980 International Electron Device  Meeting Technical Digest, p.151-154.  [13]. I. Deyhimy, J.S. Harris, R.C. Eden, D.D. Edwall, and R.J. Anderson, High Speed GaAs CCD, 1978 International Electron Device Meeting Technical Digest, p.617-619. [14]. R.E. Colbeth, J-I. Song, D.V. Rossi and E.R. Fossum, A Recessed-Gap Capacitive-Gate GaAs CCD, IEEE Electron Device Letters, vol.10, #12, Dec. 1989, p.525-527. [15]. E.A. Sovero, R. Sahai, W.A. Hill, and J.A. Higgins, Microwave Frequency GaAs Charge-Coupled Devices, Proceedings of the 1984 IEEE GaAs IC Symposium, p.101-104. [16]. J-I. Song and E.R. Fossum, Characterization of Evaporated Cr-SiO Cermet Films for Resistive-Gate CCD Applications, IEEE Transactions on Electron Devices, vol. 36, #9, Sept. 1989, p.1575-1579. [17]. E.R. Fossum, J-I. Song and D.V. Rossi, Two-Dimensional Electron Gas ChargeCoupled Devices (2DEG-CCD's), IEEE Transactions on Electron Devices, vol.38, #5, May 1991, p.1182-1192. [18]. M. LeNoble, J.V. Cresswell, and L. Young, The Surface Potential Variation in the Interelectrode Gaps of GaAs Cermet-Gate Charge-Coupled Devices, Solid State Electronics, vol.33, #7, 1990, p.851-857. [19]. C.R. Wronski, B. Abeles, R.E. Daniel and Y. Arie, Granular Metal-Semiconductor Schottky Barriers, Journal of Applied Physics, vol.45, 1974, p.295-299.  56  [20]. F. All and A. Gupta, HEMTs and HBTs: Devices, Fabrication, and Circuits, Artech House, Norwood, MA, 1991, p.1-13. [21]. M. S. Shur, GaAs Devices and Circuits, Plenum, New York, NY, 1987, p.541-545. [22]. M. S. Shur, GaAs Devices and Circuits, Plenum, New York, NY, 1987, p.513-525. [23]. Y.Z. Liu, I. Deyhimy, R.J. Anderson, J.S. Harris Jr., and L.R. Tomsetta, GaAIAs/GaAs Heterojunction Schottky Barrier Gate CCD, 1979 International Electron Device Meeting Technical Digest, p.622-624. [24]. R.A. Milano, M.J. Cohen, and D.L. Miller, Modulation-Doped AlGaAs/GaAs Heterostructure Charge Coupled Devices, IEEE Electron Device Letters, vol.3, #8, Aug. 1982, p.194-196. [25]. R.A. Milano, J.A. Higgins, D.L. Miller, and E.A. Sovero, The Application of Modulation-Doped Heterostructures to High Speed Charge Coupled Devices, GaAs and Related Compounds 1982, p.445-452. -  [26]. J-I. Song, D.V. Rossi, S. Xin, W.I. Wang and E.R. Fossum, A Resistive-Gate A10.3 GacoAs/GaAs 2DEG CCD with High Charge Transfer Efficiency at 1 GHz, IEEE Transactions on Electron Devices, vol. 38, #4, April 1991, p.930-931. [27]. R.H. Kingston and F.J. Leonberger, Fourier Transformation Using an Electroabsorptive CCD Spatial Light Modulator, IEEE Journal of Quantum Electronics, vol.19, #9, Sept. 1983, p.1443-1451. [28]. R.C. Eden and I. Deyhimy, GaAs Integrated Circuits and Charge-Coupled Devices (CCDs) for High-Speed Signal Processing, SPIE vol. 180 Real-Time Signal Processing II, 1979, p.182-189. [29]. E.A. Sovero, W.A. Hill, R. Sahai, J.A. Higgins, S. Pittman, E.H. Martin and R.L. Pierson Jr., Transversal Filter Application of a High Speed Gallium Arsenide CCD, Proceeding of the 1983 GaAs IC Symposium, p.92-95.  57  [30]. R.H. Kingston, B.E. Burke, K.B. Nichols and F.J. Leonberger, Spatial Light Modulation using Electroabsorption in a GaAs Charge-Coupled Device, Applied Physics Letters, vol. 41, #5, Sept. 1982, p.413-415. [31]. J.A. Higgins, Electro-optical Signal Processing Applications of the GaAs CCD, SPIE vol.495 Real Time Signal Processing VII, 1984, p.197-204. [32]. R.E. Colbeth and E.R. Fossum, A 1-GHz Charge-Packet Replicator/Subtractor Circuit for GaAs CCD Signal Processing, IEEE Journal of Solid-State Circuits, vol.25, #4, Aug. 1990, p.1016-1019. [33]. P.B. Kosel, M.R. Wilson, J.T. Boyd and L.A. King, Configurations for High Speed GaAs CCD Imagers, SPIE vol.460 Processing of Guided Wave Optoelectronic Materials, 1984, p.71-78. [34]. J-I. Song, D.V. Rossi and E.R. Fossum, GaAs CCD Readout for Engineering Bandgap Detectors, SPIE vol.1308 Infrared Detectors and Focal Plane Arrays, 1990, p.254-260. [35]. D.A. Davidson and 0. Berolo, GaAs Charge-Coupled Devices, Canadian Journal of Physics, vol.67, 1989, p.225-231. [36]. M. Atiya, M. Ito, J. Haggerty, C. Ng and F.W. Sippach, Waveform Digitizing at 500 MHz, Nuclear Instruments and Methods in Physics Research, vol.279, 1989, p.180-186. [37]. D. Bryman, J.V. Cresswell, M. LeNoble and R. Poutissou, 500 MHz Transient Digitizers Based on GaAs CCDs, IEEE Transactions on Nuclear Science, vol.38, #2, Apr. 1991, p.295-300. [38]. H.B. Crawly, A 15 MHz 32-Channel Flash ADC FASTBUS Board for use at LEP, IEEE Transactions on Nuclear Science, vol.35, #1, 1988, p.295-299. [39]. S. Weinberg, A Model of Leptons, Physical Review Letters, vol.19, #21, Nov. 1967, p.1264-1270. 58  [40]. D.A. Bryman, Rare Kaon Decays, International Journal of Modern Physics A, vol.4, #1, 1989, p.79-114. [41]. M.S. Atiya, I-H. Ciang, J.S. Frank, J.S. Haggerty, M.M. Ito, T.F. Kycia, K.K. Li, L.S. Littenberg, A. Stevens, R.C. Strand, D.S. Akerib, D.R. Marlow, P.D. Meyers, M.A. Selen, F.C. Shoemaker, A.J.S. Smith, G. Azuelos, E.W. Blackmore, D.A. Bryman, L. Felawka, P. Kitching, Y. Kuno, J.A. MacDonald, T. Numao, P. Padley, J-M. Poutissou and J. Roy, Search for the Decay K+ ir+vv, Physical Review Letters, vol.64, #1, Jan. 1990, p.21-24. [42]. T.J. Drummond, H. Morkoc, K. Lee and M.S. Shur, Model for Modulation Doped Field Effect Transistor, IEEE Electron Device Letters, vol.3, #11, 1981, p.338-341. [43]. T. Ando, A.B. Fowler and F. Stern, Electronic Properties of Two-Dimensional Systems, Reviews of Modern Physics, vol.54, #2, Apr. 1984, p.437-672. [44]. F. Stern and S.D. Sarma, Electron Energy Levels in GaAs/Al.Ga i.„As Heterostructure, Physical Review B, vol.30, #2, 1984, p.840-848. [45]. D. Delagebeaudeuf and N.T. Linh, Metal-(n)AIGaAs-GaAs Two-Dimensional Electron Gas FET, IEEE Transactions on Electron Devices, vol.29, 1982, p.955. [46]. M. S. Shur, GaAs Devices and Circuits, Plenum, New York, NY, 1987, p.524-536 and p.569-571. [47]. G. George and J.R. Hauser, An Analytic Model for MODFET Capacitance-Voltage Characteristics, IEEE Transactions on Electron Devices, vol.37, #5, 1990, p.1193-1198. [48]. J-L. Cazaux, G-I. Ng, D. Pavlidis and H-F. Chau, An Analytical Approach to the Capacitance-Voltage Characteristics of Double-Heterojunction HEMT's, IEEE Transactions on Electron Devices, vol.35, #8, Aug. 1988, p.1223-1230. [49]. E.S. Yang, Microelectronic Devices, McGraw-Hill, 1988, New York, NY, p.184-190.  59  [50]. S.M. Sze, Semiconductor Devices Physics and Technology, J. Wiley & Sons, 1985, New York, NY, p.166 169. -  [51]. K. Lee and M. Shur, Electron Density of the Two Dimensional Electron Gas in Modulation Doped Layers, Journal of Applied Physics, vol.54, #4, April 1983, p.2093 2096. -  -  [52]. S T. Fu and M.B. Das, Extraction of Electronic Transport Parameters in Submicrometer Gate Length MODFET's, IEEE Transactions on Electron Devices, vol.38, #8, -  -  Aug. 1991, p.1719-1728.  [53]. I.C. Kizilyalli, M. Artaki and A. Chandra, Monte Carlo Study of GaAs/Al„Ga i.,,,As MODFET's: Effects of Al x Ga l .„As Composition, IEEE Transactions on Electron Devices, vol.38, #2, Feb. 1991, p.197 206. -  [54]. A. Eskandarian, Determination of the Small Signal Parameters of an AlGaAs/GaAs MODFET, IEEE Transactions on Electron Devices, vol.35, #11, Nov. 1988, p.1793-1801. -  [55]. S. Subramanian, A.S. Venggurlekar, and A.A. Diwan, Effect of Shallow and Deep Donors on the Equilibrium Electron Density of the Two Dimensional Electron Gas in a Modulation Doped Field Effect Transistor, IEEE Transactions on Electron Devices, vol.33, -  -  -  #5, 1986, p.707-710.  [56]. R.A. Smith, Semiconductors, 2nd Edition, Cambridge University Press, Cambridge, NY, 1978, p.83. [57]. J. Yoshida, Classical Versus Quantum Mechanical Calculation of the Electron Distribution at the n-AlGaAs/GaAs Heterointerface, IEEE Transactions on Electron Devices,  vol.33, #1, p.154-156. [58]. R.E. Williams, Gallium Arsenide Processing Techniques, Artech House Dedham, MA, 1984, p.126-127. [59]. R.E. Williams, Gallium Arsenide Processing Techniques, Artech House Dedham, MA, 1984, p.211-223. 60  [60].R.E. Williams, Gallium Arsenide Processing Techniques, Artech House Dedham, MA, 1984, p.145. [61].R.E. Williams, Gallium Arsenide Processing Techniques, Artech House Dedham, MA, 1984, p.136-142. [62].Du Pont Company. PYRALIN polyimide coatings, Wilmington, DE, bulletin E-76692686. [63].R.E. Williams, Gallium Arsenide Processing Techniques, Artech House Dedham, MA, 1984, p.235. [64]. H. Hashimoto, Very High Speed Integrated Circuits: Gallium Arsenide LSI, Semiconductors and Semimetals, vol.29, 1990, p.79. [65].R.E. Williams, Gallium Arsenide Processing Techniques, Artech House Dedham, MA, 1984, p.183-187. [66]. R.W. Brodersen, D.D. Buss and A.F. Tasch Jr., Experimental Characterization of Transfer Efficiency in Charge-Coupled Devices, IEEE Transactions on Electron Devices, vol. 22 , #2, Feb. 1975, p. 40-46. [67]. G.F. Vanstone, J.B.G. Roberts and A.E. Long, The Measurement of the Charge Residual for CCD Transfer using Impulse and Frequency Responses, Solid State Electronics, vol. 17, 1974, p.889-895. [68].L.J.M. Esser and F.L.J. Sangster, Handbook on Semiconductors, vol.4, North-Holland Publishing Co., Amsterdam, 1981, p.335-421. [69].H. Takakuwa, K. Tanaka, Y. Mori, M. Arai, Y. Kato and S. Watanabe, A Low-Noise Microwave HEMT using MOCVD, IEEE Transactions on Electron Devices, vol.33, #5, May 1986, p.595-599.  61  [70]. G W. Wang and L.F. Eastman, An Analytic Model for I-V and Small-Signal Characteristics of Planar Doped HEMT's, IEEE Transactions on Microwave Them) and Techniques, vol.37, #9, Sept. 1989, p.1395-1400. -  -  [71]. E.F. Schubert, A. Fischer and K. Ploog, The Delta Doped Field Effect Transistor (SFET), IEEE Transactions on Electron Devices, vol.33, #5, May 1986, p.625-631. -  -  [72]. K. Matsumura, D. Inuoe, H. Nakano, M. Sawada, Y. Harada and T. Nakakado, A New High Electron Mobility Transistor (HEMT) Structure with a Narrow Quantum Well Formed by Inserting a Few Monolayers in the Channel, vol.30 #2, p.166 169. -  [73]. Y C. Pao, C. Nisimoto, M. Riaziat, R. Majidi Ahy, N.G. Bechtel and J.S. Harris Jr., -  -  Impact of Surface Layer on In 0.52A1 0.48As/In 0.53 Gao.47As/InP High Electron Mobility Transistors, IEEE Electron Device Letters, vol.11, #7, July 1990, p.312-314.  [74]. P.C. Chao, A.J. Tessmer, K-H.G. Duh, P. Ho, M-Y. Kao, P.M. Smith, J.M. Ballingall, S M. Liu and A.A. Jarba, W Band Low Noise InAIAs/InGaAs Lattice Matched HEMT's, IEEE Electron Device Letters, vol.11, #1, Jan. 1990, p.59-62. -  -  -  -  62  APPENDIX A: Program Listing for the Carrier Density Calculations  This is the MATHCAD, version 3.1 for Windows, file used to calculate the carrier densities in the HRGCCDs as a function of the bias applied to a Schottky-barrier diode. The carrier densities were found by using a quantum mechanical model of the triangular potential well at the AIGaAs/GaAs interface coupled to a solution of Poisson's equation in the bulk AIGaAs. All references to equations in this file are directed to the work done by Eskandarian[54].  1. Defining the constants:  Nd := 2.10 17	cmA(-3)  doping density  d =1100- 10-8	cm  -doped AIGaAs layer thickness  t :=40.10-8 .  undoped AIGaAs layer thickness  cm  V  4* :=.92  Schottky-barrier height  E :=-- 1.06.10  permittivity of the AIGaAs  -12  F/cm  conduction band discontinuity  AEC := 0.28  eV  donor level energy  AEd : = 0.006  eV  electronic charge  q := 1.602.10-19	C  thermal voltage, kT/q  Vt := 0.0259  effective density of states  Nc := 6.988-10  two-dimensional density of states  D := 3.24.10 13	eVA(-1)*cm^(-2)  Shubnikov-de Haas constant  yo := 1.16. 10-9	eV*cm^(4/3)  Shubnikov-de Haas constant  71 := 1.49.10-9	eVwcmA(4/3)  63  eV 17  cm^(-3)  2. Defining the variables: All energies are referenced to the Fermi level unless otherwise stated. EO  the first energy level in the 2DEG referenced to the bottom of the triangular potential well.  El  the second energy level in the 2DEG referenced to the bottom of the triangular potential well.  EC  the conduction band energy.  ECg  the conduction band energy at the Schottky metal/AIGaAs interface.  ECt, Eg, ECgate  dummy variables used to find ECg.  ECi  the conduction band energy at the GaAs/AIGaAs interface referenced to the bottom of the triangular potential well.  ECm  the minimum conduction band energy in the bulk AIGaAs.  ECml, ECm2, dummy variables used to find ECm. Em, ECroot ECs  the conduction band energy at the doped/undoped AlGaAs interface.  Es  a dummy variable used to find ECs.  ECmax  the conduction band energy at the AIGaAs/GaAs interface when the 2DEG carrier density is a maximum.  ECmaxO  the conduction band energy at the AIGaAs/GaAs interface, referenced to the bottom of the traingular potential well, when the 2DEG carrier density is a maximum.  F    a dummy variable for integration.  Qt ns    the charge within the bulk AIGaAs.    nb  the carrier density in the 2DEG.   xm  p      the carrier density in the bulk AIGaAs. the distance between the minimum conduction band energy in the bulk AIGaAs and the doped/undoped AIGaAs interface. the space charge density in the bulk AIGaAs. a dummy variable for integration.  64  3. Determining the maximum 2DEG carrier density:  The maximum 2DEG carrier density (nm) is found by assuming that the minimum conduction band energy (ECm) is equal to the conduction band energy of the bulk AIGaAs. The conduction band energy of the bulk AIGaAs is obtained by assuming that charge neutrality exists within the bulk AIGaAs. Therefore, Poisson's equation in the bulk AIGaAs can be written as; p = 0 = Nd+ - nf where Nd+ is the ionized donor density and of is the free electron density. By solving Poisson's equation for ECmax the following expression is obtained:  —Ne•exp  ECmax :=Vt.ln 0.5•  Nd  .NT lAEd\ + (0.25- Vt / Nd  - (0.25- Nc ) Nd  eV  ECmax = 0.0417072  The conduction band energy is assumed to be constant in the bulk AIGaAs therefore, the derivative of the conduction band energy with respect to the depth in the bulk AIGaAs is zero (d(EC)/dx = 0) and the left hand side of equation (4) is zero. The maximum carrier density in the AIGaAs is found by numerically solving equations (4) and (5) simultaneously.  a := 2.E.Nd.  b := 4.  Vt  Nc  Nd  c :=1n (2+ exp  / ECmax- AEd)) /  4+ exp  Vt  LECmax\ ) b 1 Vt  An initial guess of the carrier density in the 2DEG (ns) and the conduction band energy (ECmaxO) is required to solve equations (4) and (5) simultaneously.  ECmaxO : _ .2 eV  ns 1.10 11 crn^ 2 -  Note: the variable ECmax is not the same as ECmaxO. Given 2,  2  ECmaxO- y o .ns 3 In  1+ exp  ECmaxO- y i .ns 3 + exp  Vt  Vt  65  ns =0 Vt.D  t  ECmax0 + ns- - - AEC  AEC - AEd - ECmax0 - q.ns2 + exp  nm \ECm  4 + exp  vt  Vt  - ns=0  ' = Find( ns ,ECmax0)  nm = 5.49914583.10 11 cm^-2  4. Calculating the conduction band energy (Ecs) at the undoped/doped AIGaAs interface for a given 2DEG carrier density (ns)  Ecs is found by subtracting the conduction band energy at the GaAs/AIGaAs interface (ECi) and the linear drop in the conduction band energy across the undoped AIGaAs layer (q*net/E) from the conduction band discontinuity. Before Ecs can be found ECi must be found as a function of ns. This is done by calculating E0 and El as a function of ns and then solving equation (5) numerically to find ECi.  maxi = 100 i .. maxi ECO := .5  eV  Given  In 1 + exp  ECO- E0) ) 'ECO El + exp Vt Vt )) 11  ECM(E0 , El , ns) = Find(ECO)  ns. := nm. tanh 3•  maxi  2  E0 i : = yo - (ns i) 3 2  El i : = y i - (ns i) 3  66  ns =0 Vt- D  ECi i := ECf0 (E0 i , El i , ns i) q  E	 Cs. :=DEC - ECi.  5. Calculating the minimum conduction band energy (ECm) in the bulk AIGaAs.  ECm is calculated for a given ns by setting the left hand side of equation (4) to zero, and then numerically solving the resultant equation for ECm. The solution of equation (4) produces two roots ECm1 and ECm2. Finding the first root of equation (4).  Vt  rl  2. q.Nd.—  EC = .5  eV  Given  ri 1+ —.in  2 + exp  1 - EC \ b S EC - Ed) \ ( 4 + exp Vt Vt  ro  e2  ECminl(e2, FO) := Find(EC)  e2 i -  ro i .=  q•ns i  2  2 + exp  ECs i - AEd)) Vt  4 + exp  ECSi b Vt  ECml i	(e2i,F0) Finding the second root of equation (4). EC :=.01  eV  67  -o  Given  / 1 +  2 + exp  F1 ln e2  / EC - AEd\  + exp  b  /-EC  Vt  Vt „  FO EC - ECrootl  -  o  ECmin2(e2, FO,ECrootl ) :=Find(EC) ECm2 i = ECmin2(e2 i  ro i , ECml i)  Choosing the correct root.  1 ECml i  ECm i := max t  ECm2  i  6. Calculating the distance (xm) from the point in the bulk AlGaAs where the conduction band energy is a minimum to the undoped/doped AIGaAs interface.  Equation (4) is integrated from ECs to ECm to find xm.  F( EC , e2, FO) :=1 + Fl -ln  (2 + exp  (EC- AEd \ \ / Vt  4 exp  /  /- EC) b Vt  ro  e2  ECs. 1 ECm I.  2- T  , IF[ (ECm i + T2) , e2i , rod  dT  \  0  7. Calculating the applied bias (Vg) for a given ns:  Equation (4) is used to find the conduction band energy (ECg) at the Schottky metal/AIGaAs interface.  ECt := 2  68  Given  4ECt - ECm  V  •0  2.  - ( d - xm). )12=0  F[ (ECm + T2) , e2, TO  ECgate(ECm, e2, T0, d, xm) : = Find(ECt) ECgi = ECgate (ECm i , e2i , TO i , d, xmi) Vg is found from the relationship:  Vgi : =  -  ECg i  8. Calculating the ionized donor density (nb) caused by the bias (Vg) applied to a Schottky-barrier diode. nb is calculated by integrating the space charge density (p) in the doped AIGaAs from the edge of the depletion region to the AIGaAs/metal interface.  exp /EC - AEd \  Vt  p(EC ) = q. Nd.  2 + exp EC - AEd Vt  VEg - Em Qt(Em, Eg, e22, roo) :=  2. t• p(Em + T2)  Ch  •0  e22-F (Em + t2 , e22, TOO)  1  nb. := —q . Qt(ECm i , ECgi , e2i ,T0 i)  69  APPENDIX B: The HRGCCD Fabrication Procedure  Ohmic Contact Formation  1. General Clean-up 3 min. in warm acetone, immersed in an ultrasonic(U/S) bath 3 min. in hot clean trichloroethylene 3 min in hot clean acetone 3 min. in hot clean iso-propanol dry wafer with N2 2. Photolithography dispense AZ4110, 1.1 pm, positive photoresist, onto wafer spin wafer at 4000 rpm for 20 sec. softbake wafer at 90°C for 30 min. allow wafer to cool for 3 min align wafer with 'ohmic contact' mask expose wafer with 405 nm, 5 mW/cm 2 light for 16 sec. spray develop photoresist using AZ400K:H 2 0 (1:4), for 90 sec. rinse wafer in deionized H 2O for 1 min 3. Evaporation thermal evaporate: 550 A of Au-Ge (12% weight Ge) at a pressure of 840 6 Torr sequentially e-beam evaporate: 200 A of Ni 1500 A of Au at a pressure of 840 6 Torr  4. Photoresist Lift-off and Cleaning 10 min. in hot lift-off acetone 3 min. in hot, new lift-off acetone immersed in an U/S bath 3 min. in warm acetone immersed in an U/S bath 3 min. in hot clean trichloroethylene 3 min. in hot clean acetone 3 min. in hot clean iso-propanol dry wafer with N2 5. Inspect pre-RTA current voltage characteristics of the contacts 6. Rapid Thermal Anneal 10 sec. RTA at 395°C in a  N2 ambient  7. Inspect current-voltage characteristics of the contacts  Device Isolation 1. General Clean-up 3 min. in warm acetone immersed in an U/S bath 3 min. in hot clean trichloroethylene 3 min. in hot clean acetone 3 min. in hot clean iso-propanol dry wafer with N2 2. Photolithography dispense AZ4620, 6.2 gm, positive photoresist, onto wafer spin wafer at 4000 rpm for 20 sec. softbake wafer at 90°C for 30 min. allow wafer to cool for 3 min. align wafer with 'isolation' mask expose wafer with 405 nm, 5 mW/cm 2 light for 60 sec. spray develop photoresist using AZ400K:H 20 (1:4), for 90 sec. rinse wafer in deionized H 2O for 1 min. postbake wafer at 120°C for 15 min. allow wafer to cool for a minimum of 3 min  71  3. Isolation Implants implant H+ atoms at 200 keV, 1.10 13 cm -2 implant H+ atoms at 35 keV, 1.10 13 cm -2 4. Photoresist stripping and cleaning 15 min. in hot lift-off 1-methyl 2-pyrrolidone(1M2P) 5 min. in hot, new lift-off 1M2P immersed in an U/S bath 5 min in hot lift-off acetone immersed in an U/S bath 3 min in warm acetone immersed in an U/S bath 3 min. in hot clean trichloroethylene 3 min. in hot clean acetone 3 min. in hot clean iso-propanol dry wafer with N2 5. Inspect current-voltage characteristics of isolated and unisolated regions  Cermet Deposition 1. General Clean-up 3 min. in warm acetone immersed in an U/S bath 3 min. in hot clean trichloroethylene 3 min. in hot clean acetone 3 min. in hot clean iso-propanol dry wafer with N2 2. Photolithography dispense AZ4210, 2.1 tim, positive photoresist, onto wafer spin wafer at 4000 rpm for 20 sec. softbake wafer at 70°C for 30 min. allow wafer to cool for 3 min. soak wafer in chlorobenzene for 20 min. dry wafer with N2 align wafer with 'cermet' mask expose wafer with 405 nm, 5 mW/cm 2 light for 25 sec. spray develop photoresist using AZ400K:H 20 (1:4), for 90 sec. rinse wafer in deionized H 2O for 1 min. dry wafer with N2 72  3. Sputter r.f. magnetron sputter 2000 A Cr:SiO (45:55 at. wt %) set: argon flow rate: 50 sccm base pressure: 5 mTorr input power to target: 200 Watts d.c. target bias: -230 V r.f. magnetron sputter 500 A Ti:W (30:70 at. wt %) set: argon flow rate: 50 sccm base pressure: 5 mTorr input power to target: 100 Watts d.c. target bias: -140 V 4. Photoresist stripping and cleaning 10 min. in hot lift-off acetone 5 min. in hot, new lift-off acetone immersed in an U/S bath 3 min. in warm acetone immersed in an U/S bath 3 min. in hot clean trichloroethylene 3 min. in hot clean acetone 3 min. in hot clean iso-propanol dry wafer with N2 5. Measure cermet height and inspect current-voltage and capacitance-voltage characteristics of the cermet diode structures Gate Metal Deposition 1. General Clean-up 3 min in warm acetone immersed in an U/S bath 3 min. in hot clean trichloroethylene 3 min. in hot clean acetone 3 min. in hot clean iso-propanol dry wafer with N2  2. Photolithography dispense AZ4110, 1.1 rim, positive photoresist, onto wafer spin wafer at 4000 rpm for 20 sec. softbake wafer at 90°C for 30 min. allow wafer to cool for 3 min. align wafer with 'gate metal' mask expose wafer with 405 nm, 5 mW/cm 2 light for 16 sec. spray develop photoresist using AZ400K:H 2 0 (1:4), for 90 sec. rinse wafer in deionized H 2O for 1 min. dry wafer with N2 3. Evaporation sequentially e-beam evaporate: 500 A of Ti 100 A of Pt 3000 A of Au at a pressure of 840 -6 Torr 4. Photoresist Stripping and cleaning 15 min. in hot lift-off 1M2P 5 min. in hot, new lift-off 1M2P in an U/S bath 5 min. in hot lift-off acetone immersed in an U/S bath 3 min in warm acetone immersed in an U/S bath 3 min. in hot clean trichloroethylene 3 min. in hot clean acetone 3 min. in hot clean iso-propanol dry wafer with N2 5. Reactive Ion Etch precondition plasma chamber with a CF 4 :0 2 plasma for 20 min. reactive ion etch unwanted Ti:W with CF 4 :0 2 for 2 min. set:  CF4 :0 2 flow rate: 100:10 sccm base pressure < 2 mTorr pressure: 150 mTorr power density: 400 mW/cm 2 temperature: 30°C  74  6. Measure cermet height, inspect current-voltage and capacitancevoltage characteristics of FETs and check the quality of the gates with a scanning electron microscope(SEM) Interlayer Dielectric and Via Formation 1. General Clean-up 3 min. in warm acetone immersed in an U/S bath 3 min. in hot clean trichloroethylene 3 min. in hot clean acetone 3 min. in hot clean iso-propanol dry wafer with N2 2. Deposit and cure polyimide dispense Du Pont PI-2556 polyimide onto wafer spin wafer at 4000 rpm for 60 sec. softbake wafer at 105°C for 15 min. in a forced air oven ramp up and hold the oven temperature at 250°C for 90 min. ramp down the oven temperature to below 100°C allow wafer to cool for 3 min. 3. Evaporation e-beam evaporate: 500 A of Ti at a pressure of 840 6 Torr 4. Photolithography dispense AZ4110, 1.1 gm, positive photoresist, onto wafer spin wafer at 4000 rpm for 20 sec. softbake wafer at 90°C for 30 min. allow wafer to cool for a minimum of 3 min. align wafer with 'interlayer dielectric' mask expose wafer with 405 nm, 5 mW/cm 2 light for 16 sec. spray develop photoresist using AZ4001C:H 20 (1:4), for 90 sec. rinse wafer in deionized H 2O for 1 min.  5. Reactive Ion Etch precondition plasma chamber with a CF 4 :0 2 plasma for 20 min. reactive ion etch exposed Ti with CF 4 :0 2 for 3 min. set: flow rates of CF 4 :0 2 : 100:10 sccm base pressure < 2 mTorr pressure: 150 mTorr power density: 400 mW/cm 2 temperature: 30°C reactive ion etch exposed polyimide and photoresist with 0 2 for 8 min. set: flow rate of 0 2 to 100 sccm base pressure < 2 mTorr pressure: 50 mTorr power density: 400 mW/cm 2 temperature: 30°C reactive ion etch remaining Ti with CF4 :0 2 for 4 min. set: flow rate of CF 4 :0 2 to 100:10 sccm base pressure < 2 mTorr pressure: 150 mTorr power density: 400 mW/cm 2 temperature: 30°C 6. Measure polyimide height and check the quality of the vias with a SEM Second Level Metallization 1. General Clean-up 3 min. in warm acetone immersed in an U/S bath 3 min. in hot clean acetone 3 min. in hot clean iso-propanol dry wafer with N2  2. Photolithography dispense AZ4210, 2.1 p,m, positive photoresist, onto wafer spin wafer at 4000 rpm for 20 sec. softbake wafer at 90°C for 30 min. allow wafer to cool for a minimum of 3 min. align wafer with 'second level metal' mask expose wafer with 405 nm, 5 mW/cm 2 light for 16 sec. spray develop photoresist using AZ400K:H 20 (1:4), for 90 sec. rinse wafer in deionized H 2O for 1 min 3. Evaporation sequentially e-beam evaporate: 1000 A of Ti 5000 A of Au at a pressure of 8.10 6 Torr 4. Photoresist Stripping and cleaning 15 min. in hot lift-off acetone 5 min. in hot, new lift-off acetone immersed in an U/S bath 3 min. in warm acetone immersed in an U/S bath 3 min. in hot clean acetone 3 min. in hot clean iso-propanol dry wafer with N2  APPENDIX C: HRGCCD Bonding Configuration    C  a  b  HRGCCD Die _ . .	 _  .  .  _.. _..  .  .  .  . _ .  •  —  .  VVV1  •••••4	s 0 ,•4 4,40 4 60	 	4  —  '••• !"  	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'VW ••• •• •• Al se• • ••••• ■ ••••4 .  	.  _•  ■  4  -  16 17 18 19 20 21 22 23 24 25  - . . .■ •  _  — • .	 .  	_  . _• . _ .  ,  —  A  ‘e.t.e.	 *.t.t.o.,  t•te..  15 - Ground  — •  - - -  4iii.  „:•••::.......... . ....., • . f...4 •$ ••  •  •  "►• .• . v 6	 ,	 ••" •, 4-  -  -.  •  \  • ■  .t , .  —  'Ii!: il  •••■ A "  —  -  41.1i I P. P é14 k• • ••••	 i 0 4 4 I ,,40 , •1  .1 I • 4  :1II  ' ' ' '..  ..  _  — -  417.4441044:4.01 ...  '  -  —  — •  f VP V, .1 I 	0.411 4% ll'e 4 .43: 0.  ii  .	 ••■ '• "' 1 ••• •v. ••••• !i 14 t A 01 •  • •  'lip II I 1 1I 110  - ' '  .1•• • • • ''•••••• .  •  iiirie.V. A . "  ,  -  —  4  •  WO 1 •••• -•-•  .  1  .  -  0 wiloo d I1 •• . • . • •0 .■ A • a r 0 .01■••■• .....  -4464.4! •  ••••••••• • • ■•■•■•■•■•■•  .  4,	 • . ■■,.. ili",%!..•• A  	,  	_  4,  I •• I *4,4o	, t.  a  5 - No Connection 6 - G2 7 - Input Ohmic 8 - G1 9 - No Connection 10 - No Connection 11 - No Connection 12 - No Connection 13 - No Connection 14 - No Connection  — .	 .  —  • ".'  a1  •  	.  '  •  3 - No Connection  . —. .	 .	 _  • ,  • ...  - '	 '  _  ,  ,  .  .  ,  *NI . ‘ & Iiii.  0.• fe.,-. .., 44  .  2 - (I)1A  .  -  	'  .  • ... ...• . -  	 ; 41;4  4,47,4111  ••••• • • • ••	6	 *•• 6		4  ,	1  .  -  "Wili  '  .  .  —  t  i ,	 • 646•4  .  —  •  s  rIrlr4  *A:Ito....%14r 	 1,.... *•••• ••••• • 4 •• • •4 ;	 i4, 	4 •16 	4. 44 it 4 , :•• :4 O.*, • • • 0 :	 ••••••••••, ‘•••••••■ 	V.*. C•••••• *••• •4 ••••e_e. ••4	 ••••• 	41 I • .•■•••	 P •••	 •4•• ik‘e• 	.  	,  —  _.  4 - c1)1  	WIr ,	*nlrlr• 	6  1 - No Connection  • •  	—  . _.  .._  Ribbon Size: 0.0005" x 0.003"  Gate Wires: 0.0008"  Ref. Dwgs.:  Rev  Date  Loc  Revision:  Tolerances Unless Otherwise Specified: Angular Dimensions:  Fractional Dimensions: ± Decimal Dimensions:  Surface Finish:  ±  C  BY  J. Crewmen  Drawn by:  B. Wilson  Checked by:  J. Cresswell  Approved by  J. Cresswell  HRGCCD Bonding Configuration  App'd  Drawing List:  Root Filename:  DL—XXXX  5V1  b  28 - cl)2A  TRIUMF  University of British Columbia Vancouver, B.C., Canada Designed by:  - No Connection - No Connection - No Connection - No Connection - Amplifier Drain - Amplifier Output - Amplifier Source - Reset Drain - Reset Gate - G3 26 - (1)2 27 - No Connection  Scale:  None  Date:  02/10/92  Master Disk No.:  Drawing No.:  MD—XXXX  A-99 a  Rev.:  

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