UBC Theses and Dissertations

UBC Theses Logo

UBC Theses and Dissertations

A low-swing, wide-tuning-range CMOS phase-locked loop Nouri, Neda 2005

Your browser doesn't seem to have a PDF viewer, please download the PDF to view this item.

Item Metadata

Download

Media
831-ubc_2005-0577.pdf [ 3.78MB ]
Metadata
JSON: 831-1.0065861.json
JSON-LD: 831-1.0065861-ld.json
RDF/XML (Pretty): 831-1.0065861-rdf.xml
RDF/JSON: 831-1.0065861-rdf.json
Turtle: 831-1.0065861-turtle.txt
N-Triples: 831-1.0065861-rdf-ntriples.txt
Original Record: 831-1.0065861-source.json
Full Text
831-1.0065861-fulltext.txt
Citation
831-1.0065861.ris

Full Text

A Low-Swing, Wide-Tuning-Range CMOS Phase-Locked Loop by Neda Nouri B.Sc, Tehran Polytechnic University, 2001 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in The Faculty of Graduate Studies Electrical and Computer Engineering THE UNIVERSITY OF BRITISH COLUMBIA September 12, 2005 ©NedaNouri, 2005 Abstract Increasing demand for affordable high performance communication devices, in particular in mobile systems, is the driving force behind the development of high-speed, low cost, and low power circuits in CMOS technology. This is mainly due to the fact that CMOS process facilitates the integration of analog and digital circuits on the same chip. A major technique to reduce the power consumption in a CMOS chip is the use of low-swing signaling. Integrated phase-locked loops (PLLs) are versatile components used in many communication and control applications. In this thesis, the design of a low-swing, wide tuning range charge-pump PLL is presented. PLLs are the integral part of many communication and computing applications. The PLL is designed and simulated in a 0.18um standard CMOS technology. Its frequency range of operation is from 1.14GHz to 2.25GHz. Almost all of the PLL internal signals are fully differential and low swing (IV peak-to-peak differential swing). To further reduce the power consumption of the PLL, the charge pump current of 15uA is used. The PLL operates from a single 1.8V supply while consuming 14.5mW. It remains functional if the supply voltage changes by ±10%. Due to the low-swing nature of the internal PLL signals, the magnitude of the induced noise on the power supply is small, less than 0.8mV. n Table of Contents Abstract i i Acknowledgments viii Table of Contents i i i List of Tables iv List of Figures : v List of Abbreviations vii Chapter 1 1 Introduction 1 1.1. Motivation 1 1.2. Overview of Previous Designs 2 1.3. The Proposed PLL Design Overview 3 Chapter 2 5 Phase-Locked Loop Fundamentals 5 2.1. Phase or Phase/Frequency Detector 7 2.2. Charge-Pump and Loop Filter 11 2.3. Voltage-Controlled Oscillator 14 2.4. Frequency Divider 18 2.5. Charge-Pump Loop Characteristics 18 2.6. Jitter in PLLs 24 Chapter 3 27 Phase-Locked Loop Design Procedure 27 3.1. Phase/Frequency Detector Circuit 29 3.1.1. D-Flip Flop Circuit 31 3.1.2. AND-Gate Circuit 34 3.2. Charge Pump Circuit 35 3.3. Common-Mode Feedback (CMFB) Circuit 37 3.4. Loop Filter Circuit 38 3.5. V C O Circuit 39 3.6. Divider Circuit 43 3.6.1. Divide-by-2 Circuit 44 3.6.2. Divide-by-2/3 Circuit and the Programmable Divider Circuit 46 Chapter 4 51 Simulation Results 51 4.1. General PLL Design 52 4.2. PFD Simulation Results 55 4.3. VCO Simulation Result 56 4.4. PLL Simulation Results 61 4.5. Jitter Measurement 66 4.6. Post Layout Simulations 67 Chapter 5 70 Conclusion and Future Work 70 Bibliography 72 iii List of Tables Table 1. Performance comparison of the proposed PLL with other designs 2 Table 2. Design specifications 28 Table 3. Transistor sizes of the latch block 33 Table 4. AND-gate transistor sizes 35 Table 5. The charge pump transistor sizes 36 Table 6. The sizes of the CMFB transistors 38 Table 7. The transistor sizes in the VCO 43 Table 8. Main parameters in the PLL design 52 Table 9. Impact of process and temperature variations on PLL output frequency 63 Table 10. Simulation results for 10% variation in supply voltage 65 Table 11. Jitter measurement results in Matlab 66 iv List of Figures Figure 2-1. Block diagram of a generic PLL 5 Figure 2-2. Block diagram of a charge-pump PLL 7 Figure 2-3. Definition of a phase detector 8 Figure 2-4. In figure (a), there is a difference between the frequencies of two signals, but in figure (b), both frequencies are equal, although they have a phase difference 9 Figure 2-5. A conventional tri-state PFD 10 Figure 2-6. Tri-state PFD state diagram 10 Figure 2-7. Simplistic charge-pump circuit 11 Figure 2-8. Differential charge pump with a loop filter 12 Figure 2-9. The PFD/CP/LF 13 Figure 2-10. The step response of the PFD/CP/LPF combination 13 Figure 2-11. VCO transfer characteristics 15 Figure 2-12. LC tank 16 Figure 2-13. A chain of inverters as a ring oscillator 16 Figure 2-14. A ring oscillator with four cells 17 Figure 2-15. The equivalent phase domain LTI model for the generic PLL 19 Figure 2-16. Second-order loop filter schematic 21 Figure 2-17. Magnitude and phase of the open-loop transfer function for a third-order P L L 22 Figure 2-18. Charge-pump PLL 22 Figure 2-19. Long-term jitter 24 Figure 2-20. Cycle jitter , 25 Figure 2-21. Cycle-to-cycle jitter 25 Figure 3-1. The proposed PLL building blocks 27 Figure 3-2. Simplified tri-state PFD schematic 29 Figure 3-3. Phase-frequency detector transfer curve..... 30 Figure 3-4. PFD output characteristic versus input phase error 31 Figure 3-5. Basic structure of a D-FF 31 Figure 3-6. Schematic of a C M L latch 32 Figure 3-7. Current mode logic AND/NAND gate with differential inputs and output 34 Figure 3-8. Differential charge pump schematic 35 Figure 3-9. Common-mode feedback and the loop filter 37 Figure 3-10. Three-stage ring oscillator 40 Figure 3-11. One-stage cell of the proposed oscillator 40 Figure 3-12. Architecture of a divide-by-2 circuit 44 Figure 3-13. Circuit details for a divide-by-2 circuit 45 Figure 3-14. The timing diagram of a divide-by-2 circuit 45 Figure 3-15. The schematic of a divide-by-2/3 circuit 46 Figure 3-16. Divider-by-8/9 schematic 46 Figure 3-17. The signal diagram of dividing by 8/9 divider 47 Figure 3-18. A 32 to 63 divider 48 Figure 3-19. The implementation of a Latch-AND gate 49 Figure 3-20. Divider output timing diagram for N = 42 50 v Figure 4-1. Bode diagram of the open loop transfer function 53 Figure 4-2. Closed loop step response of the PLL 54 Figure 4-3. Output phase noise of the PLL 54 Figure 4-4. PFD inputs, UP, and D N 55 Figure 4-5. PFD transfer characteristic 56 Figure 4-6. VCO tuning range 57 Figure 4-7. The transient response of the V C O at 1.14GHz 58 Figure 4-8. The transient response of the VCO at 2.25GHz 58 Figure 4-9. Lock-in time transient of the V C O control voltage 59 Figure 4-10. VCO voltage control and the UP signal 60 Figure 4-11. Phase noise of a free running V C O 61 Figure 4-12. The transient response of the major signals in the PLL 62 Figure 4-13. The response of the control voltage of the VCO to the divider control bit switching 62 Figure 4-14. The effect of a 10% increase in supply voltage on the PLL transient response (VDD= 1.98V) 64 Figure 4-15. The effect of a 10% decrease in supply voltage on the PLL transient response (VDD= 1.62 V) 65 Figure 4-16. Eye diagram for the designed PLL 67 Figure 4-17. The magnified eye diagram 67 Figure 4-18. Layout of the entire PLL including the LF 68 Figure 4-19. Post-layout simulation result for the VCO control voltage 69 Figure 4-20. Post-layout simulation results for PFD signals 69 vi List of Abbreviations PLL Phase-Locked Loop V C O Voltage-Controlled Oscillator LF Loop Filter PD Phase Detector PFD Phase/Frequency Detector CP Charge Pump CMFB Common-Mode Feedback CMOS Complementary Metal-Oxide-Silicon C M L Current Mode Logic SCL Source-Coupled Logic FF Flip-Flop IC Integrated Circuit IEEE Institute of Electrical and Electronics Engineers VLSI Very Large Scale Integration DSL Digital Subscriber Line LTI Linear Time Invariant C M Common-Mode P M Phase Margin RF Radio Frequency vii Acknowledgments Iwant to begin my acknowledgments by expressing my deepest thanks to God. I feel very lucky to have had the opportunity to study this world from an engineering perspective and to find out what an amazing place it is. I feel blessed by God to have met many people at UBC who have made my life and my graduate studies such a rewarding experience. First, I would like to thank my research supervisor, Dr. Shahriar Mirabbasi, for his continued support, encouragement, and help. He has been a great friend and research advisor for me. It has been a great privilege to be a part of his group. Also, I would like to thank Professors Andre Ivanov and Steve Wilton for serving on my committee. I would also like to extend my grateful thanks to Dr. Hormoz Djahanshahi for his support and useful technical discussions. I would like to express my deepest appreciation to my wonderful family for their never-ending support and help. I will forever be indebted to my parents for their unbelievable love and patience. I am very grateful for all they have done for me. I would like to express my heartfelt gratitude to my lovely friends, Victor Aken'Ova, Bahar Hakimzadeh, Sara Forghanizadeh, Samad Sheikhaei, Jesse Chia, A l i Faghfuri, and Dipanjan Sengupta who have been there to share in many good times. This thesis would not have been possible without their admirable support. I was lucky to meet many talented and interesting people in the System-on-Chip Lab. My sincere appreciation goes to all of the SoC members. Last, I would like to thank Roberto Rosales for all his support and willingness to help. I also wish to thank Roozbeh Mehrabadi for C A D support and Sandy Scott for her administrative assistance in our lab. This research was supported by NSERC. viii Dedicated to those who had the talent but never got a chance ix Chapter I. Introduction Chapter 1 Introduction 1.1. Motivation The concept of phase locking was invented in the 1930s [1]. Phase locking is a powerful technique that have become ubiquitous in many communication and computing applications. Phase-locked loops (PLLs) are widely used in a variety of applications, including clock generation and skew compensations in microprocessors, clock and data recovery systems, and synchronization. For example, in fiber optic data transceivers [2], disk drive read channels [3], local area network transceivers [4], and DSL transceivers [5], PLLs are used as clock and data recovery systems. In some other applications such as the Internet, de-skewing PLL clock generators for microprocessors, DRAMs [6, 7, 8], and clock generators for network routers [9], the PLL-based circuits are used as the clock synthesis blocks. In addition to the above applications, PLL-based frequency synthesizers are used in local oscillators for RF or microwave transceivers [10]. In recent years, increasing demands for affordable high performance communication devices, in particular in mobile systems, have driven the development of high-speed, low cost, 1 Chapter I. Introduction and low-power circuits in CMOS technology. This is mainly due to the fact that CMOS process facilitates the integration of analog and digital circuits on the same chip. A major technique to reduce the power consumption of a CMOS chip is the use of low-swing signaling [11, 12, 13]. This thesis focuses on the design and simulation of a low-swing wide tuning range charge-pump PLL. Among different PLL topologies, charge-pump PLLs are more commonly used due to their advantages over other approaches. These advantages include a wide capture range, small static phase error, amenability to integration, and higher accuracy [14]. To improve the power consumption and speed of operation of this PLL, fully differential low-swing architecture is used. The PLL is designed and simulated in a 0.18pm CMOS technology. The differential structure further improves the robustness of the circuit in the presence of the power supply and common-mode noise. In addition, due to the low-swing nature of the internal PLL signals, the magnitude of the induced noise on the power supply is small. In order to minimize the area (and consequently the size) of the design, it is decided to avoid using any inductors. Therefore, a non-LC ring oscillator is used. Another benefit of using ring oscillators (as compared to LC oscillators) is their wider tuning range which has been taken advantage of in this design. In this thesis, the design of a low-swing, wide tuning range charge-pump PLL is presented. 1.2. Overview of Previous Designs Table 1 summarizes the performance of the previously published works in full swing PLL design in different CMOS technologies. As Table 1 shows, integrated PLLs with LC oscillators typically require a larger area. They also have a smaller frequency tuning range and a better jitter 2 Chapter I. Introduction performance. On the other hand, PLLs with ring oscillators occupy smaller area and have a wider tuning range at the expense of a poor jitter performance. Table 1. Performance comparison of the proposed PLL with other designs Reference • Number VCO type Technology (urn) Operating Frequency Range (GHz) Power Consumption (mW) Supply Voltage (V) Phase Noise/Jitter Area (mm2) [15] LC 0.18 4.7-5.3 29.9 1 -96.3dB @10MHz NA [16] LC 0.12 2.1-2.7 32 1.2 0.74ps @2.7GHz 0.7 [17] LC 0.25 5.35-5.64 23 1.5 -88dB @40kHz NA [18] Ring 0.13 0.03-0.65 7 1.5 1.7% of the Period 0.182 ' [19] Ring 0.25 0.2-2 10 2.5 28.89ps @2GHz 0.028 [20] Ring 0.35 0.13-1.02 4.59 1.8 11 Ops @1.02GHz 0.16 [21] LC (CML) 0.18 2.4-2.4835 22 1.8 -125dBc @lMHz NA The Proposed Design Ring (CML) 0.18 1.14-2.25 14.5 1.8 14ps @2.25GHz 0.023 1.3. The Proposed PLL Design Overview The proposed PLL is a charge-pump PLL that is intended for low-cost low-power high-speed applications. The PLL uses an input frequency reference of 35MHz (although it remains operational if the reference frequency is chosen between 25 and 40MHz). The P L L uses a divide ratio in a range of 32 to 63 with a five-bit control. A tri-state phase-frequency detector in current-mode logic is designed. A differential charge pump topology is used to compensate for any signal variations. The V C O is a ring oscillator with a frequency range of 700MHz to 4 GHz. A l l 3 Chapter 1. Introduction of the internal signals of the PLL, with the exception of the V C O control voltage, are low swing and differential with about IV peak-to-peak differential voltage swing. The PLL operates from a 1.8V supply and consumes less than 14.5mW. The complete PLL including its loop filter occupies 0.023mm2 of which loop filter capacitors account for 76% of the total area. To analyze the transient time behavior, the PLL circuit is simulated at its two extreme frequencies, the maximum frequency of 2.25GHz, and the minimum of 1.14GHz. This thesis is organized in five chapters. Phase-locked loop fundamentals are described in Chapter 2, including the basic concepts of charge-pump PLLs, the loop dynamic, and a general description of PLL building blocks. Chapter 3 presents the design of the entire PLL, including all of its internal components. Chapter 4 and Chapter 5 explain the simulation results of the V C O and PLL and the conclusion and future work, respectively. 4 Chapter 2. Phase-Locked Loop Fundamentals Chapter 2 Phase-Locked Loop Fundamentals Phase-locked loops are an integrated block of many communication and computing applications. A generic block diagram of a PLL is illustrated in Figure 2-1. A PLL is essentially a feedback system that synchronizes its output signal with its input reference signal by minimizing the phase difference between these two signals. In general, PLLs consist of a phase detector1 (PD), a loop filter (LF), a voltage-controlled oscillator (VCO), and two optional dividers, one in the feedback path and the other in the input path as an input divider. Although, the entire PLL or each component can be implemented in the digital domain, but analog PLLs are preferred in high frequency applications. fin PD • LF • VCO r -> f 1 ou H-N Figure 2-1. Block diagram of a generic P L L ' Some applications use phase frequency detectors (PFDs). 5 Chapter 2. Phase-Locked Loop Fundamentals The reference signal is generally produced by a crystal oscillator due to its low phase noise and high accuracy. A phase detector compares the phases of the reference signal (Vj n ) and the feedback signal (Vfb) (Figure 2-1) in order to generate an error signal that is used to adjust the frequency of the V C O until the phases are aligned. To suppress the high-frequency components of the PD output and prepare the control voltage of the VCO, the PD output must be filtered through a LF. The output frequency of the VCO is then adjusted based on the value of its input control voltage. The output frequency may be divided down by a frequency divider in the feedback path. The frequency divider in the feedback path is usually a programmable divider that allows the output frequency to fall within the reference frequency. The division ratio of this divider can be either an integer or a fractional number. As illustrated in Figure 2-1, there could be another divider (with divide ratio of M) at the input of the PLL to set the reference frequency *sfref=finput/M[22,23]. When a PLL is in lock, the negative feedback adjusts the average value of the V C O control voltage so that the two inputs of the PD have a constant, ideally zero, phase difference, i.e., they have the same frequency [24]. A popular class of PLLs, particularly in integrated applications, is the charge-pump PLL. In these PLLs, a charge-pump is included in the forward path of the PLL, as illustrated in Figure 2-2. This class of PLLs is capable of accurately tracking the input phase [25]. A charge-pump PLL is typically composed of a PD or phase-frequency detector (PFD), a charge-pump (CP), a LF, a VCO, and a frequency divider. 6 Chapter 2. Phase-Locked Loop Fundamentals Reference Clock PD/PFD CP LF VCO Output Clock Figure 2-2. Block diagram of a charge-pump PLL In this chapter the building blocks of a PLL and the basic PLL dynamics are briefly reviewed. The following sections explain the different building blocks of the charge-pump PLL, followed by the loop characteristic explanation of a CP PLL. Section 2.1 explains the building blocks of the phase or phase/frequency detector. Section 2.2 presents the general overview of the charge-pump, the common-mode feedback, and the loop filter. Sections 2.3 and 2.4 describe the voltage-controlled oscillator operation and the frequency divider building block, respectively. Section 2.5 describes the charge-pump loop characteristic. Finally, jitter in PLLs is briefly reviewed in Section 2.6. 2.1. Phase or Phase/Frequency Detector A phase detector compares the phase of its two input signals and generates an output signal whose average value is proportional to the phase difference between the two inputs (Vout a A ^ ) . In the ideal case, the relationship between Vow and A0 is linear, and the constant of proportionality, KPD, is referred to as the gain of the PD (Figure 2-3). 7 Chapter 2. Phase-Locked Loop Fundamentals out Figure 2-3. Definition of a phase detector One of the most common phase detectors is the XOR detector, which is not suitable for this application. An XOR PD has the disadvantage of possible locking on the harmonics of the reference signal because its output frequency can vary by a factor of more than two. To avoid this, the VCO must not send any harmonics of the chosen operating frequency, and its two inputs should be close enough. Additionally, the XOR phase detector is fairly insensitive to frequency differences of its inputs, and in the presence of a large frequency difference between its two inputs, it cannot generate the proper output, and so the PLL could fail to lock. This problem is called an inadequate acquisition range of the PLL [24] and can be ameliorated by using a PFD instead of a PD. Furthermore, XOR PD circuits produce error pulses on both edges (rising and falling), but other types of PDs may generate a pulse error only on one of the edges, which means that a 50% duty cycle is not necessary. The PFD circuit generates three states according to its response to the rising or the falling edges of its two inputs. Consider that both outputs, Outl and Out2, are low (Figure 2-4), and are called UP and DN respectively in a PFD. A rising edge on INI leads to Outl=l, and Out2=0. The circuit will keep this state until a rising edge occurs on IN2, and consequently it forces the Outl to become low. The same procedure is considered for IN2. 8 Chapter 2. Phase-Locked Loop Fundamentals flNl ^ flN2 INI JTJT_rLTL IN2 Outl Out2 (a) *> Outl (UP) >• Out2 (DN) flNl ~flN2 I N 1 ^1JTJTJT IN2 Outl • • i • • • • • J L J L J L J L Out2 (b) Figure 2-4. In figure (a), there is a difference between the frequencies of two signals, but in figure (b), both frequencies are equal, although they have a phase difference In Figure 2-4 (a), the frequencies of the two inputs are equal, but INI leads IN2. The PFD produces a series of pulses on Outl that is proportional to (PINI-(PIN2, and Out2 remains zero. In Figure 2-4 (b), the two inputs have unequal frequencies, and INI has a higher frequency than IN2, and Outl generates pulses when Out2 is zero. The dc value of the outputs provides information about the phase difference or the frequency difference between the two inputs. A tri-state PFD is a good choice, because it locks only at the fundamental frequencies of its input. Figure 2-5 depicts a simplified implementation of a standard tri-state PFD consisting of two edge-triggered and resettable D-flipflops (D-FFi and D-FF2). The inputs of both D-FFs are connected to VDD- The reference clock (CK r ef) and the feedback clock (CKft) act as two inputs (the same as INI and IN2 in Figure 2-4) for the PFD. 9 Chapter 2. Phase-Locked Loop Fundamentals v ref uu 4-DFF1 Reset uu t_J» UP DFF2 DN Figure 2-5. A conventional tri-state PFD The state diagram of the tri-state PFD is shown in Figure 2-6. Initially PFD is in "State-II". On the rising edge of reference clock (Clk r ef), UP becomes one and PFD goes to State-I. The PFD remains in this state until another edge occurs on the feedback signal (Oka) and causes a transaction to State-II and therefore, forcing the UP signal to return to zero and takes PFD to "State-II." In this diagram, it is important to consider the frequency difference between the reference and feedback signals. The final state of the operation of the PFD is toggling between "State-II" and "State-I." To clarify, consider the case that the feedback frequency is smaller than the reference frequency, then there is a time interval during which two edges of Clk r e f take place between two edges of Clkft. Figure 2-6 shows that PFD leaves "State-Ill" and toggles between "State-I" and "State-II" [26, 27]. State-Ill State-II State-I V f b=high y v y r e f = high V f b=higri V r e f=high ^ Vfb=high Figure 2-6. Tri-state PFD state diagram V r e f = high 10 Chapter 2. Phase-Locked Loop Fundamentals When both UP and DN signals are high, both registers will be reset through the A N D gate. The reset signal stays high until both UP and DN have gone low again. If a simple A N D gate is used to produce the reset signal, sufficient delay should be added in the reset path to make sure that the reset signal stays high long enough to satisfy the hold time requirements of both D-2.2. Charge-Pump and Loop Filter The charge-pump circuit consists of two switches driven with UP and DN signals that are produced by the PFD (Figure 2-7). The charge pump draws the current into or out of the loop filter. At the rising edge of the UP signal, the charge-pump forces a current into the loop filter. Similarly, when the reference signal operates at a lower frequency than the feedback signal, D N rises. At the rising edge of DN, the charge pump sinks the current out of the loop filter. The combination of the charge pump and the loop filter generates the average output of the PFD (UP - DN) that is used to adjust the frequency of the V C O oscillation. FFs. v, Figure 2-7. Simplistic charge-pump circuit 11 Chapter 2. Phase-Locked Loop Fundamentals One major drawback in a single-ended charge pump structure is the leakage problem [28]. When a pulse from the PFD turns one of the switches OFF from its ON position, the charge stored in the channel of the switch transistor escapes to its nearby nodes, shown by the dashed lines in Figure 2-7. Consider the PMOS switch (UP) in Figure 2-7, half of the charge is injected to the parasitic capacitor at the source of the switch, and the other half is injected to the loop filter. When UP forces the PMOS switch to be OFF, this additional charge is added to the loop capacitor (C), which is an undesirable effect. Differential charge pump topology is used to provide an additional path for this extra charge, as shown in Figure 2-8, by adding the complementary inputs. When the UP switch is closed, the current path exists for the extra charge between the current source (Ic) and the charge pump to function exactly like a normal charge pump. A PFD, a single-ended CP, and a loop filter (Figure 2-9) are modeled as a linear continuous time system. In a real system, a PFD acts as a pulse modulator and drives the charge pump for the duration of a pulse width, which is related to the PFD input phase difference (Figure 2-10). The output of the PFD, named UP, forces the current into the loop filter and causes the V C O control voltage to rise. As illustrated in Figure 2-10, when UP and DN are equal DN 'CP Figure 2-8. Differential charge pump with a loop filter 12 Chapter 2. Phase-Locked Loop Fundamentals to zero, Si and S2 are off, and V o u t remains constant. If UP is high and D N is low, then Ii charges the C p . On the other hand, if UP is low and DN is high, I2 discharges C p . CK„, a u • Q ) UP DFF, VCO Control Voltage V-Figure 2-9. The PFD/CP/LF DN UP "ctrl % F D . I c p .F(sM • t Figure 2-10. The step response of the PFD/CP/LPF combination The time during which the UP or DN signals are high determines the amount of current that gets delivered to the loop filter. The difference between the reference and the feedback signal phases can be shown as: A(t> = (t>ref-<t>ih (2-1) 13 Chapter 2. Phase-Locked Loop Fundamentals The PFD outputs go high on the leading edge of their related clock inputs and remain high until the reset signal makes them low. The time during which the outputs are high, thigh, which is related to the phase error, A ^ , can be shown as [29]: lMgh ~ „ ( 2 - 2 ) ^ref The open loop transfer function of the PFD/CP/LF combination, illustrated in Figure 2-10, can be expressed as: V„ Ctrl (s) = KPFD.ICP-F(s) ( 2 - 3 ) where KPFD is the PFD gain, Icp is the charge pump current, and F(s) is the transfer function of the loop filter. 2.3. Voltage-Controlled Oscillator An oscillator is a system that generates a periodic output signal without any input. Voltage-controlled oscillators (VCOs) are tunable oscillators that are widely used in PLLs. Their output frequency is a function of their input control voltage, as depicted in Figure 2-11, and can be expressed as: ®out=<»0+KVCOVctrl ( 2 - 4 ) where coo represents the centre frequency of the V C O and Kvco denotes the conversion gain of the oscillator that is the slope of the linear region [24]. Ideally, for a linear analysis, K V co should be constant. Kvco and the achievable frequency range, ©2 - coi, is called the V C O tuning range, as shown in Figure 2-11. 14 Chapter 2. Phase-Locked Loop Fundamentals J. i S • V v, v 2 Figure 2-11. VCO transfer characteristics The V C O has a fundamental role in defining the desired range of operation of a PLL because all of the PLL building blocks, except VCO, are operating over a wide frequency range, and the V C O is the only limiting block. A V C O is usually considered as a linear time-invariant system, with the control voltage as the input of the system and the excess phase of the output signal as the output of the system. This output phase can be written as: §0UM) = KVC0\Vc!rldt (2-5) The V C O input/output transfer function is: §oUt(s) _ Kvco y«<?)~ * ( ' Equation (2-5) shows that to change the output phase, we must first change the frequency, Which lets the integration take place. The above equations reveal that the output phase of the VCO cannot be determined only from the present value of the control voltage, but that is also depends on the history of V c t r i . Two chief topologies are used in the design of VCOs: LC-Oscillator and the ring oscillator. LC-oscillators oscillate at the resonant frequency (GDO) of the inductor and the capacitor, given by co0 = \j^LC. An LC tank filters out frequencies away from the resonant peak, which improves the phase noise performance, particularly with a high-Q tank (Figure 15 Chapter 2. Phase-Locked Loop Fundamentals 2-12). The advantage of the LC-oscillator is its good phase noise performance because of the energy storage nature of the inductor and the capacitor, which greatly limits the amount of energy added by other active devices. In spite of their good phase noise response, their tuning range is very limited. Also, the LC-oscillator topologies do not provide quadrature outputs by nature. Quadrature outputs are four output signals with four different phases that are apart of each other by 45° as shown in Figure 2-14. The second topology is the ring oscillator, which contains a ring of inverters with a net inversion in the feedback path, as illustrated in Figure 2-13. The frequency of the ring oscillator VCO is inversely proportional to the propagation delay of each inverter (tj) and the number of the inverters (N) can be written as f0 = l/2Ntd . To tune the V C O frequency, the propagation delay of each inverter can be adjusted. The propagation delay of each inverter is small, which increases the maximum output frequency of the ring oscillator. The other reason for their wide tuning range is that the current through each stage can be varied in several orders. In the single-ended ring oscillator topology, there are an odd number of inverters. Figure 2-12. LC tank Figure 2-13. A chain of inverters as a ring oscillator 16 Chapter 2. Phase-Locked Loop Fundamentals With differential signaling, a ring oscillator can be built with an even number of inverters by flipping the output of the last stage, which is fed back to the input of the first stage. Ring oscillators can produce quadrature outputs by their nature. For example, by using four stages as a ring oscillator, quadrature outputs can be produced (Figure 2-14). Figure 2-14. A ring oscillator with four cells Although they have a good tuning range, their phase noise is poor. As described in [30], in a ring oscillator, the transistors have to provide all the energy that is necessary to charge and discharge the node capacitances in each cycle because there is no storage element in a ring oscillator. Therefore, ring oscillators can improve phase noise performance by consuming more power. Compared to LC-oscillators, ring oscillators have a very wide tuning range determined by current variation, an inherent ability to produce quadrature outputs, poor phase noise, and their power, which can vary greatly due to the trade-offs between the power and the phase noise. LC-oscillators have a narrow tuning range and a very good phase noise. They consume too much power and do not have the inherent ability to produce quadrature output [30]. In this thesis, a ring oscillator has been chosen because of its wide tuning range. Generally, they also occupy a smaller chip area compared to integrated L C oscillators [31]. 17 Chapter 2. Phase-Locked Loop Fundamentals 2.4. Frequency Divider The PLL reference signal is produced by a crystal that operates from between tens of kHz to a few hundred MHz. The PLL output signal generated by the V C O operates at a few GHz. To compare the reference signal with the V C O output signal, a frequency divider is necessary in the feedback path from V C O output to the PFD input in order to produce a low frequency programmable signal from a high frequency signal. This frequency division can be done using an analog frequency divider [32] or a digital counter [33, 34]. Due to the resonant nature of the analog dividers, they are less noisy than the digital ones. However, digital dividers are capable of providing large and programmable division ratios. In this work, a digital divider has been chosen for this reason. Chapter 3 provides a detailed description of the divider design. 2.5. Charge-Pump Loop Characteristics This section deals with the dynamic behavior of a low-swing charge-pump PLL. A PLL is a system with a memory that requires a finite time to respond to its input changes. In addition, the dimensions of the variable of interest change around the loop. Furthermore, under the lock condition, the output frequency is equal to the input frequency, regardless of magnitude of the loop filter [24]. It is a common practice to analyze the behavior of the PLL near its lock condition by Using a linear time invariant (LTI) model, as shown in Figure 2-15. The transfer function of this linearized PLL model can be expressed as: 18 Chapter 2. Phase-Locked Loop Fundamentals Divider he! PFD LF V C O V F(s) V Divider Figure 2-15. The equivalent phase domain LTI model for the generic PLL H(s) = = KPFDKVC0F{s)lM = N/M <LM s , KPFDKVC0F^j ] | s (2-7) N (0LPF where K P F D is the gain of the PFD, K V co is the VCO gain, and F(s) is the loop filter transfer function. The exact nature of the transfer function in Equation (2-7) is determined by the loop filter transfer function. The order of the loop filter determines the speed and the transient behavior of the P L L response. In its simplest form, F(s) could be a constant, representing gain or attenuation. In that case the loop is a first-order system. In a first-order loop, to have a lower steady-state phase error, the loop bandwidth should be increased. High-order loops are more common because they are not limited by this strong coupling between the bandwidth and the steady-state phase error of the first-order loop, as shown in (2-7) [25]. Many applications use a low-pass filter for F(s) to add another pole to the system. This extra pole allows more flexibility in the design of the PLL. One capacitor (F(s) =l/Cs) is not a good choice as a LF. It adds one pole in origin, which makes the PLL unstable. To guarantee system stability, a compensating network that is typically a zero should be added to the filter. One of the most common loop filters has a pole at the origin and a zero at a frequency, coz, just below the unity gain frequency of the PLL loop (Figure 2-17). In this case the transfer function of the loop filter can be written as: 19 Chapter 2. Phase-Locked Loop Fundamentals / t O - i t i i (2-8) Consider: K = KVCOKPFD (2-9) By substituting F(s) (2-8) in (2-7), the new transfer function is achieved as: W s2 +(KXZ/N)S + (K/N) V ' The resulting PLL transfer function in (2-10) is a second-order system that is characterized by its natural frequency, con, and its damping factor, ^. A second-order transfer function can be rewritten with its natural frequency and damping factor as: / \ 2bta„s + (02„ H®=-rr£—rr ( 2 " n ) 5 +2t>(dns + can A comparison of the resulting transfer function with (2-11) shows that the natural frequency and the damping factor can be expressed as: CD„ = JK/N ( 2 _ 1 2 ) % = ^4K/N (2-13) The loop filter is used to set the appropriate unity gain frequency and guarantee stability when the other important parameters such as the gain of the PFD, the V C O gain, and divider ratio have been chosen. The open loop gain of the LF should be kept as small as possible to reject the noise that is added within the loop. It can be achieved by a second-order filter with a pole at DC, a zero before the unity gain frequency, to provide an adequate phase margin, which is one of the key parameters for measuring the stability, and a second pole after the unity gain frequency to help improve the high frequency rejection. Figure 2-16 and Figure 2-17 show the 20 Chapter 2. Phase-Locked Loop Fundamentals loop filter schematics and the magnitude and the phase of the open-loop transfer function, respectively. The damping factor is a measure of stability. An increase in the damping factor of the PLL allows both poles of the PLL will move into the left-hand plane to make sure that the PLL is stable. For optimum settling time and no peaking in the frequency response,^, damping factor is chosen as 0.7 [24]. Noise can be filtered by adjusting the loop bandwidth and peaking in the frequency response based on the dominant noise source [35]. Because of the direct relation between the "zero" time constant and the loop damping factor, adjusting one of them will adjust the other. 'IN Vctrl Figure 2-16. Second-order loop filter schematic 21 Chapter 2. Phase-Locked Loop Fundamentals |HO D e n(s)l -180' -40dB/dec Figure 2-17. Magnitude and phase of the open-loop transfer function for a third-order PLL The transfer function of the loop filter in Figure 2-16 can be written as: Z(s)- {RCs + l) (C + C')s{R{c\\C')s + l) (2"14) In a charge-pump PLL (Figure 2-18), the open-loop transfer function (FT(s)) is: Reference Clock PFD CP ^P-Zi!*? 'CP F I T I F(s) VCO ^ v c o / ' s Output Clock Divider Figure 2-18. Charge-pump PLL 22 Chapter 2. Phase-Locked Loop Fundamentals where a>_ = ,co. - RC p3 1 R{C\C) and a>c are zero frequency, third pole frequency, and the open-loop unity gain frequency, respectively. The resistor and the capacitors of the loop filter should be chosen carefully so that they can filter the high-frequency portion of the signal, maintain the stability of the loop, and not produce extra noise. Another major parameter for stability measurement is phase margin. For phase margin calculation, the Equation (2-14) can be rewritten as: Z{s)- m xs + 1 m + 1 (2-16) where x = RC, and m = C / C . Also: H'{s)~ KVC0ICPKP < m ^ \m +1 j XS + 1 s2C\ xs m + 1 + 1 (2-17) The phase margin (PM) for a third-order P L L can be approximated with [36, 37]: PM = tan '(xac)-tan ' f xoic ^ \m +1 j (2-18) where coc is the crossover frequency shown in Figure 2-17. The maximum phase margin is only a fraction of the loop filter capacitors (C and C ) . The 'm' value greater than one is desirable in order to have a stable loop, which forces the phase margin to be greater than 20. Typically'm' is considered around 10 or 20 to achieve a stable loop [24]. 23 Chapter 2. Phase-Locked Loop Fundamentals 2.6. Jitter in P L L s Jitter is defined as the deviation of the significant instances of a signal from its ideal location in time. The significant instances in a signal are typically chosen to be the transition points (zero crossing of the signal). In other words, jitter shows how early or late a signal transition happens with respect to the expected transition time [52]. Jitter can be specified in a time unit (e.g., pico-seconds) or a percentage of the time period. There are three main measures for the jitter: long-term jitter, cycle jitter, and cycle-to-cycle jitter [38]. Long-term jitter is the maximum change in a clock's output transition from its ideal position, over many cycles. In other words, the long-term jitter is the accumulated jitter over time, as shown in Figure 2-19. The time point of the n"1 negative-to-positive zero crossing of the output of the PLL in the steady state is referred to as tn, and the n* period is defined as T n = tn+i-tn- For an ideal PLL, this time difference is independent of n. But in reality, it varies with n as a result of jitter in the circuit. This variation results in a deviation AT„ = T„-T from the mean value of the period, T [43, 52, 38]. Long-term jitter is the accumulated value of ATn over time, which can be expressed as: N Long-term j itter = ^  ATn (2-19) Ideal Reference Oscillator Output >u j Long-term Jitter Figure 2-19. Long-term jitter 24 Chapter 2. Phase-Locked Loop Fundamentals A better measure of jitter for the P L L and especially for the VCO is the cycle jitter, which is defined as the rms value of the timing error ATn. Cycle jitter describes the magnitude of the period fluctuations and is written as (2-20). Figure 2-20 illustrates the cycle jitter diagram. Ideal Cycle A r Figure 2-20. Cycle jitter The third type of jitter considered here is the cycle-to-cycle jitter, which represents the rms value of the difference between the two consecutive periods, as shown in Figure 2-21. In other words, the cycle-to-cycle jitter is the change in a signal transition time compared to its corresponding position in the previous cycle. This jitter is expressed as: A74=hm . ^ { T ^ - T j (2-21) T+t, T+t, t^t^Cyde-to-cycle Jitter Figure 2-21. Cycle-to-cycle jitter 25 Chapter 2. Phase-Locked Loop Fundamentals The cycle jitter compares each period with the mean value of the periods, while the cycle-to-cycle jitter compares each period with the preceding one. Therefore, cycle-to-cycle jitter describes the short-term dynamics of the time period [43]. 26 Chapter 3. Phase-Locked Loop Design Procedure Chapter 3 Phase-Locked Loop Design Procedure The block diagram of the proposed PLL that is intended for high-speed low-power application is shown in Figure 3-1. A 35MHz crystal produces the input reference frequency. A programmable divider in the feedback path produces the 32 to 63 division range through a 5-bit control inputs. The resolution step size is around 30MHz, controlled by a divider in the feedback path. This PLL has been designed and simulated in a 0.18 pm CMOS technology with a 1.8V supply. The total power consumption is less than 14.5mW, and it takes less than 700ns for the PLL to lock to the desired frequency. Table 2 summarizes design specifications. Reference Clock ~* Control Voltage PD/PFD CP+ CMFB LF 3-Stage VCO Divider 5-bits Control Output Clock Figure 3-1. The proposed PLL building blocks 27 Chapter 3. Phase-Locked Loop Design Procedure Table 2. Design specifications Input reference frequency 35MHz Output frequency 1.14GHz-2.25GHz (31 steps) Lock time < 700ns Power consumption 14.5mW Process technology TSMC 0.18pm CMOS Supply voltage 1.8 ±0.18 V Low-swing signaling is used through the PLL to enhance its speed as well as the power consumption. The designed voltage-controlled ring oscillator (VCO) is operational in the frequency range from 700MHz to 4GHz. Due to the C M L implementation of the low-swing PLL; at the frequency range of PLL operation (1.14GHz to 2.25GHz) the static power consumption of the PLL is lower than the standard CMOS implementation. In lower frequencies, the C M L , which has a constant power that is relatively independent of its frequency of operation, may consume more power than standard CMOS. But at higher frequencies, the power consumption of the standard CMOS will also increase. In C M L logic circuits, a constant current passes through the cells, which produce less noise on the power supply. On the other hand, the CMOS standard circuits work on the basis of the current switching. In the same coupling situation, the low-swing C M L logic circuits produce a smaller amount of noise on the power supply. This noise contribution can be measured by the IR drop technique. This chapter discusses the building blocks of this fully differential PLL. Section 3.1 explains the design of the phase-frequency detector. Section 3.2 discusses the design of the 28 Chapter 3. Phase-Locked Loop Design Procedure charge-pump circuit, including common-mode feedback along with the loop filter implementation. Sections 3.3 and 3.4 present the V C O and the divider, respectively. 3.1. Phase/Frequency Detector Circuit Figure 3-2 depicts a simplified schematic of the PFD. As mentioned before, the rising edge of the reference voltage (V ref) sets the output to UP, and the rising edge of the feedback signal (Vfb) (output of the divider) sets the output to DN. Phase error is obtained by comparing the widths of the UP and DN pulses. Once both UP and D N are high, the "Reset" signal through the delay path resets both registers. The reset stays high until both outputs of the registers go low again. uu DFF1 Reset uu U P DFF2 DN Figure 3-2. Simplified tri-state PFD schematic The error signal is the difference of the averages of the UP and DN signals. If the reference input is ahead of the feedback signal, the frequency of the V C O will increase to reduce the phase error between the two signals. Therefore, when the reference phase (0 r e f) is ahead of 29 Chapter 3. Phase-Locked Loop Design Procedure the feedback phase the width of the UP pulse increases, given that <|>re/ -<t>yt| < 2%. Also, when <j)ref - <f>fb (neglecting the narrow pulses in Figure 2-4(b)), the output is low [31]. Figure 3-3 illustrates the transfer characteristic of the PFD. It shows that the output varies symmetrically as the phase difference changes around zero. The slope of this transfer function represents the PFD gain that is VJ2n. Figure 3-3. Phase-frequency detector transfer curve As shown in Figure 3-2, the main building blocks in a PFD are two D-flip flops (D-FFs) and the AND gate. Combined with the charge pump, the PFD potentially suffers from a dead zone in its transfer characteristic, as shown with the solid line in Figure 3-4. If the phase difference between the input and the output varies within the dead zone area, the dc output of the charge pump does not change significantly and the loop fails to correct the resulting error; therefore, a peak-to-peak jitter equal to the dead zone width arises in the output [31]. The dead zone, which is due to the inherent delay in turning on charge pump currents, directly translates to a peak-to-peak phase jitter in the PLL [39]. In other words, if the delay through the reset path is shorter than the delay to the charge pump, which the PFD is driving, then the charge pump will not get switched even though there is a phase error present. To eliminate the dead zone, the delay of the reset path of the PFD should be increased. Including the proper amount of delay results in 30 Chapter 3. Phase-Locked Loop Design Procedure the dashed line in Figure 3-4. Subsection 3.1.1 and 3.1.2 explain the design of the D-FF and the design of the C M L AND gate. V o u , i v„ *)y / y / y i i // / y \ -2 JI ^ i i y^ • / s i yy / ' y / -v„ Figure 3-4. PFD output characteristic versus input phase error 3.1.1. D-Flip Flop Circuit Figure 3-5 shows the basic structure of a D-FF, which consists of two cascaded latches. The clock input for the second latch is the inverse of the clock input for the first one. Q D g Latch Q Latch Q A Figure 3-5. Basic structure of a D-FF The building blocks of the PFD are designed using differential C M L , also known as source-coupled logic (SCL), blocks. This logic family of circuits is fully differential and has two main benefits over other logic families such as the standard static or dynamic CMOS logic. First, C M L can be used at high speed partly because only NMOS devices are used. Second, the current 31 Chapter 3. Phase-Locked Loop Design Procedure through the logic gates is constantly dictated by the constant tail current, even when the differential output is switching, leading to less noise on both the power supply and the substrate [31, 40]. In addition, for high operating frequencies, C M L has lower power dissipation than rail-to-rail logic [41]. One disadvantage of the C M L circuit is its static current, which causes higher power consumption. In this work, at low frequencies, the number of the C M L gates used in low frequency blocks (e.g., PFD) has been minimized to limit their power consumption. Figure 3-6 shows the differential C M L latch structure. This kind of structure employs positive feedback, which is realized using a cross-coupled NMOS differential pair. The latch consists of an input pair ( M 1 - M 2 ) for sensing (tracking) the input and a regenerative pair ( M 3 -M 4 ) , for storing the state. The track and store modes are established by the clocked transistor pair, M 5 - M 6 . When C L K is high, the tail current is steered to the input pair, allowing the output voltage to track the input voltage, while M 3 and M 4 are turned off. When C L K is low, in the transition to the store mode, M i and M 2 are off, and the cross-coupled pair can store the output levels on the output nodes [37]. Reset signal is connected to the outputs through M 7 and Mg,. VDD R R-Qb High CLK I Reset ! s e H [ 3PW CP CLKb Figure 3-6. Schematic of a CML latch 32 Chapter 3. Phase-Locked Loop Design Procedure There are three steps in designing such a latch. First, the tracking amplifier should be designed to have a moderate gain of around 2. Second, for simplicity, cross-coupled devices should be sized the same as the transistor sizes in the tracking stage. Third, the clock transistors should be chosen roughly 20% larger in width compared to the other transistors because they will be in the triode region of operation and have a lower drive capability [37]. There are several options for the load of the C M L logic, including resistors, diode connected PMOS or NMOS transistors, and PMOS transistors biased in the triode region. Resistors are used for high-speed applications, but they occupy a larger area. Diode connected PMOS or NMOS transistors are usually used in applications where the area is an important issue, but their speed of operation is low. The other choice for the load is PMOS transistor operating in the triode region. This type of load can be used in high speed applications, but it is nonlinear, and the designer has to make sure that they stay in the triode region. In this work, resistors have been used as the loads. Table 3 shows transistor sizes in the PFD. The resistor loads are 6KQ, each. Table 3. Transistor sizes of the latch block (W/L)!,2 (W/L) 3,4 (W/L)s,6 1.8um/0.18um 1.8um/0.18um 3um/0.18um An important design issue in the low-swing design is the value of the output swing. In particular, when one differential stage drives another one, the second differential stage requires a large enough V D s to stay in the saturation region. The output voltage levels should be carefully chosen such that they can fully switch the subsequent differential stage. 33 Chapter 3. Phase-Locked Loop Design Procedure 3.1.2. AND-Gate Circuit Figure 3-7 illustrates the basic schematic of C M L logic AND gate. Depending on the input and output signal configuration, this structure can be used as an AND/NAND and OR/NOR gate. The chosen arrangement of the input and the output signals in Figure 3-7 is AND/NAND operation such that the gate would perform. When A and B are high, the current flows through R\ and causes the NAND output to become VoD-RiIbias, while the other output, which represents the AND operation, goes to VDD- The output voltage swing cannot be too large because M i and M 2 are in the triode region and the drain-source voltage of the M i and M 2 should be enough to keep them in that region. To achieve a symmetric output waveform in the A N D gate, an NMOS transistor, M 5 , is added, as shown in Figure 3-7 [41]. Figure 3-7. Current mode logic AND/NAND gate with differential inputs and output Sufficient delay should be added in the reset path of the PFD to make sure that the reset signal stays high long enough to satisfy the hold times of both D-FFs and therefore to minimize the dead zone. Two NOT gates (Figure 3-2) has been used in the reset path to provide this delay. Table 4 shows the transistor sizes in the PFD. The resistive loads are equal to 6kQ. 34 Chapter 3. Phase-Locked Loop Design Procedure Table 4 . AND-gate transistor sizes (W/L), , 2 (Vv7L)3,4 (W/L) 5 1.5um/0.18um 2pm/0.18um 1.8um/0.18um 3.2. Charge Pump Circuit The charge pump circuit uses the UP and DN signals as its inputs and controls the amount of current that should be sources or sinked from the loop filter. Figure 3-8 depicts the fully integrated charge pump designed in this system. Since inputs of the charge pump circuit are low-swing signals as opposed to the rail-to-rail, the sizing of the transistors M i to M 4 are carefully chosen so that they can properly be turned off. This charge pump consists of two current mirrors. The PMOS one ( M 5 , M 6 , and M 1 0 ) mirrors Ibias through the UP current (Iup) into the charge-pump (CP). Similarly, there is an NMOS current mirror ( M 7 and M 8 ) to mirror the current bias (Ibias) through the DN current (ID N) Figure 3-8. Differential charge pump schematic 35 Chapter 3. Phase-Locked Loop Design Procedure into the charge pump. Depending on the value of the input signals at the gates of transistors M i to M 4 , the charge pump current is sinked to or sourced from its differential output. ITJP and IDN of the charge pump must be equal to ensure a constant value for the K P F D . The bias circuit shown in Figure 3-8 is used to produce equal UP and DN currents. In a differential charge-pump, the paths for the UP and DN signals should be symmetric. In the PLL's lock mode, the UP and DN signals have narrow pulses. In this case, i f the UP and D N paths are not symmetric, the charge pump's net output current will be non-zero. This non-zero current would generate a drifting ripple on the control voltage and consequently result in a phase error. Even with a perfect adjustment of the UP and D N signals, the net current produced by the charge pump can be nonzero because of the mismatch between the drain currents of M 5 and M 8 (Figure 3-8). The charge-pump UP and D N currents are chosen to be 15pA. Special care has been given to the sizing of M5 and M8 to make sure that these devices stay in the saturation region. The proper VSAT allows a possible 0.45V drop across the switches. Initially the transistor sizes can be chosen using the following equation. Table 5 shows the transistor sizes in the charge-pump, which are optimized through simulation in Cadence. > 21 r V ^ J u C VL "n ox SA1 (3-1) Table 5. The charge pump transistor sizes (W/L) U 2 (W/L) 3, 4 (W/L)5,6,io (W/L) 7 t 8 (W/L) 9,„ 1.5pm/0.18pm 0.8pm/0.18um 8um/0.27um 7pm/0.36um 7pm/0.36um 36 Chapter 3. Phase-Locked Loop Design Procedure 3.3. Common-Mode Feedback (CMFB) Circuit To set the output common-mode voltage of the differential charge pump to the desired dc voltage, a common-mode feedback circuit is used, as illustrated in Figure 3-9 [42]. The output common-mode (CM) level of a differential structure is sensitive to device properties and mismatches. Basically, the common-mode feedback (CMFB) circuit senses the C M level of the outputs, then compares it with a reference and returns the error signal to the charge pump circuit. CMFB Loop Filter M2 H M3 M8 —t  M9 R/2 outl R/2 out2 Figure 3-9. Common-mode feedback and the loop filter Outl and out2 are the two outputs of the charge pump circuit. Ms-io and M1 .3 are NMOS and PMOS current sources, respectively. The reference voltage is equal to twice that of the VQS of the NMOS transistors. If the C M level of the CP output increases, the gate-source voltage of the current source transistors will be increased and, consequently, their current is increased. As a result, the voltage of the outl and out2 nodes drops. Table 6 shows the transistor sizes in the CMFB circuit. A differential to single-ended voltage converter is used at the output of the loop 37 Chapter 3. Phase-Locked Loop Design Procedure filter to generate the control voltage for the VCO because the designed V C O works with a single-ended control voltage. Table 6. The sizes of the CMFB transistors (W/L) 1 > 2 ,3 (W/L) 4, 5 (W/L) 6 ,7 (W/L)8,9,io 4um/0.18um 4um/0.18 urn 3pm/0.27um 3u.m/0.36um 3.4. Loop Filter Circuit Basically, the loop filter circuit attenuates the high frequency components of the charge pump's output. To have a stable loop filter, special attention is given to choosing the loop filter type, as explained and illustrated in Figure 2-16. To have a symmetrical layout topology for the differential low pass filter, the loop filter's resistor is broken into two equal parts (Figure 3-9) each connected to one terminal of C. The resistor R, in series with capacitor C of the loop filter, produces some ripple at the output of the loop filter (i.e., the control voltage of the VCO) that can cause cycle-to-cycle jitter. As a common practice to reduce this effect [42], the capacitor C is added in parallel with the RC filter. For C ' « C, the additional pole due to C is large, and its effect can be neglected. The loop filter's cut-off frequency is usually chosen to be about one tenth or one twentieth of the maximum operation frequency of the PLL. For this loop filter design, one tenth of the reference frequency is used. As mentioned in [36] the phase margin, PM, and crossover frequency, G J c , are where m=C/C\ 38 Chapter 3. Phase-Locked Loop Design Procedure PM - tan 1 ( r a j - t a n " rac \m + \ (3-2) Differentiating (3-2) with respect to coc achieves the maximum phase margin: coc = Jm + l/x (3-3) If we force the crossover frequency to be exactly equal to (3-3), then we get: ^ C m T2 Vm + 1 (3-4) vm + l , The loop filter can be designed as follows: first, the VCO gain should be set. After setting KvcO) the desired P M should be chosen and from (3-2) 'm' can be calculated. Then from (3-3), x should be chosen. C and Icp can be selected such that they satisfy (3-4). The noise contribution of R is calculated. If the calculated value is negligible the design is complete; otherwise, the C value should be changed [36]. In this design C=15pF, C'=3pF, and R=10kf2 have been chosen. 3.5. VCO Circuit One of the challenging building blocks of a fully integrated PLL is the VCO. A major design challenge for integrated VCOs is to have a large tuning range to compensate for temperature and process variations. Ring oscillators are among the popular structures for VCOs due to their wide tuning range and amenability to integration. Despite the fact that they have a relatively poor phase noise performance (as mentioned in Chapter 2), ring oscillators are commonly used in many PLL applications, including wire-line communication, microprocessor clock generation, and wireless systems [43, 44]. In this work, a three-stage differential ring oscillator (Figure 3-10) is used for the VCO. The differential structure of the VCO reduces the common-mode noise effect, which improves 39 Chapter 3. Phase-Locked Loop Design Procedure the system's overall jitter performance. Jitter (phase noise) increases as the number of stages of the V C O increases. The lower the number of stages, the higher the free running frequency of the VCO. The number of stages is typically chosen to be three or four [49]. By dissipating the same total power of the large number of stages in a smaller number of stages, one can achieve a better jitter/phase noise [49]. Hence, three stages are chosen for this design. Control Voltage Figure 3-10. Three-stage ring oscillator This V C O has a single control voltage that is used to set the desired output frequency. Figure 3-11 depicts the schematic of each stage of the V C O [45]. To have a high differential gain, a cross coupled PMOS pair is used as the active load of the differential stage [46]. M, M 2 M 3 M 4 Figure 3-11. One-stage cell of the proposed oscillator 40 Chapter 3. Phase-Locked Loop Design Procedure Equation (3-5) shows the phase shift of each stage in an N-stage ring oscillator. In this design, N is equal to three. This means that the phase shift of each stage is 60°. 2NA0 = 360° ^ A<|> : 180° N (3-5) To the first-order approximation, the transfer function of each stage is: 1 + (3-6) Therefore, the overall transfer function is: L(jm) = 1 + -co (3-7) o J The circuit oscillates if the phase shift of each stage equals 60°. The frequency at which this occurs is given by (3-8). coo and coosc are the 3-dB bandwidth of each stage and the V C O Oscillation frequency, respectively. A low-frequency gain of 2 is needed per stage. tan" = 60° (3-8) = co0j3 ^ A0=2 (3-9) The time constant on each node is calculated in (3-10). CL is the total capacitance at the output node of each stage that includes the drain parasitic capacitances of all of the transistors connected to the output node. The total resistance on each output node is calculated in (3-11). 41 Chapter 3. Phase-Locked Loop Design Procedure T = Ror,3,4,6CL (3-10) v . Kon-—j (3-H) 1D To improve the speed, low-swing architecture is chosen for the VCO. The choice of the output swing is influenced by several factors. There is a trade-off between speed and noise margins. A higher speed needs a lower output swing, while a better noise margin requires a higher swing [47]. In a simple differential pair with resistive PMOS loads shown in Figure 3-11, the gain of the stage is approximately equal to the product of g m and R L , which has an inverse relation with (VGS-VTHN)- According to Equation (3-12), a low swing will require a low (V Gs-VTHN) bias voltage. / V • V . n bias swing swing gain = gmR,= — . - = (3-12) 6 & m L y _y j y _y \ ) ' GS ' THN 1 bias r GS ' THN Some considerations limit the size of this output signal. First of all, the PMOS load transistors should stay in the triode region of operation, which needs a drain-to-source voltage (VDS) that is kept below the VGS-VJHP bias point of the PMOS transistors [47]. Vswing < |^GS ~ VTHP \ (3-13) It is usually preferable to keep the load devices deep in the triode region over the entire range of the output voltage swing. This provides a more linear output resistance, which helps with the shape of the output waveforms, including the matching between the rising and falling shape of the output waveforms. It also guarantees a good performance over process variation. For this reason a smaller output swing is desired [47]. In addition to the above considerations, the output swing of each stage should be in the input voltage range of the next stage in the ring oscillator. This is required since the tail current 42 Chapter 3. Phase-Locked Loop Design Procedure source of the next differential stage should remain in the saturation region. Typically, the output swing is considered larger than this value so that the transistor maintains in the desired region of operation. The tuning range of VCO defines the frequency range of the PLL. V C O Tuning Range > 1.11 GHz (3-14) The conversion gain of the V C O depends on two factors: the tuning range of the V C O and the range of the V C O control voltage. The V C O conversion gain can be obtained by: _ 2n(Frequency - tuning - range) rad v c o {Control -voltage - range) V ^ 15) The calculated transistor widths were optimized by using the Cadence simulations. Table 7 summarizes the transistor sizes. Table 7. The transistor sizes in the VCO (W/L),, 4 (W/L) 2, 3 (W/L) 5,6 1.8um/0.18um 0.9um/0.18um 2.2|am/0.27um 3.6. Divider Circuit A programmable divider is needed for a wide tuning range as shown in Figure 3-1. Dividers are necessary to keep the V C O output frequency down to about the reference frequency at the input of the phase frequency detector. For this PLL, a divider with a division range of 32 to 63 is needed to produce the desired range of output frequencies. To achieve this division range, a number of 2/3 dividers are needed. A 2/3 divider circuit is a circuit that divides by 2 or 3, depending on a control input signal. These types of dividers are widely used in programmable 43 Chapter 3. Phase-Locked Loop Design Procedure dividers to achieve a range of division ratios. First the divide-by-two circuit and then the 2/3 divider circuit will be discussed. Finally, the timing diagram of each circuit along with its schematic is presented. As the divider has to operate at the V C O frequency, its power dissipation is of major concern. In this design, C M L flip-flop topology is used. There are other topologies such as [22, 34]. However, C M L circuits with resistor loads have higher speeds. Also, they require a low-swing clock, which is much easier to satisfy at higher frequencies. Additional speedup can be obtained by using inductor peaking. However, in this work, resistors are preferred because of the area constraint. Section 3.6.1 expresses the divide-by-2 schematic and timing diagram. Section 3.6.2 explains the circuit of the 2/3 divider and the schematic and operation of the chosen programmable divider used in this work. 3.6.1. Divide-by-2 Circuit A divide-by-2 block is implemented using a toggle flip-flop, as shown in Figure 3-12. Frequency division by two is achieved by clocking these two latches. Figure 3-13 and Figure 3-14 show the schematic transistor level and the timing diagram of the flip-flop-based divide-by-2 circuit. Latch 1 Latch2 D n V w Q Q elk elk IN IN Figure 3-12. Architecture of a divide-by-2 circuit 44 Chapter 3. Phase-Locked Loop Design Procedure R R ; 4>, O, 0 Figure 3-13. Circuit details for a divide-by-2 circuit The circuit operates as follows. The cycle starts when the clock signal is rising, 92 is low, and its complement 94 is high. These are the input signals of the left latch in Figure 3-13. In the first step, in the left latch, a current is directed into the latch's differential amplifier portion to follow the input, i.e., cpi rises to high and cp3 falls to low. At the same time, in the right latch, in order to hold the output of the latch, the current is directed into the latch's cross-coupled pair portion. In the second step, in a similar process, the left latch goes to the hold mode while the right latch enters the track mode, and the process continues. In the third step, the same process repeats on the left side, but the voltage polarity is now reversed [37]. IN IN (P1 V2 V I 1 \ I r 1 Figure 3-14. The timing diagram of a divide-by-2 circuit 45 Chapter 3. Phase-Locked Loop Design Procedure 3.6.2. Divide-by-2/3 Circuit and the Programmable Divider Circuit As stated before, for 32 to 63 division ratios, 2/3 divider cells are required. A 2/3 divider circuit is shown in Figure 3-15 [37]. IN "Ke"g"A" <3 R e g B D Q > Q +2/3 Out C O N * Figure 3-15. The schematic of a divide-by-2/3 circuit The function of the circuit is determined by the control bit 'CON*'. When CON*=0, the input signal frequency is divided by 2, while a CON*=l causes a division ration of 3. To use the divider in a divider chain, the CON* input signal is generated by the output signals of the next cells in the chain. For this purpose, an end-of-cycle logic circuit is used. This logic circuit activates the CON* signal once in a division period [37, 41]. To further investigate this concept and to provide an example of a divider chain, an 8/9 divider is designed using a 2/3 divider followed by two dividers by 2, as shown in Figure 3-16, the end-of-logic circuit. IN -2/3 A w -2 B w -i-9 • z. CON* CON OUT End-of-cycle Logic Figure 3-16. Divider-by-8/9 schematic 46 Chapter 3. Phase-Locked Loop Design Procedure In this figure, there is an external input ' C O N ' to determine the division ratio, i.e., 8 or 9. Figure 3-17 shows the timing diagram for this divider. When the CON input is zero, the end-of-cycle logic circuit is disabled and no CON* pulse is generated. As a result, the 2/3 divider works as a divider by 2, and the complete circuit divides the input by 8. When the CON input is one, the end-of-logic circuit is enabled to find the end of a cycle; that is, when all the dividers' outputs are zero, the CON* will be one. Thus, once in a division cycle the 2/3 works as a divide by 3. This results in a division by 9. In other words, we can say that when the CON input is one, one extra period of the input clock is 'swallowed' in the divider. Note that to achieve a divide by 9, the functionality of the end-of-logic circuit is important. By cascading a number of 'n ' 2/3 division cells a division range of 2" to 2 n + l - l can be achieved. Figure 3-18 shows the divider circuit for n=5 [23, 41]. IN A _ J B OUT CON CON* 1 I I I L 7^ r Figure 3-17. The signal diagram of dividing by 8/9 divider As Figure 3-16 shows if we replace the two dividers by 2 with two dividers by 2/3, we will get an 8 to 15 divider. This is because each divider can swallow 'up to one' clock period (depending on its CON input). Note that one clock period in the inputs of the second and the third dividers correspond to 2 and 4 input clock periods, respectively, because of the division function. Therefore, the combination of these 3 cascaded dividers can swallow up to 1 + 2 + 4 or 47 Chapter 3. Phase-Locked Loop Design Procedure 7 clock periods. This means that we have an 8 to 15 divider. Figure 3-18 shows the divider circuit for n=5 to achieve the desired range of 32 to 63. CON, CON CON CON, CON, Figure 3-18. A 32 to 63 divider Generalizing this idea to a number of 'n ' cascaded 2/3 division cells yields a division range of 2 n to 2 n + 1 - l . The division ratio, N , can be formulated as: N = 2" + 2"-\CONn_, + + 2\CON, + 2°.CON0 (3-16) The output signal period can be depicted as: T0Ut=N.Tin (3-17) In (3-16) and (3-17), T^ is the period of the input signal, and CONo, CON],.. . . ,CON n-i are the binary control voltages of the cells 0 to n-1, respectively. A division ratio of 2" is achieved by an all-zero input, while an all-one input results in a division by 2 n + 1 - l . An example operation of the circuit in is shown in Figure 3-20, for N=42 (42 = 1010 IB). As a result, the 2 n d and the 4 t h dividers ( 'B' and ' D ' outputs) operate as divide by 2, while the other dividers operate as 2/3 dividers, depending on their control inputs. The divider's power consumption can be reduced by combining the two circuits of the C M L AND gate and the C M L latch to achieve a C M L latch-AND gate, as shown in Figure 3-19 [41]. The 2/3 divider can be modified by these combined circuits to achieve a faster speed and lower power consumption. One of the drawbacks of this circuit is the use of stacked NMOS 48 Chapter 3. Phase-Locked Loop Design Procedure transistors. Because of the relatively low swing supply voltage, this circuit can be used in higher supply voltages. Figure 3-19. The implementation of a Latch-AND gate 49 Chapter 3. Phase-Locked Loop Design Procedure IS S i s CD ro g ^ T— r-^  E CM r~ ( A ) ( A ) C CNI - — ZD ZD ( A ) CM CM =3 o CM E -( A ) ( A ) ( A ) Figure 3-20. Divider output timing diagram for N = 42 50 Chapter 4. Simulation Results Chapter 4 Simulation Results This chapter presents the simulation results for the PLL and its building blocks. These simulations are performed using Cadence environment and Matlab tools. Table 8 summarizes the loop parameters of the PLL. The PLL system level phase noise is simulated using the "PLL Design Assistant" program [48]. Section 4.1 presents the correspondingly system level simulation results. Section 4.2 shows the PFD simulation results, including the transient behavior and the transfer characteristic. Section 4.3 reviews the VCO simulation results, including the tuning range and the transient waveforms for the V C O output and control voltage. Also, the transient response of the VCO control voltage is shown in this section. Section 4.4 shows the simulation results of the complete PLL for different division factors corresponding to the maximum and minimum operating frequencies of the PLL. Finally, Section 4.5 explains the different jitter measures along with the jitter measurements in the PLL by Matlab. 51 Chapter 4. Simulation Results Table 8. Main parameters in the PLL design Parameter Value ICP 15uA Kvco 3.2e6 C 15pF C 3pF R KppD 1/271 PM 44.6° 4.1. General P L L Design A systematic simulation of the PLL in Matlab provides the phase and gain margins of the PLL. Figure 4-1 illustrates the results. The magnitude diagram of the PLL transfer function shows two poles in the origin, which cause the phase diagram to start from -180°. The diagrams also represent a zero in the middle of the frequency range. This zero improves the stability of the system. Simulations show a phase margin (PM) of 42°, which meets the system's stability requirements. The P L L loop's phase margin and gain margin are obtained by examining the PLL transfer function using Matlab, as illustrated in Figure 4-1. 52 Chapter 4. Simulation Results 150 I 1 1 1—i—i i i i | ! 1 1—I—i i j ; | 100 h • S 6 ? S 9 10 10 10 10 10 Frequency (rad/sec) Figure 4-1. Bode diagram of the open loop transfer function The "PLL Design Assistant Program" is provided as a self-extracting executable file that provides a graphical user interface for designing PLLs. This design is at the transfer function level. This program takes a desired closed-loop transfer function description as the input and calculates the open-loop parameters that must be chosen in the design. The other feature of this package is its ability to estimate the PLL noise performance by entering the noise parameters and observing the phase noise and the jitter of the P L L [48]. Figure 4-2 and Figure 4-3 show the step response and the phase noise simulation results, respectively. As Figure 4-3 shows the main contributor to the PLL phase noise is the V C O [49]. 53 Chapter 4. Simulation Results Also shown in the figure, PFD is the other building block, which has a considerable contribution in the phase noise. The measured rms jitter by this package is 13.7ps, which is within 10% of that of the simulation result in Cadence. Closed Loop Step Response Time (seconds) Figure 4-2. Closed loop step response of the PLL Output Phase Noise of Synthesizer 10 !0 Frequency Offset (Hz) Figure 4-3. Output phase noise of the PLL 54 Chapter 4. Simulation Results 4.2. PFD Simulation Results PFD compares its two input signals and generates the UP and D N outputs based on the phase difference between its two inputs. Figure 4-4 shows the waveforms of the PFD signals in the closed loop PLL for an operating frequency of 2.25GHz. As illustrated in this figure, the rising edges of the reference and feedback signals generate the UP and D N signals, respectively. > > > 2.0 1.3 600m v. Reference Clock 1.8 1.2 600m 1.3 600m 1.2 • : Feedback Clock m—f'HI f 'H—n A : U P >: DN 600m 3.0u 3.1u U . U U U 3.2u time ( s ) 3.3u 3.4u Figure 4-4. PFD inputs, UP, and DN As stated in Section 3.1, adding enough delay to the reset path of the PFD removes the dead zone in the PFD transfer characteristic, which is shown in Figure 4-5. This figure depicts 55 Chapter 4. Simulation Results the difference between the average values of UP and D N signals versus the phase difference between the two inputs. B" \ \ \ •1 \ • \ . 50.0O 60.0n 70.0n 80.0n 90.0- 100n delto_phi Figure 4-5. PFD transfer characteristic 4.3. VCO Simulation Result The VCO's tuning range is calculated by running a parametric simulation over the entire range of the V C O control voltage. Simulations show that a range of 0.4 to 1.4V for the control voltage results in a tuning range of 750MHz to 4GHz for the VCO. However, in this design a smaller frequency range of 1.14GHz to 2.25GHz is used, which corresponds to the 0.68V to 1.03V control voltage. Figure 4-6 illustrates the VCO frequency-voltage conversion curve. The gain of the V C O in the desired frequency range is 3.2GHz/V. 56 Chapter 4. Simulation Results Frequency vs. Control Voltage 4.5 i OOOO OO OOOO OOOO r-'^ r^^  ^ Contro l Vol tage (V) Figure 4-6. VCO tuning range Figure 4-7 and Figure 4-8 show the transient output signal of the VCO at both ends of the frequency range, i.e., 1.14GHz and 2.25GHz. Simulations over a number of control voltages in this range show that the output amplitude of the PLL is almost constant. This is confirmed by the waveforms in Figure 4-7 and Figure 4-8. 57 Chapter 4. Simulation Results 4.171u 4 - .174U 4-.177u 4 . 1 8 0 U time ( s ) Figure 4-7. The transient response of the VCO at 1.14GHz 2.955u 2.956u 2.957u time ( s ) 2.95Bu 2.959u Figure 4-8. The transient response of the VCO at 2.25GHz 58 Chapter 4. Simulation Results One of the noisy signals in the PLL is the VCO control voltage. Figure 4-9 shows the V C O control voltage under the lock condition. The ripples on the waveform are due mainly to the switching behavior of the charge pump. However, the UP and DN current mismatch could also increase the ripples. These ripples are attenuated (smoothed) by the loop filter. The amplitude of the ripples on the control voltage in the steady state is 28mV. As shown in Figure 4-9, the lock-in time for the control voltage is less than 700ns. 2 s 1.1 33Bn 4B0n T l m B (BAG) Figure 4-9. Lock-in time transient of the VCO control voltage Figure 4-10 illustrates the waveforms of UP and control voltage signals. This figure shows how the control voltage of the VCO, which is the LF's output, responds to the UP signal, which is the input signal of the charge pump. When the UP signal is high, the capacitor in the LF is charged to a higher voltage. This capacitor is discharged when the UP signal is low. 59 Chapter 4. Simulation Results ~41 —1 J - L _J_ -L L -3.2u 3.3u 3.4u si.5u 3.Su 3.7u 3.Su t i m e ( s ) Figure 4-10. VCO voltage control and the UP signal Finally, a phase noise measurement is performed on the circuit. For this purpose, the VCO is simulated in free running mode in a centre frequency of 1.53GHz, which corresponds to a 0.9V control voltage. Figure 4-11 represents the simulation results. The measured phase noise of the VCO is around -62.75dBc/Hz @lMHz. 60 Chapter 4. Simulation Results 4.4. PLL Simulation Results The complete circuit of the PLL, including the divider, is simulated for N=63. Figure 4-12 shows the PLL internal waveforms, including UP, DN, and the output and control voltage of the VCO. To analyze the transient behavior when the divider's division ratio changes, a simulation is performed with N=32 and N=63. Figure 4-12 shows changes in the control voltage due to the switching in the divider's division ratio. As illustrated in the figure, the lock time of the PLL in the switching from N=63 to N=32 is less than 700ns. 61 Chapter 4. Simulation Results 1.2 6?°i 1 1.8 H 1.2 t i„ 6 0 0 r n t 1.8 1.2 * "t b j c k ' k J l l A : R e f e r e n c e C l o c k r4-rr UP 5 0 0 m 1.8 5 0 0 m DN , 7 u 4 . 0 u t i m e ( s ) 4 . 3 u Figure 4-12. The transient response of the major signals in the PLL 1 3 0 D ; C o l t a g c Con t ro l 9 0 0 m 7 0 0 m B.0u Figure 4-13. The response of the control voltage of the VCO to the divider control bit switching 62 Chapter 4. Simulation Results As a complementary step in the design of the PLL, the circuit must be tested in process, temperature, and supply voltage variations. Table 9 gives the results of the PLL simulation in four process corners and three different temperatures. The process corners are SS (slow PMOS/slow NMOS), FF (fast PMOS/fast NMOS), FS (fast PMOS/slow NMOS), SF (slow PMOS/fast NMOS). Also, Table 9 shows the simulation results for a typical (T) process. Table 9. Impact of process and temperature variations on PLL output frequency PMOS NMOS Temperature Minimum Frequency (GHz) Maximum Frequency (GHz) T T 0 1.161 2.29 T T 27 1.14 2.25 T T 70 1.118 2.205 S S 0 1.087 2.251 S S 27 1.077 2.23 S S 70 1.066 2.209 F F 0 1.256 2.358 F F 27 1.205 2.262 F F 70 1.154 2.167 S F 0 1.1084 2.32 S F 27 1.1064 2.316 S F 70 1.1044 2.27 F S 0 1.188 2.205 F S 27 1.175 2.181 F S 70 1.161 2.157 63 Chapter 4. Simulation Results To find the sensitivity of the circuit to supply variation, a ±10% change in the power supply voltage is applied to the circuit. Figure 4-14 and Figure 4-15 show the related waveforms. The simulation results show that the output frequency is almost independent of the supply voltage, when the change in supply is within 10%. In fact, supply variations are compensated by the changes in the VCO control voltage. Table 10 tabulates the changes in the range of V C O control voltages due to the supply variations. 2.10 r e e d b o c K C l o c k 600m r: 2.10 Reference Clock 600m 2.10 > ! - 35 600m 2.10 iLlLI UP DN > 1-35 600m 2.10 T~ 'i Vh 600m ©: VCO Voitoce Contra 3.1u 3 .7L irne ( s ) 4.0u 4.3u 4 . D U Figure 4-14. The effect of a 10% increase in supply voltage on the PLL transient response (VDD=1.98V) 64 Chapter 4. Simulation Results : Feedback Clock 500m 3.10u 3.50u 3.90u time ( s ) 4.30u 4 .70L Figure 4-15. The effect of a 10% decrease in supply voltage on the PLL transient response (VDD=1.62V) Table 10. Simulation results for 10% variation in supply voltage Power Supply Voltage (V) VCO Voltage Control Range (V) Frequency Range (GHz) Output Amplitude Voltage (V) 1.98 0.73-1.15 1.139-2.267 1.1 1.8 0.67-1.05 1.14-2.25 1 1.62 0.525 - 0.871 1.14-2.248 0.977 65 Chapter 4. Simulation Results 4.5. Jitter Measurement Timing jitter has been the subject of many studies. Different models exist that predict the jitter of the PLL based on the internal circuit blocks of the PLL. Several circuit blocks are typically fabricated on the same substrate. PLL operates from the global supply voltage and ground, experiencing both substrate and supply noise. This noise reveals itself as jitter in the output of the PLL. The building blocks of the PLL contribute different amounts of noise to the output, but VCO plays the dominant role in the amount of the jitter. Ring oscillators are increasingly being used in jitter sensitive applications because of their speed, ease of integration, and wide tuning range. Several studies have been done specifically on jitter and phase noise in ring oscillators [50, 51, 52]. Cycle-to-cycle jitter, cycle jitter, and long-term jitters, explained in Chapter 2, have been meassured for both ends of the PLL tuning range in Matlab. Table 11 presents the results. Table 11. Jitter measurement results in Matlab Jitters (ps) Output Frequency =1.14GHz Output Frequency =2.25GHz Cycle-to-cycle 2.38 3.02 Long-term 6.35 7.06 Cycle 12.77 14 Peak-to-peak 22.7 24.2 One of the most popular and efficient representations of the jitter is the eye diagram, which is a composite view of several periods of a captured waveform. Based on time domain jitter analysis (eye diagram), deterministic jitter can be calculated. Deterministic jitter can be defined as the worst-case difference between a determined crossing point and a rising (or falling) 66 Chapter 4. Simulation Results edge [52]. This eye diagram shows a non-symmetric waveform that has different falling and rising edges, which indicates the presence of deterministic jitter. Figure 4-16 illustrates the eye diagram for the PLL output. In this figure, the outer distance of the rising and falling edges represents the total deterministic jitter. As measured in this eye diagram, the mean value of the deterministic jitter is 25ps, which is compatible through the related formulas, with the measured result in Table 11. Figure 4-17 illustrates the magnified eye diagram of the output of this work, which is the cross point of the differential outputs. Eye Diagram Eve Diagram ; ; : * « , . i % w ; ; • : : I : iyj M ; ; ? | ; # f \ : ; i K l : % 5.5 5 6.5 7 7.5 6 : Deterministic Jitter **** Tiilie(iec) Figure 4-16. Eye diagram for the designed Figure 4-17. The magnified eye diagram PLL 4.6. Post-Layout Simulations The PLL is designed and laid out in a 0.18 pm CMOS technology. The layout of the entire PLL including the loop filter is shown in Figure 4-18. The overall die area of the PLL is 0.023mm2. 67 Chapter 4. Simulation Results Figure 4-18. Layout of the entire PLL including the LF The extracted view of the layout has been also simulated and in general the post-layout simulations are in a good agreement with the corresponding pre-layout ones. For example, Figure 4-19 shows the post-layout simulation results for the VCO control voltage. In this simulation, the divider ratio is changed between its two extreme values, 32 and 63. As shown in Figure 4-19, the PLL can follow this frequency change and the lock-in time is less than 700ns, which is very close to the pre-layout simulation results. It should be mentioned that the voltage ripple on the control voltage is slightly bigger than that of the pre-layout simulation results (by 2.5%). Figure 4-20 shows the post-layout simulation results for the PFD signals, UP and DN. 68 Chapter 4. Simulation Results 1.7 6 0 0 ml 4 . 0 u Figure 4-19. Post-layout simulation result for the VCO control voltage i s i : Input Signal l , u r I — i t-—I I—I 1.4 > — 1.0 6 0 0 r n : 2 . 1 0 1 .60 — 1.10 600m : Feedback Signal ^ r n r S r H ri rS rS rS rh 1.80 1.40 L 1.00 600m UP 1.80 > — 1.00 t •: D N 6 0 0 m 2.10U 2 . 2 0 u ! . 3 0 u 2 . 4 0 u time ( s ) 2 . 5 0 J 2.B0U Figure 4-20. Post-layout simulation results for PFD signals 69 Chapter 5. Conclusion and Future Work Chapter 5 Conclusion and Future Work This thesis presents the design of a fully differential low-swing charge pump phase-locked loop that operates in the frequency range of 1.14GHz to 2.25GHz. The target technology for this design is 0.18pm CMOS. Fully differential low-swing design structure improves the system immunity to common-mode noise (power supply noise), while facilitating high speed of operation. To operate with low-swing signals, most of the building blocks of the PLL are designed in C M L . Although at low frequencies, CMOS C M L circuits usually suffer from high power consumption in comparison with the standard CMOS gates, as the CML's power consumption remains relatively constant with increasing frequency. Therefore, at high frequencies C M L circuits demonstrate a better performance as compared to the standard CMOS gates. Voltage-controlled oscillator is one of the key elements in the PLL design. LC-oscillators show a very good phase noise performance, while they occupy a large space and also, their tuning range is limited. Therefore, non-LC based ring oscillator is chosen for the VCO. To reduce the power and noise contribution of the VCO, three stages are used in the ring oscillator. To make sure that the PLL locks only to the fundamental component of its input frequency, a tri-state PFD implemented in C M L is used in this design. Since this PLL is intended 70 Chapter 5. Conclusion and Future Work for a wide tuning range application, a divider with variable division ratio is required. To address this, a 5-bit programmable divider is designed to be used in the feedback path of the PLL. The PLL is simulated with an input reference frequency of 35MHz. With a division ratio of 32 to 63, an output frequency of 1.14 to 2.25GHz is achieved. Simulations show an approximately constant power consumption of 14.5mW over the entire tuning range. The phase noise of the free running V C O is -62dBc/Hz @ 1MHz. The deterministic jitter for the output of the PLL is 25ps. The worst-case locking time in the complete frequency range is 700ns. Low-swing design in all the building blocks of the PLL results in higher-speed of operation. Simulation results show a maximum operating frequency of 4GHz for the designed VCO of the PLL. Thus, with some modifications, the entire PLL circuit can operate in the frequencies up to 4GHz. By changing the divider to one that is capable of larger division increments, this PLL can have higher output frequencies. Experimental test and verification of the proposed P L L should also be performed. In addition, the sensitivity of the PLL to power supply and substrate noise should be verified in practice. It should be noted that testing of P L L circuits, at both prototyping and production stages, is a challenging task and is an active area of research [53, 54, 55, 56, 57]. Another possible extension to this work is to reduce the power consumption in the divider; using techniques that can decrease the current through biasing resistors in the low-frequency stages of the divider can make an immediate impact. 71 Bibliography Bibliography [1] Thomas H. Lee, "The design of CMOS Radio Frequency Integrated Circuits," Cambridge University Press, 2004. [2] L. Andersson, B. Rudberg, T. Lewin, et. al, "Silicon bipolar chipset for SONET/ SDH 10 Gb/s fiber-optic communication links," IEEE J. Solid-State Circuits, vol.30, no.3, pp. 210-18, March 1995. [3] S. Kiriaki, T. Viswanathan, et. al., " A 160-MHz analog equalizer for magnetic disk read channels," IEEE J. Solid-State Circuits, vol.32, no.l 1, pp. 1839-50, Nov. 1997. [4] B. Thompson, H.S. Lee, L. DeVito, " A 300-MHz BiCMOS Serial Data Transceiver," IEEE J, Solid-State Circuits, vol. 29, no.3, pp. 185-192, March 1994. [5] D. Johns, D. Essig, "Integrated circuits for data transmission over twisted-pair channels," IEEE J. Solid-State Circuits, vol.32, no.3, pp. 398-406, March 1997. [6] T. Lee, K. Donnelly, et. al, " A 2.5V CMOS Delay-Locked Loop for an 18 MBit, 500 Megabyte/s D R A M , " IEEE J. Solid-State Circuits, vol. 29, No. 12, pp. 1491-1496, Dec. 1994. [7] M . Horowitz et. al, "PLL Design for a 500 MB/s interface," in ISSCC Dig. Tech. Papers, pp. 160-161, Feb. 1993. [8] I. Young, J. Greason, J. Smith, K. Wong, " A PLL Clock Generator with 5 to 110 MHz Lock Range for Microprocessors," IEEE J. Solid-State Circuits, vol.27, no . l l , pp. 1599-1607, Nov. 1992. [?] A . Widmer, K. Wrenner, H. Ainspan, et. al, "Single-chip 4*500-MBd CMOS transceiver," IEEEJ. Solid-State Circuits, vol.31, no. 12, pp. 2004-14, Dec. 1996. 72 Bibliography [10] T. Stetzler, I. Post, J. Havens, M . Koyama, " A 2.7-4.5 V single chip G S M transceiver RF integrated circuit," IEEE J. Solid-State Circuits, vol.30, no.12, pp.1421-9, Dec. 1995. [11] Zhang, H., George, V., Rabaey, J.M.,"Low-swing on-chip signaling techniques: effectiveness and robustness," IEEE Tran. VLSI Systems, vol. 8, no. 3, pp. 264-272, June 2000. [12 ] Chandrakasan, A.P., Sheng, S., Brodersen, R.W., "Low-power CMOS digital design," IEEEJ. Slid-State, vol. 27, no. 4, pp. 473-484, April 1992. [13] Enz, C.C., Vittoz, E.A., "CMOS low-power analog circuit design," Emerging Tech. Designing Low Power Digital Systems, pp. 79-133, 1996. [14] Woogeun Rhee, " A Low Power, Wide Linear-Range CMOS Voltage-Controlled Oscillator," in IEEE Int. Symp. on Circuits and Systems, vol. 2, no. 31, pp. 85-88, May 1998. [15] Hyung-Seuk Kim and Mourad N . El-Gamal, " A 1-V Fully Integrated CMOS Frequency Synthesizer for 5-GHz W L A N , " in IEEE Int. Symp. on Circuits and Systems, vol. 2, no. 31, pp. 4389-4392, May 2005. [16] Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri, and Luca Selmi, "Modeling, Design and Characterization of a New Low-Jitter Analog Dual Tuning LC-VCO PLL Architecture," IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1303-1309, June 2005. [17] Chie-Ming Hung and Kenneth K. O, " A Fully Integrated 1.5-V 5.5-GHz CMOS Phase-Locked Loop," IEEEJ. Solid-State, Circuits, vol. 37, no. 4, pp. 521-525, April 2002. [18] John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, and Manjusha Shankaradas, "Self-Biased High-Bandwidth Low-Jitter l-to-4096 Multiplier Clock Generator PLL, " IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1795-1803, Nov. 2003. 73 Bibliography [19] Mozhgan Mansuri, Chie-Kong Ken Yang, " A Low-Power Adaptive Bandwidth PLL and Clock Buffer with Supply-Noise Compensation," IEEE J. Solid-State, vol. 38, no. 11, pp. 1804-1812, Nov. 2003. [20] Oscal T.-C. Chen, Robin Ruey-Bin Sheen, " A Power-Efficient Wide-Range Phase-Locked Loop," IEEEJ. Solid-State Circuits, vol. 37, no. 1, pp. 51-62, Jan. 2002. [21] Saurabh Kumar Singh, T K Bhattacharyya, and Ashudeb Dutta, "Fully Integrated CMOS Frequency Synthesizer forZigBee Applications," Int. Conf. VLSIDesgin, pp. 780-783, Jan. 2005 [22] HongMo Wang, " A 1.8V 3mW 16.8GHz Frequency Divider in 0.25pm CMOS," in IEEE Int. Solid-State Circuits Conference, Dig. Tech. Papers, pp. 196-197, Feb. 2000. [23] Cicero Vaucher, Dieter Kasperkovitz, " A Wide-Band Tuning System for Fully Integrated Satellite Receivers," IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 987-997, July 1998. [24] B. Razavi, "Design of analog CMOS integrated circuits," McGraw-Hill, 2001. [25] F. M . Gardner, "Charge-ump Phase-Lock Loops," in IEEE Tran. on Communications, vol. 28, pp. 1849-1858, Nov. 1980. [26] B. Razavi, "Monolithic phase-locked loops and clock recovery circuits," IEEE press, 1996. [27] C. A . Sharpe, " A 3-state phase detector can improve your next design PLL design," pp. 55-59, Sep. 1976. [28] D. A . Hodges, R. A . Saleh, H. G. Jackson, "Analysis and Design of Digital Integrated Circuits: In Deep Submicron Technology," McGraw-Hill, 3rd edition, July 2003. [29] F. M . Gardner, "Charge-pump Phase-Lock Loops," in IEEE Tran. on Communications, vol. 28, no. 11, pp. 1849-1858, Nov. 1980. [30] T.H. Lee and A. Hajimiri, "Oscillator Phase Noise: A Tutorial," IEEE J. Solid-State Circuits, vol. 35, no. 3, pp.326-336, March 2000. 74 Bibliography [31] Brian P. Ginsburg, " A 1.6-3.2GHz, High Phase Accuracy Quadrature Phase Locked Loop," Masters of Engineering, Massachusetts Institute of Technology, June 2003. [32] Michael M Driscoll, "Phase Noise Performance of Analog Frequency Dividers," in IEEE Tran. on Ultrasonic Ferroelectrics and Frequency Control, vol. 37, no. 4, pp. 295-301, July 1990. [33] Jan Craninckx and Michiel S. J. Steyaert, " A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-um CMOS," IEEEJ. Solid-State Circuits, vol. 31, no. 7, pp. 890-897, July 1996. [34] Behzad Razavi, Kwing F. Lee, Ran H. Yan, "Design of High-speed, Low-Power Frequency Dividers and Phase-Locked Loops in Deep Submicron CMOS," IEEE J. Solid-State Circuits, vol. 30, no. 2, pp. 101-109, Feb. 1995. [35] Mozhgan Mansuri, "Low-Power Low-Jitter On-Chip Clock Generation," University of California, 2003. [36] Hamid R. Rategh, Hirad Samavati, and Thomas H. Lee, " A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless L A N Receiver," IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 780-787, May 2000. [37] M . Perrott. (2005, Feb.) MIT's OpenCourseWare [Online]. Available:http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-976High-Speed-Communication-Circuits-and-SystemsSpring2003/CourseHome/index.htm/ [38] Frank Herzel, Behzad Razavi, " A Study of Oscillator Jitter Due to Supply and Substrate Noise," IEEE Tran. on Circuit and Systems-IT. Analog and Digital Signal Processing, vol. 64, no. l,pp. 56-62, Jan. 1999. 75 Bibliography [39] B. Razavi, "Phase-Locking in High-Performance Systems from Devices to Architectures," IEEE press, 2003. [40] M . Albuquerque and W. Silva, "Current-balanced logic for mixed-signal IC," in IEEE Int. Symp. on Circuits and Systems, vol. 1, pp. 274-277, May 1999. [41] Cicero. S. Vaucher, Igor Ferencic, Matthias Locher, Sebastian Sedvallson, Urs Voegeli, and Zhenhua Wang, " A family of low-power Truly Modular Programmable Dividers in Standard 0.35-um CMOS Technology," IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1039-1045, July 2000. [42] Hormoz Djahanshahi and C. Andre T. Salama, "Differential CMOS Circuits for 622-MHz/933-MHz Clock and Data Recovery Applications," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 847-855, June 2000. [43] Frank Herzel, Gunter Fischer, Hans Gustat, and Peter Weger, "An Integrated CMOS PLL for Low-Jitter Applications," IEEE Tran. on Circuits and Systems-II: Analog and Digital Signal processing, vol. 49, no. 6, pp. 427-429, June 2002. [44] A l i Hajimiri, Sotirios Limotyrakis, and Thomas H. Lee, "Jitter and Phase Noise in Ring Oscillators," IEEEJ. Solid-State Circuits, vol. 34, no. 6, pp. 790-804, June 1999. [45] Neda Nouri, Shahriar Mirabbasi, " A 900MHz-2GHz low-swing low-power 0.18pm CMOS PLL", Canadian Conference on Electrical and Computer Engineering, May 2005. [46] Payam Heydari and Masoud Pedram, "Jitter-Induced Power/Ground Noise in CMOS PLLs: A Design Perspective," Proceedings of Int. Conf. on Computer Design, pp. 23-26, Sep. 2001. [47] Todd Charles Weigandt, "Low-Phase-Noise, Low-Timing-Jitter Design Techniques for Delay Cell Based VCOs and Frequency Synthesizers," University of California, Berkeley, Spring 1998. 76 Bibliography [48] Michael H. Perrot, "PLL Design Using the PLL Design Assistant Program," http://www-rntl.mit.edu/researchgroups/perrottgroup/tools.html, Massachusetts Institute of Technology, April 2005. [49] A l i Hajimiri, "Noise in Phase-Locked Loops," Mixed-Signal Design, SSMSD, 2001 Southwest Symp., pp. 1-6, Feb. 2001. [50] A l i Hajimiri, Sotirios Limotyrakis, Thomas H. Lee, "Jitter and Phase Noise in Ring Osc i l l a to r s , "^^ / . Solid-State Circuits, vol. 34, no. 6, pp. 790-804, June 1999. [51] Payam Heydari, "Analysis of the PLL Jitter Due to Power/Ground and Substrate Noise," IEEE Tran. on Circuits and Systems-T. Analog and Digital Signal Processing, vol. 51, no. 12, pp. 2404-2416, Dec. 2004. [52] "Measuring Jitter in Digital Systems", Agilent Technologies, Application Note 1448-1. [53]Dalmia, M . , Ivanov, A. , Tabatabaei, S., "Power supply current monitoring techniques for testing PLLs," IEEE Test Symp., pp. 366-371 , Nov. 1997. [54 ] Seongwon Kim, Soma, M . , "An all-digital built-in self-test for high-speed phase-locked loops," IEEE Tran. On Circuits and Systems-II: Analog and Digital Signal Processing, vol. 48, no. 2, pp. 141-150, Feb. 2001. [55 ] Azais, F., Bertrand, Y . , Renovell, M . , Ivanov, A., Tabatabaei, S., "An all-digital DFT scheme for testing catastrophic faults in PLLs," IEEE Design & Test of Computers, vol. 20, no. 1, pp. 60-67, Jan.-Feb. 2003. [56] Ou, N . , Farahmand, T., Kuo, A., Tabatabaei, S., Ivanov, A. , "Jitter models for the design and test of Gbps-speed serial interconnects," IEEE Design & Test of Computers, vol. 21, no. 4, pp. 302-313, July-Aug. 2004. 77 Bibliography [57 ] Chun-Lung Hsu, Yiting Lai, Shu-Wei Wang, "Built-in self-test for phase-locked loops," IEEE Tran. on Instrumentation and Measurement, vol. 54, no. 3, pp. 996-1002, June 2005. 78 

Cite

Citation Scheme:

        

Citations by CSL (citeproc-js)

Usage Statistics

Share

Embed

Customize your widget with the following options, then copy and paste the code below into the HTML of your page to embed this item in your website.
                        
                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            src="{[{embed.src}]}"
                            data-item="{[{embed.item}]}"
                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
                            data-width="{[{embed.width}]}"
                            async >
                            </script>
                            </div>
                        
                    
IIIF logo Our image viewer uses the IIIF 2.0 standard. To load this item in other compatible viewers, use this url:
http://iiif.library.ubc.ca/presentation/dsp.831.1-0065861/manifest

Comment

Related Items