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Representation of multivariable-controlled MOSFET nonlinearities in transient analysis programs Ma, Hong 1991

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REPRESENTATION OF MULTIVARIABLE-CONTROLLED M O S F E T NONLINEARITIES IN TRANSIENT ANALYSIS  P R O G R A M S  By Hong Ma B. Eng. (Automation) Beijing Institute of Technology (1984) M . Eng. (Control) Chongqing University (1987)  A T H E S I S S U B M I T T E D IN P A R T I A L F U L F I L L M E N T O F T H E REQUIREMENTS FOR T H E D E G R E E OF M A S T E R OF APPLIED  SCIENCE  in T H E F A C U L T Y OF G R A D U A T E STUDIES ELECTRICAL  ENGINEERING  We accept this thesis as conforming to the required standard  T H E U N I V E R S I T Y O F BRITISH C O L U M B I A  April 1991 © Hong Ma, 1991  In presenting this thesis in partial fulfilment  of the requirements for an advanced  degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department  or by his or  her  representatives.  It is understood  that copying or  publication of this thesis for financial gain shall not be allowed without my written permission.  Department of The University of British Columbia Vancouver, Canada Date  DE-6 (2/88)  Abstract  This thesis deals with the modelling and circuit simulation problems of nonlinear electronic devices. Emphasis has been aimed at MOSFET devices. A Piecewise Linear ( PWL) modelling scheme has been proposed for a general four-terminal nonlinear charge device. The charge functions are all nonlinear and are approximated by PWL functions. If analytical expressions for the nonlinear functions are not available, PWL function approximations can be built from a data table in which discrete data points are recorded. In the time domain, the critical-damping-adjustment (CDA ) scheme is used as the integration rule in the discretization of dynamic charge devices. Piecewise linear modelling combined with the CDA integration scheme gives a fast yet adequately accurate simulation algorithm. The algorithm is based on linear analysis because the entire circuit becomes linear with PWL modelling of nonlinear elements. In order to avoid an iterative solution, PWL region extrapolation is permitted when the circuit solution switches PWL regions. The extrapolation approximation will generate an overshoot error in the solution vector. However, with caution in the selection of the integration step size, the error can be limited to an acceptable range. Two types of MOSFETs have been modelled and simulated with the algorithm introduced in this thesis, and satisfactory results have been obtained as compared to Newton's iteration solutions.  ii  List of Contents Abstract  ii  List of Figures  v  List of Tables  vii  Acknowledgment  viii  Chapter 1  Introduction  1  1.1  Time domain discretization  1  1.2  Linearization  5  1.3  Objectives  8  1.4  Organization of this thesis  8  Chapter 2  PWL Modelling of A Four-Terminal Nonlinear Charge Device  9  2.1  Definition of a four-terminal nonlinear charge device  9  2.2  Simplicial partitioning of the voltage space  11  2.3  Charge representation in PWL regions  13  Chapter 3  Time Domain Solution Algorithm of PWL Circuits  16  3.1  Time domain solution of PWL models  3.2  Newton's iteration solution algorithm  3.3  PWL solution algorithm  21  3.4  Location of PWL regions during the transient solution  23  Intrinsic MOSFET PWL Modelling and Circuit Simulation  25  Chapter 4  16 18  4.1  Intrinsic MOSFET devices  25  4.2  Review of modelling of MOSFET device  27  4.3  PWL representations of MOSFET terminal currents  30  4.4  Circuit simulation experiments  33  Chapter 5 5.1  Power MOSFET modelling and simulation VDMOST equivalent circuit for transient analysis iii  52 52  5.2  PWL modelling and simulation  63  5.3  Power MOSFET circuit simulation  70  Chapter 6  Discussions and Conclusion  72  Appendix A  A First-Order MOSFET Charge Model  74  Appendix B  PWL Coefficients for MOSFET Terminal Currents  79  References  80  iv  List of Figures Figure 1.1.1  Companion circuit for a linear capacitor  4  Figure 2.1.1  A four-terminal charge device  9  Figure 2.2.2  Simplicial partitioning of controlling voltage space  11  Figure 3.4.1  Location of PWL regions on a plane  24  Figure 4.1.1  A cross sectional view of the intrinsic NMOSFET  26  Figure 4.2.2  Equivalent circuit of intrinsic MOSFET device  30  Figure 4.4.3  A single MOSFET inverter  34  Figure 4.4.4  Trapezoidal rule, Newton's iteration, At=l^s. a) Input(solid line) and output(dotted line) voltages; b) Source terminal current  Figure 4.4.5  Trapezoidal rule, Newton's iteration, At=0.5/is. a) Input(solid line) and output(dotted line) voltages; b) Source terminal current  Figure 4.4.6  40  PWL algorithm, At=0.5^s. a) Input(solid line) and output(dotted line) voltages; b) Source terminal current  Figure 4.4.9  39  PWL algorithm, At=l^s. a) Input(solid line) and output(dotted line) voltages; b) Source terminal current  Figure 4.4.8  38  Trapezoidal rule, Newton's iteration, At=0.1/is. a) Input(solid line) and output(dotted line) voltages; b) Source terminal current  Figure 4.4.7  37  41  PWL algorithm, At=0.1/xs. a) Input(solid line) and output(dotted line) voltages; b) Source terminal current  42  Figure 4.4.10  MOSFET charging circuit  43  Figure 4.4.11  Trapezoidal rule, Newton's iteration, At=0.1/iS. a) voltages on capacitors Ci and C2 (they are identical); b) source terminal current  Figure 4.4.12  44  PWL algorithm, At=0.1jjs. a) voltages on capacitors C\ and C2 ( they are identical); b) source terminal current  45  Figure 4.4.13  MOSFET switched capacitor  46  Figure 4.4.14  Trapezoidal rule, Newton's iteration, At=0.2^s. voltages on capacitors C (a) and C {b) 2  48  x  V  Figure 4.4.15  PWL algorithm, At=0.2/zs. voltages on capacitors C2(a) and Ci(b). 49  Figure 4.4.16  Trapezoidal rule, Newton's iteration, At=0.1^s. a) Voltages on capacitors Ci (solid line) and C2(dotted line); b) Source terminal currents. . . .  Figure 4.4.17  PWL algorithm, At=0.1fjs. a) Voltages on capacitors C\(solid line) and C2(dotted line); b) Source terminal currents  Figure 5.1.1  50  51  A cross sectional view of a double diffused vertical power MOST. It has a symmetrical structure. The elements in the equivalent circuit are shown in the right half of the device  53  Figure 5.1.2  Equivalent circuit model of VDMOST for large signal analysis . . .  54  Figure 5.1.3  Nonlinear large-signal capacitance model of Cds for VDMOST . . .  58  Figure 5.2.4  Two-dimensional PWL partitioning  64  Figure 5.2.5  Current characteristics of a diode  65  Figure 5.3.6  VDMOST with resistive load  70  Figure 5.3.7  Simulated switching waveforms, from top to bottom: input voltage on gate; output voltage on drain terminal; source terminal current; drain terminal current. At=200ns  71  Figure A.1  Source terminal charge Qs  77  Figure A.2  Drain terminal charge Qd  77  Figure A.3  Substrate terminal charge Qb  78  Figure A.4  Channel current Ids  78  vi  List of Tables Table 1  Computation Times for Circuit 1  43  Table 2  Computation Times for Circuit 2  46  Table 3  Computation Times for Circuit 3  47  Table 4  VDMOST equivalent model parameters  62  vii  Acknowledgment  I am deeply grateful to Dr. Jose R. Marti, my supervisor, for his excellent and patient academic guidance as well as his generous financial support throughout the past two years. He has led me into the field of circuit CAD which I was not familiar with at the beginning. I will always remember the discussions we had during the course of this research. My thanks also go to Mr. Rob Ross, Ms. Doris Soo and all the professors and friends who taught me and gave me a hand during my study here at UBC. I would also want to thank my family who supported me spiritually from the other side of the Pacific. Their constant encouragement helped me through the difficult times.  Chapter J. Introduction  Chapter 1  Introduction Direct time domain nonlinear dynamic circuit simulation involves two aspects: one is the time domain discretization of the differential equations which model the dynamic devices; the other is the solution of nonlinear algebraic circuit equations. Generally, one can first formulate the circuit by a set of differential-algebraic equations by any one of the circuit analysis approaches , then use the above two steps to compute time domain 1  solutions. But a practical and convenient way is to discretize and linearize each nonlinear device model itself. After discretization and linearization, each nonlinear dynamic component can be modelled by a linear companion circuit; thus, the entire circuit can be formulated by a set of linear algebraic equations. Therefore linear analysis techniques can be applied direcdy to compute the time domain solutions of the nonlinear circuits and systems.  1.1 Time domain discretization Most dynamic devices in today's electronic circuits can be described by first-order differential equations. For example, a two-terminal linear inductor can be described by  v (t) = L  di {t)  L  L  dt  (1.1.1)  and a two-terminal linear capacitor can be described by  i (t) = C c  dvcit) dt  (1.1.2)  where L and C are a constant inductance and a constant capacitance. If the inductor and capacitor 1  Nodal analysis approach will be used throughout the entire thesis.  1  Chapter 1. Introduction  are nonlinear devices, the differential relations above have to be changed to the following:  for the nonlinear inductor, and  .00) =  d.1.4)  for the nonlinear capacitor. In these equations, <$>L  =  <^L(*L(0) ^ 1c = 1c(vc(t)) m<  a r e  nonlinear  functions. In a time domain step-by-step digital computer solution, the differential equations have to be approximated by finite difference formulas, namely, numerical integration rules. This transformation of device models from continuous differential form into approximated discrete form is time domain discretization. The trapezoidal integration rule and the Backward Euler ( BE ) integration rule are the two most often used discretization rules in today's popular circuit simulators. They are implicit and easy to implement. More importantly, they are A-stable [4]. According to [15][33] , the trapezoidal rule exhibits overall better numerical properties than BE rule both in the time domain and the frequency domain. But a major shortcoming of the trapezoidal rule is its lack of numerical oscillation damping capability. High frequency artificial numerical oscillation, which can be superimposed on the normal solution waveform, will occur whenever there is a discontinuity of the circuit variables during the simulation. In [33], the critical-dampingadjustment ( CDA ) scheme, a combination of trapezoidal rule and BE rule, was proposed to suppress such numerical oscillations. In piecewise linear circuit simulation, the CDA scheme suppresses artificial numerical oscillations in two consecutive BE steps by exploiting the strong damping capability of the BE integration rule. This technique maintains the computational accuracy of die trapezoidal rule within linear regions. BE integration is only invoked at the moment when the solution vectors of the circuit are found to have switched from one linear 2  Chapter I. Introduction  region into another. In this thesis, the CDA scheme will be used as the integration rule for the discretization of a Piecewise Linear ( PWL ) multi-terminal multi-voltage controlled charge device model. To illustrate the discretization process, we can take the linear capacitor as an example. Integrating equation (1.1.2) from t-At to t, we get  J i (t)dt = C j c  t-At  <^dt.  (1.1.5)  t-At  Applying the trapezoidal rule to approximate the integral into a finite difference relation yields icit) +  i  f-  A t )  At  = C[vc(t)-vc(t-At)].  (1.1.6)  If the BE rule is applied, we then get  i (t)At = C[v (t) - v (t - A < ) ] . c  c  c  (1.1-7)  Since the circuit variables at t-At are known during the solution at time t, the above approximate difference equations can be rewritten into a more compact form:  ic(t) = a v (t) + b • C  C  c  (1.1.8)  A companion equivalent circuit can be set up for this linear capacitor according to equation (1.1.8), as shown in Figure 1.1.1,  3  Chapter 1. Introduction  1/a.  Figure 1.1.1 Companion circuit for a linear capacitor where the constants ac and be are given by: For the trapezoidal rule 2C  At  (1.1.9)  _2C_  be  At  v (t - At) - i (t - At) • C  c  For the B E rule  a  c  = At  be =  (1.1.10) --^v (t-At) c  However, if the capacitor is a nonlinear one, the discretization of equation (1.1.4) leads to the following compact form:  ic(t) = a q {t) + b c  c  where the constants a' and b' are given by: c  c  4  c  (1.1.11)  Chapter 1. Introduction  For the trapezoidal rule a  c  --  _2_  At  (1.1.12)  For the BE rule 1 (1.1.13)  At  <Zc(* - A * ) .  Since qc(t) is nonlinear function of vc(t), the voltage across the capacitor, the companion a  equivalent circuit will not be as simple as the one shown in Figure 1.1.1. The linear conductor in Figure 1.1.1 has to be replaced by a nonlinear conductor which has an i-v characteristic of a' qc(t)/vc(t) c  of  or replaced by a voltage controlled current source with a nonlinear amplitude  a q (t). c  c  At each time point t, after each dynamic device (linear or nonlinear ) has been discretized, the entire circuit becomes a resistive circuit represented by a set of algebraic equations,  F[v(t)] = u(«)  (1.1.14)  where F is a matrix function, v(t) is the node voltage vector, u(t) is the source vector. F could be linear or nonlinear. It depends on the characteristics of the devices in the circuit. If one or more devices are nonlinear ( static or dynamic ) , then F would be nonlinear. To make use of the linear analysis techniques, or to make F become a linear matrix function, linearization procedures have to be applied to the nonlinear characteristics of the devices. 1.2  Linearization The most widely used local linearization technique in solving nonlinear problems is Newton's  iteration. Take the nonlinear capacitor as an example. Apply Taylor's expansion to equation 5  Chapter 1. Introduction  (1.1.11) at time point t and discard the higher order terms. We can then get the locally linearized approximation to the original nonlinear function i (t) at an initial or intermediate iterative voltage c  point Vc(t):  «c(0 = «c(0 +  0  dicjt)  [»c(0-«£(*)] >  dv (t)  d-2-15)  c  where the superscript "0"representsthe circuit variables at the previous iterative step, and "1" represents the circuit variables at the current iterative step which are to be solved for. ic(t) can be found by substituting *>£.(£) into equation (1.1.11 ):  ic(t) = "elegit))  + b'  c  (1.2.16)  where a' and b' are related to time discretization step size At and the circuit variables at the c  c  last time point t-At, these values are known at time point t. Since ic(t) is a nonlinear function of vc{t) through the representation of charge qc{t), the derivative of ic{t) with respect to the controlling variable vc(t) in equation (1.2.15) can be found as follows: 'dicity  a  c  dqcjt)  (1.2.17)  dv {t) c  Then the locally linearized equation (1.2.15) can be further written into a compact form,  (1.2.18)  t (t) = a' v (t) + b' , l  c  where d' and c  c  c  c  are given by  a  c  - a  dq (t)  i0  C  c  (1.2.19)  dv (t); C  II  be  a'cqcivcit))  +b'  c  6  a v (t) c  c  Chapter I. Introduction  After each nonlinear device is linearized, the matrix function F(t) of the entire discretized circuit becomes linear. Newton's iteration solution will be successfully completed at each time point when a convergence is reached. The criteria for the convergence usually takes the following form  (1.2.20)  H v ^ - v ^ t O I K e ,  where e is a pre-defined small positive number. Two factors are crucial for Newton's iteration to be successful in reaching a convergence quickly. One factor is the initial guess of node voltage v(t); the other is the existence of derivatives of nonlinear functions of the discretized current with respect to the controlling voltages. The second factor requires that the nonlinear charge functions be smooth along each dimension of the controlling voltages in the nonlinear device model. Many simulators employing Newton's iteration require the nonlinear functions to be C smooth [35], 1  If the initial guess of v(t) is  far off from the real solution, or if the nonlinear characteristics of the devices are not smooth enough, Newton's iteration may not converge, in the sense that the criteria in (1.2.20) will never be satisfied within a certain amount of iteration steps. In practice, it is not uncommon that a nonlinear circuit simulation session will fail to converge due to the above reasons. Furthermore, even with well-constructed analytical models for the nonlinear devices, Newton's iteration still needs three to four steps to converge. These extra computation steps slow down the speed of simulators which employ Newton iteration as their nonlinear solution algorithms. Finally, since our concern is in the time domain analysis of nonlinear circuits, the time step size plays an important role in the solutions. As can be seenfromdiscretized equation (1.2.11), the nonlinear characteristics of the devices are related to the time step size as well as to the integration rule used. Generally, a smalltimestep size will help the convergence of the Newton's iteration algorithm. 7  Chapter 1. Introduction  1.3 Objectives The objective of this work is to find a modelling and solution method for nonlinear electronic devices in time domain simulations. Realizing the disadvantages of using Newton's iteration as the linearization tool in time domain nonlinear circuit analysis modelling, we will use instead a PWL approximation technique. We will apply this technique to the modelling of a four-terminal multi-voltage controlled nonlinear charge device in time domain circuit simulation. Since PWL modelling of the charge device for time domain solutions will cause abrupt changes of the capacitive parameters when switching PWL regions, the CDA scheme is adopted as the integration technique to suppress the numerical oscillations when this happens. The immediate application of the proposed PWL modelling and time domain solution algorithm is to the MOSFET intrinsic device and its circuit simulation. In the latter part of the thesis, the PWL approximation technique is also applied to the modelling of power MOSFETs ( VDMOSTs ). 1.4 Organization of this thesis In chapter 2, a PWL model is presented for a four- terminal multi-voltage controlled charge device based on the simplicial division [7][6] of the controlling voltage space. PWL modelling and solution algorithm is proposed in chapter 3 for the nonlinear charge device defined in chapter 2 in time domain circuit simulation. In chapter 4, we first give a brief review of the modelling of the MOSFET intrinsic device, then the algorithm proposed in chapter 3 is applied to MOSFETs in simulation examples. Comparison simulation examples with the Newton's iteration solution are also given in this chapter. VDMOST PWL modelling and simulation examples are discussed in chapter 5. Finally, chapter 6 concludes the thesis.  8  Chapter 2.  PWL Modelling of A Four-Terminal Nonlinear Charge Device  Chapter 2 PWL Modelling of A Four-Terminal Nonlinear Charge Device PWL modelling of nonlinear functions has been studied for many years.  Since PWL  modelling is an interpolation approximation technique, it only needs discrete data points on which the PWL functions are interpolated to approximate the original nonlinear functions. The data points can be obtained by physical measurement of the device or by theoretical calculations from the nonlinear analytical expressions describing the physics of the device or by numerical simulations of the device. The resolution of PWL approximations can be freely controlled by the designer so that a good compromise between computational speed and solution accuracy are attained.  2.1 Definition of a four-terminal nonlinear charge device A four-terminal multi-voltage controlled charge device is shown in figure 2.1.1.  Figure 2.1.1 A four-terminal charge device 9  Chapter 2.  PWL Modelling of A Four-Terminal Nonlinear Charge Device  In this Figure v , Vb, v and Vd are terminal voltages with respect to a datum point in the a  c  circuit. i , it, i and id are terminal currents. The directions of the terminal currents are assumed a  c  as indicated in the Figure. These voltages and currents are governed by K V L and K C L as follows: KVL:  V b + bc + V d + Vda = 0 ; v  a  c  (2.1.1)  KCL:  i  a  (2.1.2)  + H + ^ + id — 0  There are only three independent terminal voltage drops and three independent terminal currents because of K V L and KCL. We also assume that the terminal currents are generated by the corresponding device charges attached to each terminal. Furthermore , we assume that all terminal charges are multi-voltage controlled nonlinear functions of three terminal voltage drops. Selecting terminal a as the positive reference terminal for the controlling voltage variables, the nonlinear charge functions are generally assumed in the following form: Qa =  Qa(v b,V ciV >)  Qb =  Qb(v b,V ,V <)  a  a  a  aa  ac  aa  (2.1.3) Qc = Qc(v b,V , a  V)  ac  ad  Qd = Qd(v b,V ciV d) a  a  a  .  Since we have assumed that the individual terminal currents are generated by their own charges, from KCL equation (2.1.2), we can get the charge neutral equation  Qa + Qb + Qc + Qd =  10  0  (2.1.4)  Chapter 2.  PWL Modelling of A Four-Terminal Nonlinear Charge Device  The major task in this chapter is to approximate these nonlinear charges by PWL models.  2.2 Simplicial partitioning of the voltage space The basis of the PWL approximation to an arbitrary monotonic continuous nonlinear function is the partitioning of the multidimensional controlling voltage space. First the three dimensional controlling voltage space [v i, v , v d] is partitioned into cubes. a  ac  a  Then each cube is partitioned into six polyhedral simplices which are denned by the vertices and hyperplanes of the polyhedrons. These polyhedral PWL regions are not overlapping within the entire range of controlling voltage space considered. Figure 2.2.2 shows the partitioning of the voltage space in three dimensions. 6  2  Figure 2.2.2 Simplicial partitioning of controlling voltage space  Suppose an equal resolution partitioning scheme for each voltage dimension is employed. A 11  Chapter 2.  PWL Modelling of A Four-Terminal Nonlinear Charge Device  PWL voltage cube is defined by (n,- -  l)AV  < v  ab  < niAVab  (nj -  l)AV  < v  ac  < njAV  < v  ad  < n AV  ab  ac  (njt - l)AV  ad  (2.2.5)  ac  k  ad  where n,-, n,j and rik are the cube numbers in voltage dimensions v b, v a  AV b, a  AV  ac  and  AV  ad  ac  and v , respectively. ad  are the partitioning resolutions in each voltage dimension. The resolutions  may be different from each other and can be decided based on the characteristics of the actual devices considered. For simplicity, equal voltage partitioning resolution for all the dimensions is used in the simulations in this thesis. Total PWL Cube numbers can be easily determined after having chosen  AV b, a  AV  ac  and  AV  ad  N  t  ~  AV  ab  Vacmax  T.  T  Nj =  max N t  where V^ s tmax  =  ^ocmin  /•> ^\  -  —  (2.2.6) Vadmin  AV^  (t = b,c,d) are higher ends of the voltage dimensions; while V^ s tmin  (t = b,c,d)  are lower ends of the voltage dimensions. It must be pointed out that if a non-equal partitioning scheme on each voltage dimension is used, a multidimensional data table should be set up to store the voltages and nonlinear charge function values ( experimental results or device numerical simulation results ) at these data points. The higher the resolution, the larger the data-table. Equal size partitioning of voltage space is used without explicit mentioning in the explanations that follow. In each cube, there can be six non-overlapping polyhedral regions as shown in Figure 2.2.2. Each of them is delimited and designated by four vertices as follows: R l : vertex[7651] R2: vertex[7261] R3: vertex[7321] 12  Chapter 2.  PWL Modelling of A Four-Terminal Nonlinear Charge Device  R4: vertex[7581] R5: vertex[7841] R6: vertex[7341] PWL regions obtained as above are said to be proper since the vertex matrix of each PWL polyhedron  v y v 1 1 1 1  Vi  [V} =  3  2  (2.2.7)  A  is non-singular. In this matrix Vj's (i = 1,2,3,4) are the coordinate vectors of the four vertices of one PWL polyhedron [6]. This property of non-singularity ensures the success of PWL interpolation over the polyhedrons.  2.3 Charge representation in PWL regions After having partitioned the voltage space into polyhedral PWL regions, in each PWL region, the original nonlinear charge functions can be approximated by linearly interpolated functions as follows: Q?  WL  = Cj\V  ab  + CjlVac + CjZV  ad  + Qj  0  J  j = a,b,c,d  where Q?  WL  (2.3.8)  ,  = Qj at the vertices of a PWL region. Nonlinear terminal charge functions are thus  linearized by interpolation within each PWL region. Compared to the small-signal linearization during Newton's iteration solutions, this is a large-signal linearization of nonlinear functions. The parameters, Cj, and Qj , in die linear expressions of charge functions have to be identified in 0  their residing PWL region by data at the four vertices that form the PWL region. Since Qj =  Qj(v b, ac,V ) v  a  ad  (2.3.9) j = a,b,c,d  13  ,  Chapter 2.  PWL Modelling of A Four-Terminal Nonlinear Charge Device  The four vertices are  i = 1,2,3,4  (2.3.10)  j = a,b,c,d . Substituting into equation (2.3.8), we can identify the linear coefficients for each terminal charge function. We need to solve a set of linear equations  [Q] = M[C]  (2.3.11)  where [Q] is the charge vector on the four vertices, [C] is the linear coefficients to be identified, and [V] is the vertex matrix mentioned in equation (2.2.7). Since matrix [V] is non-singular, [C] can be found from  [C] = [V]-\Q] .  (2.3.12)  If the original nonlinear charge functions are continuous over the entire voltage space considered, then the PWL charge approximations obtained as above have the following properties [6]:  1.  For any given small number e > 0, a PWL cube division can be chosen such that Qj-Q? \\<e WL  (2.3.13)  exists in the entire region. 2.  The PWL charge functions Q?  WL  are continuous over the entire voltage space considered.  14  Chapter 2.  PWL Modelling of A Four-Terminal Nonlinear Charge Device  Property 1 assures that if the voltage partitioning resolution is small enough, the PWL function approximation will be close enough to the original nonlinear function. Hence, the PWL solution will approach the actual solution of the circuit. By approximating nonlinear charge devices with PWL functions, the nonlinear analysis problem is transformed into a linear analysis problem in the large-signal sense within each PWL region. This transformation greatly simplifies the time domain solution of a circuit which involves such devices. This aspect will be shown in the next chapter.  15  Chapter 3.  Time Domain Solution Algorithm of PWL Circuits  Chapter 3 Time Domain Solution Algorithm of PWL Circuits Time domain solution of nonlinear circuits involves discretization and linearizatioa For PWL systems, since the characteristics of the nonlinear devices have been modelled by linear functions within each PWL region, the solution process at each time point is a straight-forward linear analysis. To ensure the proper representation of PWL models of nonlinear devices, the crucial point is to check the position of the solution vectors.  3.1 Time domain solution of PWL models In time domain circuit simulation, discretized i-v relationships for each PWL device have to be found in order to form circuit equations. The terminal currents for the charge device are given by the definition  j  (3.1.1)  dt j = a,b,c,d  .  All the terminal charges are nonlinear functions of controlling voltages v b(t), v (t) and v d(t). a  ac  a  Note that although the nonlinear charges have been linearized by PWL functions, the PWL linear expressions of die charges can't be substituted into the differential relations above because the PWL functions are not purely linear functions over the entire range of the voltage space. During the solution process, the linear capacitive coefficients are changing from one PWL region to another. This fact has to be included in the time domain discretization process by using the charge variable directly instead of its linear expression. Applying the trapezoidal integration rule to directly discretize the first-order differential equations in (3.1.1), we get 16  Chapter 3.  Time Domain Solution Algorithm of PWL Circuits  " h'f'V ~ l > Q  ~ -' ~  WL(t  At)  j — a,b,c,d .  { {t  M)  (3.1.2)  Rewriting into a compact form, we obtain  =  +  ( 3  .  U )  j = a, 6, c, d , where I j represents the last two terms in equation (3.1.2). Substituting Qj" , j=a,b,c,d, into WL  n  equation (3.1.3), we get linear relationships between terminal currents ij and terminal voltages Vj.  ij{t) = Gjiv {t) + Gj2v (t) + Gjtv (t) + Gj4v (t) + Ij a  b  c  j = a,b,c,d ,  d  (3.1.4)  where the linear coefficients are provided by the following relations: 2  G  *  =  -Ei * C  (3.1.5)  2 T  i = -frfii<> + hj  j = a,b,c,d . Note that since i + if, + i + id = 0 , we only need to obtain the coefficients for three of the four a  c  terminal currents. The linear coefficients of the other terminal current, say id, can be obtained by the following relations: 17  Chapter 3.  Time Domain Solution Algorithm of PWL Circuits  Gd\ = -(Gal + Gbi + Gci)  +  Gd2 = ~(G 2 + Gw a  G 2) C  G * = - ( G « + GM + Gts) d  3  GdA — ~(G A + G\,\ A  +  (3.1.6)  G A) C  I = ~(I + h + Ic) • d  a  Next, before presenting the PWL solution algorithm, we first review the commonly used Newton's iteration solution algorithm for nonlinear circuit simulations.  3.2 Newton's iteration solution algorithm Assume the nonlinear terminal charges have not been linearized by PWL functions. Applying Taylor's expansion to the discretized terminal current equation (3.1.3) and discarding the higherorder terms, we get dQ (t)] 3  Vk(t) =  ft  H(t) - vict)]  !>*(*) J  v (t),v (t),v (t) ab  j = a,b,c,d  ac  (3.2.7)  ad  ,  where superscript "0" represents previous iterative values; and "1" represents the current iterative variables to be found by solving the circuit equations. J}(t), j = a,b,c,d, can be obtained by inserting v%(t), k = ab,ac,ad, into the discretized terminal current expressions as follows:  (3.2.8) j = a, 6, c, d . Equation (3.2.7) can be rewritten into a more compact form as follows: 18  Chapter 3.  Time Domain Solution Algorithm of PWL Circuits  i)(t) = Pjivfo) + P vl(t) + Pjwl(t) + Pjiv {t) + IN, l  j2  d  j = a,b,c,d ,  (3.2.9)  where the linear parameters are provided from -|0  2 v-^ dQj(t) dv (t)\ k  Vk  Pj2 = ~  _2_ dQj(t) At dv (t) ab  P  dQjjt) » = -At dv (t) ac  (3.2.10)  dQjjt) At [dv (t) ad  dv (t)\  Vk(t) =  V  k  W  k  Vk  v (t),v (t),v (t) ab  ac  j = a,b,c,d  ad  .  Comparing equation (3.2.10) with equation (3.1.5), we can see that the Newton's iteration expressions have a similar form to i-v relations such as the PWL i-v relations. The difference is in the linear parameters. In Newton's iteration, the parameters are obtained from local derivatives of the nonlinear charge functions, while in the PWL method, the parameters are obtained from interpolation on the vertices of the PWL region. Intuitively, when the PWL voltage space partitioning resolutions tend to be infinitively high, the differences between the two methods disappear. Assume now that the only type of nonlinear device in the circuit is the charge device we discussed above. The time domain solution algorithm using Newton's iteration as nonlinear equation solver proceeds as follows:  19  Chapter 3.  Time Domain Solution Algorithm of PWL Circuits  Newton's iterationtimedomain solution algorithm  Step 1) Assign initial values for node voltages and currents. These values are usually taken from those at last time point. Step 2) Replace nonlinear terminal currents by linear equation (3.2.9), form circuit equations by nodal analysis approach. Step 3) Solve the circuit's linear equations. Step 4) Check the convergence of the solutioa If converged, go to step 5; if not, update voltages, go to step 2. Step 5) Increase time t by a step At. Go to step 1.  These steps continue until the pre-specified simulation time is reached. Two factors are essential for Newton's iteration to achieve quadratic convergence rate [32][36][33][4]. The first one is that the initial values of the node voltages should be close enough to the real solution. In the DC operating point analysis of an arbitrary circuit, it is difficult to assign initial node voltages close enough to the real solution for the nonlinear devices in a computer-aided solution. In time domain analysis, the initial guess voltages can be taken as the solutions at the last time step, and therefore, it is generally possible to achieve a good closeness of the initial voltages by reducing the discretization time step size. The other factor relates to the nonlinear charge functions themselves. Good models are at least continuous as a function of each of the controlling voltage variables. Usually the continuity of the derivatives of the nonlinear charge functions is required for the entire working voltage space, since the circuit variables may stray into every possible voltage areas during Newton's iteration.  Hence, nonlinear charge functions should be smoothly continuous over the entire  considered voltage space. This requirement limits the applicability of analytical modelling of modern electronic devices, such as MOSFET, in circuit transient analysis because these devices are intrinsically nonlinear in both of their DC and A C aspects. 20  Chapter 3.  Time Domain Solution Algorithm of PWL Circuits  There have been many published works dealing with techniques in multidimensional space for surface smoothing of nonlinear functions. These techniques can be applied to the nonlinear functions and the smoothed functions used in the Newton's iteration.  In general, however,  without proper conditioning, simulations using Newton's iteration may take a relatively long time to achieve a reasonable convergence, or may even fail to converge. An alternative to using nonlinear analytical charge functions in time domain simulations is to use PWL approximations to represent the nonlinear characteristics of the charge device. Since only linear algebraic analysis techniques are involved in a PWL circuit simulation, the simulation speed is expected to improve rapidly as compared to Newton's iteration algorithm .  3.3 P W L solution algorithm In the DC analysis of a resistive circuit , two PWL modelling and solution algorithms have been widely used. One is the Katzenelson's method [6][7][31], and the other is the Newton-like iteration method [8]. Both of them are iterative solution methods. Katzenelson's method makes extensive searches through the whole range of the concerned voltage space. It is an iterative algorithm, and although it always can find a solution, the searching for this solution may take a long time. Also it is tedious in determining the parameter A [31] used to force the next iterative guess point to be exactly on the PWL region's boundary. Newton-like iteration faces similar problems of failing to converge to the real PWL solution  as die Newton's iteration does [8]. In the method of PWL Newton's iteration solution, the criteria for convergence is judged by the fact that the iterative solution is falling within the same PWL region of the last iterative solution. If the iterative solution cannot fall within the PWL region of the last iterative solution, the divergence form will be such that the iterative solutions are cyclic through a series of identical PWL regions [8]. Unlike the iterative PWL solutions, we expand the single dimension PWL direct solution method of [33] into a multidimensional PWL solution scheme.  21  Chapter 3.  Time Domain Solution Algorithm of PWL Circuits  PWL direct solution algorithm  Step 1) Assign initial node voltages and currents for the dynamic elements. Step 2) Determine the PWL regions for each nonlinear device and get the linear parameters of the PWL models. Step 3) Form the circuit equations and solve for the node voltages. Step 4) Check if all the PWL devices stay in their previous regions. If all the PWL devices stay in their previous regions, increase time t by At, go to step 3; if there is a PWL region change of any PWL devices, go to step 5. Step 5) Switch integration rule to BE rule. Carry out two steps of BE integration. 5.1) Increase time t by At / 2. Use the BE integration rule to discretize the PWL charge device. Repeat step 2 and step 3. 5.2) Check the PWL regions for each PWL charge device. 5.3) Repeat steps 5.1 and 5.2. If there is any change of PWL regions during the two steps of BE integration, repeat step 5; if there is no PWL region change, switch back to normal trapezoidal integration rule and go to step 3. The algorithm continues until the pre-specified simulation time is reached.  Remarks on PWL direct algorithm: 1) The solution is accurate if PWL devices stay in the same region in two consecutive solution steps. 2) There is no iteration in rinding the solution if the current solution reaches out of the present PWL region. Instead, a linear extrapolation of the present PWL region is employed to find an approximate solution. Hence, caution should be taken in choosing the integration time step size in order to minimize the overshoot error incurred by the extrapolation approximation. 3) Two consecutive BE integration rules are introduced if there is a switch of PWL regions in order to suppress the numerical oscillations that occur in the trapezoidal integration solutions. 4) PWL modelling and direct solution algorithm translates a nonlinear problem into a linear one by piecewise linearization of nonlinear device functions. There is no need to require the original nonlinear device functions to be smoothly continuous 22  Chapter 3.  Time Domain Solution Algorithm of PWL Circuits  over the entire voltage space. A compromise between solution speed and accuracy can be freely determined by the user. 5) This algorithm is compatible with the electric circuits simulation program EMTP [13], which is a fixed time step size simulator. The device models can be directly implemented into the EMTP. In the following chapters, we will use this algorithm to model and simulate mtrinsic MOSFET devices in a circuit environment and to compare the results with those obtained by a Newton's iteration algorithm.  3.4 Location of PWL regions during the transient solution As has been noted, the three-dimensional voltage space is partitioned into a bulk of PWL regions which are non-overlapping polyhedrons. If at the present solution point t, the controlling voltage vector of a nonlinear device is found outside the current PWL region, the location of the new PWL region has to be identified. Here we illustrate this in a two-dimensional plane because it is cumbersome to graphically describe it in the three-dimensional space. The procedure of locating PWL regions in the three-dimensional space is similar to that in the two-dimensional plane. Figure 3.4.1 shows a two-dimensional voltage plane. The plane has been partitioned into rectangles. Each rectangular area is divided into two triangles. A single triangle area, including the boundaries, is a PWL region Assume the present controlling voltage vector is located in one of the triangles as shown by a dot at the starting point of the arrows. Referring to Figure 3.4.1, the following situations can happen: Case 1) If the voltage vector is shifting to positions 5, 6 and 7, the voltage vector is still in the same PWL region. Case 2) If the voltage vector is shifting to positions 1, 3 and 4, the voltage vector then belongs to the upper triangle PWL region in the same rectangle. Case 3) If the voltage vector is shifting onto any triangular area of a rectangle other than that of itself, the new PWL region is assigned to be the lower triangle. 23  Chapter 3.  Time Domain Solution Algorithm of PWL Circuits  /  1  7  /  /  Figure 3.4.1 Location of PWL regions on a plane  In the three-dimensional space, we can similarly deal with the cube and the six PWL polyhedral regions as shown in figure 2.2.2.  24  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  Chapter 4  Intrinsic MOSFET PWL Modelling and Circuit Simulation There has been a lot of literature published presenting intrinsic MOSFET models. There are two directions in this area. One is to model the device physics and use numerical methods to solve the nonlinear physical equations directly. This branch is usually branded as device simulation. The other modelling methodology of MOSFET devices, which has been used in almost all of the popular circuit simulators, is based on building an equivalent circuit for the device. Device simulation can accurately represent the physical process happening in the device, but it is hard to couple the representation with the external circuit equations. Equivalent circuit methods have been used widely in the past years to simulate the circuit behaviors of MOSFETs in ICs. Intrinsic MOSFETs are modelled by a DC channel current and a set of dynamic capacitive charge components. They are all nonlinear functions. 4.1 Intrinsic MOSFET devices Intrinsic MOSFET devices are composed of four terminals and a conducting channel. Each terminal is associated with a part of the device area. The surface state of the channel is controlled by the voltages applied on the terminals. The channel current is a nonlinear function of the terminal voltages characterized by the square-law. It can be modelled by a voltage-controlled current source under the quasi-static assumption. A cross sectional view of an n-type MOSFET device is shown in Figure 4.1.1 . In Figure 4.1.1, g,s,d,b represent the each device's terminal. Qg, Qs and Qb are three spacedistributed charges inside the device. They are responsible for the transient charging currents on the terminals. Apart from these capacitive charging currents, the channel current ids plays the most important role for transient analysis under several assumptions. One of the major assumptions is the quasi-static assumption, which means that the channel current and all the space charges are instantaneously reacting to the variation of terminal voltages. Obviously this assumption implies that the variation rate of die applied external terminal voltages should be in the low range of 25  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  frequencies. If the working frequency of the MOSFET is too high, a modified model for the charges and currents should be pursued without the quasi-static assumption. Our modelling and solution method is concerned mostly about the numerical solution of nonlinear models rather than the physical details of the device. Once the analytical form of a nonlinear model of charges and currents can be found by non quasi-static approaches, our solution method will still be applicable. z  y  Figure 4.1.1 A cross sectional view of the intrinsic NMOSFET  Another point we would like to mention refers to the charge conservation problem during transient simulation of MOSFET circuits. This problem, as indicated in [8], arises from the mistreatment of the nonlinearity of small-signal MOSFET mutual terminal capacitances in Meyer's capacitance model [33].  Since we are using a nonlinear charge model direcdy before  the time domain discretization of terminal current, this problem does not arise in out model. Before using the PWL technique to model the nonlinear analytical functions of the device, we first look at the equations of the MOSFET's intrinsic nonlinear charges and channel current. 26  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  4 . 2 Review of modelling of  M O S F E T  device  A first-order MOSFET model from [25] is presented below. The channel charge density q (x) is given by Poisson's equation c  q (x) = C c  ox  v,'cs(x) -v  g  + VFB + 2<t>F + 7\/v (x) - v + 2(f>r cs  b  (4.2.1)  under the following assumptions: 1.  quasi-static assumption  2.  uniform channel approximation  3.  one dimensional depletion approximation  4.  strong inversion approximation  5.  electron mobility is constant along the channel  6.  electron current is in the x dimension only  7.  hole current is negligible  8.  substrate is uniformly doped  9.  recombination is negligible .  The channel transport current is given as follows under the same assumptions, dv, Ld (x) = -fiWq (x) 'cs dx s  where C  ox  c  (4.2.2)  is the oxide linear capacitance per unit area; v (x) is the channel to source terminal cs  voltage drop; VFB is the device flat band voltage; 4>p is the Fermi level of the semiconductor surface; 7 is the body effect factor, and W is the width of the channel. The charge continuity assumption in the channel leads to the following charge partitioning equations  (4.2.3)  27  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  <W(*) = jQc(x)  (4.2.4)  where L is the length of the channel. Note that q = q + q . Choosing the gate terminal as the c  a  d  positive reference terminal, Vcs(x) = V (x) - V c  s  (4.2.5) = -Vgc(x) + V  gs  .  Changing variables in the channel charge equation (4.2.1) and transport current equation (4.2.2), we get du q (x) = -C [v (x) c  ox  J^2(f>  + v  F  - (V  gc  -  gb  + 24 )-  FB  (4.2.6)  F  Vg (x)} C  q contains two distinctive parts, q and qi,. These charges satisfy the charge neutral condition of c  g  the device  q + q + qb = 0 c  (4.2.7)  g  where q and qb are gate charge density and substrate charge density, respectively, g  q (x) = C [v (x) - (V B + 2(f) )} g  ox  <,(X) =  gc  F  -lC yj2(j) 0X  F  F  (4.2.8)  + V  -  gb  Vg (x) C  The further assumption of constant substrate charge density eliminates variable x out of v (x) gc  in qb(x) and v (x) can be replaced by v . The device threshold voltage is denned as follows gc  g3  Vi (v , v ) ga  gb  = V  FB  + 2<f> + F  28  7  ^2<f> + v -v F  gb  gs  (4.2.9)  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  and denote Vgct = "go  -v Vgdt = gd -v Vg t = Vg -v Vgst = Vgs  t  (4.2.10)  v  b  b  t  t  Finally, we can get the needed terminal charge densities for the calculation of the terminal charges, q {x) =  -C v t(x)  c  ox  q (x) = ( l s  Qd(x) = q (x) g  qb —  gc  j)<lc(x)  jq (x)  (4.2.11)  c  =C  ox  Vg i(x) + Jyj2<t>f + Vgbt - Vg t C  -CoxiyZ^F  S  + Vgbt  - Vgst  and the channel transport current dvg t(x)  Ids = tiWq (x)c  C  dx  (4.2.12)  Integrating the charge densities and channel current along the channel dimension from x = 0 to x = L, we can get the total terminal charges and the channel current ( see appendix A ). Note that the charge densities above are obtained under the assumption that the device is working in the linear region. When the device works in other operational regions, such as the cut-off region or the pinch-off region, those charge densities will be different. In appendix A, the total terminal charges are given for all the operational regions of the device. An equivalent circuit can now be built for transients analysis of the MOSFET's intrinsic device charges and current. This circuit is shown in Figure 4.2.2.  29  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  Qgs Cgso  Cgdo Qb  Qs  Qd  Cgbq  Ids  II  Csb  Cdb  Figure 4.2.2 Equivalent circuit of intrinsic MOSFET device  In the circuit of figure 4.2.2 the nonlinear capacitors are represented by charges Q  gs  = —Q , 3  Q d = —Qdi and Q b = —Qb- The capacitors in dotted lines represent the parasitic capacitive g  g  elements in the device. The nonlinear capacitances in the equivalent circuit model the space charge effects of the device. The voltage-controlled current source models the channel transport current Notice that the nonlinear capacitances are modelled by charges directly and that the sum of the three charges on the nonlinear capacitors equals the gate charge with opposite polarity. Therefore, the charge conservation law still holds.  43  P W L representations of M O S F E T terminal currents The PWL modelling and solution algorithm introduced in chapter 3 can be applied directly  to the four-terminal nonlinear charges and channel current of the MOSFET intrinsic device. The terminal currents are the sum of charging currents and transport currents.  30  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  For the source terminal current i (t), s  i (t) s  = -ig (t)  - Ids(t) ~ icgso(t) + i b(t)  S  3  ,  (4.3.13)  where  ^ s(t) = ^  (4-3.14)  9  •wo = c^^r i s b ^ ^ C ^  -  (43 15)  .  (4.3.16)  Both Q (t) and Ids(t) are nonlinear functions of v (t), v d(t) and v b(t). gs  gs  g  g  Applying the trapezoidal rule to discretize the differential equations, we get  tgs(t) = -£j(Qgs(t)  ~ Qgs(t - At)) - i (t gs  - At)  (4.3.17)  2C icgso(t) = -^.(  (t)  Vgs  - v (t - At)) - i (t gs  cgso  isb(t) = ^%r(v,b(t) ~ v (t - At)) - i (t sb  sb  (4.3.18)  - At)  - At)  .  (4.3.19)  Substituting the discretized currents into i (t), s  = ~  is(t)  J  T  + C gsoVgs(t) C  - C (t)v (t)} sb  sb  + IH - I (t) a  ds  ,  (4.3.20)  where IH is called the " history term" and it is given by the values of circuit variables at S  previous time point t-At, 31  Intrinsic MOSFET PWL Modelling and Circuit Simulation  Chapter 4.  IH  S  1 2C = —Q (t - At) + i (t - At) + —^v {t - At) gs  A  g3  gs  t  A 2  (4.3.21)  t  C  + i (t - At) - -£fv (t cgso  - At) - i (t - At)  sb  .  sb  For PWL modelling, the nonlinear charge Q and the nonlinear current I are approximated by ga  da  PWL functions as follows  ds ( )  I  Q  WL  = GgsVgsi*) + G v (t) + G v {t) + I  t  gd  gd  gb  gb  = CsWgsit) + C v (t) + C w (t) + Q  WL ga  s2  gd  s  (4.3.22)  dso  gb  gso  .  (4.3.23)  Substituting these PWL functions into equation (4.3.20), we get the expression for the linearized source terminal current as follows:  i (t) = h v (t) + h v (t) + h w (t) + h v (t) + I s  sl  g  s2  s  s  d  s4  b  s  ,  (4.3.24)  where the linear coefficients are given by 2 2 h l = - ~£^(C \ + C 2 + C 3) - -£^C s  S  3  S  — (G + G + G ) 2 2 2 h 2 - -r~.Csi + -j-.Ggso + 2 h ?> = ~£^G + G gs  gd  gb  s  a  a2  2  + Ggs (4.3.25)  gd  2  h 4 — ~£~jp % s  gS0  s  — ~^G b + G s  gb  2 Is = ^Qaso - hso + IHs  The discretized and linearized expressions for the currents in the other three terminals can be obtained similarly to the source terminal current i (t) presented above. Now, since. a  32  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  (4.3.26)  id(t)  •igd(t)  ib(t)  igb(t) - icgbo{t) - isb(t) ~ idb(t)  (4.3.27)  •(«',(*) + i (t) + »,(*))  (4.3.28)  + Ids(t) ~ icgdo(t) + idb(t)  d  after discretization with the trapezoidal rule and linearization by PWL function approximations, the terminal currents can also be expressed as:  id(t)  h  ib(t)  h  + h 4Vb(t) + Id  (4.3.29)  + hh2V (t)  + h^Vd(t) + hbAVb(t) + lb  (4.3.30)  + h 2V (t)  + h Wd(t) + h 4V (t) + I  div (t)  + hd2V (t) + dZV (t)  biv (t)  hgiVgit)  g  g  h  d  s  s  g  s  d  G  g  b  g  (4.3.31)  The linear coefficients for the above terminal current equations are given in appendix B. 4.4 Circuit simulation experiments A simulation program has been written to test the MOSFET equivalent circuit model in nodal analysis approach using both the Newton's iteration and the PWL modelling solutions. The input format of the simulation is similar to that used by SPICE2 [2] for the description of the connection of circuit components. The CDA [34] integration scheme is used for time domain discretization in the PWL solution algorithm. The advantage of this scheme is its capability to dampen numerical oscillations when the controlling voltage variables in the MOSFET device switch from one PWL region into another. For comparison, the trapezoidal integration rule is used with the Newton's iteration nonlinear solution algorithm to simulate the same circuits. The derivative elements in the Jacobian matrix of Newton's iteration are obtained from the central difference formula as follows: dq _ c/(v + Avjo) - q(v dv  2Av; 33  0  AVJ ) 0  (4.4.32)  Chapter 4.  where A V J  0  Intrinsic MOSFET PWL Modelling and Circuit Simulation  is a small positive number representing increment of the voltage vector in the  Vj  dimension. Newton's iteration in which Jacobian matrix is calculated by the central difference formula is called discrete Newton's iteration. The convergence criteria in the simulations is set to be  (4.4.33)  \v) - V j\max < 10" K  where subscript j indicates one of the controlling voltage variables of the nonlinear MOSFET charge functions.  The subscript "max" represents the largest difference value between two  consecutive iterations. Circuit 1 is a single MOSFET inverter as shown infigure4.4.3.  Vout  T»20  us  -5v  Figure 4.4.3 A single MOSFET inverter  To emphasize the effects of nonlinearity and the numerical properties of the CDA scheme and the trapezoidal rule, only the MOSFET equivalent circuit of the intrinsic device, as shown in figure 4.2.2 with solid lines, is used in this simulation . 34  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  Figure 4.4.4 shows the output voltage and MOSFET source terminal current waveforms using Newton's iteration solution when the input signal is a sinusoidal waveform. The simulation integration time step is At=l/is. Numerical oscillations appear in the output voltage and in the source terminal current  The oscillations are superimposed on the correct solutions with  the frequency of the sampling rate ( inverse of integration time step size ). The oscillation amplitudes are accumulating along the cycles of the input waveform. Since there is no linear capacitor in the circuit, and the input is a continuous sinusoidal waveform, the cause of these oscillations must be due to the discretization of nonlinear charges by the trapezoidal integration rule. Every time the input waveform changes from a level of 0 volt to 5 volts, the controlling voltages of the MOSFET nonlinear charges sweep through all the operational regions of the device from cut-off region to linear region until pinch-off region. The nonlinear capacitive effects lead to the numerical osculations when the trapezoidal integration rule is used to approximate the differential equations. We decrease the time step size At to simulate the circuit again. It was found, however, that as the time step size At decreases, the amplitudes of the oscillations also decreases. This effect is shown in Figure 4.4.5 and Figure 4.4.6 ( scale changed) where At=0.5^s and At=0.1^s. It is therefore important in this solution method to make a proper choice of the time step size because of the truncation error imposed by the approximation of the differential equations by the trapezoidal integration rule. Generally, the smaller the time step, the smaller the truncation error. In the solution with the PWL algorithm presented in Figures 4.4.7 to 4.4.9, the partitioning resolution plays an important role in determining time step size. If the resolution is high enough, the PWL approximation will be in good agreement with the original nonlinear charge functions. Figures 4.4.7 to 4.4.9 shows the results of simulating the same MOSFET inverter using PWL algorithm presented in this chapter. As shown in the simulation results using the PWL algorithm, numerical oscillations are completely suppressed. This is due to the CDA procedure which introduces two half-size BE integration steps when the controlling voltage vectors change PWL regions. But as can be seen from these results, the overshoot error of PWL algorithm is also reduced with the decreasing 35  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  time step size. The PWL algorithm also gives much faster computational times than Newton's iteration. Table 1 lists the computation times for the simulation of circuit 1 on a SUN SPARC station l . The simulations were run from* = 0 to t = T  max  2  with the indicated time step size. The last  column in the table is the total CPU computer time.  2  The simulation program is written in Fortran and is by no means optimal. These times include output time at each time step  point.  36  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  Figure 4.4.4 trapezoidal rule, Newton iteration, At=l/iS. above) Input and output voltages; below) Source terminal current  37  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  6  .61  0  1  •  •  •  •  •  •  •  •  0.1  0.2  0.3  0.4  0.5  0.6  0.7  0.8  0.9  1  time ( sec . )  1  xio-«  xio-«  .  1  2  i  0  •  .  •  .  .  .  .  .  .  p  0.1  0.2  0.3  0.4  05  0.6  0.7  0.8  0.9  1  time ( sec . )  Figure 4.4.6  xio-«  trapezoidal rule, Newton iteration, At=0.1/iS. above)  Input and output voltages; below) Source terminal current  39  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  time ( sec . ) Figure 4.4.7 PWL algorithm, At=ljis. above) Input and output voltages; below) Source terminal current  40  xio-«  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  time (sec. ) Figure 4.4.8 PWL algorithm, At=0.5/is. above) Input and output voltages; below) Source terminal current  41  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  Table 1 Computation Times for Circuit 1 Scheme  Step size At (ps) Tmax (PS)  CPU time (s)  PWL  1  400  2.6  Newton  1  400  21.25  PWL  0.5  400  4.74  Newton  0.5  400  37.77  PWL  0.1  100  4.4  Newton  0.1  100  41.55  Circuit 2 is a MOSFET charging circuit, shown infigure4.4.10, which has been used by many authors to check the charge conservation problem of the MOSFET device equivalent circuit.  40u»  Figure 4.4.10 MOSFET charging circuit  We use the same intrinsic MOSFET equivalent circuit in the simulations described previously. Figures 4.4.11 shows the Newton's iteration solution for the voltage on capacitors Ci and C2 and for the source terminal current Figure 4.4.12 shows the results obtained with the proposed PWL algorithm. 43  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  Figure 4.4.11 trapezoidal rule, Newton iteration, At=0.1/js. above) Voltages on capacitors Q and C2 ( they are identical ); below) Source terminal current. 44  Chapter 4.  Intrinsic MOSFET PWL ModelUng and Circuit Simulation  \2 „ >  0)  J  1 0.8 0.6  o >  0.4 0.2  -0.2  3  4  time (sec.) 4  6  xl0-<  xlO*  3  e  c Q>  U U 3 U  2 I 0 -1 -2 -3  -5  •6  3  6  4  time (sec. )  xlO-  4  Figure 4.4.12 PWL algorithm, At=0.1/xs. above) Voltages on capacitors Q and C2 ; below) Source terminal current The simulations were repeated with a larger time step size of 0.2^s with similar results. The 45  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  computation time comparisons are listed in table 2 below.  Table 2 Computation Times for Circuit 2 Scheme  Time step At (ps)Tmax (PS)  CPU time (s)  PWL  0.1  400  16.16  Newton  0.1  400  107.31  PWL  0.2  400  8.98  Newton  0.2  400  67.46  Circuit 3 is a MOSFET switched capacitor network as shown in figure 4.4.13.  Figure 4.4.13 MOSFET switched capacitor  An integration time step of At = 0.2/xs is used. Figure 4.4.14 shows the voltages on capacitors Ci and Cz simulated by the Newton's iteration algorithm. Figure 4.4.15 shows the results obtained with PWL algorithm.  46  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  The simulations were repeated with a reduced time step size of At = 0.1/zs. The results are shown in figures 4.4.16 and 4.4.17. Note in figure 4.4.16, the voltages on Ci and C2 are shown in the upper plot with solid line and dotted line, respectively. In the lower plot the source terminal currents of both MOSFETs are shown with severe numerical oscillations. The same arrangement of simulation results using the PWL algorithm is shown in figure 4.4.17. In figure 4.4.17, the simulated voltage results are very close to those of Newton's iteration algorithm while the numerical oscillations in the source terminal currents are totally suppressed. It was also found that the time step size has non—trivial influence on the simulated waveforms. Referring tofigure4.4.14 andfigure4.4.16, both of them are simulation results with the Newton's iteration algorithm. But the voltage waveforms are different. We may speculate that the reason for this is that the Newton's iteration converges to the different solution points since the discretized finite difference equation of the original differential device equation is a function of time step size At. Table 3 lists computation time comparisons between Newton's iteration and PWL solutions.  Table 3 Computation Times for Circuit 3 CPU time (s)  Scheme  Time step At (ps)Tmax (PS,)  PWL  0.1  800  70.77  Newton  0.1  800  265.74  PWL  0.2  800  37.02  Newton  0.2  800  161.56  47  4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  3  3  4  5  time (sec.)  4  5  time (sec.)  7  6  8  xio-  4  8  6  xio-  4  Figure 4.4.14 trapezoidal rule, Newton iteration, At=0.2/iS. voltages on capacitors Ci{above) and C (below). x  48  Chapter 4.  Intrinsic MOSFET PWL ModelUng and Circuit Simulation  3  4  5  6  7  time (sec.)  a$  o >  Figure 4.4.15 PWL algorithm, Afc=0.2/is. voltages on capacitors Ci(above) and C\(below).  49  8 xlCH  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  Figure 4.4.16 trapezoidal rule, Newton iteration, At=0.1/*s. above) Voltages on capacitors Q and C ; below) Source terminal currents. 2  50  Chapter 4.  Intrinsic MOSFET PWL Modelling and Circuit Simulation  g  i  ~T  7  h.  h.  r\h,h,  h. h, h,  i  r—  h i  h.h.h.1  6  cu  .1...P  cn  •P .-I  o >  J  ..P  J  2  3  4  5  6  7  time (sec.)  8  *" 10  xlO-« lOr  8 -  •  a e <  6 • 4 • 2  c a> n 3  0  -2 -4 • -6 • -8 • 0  3  4  5  time (sec.)  7  8 xl(H  Figure 4.4.17 PWL algorithm, At=0.1/iS. above) Voltages on capacitors Q and C2; below) Source terminal currents.  51  Chapter 5.  Power MOSFET modelling and simulation  Chapter 5  Power MOSFET modelling and simulation In chapter 4, an equivalent circuit was presented to model MOSFET devices in circuit transients analysis. In this chapter, a model is presented for power MOSFETs. In general, in dealing with the transient behavior of solid state electronic devices, it is not always possible to find a suitable equivalent circuit representation for the device and it becomes necessary to solve the device physical equations and couple the solution with the circuit equation [29]. In the case of power MOSFETs, the circuit where these devices are used and the device parameters usually limit the operation to well below microwave frequencies [19]. One can then assume that at any moment the device charge densities and channel current are determined by the instantaneous values of the terminal voltages ( quasi-static assumption ).  5.1 VDMOST equivalent circuit for transient analysis The power MOSFET is different from the general small-size MOSFET device in large-scale integrated circuits in terms of both physical structure and analytical characteristics. Some of the main differences are related to the variation property of gate-drain capacitance and of the bodydrain diode in the power device. These differences are important in determining the response of the device in the circuit. Figure 5.1.1 shows a cross sectional structure of a vertical double diffused power MOSFET ( VDMOST) device. The VDMOST is a three terminal device. There is no substrate. Under normal voltage bias, Vd > v„ the channel current flows from drain to source (in fact, the minority carrier in the inversion layer flows from source to drain in the channel ). The transient behavior of the VDMOST is also largely determined by the parasitic capacitances and the packaging inductances. Figure 5.1.2 shows a large-signal equivalent circuit model for this device which includes 11 linear and nonlinear elements. This equivalent circuit has most of the critical parasitic elements in it [19][39].  52  Chapter 5.  Power MOSFET modelling and simulation  Gate  Source  5r Rs  Ids  r  "  1/  Cds  Ids Rd  N-  Drain  Figure 5.1.1 A cross sectional view of a double diffused vertical power MOST. It has a symmetrical structure. The elements of the equivalent circuit are shown on the right half of the device We will discuss each component in the following.  Channel current Ljs The VDMOST channel DC characteristic is modelled by the nonlinear channel current Id and resistances R and Rj. Based on quasi-static assumption, the channel s  s  current is controlled by the terminal voltages instantaneously. 7<f* is governed by the following square-law characteristics [19][39]:  0 v ,i < g  VT  lds = 0  53  (5.1.1)  Power MOSFET modelling and simulation  Chapter 5.  Ld  Figure 5.1.2 Equivalent circuit model of VDMOST for large signal analysis  ii) 0 < v  dti  < v  Sfi  -  V  T  4  iii)  0 < v  tti  -  V  T  <  v  =  fl2^i(v-^)-i]  (5.1.2)  dti  Ids = P(v si ~ VT? , 9  The channel current I  da  internal terminal voltages  (5.1.3)  is a nonlinear function of two controlling voltage variables, the and v : SJI  54  Chapter 5.  Power MOSFET modelling and simulation  i gst  -V  gi  ~ V,  (5.14)  Vdsi = Vdi - V i s  Those voltages are related to the external terminal voltages by Vgi — Vg  Tglg  — Vg  (5.15)  ri 3  3  Vdi — d — d d v  T  %  where T and r are two portions of channel resistance residing in source terminal and drain 3  d  terminal. r is the gate access resistance. In DC state, i = 0, i = -idg  g  s  There are four model parameters to determine for channel current Ids- They are the threshold voltage V j , and /?, r and r<*. s  1.  Determination of V T and /? There exist analytical formulas to compute these parameters [18] and their values could be obtained from the data in the data-sheets of VDMOST product Another way is to measure the device channel characteristics of v  gs  versus Ids in die pinch-off region and deduce the  parameters from the analytical equation (5.1.3) and the measurement curve as shown in [38]. In the pinch-off region, the terminal current is i = -Ids and the drain current is given by s  hs = P(v si - VT)  2  g  = P(v - r I gs  s  - V)  2  ds  T  .(5.1.6)  For small r and Id we can get the following approximate linear relation from equation s  s  (5.1.3)  (5.1.7)  55  Chapter 5.  Power MOSFET modelling and simulation  Then Vr and fj can be deduced from the measurement plot in the lower range of the channel current  2.  Determination of r  s  Again, in the pinch-off region, from equation (5.1.3), we have  =  V -  1_ VP Ids  VT  Ids  (5.1.8)  After obtaining V? and /?, we need only substitute one set of data (v , Vr) to determine ga  this parameter. However, this set of data should be taken at an appropriate measurement point where the Id r drop is significant The authors of [12] neglected this parameter since a  a  it is primarily due to the bonding wire and the metallization and the diffusion layers of the device chip. In the actual device , it may be reduced to the Ohm range.  3.  Determination of rd In the device data-sheets, the static drain-to-source on-state resistance Rd ( ) is provided. a  In the linear region  Rd ( n) a  0  =  T  on  d + Tch + f , where r h is the channel resistance in the linear c  s  operating region. For small Vd„, equation (5.1.2) approximates the channel resistance  rch =  1 0  R  (  v  2j3(v g3  where v { has been approximated by v ga  gs  ,  (5.1.9)  V) T  under the condition of large v . Notice that gs  is  a nonlinear function of v . It is therefore suggested that to more accurately model channel gs  resistances, a more elegant nonlinear function may be used. Dynamic components  There are six dynamic components in this model. They are the gate-  source capacitance C , the gate-drain capacitance C d, the drain-source capacitance C gs  g  da  and the  three terminal inductances. Device data-sheets will give typical parameter values and measured voltage-capacitance curves of three capacitances Cj , C s and C^s, known as input capacitance, SS  56  OS  Chapter 5.  Power MOSFET modelling and simulation  output capacitance and reverse transfer capacitance, respectively. To model the device, we n to know the analytical models of the nonlinear capacitances, C , C j and Cd which will be used gs  g<  g  in the equivalent circuit model. . The author of [38] measured the small-signal characteristics of 3  a VDMOST of the International Rectifier type IRF130 to deduce the relations between terminal bias voltages and capacitances across the terminals. Since those capacitances are obtained based on small-signal measurements, the actual nonlinear charges on these capacitors have to be found in order to be used in the time domain discretization of the charge differential equations. 1.  Determination of the drain-gate capacitance C  d g  The measured drain-to-gate capacitance curve in [38] shows that this capacitance depends on only one controlling voltage v  dg  and it can be approximated by a polynomial function.  We should mention here that since voltage controlled nonlinear capacitances are usually described as small-signal capacitances, from the definition of small signal capacitance, Cd  g  is  C  dg  = ^  .  (5.1.10)  dV g d  To calculate the current in a nonlinear capacitor, we can no longer use the small-signal capacitance directly in the discretization of the differential equation without considering the nonlinearity of the small-signal capacitance. Instead, charges on the nonlinear capacitor should be integrated out and used in the time domain discretization . 4  Qdg = J C dv dg  (5.1.11)  dg  Here for VDMOST, Cd is approximated by a polynomial function g  3  The relation among these capacitances are : d , s  4  =C  gs  +C, C gd  O J J  = C  gd  + C , Ca = C ds  ri  gd  Of course it is better if the nonlinear charge can be found directly without resort to the integration from the small-signal  capacitance.  57  Chapter 5.  Power MOSFET modelling and simulation  n  (5.1.12)  ^2fCd  Cdg =  o where the Cd  gn  are constant capacitive parameters.  They are obtained by fitting the  measurement data with the polynomial function by least-square method. Then the nonlinear charge would be  (5.1.13)  The constant of integration Q ( 0 ) is set to be zero. Note, however, that since the measured s  data are only obtained within a certain range of voltage spans, the application of these data are limited to the corresponding ranges and the specific device measured. 2.  Determination of the drain-source capacitance Q g This small-signal capacitance is largely due to the nonlinear depletion and diffusion capacitances presented by the channel diode. The equivalent circuit for this part infigure5.1.2 is modelled as shown infigure5.1.3.  v  diode  diode  Figure 5.1.3 Nonlinear large-signal capacitance model of C& for VDMOST 58  Power MOSFET modelling and simulation  Chapter 5.  In the circuit of Figure 5.1.3, the diode is modelled by a current source, diode capacitance and internal resistance, C is the parasitic capacitance. The diode capacitance is given by v  (5.1.14)  K  where the first term is the diffusion capacitance, the second term is the depletion capacitance, and vnode is the junction voltage of the diode. Under normal operation, Vdiode < 0 and the diode is turned off. Cd is dominated by the depletion capacitance:  Cd = c (\- -tf^ v  (5.1.15)  d0  When  Vdiode >  0, the diode is working under forward bias, and the second term in equation  (5.1.14) is no longer valid. The diffusion capacitance will dominate Cd and "diode  T C  d  = k  e  (5.1.16)  k  The charge on the nonlinear diode capacitance can now be obtained by integrating the smallsignal capacitance. In order to get a continuous charge function, the condition Qd(0) = 0 has been set in the following integrations.  For v d < 0 dio  e  Qd =  1 Cdo<t>1 1—m  Vdiode  l-m  (5.1.17)  For v i d > 0 d  0  e  Q, = r ( e ^ - l )  59  (5.1.18)  Chapter 5.  3.  Power MOSFET modelling and simulation  Determination of the gate-source capacitance C  g s  Physically, the gate-source capacitance comprises the overlap capacitance, the gate-channel capacitance, and the capacitance through the field oxide of the source overlay. It is largely independent of bias and is treated as a linear constant. Hence the charge on it is simply obtained from Q  4.  93  = Cg v 3  gs  .  Determination of the terminal inductances L , Ls and L g  (5.1.19)  d  These parasitic inductances originate from the device bonding and packaging. They can all be treated as linear components and are given in the device data-sheets for each specific VDMOST.  Other components The last two elements, the gate access resistance r and channel diode g  current idiode need to be modelled. 1.  Determination of the gate access resistance r  g  This resistance is very small, but making this parameter zero would affect the delay times, especially when the transistor is driven by a very low impedance circuit. The value of this resistance can be obtained by measuring the time constant of the step response of the gate voltage when the device is operating in the cut-off region [38]. 2.  Modelling of the channel diode current idiode The channel diode current is given by  ^<We = ^ ( e ^ - l )  where  Vdiode  (5.1.20)  is the diode junction voltage. When die VDMOST works in the reverse mode,  i.e., when v ,i < 0, the channel current will be less significant as compared to the channel d  60  Chapter 5.  Power MOSFET modelling and simulation  diode current which is forward biased . v i de and Vd i have the following relation, 5  d 0  v  Vds  where r i de is d 0  m  e  3  diode i I ^diode fy J diode r  (5.1.21)  internal resistance of the diode. The current originated from the diode  nonlinear capacitance, dQd/dt,  can be discretized with the trapezoidal integration rule and  expressed as dQ dt  d  *Qd(0  (5.1.22)  where Idh denotes the history term. Q is a nonlinear function of v<f, - as shown in equations d  od e  (5.1.17) and (5.1.18). However, after linearization by PWL functions, Qd can be expressed as Qd = Cdiode diode + Qdo v  •  (5.1.23)  Substituting the PWL Qd into equation (5.1.22), iQ (t) can be expressed as a linear d  relationship  •5^(0  = 9Q v (t) d  + 4  dtode  (5.1.24)  where the linear coefficients are given by  diode  9Qd  A  o  T  s  T  (5.1.25)  t  _L  n 2  Q  d  °  In fact, almost all of the VDMOST models published did not discuss the channel current under reverse bias mode.  61  Power MOSFET modelling and simulation  Chapter 5.  Hence equation (5.1.21) can be expressed as  Vdsi =  - ( l + gQ rdiode)v'diode ~ {jdiode + hj diode T  r  d  d  •  (5.1.26)  Note that the diode current idiode is also a nonlinear function of Vdi<,de> but it can also be linearized by a PWL function as well. After linearization, Vdiode can be found once Vdsi has been determined. Table 4 lists all the coefficients used in the VDMOST equivalent model [38][18] studied here. Table 4 VDMOST equivalent model parameters  Elements  Values  R  0.005ft  8  0.07ft Rg  4.5ft  Cdg(pF)  Cdgj , j=0 to 5 600, -98.3, 2.7624, 0.51193, -0.036845, 0.00067881  Cdso  HOOpF  k  0.0259  4>  0.7 v  T  200ns  Cg  550pF  c  80pF  s  p  62  Chapter 5.  Power MOSFET modelling and simulation  Table 4 (Continued) VDMOST equivalent model parameters Io  l.lxl0 amp  Tdiode  0.05ft  10  5.5nH, 40nH, 40nH  5.2 PWL modelling and simulation  In this section, the nonlinear elements in the VDMOST equivalent circuit will be modelled by PWL function approximations .  5.2.1  PWL modelling of the channel current Ids  The channel current Ids is a nonlinear function of two internal node voltages, v<f- and v i ts  Ids = Ids(vd i,v i) s  gs  .  gs  (5.2.27)  Compared to the three-dimensional case discussed in the last chapter for a small size MOSFET device, the VDMOST device is much simpler to approximate by PWL functions. Two-dimensional PWL partitioning should be applied to the channel current Figure 5.2.4 shows the triangular partitioning of a two-dimensional voltage plane. The plane is divided into rectangular areas and each rectangle is then divided into two triangular PWL regions.  63  Chapter 5.  Power MOSFET modelling and simulation  9»i  Ydsi  Figure 5.2.4 Two dimensional PWL partitioning In each PWL region, the following form of linear expression of Ids is obtained by interpolating the nonlinear channel current on three vertices of the triangle,  I  5.2.2  ds  = 9lVdsi +  WL  92Vgsi  + Idso .  PWL modelling of the nonlinear capacitances Qd and Q g  (5.2.28)  d  Qd and Qd are both nonlinear capacitors and are single variable controlled. Their PWL g  modelling is thus straight forward. For these one-dimensional charges, the PWL linear expressions are Qdg  WL  = dgVdg + Qdgo C  2  QPWL _ QdiodeVdiodt + Qdo  where the capacidve parameters and charge constants are to be obtained by PWL function interpolation over the two end points of each PWL voltage segment . 64  Chapter 5.  Power MOSFET modelling and simulation  5.2.3 P W L modelling of the diode current The diode current can be expressed in exponential form as in equation (5.1.20)  (5.2.30)  diode  Figure 5.2.5 shows this voltage-current curve. Note that the control variable is the junction voltage v  .  diode  * diode  -Io  Figure 5.2.5 Current characteristics of a diode  The diode current is a highly nonlinear function of the junction voltage. Under forward bias , it increases exponentially, while under reverse bias, it stays near the value of saturation I in 0  opposite direction. At T=300 K, the thermal parameter k is about 0.0259, and a small forward junction voltage will produce quite a large current Overflow problem may be encountered using iterative solution since the iteration solutions may stray into a large forward bias. Due to the heavy nonlinearity of the diode current characteristics, under forward bias diode > 0, we divide the voltage dimension into segments with a resolution of 6\ smaller  v  than the resolution used in reverse bias. The nonlinear characteristic of die diode is linearized in  65  Chapter 5.  Power MOSFET modelling and simulation  each PWL segment by interpolation at the two ends of the segment  S  = QdiodeVdiode + Idiode •  If the forward voltage is over the pre-specified value v  (5.2.31)  ( we choose v  do  do  = 1 volt and 6v = 0.1  volt) , the linearized expression for i i de is used as follows: d 0  _ . didiod,  9diode — dv J diod  /•  R  Vd  (  \  5  2  3  2  )  I diode \ dl  Under reverse bias, a larger PWL division resolution can be chosen since the reverse current is almost constant at the value of saturation current I . 6  0  The relation between v i d  ode  and v^, is described by equation (5.1.26). Substituting  into equation (5.1.26), we obtain the following equation  Vdsi = - ( 1 + 9Q rdiode)Vdiode ~ (d'diode diode + hiode + Idhj diode v  r  d  (5.2.33)  therefore,  Vdsi + [Vdiode + Idh) diode r  v de = dx0  r  ——~r—; 1  + \9Q + d  9  diod€  •  (5234)  )r iode d  The above equation can be rewritten into compact form  Vdiode = dsi av  6  + f]  (5.2.35)  Reverse break down of diode is not considered since the reverse voltage is normally within the rated break down voltage of  the device.  66  Chapter 5.  Power MOSFET modelling and simulation  where a and 77 are given by  a =  1 + (dQd + 9 diode) diode r  4. /Mrrdiode  (T  I diode Tijn J  V=  (5  I  '  236)  + (9Q + 9 diode) diode  1  r  d  5.2.4 VDMOST P W L terminal currents Referring to the equivalent circuit in Figure 5.1.2, the terminal currents of the VDMOST in the time domain are provided by the following relations . _ %  dQd i  dvg i  g  ~  S  dt dt dVdsi . -Vdsi - Vdiode . dQdgi d = P~H~ + ds 1 "77 at rjiode dt dvdsi , -Vdsi - Vdiode dVg j ' p—~T ds i ^gs j, dt rdiode dt g  +  U  g  n  %  s  T  C  1  n L/  T 1  n  (5.2.37)  S  t  They satisfy KCL  (5.2.38)  i + is + id = 0 g  We now apply the trapezoidal rule to equation (5.2.37) to discretize the terminal currents. For i , g  *'</(') = --TlQdgit)  + ir Qdg{t ~ A t ) + i g(t - At) A* + -£- C s[vgs,(t) - v (t - At)} - i (t - At) . A  4  d  t  2  t  9  gsi  67  gs  (5.2.39)  Chapter 5.  Power MOSFET modelling and simulation  Substituting the PWL approximation of Qd into the discretized equation, we can get the following g  circuit equation for the gate terminal current  i (t) = a \v i(t) + a 2V {(t) + a ^v i(t) + I g  g  g  g  s  g  d  ,  g  (5.2.40)  where the parameters are provided by the following relations: 2C,  2C g d  9l  a  =  TAtT + At 2Cg  a  S  At  g2  a , ^ -  (5.2.41)  p  2  h = -£- Qd,o t  + ^- Qd,(t - At) + i (t - At) t  d!  2C  - "^f W < ~ ) ~  - ) •  A t  A t  For Lj, 2C  - W < - At)} - i (t - At)  ii(t) = -£j[vds,(i) +  I  j  ds  (±±J±l^  M +  2 &t  +  Q  diode . r  - i (t - At) dg  i  g  {  t  )  _ 2  Substituting the linearized expressions of Qd > Q , Ids i s  n t o  dg  Q  d  t  (  t  _  A  t  (5-2.42)  )  this equation, the following relation  can be obtained  =(lk  \ At  + 9i + —)  r  diode  )  W O  + WW O  where 7^ is as follows 68  + ^  At  W O  + h  >  (-- ) 5  2  43  Chapter 5.  Power MOSFET modelling and simulation  2C Id = —rjv {t  - A t ) - i (t - At)  iai  d3  r, 2 2 + hso + - — + -TlQdgo ~ -7T.Qdg{i ~ A t ) - i (t - A t ) rdiode At At 1  dg  t - - ) 5  .  2  44  Equation (5.2.43) can be rewritten as a linear combination of node voltages  id(t) = adiv i{i) + a 2V (t) + a ^v (t) + I g  d  si  d  di  ,  d  (5.2.45)  where 2C g d  a  dl = 92-  At .'2C l + a\ a 2 = ~ Hrf + 91 + - 92 V At diode ) (2C , 1+ ^ 2C + \ At r J At P  ,  (5.2.46)  d  r  P  dg  diode  In a similar way we obtain the source terminal current t . But since the terminal currents s  are related by KCL, we can simply find the linear parameters for i from s  i (t) — a iv (t) + a 2v (t) + a ^v (t) + I s  s  g  s  s  s  d  s  ,  (5.2.47)  where the parameters are provided by the following equations -(a i  + a i)  = -(a 2  +a )  g  a  s2  g  d  d2  (5.2.48)  a s = ~(a 3 + a z) s  ff  d  Is = --(Ig + Id) •  69  Chapter 5.  Power MOSFET modelling and simulation  Equations (5.2.47). (5.2.45) and (5.2.40) give the complete PWL forms for the implementation of the internal terminal currents of the VDMOST for nodal analysis. To simulate a complete VDMOST, the terminal resistances R , Rd and R , as well as terminal linear inductances L , a  g  s  Ld and L have to be added to the internal equivalent circuit. g  5.3 Power MOSFET circuit simulation  The simulation circuit is shown infigure5.3.6. It is a VDMOST drive circuit with resistive load.  VDMOST  Figure 5.3.6 VDMOST with resistive load  Figure 5.3.7 shows the simulation results of the VDMOST terminal voltages and currents.  70  Chapter 5.  Power MOSFET modelling and simulation  15  0)  10  r  cn  (0  JJ 5  o > 0  0.5  1  1.5  2.5  3  3.5  4  4.5  Figure 5.3.7 Simulated switching waveforms, from top to bottom: input voltage on gate; output voltage on drain terminal; source terminal current; drain terminal current, At=200ns  71  5  Chapter 6.  Discussions and Conclusion  Chapter 6  Discussions and Conclusion In this thesis, a PWL modelling method has been combined with the very effective CDA integration scheme to simulate the time domain response of nonlinear voltage controlled charge and current devices and circuits. Very good simulation results have been obtained in several MOSFET circuit examples using the PWL direct solution algorithm. Very few works are found in the literature dealing with PWL modelling and simulation of MOSFET devices in which both nonlinear charges and currents are all multidimensional voltage-controlled functions. The proposed PWL solution scheme constitutes a new and effective transient analysis algorithm for nonlinear devices and circuits. In comparison with the conventional Newton's iteration solution algorithms, our approach possesses the following advantages: No C smooth requirement on the nonlinear analytical device model. 1  •  No convergence problem since there is no iteration.  •  Much faster solution speed.  •  Suppression of numerical oscillation while keeping the computational accuracy of the trapezoidal integratioa A high freedom of choosing modelling resolution to get the best compromise between the modelling accuracy and the simulation speed. Since we have inserted two consecutive steps of BE integration rule for the suppression of  numerical oscillations, the simulation is slowed down when the circuit solution switches from one PWL segment combination to another. When the solution stays within the same PWL segment, the integration rule is the trapezoidal rule which is much more accurate than the BE rule. In the linearization aspect of PWL modelling, PWL region extrapolation is employed at the moment of switching regions. This can cause overshoot errors, even though the computational speed is much faster than that of the iterative solution method. Caution should be paid, however, 72  Chapter 6.  Discussions and Conclusion  to the selection of the size of integration step in order to minimize the overshoot error. To get a more accurate circuit solution while maintaining a fast solution speed, future work may have to concentrate on searching for an effective iterative solution method. As for the analytical modelling of MOSFET devices, since all the device models are based on the quasi-static assumption, they are valid only in the lower range of operational frequencies. To simulate higher frequency effects in MOSFET devices and circuits, non-quasi-static device models should be pursued. In spite of the advantages of the proposed PWL algorithm, several important issues remain future researches: •  The effects of overshoot error and its influence on the solutions.  •  The methodology in selecting a proper integration time step which can minimize the overshoot error while maintain a high simulation speed. The study ofrelationsamong discretization error, time step size and overshoot errors.  73  Appendix. A  Appendix A  A First-Order MOSFET Charge Model  A first-order charge analytical model and channel current model are provided by the following piecewise equations [25]:  Normal mode v > v d  1.  s  When Vgb < VFB  - VFB)  Q - C (v g  0  gb  Qb = -C (v b - V ) 0  FB  g  Q =0  (A.1)  s  Qd = 0 lds = 0  2.  When v  gb  > VFB and v  gdt  <v  gat  Qg = C  ol  < 0  \Z(I)  Qb = ~>  + v  n ~ b  V F B  + Vgb - V B F  Qs=0 Qd = 0 lds = 0  74  7  (A.2)  Appendix. A  3.  When v > V gb  FB  and v  gdt  Q  9  <0< v  < v  gst  =Co^v  gbt  +V  g s t  Qb = - C „ ^ v  §  a  - (VFB + 2<f> )}  T  F  +V  i  + 2^)|  - (V  T  FB  Qs — —~^C Vg t 0  (A.3)  S  4 _  pWCoii  ~  4.  When v«, > V t  FB  2L  and 0 < v  gdt  9  <v  S  t  < v  gst  gbt  Qg =Co{[V -(V t  + 2<l> )] +  FB  F  2r  v v gst  Vgst + V  gdt  -  gdt  Vgst + % d t .  Qfc = -C -yyj2<t>F  }  + Vgbt ~ Vgst  0  V  4  gs  (Vgst +  5  (A.5)  U  n ^r a . • Qs = ~ -Z-hvgst + -zVgdt + " 3 5 5 V t + Vgdt 1 VgstVgdtjVgst ~ Vgdt) ^ 1  (A.4)  (A.6)  V )  2  gdt  „ Co A 4 Qd = ~ ~ir[-zVgdt + 7 gst + v  3  5  5  v  f l S  1 VgstVgdtjVgdt ~ Vgst) 2 5  t +  Vgdt  (A.7)  ]  ( l > * i + *V<) s  \lWC , 0X  2  X  75  2  {v] -v] ) 2  st  dt  (A.8)  Appendix. A  Reverse mode v < v d  3  Since the MOSFET is a symmetric device, the roles of the source terminal and drain terminal will be reversed under such bias. The charge and channel current equations of the normal operation model are all valid simply by swapping the voltage variable v to v t, and vice versa. Note, however, that the physical terminals remain the same. g3t  gd  The physical constants used in the calculations are W=50xl0- m 6  L^Oxlfr m 6  <£F=0.33 volt VFB=-1.18 volt 7=1.03 \olt  m  p=100xlQT* m /s 2  T =10- m 9  ox  Kox=3.9 e =8.86xl0- Farad/m 14  o  e x=KoxXe Farad/m 0  0  Cox=€ox/Tx Farad/m  2  0  C =WxLxCox Farad 0  Figures A.1 to A.4 show the surface shape of three nonlinear charges and the nonlinear channel current under the condition of v b — 0 volts. g  76  A  pp  endix  A  7?  Charge on Cgb  Vgb=0, DV=2v, Qgb vs. Vgs(-20v,20v),Vgd(-20v.20v)  Figure A.3 Substrate terminal charge Qb channel current Ids  Vgb=0, DV=2v, Ids vs. Vgs(-20v,20v),Vgd(-20v,20v)  Figure A.4 Channel current Ids  78  Appendix. B  Appendix B  PWL Coefficients for MOSFET Terminal Currents The linear coefficients of the drain, substrate and gate currents for time domain analysis using the trapezoidal integration rule are given below. Drain terminal id 2  2 + Cd2 + CM) -  hdi = ~~£^\Cd\ (Ggs + Ggd + hd2 — ~£^C l  g  Ggb) -  d  -^C do+  Ggs  2  2  d  + -^.Cdb  g  2  (B.l)  2  h % = ~£^Cd2 + ~^C do  - Ggd  2  hdi = ~£^Gd?,  -  ~^Gdb  -  Ggb  2  h = ~~^Qado + hso + IHd Substrate terminal i  b  2  = ~~At(Gbi h2  = ^-Cbl ~ ^ C  h* = b  X  C  b  2  2  + Cb2 + Cba) -  -  x  2  C  d  -£^C bo g  s h  b  (B.2)  2  ^64 = ~^GbZ + ~£^{Ggbo  + Cb + s  C b) d  2  h = ~~^.Qgt>° + *> IH  Gate terminal i  g  hi  = -(h-si  h2  =  g  g  hgi = h4 g  + h \ +  hb\)  h2 +  h )  d  -(^2  +  -(ha  + h* +  d  d  b2  h z) b  = — (/i 4 + hd\ + hbA)  Ig = -(I  s  s  +I  d  79  +  I) b  (B.3)  References [I] P. K. Ko B. J. Sheu, D. L. Scharfetter and M. C. Jeng. Bsim: Berkeley short-channel igfet model for mos transistors. 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