ANALYSIS AND EVALUATION OF THREE SYMBOL TIMING RECOVERY TECHNIQUES FOR DIGITAL WIRELESS PERSONAL COMMUNICATION SYSTEMS by CHRISTOPHER A. WILLIAMS B. A. Sc. (Hons.), The University of Waterloo, 1991 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES Department of Electrical Engineering We accept this thesis as conforming to the. equired standard Signature(s) removed to protect privacy ThE UNIVERSITY OF BRITISH COLUMBIA July 1994 © Christopher A. Williams, 1994 _______ In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Signature(s) removed to protect privacy Signature(s) removed to protect privacy (Signature) Department of Electrical Engineering The University of British Columbia Vancouver, Canada Date DE-6 (2)88) July 22, 1994 Abstract Abstract This thesis investigates the performance in the presence of CCI and multipath fading of three symbol timing recovery schemes, maximum likelihood (ML) non-data aided (NDA) and data-aided (DA) tracking loops, and a ML block symbol synchronizer, for QPSK, it/4—shift DQPSK, and 16—QAM modulation schemes. In the first part of the thesis, analysis of the three symbol synchronizers in a combined AWGN and CCI environment is performed, based on a linear assumption for small jitter, and expressions for RMS symbol timing jitter are presented for each technique, assuming Nyquist pulse shaping. Computer simulations are also performed in order to validate the results and pro vide bit-error rate (BER) performance of each synchronizer. CCI was found to be the chief limit on symbol timing jitter performance at high signal-to-noise ratios (SNR) for all three synchronizers. Simulations matched theory in most cases, except where the linear assumption is no longer valid. Simulation showed that for carrier-to-interference (C/I) ratios of 10 dB, CCI effects on symbol timing recovery result in negligible BER degradation over ideal sampling. The second part of the thesis investigates the three symbol synchronizers in a fading envi ronment. Irreducahie BER and RMS timing jitter estimates were made by computer simulation using it/4—shift DQPSK modulation in frequency non-selective Rayleigh and Ricean fading, as well as in frequency selective fading. Rayleigh fading had little effect on symbol timing jitter at high SNR unless the fading was extremely fast, that is where the fading bandwidth (BF) times the information symbol duration (T) product is relatively high (i.e. BT>O. 1), and had no noticeable effect on irreducable BER for the range simulated. In frequency selective fading with a two-ray model, the synchronizers were observed to track the optimum sampling instant well at high SNR, Li Absraci for delay spreads of the two-ray model used of td < 0.21 For more severe fading (i.e. td> 0.27), the Ml. block synchronizer performed best, tracking the optimum sampling instant with no increase in the irreducahie BER until td = T/2. The Ml. NDA technique was found to be the worst performer for frequency selective multipath fading, with double the irreducable BER in the worst case simulated. U’ Table of Contents Abstract .1 Table of Contents iv viii List of Tables & List of Figures Acknowledgments xiii 1 introduction 1 1 .1 Modulation Schemes 2 1.2 Wireless Personal Telecommunication Channels 3 1.2.1 Co-Channel Interference (CCI) 3 1.2.2 Multipath Fading 4 1.3 Symbol Timing Recovery Techniques 7 1.3.1 Measures of Symbol Timing Recovery Performance 8 1.3.2 Symbol Timing Estimation Techniques 8 1 .3.3 Timing Recovery in Wireless Communication Channels 9 1.4 Thesis Research Objectives 10 1 .5 Organization of Thesis 11 2 Symbol Synchronization Principles 14 2.1 Introduction 14 2.2 The Symbol Timing Recovery Process 15 2.2.1 Cyclostationary Processes in Timing Recovery 15 2.2.2 Symbol Timing Jitter in Symbol Synchronization 16 iv 2.2.3 Effects of Symbol Timing Jitter on Receiver BER Performance 17 18 2.3 Maximum Likelihood Estimation 2.3.1 ML Non-Data Aided Estimation 19 2.3.2 ML Data Aided Estimation 20 2.3.3 ML Block Estimation 21 2.4 Analysis of Symbol Synchronization Techniques 23 2.4.1 Phase-Lock Loop Theory for the NDA Implementation 23 2.4.2 Phase-Lock Loop Theory for the DA Implementation 27 2.4.3 Symbol Block Synchronizers 29 31 2.5 Summary 3 Symbol Synchronization Analysis in CCI Channels 32 3.1 Introduction 32 3.2 System Model 33 3.2.1 Transmitter Model 33 3.2.2 Receiver Structure 34 3.2.3 Co-Channel Interference Model 35 3.3 Analysis of the ML Non-Data Aided (NDA) Synchronizer 37 3.4 Analysis of Data Aided Synchronizers 43 3.4.1 Maximum Likelihood Data Aided Synchronizer 43 3.4.2 Modified Maximum Likelihood DA Synchronizer Analysis 45 3.4.3 Results of ML and MML DA Jitter Performance Analysis 47 3.5 Analysis of the ML Block Synchronizer 49 3.6 Summary 52 4 Computer Simulation of Symbol Synchronization in CCI V 54 4.1 Introduction .54 4.2 Computer Simulation System Description 54 4.2.1 Description of the ML NDA and DA Tracking Loop Simulations 56 4.2.2 Description of the ML Block Simulations 59 4.3 ML NDA Synchronizer Simulation Results 59 4.4 ML DA Simulation Results 66 4.5 ML Block Synchronizer Simulation Results 72 4.6 Summary 75 5 Symbol Synchronization in Multipath Fast Fading Channels 78 5.1 Introduction 78 5.2 Fading Models 80 5.2.1 Frequency Non-Selective (Flat) Fading Model Description.... 80 5.2.2 Frequency Selective Fading Model Description 5.3 Simulation Results and Discussion 82 83 5.3.1 Fast Frequency Non-Selective Fading 83 5.3.2 Fast Frequency Selective Fading 89 95 5.4 Summary 6 Conclusions and Suggestions for Further Research 97 97 6.1 Conclusions 6.2 Suggestions for Further Research 101 6.2.1 Effects of CCI and multipath fading on tracking loop acquisition time 101 and cycle slipping 6.2.2 Performance of fast acquisition digital tracking loops in fading and 102 CCI vi cE 6.2.3 Effects of slow fading on system performance . 102 103 Bibliography Appendix A: Derivation of ML NDA Synchronizer Timing Jitter in CCI.. 109 Appendix B: Simulation Error in Timing Jitter Measurements vu 113 List of Tables Table 1: Effect of symbol synchronization error on BER performance compared to SNR for ideal timing, for coherently demodulated BPSK (from [10]) 17 Table 2: Effect of sampling rate on minimum possible jitter at high SNR (no noise 51 Table 3: Simulation Error vs. excess bandwidth c, ML NDA synchronization with QPSK modulation, C/I= 10 dB, 2BLT=0.0065, and no noise 65 Table 4: Simulation Error vs. excess bandwidth, ML DA synchronization, for QPSK modulation, C/I= 10 dB,, 2BLT=0.008, and no noise 71 Table B.1: Simulation error in estimating normalized RMS Timing Jitter, 128 samples per symbol 115 VII’ List of Figures Figure 1: Signal constellations for modulation schemes under consideration. (a) QPSK, (b) it/4—shift DQPSK, (c) 1 6—QAM 2 Figure 2: lS-54 TDMA half-rate frame structure (from [6]) 3 Figure 3: A typical channel power delay spread profile for an urban environment Figure 4: ML non-data aided symbol timing tracking loop [31] . 6 19 Figure 5: Data-aided symbol timing tracking loop. (DD) is decision device, (SPC) is parallel-to-serial converter for output data sequence, (NCC) is number controlled counter [31] 21 Figure 6: Block diagram of ML block synchronization scheme 22 Figure 7: Comparison of signal constellation for ML block synchronization using (a) symbol constellation, and (b) differential symbol constellation, for iv /4—shift DQPSK signalling 23 Figure 8: A general symbol synchronizer as a PLL. F(f) is a loop filter, and VCC is a Voltage Controlled Clock 24 Figure 9: Illustration of timing wave variance for (a) wide-sense stationary and (b) wide-sense CS inputs to the filter-square-filter ML NDA synchronizer. 0 represents a possible bias in the estimation 26 process Figure 10: Block diagram of the baseband system model. (a) Transmitter, (b) 33 Channel, (c) Receiver ix Figure 11: ML NDA QPSK Synchronizer: Normalized RMS timing jitter vs. SNR, 2BL=1 /1 00, and Butterworth G(f) with 11(107) bandwidth 41 Figure 12: ML NDA Synchronizer for QPSK: Normalized RMS timing jitter vs. excess bandwidth a, SNR = 15 dB 42 Figure 13: DA ML and MML Synchronizers for QPSK: Normalized RMS timing jitter vs. SNR, 2BLT=l/l00, a=0.35 48 Figure 14: ML and MML DA Synchronizers for QPSK: Normalized RMS timing jitter vs. excess bandwidth a, for 2BLT=1I100, and no noise 49 Figure 15: DA block synchronizer performance for QPSK: Normalized RMS timing jitter vs. SNR for a=0.35 and 16 samples/symbol 52 Figure 16: Block diagram of model for computer simulation 55 Figure 17: Typical sampling time error during acquisition for two simulations: ML DA QPSK synchronization with no noise, and SNR = 0 dB 57 Figure 18: Simulation results for ML NDA QPSK scheme: Normalized RMS timing jitter vs. SNR, 2BLT=0.0065, a=0.35, and 128 samples? symbol 62 Figure 19: Simulation results for ML NDA it/4—shift DQPSK scheme: Normalized RMS timing jitter vs. SNR, 2BLT=0.0065, a=0.35, and 128 samples/symbol 63 Figure 20: Simulation results for ML NDA 16—QAM scheme: Normalized RMS timing jitter vs. SNR, 2BLT=0.0065, cz=0.35, and 128 samples? symbol 64 Figure 21: Simulation results for ML DA QPSK scheme: Normalized RMS timing jitter vs. SNR, 2BLT=O.008, a=0.35, and 128 samples/symbol. x 68 Figure 22: Simulation results for ML DA ir/4—shift DQPSK scheme: Normalized RMS timing jitter vs. SNR, 2BLT=0.008, a=0.35, and 128 69 samples/symbol Figure 23: Simulation results for ML DA 1 6—QAM scheme: Normalized RMS timing jitter vs. SNR, 2BLT=0.008, cz=0.35, and 128 samples! 70 symbol Figure 24: ML Differential Symbol Block Synchronizer for ir/4—shift DQPSK: Comparison of 32 and 64 block length synchronizers in CCI, a=O.35, and 16 samples per symbol 73 Figure 25: Bit error rate performance for block synchronizer and irI4—shift DQPSK modulation scheme, a=O.35 and 16 samples/symbol Figure 26: Block diagram of fading process generation for simulation 74 81 Figure 27: Block diagram of generation of a frequency-selective faded signal for 83 simulation Figure 28: Symbol timing recovery performance in frequency non-selective Rayleigh and Ricean fading for the 3 synchronization schemes, no noise 86 Figure 29: Irreduciblelrreducible BER for fast flat fading channel, no noise 88 Figure 30: Irreducible BER vs. sampling time offset from T!2 sampling instants for it/4—shift DQPSK with 2—ray frequency selective Rayleigh fading model, with BFT=0.065 90 Figure 31: Irreducible BER for 3 synchronizers in a frequency selective fast fading channel (-10 dB and -3 dB rays), including the BER for T!2 sampling and for optimal sampling xi 92 Figure 32: Irreducible BER for 3 synchronizers in a frequency selective fast fading channel (-10 dB and 0 dB rays), including the BER for T/2 sampling and for optimal sampling 93 Figure 33: Tracking performance of ML block synchronizer for Ic /4—shift DQPSK modulation, without interference, and with frequency selective 94 fading Figure B. 1: Probability density function f(c), of timing jitter, with sampling instants 113 marked XII Acknowledgments I thank my parents Raymond and Beverly for their encouragement and continuous support of all my endeavors, academic or otherwise. I would like to thank Dr. P. T. Mathiopoulos for his suggestion of thesis topic, and for his valuable experience and guidance, without which this thesis could not have been completed. I would also like to thank D. R Bouras for his helpful suggestions, as well as his contribution of much of the simulation code used in this thesis. Finally, I would like to acknowledge the financial assistance provided by the Natural Sciences and Engineering Research Council (NSERC) of Canada, the Advanced Systems Institute (ASI) of British Colum bia, and the University of British Columbia Faculty of Graduate Studies. xlii Chapter 1: introduction Introduction 1 In recent years there has been a dramatic increase in commercial interest toward digital wireless personal telecommunication systems [1]. Interest has been generated by the promise of making communication truly personal, in that users could communicate with anyone, virtually anywhere on the globe. Although complete integrated world coverage is not yet a reality, many systems are currently in use or under development to provide wireless transmission of voice and data for the personal user. Examples of such systems include pagers, cellular and cordless tele phones [2], [3], cellular digital packet data (CDPD) [4], and indoor personal communication sys tems (PCS) [1]. Virtually all these examples are now utilizing digital transmission technology. Digital net works are popular because of the increased capacity over analog systems, and the cheaper, smaller, and more power efficient receivers which may be used [31. However, digital transmission of sig nals adds a number of new complexities to system design. One such issue is that of symbol liming recovery -- synchronizing the phase of the receiver’s symbol-rate clock with the received signal so that recovery of the transmitted symbols may be achieved. Symbol timing recovery has been well studied in the past for the additive white Gaussian noise (AWGN) channel, see for example [71, [8], [9], [10], [Il]. However, for the wireless commu nication system designer, the most serious sources of system degradation come from multipath fading due to scattering of signals on terrain features, and co-channel interference (CCI) due to - - interference from other users in a frequency re-use network. This thesis concerns itself with the effects of CCI and multipath fading channels on symbol timing recovery performance. I Chapter 1. Introduction 1.1 Modulation Schemes Two genera] classes of modulation schemes are frequently used in wireless telecommuni cation environments, namely linear (quadrature) modulation, and continuous phase modulation (CPM). The linear schemes, such as L-ary phase shift keying (L-PSK) and L-ary quadrature amplitude modulation (L-QAM), usually possess a non-constant signal envelope, while CPM is a family of schemes which maintain a constant signal envelope. Both classes are currently in use in wireless telephony, the North American digital cellular standard (IS-54) uses itI4—shft differential quadrature phase shift keying (,t/4—shift DQPSK) as its modulation scheme, while the GSM Euro pean digital cellular system has chosen Gaussian Minimum Shift Keying (GMSK) as its modula tion scheme [5], [6]. This thesis concerns itself with popular variations of linear modulation techniques, which are perhaps the most common for digital transmission of information. Specifi cally considered here are 4-phase shift keying (quadrature-PSK or QPSK and it/4—shift DQPSK), and quadrature amplitude modulation (16—QAM), whose signal constellations are shown in Figure • . . • . . (a) I • . (b) ...• .... .... .••. (c) Figure 1: Signal constellations for modulation schemes under consideration. (a) QPSK, (b) itI4—shift DQPSK, (c) 1 6—QAM These modulation techniques are often used in wireless telecommunication networks in conjunction with a time-division multiple access (TDMA) scheme. TDMA splits a time interval 2 Chapter 1: Introduction (frame) into several time-slots, with each user occupying one or several time-slots in each frame for transmission or reception of signals. An example is the North American digital cellular stan dard (IS-54) TDMA specification [6]. TDMA is superior to frequency division multiple access (FDMA) schemes in that it allows more efficient use of channel bandwidth for intermittent data transfers and allows mobile transmitters to operate in only a fraction of the total frame length. However, FDMA allows simpler implementation since breaking the frame into time-slots calls for more stringent synchronization requirements in the network [13]. Half-rate TDMA frame Slot 1 Slot 2 j Slot 4 Slot 3 Slot 5 Slot 6 Time slot 324 bits in 6.67rns Figure 2: IS-54 TDMA half-rate frame structure (from [6]). 1.2 Wireless Personal Telecommunication Channels The mobile wireless environment introduces new challenges to the reliable transmission of digital information which are not seen in wire-line or optical communications. Chief among the sources of interference are co-channel interference and multipath fading, both of which will exam ined in this thesis. 1.2.1 Co-Channel Interference (CCI) With the increased popularity of digital cellular networks and current research into and development of PCS, there is great economic pressure to increase network caller capacity to allow more users on the limited bandwidth allotted to commercial use [1], [2]. In frequency re-use net- 3 Chapter 1: Introduction works, a hasestation is responsible for servicing all mobile users within its assigned transmission region, or cell. Each hasestation is allocated a sub-set of the entire bandwidth associated with the network. Basestations in neighboring areas are assigned other sub-sets of the network bandwidth. The simplest way to increase capacity is to reuse the frequencies assigned to a particular geograph ical location in another nearby location. Interference due to the common use of a radio channel is known as co-channel interference (CCI), and is a major concern in frequency re-use systems. CCI is becoming a more prominent problem for cellular networks as they increase capacity by subdi viding cells and moving them physically closer together [3], which is necessary for today’s call volumes in urban areas. Network designers must carefully balance the added capacity available through frequency reuse with the increased signal degradation due to CCI. An important measure of the level of CCI is the ratio of carrier power to interference power on a channel, known as the carrier-to-interference ratio (CII ratio), given as [3]: M C/i (L) = j= (EQ. 1.1) 1 where M is the number of transmitters nearby which are using the same frequency as the transmit rh transmitter, and R is the radius of coverage of ter under consideration, D is the distance to the 1 each transmitter, depending upon the radiated power. The exponent y, due to path-loss, is typically equal to 4 [3]. Most wireless networks have specifications as to acceptable levels of CCI, based on a trade-off between the network capacity required and the allowable system degradation. 1.2.2 Multipath Fading Since personal communication devices rarely have a direct line-of-sight path to a basesta tion transmitter, especially in urban areas, signals are scattered by terrain features. If the receiver is 4 Chapter 1: Introduction mobile, this caii cause a serious degradation of system performance, known as multipath fading. Fading is a major concern in the transmission of information over wireless channels [31, [13]. Multipath fading may he modelled as a multiplicative interference [14], [3]: r(r) = f(t)s(t) (Eq. 1.2) where s(t) and r(t) are the transmitted and received signals, andf(t) is the complex multiplicative fading function, which may he modelled as a complex Gaussian process [3]: f(t) = rexp (JO) (Eq. 1.3) where r is a random process with Rayleigh or Ricean distribution and 9 is a random process with uniform distribution over (-ic,t] [13]. Fading may also be viewed as a form of modulation applied to the signal. The phase term results in ‘random frequency modulation’ or ‘random FM’ of the sig nal which causes errors irrespective of the presence of AWGN. Therefore, fading causes a mini mum achievable error rate, or ‘error floor’ on system performance [14]. Rayleigh and Ricean fading can be characterized by the one-sided bandwidth of the fading processf(t), given by [3]: 2Vf BF (Eq.1.4) = where V is the velocity of the receiver [m/s],f is the carrier frequency [Hz], and c is the propaga tion velocity of the electromagnetic signal [mis]. The BFT product, the ratio of the fading band width, BF, to the transmitted symbol rate, l/7 is an important measure of the amount of fading present, indicating whether it is ‘slow’ or ‘fast’ fading. The boundary between the two classifica tions is a loose one, but a rule of thumb states that slow fading results from BFT<O.OO1 [13]. 5 Chapter 1: introduction Ricean fading has a line-of-sight component in addition to a reflected faded component. It is also characterized by the power ratio K, between the direct line-of-sight signal and the reflected signal component. Multipath fading may also spread the received signal over time, as well as frequency, since scattered signals will arrive at the receiver with different time delays due to the varying lengths of propagation paths. This leads to a channel impulse response which spreads the received power over a finite time interval. An illustration of a typical time-delay profile which might be measured in an urban cellular channel is shown in Figure 3, which illustrates the spreading of power due to different signal paths (see [161 for actual test data). Such a channel characteristic will vary with time if the receiver or scatterers are mobile. Figure 3: A typical channel power delay spread profile for an urban environment Multipath fading can he characterized by the average time-delay spread, td, which is the average time delay of the received power. For large values of ‘td/T (e.g., > 0.1), the fading is con sidered frequency selective [13]. It earns its name from the fact that for large tdT, different fre 6 Chapter 1: Introduction quencies within the signal bandwidth suffer different fading effects. At any instant deep amplitude fades may occur at specific frequencies only, instead of over the entire signalling bandwidth as with frequency non-selective, or flat fading [3]. Both frequency selective and non-selective fading may be encountered by a mobile wire less transceiver. Because of this, both Ricean and Rayleigh land-mobile fast fading, including both frequency selective and non-selective situations will be considered in this thesis. 1.3 Symbol Timing Recovery Techniques There are a number of synchronization problems in digital communications, including car rier, frame, and symbol timing synchronization. The latter, also known as bit or symbol timing recovery (STR), is the problem of synchronizing a receiver clock’s rate and phase with the received baseband data symbol sequence. Correct receiver synchronization is necessary for proper recovery of the received data. Errors in symbol synchronization can affect most aspects of system performance, including equalization and echo cancellation [18], [19], as well as bit error rate (BER) performance [201. Some telecommunication systems transmit clock information on a separate channel or by inserting a pilot-tone at the clock frequency [211, similar to inserting a pilot tone at the carrier fre quency for carrier recovery and tracking [13]. These methods are inefficient, the former due to the added bandwidth required to transmit a second signal, and the latter due to the increased power required for the pilot-tone. In most cases symbol timing must be recovered from the received sig nal itself through a process of estimation. 7 Chapter 1: Introduction 1.3.1 Measures of Symbol Timing Recovery Performance Different symbol synchronization schemes may be compared based on a number of metdes, including steady-state symbol timing jitter, acquisition time, and cycle slipping rate [7]. Acquisition time is the amount of time required from the moment symbol timing recovery on a sig nal with unknown symbol clock phase is begun, until the clock phase is synchronized to the received signal. Timing recovery schemes can be evaluated by the average acquisition time, in symbols, which are required to recover the symbol clock phase [71. Cycle slipping is a reference to a non-linear effect observed in many recovery techniques, where the recovered clock effectively slips’ a symbol period, so that one or several clock periods are not registered by the recovery scheme, [34), [35], [361. This is especially relevant in systems which employ a phase-lock loop (PLL) as a component of the recovery technique [9]. Symbol timing jitter is a measure of the steady-state clock phase error associated with a particular recovery scheme, after acquisition has been achieved. Timing jitter is usually measured as the root-mean-square (RMS) of the clock phase error, often normalized by the symbol rate [10]. This thesis concentrates on steady-state error, or symbol timing jitter since this is the most popular measure of performance for comparing symbol timing recovery techniques. 1.3.2 Symbol Timing Estimation Techniques Traditional symbol timing recovery techniques involve extracting a periodic timing com ponent from the received signal, which a tracking loop such as a PLL uses to estimate the correct symbol clock phase [111. These techniques can be implemented by either analog or digital means (see for example [101, [24]). However, with the increased computational power available from Very Large Scale thtegration (VLSI) digital receiver architectures, there has been development of new synchronizers which process blocks of received samples simultaneously [25], [26]. BLock 8 Chapter 1: Introduction synchronizers, as they are known, store a block of input samples and process them together to extract a timing estimate for the entire block. Both digital tracking loops as well as block synchro nizers generally involve multiple samples per symbol, although either can be implemented in a form using as little as one sample/symbol in high Baud-rate applications [27], [28], [29] Symbol synchronizers have been based on heuristic approaches [29], [30], such as the early-late gate synchronizer [13], as well as on estimation principles such as maximum likelihood (ML) estimation, and minimum mean square error (MMSE) criteria [22], [23]. This thesis deals exclusively with methods based on ML principles as their performance is generally superior to other methods [22]. In particular, two tracking loops based on ML principles are examined -- a data aided (DA) technique which assumes knowledge of the received data sequence to aid in esti mation, and a non-data aided (NDA) technique which does not require knowledge of the received data sequence [10], [11]. A third method, a block synchronization scheme based on ML principles will also be examined. 1.3.3 Timing Recovery in Wireless Communication Channels Although the three synchronizers to be examined have been proposed and analyzed for the AWGN channel [101, [11], [22], [23], the performance of symbol synchronization schemes in mobile wireless channel conditions has had little attention in published literature. With regards to CCI, we are aware of only one publication which deals with a simulation study of the effect of CCI channels on symbol timing recovery of a QPSK signal [31]. This study provides only a few results for specific simulation cases, and does not provide general conclusions as how to minimize the effects of CCI. Several authors have examined the effect of fading channels on synchronization. A ML9 Chapter 1: introduction based synchronizer for a general fading dispersive channel has been proposed [32], [33]. However, it relies upon knowledge of channel characteristics and requires a computationally intensive search-algorithm. Furthermore, its performance is evaluated with no prediction as to actual improvements in BER or symbol timing jitter performance. Another technique has also been developed for ML block synchronization and demodulation of a TDMA data frame involving car rier phase, symbol timing, and carrier frequency offset estimation [25], [261, and tested in a fre quency selective fading environment. The algorithm was implemented in hardware, and is a promising candidate because of the simplifications in implementation used to reduce computa tional complexity. This technique is generalized to the block synchronizer examined in this thesis, in order to allow for theoretical analysis. In [611, a study is made of the ML NDA synchronizer in frequency-selective fading for binary-PSK modulation. The paper found that the steady-state symbol timing jitter of an infinitely fast (ideal) ML NDA tracking loop has no benefit over practical synchronizer’s performance. However, it does not provide symbol timing jitter expressions which may be useful for system design, and more importantly, the analysis is only valid for the case that the delay spread is small compared to the symbol period. 1.4 Thesis Research Objectives Noting the background provided, this thesis explores the effects of CCI and multipath fad ing on the performance of three popular symbol timing recovery schemes -- two tracking loops, and one block synchronizer, all based upon maximum likelihood estimation principles. The track ing loops (ML NDA and ML DA) are based upon recovering a sinusoidal timing wave through a phase-lock loop structures, while the ML block synchronizer is based on a direct evaluation of the 10 Chapter 1: Introduction ML log-likelihood function for symbol timing recovery. Genera] analysis is supported by com puter simulation studies based on conditions encountered in digital wireless personal telecommu nication systems. The thesis has two main objectives, which are: 1) To study the effect of CCI on the tracking error (symbol timing jitter) of the three syn chronizers. This will include a theoretical derivation of symbol timing jitter perfor mance of the three synchronizer schemes in CCI, as well as computer simulations to confirm the analysis and provide further insight. For both theoretical and computer simulated results, the performance of three popular modulation schemes (QPSK, t/4— shift DQPSK, and 1 6—QAM) will be considered and compared. 2) To examine the operation of the ML NDA and ML DA tracking loops in a multipath fading environment, including both frequency non-selective and frequency selective fading, and with both Ricean and Rayleigh fading. The performance evaluation results for the fading channel will be obtained by means of computer simulation and will involve the it/4—shift DQPSK modulation scheme. 1.5 Organization of Thesis The thesis consists of six chapters, including this introduction (Chapter 1), and two appen dices. The chapters are organized as follows: Chapter 2 introduces the concept of symbol timing recovery, providing a background for the analysis and simulations which follow. Section 2.2 introduces the concept of symbol timing recovery, and introduces root mean-square timing jitter as a measure of performance. Section 2.3 11 Chapter 1: Introduction explains maximum likelihood (ML) estimation for symbol timing recovery, and introduces the three synchronizers to he examined in the thesis. Section 2.4 provides background on methods of deriving expressions of RMS symbol timing jitter for each of the synchronizers. These methods will be used in Chapter 3 to analyze the three synchronizers in a combined AWGN and CCI envi ronment. Finally, Section 2.5 provides a summary of the chapter. Chapter 3 presents the analytical results obtained for symbol timing recovery performance in CCI for the QPSK, t/4—shift DQPSK, and 16—QAM modulation schemes. Section 3.1 is an introduction to the subject of symbol timing recovery in CCI channels. It is followed, in Section 3.2, by a description of the system model, including the CCI model, used in the analysis of the three synchronization schemes. Section 3.3 to Section 3.5 present the analytical results of the effect of CCI on the ML NDA, ML DA, and ML block synchronizers. Section 3.6 provides a sum mary of the chapter’s results. Chapter 4 is a presentation of a series of computer simulations performed to validate the analytical results obtained in Chapter 3. After the introduction of Section 4.1, Section 4.2 is a description of the computer simulation used to obtain the results, which are presented for the ML NDA, ML DA, and ML block synchronizer structures in Section 4.3 to Section 4.5. Section 4.6 provides a summary of the chapter. Chapter 5 is an examination of the effects of multipath fading on symbol timing recovery for the t/4—shift DQPSK modulation scheme by means of computer simulation. Section 5.1 gives an introduction to the topic, while Section 5.2 presents the models used to generate both frequency nonselective and selective fading in the computer simulations. The simulation results and discus sion then follow in Section 5.3. Finally, Section 5.4 gives a summary of the chapter’s results. 12 Chapter 1: Introduction The conclusions of the thesis, and some suggestions for future research are given in Chap ter 6. Appendix A gives the detailed derivation of the equation for symbol timing jitter of the ML NDA technique in AWGN and CCI channels. Appendix B provides a detailed analysis of the error involved in measuring the symbol timing jitter in the simulations performed. 13 Chapter 2: Symbol Synchronization Principles 2 Symbol Synchronization Principles 2.1 Introduction The symbol timing recovery process has been well studied in the past for the AWGN envi ronment (see for example [7]-[ll]). Although many heuristic methods for symbol synchronization have been proposed, it has long been recognized that timing recovery is essentially an estimation problem of the time difference between the transmitted and received digital signal [10], [13]. This chapter presents the basic principles and background of the symbol timing recovery problem. Since this thesis concerns itself with the symbol timing jitter performance of three maximum like Ithood synchronizers, methods of analysis for each technique are introduced here, and used in later chapters. Section 2.2 presents the basic principles of symbol timing recovery. The concept of a cyclostationary process is introduced to explain the underlying periodicity which enables the esti mation of symbol timing. The behaviour of symbol timing jitter is also discussed, including its effect on the BER performance of a receiver. Section 2.3 explains how maximum likelihood esti mation can be brought to bear on the problem of symbol timing recovery. The three symbol syn chronizers to be examined in later chapters are introduced: the ML NDA synchronizer, the ML DA synchronizer, and the ML block synchronizer. All three are explained in terms of the maximum likelihood concept. Section 2.4 provides the method of analysis for each technique which will be used in Chapter 3 to determine symbol timing jitter performance in combined CCI and AWGN channels. Finally, Section 2.5 provides a summary of this chapter. 14 Chapter 2: Symbol Synchronization Principles 2.2 The Symbol Timing Recovery Process 2.2.1 Cyclostationary Processes in Timing Recovery Symbol timing recovery is possible because digital signalling introduces an underlying periodicity to the transmitted signal. Digitally modulated signals have a non-stationary component whose mean and autocorrelation functions are periodic in time with the symbol period T Such a process is known as a wide-sense cyclosratianary (CS) process [38]. For example. a pulse-amplitude modulated (PAM) signal waveform may be expressed as: s(t) = (EQ.2.1) ag(t—kT) k where g(t) is an arbitrary pulse shape, and ak is the information symbol transmitted at t=kT, from the set of {ak} independent and stationary symbols. This can be shown to be a wide-sense CS pro cess, since the mean and autocorrelation of the signal can be written as: E[s(t)] =E[aJg(t—kT) =E[s(t+T)] k E[s(t)s(u)J (Eq. 2.2) =E[s(t+T)s(u+T)] = km where Ef.) indicates the expectation over the argument. This extends to the case of the quadrature modulation schemes under consideration here (L-ary PSK and L-ary QAM), as well as CPM sig nalling such as GMSK [39], [40]. Many commonly used PAM signalling schemes use zero-mean data (i.e. E[akJ=O) for power efficiency, since there is no resultant DC component to the signal. Most symbol synchroniz ers require a signal with non-zero mean to recovery timing and therefore use some form of nonlin ear processing to remove the modulation of the signal and generate a cyclostationary signal with non-zero mean. After this operation. the signal can be written as: 15 Chapter 2: Symbol Synchronization Principles s’(t) g’(t—kT) = (Eq.2.3) A: where g’ (t) is the pulse-shape after processing. For many choices of non-linearity, the resultant signal now has a non-zero periodic mean as well as autocorrelation function, and can be used to recover symbol timing. This operation can he thought of as removal of the modulating signal, or modulation removal, and is a basic concept in many symbol synchmnizers [11]. 2.2.2 Symbol Timing Jitter in Symbol Synchronization The steady-state tracking performance of a symbol synchronizer is generally measured by rootmean square (RMS) timing jitter normalized by the symbol period: f /E[c21 T=4E4 T 2 r (Eq.2.4) 2 [41]. where ‘r is the receiver clock timing error, a stationary random variable with variance a For most synchronizers in an AWGN channel the timing vaiiance can be expressed by two statistically independent components [221: = a a + 2 (Eq.2.5) . and the data-, or pattern-dependent jitter, d 2 the noise-dependent jitter, a, 2 which is also known as self-noise [421. The noise-dependent jitter is due to AWGN, and in well-designed systems is the main contribution to synchronization errors at low signal to noise ratios (SNR). The pattern-depen dent jitter term is present in the absence of noise, and is caused by the intersymbol interference (ISI) of pulse overlap at the non-ideal sampling instants [411. Pattern-dependent jitter is the chief limit to timing jitter performance at high SNR, and may be viewed as causing a jitter ‘floor’ minimum level of timing jitter which can be obtained despite the absence of noise. 16 -- a Chapter 2: Symbol Synchronization Principles 2.2.3 Effects of Symbol Timing Jitter on Receiver BER Performance Symbol timing estimation is an important requirement of the detection process. Consid ered in this thesis is the case of a digital modulation scheme which employs Nyquist raised-cosine pulse-shaping to eliminate ISI at the ideal sampling instant [13]. Errors in symbol timing estima tion degrade system BER performance because of sampling at a reduced eye opening. The specific effect of timing jitter on the BER performance of a system depends upon the modulation scheme used. For example. the errors introduced by symbol timing jitter in coherently demodulated binary PSK signalling is shown in Table 1. assuming no clock frequency or carrier phase estimation error. As can he seen, an offset of 9% of a symbol period can have an effect on BER perfonuance, which is increasingly severe for high SNR. In fact, an RMS jitter of 15% of a symbol period brings about an error floor at a BER of about i0 [101. Table 1: Effect of symbol synchronization error on BER performance compared to SNR for ideal timing, for coherently demodulated BPSK (from (10]). RMS timing jitter (a/T) SNR loss at BER = iO SNR loss at BER = 1O 0.09 1dB 5dB 0.12 4dB 16dB 0.15 N/A N/A N/A indicates that an error floor of approximately i0 is present for this amount of timing jitter. For applications such as data transmission which require low BER performance, RMS timing jitter must be well below the O.09T level. Low BER requirements may necessitate a syn chronization scheme which guarantees less than O.OIT jitter [101. For applications under consider ation here, such as cellular telephony and PCN, higher BER levels may be acceptable and an RMS jitter of O.09T may be a measure of acceptable synchronization performance. 17 Chapter 2: Symbol Synchronization Principles 2.3 Maximum Likelihood Estimation Maximum likelihood estimation of symbol timing is based upon expressing the likelihood of the timing offset being a particular value, t = ‘c, based upon observation of the received signal. The likelihood function is maximized to locate the ML value of the symbol timing offset. In [11] the natural log of the likelihood function, or log-likelihood function for timing recovery is found to he: A(t) (Eq.2.6) fx(t,t)s(t)dt = 0 T where s(t) is the transmitted signal as in Eq. 2.1, arid x(t,t) is the received signal, dependent upon the timing offset t, as well as any noise added in the channel. The log-likelihood function has an observation period of T . An approximation is made by assuming the observation period is infinite, 0 and that only K previous symbol periods are relevant during the current symbol period in s(t). The ML log-likelihood function for estimation of correct timing can then be simplified to [11]: (Eq. 2.7) A = where Ck k=O is in general a complex data symbol at the kth symbol interval, and: q() = f s(r)hR(t—kT—)dt (Eq.2.8) where hR(t) is a receive filter matched to the transmitted pulse-shape, h’t), and qk(t) is simply the output of the receiver’s matched filter, sampled at value of t = kT + t. The function is maximized by the which is optimal for sampling. Eq. 2.7 is used in the next three sections to illustrate how the three synchronizers under consideration, the ML NDA, ML DA, and ML block synchronizer, are based upon the principles of ML estimation. 18 Chapter 2: Symbol Synchronization Principles 2.3.1 ML Non-Data Aided Estimation The ML function, A (‘c), requires knowledge of the symbol sequence, Ck, transmitted. In [11], the likelihood function is averaged over the probability density function of the data symbols, ck } to rid the equation of its dependence on the symbol sequence. Assuming the symbols are binary with ck E {±l} ,or Gaussian random variables, the result is similar [11]: A(t) ocln([cosh(q(t))]) =q(tI ck binary k k A (t) ° q(t) ck Gaussian. (Eq.2.9) For the common NDA implementation the output of a matched filter, q(t,t) is fed to a square-law device, and the integration over K symbol intervals is realized by a narrow bandwidth filter or PLL [431, as shown in Figure 4. The prefilter. often a handpass filter (BPF) centred atf=I/ 2T, is used in order to minimize pattern-dependent timing jitter at high SNR [37], [12]. The BPF, K(f), extracts the periodic component of the resultant waveform, of frequencyf=I/T Zero-cross ings of the timing wave, z(t), are used to locate the correct sampling instants. K(f) is often imple mented as a PLL to provide a more reliable frequency-selective filter with an ability to compensate for small clock-frequency offsets at the receiver [34]. [37]. I Channel z(t) x(t) BPF (@110 Figure 4: ML non-data aided symbol timing tracking loop [31]. Notice in Figure 4 that the in-phase (I) and quadrature 19 (Q) inputs are processed separately, Chapter 2: Symbol Synchronization Principles since squaring the complex received signal in a balanced modulation scheme results in a subtrac tion of the two independent timing waves, canceLing the output [11]. However, each of the I and Q signals can be viewed as separate binary PAM signals which yield periodic timing signals of equal phase. and may be added together to pmvide a timing estimate for the received waveform [311. 2.3.2 ML Data Aided Estimation The ML data-aided scheme uses a decision device to approximate the transmitted symbol sequence. The derivative, denoted by ‘S’, of the simplified log-likelihood function in Eq. 2.7 is: K A(t) ckk(t). = (Eq. 2.10) k=O The log-likelihood function is maximized when Eq. 2.10 is zero. The ML DA implemen tation in Figure 5 is a realization of this method. It can be viewed as a gradient method, where the derivative, or gradient of the ML log-likelihood function is used to achieve tracking. At the nomi nal interval T specified by the timing wave, z(t), a sample is taken of both the signal and its deriva tive. A decision device decides on the symbol transmitted, which is multiplied by the sampled derivative of the signal. The result is fed through a loop filter to a number controlled counter (NCC), the digital equivalent of a voltage-controlled oscillator (VCO), which generates z(t). Since the feedback loop is similar to a PLL, this synchronizer will be subject to acquisition time consid erations, as well as cycle slipping phenomena. Notice, as with the NDA case, the I and processed separately to avoid cancellation of the resultant timing wave. 20 Q inputs are Chapter 2: Symbol Synchronization Principles x(t) Figure 5: Data-aided symbol timing tracking loop. (DD) is decision device, (SPC) is parallel-to-serial converter for output data sequence, (NCC) is number controlled counter [31]. 2.3.3 ML Block Estimation The ML block symbol synchronizer differs from the previous two methods since it oper ates on a block of samples at one time to derive timing estimates for the entire stored waveform. The block synchronizer under consideration here simply divides the symbol period into a finite number (N) of equal intervals and evaluates the ML function of Eq. 2.7 over K symbols for each discrete time interval, choosing the instant which maximizes the expression. This suggests a search algorithm, shown in Figure 6, as follows: 1) Sample the received signal at a rate NIT. 2) Store samples over a duration of K symbol periods, or KN samples. 3) Calculate the N metrics given by: 1 A = i 21 = { 1, ...,N} q.2.11) Chapter 2: Symbol Synchronization Principles 4) Choose the sampling instant t=(k÷iIN)T, where i is chosen to maximize A . 1 NIT input samples A t Figure 6: Block diagram of ML block synchronization scheme. This synchronizer has a great deal of added complexity, but allows synchronization with out any required acquisition time. As well, since it does not contain a non-linear tracking ioop, it will not suffer from cycle slipping phenomena seen in synchronizers employing tracking loops. An alternate synchronizer structure has been proposed [251, [261, which uses differential decoding prior to symbol synchronization. This may be performed by multiplying each sample by the complex-conjugate of the sample occurring N samples previously (one symbol period). Thus, the synchronizer metrics are given by: K = where ‘—‘ N 2 k= I N = {1 N) (Eq. 2.12) indicates complex conjugation, and l is now an estimate of the differential symbol received. Using differential symbols for synchronization can help overcome carrier-phase offsets at the receiver. This is especially appropriate for use with the jr/4—shift DQPSK modulation scheme, since for the DA ML synchronizer, the decision device must be able to distinguish between an 8—symbol constellation, as shown in Figure 7. Using the differential symbols, only a 4—symbol constellation must be distinguished. As well, the term (iT/N) is 1 q(iT/N)_ observed to be the differential decoding operation used in a symbol-by-symbol differential 22 Chapter 2: Symbol Synchronization Principles receiver, therefore the transmitted data can he recovered in the same operation. Since differential detection can be used, this completely eliminates the need for carrier phase recovery at the receiver. Of course the disadvantage of this scheme is the amplification of noise in the received signal. However, it has been shown that implementation of this technique in an AWGN can still produce accurate timing estimates [261. . . . . (b) (a) Figure 7: Comparison of signal constellation for ML block synchronization using (a) symbol constellation, and (b) differential symbol constellation, for it /4—shift DQPSK signalling. 2.4 Analysis of Symbol Synchronization Techniques Having introduced the three synchronization schemes, it will prove useful in this section to examine methods of analyzing the symbol timing jitter of each technique. In the three methods presented, analysis is simplified by assuming that perfect carrier recovery is achieved, and signals are demodulated to hasehand. In Chapter 3, these methods will be used to analyze the effect of CCI on synchronizer performance. 2.4.1 Phase-Lock Loop Theory for the NDA Implementation The tracking symbol synchronizers under consideration may he viewed as PLL’s with nonlinear phase detectors, as illustrated in Figure 8. This allows the use of linearized PLL theory to 23 Chapter 2: Symbol Synchronization Principles determine expressions for symbol timing jitter. However, most PLL analysis assumes stationary input disturbances [71, [34], whereas here the input to the synchronizer is a cyclostationary signal [12], [44]. It has been shown that use of the general equations derived for a stationary input distur bance can greatly overestimate the amount of timing jitter at the PLL output [42], [44j, [45], since it ignores the CS process, in effect averaging out its periodicity. u(t) Figure 8: A general symbol synchronizer as a PLL. F(f) is a loop filter, and VCC is a Voltage Controlled Clock. The output of the nonlinear phase detector block can be written as the sum of a sinusoidal component to be tracked and a zero mean noise disturbance, M(t) [12]: v (t) 2it 1 —cos (—t + e) + M (1) (Eq. 2.13) where P is the power of the sinusoidal component. The phase offset 0, of the sinusoid represents a possible offset of the PLL nonlinear phase detector stable point from the ideal sampling instant due to a bias in estimation [46]. The above equation is a well-known PLL expression, with the param eters related by [12]: .Jexp (jo) where <.> = (E [v (t) I exp (—2jict/T)) (Eq. 2.14) indicates a time-average over T For wide-sense stationary noise input, the output jitter variance of the PLL, can be expressed as [9]: 24 Chapter 2: Symbol Synchronization Principles = (f— )]df 0 .1 IHL(f)I2[So(f÷ ) +S (Eq. 2.15) (f) is the power 0 where L(f) is the equivalent linearized phase transfer function of the PLL, and S spectral density (PSD) of M(t). It has been shown for wide-sense CS M(t) that timing jitter variance can be written as [121: = I V’i.. (f) 25 (Eq. 2.16) (I) df where S (f) = ! [s (f+!) + 5 (f_!) (Eq. 2.17) (f+ ) exp (—2j0) ) exp (2j0)] and Sk(f) = k FT{y(x)} = {O,±1,±2} (Eq.2.18) where FT{ } represents the Fourier transform of the argument with respect to the time-variable x. . yk(x) is the kth Fourier series coefficient of the autocorrelation of a CS M(:) expressed as a Fourier series: RM(u,u+x) = y(x)exp(ku). (Eq. 2.19) If the input is stationary, the autocorrelation function becomes simply RM(v), and Sk(J) k = 0 for 0. It can be seen that Eq. 2.15. for stationary M(t), is simply a special case of Eq. 2.16 for CS M(r). To see more clearly the difference between the two equations, it is useful to examine the timing wave, z(t), which is the output of the ML NDA synchronizer, as seen in Figure 4. Its vari ance can be written as [101: 25 Chapter 2: Symbol Synchronization Principles E [z 2 (t)] = 1 C + (Eq. 2.20) C,cos (t) which consists of C , a constant term, made up of (signal x signal), (signal x noise), and (noise x 1 noise) terms at the output of the square-law device, and a periodic C 2 cos(4itIT) component due to the CS nature of the (signal x signal) term [37]. The two terms are statistically independent [12], and when added together the ideal sampling instant occurs at the location of minimum jitter, which is smaller than in the stationary case. This is illustrated in Figure 9, where the importance of using Eq. 2.16 is evident. (t)] 2 E[z (t)] 2 E[z time process (a) (b) Figure 9: Illustration of timing wave variance for (a) wide-sense stationary and (b) wide-sense CS inputs to the filter-square-filter ML NDA synchronizer. 0 represents a possible bias in the estimation process. If it is assumed that the PSD of the disturbance is relatively constant over the frequency range for which IHL (J) 0, and furthermore that = BL is defined as the IIHL (t) I f where 2 2 equivalent double-sided noise bandwidth of the PLL equivalent phase transfer function, then for wide-sense CS input noise: = (2B) S (0). 26 (Eq. 2.21) Chapter 2: Symbol Synchronization Principles Thus, the jitter can be specified by determining the PSD of the input noise term, and the equivalent noise loop bandwidth of the PLL used for recovery. It is important to note, however, that linearized PLL theory is based upon the linearization of a nonlinear PLL transfer function. This is strictly valid only for a small disturbance term, M(t), so actual and predicted performance will diverge for large M(t). Since small sampling time errors in multi-level modulation schemes may cause unaccept able bit error rate performance [10], pattern dependent jitter is a concern for system designers. A number of schemes have been put forward to minimize or eliminate the pattern-dependent jitter component. In [37] it was found that the pattern dependent jitter term is eliminated by a pulse shape, G(f) 1 at the input to the squarer, which has even symmetry aboutf=l/(2T) and is bandlim ited to 11(47) < f I <z 3/(47). Using a bandpass prefilter as in Figure 4 is meant to shape G(J) to these parameters. However, timing jitter can never be eliminated practically in this configuration, since the symmetry conditions must be exact. For example, in [37] it was found that a ML NDA scheme with bandpass prefilter bandwidth 0.4/T and PLL normalized equivalent noise bandwidth of 2 BL= 1/20, has an RMS pattern dependent jitter value of 0.O1T for a filter frequency mistuning of only 0.0025T. 2.4.2 Phase-Lock Loop Theory for the DA Implementation The DA scheme, which samples at a nominal rate of lIT, is best analyzed through digital PLL theory [7], [34]. If the nonlinear processing involves a sampler at the clock rate, v(t), u(t), and F(f) in Figure 8 can be replaced by vk(t)=v(kT-i-t), uk(t)=u(kT+t), and F(z), respectively. 1. G(i is the pulse shape at the output of the prefilter so 0(f) = H(f)P(f), where P(19 is the Fourier transform of the prefilter, and H( is the Fourier transform of the input signal pulse-shape. See Figure 4. 27 Chapter 2: Symbol Synchronization Principles The output of the nonlinear processing section, vk, can be written as the summation of the average output. as well as a disturbance term [12], dk (k) such that vk () = E [vk (k) 1 + dk ()• The mean value is the output of an equivalent phase detector, denoted spD(t)=E[vk(t)1, which is simply the output of the PLL nonlinear phase detector in the absence of a disturbance term. By lin earizing the phase-detector characteristic around t=O, and replacing the PLL with its equivalent close-loop phase transfer function, whose impulse response is hjjz), the tracking error, e, can be expressed as [22]: ek = (Eq.2.22) —hL(k—n)dfl(t)/4D(O) where the transfer function of the PLL is given by [221: KNCCF(z) rPD (O) z— 1 +KNCCF(z)spD(O) HL (z) (Eq. 2.23) with KNCC indicating the sensitivity, or ‘gain’ of the NCC in the feedback path. Unlike the ML NDA case, where the phase detector characteristic may not pass through the origin and therefore have a phase offset term (see Eq. 2.13), the phase detector characteristic for the DA ML scheme results in an unbiased timing estimate [46], since it does pass through the origin. As with the ML NDA case (see Section 2.3.1), linearizing the PLL transfer function is strictly valid only for small dk(tk), which remains in the linear region of the phase detector, or equivalently, small timing jitter. If the double sided loop bandwidth is given by 2BLT = I [exp U2I) I I df, the timing 2 jitter can be found as the variance of the error term [22]: = E [e1 = S [exp (j2icf)] df/4D (0) 2 IIHL [exp (j2itf) I 1 = (Eq. 2.24) LT) S (0) ‘D (0) ( B 2 where S(O) is the PSD of the disturbance term, {dk(t)), evaluated atf=O, provided that the PSD is 28 Chapter 2. Symbol Synchronization Principles approximately constant nearf=O. Although the simplification in Eq. 2.24 holds for a PLL with stationary input, a cyclosta tionary input will include a disturbance term whose PSD is zero at preciselyf=O and therefore is not constant over the range of frequencies where L 11 [exp (j21rJ) 2 j 0 [48]. This term gives rise to pattern-dependent jitter. It has been shown in [42] that this disturbance term is proportional to a higher power of ( 2 for a first-order PLL, BL7). The resultant jitter term is proportional to (2BLT) 2 and (2BLT) 3 for second-order PLL [48]. An approximation to this term is given in [22] for the DA ML synchronizer with second-order PLL transfer function as: 2 S(O) = (2BT) m [-Rd (m)] 2 + 3 (2BLT) , .2 SpD(O) rn—I SPD(O) (Eq. 2.25) where: • S,(f) is the PSD of the disturbance terms for which S(J) is approximately constant around f:=O, and has autocorrelation sequence, R(m). Rd(m) is the autocorrelation sequence of the disturbance term for which the PSD term Sd(O)=O, • is the damping ratio of the synchronizer’s close-loop equivalent continuous-time transfer function [34]. As with the ML NDA case, a number of techniques have been put forth to eliminate pat tern dependent jitter, such as the modified ML (MML) scheme (see Section 3.4.2) which includes a prefilter, as well as a minimum mean square error (MMSE) based technique [23]. Both of these, however, sacrifice performance at low SNR to improve performance at high SNR. 2.4.3 Symbol Block Synchronizers The simplified ML log-likelihood function of Eq. 2.7 can be expressed as a three term 29 Chapter 2: Symbol Synchronization Principles Taylor series expansion around the ideal sampling instant. By approximating A (t) with its mean, noise-free equivalent, the symbol timing jitter can be written as [101: r.2 ELA (0) = E[A(0)j 2 (Eq.2.26) which holds for small values of timing jitter. This technique yields a lower bound on performance of a general ML symbol timing recovery technique. Since the ML block synchronizer evaluates the ML log-likelihood function discretely, the equation will provide a lower bound on perfor mance, limited by sample time resolution, as well as the number of symbols processed in a block. For Nyquist raised-cosine pulse-shaping h(t), and AWGN with double-sided PSD of NJ2 this provides a lower bound of [10]: >! (SNR) 1 K where SNR = h(O) (Eq. 2.27) —h(0)} /2). It is interesting to note that performance is identical to 0 (a + a) h (0) / (N the a ML DA implementation, ignoring the pattern-dependent jitter term, with 2BLT= 1/K (see Eq. 3.18). It should be kept in mind that this derivation does not account for the sampling rate of the algorithm. Rather, it is a more general expression for a ML synchronizer which evaluates the ML log-likelihood function. Since this is an expression for a generic ML symbol synchronizer, it can be seen that the ML DA technique reaches the lower bound on performance unless pattern depen dent jitter is the dominant contributor to timing jitter. Tracking performance of the ML DA track ing loop can be viewed as that of a block synchronizer with ‘memory’ of 1/(2BLT) symbols [10]. The traile-off for ML block synchronizers is between time tsolution and the expense in time and hardware of metric calculations. The number of samples/symbol, N, determines the num . In the absence of noise 2 ber of metrics to be calculated, and the minimum timing-jitter attainable 3 is T/ (NJi). The worst case sampling jitter, the average RMS jitter due to time quantization 30 Chapter 2: Symbol Synchronization Principles where the ideal sampling instant lies exactly between samples is T/ (2N). A sampling rate of 16/T allows a minimum normalized RMS timing jitter of 1.8% of T, while the worst-case minimum block RMS timing jitter would he 3.125% ofT 2.5 Summary This chapter outlined the theory of symbol timing recovery, as it applies to three synchro nizers under consideration, the ML NDA and ML DA tracking loops, as well as the ML block syn chronizer. The concept of the CS process was introduced to explain the periodic nature of digital signalling which enables symbol synchronization at the receiver. Symbol timing recovery is an estimation problem, and maximum likelihood estimation was discussed. It was shown that all three synchronizers are based upon a simplification of the ML function for symbol timing estimation. Popular methods of finding the steady-state symbol timing jitter performance of the track ing loop synchronizers were presented, which recognize them as forms of a PLL with CS inputs. The methods presented are general and cover both stationary and CS input disturbances. A method of detennining the lower bound on timing jitter performance is presented for the block synchro nizer, which exhibits jitter performance similar to the ML DA scheme. It was pointed out that all methods presented involve linearizing a non-linear process, and assume that levels of noise and interference in the synchronizer are low enough to maintain operation in a linear region. The tools presented in this chapter will be used in to analyze the effects of a combined AWGN and CCI channel on jitter performance of each synchronizer in Chapter 3 and Chapter 4, as well as in fading channels in Chapter 5. 2. Since the error in sampling time will be constant over an entire block, timing jitter in this case refers to the aver age sampling time error over multiple blocks. 3. This is the well-known result for quantization noise in digital sampling [49J. 31 Chapter 3: Symbol Synchronization Analysis in CCI Channels 3 Symbol Synchronization Analysis in CCI Channels 3.1 Introduction Although symbol timing recovery jitter performance has been well studied for the AWGN channel with a variety of signalling formats, little has been published on the effects of CCI on symbol timing recovery. As previously mentioned, we are aware of only one conference paper published on this topic. More specifically, in [31] simulations are used to predict the level of CCI which yields a BER of iO for QPSK signalling with both ML NDA and ML DA synchronizers. The paper concludes that a BER of iO is achievable in the presence of a single interferer at C/I levels up to 3.5 dB. However, the simulations are performed for only a few cases of 1 or 2 interfer ers with particular timing offsets, and can not he used to predict performance for other modulation schemes. Furthermore, the results reported in [311 do not provide an exact explanation of how the synchronization schemes are affected by CCI. In this chapter. the effect of a combined AWGN and CCI environment is considered. Anal ysis of the three synchronization schemes discussed in Chapter 2, the ML NDA, ML DA, and ML block synchronizers, provide expressions for the timing jitter performance of each for a general linear quadrature modulation scheme. Section 3.2 introduces the baseband system models for the transmitter, channel, and receiver, including the model of CCI, to be used in the analysis. Then, Section 3.3 to Section 3.5 outline the analysis of the ML NDA, ML DA, and block synchronizers, in CCI and AWGN for the general case of linear quadrature modulation, including QPSK, 7t/4— shift DQPSK, and 16—QAM. The chapter ends with Section 3.6, which provides a summary of the 32 Chapter 3: Symbol Synchronization Analysis in CCI Channels results obtained. 3.2 System Model The block diagram of the system model is shown in Figure 10. A baseband model is used for mathematical convenience. 3.2.1 Transmitter Model The block diagram of a typical transmitter is shown in Figure 10(a).. _4>[j> optional (a) n(t) 1(t) r(t) (b) real I-channel (C) zzzz> complex Q.channe. Figure 10: Block diagram of the baseband system model. (a) Transmitter, (b) Channel, (c) Receiver. The signal mapper maps the input binary data stream, {dk) into the symbols k=7k 33 Chapter 3: Symbol Synchronization Analysis in CCI Channels exp(ji2k), where ‘Ik and k are the amplitude and phase of k’ respectively. For the case of L-PSK signals, the amplitude, ‘Yk is constant, and the phase, k 12 takes a value from a discrete set of L equally distributed phases, depending upon the data stream {dk). A differential encoder may be utilized to code a new sequence, = = where exp {Ck), where: (EQ. 3.1) k— I indicates modulo 2ic addition, and ‘ k is the phase of ck. 1 -j’t) to shape the 7 The signal is then passed through a transmit filter with impulse response h signal pulses, yielding the equivalent haseband transmitted signal: s(t) = (Eq.3.2) ckhT(t—kT) k and the resultant signal is then mixed to the carrier frequency and transmitted through the channel. 3.2.2 Receiver Structure The block diagram of the basehand receiver is illustrated in Figure 10(c). The received equivalent haseband signal is: r(t) = (Eq.3.3) s(t) +n(t) +1(t) where n(t) and 1(t) are the hasehand equivalents of the channel AWGN process with double-sided PSD N 12, and the CCI process, respectively. The signal is passed through a receive filter with 0 impulse response hR(t), yielding in a pulse-shape h(t)=hr)*hR(t) where ‘*‘ indicates convolution. The pulse shape considered is the well-known Nyquist raised-cosine filter which eliminates ISI at ’(f) 7 the sampling instants, where h = hR(f) are each has transfer function [13]: 34 ..J& raised cosine filters. The pulse shape H(f) Chapter 3: Symbol Synchronization Analysis in CC’! Channels 11(J) (Eq.3.4) (1_sin[(f_)]) 1+ct 0 4 of the signal. The resultant signal, assuming no frequency offset where a is the excess bandwidth between the transmitted symbol rate and the local reference at the receiver, is: x(t) = ckexp (jp)h(t—kT+t) +u(t) +1(t) (Eq.3.5) k where p is the difference in carrier phase between transmitter and receiver and t is the symbol-rate clock offset or timing error of the receiver sampling clock. The case of ideal carrier recovery will be considered in this thesis to simplify analysis, therefore it is assumed that p=O. The complex basehand Gaussian noise process can be written as u(t)=n(t)*hR(t), and the baseband CCI equiva lent is 1(t)=i(t)*hR(t). Since the signals under consideration in this thesis are quadrature modulated, the transmitted symbols can be expressed in terms of the in-phase and quadrature symbols: ck where = a +jbk (Eq. 3.6) and bk have variance G b, respectively. The symbol timing recovery system must 2 a and G 2 adjust the phase of a symbol-rate clock, in order that sampling for data recovery is performed at the maximum eye opening within each symbol period. Finally, the sampled signal is passed to the decision device, where an estimate of the trans mitted binary data stream, { d } is recovered. , 3.2.3 Co-Channel Interference Model As explained previously the CCI, 1(J), results from other inobile-basestation pairs hans 4. Excess bandwidth a is with respect to the minimum Nyquist bandwidth of 11(27). 35 Chapter 3: Symbol Synchronization Analysis in CCI Channels mitting on the same frequency, at a distance from the mohile-hasestation pair under consideration. CCI is often modeLled in literature as a summation of equal-amplitude unmodulated carriers, each with a statistically independent carrier phase offset from the transmitted signal (see for example [50], [51]). This model has been shown to work well in calculation of BER, with the assumption of ideal timing [5 1]. Here, however, a more comprehensive model of CCI will he used, similar to [50], [62], and [63). CCI is defined as a summation of M independently generated and modulated signals, such that: Al M 1(t) (t) 1 = 1=1 = il 1=1 A: (Eq.3.7) ) 1 khT(t—kT+t÷Wl)exp (Jp h interferer, where the t1 !Kt), has a statistically independent data stream, {il.k} and has carrier phase and timing offsets, Pt and 4’i respectively, from the transmitted signal. it will become appar ent later that this is an appropriate CCI model for considering effects on symbol timing recovery, since it is a summation of cyclostationary processes which may affect symbol synchronization dif ferently than a summation of unmodulated carriers. The analysis will concern itself with the case where each interfering signal is of the same modulation type as that under consideration, which accurately reflects a frequency re-use network such as cellular or PCS systems. The results are also simplified by considering only equal-ampli tude interferers, which yields, for a given C!! ratio, the worst bit-error rate performance [51]. Thus, each interferer has a quadrature modulation similar to the transmitted signal, or k = ‘4k The variance of each interferer can be expressed in terms of the variance of the signal for balanced modulation such as L-PSK and L-QAM as = = Ao = a 2 A . Here, a and are the variances of the independent in-phase and quadrature zero-mean CCI symbol streams, {l,k) and 36 Chapter 3: Symbol Synchronization Analysis in CC’! Channels {tk} respectively, a 2 and are variances of the I and Q data symbols, a and bk respectively, b 2 G and A 2 is the ratio of the interferer power to the signal power. Therefore, the C/I ratio in dB can be expressed as: [C/IjdB = —lOlog (MA ). 2 (Eq. 3.8) For the purpose of the analysis, the carrier phase offset of each interferer will be disre garded. If the term exp(jp ) is included in the symbol sequence, {ilk}. the adjusted interferer data 1 sequences will have the same mean and variance. The forthcoming analysis will depend only on the mean and variance of the interferer data sequences. so as long as the carrier offsets for each interferer is statistically independent of all others, and essentially constant compared to the hit period, the carrier offset can be ignored. This will he sufficient for us to ignore the carrier phase in the timing jitter analysis to follow, and for simplification Pt is set to zero for all interferers. 3.3 Analysis of the ML Non-Data Aided (NDA) Synchronizer Using the method outlined in the Section 2.4.1. analysis begins by finding the power and bias terms inherent in the ML NDA synchronizer. The power of the averaged input v(t) and its phase offset can he derived by solving for v(t) and substituting into Eq. 2.14 to express the average input power and the phase offset: 2 ‘)2 2 P=_a+G) T 9 1 Z ( 0 —) T 2 (1±1/C) (Eq 3.9) = where the expectation has been taken over the CCI timing offsets, uniformly distributed between (— <ji ) 1/C is the inverse of C/I, and: . Zm(f) = FT{g(t)g(t—mT) } = f G(s)G(f—s)exp (—j2nmTf)ds 37 (Eq. 3.10) Chapter 3: Symbol Synchronization Analysis in CCI Channels where g(t), with Fourier transform G(f), is the pulse-shape at the output of the prefliter P(f) seen in Figure 4 prior to the square-law device , such that g(t)=h(t)*p(t). To simplify the final expression, 5 the effect of the Cd ratio on the power term in Eq. 3.9 will be neglected. since the result in the final RMS jitter equation for a C/I of 10 dB will be less than 10%, and eliminating the term will sim plify the result. The input signal is a summation of the transmitted signal, AWGN and CCI, so the input to the square-law device (see Figure 4) for the in-phase (I) channel can be expressed as: y(t) = ag(—kT) +u’ (Eq. 3.11) (t) where u’(t) is the AWGN filtered by the receive filter HR(f) and prefilter P(f), such that u’ (t)=n(t)*hR(t)*p(t), and 1.k is the in-phase (I) data component of the n1 interferer at the kih sym bol interval. A similar equation can be written for the quadrature arm of the synchronizer. To solve for timing jitter, the method outlined in Eq. 2.16- Eq. 2.18 is used. This involves finding the autocorrelation function, R(u,u+ v) of components of v(t), and solving for Sk(JJ, the PSD of the jitter components. The final equation is averaged over the range of possible CCI timing off sets to yield an average jitter perlbrmance. The detailed calculations are performed in Appendix A, which can be simplified, when = + =C1b 2 Ga = l for normalized power to he: (2B) [C V+3 1 V+V 1 4 V 2 (SNR)’ + (SNR) 2 (Eq. 3.12) +2V V 3 (V + (V V 2 (C/1) ÷ + (C 6 ) + 5 6 )/(2M))J 7 V 1 BL) [(C/I)’ 5 2 ( where: 5. Note that g(t) here is the output of the prefilter pnor to the square-law device, as seen in Figure 4. Previously, in Eq. 2.1 Eq. 2.3, g(t) was ussd as a generic signal pulse shape. - 38 Chapter 3: Symbol Synchronization Analysis in CC! Channels Vl=[1_cos(ØA_2O)] 2 V,= 2jZo(1/T)I = 3 v 2 —) [l—cos(ØB— 2 ( 0 Z )J 28 T m t (1/T)I 0 IZ = 4 V 1 2 2i’ SG(—s)ds - (Eq. 3.13) 2 JSGSG(Td5 — jl((s)I2G(ls)ds V= 2TIZo(l/T)I.. 1 1zo(0)1 2 (1/T)I 0 2TIZ 7 V and 1 C = = ÷ (a2) 2 [a4+a4_3((a2) )1 2 where a 4 and a are the expectations of the fourth , (1=1,.. ,6) are dependent on synchronizer ifiter 1 power of the I arid Q data streams. The variables V 1 is dependent upon the modulation scheme used. In this case, signaling, while only the variable C to-noise ratio and carrier-to-interference ratio are defined by C/I = SNR = /2) and 0 (a + a) / (N 2 respectively. MA In Eq. 3.12, the first line represents the performance of the ML NDA synchronizer in an AWGN environment [121. The second line is made up of components introduced by CCI. It can be 1 and V 2 contain a term of the form -cos(4 seen that both V - 20), which represent the cyclostation 5 arity of the received signal. However, the CCI terms 1/3 and V - 7 have no such component. V Examination of Eq. A.6 and Eq. A.8 of Appendix A reveals that each CCI component does, in fact, contribute a cyclostationary component. However, since each contributes a sinusoidal component 39 Chapter 3: Symbol Synchronization Analysis in CCI Channels with a random phase to the variance, the net effect of averaging over the range of CCI timing off sets 1411, for each interferer IKi), is to cancel out the sinusoidal components. Averaging over the range of all possible CCI timing offsets yields the same result as not averaging the offsets, hut including a large number of CCI components, M. For a small number of interferers however, cases of specific timing offsets may yield either better or worse performance than the average timing jitter derived in Eq. 3.12 indicates. However, given that a mobile receiver, by definition, changes orientation and distance from the various sources of CCI, the timing offsets from the various CCI sources would he expected to vary over time, effectively averaging the tim ing offsets over the symbol period. /(2M) term in Eq. 3.12, the timing jitter is independent of the number 7 V 1 Except for the C of interferers present. This term however, is found to be very small when evaluated numerically for some specific cases. For the case of Nyquist filtering, with a Butterworth bandpass prefilter of bandwidth 0. lIT, the difference in RMS timing jitter between I interferer and a lalEe number of 7 tenn will interferers, such as 50, is less than 5%. As long as the bandwidth of 0(f) is small, the V he negligible. Therefore, it can he stated that for cases under consideration in this thesis, with nar row bandwidth prefilters, timing jitter is only weakly dependent upon the number of interferers, M. V term in Eq. 3.12 is very small compared to the 1 Numerical evaluation also indicates that the C 1 is dependent upon the modulation scheme used, the results for QPSK, it/4— 2 term. Since only C V shift DQPSK, and 16—QAM were found to be practically identical (less than 4% difference in eval uation). Therefore, it is expected that the results for the three modulation schemes should be simi lar. However it has been shown with different filter characteristics that higher level modulation schemes such as 64—QAM may exhibit considerably more timing jitter [37]. 40 Chapter 3: Symbol Synchronization Analysis in CCI Channels The normalized RMS timing jitter for the NDA synchronizer in the presence of AWGN and CCI was found by evaluating Eq. 3.12 by numerical integration. Figure 11 illustrates the effects of CCI on the NDA synchronizer for 2BLT= 1/100 with G(f) a 4-pole Butterworth filter with a 3 dB bandwidth of 11(107). Although this PLL bandwidth may be considered large for some tra ditional timing applications [22], the acquisition time required by TDMA systems requires a rela tively large PLL bandwidth be used. Figure 11 shows that although careful system design can eliminate pattern dependent jitter at high SNR, the addition of CCI to the channel greatly degrades jitter performance, and is the chief limit to performance at high SNR. _i 10 I ‘ - Ci1=lOdB I — [ = — jE1o2 Cfl=14d8 : ,‘ L ‘% . \ 10 = ‘ F ‘ C’) ‘. N4 1N0 Interfej \44 ‘1 . ML NDA QPSK_Synchronizerj 0 LL.H 10 20 30 40 50 60 S 70 SNR [dB] Figure 11: ML NDA QPSK Synchronizer: Normalized RMS timing jitter vs. SNR, 2BL=lIlOO, and Butterworth G(f) with iI(i07) bandwidth. 41 Chapter 3: Symbol Synchronization Analysis in CCI Channels Figure 12 illustrates the effect of the signal excess bandwidth, a, on jitter performance for various levels of CCI. The effect of CCI can be seen to be approximately equal over the entire range of bandwidths, since each interferer has the same bandwidth as the transmitted signal and will therefore behave similarly with varying bandlimiting. — ..,. ,,.. - -- ,... ... -\—---“-------- C4 • 1O %%f -2 .... — —— 10 dB C/!=2B Inteerenc CI, j ML NDA QPSK Synchronizer SNR=l5dB .... 1 0 0.1 .... .... ..,. .... 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Excess Bandwidth a Figure 12: ML NDA Synchronizer for QPSK: Norrnali.zed RMS timing jitter vs. excess bandwidth a, SNR = 15 dB. In the absence of CCL the pulse-shape of the symbol sequence may be manipulated to eliminate pattern-dependent jitter (see Section 2.4.1). However there are no subtraction terms in the equation due to CCI since the cyclostationary aspect of the signal has been averaged out, so the 42 Chapter 3: Symbol Synchronization Analysis in CC! Channels CCI jitter terms may not he eliminated. Examination of the CCI term in Eq. 3.12 shows that only by decreasing the PLL loop bandwidth, 2BLT may the effects of CCI he minimized. Of course, this will increase the acquisition time of the synchronizer [7] and is generally not desirable. 3.4 Analysis of Data Aided Synchronizers 3.4.1 Maximum Likelihood Data Aided Synchronizer The equivalent phase-detector function for the ML DA symbol synchronizer, defined in Section 2.4.2 as the average E[vk(r)] (see Figure 5), is unaffected by the introduction of CCI to the system, since the derivative of the I and streams results in Q portions of CCI multiplied by the recovered data a zero-mean process. Therefore: SPDet) = E[vkCr)1 = (o+a)h(t) (Eq. 3.14) which is the same as the case of no CCI, and indicates that the introduction of CCI will not bias the timing estimate by altering the linearized phase detector slope, which will pass through the origin for a Nyquist raised-cosine h(t). As explained in Section 2.4.2, the term vk(t) can be written as a sum of the average, or equivalent phase detector function, and a disturbance term. The disturbance term of Eq. 2.22 can ) being the disturbance due to the data x noise d r then be written as the sum of three terms, 1 term, d2k(t) due to the data x signal term, and d lt) due to the data x CCI term. Therefore, writ 3 ing an expression for vk(t) from Figure 5, and subtracting E[vk(t)j gives: dk(t) = = (t) +d +d k dlk(t) 2 k(t) 3 (akak_m+bkbk_m)h(nT+t) (ak+bk)Nk+ (Eq. 3.16) M + (Eq. 3.15) (aki_m + bk?k_m) h(mT÷t where N is the derivative of the AWGN filtered by hR(t) and sampled at :=kT+rk. 43 Chapter 3: Symbol Synchronization Analysis in CCI Channels The autocorrelation sequences of the three disturbance terms can be written: (m)={ 1 R 2) (N / a + 2 (a ) a b [—h(O)] 0 ,n=O o mO 2)2]2 [22 m=O (m) 2 R = (m) 3 R —[(a2) 2 (Eq. 3.17) 2-i.2 + (a) ]h (mT) ,nO m=O = 0 m0 The last term in Eq. 3.17 is the contribution of CCI to the timing jitter Notice when taking (m) is an impulse func 3 the Fourier transform of the disturbance autocorrelation functions that R (m). Therefore S 1 tion, similar to the AWGN component, R (f) is a constant and may be treated as 3 (O) and the resultant jitter term will be 3 part of the noise-dependent jitter, such that S(O)=S 1 (O)+S proportional to the loop-bandwidth of the PLL. The signal-to-noise ratio can be expressed in this /2) and substitution of Eq. 3.15 0 h (0) / (N case as (a + = - Eq. 3.17 into Eq. 2.25 gives: (2BT) (Eq. 3.18) + BLT) (C/I)’ 2 ( 1 h (0) In the above equation, the first term is the AWGN term, and the second term is the patterndependent jitter term. The third term is inversely proportional to C/I, as well as proportional to the PLL loop-bandwidth. Since it is independent of the SNR, it will have its greatest effect at high SNR when noise-dependent jitter is negligible. Average timing jitter is independent of M, the num ber of interferers. Also note that the result is independent of the modulation scheme employed, 44 Chapter 3: Symbol Synchronization Analysis in CCI Channels provided each scheme has normalized power such that Ga 2 = Gb = 1. The numerator of the third term in Eq. 3.18 due to CCI is an average over all possible tim ing offsets for each interferer. As with the ML NDA case, individual instances of CCI with partic ular values of timing offsets may yield larger or smaller CCI components than the average. However, for large M, or a mobile receiver as explained in Section 3.3, the value observed will be averaged. The result of Eq. 3.18 is similar in form to that in [521, where the effect of a single echo signal on telephone line ML DA symbol synchronization was examined. Since the echo is mod elled as a signal with a statistically independent data sequence and a timing offset from the signal of interest, it is seen that this result is simply a special case of the derivation of Eq. 3.18, where M= 1 and the pulse-shape h(t) is limited to a specific shape. 3.4.2 Modified Maximum Likelihood DA Synchronizer Analysis The modified ML data aided, or MML DA, synchronizer is a modification of the ML DA synchronizer, put forward in [23] to eliminate pattern-dependent jilter which dominates at high SNR in the Ml. DA synchronizer in AWGN. From Eq. 3.18 pattern-dependent jitter depends on the output of the differentiator at t=kT. The MML DA scheme eliminates this term by replacing the differentiator in Figure 5 with filter, HMML(f), which has impulse response hMML(t) [231, so the cascaded filtering on the differentiator arm is now: HR (I’) HMML (f) = HR (f) (J21cf_ h(mT) exp (—J2lrmTf)) (Eq. 3.19) which can be approximated with a digital filter implementation [23]. The first term in brackets is a differentiator, and the second term is a cancellation term. If the output pulse-shape of this filter is designated r(t), which replaces the pulse shape h(t) in the ML DA analysis: 45 Chapter 3.’ Symbol Synchronization Analysis in CCI Channels r(t) = hT(t)*hR(fl*hUML(t) = h(t)_h(mflh(t_mT) Since we consider Nyquist filtering, h(t-mT) = 0 for all cases but m = 1, where h (mT) fore r (mT) = (Eq.3.20) 0, there 0, V m. Now, the autocorrelation of the pattern-dependent jitter term is given by: Rd(m) = E[anan+mafl_kafl+m_l]r(kT)r(lT) = 0 (Eq.3.21) ki so the pattern-dependent jitter term vanishes. Unfortunately, since HMML(f) is optimized to elimi nate pattern-dependent jitter, noise dependent jitter increases and performance of the MML DA synchronizer degrades compared to the ML DA synchronizer at low SNR. The MML DA synchronizer in the presence of AWGN and CCI is now examined. As before, the phase-detector characteristic is unchanged. The disturbance term associated with CCI and its resultant autocorrelation function can he written as: ) 1 (aki,k_m+ bkk_m) r (mT+W k(t) 3 d (Eq. 3.22) = { 3 (m) R (aa + aa) EL r2 (kT + Wi)j = ::: (Eq. 3.23) This is the same CCI term as appears in Eq. 3.17, with r(t) substituted for h(t). The result ant jitter expression, combining the spectrum of Eq. 3.23 with the result in AWGN from [23]: h(0) aMML = BLT) (SNRY’ 2 ( ‘° E + (Eq. 3.24) 2 1 (BL2T) (C/!) h(0) (kT+’qi) 2 r 2 r (0) 46 Chapter 3: Symbol Synchronization Analysis in CC! Channels The second term, the CCI-dependent jitter, is independent of the SNR and will dominate at high SNR causing a lower limit to the minimum achievable jitter, as in the ML DA case. From the HM,L(f) filter shape in Eq. 3.19, it can be seen that although the MML DA scheme has a performance benefit over the ML DA scheme at high SNR, it is more difficult to implement. While the ML DA scheme uses a simple derivative (realizable as a difference equation in digital implementation), the MML DA scheme uses HMML(f), a more complicated filter to implement. However, in either case, CCI will be remain a problem at high SNR. 3.4.3 Results of ML and MML DA Jitter Performance Analysis The analytical results of jitter performance for the ML and MML DA schemes in a com bined AWGN and CCI environment were evaluated numerically for equivalent noise bandwidth of 2BLT= 1/100. The obtained performance results in terms of the RMS timing jitter are shown in Fig ure 13 with the ML DA scheme having a PLL with damping ratio, 2=1I2 which has been show to be near optimum for symbol timing recovery [481. As expected, it can be seen from both figures that the ML scheme outperforms the M1bVIL scheme by approximately 3 dB at low SNR, while the MML performs slightly better at high SNR in the presence of CCI. Comparing the performance of the ML NDA and ML DA synchronizers in Figure 11 and Figure 13 shows that the ML DA tech nique has better performance in CCI. It should be noted, for both the ML DA and MML DA symbol timing jitter results in Eq. 3.18 and Eq. 3.24 respectively, that the CCI jitter term can be decreased only by narrowing the PLL bandwidth. Since the jitter performance is comparable between the two techniques in CCI, the added difficulty of implementing a scheme which eliminates pattern-dependent jitter, such as the MML DA scheme may not be warranted if CCI is deemed to he a problem. 47 Chapter 3: Symbol Synchronization Analysis in CCI Channels — 101 — C I 10 d , h. —‘ p II.. - ,, — ..) —_ii 1-== I-. : j 4= 14dl]— - 10.2 -‘ U .— -I %. .‘. ‘F .. —L ,‘ ..m . C/I =20 F L. 10 4 —-- — —c-- I, C/I. j 1 -I’ I. — DA MML Scheme DA ML Scheme__H— —.j j— — ‘I — ‘I ‘ 1 0 10 20 30 40 50 60 70 SNR [dB] Figure 13: DA ML and MML Synchronizers for QPSK: Normalized RMS timing jitter vs. SNR, 2BLT=lI100, cx=0.35. Figure 14 illustrates the effect of excess bandwidth, a, of the raised-cosine pulse-shape on the timing jitter, with no AWGN present. The MML DA scheme ideally has no jitter in the absence of noise. It can be seen that CCI affects are similar over the entire range of a, although the MML scheme has worse performance than the ML case for small excess bandwidths (a<O.15). This is similar to the MML DA case in AWGN only, where performance is degraded for small a as seen in [231. 48 Chapter 3: Symbol Synchronization Analysis in CC! Chann’ls 10 -2 F io 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Excess Bandwidth a Figure 14: ML and MML DA Synchronizers for QPSK: Normalized RMS timing jitter vs. excess bandwidth c, for 2BLT=1I100, and no noise. 3.5 Analysis of the ML Block Synchronizer The lower hound on performance may he found for the ML block synchronizer as in Sec tion 2.3, with Eq. 2.7 and Eq. 2.8. Starting with Eq. 3.5, the expression for the received waveform with AWGN and CCI, with the CCI expressed as in Eq. 3.7, the expression for the simplified loglikelihood function of Eq. 2.7 is found. The jitter may be expressed as in Eq. 2.26, in terms of the ML function, ignoring the pattern-dependent component for the sake of simplicity: 49 Chapter 3: Symbol Synchronization Analsis in CCI Channels (O)] 2 E[A = — K(a÷ a)(O) 2 + E[(aa + aa) (mT-kT+ NJ )] 1 (Eq. 3.25) and: E[A(O)] K(a+a)h(O) = (Eq.3.26) so that the lower hound to timing jitter variance may be expressed, according to Eq. 2.26 as: 1 — (SNR) K (mT÷W)] 2 E[h h(O) ‘ + (C/I) _, (—h(O)) — K m (Eq. 3.27) h(O) It is observed that the block synchronizer timing jitter lower bound is identical to the ML DA result of Eq. 3.18, ignoring the pattern-dependent jitter term, and with 2BLT= 1/K. Once again, CCI introduces a timing jitter variance term which is independent of the number of interferers M present. The derivation of Eq. 3.27 is actually valid for a generic ML recovery technique which evaluates the ML function. However, the derivation did not take into account time quantization of the ML block synchronizer. The coarse time quantization which is required by the block symbol synchronizer to reduce computational complexity will add an additional lower limit to the RMS symbol timing jitter. Since the system time and memory requirements grow with the number of samples per symbol used to evaluate the ML equation, a trade-off must be made by choosing few enough samples per symbol to fit within system constraints while still providing enough resolution to meet system timing constraints. The lower-hounds for various sampling rates are given in Table 2. The minimum average RMS jitter is calculated from the time quantization noise, while the worst-case RMS jitter assumes that the receiver symbol clock is accurate, but the ideal sampling time lies halfway between two samples. 50 Chapter 3: Symbol Synchronization Analysis in CC? Channels Since [101 indicates that for binary PSK, RMS timing jitter above approximately 0.09T may cause considerable error ax high SNR, choice of a sampling rate of at leastf =8/T is war 5 ranted, although f=16IT is used in [25] and [26] for QPSK. Unfortunately, each doubling of the sampling rate results in a doubling of the calculation required. It will be shown however, that a sampling rate off = 1 6/T is sufficient for minimal timing jitter in CCI. 5 Table 2: Effect of sampling rare on minimum possible jitter at high SNR (no noise Samples per Minimum Average RMS timing Worst-case minimum RMS timing Symbol jitter (G/T) jitter(G/T) 8 0.036 0.0625 16 0.018 0.03125 32 0.009 0.015625 64 0.0045 0.0078125 The lower bound of Eq. 3.27 was evaluated numerically, resulting in Figure 15 for block sizes of K = 32 and 64, and for N= 16. The minimum average RMS jitter was included in the bound so that any prediction of Eq. 3.27 falling below the minimum average RMS jitter were limited to that value. It is interesting to note that a block size of 64 is sufficient to keep the jitter due to CCI below the average time quantization noise. Providing the pattern-dependent jitter is smaller than the average jitter due to quantization, the chief cause of jitter at high SNR will be the jitter due to quantization. Only for K 32 is the CCI a concern. Larger block sizes will only slightly increase performance at SNR <20 dB. 51 Chapter 3: Symbol Synchronization Analysis in CCI Cha,zn1s 10_i : Cl) 1 SNR [dB] Figure 15: DA block synchronizer performance for QPSK: Normalized RMS timing jitter vs. SNR for a=O.35 and 16 samples/symbol. 3.6 Summary This chapter explores the effect of CCI on symbol synchronizer timing jitter performance for the ML NDA and DA tracknig loops including the performance of a modified ML DA (MML DA) scheme. It also examined the performance of the ML block synchmnizer. Results for the ML NDA synchronizer show that, although it has negligible effect at low SNR, CCI is the chief limit to performance at high SNR for systems with low pattern dependent jitter. It was found that the CCI added a constant term to the jitter variance, while the periodic 52 Chapter 3: Symbol Synchronization Analysis in CCI Channels components due to the cyclostationarity of the CCI signals were eliminated by averaging over all possible timing offsets. The three modulation schemes under consideration, QPSK, 7t/4—shift DQPSK, and 1 6—QAM, have quite similar performance for the Nyquist pulse-shape examined. The ML DA and MIvIL DA results also indicate that CCI is the chief limit to timing jitter performance at high SNR. As is the case for AWGN only, in a combined AWGN and CCI environ ment, the DA schemes outperform the NDA scheme, as was found in the cases evaluated in [31]. The jitter equation was found to be independent of the number of interferers present in the environ ment, or the quadrature modulation technique used. It depended only on the CII ratio. As well, the jitter was found to be the same for all of the modulation schemes considered. In both the ML NDA and ML DA cases, the only method for reducing CCI is by reducing the ioop bandwidth of the syn chronizer, although this is undesirable due to increasing synchronizer acquisition time. Analysis of the ML block synchronizer’s performance found that its lower-bound on per formance is identical to the performance of the ML DA scheme, ignoring the pattern-dependent jitter of the latter case, as was seen in [101 for the AWGN channel only. Except for very high levels of CCI such as CII <10 dB and small block lengths such as K<64, CCI was not a concern for the ML block synchronizer, since RMS timing jitter due to CCI was less than the time-quantization error for a reasonable sampling rate of 161T 53 Chapter 4: Computer Simulation of Symbol Synchronization in CC! 4 Computer Simulation of Symbol Synchronization in CCI 4.1 Introduction In the previous chapter the timing jitter performance of three synchronizers -- the ML NDA and DA tracking loops, and the ML block synchronizer were analyzed in an AWGN and CCI environment. The tracking loop analysis was based on linearizing the performance of a PLL with cyclostationary input [12], while the IvEL block synchronizer analysis was based upon a truncation of a Taylor’s series expansion of the ML log-likelihood function [10]. Both of these approaches rely on a linearization of an inherently nonlinear system. and are only valid providing timing jitter is small [11], [22]. This chapter outlines a series of computer simulations performed, modelling a typical hasehand digital communication system, to verify the analytical results of the previous chapter. Section 4.2 gives a detailed description of the computer simulation model. Section 4.3 provides further information on the ML NDA simulation, and presents results of the simulation study. Sec tion 4.4 and Section 4.5 provide results for the ML DA and ML block synchronizer simulations, respectively. Both symbol timing jitter and the bit-error rate (BER) performance for each of the synchronizers are considered, and comparison made to the results of Chapter 3. Finally, Section 4.6 provides a summary of the results of this chapter. 4.2 Computer Simulation System Description Computer simulations were performed to obtain RMS jitter estimates and BER perfor mance for each of the symbol synchronizers using the quadrature modulation schemes QPSK, ic/454 Chapter 4: Computer Simulation of Symbol Synchronization in CC! shift DQPSK, and 16-QAM. The model used was a hasehand digital communication system, as illustrated in Figure 16. Transmitter Channel Figure 16: Block diagram of model for computer simulation. A random binary symmetric source provided data for a modulator generating a baseband modulated signal which was then filtered with a root-raised cosine transmit ifiter. The receive filter was also a root-raised cosine filter, which resulted in raised-cosine Nyquist filter pulse shaping. The demodulator utilizes a symbol timing recover system (STRS) to locate sampling instants. The recovered data sequence is compared to the input data sequence to determine bit errors. The optional signal fading generator was not used in the simulations outlined in this chapter, but is used in Chapter 5. Baseband modulation, demodulation, and CCI generation followed the model outlined in Section 3.2. The CCI generator was realized by M identical transmitter sections, each with a ran dom timing offset uniformly distributed between [-T/2, T12), and equal amplitude. To average over 55 Chapter 4: Computer Simulation of Symbol Synchronization in CC! the range of timing offsets for each interferer, simulations were repeated a number of times with offsets generated randomly. A value of M=50 was used for the case of M —* oo, to yield virtually the same performance as AWGN, due to central Limit theorem [131 which dictates that CCI approaches the statistical characteristics of Gaussian noise as M increases. The simulations assume perfect carrier recovery. Simulations were performed using the BLOSIM simulation package [531, on a Sun Sparc- 10 workstation. Monte Carlo techniques were used to measure the bit-error rate, using error counting techniques. RMS timing jitter was by measured by summing the squares of the difference between the estimated sampling instant and the ideal sampling instant for each sym bol, which occurs half-way through the symbol period for each symbol. 4.2.1 Description of the ML NDA and DA Tracking Loop Simulations The tracking loop synchronizers were designed and adjusted in the absence of AWGN or CCI to achieve phase synchronization in less than 100 symbols assuming no clock frequency error. This limit was chosen in order that the two schemes reach synchronization within a typical TDMA frame, which may last only several hundred symbols. The signal had an initial timing offset of T/2, the worst-case condition. Since AWGN and CCI may prolong acquisition, the first 200 symbol periods were ignored for measurement of RMS timing jitter or BER. T’pical acquisition perfor mance is illustrated in Figure 17 for the no noise case, as well as AWGN with SNR=0 dB. In order to measure RMS timing jitter accurately in the simulations, the ML NDA and DA synchronizers were designed to exhibit more self-noise than might otherwise be present in a welldesigned symbol synchronizer. The main constraint on measurement was the number of samples per symbol. With 128 samples per symbol, the smallest recordable RMS jitter is oE.JT = 11256 = 0.0039. In order to assure correct measurement of timing jitter, both synchronizers simulated had a 56 Chapter 4: Computer Simulation of Symbol Synchronization in CCI normalized RMS pattern dependent jitter well above this value; 0.012 for ML NDA QPSK and 0.0082 for ML DA QPSK simulations. This allowed comparison of the simulation results with published theoretical results at high SNR [121, [221. Further discussion of the simulation jitter measurement error may be found in Appendix B. 0.4 MLDAQPSK Typical Simulation Acquisition 0.3 No noise I C 1- -0.1 -0.2 0 1000 500 1500 2000 Symbol Periods Figure 17: Typical sampling time error during acquisition for two simulations: ML DA QPSK synchronization with no noise, and SNR dB. = 0 The BER was measured by error counting and averaging over each simulation. The assumption was made that a cycle-slip could be detected at the receiver, perhaps by coding tech- 57 Chapter 4: Computer Simulation of Symbol Synchronization in CCI niques above the physical layer, so that cycle slipping only caused one symbol error instead of cre ating a sequence of errors if the slip were not detected. This is implemented in the simulation by monitoring the sampling time with respect to the ideal sampling point. If a symbol is missed, or a symbol is sampled twice, the output hit-stream could not be properly compared with the input bit stream. Therefore, the error is noted, and an extra sample is either include or removed from the output data stream. This greatly simplifies the measurement of BER and was found to be valid in the simulations performed, since cycle slips were only observed in the simulations for instances of very low SNR (<5 dB). In order to average the effects of CCI over all possible timing offsets, a set of 8 simula tions were performed for each result obtained, each with a random timing offset for each co-chan nel interferer. Each of the ML DA and NDA simulations measured performance over 16,000 symbols transmitted. The PSK schemes have a 90% confidence interval of (1.9x10 ,5 5 7.6x10 at ) a BER of 3.815x10 , while the 16—QAM scheme had a 90% confidence interval of approximately 5 , 3.8x10 6 (9.5x10 ) at a BER of 1.9x10 5 5 [54]. These values allow us to satisfactorily measure BER’s down to the i0 level [54]. Ideal BER curves for AWGN and CCI channels were generated for comparison by mea surements made in 8 simulations each of 16,000 symbols transmitted, with 128 samples per sym bol. These curves actually have a constant timing offset due to time quantization of 0.0039T which produces a negligible error (less than 0.5 dB degradation in SNR) over the range of BER’s exam ined. BER performance for the AWGN only case was validated by comparison with its theoretical performance [13]. 58 Chapter 4: Computer Simulation of Symbol Synchronization in CCI 4.2.2 Description of the ML Block Simulations The ML block synchronizer simulations, unless otherwise noted, were performed with 16 samples/symbol, and 256 khits of transmitted data using a t/4-shift DQPSK modulation scheme. 16 samples/symbol was chosen in Section 3.5 as a practical sampling rate for the block synchro nizer algorithm which would yield a worst-case RMS timing jitter due to time quantization for a block of 0.03 125T A total of 8 simulations with randomly chosen CCI timing offsets were per formed, with the same random seeds as for the ML DA and ML NDA schemes. Since the ML block symbol synchronizer has no requirement for acquisition time overhead, timing jitter and BER measurements were performed over the entire simulation. In this case, the timing jitter is the same for all symbols in each block processed, and was averaged over all the blocks processed in each simulation. As with the ML NDA and DA cases, ideal BER curves were generated for com parison by measurements made in 8 simulations each of 32 kbits transmitted, with 128 samples per symbol. 4.3 ML NDA Synchronizer Simulation Results The NDA simulation was designed to be typical of normal implementation. The one restriction is that pattern-dependent jitter he measurable in the simulation at high SNR. A simple second-order Butterworth handpass filter centered atf=1/(2T), with -3dB bandwidth of lJ(1OT) was used as a prefilter. Since the Nyquist raised-cosine roll-off filter used for pulse shaping is not symmetric about f= 1/(2T), the resultant signal shape G(f) is asymmetric about the center fre quency. To eliminate self-noise entirely, the prelIlter would have to be designed to distort the sig nal such that the signal was symmetric aboutf= 1/(2T), as explained in Section 2.4.1. A second-order PLL was employed with a multiplier as phase detector, iteratively 59 Chapter 4: Computer Simulation of SYmbol Synchronization in CCI designed in order to exhibit low timing jitter, while still synchronizing in less than 100 symbols in the absence of noise. A simple loop filter of the form: F(s) (EQ.4.1) = which is the approximate transfer function of a simple, popular passive loop filter for the secondorder PLL [341. The function was realized as an infinite impulse response (1W) filter via the bilin ear transform [55] for computer simulation. To compare with the analytical results of the last chap ter, the PLL was converted to its linearized PLL equivalent equation, and the equivalent noise bandwidth was solved for numerically. The accuracy of this approximation may provide some error in comparing the analytical results to the simulated results. The voltage controlled oscillator constant was KVCO= , and the resultant equivalent . 2 noise bandwidth of the loop was evaluated using linear PLL theory (see [34]) to be 2BLT=0.0065. Simulations were performed with QPSK, it/4—shift DQPSK, and 16—QAM, and results are shown in Figure 18, Figure 19, and Figure 20, respectively. Several observations may be made from Figure 18, the QPSK case: The simulation performance diverges from the theoretical jitter curves for low SNR and exhibits worse performance. This is observed in similar simulations performed in AWGN in [22], and is due to the failure of the linear assumption for the PLL phasedetector characteristic. For the derivation, the phase detector characteristic was assumed linear for small jitter. As the timing jitter increases, the linear approximation is no longer valid. RMS timing jitter performance is worse for the M= 1, or single co-channel interferer case at high SNR by about 25%, which was not predicted in Eq. 3.12. This is due to 60 Chapter 4: Computer Simulation of Symbol Synchronization in CC! the fact that the CCI amplitude is highest for the M=l case for a particular C/I ratio. For this case there is the largest difference between maximum and minimum values of the cyclostationary component of jitter variance due to CCI. The nonlinearity at higher jitter amplifies the larger values, which are no longer completely averaged out by the corresponding lower values of the sinusoidal jitter component. This results in a higher jitter value than predicted. This effect is not a concern at the M=4 case or above where the timing jitter error is less than 2%, since there are more interferers, each with lower amplitude. Figure 19 illustrates the results from ir/4—shift DQPSK simulations. As Eq. 3.12 suggests, the performance matches the QPSK case closely (for example, for infinite M at C/I = 10 dB, the difference between simulations being less than 10%). Figure 20 shows the simulation and analytical results for the 16—QAM modulation scheme. The simulation results here show that the 16—QAM scheme’s perfonuance is slightly worse than the other schemes considered. At high SNR, with CII=lOdB and M=1, the error is about 35%, while for the other two modulation schemes the error was about 25% as compared to the predicted theoretical performance. Even the case of no CCI exhibits slightly worse perfor mance than expected. The 16-QAM signal has a 4 different amplitude levels in each of the I and Q signals, so that for a constellation which is normalized to have unity power, the signal power may vary from 0.4 to 1.3. It is believed that these signal power variations affect the PLL tracking, since the loop is designed for a particular input power level. QPSK simulations were performed with the previously normalized amplitude set to 0.4 and 1.3. In the absence of noise the timing jitter increased as much 61 Chapter 4: Computer Simulaiion of Symbol Synchronization in CCI as about 45% from the unity power case. Therefore, the variation of amplitude of the 16—QAM modulation scheme causes more timing jitter due to the synchronizer’s dependence on input amplitude level. As can be seen in Figure 20, this leals to an increase in RMS jitter over the QPSK simulation results. Therefore, the analytical results arrived at in Section 3.3 will underestimate jit ter for higher-level quadrature modulation schemes, although for 16-QAM, the error is only about 10% greater. I I 10_i :‘‘: ‘ - ‘. ‘ . . ‘ ) — .‘ , L. . • -‘_. 0 : c’ CA=lOd T= J ..L . Pr 14 dB b U . ‘ 0 (% . 2 ir ML NDA QPSK Simulations A . • o D 0 1 — — — — I -,, -5 No tnterfere Theory Simulation, CA 10 dB, M’Simulation, CA 10 dB, M = 4 Simulation, C/I= 10 dB, M I Simulation, C/i= 14 dB, M Simulation, CA=l4dB,M=4 Simulation, C/I= 14 dB, M = 1 Simulation, No Interference 5 15 25 - 35 45 SNR [dB] Figure 18: Simulation results for ML NDA QPSK scheme: Normalized RMS timing jitter vs. SNR, 2BLT=00065, aO.35, and 128 samples/ symbol. 62 Chapter 4: Computer Simulation of Symbol Synchronization in CC! 10_i P ;lOdL F-____ I j14r I I.’ __,i - 0 C,, — : ML NDA • • A o O 1 -5 1V4 DQPSK,mulatiOnS No lnteeren theory Simulation, CA10dB,M Simulation, C/I = 10 cIB, M = 4 Simulation, C/I= 10 dB, M = 1 Simulation, C/I= l4dB,M Simulation, CA —14 dB, M 4 Simulation, CA=l4dB,M=1 Simulation. No Interference 5 25 15 35 45 SNR[dBl Figure 19: Simulation results for ML NDA W4—shift DQPSK scheme: Normalized RMS timing jitter vs. SNR, 5 2BLT=O.OO& a=0.35, and 128 , samples/symboL 63 Chapter 4: Computer Simulation of Symbol Synchroni:ation in CC! ,...,,,.,,,,,,,,,,, _i 10 3- %A=14dB* -5 F- C.’) 2 io : ML NDA 16-QAM Simulations Theory - - - - 1 A • Simulation, CA= 10 dB, M • Simulation, C/1= 10 dB, M Simulation, C/1= 14 dB, M o Simulation, CI1= 14 dB, M = = 4 1 — 4 o Simulation, C/I = 14 dB, M = 1 0 Simulation, No Interference ,,,L,,,[ -5 No lnterference..... Simulation, Cfl=. 10 dB, M 5 .• 15 25 35 45 SNR [dB] Simulation results for ML NDA 1 6—QAM scheme: Normalized RMS timing jitter vs. SNR, 2BLT=0.OO 5, a=0.35, and 128 samples/ 6 Figure 20: symbol. Table 3 illustrates the percentage error between the simulation results and theory for dif ferent values of the excess bandwidth, a, of the raised-cosine filtering with no AWGN , C/I 6 dB, and a large number of co-channel mterferers (i.e. M —* Do). = 10 The error increases at lower values of a since the timing jitter of the ML NDA scheme is larger at low a, and leaves the strictly linear region where the analytical results are correct. The error at large a indicates that the value of 2BLT 6. The RMS timing jitter measured in the absence of AWGN is essentially a jitter error floor as shown in Figure 18 to Figure 20. 64 Chapter 4: Computer Simulation of Symbol Synchronization in CC! used in evaluating Eq. 3.18 is slightly inaccurate, since the value was evaluated for the equivalent linearized analog system. This value affects the slope of the curve, as well as its minimum value. Table 3: Simulation Error vs. excess bandwidth a, ML NDA synchronization with QPSK modulation, CII 10 dB, M —* , 2BLT=0.0065, and no noise. Excess Bandwidth a RMS Jitter Simulation error (%) 0.10 21.7% 0.20 13.1% 0.35 -7.3% 0.50 -9.7% 0.90 -10.2% BER curves for the simulations are not included here, hut showed negligible effect of increasing timing jitter on the BER performance of the systems because the worst-case jitter at high SNR is still below 6% of a period. A sample of measured BER performance may be seen in Figure 25 in Section 4.5 for the block synchronizer, whose jitter performance at high SNR is the worst of all simulations performed. Therefore, it is concluded that CCI interference at the decision device with ideal symbol synchronization is the limiting factor on performance for these modula tion schemes. The addition of a realistic ML NDA symbol synchronizer for a combined AWGN and CCI environment did not noticeable degrade the BER performance. Within the limits of the theoretical assumptions leading to the analytical results, the simu lations show that the analytical results correctly predict timing jitter performance in the presence of CCI. The analysis underestimates performance for RMS jitter of about O.02T or above, which is the same value where performance began to diveie in simulations performed in [22]. However, the amount of jitter caused by CCI is not a significant limit on system performance at C/I ratios of 65 Chapter 4: Computer Simulation of Symbol Synchronization in CCI up to 10 dB, which would be considered a high level of CCI in today’s frequency reuse systems. At high SNR where CCI has its most prominent effect the equations predict the resultant RMS tim ing jitter with an error on the order of 10% or less for the constant amplitude constellation modula tion schemes, with the case of one interferer giving the most severe error. A difficulty with evaluating the analytical results is in determining the exact value of the PLL equivalent noise bandwidth, which has a direct effect on the symbol timing jitter results at all values of SNR. 44 ML DA Simulation Results The ML DA synchronizer lends itself well to digital implementation, and was simulated as explained in Section 2.3. The derivative in each arm of the synchronizer was approximated with a difference equation, x[nj = x[nj —xn— 11. The decision device for the QPSK and 1 &-QAM simulations simply chose the symbol from the constellation whose Euclidean distance is closest to the sample. The it/4—shift DQPSK decision device simulated was a simplification of the ideal decision device. For it/4—shift DQPSK, the ideal decision device must decide between four possible constellation points for each symbol, 7 and also keep track of which of the two possible constellations is currently used for transmission. fri the simulation the decision device was replaced with a simple 8—PSK Euclidean-distance deci sion device. The performance of this simplification will be identical to the ideal decision device at high SNR, but may suffer some degradation when interference is prominent. This simplification was used only for symbol synchronization; a normal differential detection scheme with I and Q binary decisions was implemented to recover the data from the signal once the sampling instant 7. We note here that the ML DA decision device may be quite sophisticated, and employ techniques such as Vit erbi decoding to better the symbol estimates. 66 Chapter 4: Computer Simulation of Symbol Synchronization in CCI was known. The PLL loop filter (see Figure 5) was a simple one-pole low-pass filter transformed to the discrete domain via bilinear transform [55], found through an iterative process to have 3 dB cutoff frequency at .o=itI3. This provided less than 0.O1T RMS timing jitter at high SNR, while still exhibiting measurable self-noise in the absence of interference or noise so simulation results could be compared to theoretical results. The synchronizer parameters were arrived at by an iterative design process, whose goal was a small hut measurable timing jitter at high SNR, and an approximate acquisition time of 100 symbols or less. The number controlled counter constant was KNCc=O. O, the resultant damping 6 factor of the equivalent second order PLL was =1.65, an overdamped system, and the equivalent noise bandwidth was evaluated to be 2BLT=0.008. These values were calculated for the equivalent analog PLL transfer function. Figure 21 to Figure 23 illustrate the simulation results for the three modulation schemes under consideration. As Eq. 3.18 suggests, performance does not depend upon the number of inter ferers, M, present. As predicted by analysis, the performance of the QPSK and it/4—shift DQPSK schemes are comparable. RMS jitter at high SNR differs by only about 4% between the two simu lation results, well within experimental error. Both modulation schemes exhibited about 15% error in the absence of CCI at high SNR compared to the analytical results. This is due to error in calcu lating PLL linear transfer function, which resulted in an error in both the PLL equivalent noise bandwidth, as well as the damping ratio . This error drops to less than about 10% for CII=lOdB and high SNR, where the CCI dependent jitter term dominates. The use of an 8—PSK decision device in place of the ideal it/4—shift DQPSK decision device does not cause appreciable degrada 67 Chapter 4: Computer Simulation of Symbol Synchronization in CCI tion in timing jitter at low SNR, compared with the QPSK case. — ... .... .... .... ....- — .... 10• ‘ P - ‘ ‘* — ,‘ -e — — — — - A u— k — 10 C 3] Th_-_ = — — — — - - ‘ I — — I — V A=14 /1 - F A 11 1o2 — — — — — = = — p — — No lntetferen -- — — JML DA QPSK SimuIatio Theory C’ Simulation, M 0 A Simulation, M = 1 D Simulation, M —j io -5 .. 0 5 10 15 20 25 30 35 40 45 50 SNR [dB] Figure 21: Simulation results for ML DA QPSK scheme: Normalized RMS timing jitter vs. SNR, 2BLT=0.008, a=0.35, and 128 samples! symbol. 68 Chapter 4: Computer Simulation of Symbol Synchronization in CC! ..,, . 10 ,... ,.., ,.. ..., ..,. -1 ‘ , - ,‘ ‘w — —— —- coJ ‘I I I V - JI I! — — - ,‘ — A = No lnterteref ..JML DA pi/4-shift DQPSK Theory Simulation, MO Simulation, M=1 Simulation, M -3 5 10 // -- 1E 0 J- ‘4= I J -- F , -5 - — , t — 10 - — — — — — — — — — ..., ..,. .,.. 15 20 25 — .,,. 30 35 40 45 50 SNR [dBJ Figure 22: Simulation results for ML DA irJ4—shift DQPSK scheme: Normalized RMS timing jitter vs. SNR, 2BLT=0.008, a.=0.35, and 128 samples/symbol. The ML DA scheme does not exhibit worse perfonuance for the M= 1 case employing QPSK or it/4—shift DQPSK, as was found for the ML NDA simulations. This is because the multi plication of the signal by the estimated symbol instead of squaring cancels the cyclostationary nature of the CCI terms. 69 Chapter 4: Computer Simulation of Symbol Synchronization in CC! .... . ... . 0 10 ci 1 ci OdB] +D FZL :: —— h --——--—— — — c.’ 1o -2 = — — C414 .rML DA 16-QAM Simulations Theory — — — — 0 Simulation, M = 0 Simulation, M 1 C Simulation, M ,,,.,,,,,,,,.,, -5 0 5 10 20 15 — — .,.. ..., — — 25 30 35 40 45 50 SNR [dB] Figure 23: Simulation results for ML DA 16—QAM scheme: Normalized RMS timing jitter vs. SNR, 2 BLT=0.OOB, cx=0.35, and 128 samples! symbol. The simulated performance of the ML DA synchronizer for 16—QAM modulation per forms about 30% worse than the predicted performance with no interference, and twice as poorly in the worst case, with CII = 10 dB, and M —* oo. Comparing the theoretical results with the equiv alent computer simulated results, it appears that the ML DA synchmnization technique is more sensitive to the signal amplitude changes. However, the ML DA simulated results, even in the worst case, are better than the equivalent results of the ML NDA simulations, which even had a smaller equivalent noise bandwidth. 70 Chapter 4: Computer Simulation of Symbol Synchronization in CC! For 16—QAM the M=l and M jitter for the C/I = — oo simulations do exhibit significant difference in timing 10 dB case. If the BER of the CII recovery, an error floor due to CCI is observed at BER M —* . 10 dB case is examined with ideal timing = = 2 for 2 for M=1, and BER=7.3x10 1.9x10 Obviously, the large increase in the number of decision errors for this extreme amount of interference causes the discrepancy in jitter performance, since decision errors in the ML DA syn chronizers will degrade tracking performance. The results may be made worse by nonlinear effects at high (e.g. > 0.027) jitter. Table 4 illustrates the difference between theory and simulation results for a range of raised-cosine filter excess bandwidth a for the QPSK modulation scheme, with no noise present and C/I = 10 dB. As seen in the NDA simulations, the simulated results are approximately 10% worse than theory predicts over the range of a, hut the amount of error increases for small a. The error over most of the range can be explained by simulation error due to discrete time (see Appen dix B for details). Table 4: Simulation Enor vs. excess bandwidth. ML DA synchronization, for QPSK modulation, C/!= 10 dB, M —* oc, 2BLT=O.008. and no noise. Excess Bandwidth a RMS Jitter Simulation Error(%) 0.10 28.25% 0.20 11.6% 0.35 9.2% 0.50 9.9% 0.90 10.4% As was the case with the ML NDA simulation results, the analysis of Chapter 3 correctly predicted the results found in the simulation of the ML DA scheme. Once again, the linear assump 71 Chapter 4: Computer Simulation of Symbol Synchronization in CC! tion of PLL theory leads to underestimation of symbol timing jitter at higher jitter values. Despite the ML DA synchronizer simulated having an equivalent noise bandwidth 20% lalEer than the ML NDA synchronizer simulated, the ML DA synchronizer exhibited better performance in all cases, although it is susceptible to decision errors since it incorporates them into the tracking loop. Con 2 in the 16-QAM simulation), deci sequently, where the BER is large (for example, BER> 2x10 sion errors will increase the timing jitter of the recovery scheme. 4.5 ML Block Synchronizer Simulation Results The block synchronizer was implemented in simulation directly from the description in Section 2.4.3 for it/4—shift DQPSK. Since the ideal sampling instant occurs exactly halfway between two samples in the simulation, the worst-case time quantization error was be measured in the simulation rather than the average time quantization error. That is, as explained in Section 3.5, in a real system the receiver’s symbol rate clock would not be perfect, so the error in selecting a sampling instant, for negligible timing jitter, would he due to sampling error, and would be uni formly distributed over the time between sampling instants. However, in the simulations per formed, the ideal sampling rate falls directly between two samples, and the error is that of the worst-case time-quantization. For a simulation of 16 samples/symbol, which was chosen as a real istic sampling rate (see Section 3.5), this corresponds to a minimum measurable RMS timing jitter of 0.03 125T It is seen in the simulation results in Figure 24 that the pattern-dependent jitter term is below the minimum measurable jitter, and therefore the chief limit to performance at high SNR (i.e., 10 dB) is the sampling rate at the input. As can he seen, the use of a 32—symbol block reduces jitter performance by about 3 dB at a normalized RMS timing jitter of 5x1(T . The effects of CCI 2 72 Chapter 4: Computer Simulation of Symbol Synchronization in CCI are negligible, except for the combination of a 32—symbol block and C/I = 10 dB, where CCI degrades the jitter to less than 5% above the worst-case time-quantization jittez At higher levels of CCI, the CCI term will begin to dominate at high SNR. However, for C/I = 10 dB, the BER is 3 for ic/4-shift DQPSK (as shown in Figure 25), which would indicate barely mar about 5.3x10 ginal performance for most wireless telecommunications applications. — ..., ML Differential Symbol Block Synchronizer Simulations for I4-shth DQPSK Minimum measured jther, 16 sps —0—-—-— block length = 32, No Interference block length = 32, Cii = 10 dB, M block length = 64, No Interference ock length=6CA0dM • ,. - - - - - — z \ -1 v 1o E F C.’) H-Z Z 1 o-2 - -5 0 .... 5 .... 10 ... 15 .. 20 25 30 35 40 45 SNR [dB] Figure 24: ML Differential Symbol Block Synchronizer for it/4—shift DQPSK: Comparison of 32 and 64 block length synchronizers in CCI, cx=O.35, and 16 samples per symbol. The simulations used 16 samples per symbol, which yielded an RMS symbol timing jitter of 0.031 25T at high SNR. Use of a smaller number of samples per symbol would increase the sym 73 Chapter 4: Computer Simulation of Symbol Synchronizaüon in CCI bol timing jitter at high SNR to a level which would continue to dominate over the additional jitter caused by CCI. ‘c — Simulated Bit Error Rate Performance for 1t14-shift DQPSK with Block Synch. — 101 Ideal timing Block length Block length lssamplespersymbol — 32 64 > 10-2 — \ ‘ ‘ ‘1 4) c 1=10 dB, M - \ Tee1’ E-EEEEEE 1o ... ... ... -5 0 5 .... ... 10 15 20 . ... 25 .... 30 35 40 SNR [dB} Figure 25: Bit error rate performance for block synchronizer and it/4— shift DQPSK modulation scheme, cx=O.35 and 16 samples/symbol. Comparison with Figure 15 shows that the block synchronizer using differential symbols is less than 1 dB in timing jitter performance from the lower bound for no CCI at a timing jitter of O.05T. Therefore the use of differential detection for ML block symbol synchronization does not significantly degrade performance in AWGN. The technique loses about 3dB in timing jitter per fomiance due to CCI at an RMS timing jitter of O.05T over the lower bound for the non-differen 74 Chapter 4: Computer Simulation of Symbol Synchronization in CCI tial block synchronizer for both the 32 and 64 block size cases, where only 1 dB or less was predicted. This deviation at higher jitter is likely due to the same non-linearity exhibited in the ML DA case, which yielded a quite similar expression for symbol timing jitter, and was seen to under estimate the jitter when it was at this level. Figure 25 illustrates a typical BER curve for the block synchronizer. It was included since the jitter here is larger than for the DA or NDA simulations. As can be seen, the simulated BER curve and ideal BER curve are essentially coincident over a wide range of SNR. The normalized RMS timing jitter for high SNR is 0.03 125T, which has negligible effect on the measured BER down to 10. The curve is included as the worst-case BER performance simulated for it/4—shift DQPSK, with C/I = 10 dB. The error floor here is due to the presence of CCI. However, decision errors due to timing jitter are negligible, so the interference effect on the decision device is the lim iting factor, not the interference effect on the symbol timing recovery system. 4.6 Summary This chapter has presented computer simulation of the ML NDA and DA tracking loops, and the ML block synchronizer, employing QPSK. t/4-shift DQPSK, and 16-QAM modulation in a combined AWGN and static CCI channel. The simulation results are compared, for various num bers of interferers at C/I levels up to 10 dB, with the analytical results for RMS timing jitter derived in Chapter 3. From the obtained results, it is observed that the computer simulations vali date the analytically derived theoretical results, except where the linear assumption is no longer valid for jitter values above about 0.02T in the cases simulated, where the analysis underestimates the simulation performance. This effect was also observed in [221 for the AWGN channel. For the ML NDA case, timing jitter performance is worse for a single interferer than for 75 Chapter 4: Computer Simulation of Symbol Synchronization in CC! larger numbers of interferers. This is not predicted by the analytical results of Chapter 3, and is due to nonlinear performance of the synchronizer. The analytical results derived for symbol timing jit ter in Chapter 3 assume the synchronizer has small jitter, and allows it to remain operation in the linear PLL region. For the case of ML NDA synchronization with one interferer, the disturbance to the timing wave has a larger amplitude, and forces the PLL out of the linear region. However, for larger numbers of interferers, the simulations differed by less than 10% from the analytical RMS timing jitter results at high SNR, with C/I up to 10 dB. The ML DA scheme was found to he independent of the number of co-channel interferers present as predicted by analysis. The simulations for jitter performance are in good agreement with equivalent analytical results at high SNR, with errors of 15% or less at C/I up to 10 dB. However, the case of 16-QAM modulation differed by about 30% from predicted with no CCI present at high SNR. This is believed due to the amplitude variations of the signal’s bit-energy, which are not accounted for in the analysis, and are not present in QPSK and ir/4-shift DQPSK cases simulated. It should be noted that the ML DA synchronizer simulated exhibited better performance than the ML NDA synchronizer simulated, despite having a 20% larger equivalent noise bandwidth. For the case of 16-QAM modulation at C/I = 10 dB, it was observed that the ML DA synchronizer technique exhibited twice the symbol timing jitter predicted at high SNR with M —* oo• This is due to the ML DA technique using a decision device, which is susceptible to the extreme BER perfor mance due to the high level of CCI present. The ML block synchronizer simulations showed that at a sampling rate of 161T and block lengths of 32 symbols or more, the amount of additional symbol timing jitter due to CCI at levels of up to C/I= 10 dB is not significant compared to the worst-case sampling error of time-granularity due to the sampling rate. 76 Chapter 4: Computer Simulation of Symbol Synchronization in CC! Finaily. BER computer simulated results were examined. For C/I levels of up to 10 cIB, the simulated results indicate that none of the syichronization schemes has a significant effect on the BER performance for either of the three modulation schemes examined. In all cases simulated, the degradation of BER performance due to symbol synchronization was negligible compared to the case of ideal symbol timing recovery. 77 ChapterS: Symbol Synchronization in Multipath Fast Fading Channels 5 Symbol Synchronization in Multipath Fast Fading Channels 5.1 Introduction One source of serious degradation in system performance for mobile wireless digital trans mission is due to multipath fading. Fading introduces an irreducible error-rate in reception, due to the random-FM modulation effect [3]. The effects of frequency non-selective (flat) and frequency selective multipath fading on system performance have been studied extensively (see for example [31, [13], [14], [64], [65]). However, in the open technical literature, the problem of symbol syn chronizer performance in fading channels has not received as much attention. A Ml. synchronization structure has been proposed for scattering channels which encom passes a whole range of frequency selective and non-selective fading channels [32], [33]. This syn chronizer is a tracking loop which attempts to locate the peak received signal energy of each symbol in time and frequency, and use this as the optimum synchronization instant. However, the scheme utilizes information about channel characteristics in the form of the scattering channel autocorrelation function. The method’s computational complexity and reliance on channel infor mation makes it an unlikely choice for implementation. Also, its symbol timing jitter and BER per fonnance are not predicted, so designers cannot accurately predict system performance for this technique. In [26] a complete synchronization system including symbol timing and carrier phase recovery as well as carrier frequency offset estimation was implemented and tested via computer simulation and hardware measurement. The synchronizer operates on the same principles as the 78 Chapter 5: Symbol Synchronization in Multipath Fast Fading Channels block synchronizer previously described (see Section 2.4.3), using differential symbols for estima tion of a QPSK modulated signal, performing all metric calculations with sampled phases. The system has been tested to good result in a two-ray frequency selective fading channel, with data rate of 455 kBaud and with diversity selection included in the synchronization algorithm. In [61], the effect of multipath delay spread on a ML NDA symbol synchronizer was examined. It was found that an ‘infinitely fast’ timing loop, does not significantly improve BER performance at high SNR, providing the separation of the equal-amplitude two-ray model is less than O.2T In this case, the cause of irreducible BER is due to eye closure caused by fading, and not by imperfect symbol synchronization. However, it should be pointed out that performance of the synchronizer was restricted to hinary-PSK (BPSK), and delay spreads of less than O.2T Further more, in [61] the analysis assumes that delay spread is small compared to the symbol period, and is not extrapolated to larger delay spreads. Furthermore, it is important to note that the performance of DA and NDA tracking loops in flat fading channels have not been examined in the open techni cal literature over a wide range of BFT products. A significant advantage of these schemes is that they are simple to implement and their performance is well understood for AWGN channels. The question examined in this chapter is how these schemes perform in frequency non-selective and frequency selective fading channels, and whether more complex schemes are necessary in such channel conditions. To this end, this chapter examines the effect of frequency non-selective and selective fading on the ML NDA, ML DA, and ML block synchronizers through a simulation study using itI4-shift DQPSK modulation. This chapter is organized as follows: Section 5.2 introduces both frequency non-selective (flat) and frequency selective fading models used in the computer simulations to be performed. The results of those simulations are discussed in Section 5.3 for both types of fading, using ir/479 ChapterS: Symbol Synchronization in Multipath Fast Fading Channels shift DQPSK as the modulation scheme for simulation. Finally, a summary of the chapter and its conclusions are provided in Section 5.4. 5.2 Fading Models 5.2.1 Frequency Non-Selective (Flat) Fading Model Description Frequency non-selective fading, or flat fading, is a model of the effect on a received signal due to motion of the receiver. A signal received at a mobile receiver is a summation of reflections from many different scatterers in the surrounding terrain. Each signal arriving at a different angle will suffer from a frequency shift due to the Doppler effect [3]. The effect of this frequency shift on the summation of signals from all directions results in a fading process known as frequency non-selective fading [3], [14]. Frequency non-selective fading can be modeled mathematically by the complex fading process [13]: (EQ.5.1) f(t) =f (i) +JJQ(t) 1 (t) andfQ(t) are the in-phase and quadrature Gaussian random processes, respectively. The 1 wheref fading process is a multiplicative interference, with the received signal expressed, in the absence of AWGN, as [31: r(t) =f(t)s(t) Such a representation may represent either Rayleigh (for which Ricean (for which E [J, (t)] 0, E [fQ (t)] = (Eq.5.2) E [J (t)] = E [fQ (t)] = 0 ) or 0 ) frequency nonselective (flat) fading, since the fading amplitude will follow either a Rayleigh or Ricean distribution. Figure 26 illustrates the generation of the fading process for simulation. The in-phase and 80 ChapterS: Symbol Synchronization in Multipath Fast Fading Channels quadrature functions are generated as white Gaussian noise, and then filtered by the fading filter, H/f). The characteristics of the fading process are controlled by the PSD of the fading process. In this thesis, the land-mobile fading model is used, so that [3]: Hf(f) = I q[j1c/J V c 1 o (Eq. 5.3) j9>F f(t) real I-channel zz. complex 0-channe e jn/2 Figure 26: Block diagram of fading process generation for simulation. Although the magnitude of H/f) can approach infinity for f—* F, in the simulation the magnitude of H/f) is limited to 30 dB. The one-sided fading bandwidth, F is simply half of the double-sided fading bandwidth, BF. The level of fading is usually expressed as the product of fad ing bandwidth to symbol period, BFT The fading filter of Eq. 5.3 has been shown to closely model Rayleigh land-mobile fading processes [14], [56]. For generation of Ricean fading, the signal is Rayleigh fading as above, and added to an unfaded version of the signal, whose amplitude can expressed as a power ratio of faded to unfaded signals in dB: 2 E[f(t)J K= lOlog 10 where and 2 2 (Eq.5.4) ) are the variances of the in-phase and quadrature fading processes. 81 ChapterS: Symbol Synchronization in Multipath Fast Fading Channels The simulation results presented are limited to BFT> 0.003, due to the frequency resolu tion needed to represent the land-mobile fading process in a frequency array. This limits the dis cussion to the ca.se of fast fading processes. 5.2.2 Frequency Selective Fading Mode! Description The Rayleigh and Ricean fading processes model the arrival of scattered signals to a mobile receiver. Each signal follows a path from transmitter to receiver of different length and may combine to creare a composite signal which suffers time dispersion. While Rayleigh fading models a spreading in frequency due to the Doppler effect, time dispersion also models a spreading in time due to different path lengths [13]. It is known as frequency selective fading since different parts of the signal spectrum may be affected in different ways. Time dispersion causes a time-varying channel impulse response which spreads the received signal energy over a finite time interval, usu ally denoted the channel time-spread, td [14]. Measurements of such channels in an urban envimn ment show that most of the received energy fmm a transmitted signal is concentrated at only several distinct times, due to reflections from larger terrain features [17]. A simple way to model such a channel is to reduce the time-spread to a second signal path, Rayleigh faded with a fading process statistically independent from the original signal’s fading process, with an additional time delay, td. The model for such a channel is shown in Figure 27, where the fading processes are gen erated as explained in Section 5.2.1. Measurements of such time-spreads for an urban environment give values of td in the range of 1-20 l.tsec [15], [16], [17], [66], which is up to 1/2 of a symbol period for a data rate of 24 kEaud. For a mobile receiver, the time-spread of the channel will be changing as the receiver moves through the environment. The two-ray model above portrays the case where the time- 82 Chapter 5: Symbol Synchronization in Multipath Fast Fading Channels spread changes slowly within the timeframe of the simulation. It should be noted, however, that the two-ray model is recommended by the Telecommunications Industry Association (TIA) Stan dards Committee for evaluation of system tolerance to delay-spread [57]. Due to the severe degradation in system performance attributable to frequency-selective fading. methods to counteract it, including time-varying adaptive equalization have been devel oped (see for example [58]). For the purpose of this thesis, however, it is assumed that no equaliza tion is present. Frequency Selective Faded Signal s(t) Figure 27: Block diagram of generation of a frequency-selective faded signal for simulation. 5.3 Simulation Results and Discussion 5.3.1 Fast Frequency Non-Selective Fading The introduction of a frequency non-selective (flat) fast fading process to the channel has a deleterious effect on system performance, due to the random FM interference of the fading process [3], [13]. As seen previously in Section 2.2, the received signal must be cyclostationary in order 83 ChapterS: Symbol Synchronization in Multipath Fast Fading Channels for timing recovery to take place. The received signal, along with its mean and autocorrelation function may he expressed as: r(t) =f(r) ckh (t—kT) A: E[r(t)] E[f(t)1E[ckih(tkT) (Eq.5.5) A: E[r2(t)j = E[f(t)1 E[ck]h (r—kT) 2 where the information sequence {ck} is assumed statistically independent. Clearly from the above equation, the received signal remains a cyclostarionary process in the presence of Rayleigh or Ricean fading, so symbol timing recovery is still a possibility. If the fading process is treated as a modulating waveform, the ML function may still be expressed as in Eq. 2.7, where the estimated sequence, {ck} is now replaced by the total modula tion, or: = cJ(kr) (Eq. 5.6) which is an estimate of the fading random FM as well as the symbol. The ML DA and ML block synchronizers will use this estimate over the entire symbol period, so it is important that the fading does not change substantially over a symbol period. Since removal of this modulation term is the aim of the symbol synchronizer, it appears that symbol synchronization may work well in fading environments where the fading is correlated over several symbol periods. Computer simulations were performed using the it/4—shift DQPSK modulation scheme, with raised-cosine Nyquist pulse-shaping, and an excess bandwidth of oO.35, which is the speci fication of the North American TDMA digital cellular standard [6]. The simulation used a sam pling rate off =64/T for the ML DA and ML NDA synchronizers, andf 5 =16/T for the ML block 3 84 Chapter 5: Symbol Synchronization in Multipath Fast Fading Channels synchronizer, which utilized a block-length of K=64. Approximately 200 kbits were simulated for each value attained, averaged over 6 simulations each for the tracking loops, and approximately 500 khits, over 4 simulations, for the block synchronizer. all with the same parameters as described in Section 4.2. For comparison, the performance with ideal symbol timing was approximated through simulation with 64 samples/symbol, which results in negligible degradation in perfor mance from the actual ideal sampling case. The tracking loop synchronizers were given a wide margin of 400 symbols in order to achieve timing acquisition, since the timing acquisition in worst-case simulations was observed to increase by as much as 100% compared to the no-noise case, due to the added interference. This points out the great advantage of the ML block synchronizer, which requires no acquisition period and may be used with much more confidence in extreme failing conditions without concern for loss of tracking. Figure 28 shows the timing jitter error floor, or the irreducible symbol timing jitter perfor mance over a range of BFT products. These simulations were performed with no AWGN present to examine the lower limit on performance caused by fading. A number of observations and conclu sions may he made from these results: 1) Performance is similar for all synchronizers over a wide range of BpT products. For BFT < 0.10, the RMS timing jitter is below 3.5% of a period, which is a severe fading environment. This corresponds to a mobile cellular user travelling at 100 km/hr, trans mitting on a carrier frequency of 850 MHz, with a data rate of less than 1500 Baud. Since the North American digital cellular system operate at 24 kBaud, at a frequency about 850 MHz, the most severe fading expected in such a communication system 85 ChapterS: Symbol Synchronization in Multipath Fast Fading Channels should be BFT < 0.004 for operation from an automobile. 0.045 Irreducible Jitter vs. BT Fading Product ML NDA, Rayleigh Fading ML DA, Rayleigh Fading ML NDA, Ricean Fading, Kf —3dB ML DA, Ricean Fading, K=3dB ML NDA, Ricean Fading, K,=1O dl ML DA, Ricean Fading, K =lOdB 1 ML NDA, Ricean Fading, K2OdB MLDA, Ricean Fadin =20dB 0.04 • A 0 0.035 • - H —.# —. ::i 6sI gl’ - - • 0.03 — — - [,ock Synchronizer, 1 0.025 ii —-- ‘ / t V 0.02 — — — — — — — ‘‘ V 0.015 ——:. 0.01 — , — uI .. . - r’ ... . -— M4I 71 — lI 1 P ...—“. — — I 0.005 0.001 0.01 0.1 B,T Product Figure 28: Symbol timing recovery performance in frequency nonselective Rayleigh and Ricean fading for the 3 synchronization schemes, no noise. 2) The Ml. DA synchronizer outperforms the ML NDA synchronizer for this range of fading, as was the case in AWGN and CCI environments. 3) The ML block synchronizer performance is limited by the sampling rate of the receiver, not by the fading in this range of BFT products. The timing offset of 3.125% of 7’, which is inherent in a block synchronizer with practical sampling rate of 16,7 is 86 ChapterS: Symbol Synchronization in Multipath Fast Fading Channels due to the ideal sampling instant falling halfway between samples in the simulation. 4) The tracking loops begin to fail for BFT < 0.1. the ML NDA scheme showing a faster degradation as the fading is increased than the ML DA scheme. If the fading process is approximated as having a rectangular PSD, for BFT = 0.1 the fading process is corre lated over approximately only 20 symbols (since the autocorrelation is a sin(x)/x func tion, and its main-lobe extends over 20 symbol periods). With the fading process changing this rapidly, the ML DA and NDA loops can no longer track the fading changes. 5) Performance in Ricean fading with Kf> 20 dB is not substantially worse than the results without fading, since the line-of-sight unfaded signal dominates (i.e., it is more than 100 times stronger than the faded signal). Because of this, the pattern dependent jitter term dominates jitter performance with no noise present. Performance degrades as Kf is reduced, until the signal is essentially Rayleigh faded. For Rayleigh fading, timing jitter increases about 60% over the no fading case. The BER performance measured through simulation is presented in Figure 29. As can be seen, the jitter performance in fading leads to no measurable degradation in BER performance over ideal sampling. It should he noted that the simulation results are for the case where noise is absent, and only reflects the irreducible BER. In the absence of noise, irreducible errors due to eye closure from fading are not made any worse due to sampling error. From the results of this section, it is apparent that while frequency non-selective fading causes a serious degradation of system BER performance, its effect on symbol timing jitter is not significant at high SNR for most normally encountered frequency non-selective fading conditions 87 ChapterS: Symbol Synchronization in Multipath Fast Fading Channels (i.e., Rayleigh or Ricean fading with BpT < 0.1). Although symbol timing acquisition time is not the focus of this thesis, it should be noted that acquisition time for the ML NDA and ML DA syn chronizers in the simulations performed were significantly affected by the introduction of fre quency non-selective fading, with specific observed cases exhibiting twice the acquisition time over the no-fading case. This may warrant use of the ?1L block synchronizer in such a situation, since the algorithm does not require acquisition time as it is normally defined for tracking loops. 0.1 0.01 V C) -e 0.001 0.0001 B Product Figure 29: Irreduciblelrreducible BER for fast flat fading channel, no noise. 88 Chapter 5: Symbol Synchronization in Multipath Fast Fading Channels 5.3.2 Fast Frequency Selective Fading Frequency selective fading creates a much more severe form of degradation than nonselective fading since it spreads the received energy over time. While random FM modulation of a signal by Rayleigh or Ricean fading maintains the cyclostationary characteristics of the signal, fre quency selective fading creates a spread signal which will cause much more uncertainty in the esti mation of the correct sampling instant. Due to time dispersion the ideal sampling instant is no longer necessarily at T12 in each symbol period for the matched-filtered signal. In frequency selective fading the ideal sampling instant is that which maximizes the SNR for each symbol [321. This corresponds to the time instant where received energy peaks in each symbol interval. For instance, for a two-ray model with each ray of equal power and td<T1 2 the ideal sampling instant will occur at td/ , which is the time-aver 2 age of the received power at each symbol. For low levels of fading such as a second ray with amplitude of 10 dB below the signal of the first ray, or for small td, the ideal sampling offset from the ideal non-fading sampling instant will be smaller. However in severe fading conditions , the 8 optimum sampling instant can vary significantly from the former ‘ideal’ instant. This is illustrated in Figure 30, where simulation results are shown for t/4—shift DQPSK modulation with a0.35 for the two-ray frequency selective fading channel, with Rayleigh faded rays (BFT=0.065). Two examples are shown, one with the delayed second ray of equal energy to the main ray, and one with a delayed ray with half the power of the main ray (-3 dB), both delayed from the main ray by time offset ta=T/2. Shown for each example is the optimal sampling instant, where the peak signal energy occurs. As can be seen, this offset can be substantially different from 8. For the 2-ray model, severe fading results when the second ray’s amplitude approaches or exceeds that of the primary ray, and the delay spread is a significant portion of a symbol period. 89 Chapter 5: Symbol Synchronization in Multipath Fast Fading Channels the ideal sampling instant for the no fading case. For example 25% of a symbol period in Figure 30, and can lead to degradation of performance (up to 65% worse irreducible BER performance by sampling at the T12 sampling instant for the equal power rays in Figure 30). 0.2 Irreducible BER Performance vs. Sampling Time Offset for Severe Freq. Selective Fading —a——-- Second Ray —a---— Second Ray = 0dB, T12 Offset, td T/2 -3dB, T12 Offset, ‘Ed = T/2 0.15 -c C) Peak Energy NI N! 0.1 Peak Energ] 0.05 0 0.1 ,I 0.2 — 0.3 0.4 0.5 Sampling Offset [%of 1] Figure 30: Irreducible BER vs. sampling time offset from T/2 sampling instants for 7t/4—shift DQPSK with 2—ray frequency selective Rayleigh fading model, with BFT=0.065. Computer simulations were used to evaluate the performance of the three synchronization schemes in frequency selective fading, using the 2—ray channel spread model, and with AWGN absent. The simulations used a sampling rate of f=64IT, and with the same nunther of symbols 90 ChapterS: Symbol Synchronization in Multipath Fast Fadil7g Channels simulated as for the flat fading case (see Section 5.3.1). Simulations withf=32IT were performed in order to evaluate the effects of sampling at the T/2 sampling instants, as well as at the optimal sampling instants, which were found for each td by the average of time offset, weighted by the rel ative powers of the two ray components. Figure 31 shows the irreducible BER performance of the 3 synchronization schemes for second ray powers of -10 dB and -3 dB, as a function of the second ray time delay, td. As well, simulations were performed with sampling at T12 in each symbol period, as well as with optimal sampling, found by the time-average of eneIy arrival, weighted by the power of the primary and secondary rays. Figure 32 illustrates the effect of a second ray of equal power to the primary ray. In [61], it was found that a ML NDA synchronizer performed as well as an ideal synchro nizer for rd<0.2T This is also observed here. In fact, performance of all three schemes is not sig nificantly degraded from ideal performance for td < 0.5T until the second ray is at the same power as the primary ray. In the case where the second ray is of the same amplitude as the first, the ML NDA technique begins to diverge significantly from ideal for td>O. T, with irreducible BER per 2 formance about twice as bad as the optimum sampling case at td=T12. Except for the most extreme case, with equal amplitude rays, performance of the ML DA and ML block synchronizers track the correct sampling instant well, while the ML NDA synchronizer does not adjust as well to the fre quency selective environment. 91 ChapterS: Symbol Synchronization in Multipath Fast Fading Channels 0.1 a) U a) 0.001 Ray Delay td Figure 31: Irreducible BER for 3 synchronizers in a frequency selective fast fading channel (-10 dB and -3 dB rays), including the BER for T12 sampling and for optimal sampling. Tracking of the optimal sampling instant is clearly shown in Figure 33, which plots the timing offset from the T12 sampling instant for 256 blocks of 64 symbols with the ML block syn chronizer. For the case of no interference, the synchronizer samples are close to zero offset (i.e. TI 2). When the primary ray is Rayleigh faded and added to a secondary ray with offset td=O. 43 and equal power, the average sampling instant is shifted towards the optimal sampling instant of t=T/ 2÷0.215T. However, as seen in Figure 32 the synchronizers’ performance begin to degrade for the case of equal-magnitude second ray at a timing offset of td=T/ . 2 92 ChapterS: Symbol Synchronization in Multipath Fast Fading Channels 0.1 V V 0.001 0 0.1 0.2 0.3 0.4 0.5 Ray Delay td Figure 32: Irreducible BER for 3 synchronizers in a frequency selective fast fading channel (-10 dB and 0 dB rays), including the BER for T12 sampling and for optimal sampling. From the simulation results, it can be seen that even for the worst case condition, with rd=T/2, and equal amplitude rays, that the ML NDA technique increases the BER error floor by about 100% over ideal sampling. The ML DA technique isicreases the BER error floor by about 60%, and the ML block technique by about 50% over ideal sampling. For a second ray with ampli tude 10 dB below the mam ray, the effect of any of the thie synchronization techniques is to raise the error floor by less than 20%. It must be noted, however, that where the symbol synchronization schemes are significantly worse that ideal sampling, the irreducible BER is already above 102. 93 Chapter 5: Symbol Synchronization in Multipath Fast Fading Channels Therefore, although a multipath environment can have a significant effect on the BER of a system due to non-ideal sampling at high SNR, system performance would already be marginal even with ideal timing. 0.5 0.375 0.25 Avg. Offset V 0.125 0 I V J0.125 Tracking Performance of ML B’ock Synchronizer -0.25 16 samples/symbol. 64 symbol block length — No Interference Is. Fang, = 0.43, 0dB -0.375 - 0 50 100 150 200 250 300 Block Number Figure 33: Tracking performance of ML block synchronizer for it /4—shift DQPSK modulation, without interference, and with frequency selective fading. In [32] and [33) a ML synchronizer was developed for a generalized frequency selective fading channel. This synchronization structure, realizable as either a block synchronizer or a track ing loop, is a maximum likelihood estimator of the maximum energy location. However, its imple mentation requires information about channel characteristics, namely a filter whose impulse 94 ChapterS: Symbol Synchronization in Multipath Fast Fading Channels response is the autocorrelation of the channel scattering function. Even provided that channel char acteristics can be estimated, the best performance it can achieve is to improve irreducible BER performance by up to 50% from the ML block synchronizer simulated at the worst conditions examined. Therefore for conditions where SNR is high, the added complexity of this scheme may not he warranted unless multipath fading is severe. 54 Summary This chapter has examined the performance of the ML NDA, DA, and block synchronizers for the it/4—shift DQPSK modulation scheme in both frequency nonselective and frequency selec tive fast fading channels through computer simulation. Both Rayleigh and Ricean frequency non-selective fast fading were examined, with tim ing jitter measurements and BER performance provided. It was found that although frequency nonselective fading increases the RMS timing jitter of the synchronizers, all three synchronizers simulated were able to match the irreducible BER performance of ideal sampling, over a wide 10 and above. Symbol tim range of fading with 0.003<BpT<0.2, for irreducible BER values of A ing jitter performance was remarkably unchanged over a range of BFT, although it began to degrade more seriously for BFT.0. 1. Therefore, for conditions of high SNR in Rayleigh or Ricean conditions with BFT<0. 1, use of the non-ideal symbol synchronizers examined will not have a sig nificant effect on the steady-state symbol timing jitter of a receiver. The effects of frequency selective fading were examined through computer simulation using a vaiiable-magnitude two-ray channel impulse response model. It was found that all three synchronizers operated well in most frequency selective fading environments simulated. As was found in [611, symbol timing jitter performance was near-ideal for 2 td<O. in all cases. However, T 95 ChapterS: Symbol Synchronization in Multipath Fast Fading Channels irreducible BER due to frequency selective fading was observed to increase as the amplitude of the second ray was increased, and as td increased. For the worst-case simulated, the irreducible BER was doubled for the ML NDA scheme, was 60% worse for the ML DA scheme, and was about 50% worse for the ML block synchronizer, compared with ideal sampling. However, by this point, the irreducible BER was greater than 102, even with ideal sampling, so system performance would be marginal at best at this point. Unless the fading is severe, it was observed that for high SNR, BER performance would not he seriously degraded using the three timing recovery schemes examined in Rayleigh fading or two-ray multipath fading environments, and more complex schemes created to improve symbol timing recovery performance in frequency-selective fading may not be warranted. 96 Chapter 6: Conclusions and Suggestions for Further Research 6 Conclusions and Suggestions for Further Research 6.1 Conclusions This thesis examined the effects on three ML symbol timing recovery techniques of two of the most serious forms of signal degradation in digital wireless systems -- CCI and signal fading. The thesis concerns itself with symbol timing jitter and BER performance as the measures of sys tem performance of three ML symbol synchronizers, NDA, DA, and block symbol synchronizers, for three quadrature modulation schemes, QPSK, it/4-shift DQPSK, and 16-QAM. For CCI, analysis was performed to determine expressions for steady-state symbol timing jitter for the ML NDA and ML DA cases, and a lower bounds for the ML block synchronizer, using linearized PLL analysis of the non-linear systems. Nyquist pulse shaping was assumed in an AWGN and CCI channel, and CCI was averaged over all possible timing offsets to give average RMS timing jitter expressions. A series of computer simulations were performed to test the analyt ical results. Comparison was made for various numbers of interferers for each type of modulation scheme, using symbol synchronizers with realistic parameters. C/I levels of up to 10 dB were sim ulated, with comparison made to analytical results derived. Analytical results for the ML NDA synchronizer have shown that CCI is the chief limit to performance at high SNR for systems with low pattern dependent jitter. CCI adds a constant term to the jitter variance, while the periodic components due to the cyclostationary nature of the CCI signals were eliminated by averaging over all possible timing offsets. The jitter performance for all three modulation schemes considered was similar and was found to be rather insensitive to the 97 Chapter 6: Conclusions and Suggestions for Further Research actual number of co-channel interferers. The ML NDA simulations verified the analytical results, with a number of small deviations from theory. For a large number of interferers, analysis underes timated the simulation results by less than 10% at high SNR, with CII up to 10 dB. However, a sin gle interferer exhibited worse performance, with errors of about 25% at high SNR and Cii = 10 dB, for QPSK modulation. For 16-QAM modulation, the analysis underestimated results with a larger error of about 35% at high SNR and Cli = 10 dB, with only one interferer. The performance degradation for the case where small numbers of co-channel interferers are present is due to non linearity in the PLL, which is not accounted for in the analysis and which is made worse at higher levels of CCL The ML DA and MIYIL DA analytical results also indicate that CCI is the chief limit to timing jitter performance at high SNR. As is the case for AWGN only, in a combined AWGN and CCI environment, the DA schemes outperform the NDA scheme, as was found in the cases evalu ated in [31]. Analysis of the MML DA yielded about 30% better RMS timing jitter performance at high SNR than the ML DA case, hut with reduced performance at low SNR. The jitter equations were found to be independent of the number of interferers present in the environment, or the quadrature modulation technique used. It depended only on the Cli ratio and the pulse-shaping used. Additionally, the jitter was found to he the same for all of the modulation schemes consid ered. The computer simulations verified that the theoretical timing jitter performance of the ML DA synchronizer was independent of the number of co-channel interferers present, with errors of 15% or less at CI! up to 10 dB at high SNR for QPSK and ic/4-DQPSK. In the case of 16-QAM modulation, the performance between theoretical and computer simulated results differed by about 30% with no CCI present at high SNR, due to amplitude variations in the signal constellation. 16QAM also exhibited twice the symbol timing jitter predicted at high SNR with an infinite number 98 Chapter 6: Conclusions and Suggestions for Further Research of interferers, due to the much larger BER of the 16-QAM modulation scheme for this case at CI! = 10dB. Analysis of the ML block synchronizer’s performance found that its lower-bound on per formance in noise is identical to the performance of the ML DA scheme, ignoring the patterndependent jitter of the latter case, as was seen in [10] for the AWGN channel only. The analytical result for symbol timing jitter is a lower bound which does not take into account the sampling rate of the synchronizer. The sampling rate will set a lower limit to performance due to the algorithm’s discrete-time nature, for sampling rates less than 16/T. It was found that for C/I lengths of K 10 dB and block 64, CCI was not a concern for the ML block synchronizer, since RMS timing jitter due to CCI was less than the time-quantization error for a reasonable sampling rate of 16’T. The ML block synchronizer computer simulations verified that at a sampling rate of 161T and block lengths of 32 symbols or more, the amount of additional symbol timing jitter due to CCI at levels of up to C/I=lOdB is not significant compared to the worst-case sampling error due to time-quanti zation of the sampling rate used in the algorithm. For all three synchronization techniques, the analytical results underestimated timing jitter for low SNR, where jitter is high. Similar behavior was reported in [22], for the AWGN channel. This discrepancy is due to the failure of the linear assumption used in analysis. For the ML NDA and DA analysis, the linear PLL model was used, while for the ML block synchronizer, a trunca tion of a Taylor’s series was used to linearize the analysis. The main constraint of the analysis in each case is that the symbol timing jitter remain small, so that error in the analysis remains small. Therefore, as jitter increases at low SNR, or for cases of low C/I, the jitter will increase more than predicted by the analysis. 99 Chapter 6: Conclusions and Suggestions for Further Research In both the ML NDA and ML DA cases, the only method for reducing CCI is by reducing the loop bandwidth of the synchronizer, although may be undesirable due to increasing synchro nizer acquisition time. In the case of the ML block synchronizer, increasing the length of each pro cessed block will decrease the effect of CCI at high SNR, provided the sampling rate is high enough that it is not the major source of error. However, increasing the block length will increase processing complexity. In all cases, with CCI levels up to C/1=lOdB, the effect of realistic symbol synchronization was negligible on the system BER performance. For the worst case simulated, with C/I=lOdB, at high SNR the symbol timing jitter remained less than 3.5% of a symbol period. Therefore for worst-case levels of CCI which might be encountered in a frequency reuse system, the effect of CCI on the ML synchronizers examined will not degrade the system BER compared to ideal sampling for the cases of QPSK, it/4-DQPSK, or 16-QAM. Nevertheless, the analytical results give important insight into the behaviour of the ML symbol synchronizers in a combined CCI environment, and allow prediction of design performance, given some limitations due to the small-jitter linear assumption. Finally, this thesis has presented computer simulation studies of the performance of the three previously mentioned symbol synchronization schemes in fading channels. Both frequency flat and frequency selective (2-ray) Rayleigh and Ricean fading channels were considered, in con junction with the it/4-shift DQPSK modulation scheme. Symbol timing jitter and irreducible BER performance were the measures of performance used. The obtained results have indicated that. although frequency nonselective fading increases the RMS timing jitter of the synchronizers, all three synchronizers simulated were able to match the irreducible BER performance of ideal sam , for irreducible BER values of 10 and above. pling over a wide range of fading 2 3<BFT<O. 0 (O.O ) 100 Chapter 6: Conclusions and Suggestions for Further Research Symbol timing jitter performance was remarkably unchanged over a range of BFT, although it began to degrade more seriously for BFT<0. 1. Therefore, for conditions of high SNR in Rayleigh or Ricean conditions, use of a well designed Ml. symbol synchronizer as examined here will not have a significant effect on the steady-state (phase locked) symbol timing jitter of a receiver. Also, it was found that all three synchronizers operated well in most frequency selective fading environ <zO.2T in 1 ments simulated. Similar to [61], symbol timing jitter performance was near-ideal for t all cases. However, irreducible BER due to frequency selective fading was observed to increase as the amplitude of the second ray was increased, and as td increased. For the worst-case simulated, the irreducible BER was doubled for the ML NDA scheme, was about 60% worse for the ML DA scheme, and was about 50% worse for the ML block synchronizer, compared with ideal sampling. However, in this case the in-educible BER was greater than 10-2, even with ideal sampling. There fore, system performance would be marginal at best in this instance. Because of this result, more complex schemes, such as proposed m [331, may not warrant the added complexity in symbol tim ing recovery algorithm, unless frequency selective fading is severe. 6.2 Suggestions for Further Research 6.2.1 Effects of CCI and multipath fading on tracking loop acquisition time and cycle slipping This thesis has examined the steady-state performance of the three symbol timing recov ery techniques. In order to use the ML NDA or ML DA symbol synchmnizers examined in a TDMA system, it is necessary to ensure that timing acquisition will always be possible within each timeslot. To ensure this, the acquisition time problem should be studied in greater depth [7]. As well, cycle slipping was observed in simulations of frequency selective fading at high fading rates. 101 Chapter 6: Conclusions and Suggestions for Further Research This phenomenon should also he examined in greater detail. 6.2.2 Performance of fast acquisition digital tracking loops in fading and CCI The tracking loops examined have some limited application in a TDMA network due to their strict requirements on clock frequency and carrier phase acquisition. This may be overcome by the use of digital phase-lock loops designed for fast frequency and phase acquisition (see for example [60]). It would he interesting to extend the work of this thesis to study these schemes for symbol synchronization in TDMA systems in CCI and fading channels. 6.2.3 Effects of slow fading on system performance Due to limitations of the computer simulations, this thesis only reports on the case of fast fading. Therefore, individual signal fades are of relatively short duration. It is believed that the ML NDA and DA symbol tracking loop performance may serious degrade if the length of deep fades is significant compared to lI(2BLT). It appears interesting, therefore, to investigate this problem fur ther. 102 Bibliography Bibliography [1] T. S. Rappaport, “The Wireless Revolution”, iEEE Comm. Magazine, pp. 52, 61-71, Nov. 1991. [2] D. J. Goodman, “Trends in Cellular and Cordless Communications,. IEEE Comm. Maga zine, pp. 31-40, June 1991. [3] W. C.-Y. Lee, Mobile Cellular Telecommunication Systems. New York, N.Y. McGrawHill, 1989. [41 Cellular Digital Packer Data System Specification, Release 1.0. Vol. I V, Ameritech Mobile Communications, Bell Atlantic Mobile Systems, et. al. July 19, 1993. [51 A. D. Kucar, “Mobile Radio: An Overview”, iEEE Comm. Magazine, pp. 72-85, Nov. 1991. [6] K. Raith and J. Uddenfeldt, “Capacity of Digital Cellular TDMA Systems”, IEEE Trans. Veh. Techn., vol. VT-40, pp. 323-331 May 1991. [7] H. Meyr and G. Ascheid, Synchronization in Digital Communications: Vol 1 Phase-, Fre quency-Locked Loops, and Amplitude Control. New York. N.Y., John Wiley and Sons, 1990. [81 W. C. Lindsey. Synchronization Systems in Communication and Control. Englewood Cliffs, N. J., Prentice Hall, 1972. [9] W. C. Lindsey and M. K. Simon, Phase-Locked Loops and Their Application. N. J., IEEE Press, 1978. [101 L. E. Franks, “Synchronization Subsystems: Analysis and Design”, in Digital Communi cations: Satellite/Earth Station Engineering. (K. Feher, ed.), ch 7, pp. 294-327, New York, N.Y., Prentice Hall, 1983. [11] L. E. Franks, “Carrier and Bit Synchronization in Data Communication Review”, IEEE Trans. Commun., vol. COM-28, pp. 1107-112 1, Aug., 1980. [12] M. Moeneclaey, “Linear Phase-Locked Loop Theory for Cyclostationary Input Distur bances”, IEEE Trans. Commun., vol. COM-30, pp. 2253-2259, Oct. 1982. - 103 -- A Tutorial Bibliography [13] J. 0. Proakis, Digital Communications. New York, N.Y., McGraw-Hill Book Co., 1989. [14] W. C. Jakes Jr., Microwave Mobile Communications. New York, N.Y., John Wiley and Sons, 1974. [15] R. J. Bultitude, “A Comparison of Indoor Radio Propagation Characteristics at 910 MHz and 1.75 GHz”, J. Sd. Areas Commun., vol. JSAC-7, pp. 20-30, Jan. 1989. [161 T. S. Rappaport, “900-MHz Multipath Propagation Measurements for U.S. Digital Cellu lar Radiotelephone”, IEEE Trans. Veh. Techn., vol. VT-39, pp. 132-139, May 1990. [171 D. C. Cox and R. P. Leck, “Distributions of Multipath Delay Spread and Average Excess Delay for 910 MHz Urban Mobile Radio Paths”, IEEE Trans. Ant. Prop., vol. AP-23, pp. 206-213, March 1975. [18] D. D. Falconer, “Timing Jitter Effects on Digital Subscriber Loop Echo Cancellers: Part I Analysis of the Effect”, IEEE Trans. Commun., vol. COM-33, pp. 826-832, Aug. 1985. [191 D. D. Falconer, “Timing Jitter Effects on Digital Subscriber Loop Echo Cancellers: Part II Considerations for Squaring Loop Timing Recovery”, IEEE Trans. Commun., vol. COM-33, pp. 8 33-838, Aug. 1985. - - [20] M. Moeneclaey, “The Influence of Four T’pes of Symbol Synchronizers on the Error Probability of a PAM Receiver”, IEEE Trans. Commun., vol. COM-32, pp. 1186-1190, Oct. 1984. [211 D. Y. Kim and K. Feher, “New Carrier and Symbol Synchronization Techniques for Digi tal Mobile Systems”, Proc. of IEEE Veh, Techn. Conf, pp. 37 1-376, 1988. [22] M. Moeneclaey, “Two Maximum-Likelihood Symbol Synchronizers with Superior Track ing Performance”, IEEE Trans. Commun., vol. COM-32, pp. 1178-1185, Oct. 1984. [23] M. Moeneclaey, “A Comparison of Two Types of Symbol Synchronizers for Which SelfNoise is Absent”, IEEE Trans. Commun., vol. COM-31, pp. 329-334, Mac 1983. [24] M. Oerder and H. Meyr, “VLSI Implementation of Synchronization Algorithms in a 100 Mbitlsec Digital Receiver”, Proc. of IEEE Global Telecommunications Conf, pp. 571576, 1990. [25] N. R. Sollenberger and J. C. I. Chuang, “Low-Overhead Symbol ‘Timing and Canier Recovery for TDMA Portable Radio Systems”, IEEE Trans. Commun., vol. COM-38, pp. 1886-1892, Oct. 1990. 104 Bibliography [261 J. C.-1. Chuang and N. R. Sollenberger, “Burst Coherent Demodulation with Combined Symbol Timing, Frequency Offset Estimation, and Diversity Selection”, IEEE Trans. Commun., vol. COM-39, pp. 1157-1164, July 1991. [27] F. M. Gardner, ESA Report 6847/86INJJDG: Demodulator Reference Recoveiy Tech niques Suited for Digital Implementation.. European Space Agency, 1988. [28] F. M. Gardner, ESA Report 802218811”IL/DG: Timing Adjustment via Interpolation in Dig ital Demodulators. European Space Agency, 1990. [29] J. Armstrong, “Symbol Synchronization Using Baud-Rate Sampling and Data-SequenceDependent Signal Processing”, IEEE Trans. Com,nun., vol. COM-39, pp. 127-132, Jan. 1991. [30] E. Fogel and M. Gavish, “Performance Evaluation of Zero-Crossing-Based Bit Synchro nizers”, IEEE Trans. Commun., vol. COM-37. pp. 663-665, June 1989. [31] J. B. Carruthers, D. D. Falconer, H. M. Sandier and L. Strawczynski, “Bit Synchronization in the Presence of Co-Channel Interference”, Proc. Canadian Conf on Electrical and Computer Engineering, pp. 4.1.1-4.1.7, Sept. 1991. [32] S. 5. Soliman and R. A. Scholtz, “Synchronization Over Fading Dispersive Channels”, IEEE Trans. Commun., vol. COM-36, pp. 499-505, Apr. 1988. [33] S. S. Soliman, “Tracking Loop for Fading Dispersive Channels”, IEEE Trans. Commun., vol. COM-38, pp. 292-299, Mar. 1990. [34] F. M. Gardner, Phase-Lock Techniques. New York, N.Y., John Wiley and Sons, 1979. [35] M. Moeneclaey, “The Influence of Phase-Dependent Loop Noise on the Cycle Slipping of Symbol Synchronizers”, IEEE Trans. Commun., vol. COM-33, pp. 1234-1239, Dec. 1985. [36] M. Moeneclaey, “The Influence of Cycle Slipping on the Error Probability of a PAM Receiver”, IEEE Trans. Commun. ,vol. COM-35, pp. 96 1-968, Sept. 1987. [37] L. B. Franks and J. P. Bubrouski, “Statistical Properties of Timing Jitter in a PAM Timing Recovery Scheme”, IEEE Trans. Commun., vol. COM-22, pp. 913-920, July 1974. [381 W. A. Gardner and L. B. Franks, “Characterization of Cyclostationary Random Signal Processes”, iEEE Trans. Info. Theoiy, vol. IT-2 1, pp. 4-14, Jan. 1975. [39] A. N. D’Andrea, U. Mengali and R. Reggiannini, “Carrier Phase and Clock Recovery for 105 Bibliography Continuous Phase Modulated Signals”, IEEE Trans. Commun., vol. COM-35, pp. 10951101, Oct. 1987. [40] F. Patenaude, J. H. Lodge and P. A. Galko, “Symbol Timing Tracking for Continuous Phase Modulation over Fast Flat-Fading Channels”, IEEE Trans. Veh. Techn., vol. VT-40, pp. 6 15-626, Aug. 1991. [41] P. G. Ogmundson and P F. Driessen, “Zero-Crossing DPLL Bit Synchronizer with Pattern Jitter Correction”, IEEE Trans. Commun., vol. COM-39, pp. 603-6 11, Apr. 1991. [42] F. M. Gardner, “Self-Noise in Synchronizers”, IEEE Trans. Commun., vol. COM-28, pp. 1159-1163, Aug. 1980. [431 M. H. Meyers and L. E. Franks, “Joint Carrier Phase and Symbol Timing Recovery for PAM Systems”, IEEE Trans. Commun., vol. COM-28, pp. 1121-1129, Aug. 1980. [44] M. Moeneclaey, “Comment on ‘Tracking Performance of the Filter and Square Bit Syn chronizer’ IEEE Trans. Commun., vol. COM-30, pp. 407-410, Feb. 1982. “, [451 J. K. Holmes, “Tracking Performance of the Filter and Square Bit Synchronize?’, IEEE Trans. Commun., vol. COM-28, pp. 1154-1158, Aug. 1980. [46] M. Moeneclaey, “A Class of Phase Detector Characteristics for Symbol Syncrhonizers Yielding Unbiased Estimates”, IEEE Trans. Commun., vol. COM-31, pp. 1033-1036, Sept. 1983. [47] Y. Takasaki, “Optimum Pulse Shaping for Baseband Digital Transmission with Self-Bit Synchronization”, IEEE Trans. Commun., vol. COM-28. pp. 1164-1172, Aug. 1980. [48] M. Moeneclaey, “The Optimum Closed-Loop Transfer Function of a Phase-Locked Loop Used for Synchronization Purposes”, IEEE Trans. Commun., vol. COM-31, pp. 549-553, Apr. 1983. [49) S. Haykin, Digital Communications. New York, N. Y., John Wiley and Sons, 1988. [50] J. Goldman, “Multiple Error Performance of PSK Systems with Cochannel Interference and Noise”, IEEE Trans. Com,nun. Techn., vol. COM-19, pp. 420-430, Aug. 1971. [51] R. A. Coco, “Symbol Error Rate Curves for M-QAM Signals with Multiple Co-Channel Interferers”, IEEE Trans. Commun., vol. COM-36, pp. 980-983, Aug. 1988. [52] M. Moeneclaey, “Timing Recovery in the Presence of a Residual Echo Signal”, IEEE 106 Bibliography Trans. Commun., vol. COM-35, pp. 830-833, Aug. 1987. [53] D. G. Messerschmitt, “A Tool for Structured Functional Simulation”, IEEE J. Se!. Areas Commun., vol. SAC-2, pp. 137-147, Jan. 1984. [54] M. C. Jeruchim, “Techniques for Estimating the Bit Error Rate in the Simulation of Digital Communication Systems”, IEEE J. Sel. Areas Commun., vol. SAC-2, 153-170, Jan. 1984. [55] A. V. Oppenheim and R. Schafer, Discrete Time Signal Processing. Prentice Hall, Engel wood Hills, N. 3., 1989. [56] D. P. Bouras, Optimal Decoding of PSK and QAM Signals in Frequency Nonselective Fading Channels, M.A.Sc. Thesis, The University of British Columbia, Sept. 1991. [57] “Dual-mode Subscriber Equipment Compatability Specification”, in EJAITIA Specifica tion IS-54, EIAfTIA Project Number 2215, Jan. 1990. [58] G. D’Avia, “Fast Adaptive Equalizers for Narrow-Band TDMA Mobile Radio”, IEEE Trans. Veh. Techn., vol. VT-40, pp. 392-404, May 1991. [59] K. Nemoto, T. Yamazato, 1. Sasase and S. Mon. “A Novel Detection Technique for CPM Using Variable Mapping Method”, Proc. IEEE Pacific Rim Conf on Communications, Computers and Signal Processing, vol. 2, pp. 573-576, May 1993. [60] F. Sato, T. Saba, D. K. Park and S. Moni, “Digital Phase-Locked Loop with Wide Lock-in Range using Fractional Divider”, Proc. IEEE Pacific Rim Conf on Communications, Computers and Signal Processing, vol. 2, pp. 43 1-434, May 1993. [611 J. C.-I. Chuang, “The Effects of Multipath Delay Spread on Timing Recovery”, IEEE Trans. Veh. Techn., vol. VT-35, pp. 135-140, Aug. 1987. [62] V. Prahhu, “Error Rate Consideration for Coherent Phase-Shift Systems With Co-Channel Interference”, Bell Systems Technical Journal, vol. 48, pp. 743-767, May 1969. [63] D. P.-C. Wong and P. T. Mathiopoulos, “Nonmdundant Error Correction Analysis and Evaluation of Differentially Detected it/4-Shift DQPSK Systems in a Combined CCI and AWGN Environment”, IEEE Trans. Veh. Techn., vol. VT-41, pp. 35-48, Feb. 1992. [64] L. 3. Mason, “Error Probability Evaluation for Systems Employing Differential Detection in a Ricean Fast Fading Environment and Gaussian Noise”, IEEE Trans. Comm., vol. COM-35, pp. 39-46, Jan. 1987. 107 Bibliography [65] D. Makrakis, P. T. Mathiopoulos, and D. P Bouras, “Optimal Decoding of Coded PSK and QAM signals in Correlated Fast Fading Channels and AWGN: A Combined Envelope, Multiple Differential, and Coherent Detection Approach”. IEEE Trans. Comm., vol COM 42, pp. 6375, Jan. 1994. [66] H. Hishemi, “The Indoor Radio Propagation Channel”, IEEE Proceedings, vol. 81, pp. 943-968, July 1993. 108 Appendix A.• Derivation of ML NDA Synchronizer Timing finer in CCI Appendix A: Derivation of ML NDA Synchronizer Timing Jitter in CCI The effects of CCI on the NDA symbol synchronizer can be found by following the method outlined in Section 2.4. 1. The method briefly, is to find an expression of v(t), the input to the loop filter of the PLL, after matched-filtering, prefiltering and squaring the received waveform (see Figure 4). This is equivalent to the cyclostationary input noise term M(t) discussed in Section 2.4.1. The two-dimensional autocorrelation function of this the cyclostationary noise term M(t) can then he found, and expressed in terms of a Fourier series representation, such that: RM (u, u + 2ir ku) 7 Yk (v) exp (j (EQ. A.1) 2it R (u, u + v) exp (_JTku) du. (EQ. A.2) v) = where: 1 T /2 Yk (v) = f —T/2 The resultant power spectral density of the input waveform which contributes to the phase-jitter at the output of the PLL may be expressed as: s (t) = 0 (1÷ [s + 0 S (f- - 2 S (f+ exp (-2j0) - S (f- exp (210)] (EQ. A.3) where Sk(f)=FTV{yk(v)} and FT{.} represents the Fourier transform of the argument with respect to the time-variable v. The output timing jitter variance can then be expressed as: = (2B) St (0) (EQ. A.4) where P is the power of the mean signal component. Including AWGN and CCI with the transmitted signal, the result of this process yields two terms, S (J) due to the signal and AWGN and 2 1 S, ( f) due to the addition of CCI. The terms are 109 Appendix A: Derivation of ML NDA Synchronizer Timing Jitter in CI found to be: S, 14 ) 2) Z f) 3[(a (a )Z _ f) +a_ + J 2 ( ( 0 J) =—(a (1 T +2[(a2)2+ ) Zm(fZm( 7 (G 1 2 ) 2 + a) (a + 4 +—(a 2 Ta 0 N +2(7) +0 2) 0 () () RG (0) Z ( +6 + - () R (0)5 A.5) 00 (N°) f G(s)J(s)SG(fs)ds5[n} 00 f SG(s)SG(f—s)dsS[nj and: 1 +0 4_3[(a2)2÷ (02)21) a b Ta 2 ] 2 (a) + _[(a2)2+ a T M )z exp _.n] u 0 z c Tn) (i21t(W / 1 1=1 MM jz i1l=1m exp (j2ltnW (— ) 1 /fl 1 m—(—-——) 1=1 +(a2+a) (EQ.A.6) () JG(s)G(-s)S(;f-s)dsexpU2(,/fln) 1=1 + 1 — MM n-mV (oa+ T m r 1 j21cW + T m 4 + (a2o÷aa) p (j2irn) (W W m/T)ex (j2it — 1 ) i=11=1 M 1 exp M Zm_W/T(J)Zm_V/T(_f) m 110 m)+exp( j2lcNJ, T (n_rn))] Appendix A: Derivation of ML NDA Synchronizer Timing Jitter in CCI where 6(t) is the Dirac delta function and: Zm(f) = FT{g(t)g(t—mT)} = fG(s)G(f_s)exp(_j2icmrf)cis (EQ.A.7) and RG(U) is the autocorrelation function of the pulse-shape g(l)=h(t)*p(1), and SG(f)=/I-f(f)//P(f)/ 2 is the power spectral density due to the equivalent filter hR(t)*p(t), which it the normalized power spectral density of the input AWGN after filtering. Here the transmit and receive filter are assumed to be ,.J& raised cosine Nyquist filters. Notice that each of the M interferers add terms to S, (J) which are identical to those 2 caused by the signal in S (f), with the exception of a phase offset due to the interferer’s timing 1 offset from the main signal. In addition, the last three terms of S (f) are due to the cyclostationary 2 process caused by (signal x inteiference) terms. Now, the expression for the jitter power in the bandwidth of the PLL can be written from, where 2 .t). The average over all CCI timing offsets, such that -1I(2T)< y <1/(2T). (t)+S, 1 S(f)=S, ( This results in: 111 Appendix A: Derivation of ML NDA Synchronizer Timing Jitter in CCI (EQ. A.8) S(O) (a+a 1 = + 2 3[(a2) (a2)21)z ( [1 -cos(ØA)j 26 112 2 —29)1 8 [1—cos(Ø m +2()S SG(S)SQ(S)dS 4 ÷ 2 +-(a + M[a+aj) a Tab () I IG(s)l2SG(_s)ds +M(a4+a43[(a2)2+ (G2)21)z(l) + + where 2 2 (M [2 ) 21 + 2 + a + 2 (M2[(a) = 2M (aa + ) JIG (s) I 2G ( (O) 0 Z a+aa)) 2 2 1 +2M(a 2 (a) (1/T) and ZZm (1/T) m 112 - s) ds Appendix B: Simulation Error in Timing Jitter Measurements Appendix B: Simulation Error in Timing Jitter Measurements Discrete-time simulations limit the time-resolution for timing jitter estimation. The num ber of samples per symbol chosen for the simulation determines the lower bound on accurate tim ing jitter variance estimation. This is due to the zero-crossing of the timing wave being rounded to the next discrete time value, which results in time quantization of the timing wave. Since the simu lations are limited by computer memory size, the number of samples per symbol was also limited for ML DA and ML NDA simulations. The number of samples per symbol was chosen to be 128, which causes a limit to the measurable RMS timing jitter at 1/(2x 128) = O.0039T. For jitter values which are close to this limit, time quantization may have an impact on the jitter measured by simu lation. The error in simulated jitter measurement due to time quantization is discussed here. In order to estimate the effect on measurements of low jitter, a Gaussian distribution of the timing-offset t is considered, with zero mean about the correct sampling instant, standard devia tion a, and probability density function of f(t). The distribution can be divided into regions (xv, n = {O, ±1, ±2, ...} ) of size corresponding to the sampling period, d. 1(t) Figure B.1: Probability density junction 1(r), of timing jitter, with sampling instants marked. 113 Appendix B. Simulation Error in Timing Jitter Measurements As shown in Figure B. 1, there is a finite probability that a sampling instant will fall within each interval x,. Due to limitations of the computer simulation, any sampling instant which occurs anywhere in the range x, will he rounded upwards to the next interval boundary, which is the sim ulated sampling instant. The probability that t falls within x, for a particular symbol period can be found by inte grating the area off(t) over the area x: P(tex) ((2n—l)d\ 11 —Ierfcl 2 2oJi I—erfcl } 2aJ I) }) (EQ.B.1) where erfc(.) is the well known complimentary error function [49]. The variance estimate, s , for 2 each sampling instant, as measured by the computer simulation is the difference between the mea sured sampling instant ( {±d/2, ±3d/2, ... }), and the ideal sampling instant, which is zero for the zero-mean processf(t). Therefore, for each sample, the timing jitter variance measured by the sim ulation for tE x, can be written as: 2 = [ (2n+l)d1 2 2 j (EQ.B.2) with the value d dependent upon the number of samples per symbol, expressed as: 3 T d= (EQ.B.3) with T 5 the sampling period for the simulation. d is simply the distance between sampling inter vals. The total estimated variance, 2 can then be expressed as the probability of t lying within each interval x, (Eq. B. 1) multiplied by the variance estimate for that interval (Eq. B.2, summed over all the possible regions (x, n — = {O, ±1, ±2, ...} ). The expression is: 2 [erfc27j2_erfc2tj2d)][(2t1] 114 (EQ B4) Appendix B: Simulation Error in Timing Jitter Measurements 2 need only be evaluated over a finite range of n. Since the tails off(t) rapidly approach zero, s The error in jitter measurement due to time quantization of the simulation is simply the 2, compared to the actual jitter difference between the jitter variance measured in the simulation, , evaluate d and 2 variance, a . To evaluate the error, chose a jitter variance a 2 52, and subtract the result from a . 2 The expression was evaluated numerically with -50 < n <50, for which was found to be a sufficiently large range of n to evaluate the expression. The result can be summarized for the 128 samples/symbol used in the ML NDA and DA simulations. Table B.1: Simulation error in estimating normalized RMS Timing Jitter, 128 samples per symbol. a /T a/T (RMS Jitter) Estimation Error (RM Jitter) Estimation Error 0.007 10.5% 0.010 5.2% 0.008 8.4% 0.015 3.8% 0.009 6.9% 0.020 2.3% Thus, RMS jitter values below O.02T will he slightly overestimated in the simulation results. 115
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Analysis and evaluation of three symbol timing recovery techniques for digital wireless personal communication… Williams, Christopher A. 1994
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Title | Analysis and evaluation of three symbol timing recovery techniques for digital wireless personal communication systems |
Creator |
Williams, Christopher A. |
Date Issued | 1994 |
Description | This thesis investigates the performance in the presence of CCI and multipath fading of three symbol timing recovery schemes, maximum likelihood (ML) non-data aided (NDA) and data-aided (DA) tracking loops, and a ML block symbol synchronizer, for QPSK, π/4—shift DQPSK, and 16—QAM modulation schemes. In the first part of the thesis, analysis of the three symbol synchronizers in a combined AWGN and CCI environment is performed, based on a linear assumption for small jitter, and expressions for RMS symbol timing jitter are presented for each technique, assuming Nyquist pulse shaping. Computer simulations are also performed in order to validate the results and provide bit-error rate (BER) performance of each synchronizer. CCI was found to be the chief limit on symbol timing jitter performance at high signal-to-noise ratios (SNR) for all three synchronizers. Simulations matched theory in most cases, except where the linear assumption is no longer valid. Simulation showed that for carrier-to-interference (C/I) ratios of ≥ 10 dB, CCI effects on symbol timing recovery result in negligible BER degradation over ideal sampling. The second part of the thesis investigates the three symbol synchronizers in a fading environment. Irreducable BER and RMS timing jitter estimates were made by computer simulation using π/4—shift DQPSK modulation in frequency non-selective Rayleigh and Ricean fading, as well as in frequency selective fading. Rayleigh fading had little effect on symbol timing jitter at high SNR unless the fading was extremely fast, that is where the fading bandwidth (B[sub F]) times the information symbol duration (T) product is relatively high (i.e. Β[sub F]Τ>0.1), and had no noticeable effect on irreducable BER for the range simulated. In frequency selective fading with a two-ray model, the synchronizers were observed to track the optimum sampling instant well at high SNR, for delay spreads of the two-ray model used of τ[sub d] < 0.2T. For more severe fading (i.e. τ[sub d]> 0.2T), the ML block synchronizer performed best, tracking the optimum sampling instant with no increase in the irreducable BER until τ[sub d] = T/2. The ML NDA technique was found to be the worst performer for frequency selective multipath fading, with double the irreducable BER in the worst case simulated. |
Extent | 3179326 bytes |
Genre |
Thesis/Dissertation |
Type |
Text |
File Format | application/pdf |
Language | eng |
Date Available | 2009-03-06 |
Provider | Vancouver : University of British Columbia Library |
Rights | For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use. |
DOI | 10.14288/1.0065193 |
URI | http://hdl.handle.net/2429/5609 |
Degree |
Master of Applied Science - MASc |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
Graduation Date | 1994-11 |
Campus |
UBCV |
Scholarly Level | Graduate |
Aggregated Source Repository | DSpace |
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