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Analysis and evaluation of three symbol timing recovery techniques for digital wireless personal communication… Williams, Christopher A. 1994

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ANALYSIS AND EVALUATION OF THREE SYMBOLTIMING RECOVERY TECHNIQUES FOR DIGITALWIRELESS PERSONAL COMMUNICATION SYSTEMSbyCHRISTOPHER A. WILLIAMSB. A. Sc. (Hons.), The University of Waterloo, 1991A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFMASTER OF APPLIED SCIENCEinTHE FACULTY OF GRADUATE STUDIESDepartment of Electrical EngineeringWe accept this thesis as conformingto the. equired standardThE UNIVERSITY OF BRITISH COLUMBIAJuly 1994© Christopher A. Williams, 1994Signature(s) removed to protect privacyIn presenting this thesis in partial fulfilment of the requirements for an advanceddegree at the University of British Columbia, I agree that the Library shall make itfreely available for reference and study. I further agree that permission for extensivecopying of this thesis for scholarly purposes may be granted by the head of mydepartment or by his or her representatives. It is understood that copying orpublication of this thesis for financial gain shall not be allowed without my writtenpermission.(Signature)___________________________Electrical EngineeringDepartment of_________________The University of British ColumbiaVancouver, CanadaJuly 22, 1994Date_____________ ____ ___DE-6 (2)88)Signature(s) removed to protect privacySignature(s) removed to protect privacyAbstractAbstractThis thesis investigates the performance in the presence of CCI and multipath fading ofthree symbol timing recovery schemes, maximum likelihood (ML) non-data aided (NDA) anddata-aided (DA) tracking loops, and a ML block symbol synchronizer, for QPSK, it/4—shiftDQPSK, and 16—QAM modulation schemes.In the first part of the thesis, analysis of the three symbol synchronizers in a combinedAWGN and CCI environment is performed, based on a linear assumption for small jitter, andexpressions for RMS symbol timing jitter are presented for each technique, assuming Nyquistpulse shaping. Computer simulations are also performed in order to validate the results and provide bit-error rate (BER) performance of each synchronizer. CCI was found to be the chief limit onsymbol timing jitter performance at high signal-to-noise ratios (SNR) for all three synchronizers.Simulations matched theory in most cases, except where the linear assumption is no longer valid.Simulation showed that for carrier-to-interference (C/I) ratios of 10 dB, CCI effects on symboltiming recovery result in negligible BER degradation over ideal sampling.The second part of the thesis investigates the three symbol synchronizers in a fading environment. Irreducahie BER and RMS timing jitter estimates were made by computer simulationusing it/4—shift DQPSK modulation in frequency non-selective Rayleigh and Ricean fading, aswell as in frequency selective fading. Rayleigh fading had little effect on symbol timing jitter athigh SNR unless the fading was extremely fast, that is where the fading bandwidth (BF) times theinformation symbol duration (T) product is relatively high (i.e. BT>O. 1), and had no noticeableeffect on irreducable BER for the range simulated. In frequency selective fading with a two-raymodel, the synchronizers were observed to track the optimum sampling instant well at high SNR,LiAbsracifor delay spreads of the two-ray model used of td < 0.21 For more severe fading (i.e. td> 0.27),the Ml. block synchronizer performed best, tracking the optimum sampling instant with noincrease in the irreducahie BER until td = T/2. The Ml. NDA technique was found to be the worstperformer for frequency selective multipath fading, with double the irreducable BER in the worstcase simulated.U’Table of ContentsAbstract .1Table of Contents ivList of Tables viiiList of Figures &Acknowledgments xiii1 introduction 11 .1 Modulation Schemes 21.2 Wireless Personal Telecommunication Channels 31.2.1 Co-Channel Interference (CCI) 31.2.2 Multipath Fading 41.3 Symbol Timing Recovery Techniques 71.3.1 Measures of Symbol Timing Recovery Performance 81.3.2 Symbol Timing Estimation Techniques 81 .3.3 Timing Recovery in Wireless Communication Channels 91.4 Thesis Research Objectives 101 .5 Organization of Thesis 112 Symbol Synchronization Principles 142.1 Introduction 142.2 The Symbol Timing Recovery Process 152.2.1 Cyclostationary Processes in Timing Recovery 152.2.2 Symbol Timing Jitter in Symbol Synchronization 16iv2.2.3 Effects of Symbol Timing Jitter on Receiver BER Performance 172.3 Maximum Likelihood Estimation 182.3.1 ML Non-Data Aided Estimation 192.3.2 ML Data Aided Estimation 202.3.3 ML Block Estimation 212.4 Analysis of Symbol Synchronization Techniques 232.4.1 Phase-Lock Loop Theory for the NDA Implementation 232.4.2 Phase-Lock Loop Theory for the DA Implementation 272.4.3 Symbol Block Synchronizers 292.5 Summary 313 Symbol Synchronization Analysis in CCI Channels 323.1 Introduction 323.2 System Model 333.2.1 Transmitter Model 333.2.2 Receiver Structure 343.2.3 Co-Channel Interference Model 353.3 Analysis of the ML Non-Data Aided (NDA) Synchronizer 373.4 Analysis of Data Aided Synchronizers 433.4.1 Maximum Likelihood Data Aided Synchronizer 433.4.2 Modified Maximum Likelihood DA Synchronizer Analysis 453.4.3 Results of ML and MML DA Jitter Performance Analysis 473.5 Analysis of the ML Block Synchronizer 493.6 Summary 524 Computer Simulation of Symbol Synchronization in CCI 54V4.1 Introduction .544.2 Computer Simulation System Description 544.2.1 Description of the ML NDA and DA Tracking Loop Simulations 564.2.2 Description of the ML Block Simulations 594.3 ML NDA Synchronizer Simulation Results 594.4 ML DA Simulation Results 664.5 ML Block Synchronizer Simulation Results 724.6 Summary 755 Symbol Synchronization in Multipath Fast Fading Channels 785.1 Introduction 785.2 Fading Models 805.2.1 Frequency Non-Selective (Flat) Fading Model Description.... 805.2.2 Frequency Selective Fading Model Description 825.3 Simulation Results and Discussion 835.3.1 Fast Frequency Non-Selective Fading 835.3.2 Fast Frequency Selective Fading 895.4 Summary 956 Conclusions and Suggestions for Further Research 976.1 Conclusions 976.2 Suggestions for Further Research 1016.2.1 Effects of CCI and multipath fading on tracking loop acquisition timeand cycle slipping 1016.2.2 Performance of fast acquisition digital tracking loops in fading andCCI 102vicE6.2.3 Effects of slow fading on system performance. 102Bibliography 103Appendix A: Derivation of ML NDA Synchronizer Timing Jitter in CCI.. 109Appendix B: Simulation Error in Timing Jitter Measurements 113vuList of TablesTable 1: Effect of symbol synchronization error on BER performancecompared to SNR for ideal timing, for coherently demodulatedBPSK (from [10]) 17Table 2: Effect of sampling rate on minimum possible jitter at high SNR(no noise 51Table 3: Simulation Error vs. excess bandwidth c, ML NDAsynchronization with QPSK modulation, C/I= 10 dB,2BLT=0.0065, and no noise 65Table 4: Simulation Error vs. excess bandwidth, ML DAsynchronization, for QPSK modulation, C/I= 10 dB,,2BLT=0.008, and no noise 71Table B.1: Simulation error in estimating normalized RMS Timing Jitter,128 samples per symbol 115VII’List of FiguresFigure 1: Signal constellations for modulation schemes under consideration. (a)QPSK, (b) it/4—shift DQPSK, (c) 1 6—QAM 2Figure 2: lS-54 TDMA half-rate frame structure (from [6]) 3Figure 3: A typical channel power delay spread profile for an urban environment . 6Figure 4: ML non-data aided symbol timing tracking loop [31] 19Figure 5: Data-aided symbol timing tracking loop. (DD) is decision device, (SPC)is parallel-to-serial converter for output data sequence, (NCC) isnumber controlled counter [31] 21Figure 6: Block diagram of ML block synchronization scheme 22Figure 7: Comparison of signal constellation for ML block synchronization using(a) symbol constellation, and (b) differential symbol constellation,for iv /4—shift DQPSK signalling 23Figure 8: A general symbol synchronizer as a PLL. F(f) is a loop filter, and VCCis a Voltage Controlled Clock 24Figure 9: Illustration of timing wave variance for (a) wide-sense stationary and (b)wide-sense CS inputs to the filter-square-filter ML NDAsynchronizer. 0 represents a possible bias in the estimationprocess 26Figure 10: Block diagram of the baseband system model. (a) Transmitter, (b)Channel, (c) Receiver 33ixFigure 11: ML NDA QPSK Synchronizer: Normalized RMS timing jitter vs. SNR,2BL=1 /1 00, and Butterworth G(f) with 11(107) bandwidth 41Figure 12: ML NDA Synchronizer for QPSK: Normalized RMS timing jitter vs.excess bandwidth a, SNR = 15 dB 42Figure 13: DA ML and MML Synchronizers for QPSK: Normalized RMS timingjitter vs. SNR, 2BLT=l/l00, a=0.35 48Figure 14: ML and MML DA Synchronizers for QPSK: Normalized RMS timingjitter vs. excess bandwidth a, for 2BLT=1I100, and no noise 49Figure 15: DA block synchronizer performance for QPSK: Normalized RMS timingjitter vs. SNR for a=0.35 and 16 samples/symbol 52Figure 16: Block diagram of model for computer simulation 55Figure 17: Typical sampling time error during acquisition for two simulations: MLDA QPSK synchronization with no noise, and SNR = 0 dB 57Figure 18: Simulation results for ML NDA QPSK scheme: Normalized RMStiming jitter vs. SNR, 2BLT=0.0065, a=0.35, and 128 samples?symbol 62Figure 19: Simulation results for ML NDA it/4—shift DQPSK scheme: NormalizedRMS timing jitter vs. SNR, 2BLT=0.0065, a=0.35, and 128samples/symbol 63Figure 20: Simulation results for ML NDA 16—QAM scheme: Normalized RMStiming jitter vs. SNR, 2BLT=0.0065, cz=0.35, and 128 samples?symbol 64Figure 21: Simulation results for ML DA QPSK scheme: Normalized RMS timingjitter vs. SNR, 2BLT=O.008, a=0.35, and 128 samples/symbol. 68xFigure 22: Simulation results for ML DA ir/4—shift DQPSK scheme: NormalizedRMS timing jitter vs. SNR, 2BLT=0.008, a=0.35, and 128samples/symbol 69Figure 23: Simulation results for ML DA 1 6—QAM scheme: Normalized RMStiming jitter vs. SNR, 2BLT=0.008, cz=0.35, and 128 samples!symbol 70Figure 24: ML Differential Symbol Block Synchronizer for ir/4—shift DQPSK:Comparison of 32 and 64 block length synchronizers in CCI,a=O.35, and 16 samples per symbol 73Figure 25: Bit error rate performance for block synchronizer and irI4—shift DQPSKmodulation scheme, a=O.35 and 16 samples/symbol 74Figure 26: Block diagram of fading process generation for simulation 81Figure 27: Block diagram of generation of a frequency-selective faded signal forsimulation 83Figure 28: Symbol timing recovery performance in frequency non-selectiveRayleigh and Ricean fading for the 3 synchronization schemes, nonoise 86Figure 29: Irreduciblelrreducible BER for fast flat fading channel, no noise 88Figure 30: Irreducible BER vs. sampling time offset from T!2 sampling instants forit/4—shift DQPSK with 2—ray frequency selective Rayleigh fadingmodel, with BFT=0.065 90Figure 31: Irreducible BER for 3 synchronizers in a frequency selective fast fadingchannel (-10 dB and -3 dB rays), including the BER for T!2sampling and for optimal sampling 92xiFigure 32: Irreducible BER for 3 synchronizers in a frequency selective fast fadingchannel (-10 dB and 0 dB rays), including the BER for T/2sampling and for optimal sampling 93Figure 33: Tracking performance of ML block synchronizer for Ic /4—shift DQPSKmodulation, without interference, and with frequency selectivefading 94Figure B. 1: Probability density function f(c), of timing jitter, with sampling instantsmarked 113XIIAcknowledgmentsI thank my parents Raymond and Beverly for their encouragement and continuous supportof all my endeavors, academic or otherwise. I would like to thank Dr. P. T. Mathiopoulos for hissuggestion of thesis topic, and for his valuable experience and guidance, without which this thesiscould not have been completed. I would also like to thank D. R Bouras for his helpful suggestions,as well as his contribution of much of the simulation code used in this thesis. Finally, I would liketo acknowledge the financial assistance provided by the Natural Sciences and EngineeringResearch Council (NSERC) of Canada, the Advanced Systems Institute (ASI) of British Columbia, and the University of British Columbia Faculty of Graduate Studies.xliiChapter 1: introduction1 IntroductionIn recent years there has been a dramatic increase in commercial interest toward digitalwireless personal telecommunication systems [1]. Interest has been generated by the promise ofmaking communication truly personal, in that users could communicate with anyone, virtuallyanywhere on the globe. Although complete integrated world coverage is not yet a reality, manysystems are currently in use or under development to provide wireless transmission of voice anddata for the personal user. Examples of such systems include pagers, cellular and cordless telephones [2], [3], cellular digital packet data (CDPD) [4], and indoor personal communication systems (PCS) [1].Virtually all these examples are now utilizing digital transmission technology. Digital networks are popular because of the increased capacity over analog systems, and the cheaper, smaller,and more power efficient receivers which may be used [31. However, digital transmission of signals adds a number of new complexities to system design. One such issue is that of symbol limingrecovery -- synchronizing the phase of the receiver’s symbol-rate clock with the received signal sothat recovery of the transmitted symbols may be achieved.Symbol timing recovery has been well studied in the past for the additive white Gaussiannoise (AWGN) channel, see for example [71, [8], [9], [10], [Il]. However, for the wireless communication system designer, the most serious sources of system degradation come from multipathfading - due to scattering of signals on terrain features, and co-channel interference (CCI) - due tointerference from other users in a frequency re-use network. This thesis concerns itself with theeffects of CCI and multipath fading channels on symbol timing recovery performance.IChapter 1. Introduction1.1 Modulation SchemesTwo genera] classes of modulation schemes are frequently used in wireless telecommunication environments, namely linear (quadrature) modulation, and continuous phase modulation(CPM). The linear schemes, such as L-ary phase shift keying (L-PSK) and L-ary quadratureamplitude modulation (L-QAM), usually possess a non-constant signal envelope, while CPM is afamily of schemes which maintain a constant signal envelope. Both classes are currently in use inwireless telephony, the North American digital cellular standard (IS-54) uses itI4—shft differentialquadrature phase shift keying (,t/4—shift DQPSK) as its modulation scheme, while the GSM European digital cellular system has chosen Gaussian Minimum Shift Keying (GMSK) as its modulation scheme [5], [6]. This thesis concerns itself with popular variations of linear modulationtechniques, which are perhaps the most common for digital transmission of information. Specifically considered here are 4-phase shift keying (quadrature-PSK or QPSK and it/4—shift DQPSK),and quadrature amplitude modulation (16—QAM), whose signal constellations are shown in Figure• . .I•...•........• . . ..••.(a) (b) (c)Figure 1: Signal constellations for modulation schemes underconsideration. (a) QPSK, (b) itI4—shift DQPSK, (c) 1 6—QAMThese modulation techniques are often used in wireless telecommunication networks inconjunction with a time-division multiple access (TDMA) scheme. TDMA splits a time interval2Chapter 1: Introduction(frame) into several time-slots, with each user occupying one or several time-slots in each framefor transmission or reception of signals. An example is the North American digital cellular standard (IS-54) TDMA specification [6]. TDMA is superior to frequency division multiple access(FDMA) schemes in that it allows more efficient use of channel bandwidth for intermittent datatransfers and allows mobile transmitters to operate in only a fraction of the total frame length.However, FDMA allows simpler implementation since breaking the frame into time-slots calls formore stringent synchronization requirements in the network [13].Half-rate TDMA frameSlot 1 Slot 2 j Slot 3 Slot 4 Slot 5 Slot 6Time slot324 bits in 6.67rnsFigure 2: IS-54 TDMA half-rate frame structure (from [6]).1.2 Wireless Personal Telecommunication ChannelsThe mobile wireless environment introduces new challenges to the reliable transmissionof digital information which are not seen in wire-line or optical communications. Chief among thesources of interference are co-channel interference and multipath fading, both of which will examined in this thesis.1.2.1 Co-Channel Interference (CCI)With the increased popularity of digital cellular networks and current research into anddevelopment of PCS, there is great economic pressure to increase network caller capacity to allowmore users on the limited bandwidth allotted to commercial use [1], [2]. In frequency re-use net-3Chapter 1: Introductionworks, a hasestation is responsible for servicing all mobile users within its assigned transmissionregion, or cell. Each hasestation is allocated a sub-set of the entire bandwidth associated with thenetwork. Basestations in neighboring areas are assigned other sub-sets of the network bandwidth.The simplest way to increase capacity is to reuse the frequencies assigned to a particular geographical location in another nearby location. Interference due to the common use of a radio channel isknown as co-channel interference (CCI), and is a major concern in frequency re-use systems. CCIis becoming a more prominent problem for cellular networks as they increase capacity by subdividing cells and moving them physically closer together [3], which is necessary for today’s callvolumes in urban areas. Network designers must carefully balance the added capacity availablethrough frequency reuse with the increased signal degradation due to CCI.An important measure of the level of CCI is the ratio of carrier power to interferencepower on a channel, known as the carrier-to-interference ratio (CII ratio), given as [3]:MC/i = (L) (EQ. 1.1)j= 1where M is the number of transmitters nearby which are using the same frequency as the transmitter under consideration, D is the distance to the 1rh transmitter, and R is the radius of coverage ofeach transmitter, depending upon the radiated power. The exponent y, due to path-loss, is typicallyequal to 4 [3]. Most wireless networks have specifications as to acceptable levels of CCI, based ona trade-off between the network capacity required and the allowable system degradation.1.2.2 Multipath FadingSince personal communication devices rarely have a direct line-of-sight path to a basestation transmitter, especially in urban areas, signals are scattered by terrain features. If the receiver is4Chapter 1: Introductionmobile, this caii cause a serious degradation of system performance, known as multipath fading.Fading is a major concern in the transmission of information over wireless channels [31, [13].Multipath fading may he modelled as a multiplicative interference [14], [3]:r(r) = f(t)s(t) (Eq. 1.2)where s(t) and r(t) are the transmitted and received signals, andf(t) is the complex multiplicativefading function, which may he modelled as a complex Gaussian process [3]:f(t) = rexp (JO) (Eq. 1.3)where r is a random process with Rayleigh or Ricean distribution and 9 is a random process withuniform distribution over (-ic,t] [13]. Fading may also be viewed as a form of modulation appliedto the signal. The phase term results in ‘random frequency modulation’ or ‘random FM’ of the signal which causes errors irrespective of the presence of AWGN. Therefore, fading causes a minimum achievable error rate, or ‘error floor’ on system performance [14].Rayleigh and Ricean fading can be characterized by the one-sided bandwidth of the fadingprocessf(t), given by [3]:2Vf (Eq.1.4)BF =where V is the velocity of the receiver [m/s],f is the carrier frequency [Hz], and c is the propagation velocity of the electromagnetic signal [mis]. The BFT product, the ratio of the fading bandwidth, BF, to the transmitted symbol rate, l/7 is an important measure of the amount of fadingpresent, indicating whether it is ‘slow’ or ‘fast’ fading. The boundary between the two classifications is a loose one, but a rule of thumb states that slow fading results from BFT<O.OO1 [13].5Chapter 1: introductionRicean fading has a line-of-sight component in addition to a reflected faded component. It is alsocharacterized by the power ratio K, between the direct line-of-sight signal and the reflected signalcomponent.Multipath fading may also spread the received signal over time, as well as frequency, sincescattered signals will arrive at the receiver with different time delays due to the varying lengths ofpropagation paths. This leads to a channel impulse response which spreads the received powerover a finite time interval. An illustration of a typical time-delay profile which might be measuredin an urban cellular channel is shown in Figure 3, which illustrates the spreading of power due todifferent signal paths (see [161 for actual test data). Such a channel characteristic will vary withtime if the receiver or scatterers are mobile.Figure 3: A typical channel power delay spread profile for an urbanenvironmentMultipath fading can he characterized by the average time-delay spread, td, which is theaverage time delay of the received power. For large values of ‘td/T (e.g., > 0.1), the fading is considered frequency selective [13]. It earns its name from the fact that for large tdT, different fre6Chapter 1: Introductionquencies within the signal bandwidth suffer different fading effects. At any instant deep amplitudefades may occur at specific frequencies only, instead of over the entire signalling bandwidth aswith frequency non-selective, or flat fading [3].Both frequency selective and non-selective fading may be encountered by a mobile wireless transceiver. Because of this, both Ricean and Rayleigh land-mobile fast fading, including bothfrequency selective and non-selective situations will be considered in this thesis.1.3 Symbol Timing Recovery TechniquesThere are a number of synchronization problems in digital communications, including carrier, frame, and symbol timing synchronization. The latter, also known as bit or symbol timingrecovery (STR), is the problem of synchronizing a receiver clock’s rate and phase with thereceived baseband data symbol sequence. Correct receiver synchronization is necessary for properrecovery of the received data. Errors in symbol synchronization can affect most aspects of systemperformance, including equalization and echo cancellation [18], [19], as well as bit error rate(BER) performance [201.Some telecommunication systems transmit clock information on a separate channel or byinserting a pilot-tone at the clock frequency [211, similar to inserting a pilot tone at the carrier frequency for carrier recovery and tracking [13]. These methods are inefficient, the former due to theadded bandwidth required to transmit a second signal, and the latter due to the increased powerrequired for the pilot-tone. In most cases symbol timing must be recovered from the received signal itself through a process of estimation.7Chapter 1: Introduction1.3.1 Measures of Symbol Timing Recovery PerformanceDifferent symbol synchronization schemes may be compared based on a number of met-des, including steady-state symbol timing jitter, acquisition time, and cycle slipping rate [7].Acquisition time is the amount of time required from the moment symbol timing recovery on a signal with unknown symbol clock phase is begun, until the clock phase is synchronized to thereceived signal. Timing recovery schemes can be evaluated by the average acquisition time, insymbols, which are required to recover the symbol clock phase [71. Cycle slipping is a reference toa non-linear effect observed in many recovery techniques, where the recovered clock effectivelyslips’ a symbol period, so that one or several clock periods are not registered by the recoveryscheme, [34), [35], [361. This is especially relevant in systems which employ a phase-lock loop(PLL) as a component of the recovery technique [9]. Symbol timing jitter is a measure of thesteady-state clock phase error associated with a particular recovery scheme, after acquisition hasbeen achieved. Timing jitter is usually measured as the root-mean-square (RMS) of the clockphase error, often normalized by the symbol rate [10]. This thesis concentrates on steady-stateerror, or symbol timing jitter since this is the most popular measure of performance for comparingsymbol timing recovery techniques.1.3.2 Symbol Timing Estimation TechniquesTraditional symbol timing recovery techniques involve extracting a periodic timing component from the received signal, which a tracking loop such as a PLL uses to estimate the correctsymbol clock phase [111. These techniques can be implemented by either analog or digital means(see for example [101, [24]). However, with the increased computational power available fromVery Large Scale thtegration (VLSI) digital receiver architectures, there has been development ofnew synchronizers which process blocks of received samples simultaneously [25], [26]. BLock8Chapter 1: Introductionsynchronizers, as they are known, store a block of input samples and process them together toextract a timing estimate for the entire block. Both digital tracking loops as well as block synchronizers generally involve multiple samples per symbol, although either can be implemented in aform using as little as one sample/symbol in high Baud-rate applications [27], [28], [29]Symbol synchronizers have been based on heuristic approaches [29], [30], such as theearly-late gate synchronizer [13], as well as on estimation principles such as maximum likelihood(ML) estimation, and minimum mean square error (MMSE) criteria [22], [23]. This thesis dealsexclusively with methods based on ML principles as their performance is generally superior toother methods [22]. In particular, two tracking loops based on ML principles are examined -- adata aided (DA) technique which assumes knowledge of the received data sequence to aid in estimation, and a non-data aided (NDA) technique which does not require knowledge of the receiveddata sequence [10], [11]. A third method, a block synchronization scheme based on ML principleswill also be examined.1.3.3 Timing Recovery in Wireless Communication ChannelsAlthough the three synchronizers to be examined have been proposed and analyzed for theAWGN channel [101, [11], [22], [23], the performance of symbol synchronization schemes inmobile wireless channel conditions has had little attention in published literature.With regards to CCI, we are aware of only one publication which deals with a simulationstudy of the effect of CCI channels on symbol timing recovery of a QPSK signal [31]. This studyprovides only a few results for specific simulation cases, and does not provide general conclusionsas how to minimize the effects of CCI.Several authors have examined the effect of fading channels on synchronization. A ML-9Chapter 1: introductionbased synchronizer for a general fading dispersive channel has been proposed [32], [33]. However,it relies upon knowledge of channel characteristics and requires a computationally intensivesearch-algorithm. Furthermore, its performance is evaluated with no prediction as to actualimprovements in BER or symbol timing jitter performance. Another technique has also beendeveloped for ML block synchronization and demodulation of a TDMA data frame involving carrier phase, symbol timing, and carrier frequency offset estimation [25], [261, and tested in a frequency selective fading environment. The algorithm was implemented in hardware, and is apromising candidate because of the simplifications in implementation used to reduce computational complexity. This technique is generalized to the block synchronizer examined in this thesis,in order to allow for theoretical analysis.In [611, a study is made of the ML NDA synchronizer in frequency-selective fading forbinary-PSK modulation. The paper found that the steady-state symbol timing jitter of an infinitelyfast (ideal) ML NDA tracking loop has no benefit over practical synchronizer’s performance.However, it does not provide symbol timing jitter expressions which may be useful for systemdesign, and more importantly, the analysis is only valid for the case that the delay spread is smallcompared to the symbol period.1.4 Thesis Research ObjectivesNoting the background provided, this thesis explores the effects of CCI and multipath fading on the performance of three popular symbol timing recovery schemes -- two tracking loops,and one block synchronizer, all based upon maximum likelihood estimation principles. The tracking loops (ML NDA and ML DA) are based upon recovering a sinusoidal timing wave through aphase-lock loop structures, while the ML block synchronizer is based on a direct evaluation of the10Chapter 1: IntroductionML log-likelihood function for symbol timing recovery. Genera] analysis is supported by computer simulation studies based on conditions encountered in digital wireless personal telecommunication systems.The thesis has two main objectives, which are:1) To study the effect of CCI on the tracking error (symbol timing jitter) of the three synchronizers. This will include a theoretical derivation of symbol timing jitter performance of the three synchronizer schemes in CCI, as well as computer simulations toconfirm the analysis and provide further insight. For both theoretical and computersimulated results, the performance of three popular modulation schemes (QPSK, t/4—shift DQPSK, and 1 6—QAM) will be considered and compared.2) To examine the operation of the ML NDA and ML DA tracking loops in a multipathfading environment, including both frequency non-selective and frequency selectivefading, and with both Ricean and Rayleigh fading. The performance evaluation resultsfor the fading channel will be obtained by means of computer simulation and willinvolve the it/4—shift DQPSK modulation scheme.1.5 Organization of ThesisThe thesis consists of six chapters, including this introduction (Chapter 1), and two appendices. The chapters are organized as follows:Chapter 2 introduces the concept of symbol timing recovery, providing a background forthe analysis and simulations which follow. Section 2.2 introduces the concept of symbol timingrecovery, and introduces root mean-square timing jitter as a measure of performance. Section 2.311Chapter 1: Introductionexplains maximum likelihood (ML) estimation for symbol timing recovery, and introduces thethree synchronizers to he examined in the thesis. Section 2.4 provides background on methods ofderiving expressions of RMS symbol timing jitter for each of the synchronizers. These methodswill be used in Chapter 3 to analyze the three synchronizers in a combined AWGN and CCI environment. Finally, Section 2.5 provides a summary of the chapter.Chapter 3 presents the analytical results obtained for symbol timing recovery performancein CCI for the QPSK, t/4—shift DQPSK, and 16—QAM modulation schemes. Section 3.1 is anintroduction to the subject of symbol timing recovery in CCI channels. It is followed, in Section3.2, by a description of the system model, including the CCI model, used in the analysis of thethree synchronization schemes. Section 3.3 to Section 3.5 present the analytical results of theeffect of CCI on the ML NDA, ML DA, and ML block synchronizers. Section 3.6 provides a summary of the chapter’s results.Chapter 4 is a presentation of a series of computer simulations performed to validate theanalytical results obtained in Chapter 3. After the introduction of Section 4.1, Section 4.2 is adescription of the computer simulation used to obtain the results, which are presented for the MLNDA, ML DA, and ML block synchronizer structures in Section 4.3 to Section 4.5. Section 4.6provides a summary of the chapter.Chapter 5 is an examination of the effects of multipath fading on symbol timing recoveryfor the t/4—shift DQPSK modulation scheme by means of computer simulation. Section 5.1 givesan introduction to the topic, while Section 5.2 presents the models used to generate both frequencynonselective and selective fading in the computer simulations. The simulation results and discussion then follow in Section 5.3. Finally, Section 5.4 gives a summary of the chapter’s results.12Chapter 1: IntroductionThe conclusions of the thesis, and some suggestions for future research are given in Chapter 6.Appendix A gives the detailed derivation of the equation for symbol timing jitter of theML NDA technique in AWGN and CCI channels. Appendix B provides a detailed analysis of theerror involved in measuring the symbol timing jitter in the simulations performed.13Chapter 2: Symbol Synchronization Principles2 Symbol Synchronization Principles2.1 IntroductionThe symbol timing recovery process has been well studied in the past for the AWGN environment (see for example [7]-[ll]). Although many heuristic methods for symbol synchronizationhave been proposed, it has long been recognized that timing recovery is essentially an estimationproblem of the time difference between the transmitted and received digital signal [10], [13]. Thischapter presents the basic principles and background of the symbol timing recovery problem.Since this thesis concerns itself with the symbol timing jitter performance of three maximum likeIthood synchronizers, methods of analysis for each technique are introduced here, and used in laterchapters.Section 2.2 presents the basic principles of symbol timing recovery. The concept of acyclostationary process is introduced to explain the underlying periodicity which enables the estimation of symbol timing. The behaviour of symbol timing jitter is also discussed, including itseffect on the BER performance of a receiver. Section 2.3 explains how maximum likelihood estimation can be brought to bear on the problem of symbol timing recovery. The three symbol synchronizers to be examined in later chapters are introduced: the ML NDA synchronizer, the ML DAsynchronizer, and the ML block synchronizer. All three are explained in terms of the maximumlikelihood concept. Section 2.4 provides the method of analysis for each technique which will beused in Chapter 3 to determine symbol timing jitter performance in combined CCI and AWGNchannels. Finally, Section 2.5 provides a summary of this chapter.14Chapter 2: Symbol Synchronization Principles2.2 The Symbol Timing Recovery Process2.2.1 Cyclostationary Processes in Timing RecoverySymbol timing recovery is possible because digital signalling introduces an underlyingperiodicity to the transmitted signal. Digitally modulated signals have a non-stationary componentwhose mean and autocorrelation functions are periodic in time with the symbol period T Such aprocess is known as a wide-sense cyclosratianary (CS) process [38].For example. a pulse-amplitude modulated (PAM) signal waveform may be expressed as:s(t) = ag(t—kT) (EQ.2.1)kwhere g(t) is an arbitrary pulse shape, and ak is the information symbol transmitted at t=kT, fromthe set of {ak} independent and stationary symbols. This can be shown to be a wide-sense CS process, since the mean and autocorrelation of the signal can be written as:E[s(t)] =E[aJg(t—kT) =E[s(t+T)]k (Eq. 2.2)E[s(t)s(u)J = =E[s(t+T)s(u+T)]kmwhere Ef.) indicates the expectation over the argument. This extends to the case of the quadraturemodulation schemes under consideration here (L-ary PSK and L-ary QAM), as well as CPM signalling such as GMSK [39], [40].Many commonly used PAM signalling schemes use zero-mean data (i.e. E[akJ=O) forpower efficiency, since there is no resultant DC component to the signal. Most symbol synchronizers require a signal with non-zero mean to recovery timing and therefore use some form of nonlinear processing to remove the modulation of the signal and generate a cyclostationary signal withnon-zero mean. After this operation. the signal can be written as:15Chapter 2: Symbol Synchronization Principless’(t) = g’(t—kT) (Eq.2.3)A:where g’ (t) is the pulse-shape after processing. For many choices of non-linearity, the resultantsignal now has a non-zero periodic mean as well as autocorrelation function, and can be used torecover symbol timing. This operation can he thought of as removal of the modulating signal, ormodulation removal, and is a basic concept in many symbol synchmnizers [11].2.2.2 Symbol Timing Jitter in Symbol SynchronizationThe steady-state tracking performance of a symbol synchronizer is generally measured by root-mean square (RMS) timing jitter normalized by the symbol period:r f /E[c21T=4E4 T2(Eq.2.4)where ‘r is the receiver clock timing error, a stationary random variable with variance a2 [41].For most synchronizers in an AWGN channel the timing vaiiance can be expressed by twostatistically independent components [221:= a2+a (Eq.2.5)the noise-dependent jitter, a,2. and the data-, or pattern-dependent jitter, d2 which is also knownas self-noise [421. The noise-dependent jitter is due to AWGN, and in well-designed systems is themain contribution to synchronization errors at low signal to noise ratios (SNR). The pattern-dependent jitter term is present in the absence of noise, and is caused by the intersymbol interference(ISI) of pulse overlap at the non-ideal sampling instants [411. Pattern-dependent jitter is the chieflimit to timing jitter performance at high SNR, and may be viewed as causing a jitter ‘floor’ -- aminimum level of timing jitter which can be obtained despite the absence of noise.16Chapter 2: Symbol Synchronization Principles2.2.3 Effects of Symbol Timing Jitter on Receiver BER PerformanceSymbol timing estimation is an important requirement of the detection process. Considered in this thesis is the case of a digital modulation scheme which employs Nyquist raised-cosinepulse-shaping to eliminate ISI at the ideal sampling instant [13]. Errors in symbol timing estimation degrade system BER performance because of sampling at a reduced eye opening.The specific effect of timing jitter on the BER performance of a system depends upon themodulation scheme used. For example. the errors introduced by symbol timing jitter in coherentlydemodulated binary PSK signalling is shown in Table 1. assuming no clock frequency or carrierphase estimation error. As can he seen, an offset of 9% of a symbol period can have an effect onBER perfonuance, which is increasingly severe for high SNR. In fact, an RMS jitter of 15% of asymbol period brings about an error floor at a BER of about i0 [101.Table 1: Effect of symbol synchronization error on BER performance comparedto SNR for ideal timing, for coherently demodulated BPSK (from (10]).RMS timing SNR loss at SNR loss atjitter (a/T) BER = iO BER = 1O0.090.120.151dB 5dB4dB 16dBN/A N/AN/A indicates that an error floor of approximately i0 is present for thisamount of timing jitter.For applications such as data transmission which require low BER performance, RMStiming jitter must be well below the O.09T level. Low BER requirements may necessitate a synchronization scheme which guarantees less than O.OIT jitter [101. For applications under consideration here, such as cellular telephony and PCN, higher BER levels may be acceptable and an RMSjitter of O.09T may be a measure of acceptable synchronization performance.17Chapter 2: Symbol Synchronization Principles2.3 Maximum Likelihood EstimationMaximum likelihood estimation of symbol timing is based upon expressing the likelihoodof the timing offset being a particular value, t = ‘c, based upon observation of the received signal.The likelihood function is maximized to locate the ML value of the symbol timing offset. In [11]the natural log of the likelihood function, or log-likelihood function for timing recovery is found tohe:A(t) = fx(t,t)s(t)dt (Eq.2.6)T0where s(t) is the transmitted signal as in Eq. 2.1, arid x(t,t) is the received signal, dependent uponthe timing offset t, as well as any noise added in the channel. The log-likelihood function has anobservation period of T0. An approximation is made by assuming the observation period is infinite,and that only K previous symbol periods are relevant during the current symbol period in s(t). TheML log-likelihood function for estimation of correct timing can then be simplified to [11]:A= k=O(Eq. 2.7)where Ck is in general a complex data symbol at the kth symbol interval, and:q()= f s(r)hR(t—kT—)dt (Eq.2.8)where hR(t) is a receive filter matched to the transmitted pulse-shape, h’t), and qk(t) is simply theoutput of the receiver’s matched filter, sampled at t = kT + t. The function is maximized by thevalue of which is optimal for sampling.Eq. 2.7 is used in the next three sections to illustrate how the three synchronizers underconsideration, the ML NDA, ML DA, and ML block synchronizer, are based upon the principlesof ML estimation.18Chapter 2: Symbol Synchronization Principles2.3.1 ML Non-Data Aided EstimationThe ML function, A (‘c), requires knowledge of the symbol sequence, Ck, transmitted. In[11], the likelihood function is averaged over the probability density function of the data symbols,ck } to rid the equation of its dependence on the symbol sequence. Assuming the symbols arebinary with ck E {±l} ,or Gaussian random variables, the result is similar [11]:A(t) ocln([cosh(q(t))]) =q(tI ck binaryk k (Eq.2.9)A (t) ° q(t) ck Gaussian.For the common NDA implementation the output of a matched filter, q(t,t) is fed to asquare-law device, and the integration over K symbol intervals is realized by a narrow bandwidthfilter or PLL [431, as shown in Figure 4. The prefilter. often a handpass filter (BPF) centred atf=I/2T, is used in order to minimize pattern-dependent timing jitter at high SNR [37], [12]. The BPF,K(f), extracts the periodic component of the resultant waveform, of frequencyf=I/T Zero-crossings of the timing wave, z(t), are used to locate the correct sampling instants. K(f) is often implemented as a PLL to provide a more reliable frequency-selective filter with an ability to compensatefor small clock-frequency offsets at the receiver [34]. [37].x(t)Figure 4: ML non-data aided symbol timing tracking loop [31].Notice in Figure 4 that the in-phase (I) and quadrature (Q) inputs are processed separately,I Channelz(t)BPF(@11019Chapter 2: Symbol Synchronization Principlessince squaring the complex received signal in a balanced modulation scheme results in a subtraction of the two independent timing waves, canceLing the output [11]. However, each of the I and Qsignals can be viewed as separate binary PAM signals which yield periodic timing signals of equalphase. and may be added together to pmvide a timing estimate for the received waveform [311.2.3.2 ML Data Aided EstimationThe ML data-aided scheme uses a decision device to approximate the transmitted symbolsequence. The derivative, denoted by ‘S’, of the simplified log-likelihood function in Eq. 2.7 is:KA(t) = ckk(t). (Eq. 2.10)k=OThe log-likelihood function is maximized when Eq. 2.10 is zero. The ML DA implementation in Figure 5 is a realization of this method. It can be viewed as a gradient method, where thederivative, or gradient of the ML log-likelihood function is used to achieve tracking. At the nominal interval T specified by the timing wave, z(t), a sample is taken of both the signal and its derivative. A decision device decides on the symbol transmitted, which is multiplied by the sampledderivative of the signal. The result is fed through a loop filter to a number controlled counter(NCC), the digital equivalent of a voltage-controlled oscillator (VCO), which generates z(t). Sincethe feedback loop is similar to a PLL, this synchronizer will be subject to acquisition time considerations, as well as cycle slipping phenomena. Notice, as with the NDA case, the I and Q inputs areprocessed separately to avoid cancellation of the resultant timing wave.20Chapter 2: Symbol Synchronization Principlesx(t)Figure 5: Data-aided symbol timing tracking loop. (DD) is decisiondevice, (SPC) is parallel-to-serial converter for output data sequence,(NCC) is number controlled counter [31].2.3.3 ML Block EstimationThe ML block symbol synchronizer differs from the previous two methods since it operates on a block of samples at one time to derive timing estimates for the entire stored waveform.The block synchronizer under consideration here simply divides the symbol period into a finitenumber (N) of equal intervals and evaluates the ML function of Eq. 2.7 over K symbols for eachdiscrete time interval, choosing the instant which maximizes the expression. This suggests a searchalgorithm, shown in Figure 6, as follows:1) Sample the received signal at a rate NIT.2) Store samples over a duration of K symbol periods, or KN samples.3) Calculate the N metrics given by:A1=i= { 1, ...,N} q.2.11)21Chapter 2: Symbol Synchronization PrinciplesThis synchronizer has a great deal of added complexity, but allows synchronization without any required acquisition time. As well, since it does not contain a non-linear tracking ioop, itwill not suffer from cycle slipping phenomena seen in synchronizers employing tracking loops.An alternate synchronizer structure has been proposed [251, [261, which uses differentialdecoding prior to symbol synchronization. This may be performed by multiplying each sample bythe complex-conjugate of the sample occurring N samples previously (one symbol period). Thus,the synchronizer metrics are given by:= k=2N NI = {1 N)where ‘—‘ indicates complex conjugation, and l is now an estimate of the differential symbolreceived. Using differential symbols for synchronization can help overcome carrier-phase offsetsat the receiver. This is especially appropriate for use with the jr/4—shift DQPSK modulationscheme, since for the DA ML synchronizer, the decision device must be able to distinguishbetween an 8—symbol constellation, as shown in Figure 7. Using the differential symbols, only a4—symbol constellation must be distinguished. As well, the term q(iT/N)_1(i ) isobserved to be the differential decoding operation used in a symbol-by-symbol differentialNIT4) Choose the sampling instant t=(k÷iIN)T, where i is chosen to maximize A1.inputsamplesAtFigure 6: Block diagram of ML block synchronization scheme.K(Eq. 2.12)22Chapter 2: Symbol Synchronization Principlesreceiver, therefore the transmitted data can he recovered in the same operation. Since differentialdetection can be used, this completely eliminates the need for carrier phase recovery at thereceiver. Of course the disadvantage of this scheme is the amplification of noise in the receivedsignal. However, it has been shown that implementation of this technique in an AWGN can stillproduce accurate timing estimates [261.Figure 7: Comparison of signal constellation for ML blocksynchronization using (a) symbol constellation, and (b) differentialsymbol constellation, for it /4—shift DQPSK signalling.2.4 Analysis of Symbol Synchronization TechniquesHaving introduced the three synchronization schemes, it will prove useful in this sectionto examine methods of analyzing the symbol timing jitter of each technique. In the three methodspresented, analysis is simplified by assuming that perfect carrier recovery is achieved, and signalsare demodulated to hasehand. In Chapter 3, these methods will be used to analyze the effect of CCIon synchronizer performance.2.4.1 Phase-Lock Loop Theory for the NDA ImplementationThe tracking symbol synchronizers under consideration may he viewed as PLL’s withnonlinear phase detectors, as illustrated in Figure 8. This allows the use of linearized PLL theory to. .. .(a) (b)23Chapter 2: Symbol Synchronization Principlesdetermine expressions for symbol timing jitter. However, most PLL analysis assumes stationaryinput disturbances [71, [34], whereas here the input to the synchronizer is a cyclostationary signal[12], [44]. It has been shown that use of the general equations derived for a stationary input disturbance can greatly overestimate the amount of timing jitter at the PLL output [42], [44j, [45], sinceit ignores the CS process, in effect averaging out its periodicity.u(t)Figure 8: A general symbol synchronizer as a PLL. F(f) is a loop filter,and VCC is a Voltage Controlled Clock.The output of the nonlinear phase detector block can be written as the sum of a sinusoidalcomponent to be tracked and a zero mean noise disturbance, M(t) [12]:1 2itv (t) —cos (—t + e) + M (1) (Eq. 2.13)where P is the power of the sinusoidal component. The phase offset 0, of the sinusoid represents apossible offset of the PLL nonlinear phase detector stable point from the ideal sampling instant dueto a bias in estimation [46]. The above equation is a well-known PLL expression, with the parameters related by [12]:.Jexp (jo) = (E [v (t) I exp (—2jict/T)) (Eq. 2.14)where <.> indicates a time-average over TFor wide-sense stationary noise input, the output jitter variance of the PLL, can beexpressed as [9]:24Chapter 2: Symbol Synchronization Principles=.1 IHL(f)I2[So(f÷ ) +S0(f— )]df (Eq. 2.15)where L(f) is the equivalent linearized phase transfer function of the PLL, andS0(f) is the powerspectral density (PSD) of M(t).It has been shown for wide-sense CS M(t) that timing jitter variance can be written as [121:= I V’i.. (f) 25 (I) df (Eq. 2.16)whereS (f) = ! [s (f+!) + 5 (f_!) (Eq. 2.17)(f+ ) exp (—2j0) ) exp (2j0)]andSk(f) = FT{y(x)} k = {O,±1,±2} (Eq.2.18)where FT{. } represents the Fourier transform of the argument with respect to the time-variable x.yk(x) is the kth Fourier series coefficient of the autocorrelation of a CS M(:) expressed as a Fourierseries:RM(u,u+x) = y(x)exp(ku). (Eq. 2.19)If the input is stationary, the autocorrelation function becomes simply RM(v), and Sk(J) = 0 fork 0. It can be seen that Eq. 2.15. for stationary M(t), is simply a special case of Eq. 2.16 for CSM(r).To see more clearly the difference between the two equations, it is useful to examine thetiming wave, z(t), which is the output of the ML NDA synchronizer, as seen in Figure 4. Its variance can be written as [101:25Chapter 2: Symbol Synchronization PrinciplesE [z2 (t)] = C1 + C,cos (t) (Eq. 2.20)which consists of C1, a constant term, made up of (signal x signal), (signal x noise), and (noise xnoise) terms at the output of the square-law device, and a periodic C2 cos(4itIT) component due tothe CS nature of the (signal x signal) term [37]. The two terms are statistically independent [12],and when added together the ideal sampling instant occurs at the location of minimum jitter, whichis smaller than in the stationary case. This is illustrated in Figure 9, where the importance of usingEq. 2.16 is evident.E[z2(t)] E[z2(t)]Figure 9: Illustration of timing wave variance for (a) wide-sensestationary and (b) wide-sense CS inputs to the filter-square-filter MLNDA synchronizer. 0 represents a possible bias in the estimationprocess.If it is assumed that the PSD of the disturbance is relatively constant over the frequencyrange for which IHL (J) 0, and furthermore that = IIHL (t)I2fwhere 2BL is defined as theequivalent double-sided noise bandwidth of the PLL equivalent phase transfer function, then forwide-sense CS input noise:= (2B) S (0). (Eq. 2.21)time(a) process (b)26Chapter 2: Symbol Synchronization PrinciplesThus, the jitter can be specified by determining the PSD of the input noise term, and theequivalent noise loop bandwidth of the PLL used for recovery. It is important to note, however,that linearized PLL theory is based upon the linearization of a nonlinear PLL transfer function.This is strictly valid only for a small disturbance term, M(t), so actual and predicted performancewill diverge for large M(t).Since small sampling time errors in multi-level modulation schemes may cause unacceptable bit error rate performance [10], pattern dependent jitter is a concern for system designers. Anumber of schemes have been put forward to minimize or eliminate the pattern-dependent jittercomponent. In [37] it was found that the pattern dependent jitter term is eliminated by a pulseshape, G(f)1 at the input to the squarer, which has even symmetry aboutf=l/(2T) and is bandlimited to 11(47) < f I <z 3/(47). Using a bandpass prefilter as in Figure 4 is meant to shape G(J) tothese parameters. However, timing jitter can never be eliminated practically in this configuration,since the symmetry conditions must be exact. For example, in [37] it was found that a ML NDAscheme with bandpass prefilter bandwidth 0.4/T and PLL normalized equivalent noise bandwidthof2BL= 1/20, has an RMS pattern dependent jitter value of 0.O1T for a filter frequency mistuningof only 0.0025T.2.4.2 Phase-Lock Loop Theory for the DA ImplementationThe DA scheme, which samples at a nominal rate of lIT, is best analyzed through digitalPLL theory [7], [34]. If the nonlinear processing involves a sampler at the clock rate, v(t), u(t), andF(f) in Figure 8 can be replaced by vk(t)=v(kT-i-t), uk(t)=u(kT+t), and F(z), respectively.1. G(i is the pulse shape at the output of the prefilter so 0(f) = H(f)P(f), where P(19 is the Fourier transform of theprefilter, and H( is the Fourier transform of the input signal pulse-shape. See Figure 4.27Chapter 2: Symbol Synchronization PrinciplesThe output of the nonlinear processing section, vk, can be written as the summation of theaverage output. as well as a disturbance term [12], dk (k) such that vk () = E [vk (k)1 + dk ()•The mean value is the output of an equivalent phase detector, denoted spD(t)=E[vk(t)1, which issimply the output of the PLL nonlinear phase detector in the absence of a disturbance term. By linearizing the phase-detector characteristic around t=O, and replacing the PLL with its equivalentclose-loop phase transfer function, whose impulse response is hjjz), the tracking error, e, can beexpressed as [22]:ek = —hL(k—n)dfl(t)/4D(O) (Eq.2.22)where the transfer function of the PLL is given by [221:KNCCF(z) rPD (O)HL (z) (Eq. 2.23)z— 1 +KNCCF(z)spD(O)with KNCC indicating the sensitivity, or ‘gain’ of the NCC in the feedback path. Unlike the MLNDA case, where the phase detector characteristic may not pass through the origin and thereforehave a phase offset term (see Eq. 2.13), the phase detector characteristic for the DA ML schemeresults in an unbiased timing estimate [46], since it does pass through the origin. As with the MLNDA case (see Section 2.3.1), linearizing the PLL transfer function is strictly valid only for smalldk(tk), which remains in the linear region of the phase detector, or equivalently, small timing jitter.If the double sided loop bandwidth is given by 2BLT = I [exp U2I) I 2df, the timingjitter can be found as the variance of the error term [22]:= E [e1= IIHL [exp (j2itf) I 12S [exp (j2icf)] df/4D (0) (Eq. 2.24)= (2BLT) S (0) ‘D (0)where S(O) is the PSD of the disturbance term, {dk(t)), evaluated atf=O, provided that the PSD is28Chapter 2. Symbol Synchronization Principlesapproximately constant nearf=O.Although the simplification in Eq. 2.24 holds for a PLL with stationary input, a cyclostationary input will include a disturbance term whose PSD is zero at preciselyf=O and therefore isnot constant over the range of frequencies where 11L [exp (j21rJ) j2 0 [48]. This term gives riseto pattern-dependent jitter. It has been shown in [42] that this disturbance term is proportional to ahigher power of(2BL7). The resultant jitter term is proportional to (2BLT) for a first-order PLL,and (2BLT)3 for second-order PLL [48]. An approximation to this term is given in [22] for the DAML synchronizer with second-order PLL transfer function as:S(O) 2=(2BT).2 + (2BLT)3 , m2 [-Rd (m)] (Eq. 2.25)SPD(O) SpD(O) rn—Iwhere:• S,(f) is the PSD of the disturbance terms for which S(J) is approximately constantaround f:=O, and has autocorrelation sequence, R(m).Rd(m) is the autocorrelation sequence of the disturbance term for which the PSD termSd(O)=O,• is the damping ratio of the synchronizer’s close-loop equivalent continuous-timetransfer function [34].As with the ML NDA case, a number of techniques have been put forth to eliminate pattern dependent jitter, such as the modified ML (MML) scheme (see Section 3.4.2) which includesa prefilter, as well as a minimum mean square error (MMSE) based technique [23]. Both of these,however, sacrifice performance at low SNR to improve performance at high SNR.2.4.3 Symbol Block SynchronizersThe simplified ML log-likelihood function of Eq. 2.7 can be expressed as a three term29Chapter 2: Symbol Synchronization PrinciplesTaylor series expansion around the ideal sampling instant. By approximating A (t) with its mean,noise-free equivalent, the symbol timing jitter can be written as [101:r.2ELA (0)=2(Eq.2.26)E[A(0)jwhich holds for small values of timing jitter. This technique yields a lower bound on performanceof a general ML symbol timing recovery technique. Since the ML block synchronizer evaluatesthe ML log-likelihood function discretely, the equation will provide a lower bound on performance, limited by sample time resolution, as well as the number of symbols processed in a block.For Nyquist raised-cosine pulse-shaping h(t), and AWGN with double-sided PSD of NJ2this provides a lower bound of [10]:>! (SNR)1 h(O) (Eq. 2.27)K—h(0)}where SNR=(a + a) h (0) / (N0/2). It is interesting to note that performance is identical tothe a ML DA implementation, ignoring the pattern-dependent jitter term, with 2BLT= 1/K (see Eq.3.18). It should be kept in mind that this derivation does not account for the sampling rate of thealgorithm. Rather, it is a more general expression for a ML synchronizer which evaluates the MLlog-likelihood function. Since this is an expression for a generic ML symbol synchronizer, it canbe seen that the ML DA technique reaches the lower bound on performance unless pattern dependent jitter is the dominant contributor to timing jitter. Tracking performance of the ML DA tracking loop can be viewed as that of a block synchronizer with ‘memory’ of 1/(2BLT) symbols [10].The traile-off for ML block synchronizers is between time tsolution and the expense intime and hardware of metric calculations. The number of samples/symbol, N, determines the number of metrics to be calculated, and the minimum timing-jitter attainable2.In the absence of noisethe average RMS jitter due to time quantization3 is T/ (NJi). The worst case sampling jitter,30Chapter 2: Symbol Synchronization Principleswhere the ideal sampling instant lies exactly between samples is T/ (2N). A sampling rate of 16/Tallows a minimum normalized RMS timing jitter of 1.8% of T, while the worst-case minimumblock RMS timing jitter would he 3.125% ofT2.5 SummaryThis chapter outlined the theory of symbol timing recovery, as it applies to three synchronizers under consideration, the ML NDA and ML DA tracking loops, as well as the ML block synchronizer. The concept of the CS process was introduced to explain the periodic nature of digitalsignalling which enables symbol synchronization at the receiver. Symbol timing recovery is anestimation problem, and maximum likelihood estimation was discussed. It was shown that all threesynchronizers are based upon a simplification of the ML function for symbol timing estimation.Popular methods of finding the steady-state symbol timing jitter performance of the tracking loop synchronizers were presented, which recognize them as forms of a PLL with CS inputs.The methods presented are general and cover both stationary and CS input disturbances. A methodof detennining the lower bound on timing jitter performance is presented for the block synchronizer, which exhibits jitter performance similar to the ML DA scheme. It was pointed out that allmethods presented involve linearizing a non-linear process, and assume that levels of noise andinterference in the synchronizer are low enough to maintain operation in a linear region.The tools presented in this chapter will be used in to analyze the effects of a combinedAWGN and CCI channel on jitter performance of each synchronizer in Chapter 3 and Chapter 4, aswell as in fading channels in Chapter 5.2. Since the error in sampling time will be constant over an entire block, timing jitter in this case refers to the average sampling time error over multiple blocks.3. This is the well-known result for quantization noise in digital sampling [49J.31Chapter 3: Symbol Synchronization Analysis in CCI Channels3 Symbol Synchronization Analysis in CCIChannels3.1 IntroductionAlthough symbol timing recovery jitter performance has been well studied for the AWGNchannel with a variety of signalling formats, little has been published on the effects of CCI onsymbol timing recovery. As previously mentioned, we are aware of only one conference paperpublished on this topic. More specifically, in [31] simulations are used to predict the level of CCIwhich yields a BER of iO for QPSK signalling with both ML NDA and ML DA synchronizers.The paper concludes that a BER of iO is achievable in the presence of a single interferer at C/Ilevels up to 3.5 dB. However, the simulations are performed for only a few cases of 1 or 2 interferers with particular timing offsets, and can not he used to predict performance for other modulationschemes. Furthermore, the results reported in [311 do not provide an exact explanation of how thesynchronization schemes are affected by CCI.In this chapter. the effect of a combined AWGN and CCI environment is considered. Analysis of the three synchronization schemes discussed in Chapter 2, the ML NDA, ML DA, and MLblock synchronizers, provide expressions for the timing jitter performance of each for a generallinear quadrature modulation scheme. Section 3.2 introduces the baseband system models for thetransmitter, channel, and receiver, including the model of CCI, to be used in the analysis. Then,Section 3.3 to Section 3.5 outline the analysis of the ML NDA, ML DA, and block synchronizers,in CCI and AWGN for the general case of linear quadrature modulation, including QPSK, 7t/4—shift DQPSK, and 16—QAM. The chapter ends with Section 3.6, which provides a summary of the32Chapter 3: Symbol Synchronization Analysis in CCI Channelsresults obtained.3.2 System ModelThe block diagram of the system model is shown in Figure 10. A baseband model is usedfor mathematical convenience.3.2.1 Transmitter ModelThe block diagram of a typical transmitter is shown in Figure 10(a).._4>[j>optional(a)n(t) 1(t)r(t)(b)_____realI-channel(C) zzzz> complexQ.channe.Figure 10: Block diagram of the baseband system model. (a) Transmitter,(b) Channel, (c) Receiver.The signal mapper maps the input binary data stream, {dk) into the symbols k=7k33Chapter 3: Symbol Synchronization Analysis in CCI Channelsexp(ji2k), where ‘Ik and k are the amplitude and phase of k’ respectively. For the case of L-PSKsignals, the amplitude, ‘Yk is constant, and the phase, 12k takes a value from a discrete set of Lequally distributed phases, depending upon the data stream {dk).A differential encoder may be utilized to code a new sequence, {Ck), where:== exp k— I (EQ. 3.1)where indicates modulo 2ic addition, and‘1k is the phase of ck.The signal is then passed through a transmit filter with impulse responseh7-j’t) to shape thesignal pulses, yielding the equivalent haseband transmitted signal:s(t)= ckhT(t—kT) (Eq.3.2)kand the resultant signal is then mixed to the carrier frequency and transmitted through the channel.3.2.2 Receiver StructureThe block diagram of the basehand receiver is illustrated in Figure 10(c). The receivedequivalent haseband signal is:r(t) = s(t) +n(t) +1(t) (Eq.3.3)where n(t) and 1(t) are the hasehand equivalents of the channel AWGN process with double-sidedPSD N012, and the CCI process, respectively. The signal is passed through a receive filter withimpulse response hR(t), yielding in a pulse-shape h(t)=hr)*hR(t) where ‘*‘ indicates convolution.The pulse shape considered is the well-known Nyquist raised-cosine filter which eliminates ISI atthe sampling instants, where h7’(f) = hR(f) are each ..J& raised cosine filters. The pulse shape H(f)has transfer function [13]:34Chapter 3: Symbol Synchronization Analysis in CC’! Channels11(J) (1_sin[(f_)]) (Eq.3.4)1+ct0where a is the excess bandwidth4of the signal. The resultant signal, assuming no frequency offsetbetween the transmitted symbol rate and the local reference at the receiver, is:x(t) = ckexp (jp)h(t—kT+t) +u(t) +1(t) (Eq.3.5)kwhere p is the difference in carrier phase between transmitter and receiver and t is the symbol-rateclock offset or timing error of the receiver sampling clock. The case of ideal carrier recovery willbe considered in this thesis to simplify analysis, therefore it is assumed that p=O. The complexbasehand Gaussian noise process can be written as u(t)=n(t)*hR(t), and the baseband CCI equivalent is 1(t)=i(t)*hR(t). Since the signals under consideration in this thesis are quadrature modulated,the transmitted symbols can be expressed in terms of the in-phase and quadrature symbols:ck = a +jbk (Eq. 3.6)where and bk have variance G2a and G2b, respectively. The symbol timing recovery system mustadjust the phase of a symbol-rate clock, in order that sampling for data recovery is performed atthe maximum eye opening within each symbol period.Finally, the sampled signal is passed to the decision device, where an estimate of the transmitted binary data stream, { d } , is recovered.3.2.3 Co-Channel Interference ModelAs explained previously the CCI, 1(J), results from other inobile-basestation pairs hans4. Excess bandwidth a is with respect to the minimum Nyquist bandwidth of 11(27).35Chapter 3: Symbol Synchronization Analysis in CCI Channelsmitting on the same frequency, at a distance from the mohile-hasestation pair under consideration.CCI is often modeLled in literature as a summation of equal-amplitude unmodulated carriers, eachwith a statistically independent carrier phase offset from the transmitted signal (see for example[50], [51]). This model has been shown to work well in calculation of BER, with the assumption ofideal timing [5 1].Here, however, a more comprehensive model of CCI will he used, similar to [50], [62],and [63). CCI is defined as a summation of M independently generated and modulated signals,such that:M Al1(t) = 1(t) = il khT(t—kT+t÷Wl)exp (Jp1) (Eq.3.7)1=1 1=1 A:where the 1th interferer, !Kt), has a statistically independent data stream, {il.k} and has carrierphase and timing offsets, Pt and 4’i respectively, from the transmitted signal. it will become apparent later that this is an appropriate CCI model for considering effects on symbol timing recovery,since it is a summation of cyclostationary processes which may affect symbol synchronization differently than a summation of unmodulated carriers.The analysis will concern itself with the case where each interfering signal is of the samemodulation type as that under consideration, which accurately reflects a frequency re-use networksuch as cellular or PCS systems. The results are also simplified by considering only equal-amplitude interferers, which yields, for a given C!! ratio, the worst bit-error rate performance [51]. Thus,each interferer has a quadrature modulation similar to the transmitted signal, or k = ‘4kThe variance of each interferer can be expressed in terms of the variance of the signal for balancedmodulation such as L-PSK and L-QAM as = = Ao = A2a . Here, a and are thevariances of the independent in-phase and quadrature zero-mean CCI symbol streams, {l,k) and36Chapter 3: Symbol Synchronization Analysis in CC’! Channels{tk} respectively, a2 and G2b are variances of the I and Q data symbols, a and bk respectively,and A2 is the ratio of the interferer power to the signal power. Therefore, the C/I ratio in dB can beexpressed as:[C/IjdB = —lOlog (MA2). (Eq. 3.8)For the purpose of the analysis, the carrier phase offset of each interferer will be disregarded. If the term exp(jp1)is included in the symbol sequence, {ilk}. the adjusted interferer datasequences will have the same mean and variance. The forthcoming analysis will depend only onthe mean and variance of the interferer data sequences. so as long as the carrier offsets for eachinterferer is statistically independent of all others, and essentially constant compared to the hitperiod, the carrier offset can be ignored. This will he sufficient for us to ignore the carrier phase inthe timing jitter analysis to follow, and for simplification Pt is set to zero for all interferers.3.3 Analysis of the ML Non-Data Aided (NDA) SynchronizerUsing the method outlined in the Section 2.4.1. analysis begins by finding the power andbias terms inherent in the ML NDA synchronizer. The power of the averaged input v(t) and itsphase offset can he derived by solving for v(t) and substituting into Eq. 2.14 to express the averageinput power and the phase offset:2 2 ‘)2 1 2P=_a+G) Z0(—) (1±1/C)T T (Eq 3.9)9 =where the expectation has been taken over the CCI timing offsets, uniformly distributed between(— <ji ) . 1/C is the inverse of C/I, and:Zm(f) = FT{g(t)g(t—mT) }= f G(s)G(f—s)exp (—j2nmTf)ds (Eq. 3.10)37Chapter 3: Symbol Synchronization Analysis in CCI Channelswhere g(t), with Fourier transform G(f), is the pulse-shape at the output of the prefliter P(f) seen inFigure 4 prior to the square-law device5,such that g(t)=h(t)*p(t). To simplify the final expression,the effect of the Cd ratio on the power term in Eq. 3.9 will be neglected. since the result in the finalRMS jitter equation for a C/I of 10 dB will be less than 10%, and eliminating the term will simplify the result.The input signal is a summation of the transmitted signal, AWGN and CCI, so the input tothe square-law device (see Figure 4) for the in-phase (I) channel can be expressed as:y(t) = ag(—kT) +u’ (t) (Eq. 3.11)where u’(t) is the AWGN filtered by the receive filter HR(f) and prefilter P(f), such thatu’ (t)=n(t)*hR(t)*p(t), and 1.k is the in-phase (I) data component of the n1 interferer at the kih symbol interval. A similar equation can be written for the quadrature arm of the synchronizer.To solve for timing jitter, the method outlined in Eq. 2.16- Eq. 2.18 is used. This involvesfinding the autocorrelation function, R(u,u+ v) of components of v(t), and solving for Sk(JJ, the PSDof the jitter components. The final equation is averaged over the range of possible CCI timing offsets to yield an average jitter perlbrmance. The detailed calculations are performed in Appendix A,which can be simplified, when Ga2=C1bl for normalized power to he:=(2B) [C1V + V3 +V2(SNR)’ + (SNR)2V41(Eq. 3.12)+ (2BL) [(C/I)’ (V3+2V5V6) + (C/1)2V5÷V6+(C17)/(2M))Jwhere:5. Note that g(t) here is the output of the prefilter pnor to the square-law device, as seen in Figure 4. Previously,in Eq. 2.1 - Eq. 2.3, g(t) was ussd as a generic signal pulse shape.38Chapter 3: Symbol Synchronization Analysis in CC! ChannelsVl=[1_cos(ØA_2O)]2V,= 2Z0(—) [l—cos(ØB—8)J2jZo(1/T)I m T2 t 2 1v3= 2i’ SG(—s)dsIZ0(1/T)I -V4= 2 JSGSG(Td5 (Eq. 3.13)—V= jl((s)I2G(ls)ds2TIZo(l/T)I..1 21zo(0)12TIZ0(1/T)IV7=and C1 = [a4+a4_3((a2)2÷(a2)2)1 where a4 and a are the expectations of the fourthpower of the I arid Q data streams. The variables V1, (1=1,.. ,6) are dependent on synchronizer ifitering, while only the variable C1 is dependent upon the modulation scheme used. In this case, signal-to-noise ratio and carrier-to-interference ratio are defined by SNR = (a + a) / (N0/2) andC/I = MA2 respectively.In Eq. 3.12, the first line represents the performance of the ML NDA synchronizer in anAWGN environment [121. The second line is made up of components introduced by CCI. It can beseen that both V1 and V2 contain a term of the form -cos(4 - 20), which represent the cyclostationarity of the received signal. However, the CCI terms 1/3 and V5 - V7 have no such component.Examination of Eq. A.6 and Eq. A.8 of Appendix A reveals that each CCI component does, in fact,contribute a cyclostationary component. However, since each contributes a sinusoidal component39Chapter 3: Symbol Synchronization Analysis in CCI Channelswith a random phase to the variance, the net effect of averaging over the range of CCI timing offsets 1411, for each interferer IKi), is to cancel out the sinusoidal components.Averaging over the range of all possible CCI timing offsets yields the same result as notaveraging the offsets, hut including a large number of CCI components, M. For a small number ofinterferers however, cases of specific timing offsets may yield either better or worse performancethan the average timing jitter derived in Eq. 3.12 indicates. However, given that a mobile receiver,by definition, changes orientation and distance from the various sources of CCI, the timing offsetsfrom the various CCI sources would he expected to vary over time, effectively averaging the timing offsets over the symbol period.Except for theC1V7/(2M) term in Eq. 3.12, the timing jitter is independent of the numberof interferers present. This term however, is found to be very small when evaluated numericallyfor some specific cases. For the case of Nyquist filtering, with a Butterworth bandpass prefilter ofbandwidth 0. lIT, the difference in RMS timing jitter between I interferer and a lalEe number ofinterferers, such as 50, is less than 5%. As long as the bandwidth of 0(f) is small, the V7 tenn willhe negligible. Therefore, it can he stated that for cases under consideration in this thesis, with narrow bandwidth prefilters, timing jitter is only weakly dependent upon the number of interferers, M.Numerical evaluation also indicates that the C1V term in Eq. 3.12 is very small compared to theV2 term. Since only C1 is dependent upon the modulation scheme used, the results for QPSK, it/4—shift DQPSK, and 16—QAM were found to be practically identical (less than 4% difference in evaluation). Therefore, it is expected that the results for the three modulation schemes should be similar. However it has been shown with different filter characteristics that higher level modulationschemes such as 64—QAM may exhibit considerably more timing jitter [37].40Chapter 3: Symbol Synchronization Analysis in CCI ChannelsThe normalized RMS timing jitter for the NDA synchronizer in the presence of AWGNand CCI was found by evaluating Eq. 3.12 by numerical integration. Figure 11 illustrates theeffects of CCI on the NDA synchronizer for 2BLT= 1/100 with G(f) a 4-pole Butterworth filter witha 3 dB bandwidth of 11(107). Although this PLL bandwidth may be considered large for some traditional timing applications [22], the acquisition time required by TDMA systems requires a relatively large PLL bandwidth be used. Figure 11 shows that although careful system design caneliminate pattern dependent jitter at high SNR, the addition of CCI to the channel greatly degradesjitter performance, and is the chief limit to performance at high SNR.10_i____ ______ ________________Figure 11: ML NDA QPSK Synchronizer: Normalized RMS timing jittervs. SNR, 2BL=lIlOO, and Butterworth G(f) with iI(i07) bandwidth.‘ I -Ci1=lOdB [——I =,‘jE1o2. 10FC’)Cfl=14d8:L‘%\‘‘.N4‘ =‘1ML NDA QPSK_SynchronizerjLL.H S1N0 Interfej \44.0 10 20 30 40 50 60 70SNR [dB]41Chapter 3: Symbol Synchronization Analysis in CCI ChannelsFigure 12 illustrates the effect of the signal excess bandwidth, a, on jitter performance forvarious levels of CCI. The effect of CCI can be seen to be approximately equal over the entirerange of bandwidths, since each interferer has the same bandwidth as the transmitted signal andwill therefore behave similarly with varying bandlimiting.• -21OCI,In the absence of CCL the pulse-shape of the symbol sequence may be manipulated toeliminate pattern-dependent jitter (see Section 2.4.1). However there are no subtraction terms inthe equation due to CCI since the cyclostationary aspect of the signal has been averaged out, so the— ..,. ,,.. - -- ,... ... .... —-\—---“-------- ——C4 10 dBInteerenc%%f C/!=2Bj ML NDA QPSK SynchronizerSNR=l5dB.... .... .... ..,. ....10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9Excess BandwidthaFigure 12: ML NDA Synchronizer for QPSK: Norrnali.zed RMS timingjitter vs. excess bandwidth a, SNR = 15 dB.42Chapter 3: Symbol Synchronization Analysis in CC! ChannelsCCI jitter terms may not he eliminated. Examination of the CCI term in Eq. 3.12 shows that onlyby decreasing the PLL loop bandwidth, 2BLT may the effects of CCI he minimized. Of course, thiswill increase the acquisition time of the synchronizer [7] and is generally not desirable.3.4 Analysis of Data Aided Synchronizers3.4.1 Maximum Likelihood Data Aided SynchronizerThe equivalent phase-detector function for the ML DA symbol synchronizer, defined inSection 2.4.2 as the average E[vk(r)] (see Figure 5), is unaffected by the introduction of CCI to thesystem, since the derivative of the I and Q portions of CCI multiplied by the recovered datastreams results in a zero-mean process. Therefore:SPDet) = E[vkCr)1 = (o+a)h(t) (Eq. 3.14)which is the same as the case of no CCI, and indicates that the introduction of CCI will not bias thetiming estimate by altering the linearized phase detector slope, which will pass through the originfor a Nyquist raised-cosine h(t).As explained in Section 2.4.2, the term vk(t) can be written as a sum of the average, orequivalent phase detector function, and a disturbance term. The disturbance term of Eq. 2.22 canthen be written as the sum of three terms, d1r) being the disturbance due to the data x noiseterm, d2k(t) due to the data x signal term, and3lt) due to the data x CCI term. Therefore, writing an expression for vk(t) from Figure 5, and subtracting E[vk(t)j gives:dk(t) = dlk(t) +d2k(t) +d3k(t) (Eq. 3.15)= (ak+bk)Nk+ (akak_m+bkbk_m)h(nT+t)M (Eq. 3.16)+ (aki_m + bk?k_m) h(mT÷twhere N is the derivative of the AWGN filtered by hR(t) and sampled at :=kT+rk.43Chapter 3: Symbol Synchronization Analysis in CCI ChannelsThe autocorrelation sequences of the three disturbance terms can be written:(a2+)[—h(O)] (N0/2) ,n=OR1(m)={ a bo mO[22 2)2]2m=OR2(m)=2 2-i.2 (Eq. 3.17)—[(a2) + (a) ]h (mT) ,nOR3(m) = m=O0 m0The last term in Eq. 3.17 is the contribution of CCI to the timing jitter Notice when takingthe Fourier transform of the disturbance autocorrelation functions that R3(m) is an impulse function, similar to the AWGN component, R1(m). Therefore S3(f) is a constant and may be treated aspart of the noise-dependent jitter, such that S(O)=S1(O)+S3) and the resultant jitter term will beproportional to the loop-bandwidth of the PLL. The signal-to-noise ratio can be expressed in thiscase as (a + h (0) / (N0/2) and substitution of Eq. 3.15 - Eq. 3.17 into Eq. 2.25 gives:=(2BT)(Eq. 3.18)+(2BLT) (C/I)’In the above equation, the first term is the AWGN term, and the second term is the pattern-dependent jitter term. The third term is inversely proportional to C/I, as well as proportional to thePLL loop-bandwidth. Since it is independent of the SNR, it will have its greatest effect at highSNR when noise-dependent jitter is negligible. Average timing jitter is independent of M, the number of interferers. Also note that the result is independent of the modulation scheme employed,1h (0)44Chapter 3: Symbol Synchronization Analysis in CCI Channelsprovided each scheme has normalized power such that Ga2 = Gb = 1.The numerator of the third term in Eq. 3.18 due to CCI is an average over all possible timing offsets for each interferer. As with the ML NDA case, individual instances of CCI with particular values of timing offsets may yield larger or smaller CCI components than the average.However, for large M, or a mobile receiver as explained in Section 3.3, the value observed will beaveraged.The result of Eq. 3.18 is similar in form to that in [521, where the effect of a single echosignal on telephone line ML DA symbol synchronization was examined. Since the echo is modelled as a signal with a statistically independent data sequence and a timing offset from the signalof interest, it is seen that this result is simply a special case of the derivation of Eq. 3.18, whereM= 1 and the pulse-shape h(t) is limited to a specific shape.3.4.2 Modified Maximum Likelihood DA Synchronizer AnalysisThe modified ML data aided, or MML DA, synchronizer is a modification of the ML DAsynchronizer, put forward in [23] to eliminate pattern-dependent jilter which dominates at highSNR in the Ml. DA synchronizer in AWGN. From Eq. 3.18 pattern-dependent jitter depends onthe output of the differentiator at t=kT. The MML DA scheme eliminates this term by replacing thedifferentiator in Figure 5 with filter, HMML(f), which has impulse response hMML(t) [231, so thecascaded filtering on the differentiator arm is now:HR (I’) HMML (f) = HR (f) (J21cf_ h(mT)exp (—J2lrmTf)) (Eq. 3.19)which can be approximated with a digital filter implementation [23]. The first term in brackets is adifferentiator, and the second term is a cancellation term. If the output pulse-shape of this filter isdesignated r(t), which replaces the pulse shape h(t) in the ML DA analysis:45Chapter 3.’ Symbol Synchronization Analysis in CCI Channelsr(t) = hT(t)*hR(fl*hUML(t) = h(t)_h(mflh(t_mT) (Eq.3.20)Since we consider Nyquist filtering, h(t-mT) = 0 for all cases but m = 1, where h (mT) 0, therefore r (mT) = 0, V m. Now, the autocorrelation of the pattern-dependent jitter term is given by:Rd(m) = E[anan+mafl_kafl+m_l]r(kT)r(lT) = 0 (Eq.3.21)kiso the pattern-dependent jitter term vanishes. Unfortunately, since HMML(f) is optimized to eliminate pattern-dependent jitter, noise dependent jitter increases and performance of the MML DAsynchronizer degrades compared to the ML DA synchronizer at low SNR.The MML DA synchronizer in the presence of AWGN and CCI is now examined. Asbefore, the phase-detector characteristic is unchanged. The disturbance term associated with CCIand its resultant autocorrelation function can he written as:d3k(t)=(aki,k_m+ bkk_m) r (mT+W1) (Eq. 3.22)R3 (m)={ (aa + aa)EL r2 (kT + Wi)j ::: (Eq. 3.23)This is the same CCI term as appears in Eq. 3.17, with r(t) substituted for h(t). The resultant jitter expression, combining the spectrum of Eq. 3.23 with the result in AWGN from [23]:aMML= (2BLT) (SNRY’h(0)2(Eq. 3.24)‘° h(0)E r2(kT+’qi)+ (BL2T) (C/!)1 2r (0)46Chapter 3: Symbol Synchronization Analysis in CC! ChannelsThe second term, the CCI-dependent jitter, is independent of the SNR and will dominate at highSNR causing a lower limit to the minimum achievable jitter, as in the ML DA case.From the HM,L(f) filter shape in Eq. 3.19, it can be seen that although the MML DAscheme has a performance benefit over the ML DA scheme at high SNR, it is more difficult toimplement. While the ML DA scheme uses a simple derivative (realizable as a difference equationin digital implementation), the MML DA scheme uses HMML(f), a more complicated filter toimplement. However, in either case, CCI will be remain a problem at high SNR.3.4.3 Results of ML and MML DA Jitter Performance AnalysisThe analytical results of jitter performance for the ML and MML DA schemes in a combined AWGN and CCI environment were evaluated numerically for equivalent noise bandwidth of2BLT= 1/100. The obtained performance results in terms of the RMS timing jitter are shown in Figure 13 with the ML DA scheme having a PLL with damping ratio, 2=1I2 which has been show tobe near optimum for symbol timing recovery [481. As expected, it can be seen from both figuresthat the ML scheme outperforms the M1bVIL scheme by approximately 3 dB at low SNR, while theMML performs slightly better at high SNR in the presence of CCI. Comparing the performance ofthe ML NDA and ML DA synchronizers in Figure 11 and Figure 13 shows that the ML DA technique has better performance in CCI.It should be noted, for both the ML DA and MML DA symbol timing jitter results in Eq.3.18 and Eq. 3.24 respectively, that the CCI jitter term can be decreased only by narrowing thePLL bandwidth. Since the jitter performance is comparable between the two techniques in CCI,the added difficulty of implementing a scheme which eliminates pattern-dependent jitter, such asthe MML DA scheme may not be warranted if CCI is deemed to he a problem.47Chapter 3: Symbol Synchronization Analysis in CCI ChannelsI-._____ _____ _____ _____ __________U-IF___Figure 13: DA ML and MML Synchronizers for QPSK: Normalized RMStiming jitter vs. SNR, 2BLT=lI100, cx=0.35.Figure 14 illustrates the effect of excess bandwidth, a, of the raised-cosine pulse-shape onthe timing jitter, with no AWGN present. The MML DA scheme ideally has no jitter in the absenceof noise. It can be seen that CCI affects are similar over the entire range of a, although the MMLscheme has worse performance than the ML case for small excess bandwidths (a<O.15). This issimilar to the MML DA case in AWGN only, where performance is degraded for small a as seenin [231.—h.-CII..I 10 d,-‘p-—j..)4= 14dl]—,,‘F.—%. .‘.,‘...m10110.21 011C/I =20——‘ :—_ii 1-== ..—L4—--jDA MML Scheme j— ——.j DA ML Scheme__H——‘I‘I‘L.I,C/I.—c--—-I’I.—0 10 20 30 40 50 60 70SNR [dB]48Chapter 3: Symbol Synchronization Analysis in CC! Chann’ls-210Fio1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1Excess BandwidthFigure 14: ML and MML DA Synchronizers for QPSK: Normalized RMStiming jitter vs. excess bandwidth c, for 2BLT=1I100, and no noise.3.5 Analysis of the ML Block SynchronizerThe lower hound on performance may he found for the ML block synchronizer as in Section 2.3, with Eq. 2.7 and Eq. 2.8. Starting with Eq. 3.5, the expression for the received waveformwith AWGN and CCI, with the CCI expressed as in Eq. 3.7, the expression for the simplified log-likelihood function of Eq. 2.7 is found. The jitter may be expressed as in Eq. 2.26, in terms of theML function, ignoring the pattern-dependent component for the sake of simplicity:a49Chapter 3: Symbol Synchronization Analsis in CCI ChannelsE[A2(O)] = — K(a÷a)-2(O) + E[(aa + aa) (mT-kT+ NJ1)] (Eq. 3.25)and:E[A(O)] = K(a+a)h(O) (Eq.3.26)so that the lower hound to timing jitter variance may be expressed, according to Eq. 2.26 as:1 ‘ h(O) _,E[h2(mT÷W)]— (SNR) + (C/I) — m (Eq. 3.27)K (—h(O)) K h(O)It is observed that the block synchronizer timing jitter lower bound is identical to the ML DAresult of Eq. 3.18, ignoring the pattern-dependent jitter term, and with 2BLT= 1/K. Once again, CCIintroduces a timing jitter variance term which is independent of the number of interferers Mpresent.The derivation of Eq. 3.27 is actually valid for a generic ML recovery technique whichevaluates the ML function. However, the derivation did not take into account time quantization ofthe ML block synchronizer. The coarse time quantization which is required by the block symbolsynchronizer to reduce computational complexity will add an additional lower limit to the RMSsymbol timing jitter. Since the system time and memory requirements grow with the number ofsamples per symbol used to evaluate the ML equation, a trade-off must be made by choosing fewenough samples per symbol to fit within system constraints while still providing enough resolutionto meet system timing constraints.The lower-hounds for various sampling rates are given in Table 2. The minimum averageRMS jitter is calculated from the time quantization noise, while the worst-case RMS jitter assumesthat the receiver symbol clock is accurate, but the ideal sampling time lies halfway between twosamples.50Chapter 3: Symbol Synchronization Analysis in CC? ChannelsSince [101 indicates that for binary PSK, RMS timing jitter above approximately 0.09Tmay cause considerable error ax high SNR, choice of a sampling rate of at leastf5=8/T is warranted, although f=16IT is used in [25] and [26] for QPSK. Unfortunately, each doubling of thesampling rate results in a doubling of the calculation required. It will be shown however, that asampling rate off5=1 6/T is sufficient for minimal timing jitter in CCI.Table 2: Effect of sampling rare on minimum possible jitter at high SNR (nonoiseSamples Minimum Average Worst-case minimumper RMS timing RMS timingSymbol jitter (G/T) jitter(G/T)8 0.036 0.062516 0.018 0.0312532 0.009 0.01562564 0.0045 0.0078125The lower bound of Eq. 3.27 was evaluated numerically, resulting in Figure 15 for blocksizes of K = 32 and 64, and for N= 16. The minimum average RMS jitter was included in the boundso that any prediction of Eq. 3.27 falling below the minimum average RMS jitter were limited tothat value. It is interesting to note that a block size of 64 is sufficient to keep the jitter due to CCIbelow the average time quantization noise. Providing the pattern-dependent jitter is smaller thanthe average jitter due to quantization, the chief cause of jitter at high SNR will be the jitter due toquantization. Only for K 32 is the CCI a concern. Larger block sizes will only slightly increaseperformance at SNR <20 dB.51Chapter 3: Symbol Synchronization Analysis in CCI Cha,zn1s10_i:Cl)1SNR [dB]Figure 15: DA block synchronizer performance for QPSK: NormalizedRMS timing jitter vs. SNR for a=O.35 and 16 samples/symbol.3.6 SummaryThis chapter explores the effect of CCI on symbol synchronizer timing jitter performancefor the ML NDA and DA tracknig loops including the performance of a modified ML DA (MMLDA) scheme. It also examined the performance of the ML block synchmnizer.Results for the ML NDA synchronizer show that, although it has negligible effect at lowSNR, CCI is the chief limit to performance at high SNR for systems with low pattern dependentjitter. It was found that the CCI added a constant term to the jitter variance, while the periodic52Chapter 3: Symbol Synchronization Analysis in CCI Channelscomponents due to the cyclostationarity of the CCI signals were eliminated by averaging over allpossible timing offsets. The three modulation schemes under consideration, QPSK, 7t/4—shiftDQPSK, and 1 6—QAM, have quite similar performance for the Nyquist pulse-shape examined.The ML DA and MIvIL DA results also indicate that CCI is the chief limit to timing jitterperformance at high SNR. As is the case for AWGN only, in a combined AWGN and CCI environment, the DA schemes outperform the NDA scheme, as was found in the cases evaluated in [31].The jitter equation was found to be independent of the number of interferers present in the environment, or the quadrature modulation technique used. It depended only on the CII ratio. As well, thejitter was found to be the same for all of the modulation schemes considered. In both the ML NDAand ML DA cases, the only method for reducing CCI is by reducing the ioop bandwidth of the synchronizer, although this is undesirable due to increasing synchronizer acquisition time.Analysis of the ML block synchronizer’s performance found that its lower-bound on performance is identical to the performance of the ML DA scheme, ignoring the pattern-dependentjitter of the latter case, as was seen in [101 for the AWGN channel only. Except for very high levelsof CCI such as CII <10 dB and small block lengths such as K<64, CCI was not a concern for theML block synchronizer, since RMS timing jitter due to CCI was less than the time-quantizationerror for a reasonable sampling rate of 161T53Chapter 4: Computer Simulation of Symbol Synchronization in CC!4 Computer Simulation of SymbolSynchronization in CCI4.1 IntroductionIn the previous chapter the timing jitter performance of three synchronizers -- the MLNDA and DA tracking loops, and the ML block synchronizer were analyzed in an AWGN and CCIenvironment. The tracking loop analysis was based on linearizing the performance of a PLL withcyclostationary input [12], while the IvEL block synchronizer analysis was based upon a truncationof a Taylor’s series expansion of the ML log-likelihood function [10]. Both of these approachesrely on a linearization of an inherently nonlinear system. and are only valid providing timing jitteris small [11], [22].This chapter outlines a series of computer simulations performed, modelling a typicalhasehand digital communication system, to verify the analytical results of the previous chapter.Section 4.2 gives a detailed description of the computer simulation model. Section 4.3 providesfurther information on the ML NDA simulation, and presents results of the simulation study. Section 4.4 and Section 4.5 provide results for the ML DA and ML block synchronizer simulations,respectively. Both symbol timing jitter and the bit-error rate (BER) performance for each of thesynchronizers are considered, and comparison made to the results of Chapter 3. Finally, Section4.6 provides a summary of the results of this chapter.4.2 Computer Simulation System DescriptionComputer simulations were performed to obtain RMS jitter estimates and BER performance for each of the symbol synchronizers using the quadrature modulation schemes QPSK, ic/4-54Chapter 4: Computer Simulation of Symbol Synchronization in CC!shift DQPSK, and 16-QAM. The model used was a hasehand digital communication system, asillustrated in Figure 16.Transmitter ChannelFigure 16: Block diagram of model for computer simulation.A random binary symmetric source provided data for a modulator generating a basebandmodulated signal which was then filtered with a root-raised cosine transmit ifiter. The receive filterwas also a root-raised cosine filter, which resulted in raised-cosine Nyquist filter pulse shaping.The demodulator utilizes a symbol timing recover system (STRS) to locate sampling instants. Therecovered data sequence is compared to the input data sequence to determine bit errors. Theoptional signal fading generator was not used in the simulations outlined in this chapter, but is usedin Chapter 5.Baseband modulation, demodulation, and CCI generation followed the model outlined inSection 3.2. The CCI generator was realized by M identical transmitter sections, each with a random timing offset uniformly distributed between [-T/2, T12), and equal amplitude. To average over55Chapter 4: Computer Simulation of Symbol Synchronization in CC!the range of timing offsets for each interferer, simulations were repeated a number of times withoffsets generated randomly. A value of M=50 was used for the case of M —* oo, to yield virtuallythe same performance as AWGN, due to central Limit theorem [131 which dictates that CCIapproaches the statistical characteristics of Gaussian noise as M increases. The simulations assumeperfect carrier recovery. Simulations were performed using the BLOSIM simulation package [531,on a Sun Sparc- 10 workstation. Monte Carlo techniques were used to measure the bit-error rate,using error counting techniques. RMS timing jitter was by measured by summing the squares ofthe difference between the estimated sampling instant and the ideal sampling instant for each symbol, which occurs half-way through the symbol period for each symbol.4.2.1 Description of the ML NDA and DA Tracking Loop SimulationsThe tracking loop synchronizers were designed and adjusted in the absence of AWGN orCCI to achieve phase synchronization in less than 100 symbols assuming no clock frequency error.This limit was chosen in order that the two schemes reach synchronization within a typical TDMAframe, which may last only several hundred symbols. The signal had an initial timing offset of T/2,the worst-case condition. Since AWGN and CCI may prolong acquisition, the first 200 symbolperiods were ignored for measurement of RMS timing jitter or BER. T’pical acquisition performance is illustrated in Figure 17 for the no noise case, as well as AWGN with SNR=0 dB.In order to measure RMS timing jitter accurately in the simulations, the ML NDA and DAsynchronizers were designed to exhibit more self-noise than might otherwise be present in a well-designed symbol synchronizer. The main constraint on measurement was the number of samplesper symbol. With 128 samples per symbol, the smallest recordable RMS jitter is oE.JT = 11256 =0.0039. In order to assure correct measurement of timing jitter, both synchronizers simulated had a56Chapter 4: Computer Simulation of Symbol Synchronization in CCInormalized RMS pattern dependent jitter well above this value; 0.012 for ML NDA QPSK and0.0082 for ML DA QPSK simulations. This allowed comparison of the simulation results withpublished theoretical results at high SNR [121, [221. Further discussion of the simulation jittermeasurement error may be found in Appendix B.C1-Figure 17: Typical sampling time error during acquisition for twosimulations: ML DA QPSK synchronization with no noise, and SNR = 0dB.The BER was measured by error counting and averaging over each simulation. Theassumption was made that a cycle-slip could be detected at the receiver, perhaps by coding tech-0.40.3MLDAQPSKTypical Simulation AcquisitionNo noise I-0.1-0.2 0 500 1000 1500 2000Symbol Periods57Chapter 4: Computer Simulation of Symbol Synchronization in CCIniques above the physical layer, so that cycle slipping only caused one symbol error instead of creating a sequence of errors if the slip were not detected. This is implemented in the simulation bymonitoring the sampling time with respect to the ideal sampling point. If a symbol is missed, or asymbol is sampled twice, the output hit-stream could not be properly compared with the input bitstream. Therefore, the error is noted, and an extra sample is either include or removed from theoutput data stream. This greatly simplifies the measurement of BER and was found to be valid inthe simulations performed, since cycle slips were only observed in the simulations for instances ofvery low SNR (<5 dB).In order to average the effects of CCI over all possible timing offsets, a set of 8 simulations were performed for each result obtained, each with a random timing offset for each co-channel interferer. Each of the ML DA and NDA simulations measured performance over 16,000symbols transmitted. The PSK schemes have a 90% confidence interval of (1.9x105,7.6x105)ata BER of 3.815x105,while the 16—QAM scheme had a 90% confidence interval of approximately(9.5x106,3.8x105)at a BER of 1.9x105 [54]. These values allow us to satisfactorily measureBER’s down to the i0 level [54].Ideal BER curves for AWGN and CCI channels were generated for comparison by measurements made in 8 simulations each of 16,000 symbols transmitted, with 128 samples per symbol. These curves actually have a constant timing offset due to time quantization of 0.0039T whichproduces a negligible error (less than 0.5 dB degradation in SNR) over the range of BER’s examined. BER performance for the AWGN only case was validated by comparison with its theoreticalperformance [13].58Chapter 4: Computer Simulation of Symbol Synchronization in CCI4.2.2 Description of the ML Block SimulationsThe ML block synchronizer simulations, unless otherwise noted, were performed with 16samples/symbol, and 256 khits of transmitted data using a t/4-shift DQPSK modulation scheme.16 samples/symbol was chosen in Section 3.5 as a practical sampling rate for the block synchronizer algorithm which would yield a worst-case RMS timing jitter due to time quantization for ablock of 0.03 125T A total of 8 simulations with randomly chosen CCI timing offsets were performed, with the same random seeds as for the ML DA and ML NDA schemes. Since the MLblock symbol synchronizer has no requirement for acquisition time overhead, timing jitter andBER measurements were performed over the entire simulation. In this case, the timing jitter is thesame for all symbols in each block processed, and was averaged over all the blocks processed ineach simulation. As with the ML NDA and DA cases, ideal BER curves were generated for comparison by measurements made in 8 simulations each of 32 kbits transmitted, with 128 samples persymbol.4.3 ML NDA Synchronizer Simulation ResultsThe NDA simulation was designed to be typical of normal implementation. The onerestriction is that pattern-dependent jitter he measurable in the simulation at high SNR. A simplesecond-order Butterworth handpass filter centered atf=1/(2T), with -3dB bandwidth of lJ(1OT)was used as a prefilter. Since the Nyquist raised-cosine roll-off filter used for pulse shaping is notsymmetric about f= 1/(2T), the resultant signal shape G(f) is asymmetric about the center frequency. To eliminate self-noise entirely, the prelIlter would have to be designed to distort the signal such that the signal was symmetric aboutf= 1/(2T), as explained in Section 2.4.1.A second-order PLL was employed with a multiplier as phase detector, iteratively59Chapter 4: Computer Simulation of SYmbol Synchronization in CCIdesigned in order to exhibit low timing jitter, while still synchronizing in less than 100 symbols inthe absence of noise. A simple loop filter of the form:F(s) = (EQ.4.1)which is the approximate transfer function of a simple, popular passive loop filter for the second-order PLL [341. The function was realized as an infinite impulse response (1W) filter via the bilinear transform [55] for computer simulation. To compare with the analytical results of the last chapter, the PLL was converted to its linearized PLL equivalent equation, and the equivalent noisebandwidth was solved for numerically. The accuracy of this approximation may provide someerror in comparing the analytical results to the simulated results.The voltage controlled oscillator constant was KVCO=2.,and the resultant equivalentnoise bandwidth of the loop was evaluated using linear PLL theory (see [34]) to be 2BLT=0.0065.Simulations were performed with QPSK, it/4—shift DQPSK, and 16—QAM, and results are shownin Figure 18, Figure 19, and Figure 20, respectively.Several observations may be made from Figure 18, the QPSK case:The simulation performance diverges from the theoretical jitter curves for low SNRand exhibits worse performance. This is observed in similar simulations performed inAWGN in [22], and is due to the failure of the linear assumption for the PLL phase-detector characteristic. For the derivation, the phase detector characteristic wasassumed linear for small jitter. As the timing jitter increases, the linear approximationis no longer valid.RMS timing jitter performance is worse for the M= 1, or single co-channel interferercase at high SNR by about 25%, which was not predicted in Eq. 3.12. This is due to60Chapter 4: Computer Simulation of Symbol Synchronization in CC!the fact that the CCI amplitude is highest for the M=l case for a particular C/I ratio.For this case there is the largest difference between maximum and minimum values ofthe cyclostationary component of jitter variance due to CCI. The nonlinearity at higherjitter amplifies the larger values, which are no longer completely averaged out by thecorresponding lower values of the sinusoidal jitter component. This results in a higherjitter value than predicted. This effect is not a concern at the M=4 case or above wherethe timing jitter error is less than 2%, since there are more interferers, each with loweramplitude.Figure 19 illustrates the results from ir/4—shift DQPSK simulations. As Eq. 3.12 suggests,the performance matches the QPSK case closely (for example, for infinite M at C/I = 10 dB, thedifference between simulations being less than 10%).Figure 20 shows the simulation and analytical results for the 16—QAM modulationscheme. The simulation results here show that the 16—QAM scheme’s perfonuance is slightlyworse than the other schemes considered. At high SNR, with CII=lOdB and M=1, the error isabout 35%, while for the other two modulation schemes the error was about 25% as compared tothe predicted theoretical performance. Even the case of no CCI exhibits slightly worse performance than expected.The 16-QAM signal has a 4 different amplitude levels in each of the I and Q signals, sothat for a constellation which is normalized to have unity power, the signal power may vary from0.4 to 1.3. It is believed that these signal power variations affect the PLL tracking, since the loop isdesigned for a particular input power level. QPSK simulations were performed with the previouslynormalized amplitude set to 0.4 and 1.3. In the absence of noise the timing jitter increased as much61Chapter 4: Computer Simulaiion of Symbol Synchronization in CCIas about 45% from the unity power case. Therefore, the variation of amplitude of the 16—QAMmodulation scheme causes more timing jitter due to the synchronizer’s dependence on inputamplitude level. As can be seen in Figure 20, this leals to an increase in RMS jitter over the QPSKsimulation results. Therefore, the analytical results arrived at in Section 3.3 will underestimate jitter for higher-level quadrature modulation schemes, although for 16-QAM, the error is only about10% greater.10_i______ _______ _______ ______________:_c’ ir2Figure 18: Simulation results for ML NDA QPSK scheme: NormalizedRMS timing jitter vs. SNR, 2BLT=00065, aO.35, and 128 samples/symbol.II‘ -.‘. .‘‘ —.‘ ,) CA=lOdL..-‘_.T• ..LJ0Pr= 14 dB b‘. U:‘‘:ML NDA QPSK Simulations No tnterfereTheory—A Simulation, CA 10 dB, M’- —. Simulation, CA 10 dB, M = 4• Simulation, C/I= 10 dB, M I —Simulation, C/i= 14 dB, Mo Simulation, CA=l4dB,M=4 —D Simulation, C/I= 14 dB, M = 10 Simulation, No Interference-,, I -.0 (%.1-5 5 15 25 35 45SNR [dB]6210_i______________PI__________C,,______________________-5 5 15 25 35 45SNR[dBlFigure 19: Simulation results for ML NDA W4—shift DQPSK scheme:Normalized RMS timing jitter vs. SNR, 2BLT=O.OO&5a=0.35, and 128samples/symboLChapter 4: Computer Simulation of Symbol Synchronization in CC!;lOdLj14rF-____II.’__,i-0—No lnteeren: ML NDA 1V4 DQPSK,mulatiOnStheorySimulation, CA10dB,M• Simulation, C/I = 10 cIB, M = 4• Simulation, C/I= 10 dB, M = 1A Simulation, C/I= l4dB,Mo Simulation, CA —14 dB, M 4Simulation, CA=l4dB,M=1O Simulation. No Interference163Chapter 4: Computer Simulation of Symbol Synchroni:ation in CC!10_i3--5F-C.’) io26. The RMS timing jitter measured in the absence of AWGN is essentially a jitter error floor as shown in Figure18 to Figure 20.,...,,,.,,,,,,,,,,,%A=14dB*: ML NDA 16-QAM Simulations- Theory- A Simulation, Cfl=. 10 dB, M No lnterference.....• Simulation, CA= 10 dB, M = 4—• Simulation, C/1= 10 dB, M = 1- Simulation, C/1= 14 dB, Mo Simulation, CI1= 14 dB, M 4- o Simulation, C/I = 14 dB, M = 10 Simulation, No Interference,,,L,,,[ .•1_______________________________________ ___-5 5 15 25 35 45SNR [dB]Figure 20: Simulation results for ML NDA 1 6—QAM scheme: NormalizedRMS timing jitter vs. SNR, 2BLT=0.OO65,a=0.35, and 128 samples/symbol.Table 3 illustrates the percentage error between the simulation results and theory for different values of the excess bandwidth, a, of the raised-cosine filtering with no AWGN6,C/I = 10dB, and a large number of co-channel mterferers (i.e. M —* Do). The error increases at lower valuesof a since the timing jitter of the ML NDA scheme is larger at low a, and leaves the strictly linearregion where the analytical results are correct. The error at large a indicates that the value of 2BLT64Chapter 4: Computer Simulation of Symbol Synchronization in CC!used in evaluating Eq. 3.18 is slightly inaccurate, since the value was evaluated for the equivalentlinearized analog system. This value affects the slope of the curve, as well as its minimum value.Table 3: Simulation Error vs. excess bandwidth a, ML NDA synchronizationwith QPSK modulation, CII 10 dB, M —* , 2BLT=0.0065, and no noise.Excess Bandwidth RMS Jitter Simulationa error (%)0.10 21.7%0.20 13.1%0.35-7.3%0.50-9.7%0.90-10.2%BER curves for the simulations are not included here, hut showed negligible effect ofincreasing timing jitter on the BER performance of the systems because the worst-case jitter athigh SNR is still below 6% of a period. A sample of measured BER performance may be seen inFigure 25 in Section 4.5 for the block synchronizer, whose jitter performance at high SNR is theworst of all simulations performed. Therefore, it is concluded that CCI interference at the decisiondevice with ideal symbol synchronization is the limiting factor on performance for these modulation schemes. The addition of a realistic ML NDA symbol synchronizer for a combined AWGNand CCI environment did not noticeable degrade the BER performance.Within the limits of the theoretical assumptions leading to the analytical results, the simulations show that the analytical results correctly predict timing jitter performance in the presenceof CCI. The analysis underestimates performance for RMS jitter of about O.02T or above, which isthe same value where performance began to diveie in simulations performed in [22]. However,the amount of jitter caused by CCI is not a significant limit on system performance at C/I ratios of65Chapter 4: Computer Simulation of Symbol Synchronization in CCIup to 10 dB, which would be considered a high level of CCI in today’s frequency reuse systems.At high SNR where CCI has its most prominent effect the equations predict the resultant RMS timing jitter with an error on the order of 10% or less for the constant amplitude constellation modulation schemes, with the case of one interferer giving the most severe error. A difficulty withevaluating the analytical results is in determining the exact value of the PLL equivalent noisebandwidth, which has a direct effect on the symbol timing jitter results at all values of SNR.44 ML DA Simulation ResultsThe ML DA synchronizer lends itself well to digital implementation, and was simulated asexplained in Section 2.3. The derivative in each arm of the synchronizer was approximated with adifference equation, x[nj = x[nj —xn— 11.The decision device for the QPSK and 1 &-QAM simulations simply chose the symbolfrom the constellation whose Euclidean distance is closest to the sample. The it/4—shift DQPSKdecision device simulated was a simplification of the ideal decision device. For it/4—shift DQPSK,the ideal decision device must decide between four possible constellation points for each symbol,and also keep track of which of the two possible constellations is currently used for transmission.7fri the simulation the decision device was replaced with a simple 8—PSK Euclidean-distance decision device. The performance of this simplification will be identical to the ideal decision device athigh SNR, but may suffer some degradation when interference is prominent. This simplificationwas used only for symbol synchronization; a normal differential detection scheme with I and Qbinary decisions was implemented to recover the data from the signal once the sampling instant7. We note here that the ML DA decision device may be quite sophisticated, and employ techniques such as Viterbi decoding to better the symbol estimates.66Chapter 4: Computer Simulation of Symbol Synchronization in CCIwas known.The PLL loop filter (see Figure 5) was a simple one-pole low-pass filter transformed to thediscrete domain via bilinear transform [55], found through an iterative process to have 3 dB cutofffrequency at .o=itI3. This provided less than 0.O1T RMS timing jitter at high SNR, while stillexhibiting measurable self-noise in the absence of interference or noise so simulation results couldbe compared to theoretical results.The synchronizer parameters were arrived at by an iterative design process, whose goalwas a small hut measurable timing jitter at high SNR, and an approximate acquisition time of 100symbols or less. The number controlled counter constant was KNCc=O.6O, the resultant dampingfactor of the equivalent second order PLL was =1.65, an overdamped system, and the equivalentnoise bandwidth was evaluated to be 2BLT=0.008. These values were calculated for the equivalentanalog PLL transfer function.Figure 21 to Figure 23 illustrate the simulation results for the three modulation schemesunder consideration. As Eq. 3.18 suggests, performance does not depend upon the number of interferers, M, present. As predicted by analysis, the performance of the QPSK and it/4—shift DQPSKschemes are comparable. RMS jitter at high SNR differs by only about 4% between the two simulation results, well within experimental error. Both modulation schemes exhibited about 15% errorin the absence of CCI at high SNR compared to the analytical results. This is due to error in calculating PLL linear transfer function, which resulted in an error in both the PLL equivalent noisebandwidth, as well as the damping ratio . This error drops to less than about 10% for CII=lOdBand high SNR, where the CCI dependent jitter term dominates. The use of an 8—PSK decisiondevice in place of the ideal it/4—shift DQPSK decision device does not cause appreciable degrada67Chapter 4: Computer Simulation of Symbol Synchronization in CCItion in timing jitter at low SNR, compared with the QPSK case.P-eF‘-‘‘*,‘ Au—k‘- -= 10 C—IV3]I/1-pA=14— ... .... .... .... ....- — ....— — — —- Th_-_— — —— —— — —— — —— —— = =— -- —— No lntetferen —JML DA QPSK SimuIatioTheory—j C’ Simulation, M 0A Simulation, M = 1D Simulation, M..-5 0 5 10 15 20 25 30 35 40 45 50SNR [dB]11AFigure 21: Simulation results for ML DA QPSK scheme: NormalizedRMS timing jitter vs. SNR, 2BLT=0.008, a=0.35, and 128 samples!symbol.10•1o2io68Chapter 4: Computer Simulation of Symbol Synchronization in CC!IVFigure 22: Simulation results for ML DA irJ4—shift DQPSK scheme:Normalized RMS timing jitter vs. SNR, 2BLT=0.008, a.=0.35, and 128samples/symbol.The ML DA scheme does not exhibit worse perfonuance for the M= 1 case employingQPSK or it/4—shift DQPSK, as was found for the ML NDA simulations. This is because the multiplication of the signal by the estimated symbol instead of squaring cancels the cyclostationarynature of the CCI terms.-110‘,-,‘‘w-‘I I JIcoJ-,‘I!t. ..,, ,.., ,... ,.. ..., ..,.— ———-— —— - -——1E =, No lnterteref..JML DA pi/4-shift DQPSK — — — — —TheorySimulation, MO — — — — —Simulation, M=1Simulation, M -..., ..,. .,.. .,,.J-,‘4= I--JA //--F-310-5 0 5 10 15 20 25 30 35 40 45 50SNR [dBJ69Chapter 4: Computer Simulation of Symbol Synchronization in CC!. ... .....0ci ci+DOdB]:: FZLh——--——--—— ——=—1-— —C414.rML DA 16-QAM Simulations — — — —Theory0 Simulation, M = 0 — — — —Simulation, M 1C Simulation, M,,,.,,,,,,,,.,, .,.. ...,Figure 23: Simulation results for ML DA 16—QAM scheme: NormalizedRMS timing jitter vs. SNR,2BLT=0.OOB, cx=0.35, and 128 samples!symbol.The simulated performance of the ML DA synchronizer for 16—QAM modulation performs about 30% worse than the predicted performance with no interference, and twice as poorlyin the worst case, with CII = 10 dB, and M —* oo. Comparing the theoretical results with the equivalent computer simulated results, it appears that the ML DA synchmnization technique is moresensitive to the signal amplitude changes. However, the ML DA simulated results, even in theworst case, are better than the equivalent results of the ML NDA simulations, which even had asmaller equivalent noise bandwidth.101c.’ -21o-5 0 5 10 15 20 25 30 35 40 45 50SNR [dB]70Chapter 4: Computer Simulation of Symbol Synchronization in CC!For 16—QAM the M=l and M — oo simulations do exhibit significant difference in timingjitter for the C/I = 10 dB case. If the BER of the CII = 10 dB case is examined with ideal timingrecovery, an error floor due to CCI is observed at BER = 1.9x102for M=1, and BER=7.3x102forM —* . Obviously, the large increase in the number of decision errors for this extreme amount ofinterference causes the discrepancy in jitter performance, since decision errors in the ML DA synchronizers will degrade tracking performance. The results may be made worse by nonlinear effectsat high (e.g. > 0.027) jitter.Table 4 illustrates the difference between theory and simulation results for a range ofraised-cosine filter excess bandwidth a for the QPSK modulation scheme, with no noise presentand C/I = 10 dB. As seen in the NDA simulations, the simulated results are approximately 10%worse than theory predicts over the range of a, hut the amount of error increases for small a. Theerror over most of the range can be explained by simulation error due to discrete time (see Appendix B for details).Table 4: Simulation Enor vs. excess bandwidth. ML DA synchronization, forQPSK modulation, C/!= 10 dB, M —* oc, 2BLT=O.008. and no noise.Excess Bandwidth RMS Jitter Simulationa Error(%)0.10 28.25%0.20 11.6%0.35 9.2%0.50 9.9%0.90 10.4%As was the case with the ML NDA simulation results, the analysis of Chapter 3 correctlypredicted the results found in the simulation of the ML DA scheme. Once again, the linear assump71Chapter 4: Computer Simulation of Symbol Synchronization in CC!tion of PLL theory leads to underestimation of symbol timing jitter at higher jitter values. Despitethe ML DA synchronizer simulated having an equivalent noise bandwidth 20% lalEer than the MLNDA synchronizer simulated, the ML DA synchronizer exhibited better performance in all cases,although it is susceptible to decision errors since it incorporates them into the tracking loop. Consequently, where the BER is large (for example, BER> 2x10 in the 16-QAM simulation), decision errors will increase the timing jitter of the recovery scheme.4.5 ML Block Synchronizer Simulation ResultsThe block synchronizer was implemented in simulation directly from the description inSection 2.4.3 for it/4—shift DQPSK. Since the ideal sampling instant occurs exactly halfwaybetween two samples in the simulation, the worst-case time quantization error was be measured inthe simulation rather than the average time quantization error. That is, as explained in Section 3.5,in a real system the receiver’s symbol rate clock would not be perfect, so the error in selecting asampling instant, for negligible timing jitter, would he due to sampling error, and would be uniformly distributed over the time between sampling instants. However, in the simulations performed, the ideal sampling rate falls directly between two samples, and the error is that of theworst-case time-quantization. For a simulation of 16 samples/symbol, which was chosen as a realistic sampling rate (see Section 3.5), this corresponds to a minimum measurable RMS timing jitterof 0.03 125TIt is seen in the simulation results in Figure 24 that the pattern-dependent jitter term isbelow the minimum measurable jitter, and therefore the chief limit to performance at high SNR(i.e., 10 dB) is the sampling rate at the input. As can he seen, the use of a 32—symbol block reducesjitter performance by about 3 dB at a normalized RMS timing jitter of 5x1(T2.The effects of CCI72Chapter 4: Computer Simulation of Symbol Synchronization in CCIare negligible, except for the combination of a 32—symbol block and C/I = 10 dB, where CCIdegrades the jitter to less than 5% above the worst-case time-quantization jittez At higher levels ofCCI, the CCI term will begin to dominate at high SNR. However, for C/I = 10 dB, the BER isabout 5.3x10 for ic/4-shift DQPSK (as shown in Figure 25), which would indicate barely marginal performance for most wireless telecommunications applications.— ...,ML Differential Symbol Block SynchronizerSimulations for I4-shth DQPSKMinimum measured jther, 16 sps• —0—-—-— block length = 32, No Interference,.- - - -- block length = 32, Cii = 10 dB, M—block length = 64, No Interference\ z ock length=6CA0dMEZ H-Z- .... .... ... ..0 5 10 15 20 25 30 35 40 45SNR [dB]Figure 24: ML Differential Symbol Block Synchronizer for it/4—shiftDQPSK: Comparison of 32 and 64 block length synchronizers in CCI,cx=O.35, and 16 samples per symbol.v -11oFC.’)1 o-2-5The simulations used 16 samples per symbol, which yielded an RMS symbol timing jitterof 0.031 25T at high SNR. Use of a smaller number of samples per symbol would increase the sym73Chapter 4: Computer Simulation of Symbol Synchronizaüon in CCIbol timing jitter at high SNR to a level which would continue to dominate over the additional jittercaused by CCI.Figure 25: Bit error rate performance for block synchronizer and it/4—shift DQPSK modulation scheme, cx=O.35 and 16 samples/symbol.Comparison with Figure 15 shows that the block synchronizer using differential symbolsis less than 1 dB in timing jitter performance from the lower bound for no CCI at a timing jitter ofO.05T. Therefore the use of differential detection for ML block symbol synchronization does notsignificantly degrade performance in AWGN. The technique loses about 3dB in timing jitter perfomiance due to CCI at an RMS timing jitter of O.05T over the lower bound for the non-differen101>10-21oSimulated Bit Error Rate‘c — — Performance for 1t14-shiftDQPSK with Block Synch.Ideal timingBlock length 32—Block length 64lssamplespersymbolE-EEEEEE... ... ... ....... .... ....‘‘\—4) ‘1 c-Tee1’ \1=10 dB, M-5 0 5 10 15 20 25 30 35 40SNR [dB}74Chapter 4: Computer Simulation of Symbol Synchronization in CCItial block synchronizer for both the 32 and 64 block size cases, where only 1 dB or less waspredicted. This deviation at higher jitter is likely due to the same non-linearity exhibited in the MLDA case, which yielded a quite similar expression for symbol timing jitter, and was seen to underestimate the jitter when it was at this level.Figure 25 illustrates a typical BER curve for the block synchronizer. It was included sincethe jitter here is larger than for the DA or NDA simulations. As can be seen, the simulated BERcurve and ideal BER curve are essentially coincident over a wide range of SNR. The normalizedRMS timing jitter for high SNR is 0.03 125T, which has negligible effect on the measured BERdown to 10. The curve is included as the worst-case BER performance simulated for it/4—shiftDQPSK, with C/I = 10 dB. The error floor here is due to the presence of CCI. However, decisionerrors due to timing jitter are negligible, so the interference effect on the decision device is the limiting factor, not the interference effect on the symbol timing recovery system.4.6 SummaryThis chapter has presented computer simulation of the ML NDA and DA tracking loops,and the ML block synchronizer, employing QPSK. t/4-shift DQPSK, and 16-QAM modulation ina combined AWGN and static CCI channel. The simulation results are compared, for various numbers of interferers at C/I levels up to 10 dB, with the analytical results for RMS timing jitterderived in Chapter 3. From the obtained results, it is observed that the computer simulations validate the analytically derived theoretical results, except where the linear assumption is no longervalid for jitter values above about 0.02T in the cases simulated, where the analysis underestimatesthe simulation performance. This effect was also observed in [221 for the AWGN channel.For the ML NDA case, timing jitter performance is worse for a single interferer than for75Chapter 4: Computer Simulation of Symbol Synchronization in CC!larger numbers of interferers. This is not predicted by the analytical results of Chapter 3, and is dueto nonlinear performance of the synchronizer. The analytical results derived for symbol timing jitter in Chapter 3 assume the synchronizer has small jitter, and allows it to remain operation in thelinear PLL region. For the case of ML NDA synchronization with one interferer, the disturbance tothe timing wave has a larger amplitude, and forces the PLL out of the linear region. However, forlarger numbers of interferers, the simulations differed by less than 10% from the analytical RMStiming jitter results at high SNR, with C/I up to 10 dB.The ML DA scheme was found to he independent of the number of co-channel interfererspresent as predicted by analysis. The simulations for jitter performance are in good agreement withequivalent analytical results at high SNR, with errors of 15% or less at C/I up to 10 dB. However,the case of 16-QAM modulation differed by about 30% from predicted with no CCI present at highSNR. This is believed due to the amplitude variations of the signal’s bit-energy, which are notaccounted for in the analysis, and are not present in QPSK and ir/4-shift DQPSK cases simulated.It should be noted that the ML DA synchronizer simulated exhibited better performance than theML NDA synchronizer simulated, despite having a 20% larger equivalent noise bandwidth. Forthe case of 16-QAM modulation at C/I = 10 dB, it was observed that the ML DA synchronizertechnique exhibited twice the symbol timing jitter predicted at high SNR with M —* oo• This is dueto the ML DA technique using a decision device, which is susceptible to the extreme BER performance due to the high level of CCI present.The ML block synchronizer simulations showed that at a sampling rate of 161T and blocklengths of 32 symbols or more, the amount of additional symbol timing jitter due to CCI at levelsof up to C/I= 10 dB is not significant compared to the worst-case sampling error of time-granularitydue to the sampling rate.76Chapter 4: Computer Simulation of Symbol Synchronization in CC!Finaily. BER computer simulated results were examined. For C/I levels of up to 10 cIB, thesimulated results indicate that none of the syichronization schemes has a significant effect on theBER performance for either of the three modulation schemes examined. In all cases simulated, thedegradation of BER performance due to symbol synchronization was negligible compared to thecase of ideal symbol timing recovery.77ChapterS: Symbol Synchronization in Multipath Fast Fading Channels5 Symbol Synchronization in Multipath FastFading Channels5.1 IntroductionOne source of serious degradation in system performance for mobile wireless digital transmission is due to multipath fading. Fading introduces an irreducible error-rate in reception, due tothe random-FM modulation effect [3]. The effects of frequency non-selective (flat) and frequencyselective multipath fading on system performance have been studied extensively (see for example[31, [13], [14], [64], [65]). However, in the open technical literature, the problem of symbol synchronizer performance in fading channels has not received as much attention.A Ml. synchronization structure has been proposed for scattering channels which encompasses a whole range of frequency selective and non-selective fading channels [32], [33]. This synchronizer is a tracking loop which attempts to locate the peak received signal energy of eachsymbol in time and frequency, and use this as the optimum synchronization instant. However, thescheme utilizes information about channel characteristics in the form of the scattering channelautocorrelation function. The method’s computational complexity and reliance on channel information makes it an unlikely choice for implementation. Also, its symbol timing jitter and BER perfonnance are not predicted, so designers cannot accurately predict system performance for thistechnique.In [26] a complete synchronization system including symbol timing and carrier phaserecovery as well as carrier frequency offset estimation was implemented and tested via computersimulation and hardware measurement. The synchronizer operates on the same principles as the78Chapter 5: Symbol Synchronization in Multipath Fast Fading Channelsblock synchronizer previously described (see Section 2.4.3), using differential symbols for estimation of a QPSK modulated signal, performing all metric calculations with sampled phases. Thesystem has been tested to good result in a two-ray frequency selective fading channel, with datarate of 455 kBaud and with diversity selection included in the synchronization algorithm.In [61], the effect of multipath delay spread on a ML NDA symbol synchronizer wasexamined. It was found that an ‘infinitely fast’ timing loop, does not significantly improve BERperformance at high SNR, providing the separation of the equal-amplitude two-ray model is lessthan O.2T In this case, the cause of irreducible BER is due to eye closure caused by fading, and notby imperfect symbol synchronization. However, it should be pointed out that performance of thesynchronizer was restricted to hinary-PSK (BPSK), and delay spreads of less than O.2T Furthermore, in [61] the analysis assumes that delay spread is small compared to the symbol period, and isnot extrapolated to larger delay spreads. Furthermore, it is important to note that the performanceof DA and NDA tracking loops in flat fading channels have not been examined in the open technical literature over a wide range of BFT products. A significant advantage of these schemes is thatthey are simple to implement and their performance is well understood for AWGN channels. Thequestion examined in this chapter is how these schemes perform in frequency non-selective andfrequency selective fading channels, and whether more complex schemes are necessary in suchchannel conditions. To this end, this chapter examines the effect of frequency non-selective andselective fading on the ML NDA, ML DA, and ML block synchronizers through a simulationstudy using itI4-shift DQPSK modulation.This chapter is organized as follows: Section 5.2 introduces both frequency non-selective(flat) and frequency selective fading models used in the computer simulations to be performed.The results of those simulations are discussed in Section 5.3 for both types of fading, using ir/4-79ChapterS: Symbol Synchronization in Multipath Fast Fading Channelsshift DQPSK as the modulation scheme for simulation. Finally, a summary of the chapter and itsconclusions are provided in Section 5.4.5.2 Fading Models5.2.1 Frequency Non-Selective (Flat) Fading Model DescriptionFrequency non-selective fading, or flat fading, is a model of the effect on a received signaldue to motion of the receiver. A signal received at a mobile receiver is a summation of reflectionsfrom many different scatterers in the surrounding terrain. Each signal arriving at a different anglewill suffer from a frequency shift due to the Doppler effect [3]. The effect of this frequency shifton the summation of signals from all directions results in a fading process known as frequencynon-selective fading [3], [14].Frequency non-selective fading can be modeled mathematically by the complex fadingprocess [13]:f(t) =f1(i) +JJQ(t) (EQ.5.1)wheref1(t) andfQ(t) are the in-phase and quadrature Gaussian random processes, respectively. Thefading process is a multiplicative interference, with the received signal expressed, in the absenceof AWGN, as [31:r(t) =f(t)s(t) (Eq.5.2)Such a representation may represent either Rayleigh (for which E [J (t)] = E [fQ (t)] = 0 ) orRicean (for which E [J, (t)] 0, E [fQ (t)] = 0 ) frequency nonselective (flat) fading, since thefading amplitude will follow either a Rayleigh or Ricean distribution.Figure 26 illustrates the generation of the fading process for simulation. The in-phase and80ChapterS: Symbol Synchronization in Multipath Fast Fading Channelsquadrature functions are generated as white Gaussian noise, and then filtered by the fading filter,H/f). The characteristics of the fading process are controlled by the PSD of the fading process. Inthis thesis, the land-mobile fading model is used, so that [3]:I [j1c/JHf(f) = q V c (Eq. 5.3)1 o j9>FFigure 26: Block diagram of fading process generation for simulation.Although the magnitude of H/f) can approach infinity for f—* F, in the simulation themagnitude of H/f) is limited to 30 dB. The one-sided fading bandwidth, F is simply half of thedouble-sided fading bandwidth, BF. The level of fading is usually expressed as the product of fading bandwidth to symbol period, BFT The fading filter of Eq. 5.3 has been shown to closely modelRayleigh land-mobile fading processes [14], [56].For generation of Ricean fading, the signal is Rayleigh fading as above, and added to anunfaded version of the signal, whose amplitude can expressed as a power ratio of faded to unfadedsignals in dB:E[f(t)J2K= lOlog10 2 2 (Eq.5.4))where and are the variances of the in-phase and quadrature fading processes.f(t)realI-channelzz. complex0-channejn/2e81ChapterS: Symbol Synchronization in Multipath Fast Fading ChannelsThe simulation results presented are limited to BFT> 0.003, due to the frequency resolution needed to represent the land-mobile fading process in a frequency array. This limits the discussion to the ca.se of fast fading processes.5.2.2 Frequency Selective Fading Mode! DescriptionThe Rayleigh and Ricean fading processes model the arrival of scattered signals to amobile receiver. Each signal follows a path from transmitter to receiver of different length and maycombine to creare a composite signal which suffers time dispersion. While Rayleigh fading modelsa spreading in frequency due to the Doppler effect, time dispersion also models a spreading in timedue to different path lengths [13]. It is known as frequency selective fading since different parts ofthe signal spectrum may be affected in different ways. Time dispersion causes a time-varyingchannel impulse response which spreads the received signal energy over a finite time interval, usually denoted the channel time-spread, td [14]. Measurements of such channels in an urban envimnment show that most of the received energy fmm a transmitted signal is concentrated at onlyseveral distinct times, due to reflections from larger terrain features [17]. A simple way to modelsuch a channel is to reduce the time-spread to a second signal path, Rayleigh faded with a fadingprocess statistically independent from the original signal’s fading process, with an additional timedelay, td. The model for such a channel is shown in Figure 27, where the fading processes are generated as explained in Section 5.2.1.Measurements of such time-spreads for an urban environment give values of td in therange of 1-20 l.tsec [15], [16], [17], [66], which is up to 1/2 of a symbol period for a data rate of 24kEaud. For a mobile receiver, the time-spread of the channel will be changing as the receivermoves through the environment. The two-ray model above portrays the case where the time-82Chapter 5: Symbol Synchronization in Multipath Fast Fading Channelsspread changes slowly within the timeframe of the simulation. It should be noted, however, thatthe two-ray model is recommended by the Telecommunications Industry Association (TIA) Standards Committee for evaluation of system tolerance to delay-spread [57].Due to the severe degradation in system performance attributable to frequency-selectivefading. methods to counteract it, including time-varying adaptive equalization have been developed (see for example [58]). For the purpose of this thesis, however, it is assumed that no equalization is present.Frequency SelectiveFaded Signals(t)Figure 27: Block diagram of generation of a frequency-selective fadedsignal for simulation.5.3 Simulation Results and Discussion5.3.1 Fast Frequency Non-Selective FadingThe introduction of a frequency non-selective (flat) fast fading process to the channel has adeleterious effect on system performance, due to the random FM interference of the fading process[3], [13]. As seen previously in Section 2.2, the received signal must be cyclostationary in order83ChapterS: Symbol Synchronization in Multipath Fast Fading Channelsfor timing recovery to take place. The received signal, along with its mean and autocorrelationfunction may he expressed as:r(t) =f(r) ckh (t—kT)A:E[r(t)] E[f(t)1E[ckih(tkT) (Eq.5.5)A:E[r2(t)j= E[f(t)1 E[ck]h2(r— T)where the information sequence {ck} is assumed statistically independent. Clearly from the aboveequation, the received signal remains a cyclostarionary process in the presence of Rayleigh orRicean fading, so symbol timing recovery is still a possibility.If the fading process is treated as a modulating waveform, the ML function may still beexpressed as in Eq. 2.7, where the estimated sequence, {ck} is now replaced by the total modulation, or:=cJ(kr) (Eq. 5.6)which is an estimate of the fading random FM as well as the symbol. The ML DA and ML blocksynchronizers will use this estimate over the entire symbol period, so it is important that the fadingdoes not change substantially over a symbol period. Since removal of this modulation term is theaim of the symbol synchronizer, it appears that symbol synchronization may work well in fadingenvironments where the fading is correlated over several symbol periods.Computer simulations were performed using the it/4—shift DQPSK modulation scheme,with raised-cosine Nyquist pulse-shaping, and an excess bandwidth of oO.35, which is the specification of the North American TDMA digital cellular standard [6]. The simulation used a sampling rate off5=64/T for the ML DA and ML NDA synchronizers, andf3=16/T for the ML block84Chapter 5: Symbol Synchronization in Multipath Fast Fading Channelssynchronizer, which utilized a block-length of K=64. Approximately 200 kbits were simulated foreach value attained, averaged over 6 simulations each for the tracking loops, and approximately500 khits, over 4 simulations, for the block synchronizer. all with the same parameters as describedin Section 4.2. For comparison, the performance with ideal symbol timing was approximatedthrough simulation with 64 samples/symbol, which results in negligible degradation in performance from the actual ideal sampling case.The tracking loop synchronizers were given a wide margin of 400 symbols in order toachieve timing acquisition, since the timing acquisition in worst-case simulations was observed toincrease by as much as 100% compared to the no-noise case, due to the added interference. Thispoints out the great advantage of the ML block synchronizer, which requires no acquisition periodand may be used with much more confidence in extreme failing conditions without concern forloss of tracking.Figure 28 shows the timing jitter error floor, or the irreducible symbol timing jitter performance over a range of BFT products. These simulations were performed with no AWGN present toexamine the lower limit on performance caused by fading. A number of observations and conclusions may he made from these results:1) Performance is similar for all synchronizers over a wide range of BpT products. ForBFT < 0.10, the RMS timing jitter is below 3.5% of a period, which is a severe fadingenvironment. This corresponds to a mobile cellular user travelling at 100 km/hr, transmitting on a carrier frequency of 850 MHz, with a data rate of less than 1500 Baud.Since the North American digital cellular system operate at 24 kBaud, at a frequencyabout 850 MHz, the most severe fading expected in such a communication system85ChapterS: Symbol Synchronization in Multipath Fast Fading Channelsshould be BFT < 0.004 for operation from an automobile.0.0350.030.025V0.02V0.0150.01B,T ProductFigure 28: Symbol timing recovery performance in frequency non-selective Rayleigh and Ricean fading for the 3 synchronization schemes,no noise.2) The Ml. DA synchronizer outperforms the ML NDA synchronizer for this range offading, as was the case in AWGN and CCI environments.3) The ML block synchronizer performance is limited by the sampling rate of thereceiver, not by the fading in this range of BFT products. The timing offset of 3.125%of 7’, which is inherent in a block synchronizer with practical sampling rate of 16,7 is0.0450.04Irreducible Jitter vs. BT Fading ProductML NDA, Rayleigh FadingML DA, Rayleigh FadingML NDA, Ricean Fading, Kf —3dB• ML DA, Ricean Fading, K=3dBML NDA, Ricean Fading, K,=1O dlA ML DA, Ricean Fading,1=lOdB —0 ML NDA, Ricean Fading, K2OdB• MLDA, Ricean Fadin =20dB- -• H —.# —. — - - gl’::i[,ock Synchronizer, 1 6sI ii—--‘ / t— — — ———— 71.‘‘ ... r’——:. -—M4I uI lI1 P.. ...—“.— , — . - — — — I0.0050.001 0.01 0.186ChapterS: Symbol Synchronization in Multipath Fast Fading Channelsdue to the ideal sampling instant falling halfway between samples in the simulation.4) The tracking loops begin to fail for BFT < 0.1. the ML NDA scheme showing a fasterdegradation as the fading is increased than the ML DA scheme. If the fading process isapproximated as having a rectangular PSD, for BFT = 0.1 the fading process is correlated over approximately only 20 symbols (since the autocorrelation is a sin(x)/x function, and its main-lobe extends over 20 symbol periods). With the fading processchanging this rapidly, the ML DA and NDA loops can no longer track the fadingchanges.5) Performance in Ricean fading with Kf> 20 dB is not substantially worse than theresults without fading, since the line-of-sight unfaded signal dominates (i.e., it is morethan 100 times stronger than the faded signal). Because of this, the pattern dependentjitter term dominates jitter performance with no noise present. Performance degradesas Kf is reduced, until the signal is essentially Rayleigh faded. For Rayleigh fading,timing jitter increases about 60% over the no fading case.The BER performance measured through simulation is presented in Figure 29. As can beseen, the jitter performance in fading leads to no measurable degradation in BER performanceover ideal sampling. It should he noted that the simulation results are for the case where noise isabsent, and only reflects the irreducible BER. In the absence of noise, irreducible errors due to eyeclosure from fading are not made any worse due to sampling error.From the results of this section, it is apparent that while frequency non-selective fadingcauses a serious degradation of system BER performance, its effect on symbol timing jitter is notsignificant at high SNR for most normally encountered frequency non-selective fading conditions87ChapterS: Symbol Synchronization in Multipath Fast Fading Channels(i.e., Rayleigh or Ricean fading with BpT < 0.1). Although symbol timing acquisition time is notthe focus of this thesis, it should be noted that acquisition time for the ML NDA and ML DA synchronizers in the simulations performed were significantly affected by the introduction of frequency non-selective fading, with specific observed cases exhibiting twice the acquisition timeover the no-fading case. This may warrant use of the ?1L block synchronizer in such a situation,since the algorithm does not require acquisition time as it is normally defined for tracking loops.VC)-e0.10.010.0010.0001Figure 29: Irreduciblelrreducible BER for fast flat fading channel, nonoise.B Product88Chapter 5: Symbol Synchronization in Multipath Fast Fading Channels5.3.2 Fast Frequency Selective FadingFrequency selective fading creates a much more severe form of degradation than non-selective fading since it spreads the received energy over time. While random FM modulation of asignal by Rayleigh or Ricean fading maintains the cyclostationary characteristics of the signal, frequency selective fading creates a spread signal which will cause much more uncertainty in the estimation of the correct sampling instant.Due to time dispersion the ideal sampling instant is no longer necessarily at T12 in eachsymbol period for the matched-filtered signal. In frequency selective fading the ideal samplinginstant is that which maximizes the SNR for each symbol [321. This corresponds to the time instantwhere received energy peaks in each symbol interval. For instance, for a two-ray model with eachray of equal power and td<T12 the ideal sampling instant will occur at td/2, which is the time-average of the received power at each symbol. For low levels of fading such as a second ray withamplitude of 10 dB below the signal of the first ray, or for small td, the ideal sampling offset fromthe ideal non-fading sampling instant will be smaller. However in severe fading conditions8,theoptimum sampling instant can vary significantly from the former ‘ideal’ instant.This is illustrated in Figure 30, where simulation results are shown for t/4—shift DQPSKmodulation with a0.35 for the two-ray frequency selective fading channel, with Rayleigh fadedrays (BFT=0.065). Two examples are shown, one with the delayed second ray of equal energy tothe main ray, and one with a delayed ray with half the power of the main ray (-3 dB), both delayedfrom the main ray by time offset ta=T/2. Shown for each example is the optimal sampling instant,where the peak signal energy occurs. As can be seen, this offset can be substantially different from8. For the 2-ray model, severe fading results when the second ray’s amplitude approaches or exceeds that of theprimary ray, and the delay spread is a significant portion of a symbol period.89Chapter 5: Symbol Synchronization in Multipath Fast Fading Channelsthe ideal sampling instant for the no fading case. For example 25% of a symbol period in Figure30, and can lead to degradation of performance (up to 65% worse irreducible BER performance bysampling at the T12 sampling instant for the equal power rays in Figure 30).Figure 30: Irreducible BER vs. sampling time offset from T/2 samplinginstants for 7t/4—shift DQPSK with 2—ray frequency selective Rayleighfading model, with BFT=0.065.Computer simulations were used to evaluate the performance of the three synchronizationschemes in frequency selective fading, using the 2—ray channel spread model, and with AWGNabsent. The simulations used a sampling rate of f=64IT, and with the same nunther of symbols-cC)0.20.150.10.05Irreducible BER Performance vs. SamplingTime Offset for Severe Freq. Selective Fading—a——-- Second Ray 0dB, T12 Offset, td T/2—a---— Second Ray = -3dB, T12 Offset, ‘Ed = T/2NIPeak EnergyN!Peak Energ],I —0 0.1 0.2 0.3 0.4 0.5Sampling Offset[%of 1]90ChapterS: Symbol Synchronization in Multipath Fast Fadil7g Channelssimulated as for the flat fading case (see Section 5.3.1). Simulations withf=32IT were performedin order to evaluate the effects of sampling at the T/2 sampling instants, as well as at the optimalsampling instants, which were found for each td by the average of time offset, weighted by the relative powers of the two ray components. Figure 31 shows the irreducible BER performance of the3 synchronization schemes for second ray powers of -10 dB and -3 dB, as a function of the secondray time delay, td. As well, simulations were performed with sampling at T12 in each symbolperiod, as well as with optimal sampling, found by the time-average of eneIy arrival, weighted bythe power of the primary and secondary rays. Figure 32 illustrates the effect of a second ray ofequal power to the primary ray.In [61], it was found that a ML NDA synchronizer performed as well as an ideal synchronizer for rd<0.2T This is also observed here. In fact, performance of all three schemes is not significantly degraded from ideal performance for td < 0.5T until the second ray is at the same poweras the primary ray. In the case where the second ray is of the same amplitude as the first, the MLNDA technique begins to diverge significantly from ideal for td>O.2T, with irreducible BER performance about twice as bad as the optimum sampling case at td=T12. Except for the most extremecase, with equal amplitude rays, performance of the ML DA and ML block synchronizers track thecorrect sampling instant well, while the ML NDA synchronizer does not adjust as well to the frequency selective environment.91ChapterS: Symbol Synchronization in Multipath Fast Fading Channels0.1a)Ua)0.001Ray Delay tdFigure 31: Irreducible BER for 3 synchronizers in a frequency selectivefast fading channel (-10 dB and -3 dB rays), including the BER for T12sampling and for optimal sampling.Tracking of the optimal sampling instant is clearly shown in Figure 33, which plots thetiming offset from the T12 sampling instant for 256 blocks of 64 symbols with the ML block synchronizer. For the case of no interference, the synchronizer samples are close to zero offset (i.e. TI2). When the primary ray is Rayleigh faded and added to a secondary ray with offset td=O.43 andequal power, the average sampling instant is shifted towards the optimal sampling instant of t=T/2÷0.215T. However, as seen in Figure 32 the synchronizers’ performance begin to degrade for thecase of equal-magnitude second ray at a timing offset of td=T/2.92ChapterS: Symbol Synchronization in Multipath Fast Fading Channels0.1VV0.0010 0.4 0.5Ray Delay tdFigure 32: Irreducible BER for 3 synchronizers in a frequency selectivefast fading channel (-10 dB and 0 dB rays), including the BER for T12sampling and for optimal sampling.From the simulation results, it can be seen that even for the worst case condition, withrd=T/2, and equal amplitude rays, that the ML NDA technique increases the BER error floor byabout 100% over ideal sampling. The ML DA technique isicreases the BER error floor by about60%, and the ML block technique by about 50% over ideal sampling. For a second ray with amplitude 10 dB below the mam ray, the effect of any of the thie synchronization techniques is to raisethe error floor by less than 20%. It must be noted, however, that where the symbol synchronizationschemes are significantly worse that ideal sampling, the irreducible BER is already above 102.0.1 0.2 0.393Chapter 5: Symbol Synchronization in Multipath Fast Fading ChannelsTherefore, although a multipath environment can have a significant effect on the BER of a systemdue to non-ideal sampling at high SNR, system performance would already be marginal even withideal timing.Avg.OffsetITracking Performance of ML B’ock Synchronizer—16 samples/symbol. 64 symbol block lengthNo InterferenceIs. Fang, = 0.43, 0dB-0 50 100 150 200 250 300Block NumberFigure 33: Tracking performance of ML block synchronizer for it /4—shiftDQPSK modulation, without interference, and with frequency selectiveIn [32] and [33) a ML synchronizer was developed for a generalized frequency selectivefading channel. This synchronization structure, realizable as either a block synchronizer or a tracking loop, is a maximum likelihood estimator of the maximum energy location. However, its implementation requires information about channel characteristics, namely a filter whose impulse0.50.3750.25V0.1250VJ0.125-0.25-0.375fading.94ChapterS: Symbol Synchronization in Multipath Fast Fading Channelsresponse is the autocorrelation of the channel scattering function. Even provided that channel characteristics can be estimated, the best performance it can achieve is to improve irreducible BERperformance by up to 50% from the ML block synchronizer simulated at the worst conditionsexamined. Therefore for conditions where SNR is high, the added complexity of this scheme maynot he warranted unless multipath fading is severe.54 SummaryThis chapter has examined the performance of the ML NDA, DA, and block synchronizersfor the it/4—shift DQPSK modulation scheme in both frequency nonselective and frequency selective fast fading channels through computer simulation.Both Rayleigh and Ricean frequency non-selective fast fading were examined, with timing jitter measurements and BER performance provided. It was found that although frequencynonselective fading increases the RMS timing jitter of the synchronizers, all three synchronizerssimulated were able to match the irreducible BER performance of ideal sampling, over a widerange of fading with 0.003<BpT<0.2, for irreducible BER values of 10A and above. Symbol timing jitter performance was remarkably unchanged over a range of BFT, although it began todegrade more seriously for BFT.0. 1. Therefore, for conditions of high SNR in Rayleigh or Riceanconditions with BFT<0. 1, use of the non-ideal symbol synchronizers examined will not have a significant effect on the steady-state symbol timing jitter of a receiver.The effects of frequency selective fading were examined through computer simulationusing a vaiiable-magnitude two-ray channel impulse response model. It was found that all threesynchronizers operated well in most frequency selective fading environments simulated. As wasfound in [611, symbol timing jitter performance was near-ideal for td<O.2Tin all cases. However,95ChapterS: Symbol Synchronization in Multipath Fast Fading Channelsirreducible BER due to frequency selective fading was observed to increase as the amplitude of thesecond ray was increased, and as td increased. For the worst-case simulated, the irreducible BERwas doubled for the ML NDA scheme, was 60% worse for the ML DA scheme, and was about50% worse for the ML block synchronizer, compared with ideal sampling. However, by this point,the irreducible BER was greater than 102, even with ideal sampling, so system performancewould be marginal at best at this point.Unless the fading is severe, it was observed that for high SNR, BER performance wouldnot he seriously degraded using the three timing recovery schemes examined in Rayleigh fading ortwo-ray multipath fading environments, and more complex schemes created to improve symboltiming recovery performance in frequency-selective fading may not be warranted.96Chapter 6: Conclusions and Suggestions for Further Research6 Conclusions and Suggestions for FurtherResearch6.1 ConclusionsThis thesis examined the effects on three ML symbol timing recovery techniques of two ofthe most serious forms of signal degradation in digital wireless systems -- CCI and signal fading.The thesis concerns itself with symbol timing jitter and BER performance as the measures of system performance of three ML symbol synchronizers, NDA, DA, and block symbol synchronizers,for three quadrature modulation schemes, QPSK, it/4-shift DQPSK, and 16-QAM.For CCI, analysis was performed to determine expressions for steady-state symbol timingjitter for the ML NDA and ML DA cases, and a lower bounds for the ML block synchronizer,using linearized PLL analysis of the non-linear systems. Nyquist pulse shaping was assumed in anAWGN and CCI channel, and CCI was averaged over all possible timing offsets to give averageRMS timing jitter expressions. A series of computer simulations were performed to test the analytical results. Comparison was made for various numbers of interferers for each type of modulationscheme, using symbol synchronizers with realistic parameters. C/I levels of up to 10 dB were simulated, with comparison made to analytical results derived.Analytical results for the ML NDA synchronizer have shown that CCI is the chief limit toperformance at high SNR for systems with low pattern dependent jitter. CCI adds a constant termto the jitter variance, while the periodic components due to the cyclostationary nature of the CCIsignals were eliminated by averaging over all possible timing offsets. The jitter performance for allthree modulation schemes considered was similar and was found to be rather insensitive to the97Chapter 6: Conclusions and Suggestions for Further Researchactual number of co-channel interferers. The ML NDA simulations verified the analytical results,with a number of small deviations from theory. For a large number of interferers, analysis underestimated the simulation results by less than 10% at high SNR, with CII up to 10 dB. However, a single interferer exhibited worse performance, with errors of about 25% at high SNR and Cii = 10dB, for QPSK modulation. For 16-QAM modulation, the analysis underestimated results with alarger error of about 35% at high SNR and Cli = 10 dB, with only one interferer. The performancedegradation for the case where small numbers of co-channel interferers are present is due to nonlinearity in the PLL, which is not accounted for in the analysis and which is made worse at higherlevels of CCLThe ML DA and MIYIL DA analytical results also indicate that CCI is the chief limit totiming jitter performance at high SNR. As is the case for AWGN only, in a combined AWGN andCCI environment, the DA schemes outperform the NDA scheme, as was found in the cases evaluated in [31]. Analysis of the MML DA yielded about 30% better RMS timing jitter performance athigh SNR than the ML DA case, hut with reduced performance at low SNR. The jitter equationswere found to be independent of the number of interferers present in the environment, or thequadrature modulation technique used. It depended only on the Cli ratio and the pulse-shapingused. Additionally, the jitter was found to he the same for all of the modulation schemes considered. The computer simulations verified that the theoretical timing jitter performance of the MLDA synchronizer was independent of the number of co-channel interferers present, with errors of15% or less at CI! up to 10 dB at high SNR for QPSK and ic/4-DQPSK. In the case of 16-QAMmodulation, the performance between theoretical and computer simulated results differed by about30% with no CCI present at high SNR, due to amplitude variations in the signal constellation. 16-QAM also exhibited twice the symbol timing jitter predicted at high SNR with an infinite number98Chapter 6: Conclusions and Suggestions for Further Researchof interferers, due to the much larger BER of the 16-QAM modulation scheme for this case at CI!= 10dB.Analysis of the ML block synchronizer’s performance found that its lower-bound on performance in noise is identical to the performance of the ML DA scheme, ignoring the pattern-dependent jitter of the latter case, as was seen in [10] for the AWGN channel only. The analyticalresult for symbol timing jitter is a lower bound which does not take into account the sampling rateof the synchronizer. The sampling rate will set a lower limit to performance due to the algorithm’sdiscrete-time nature, for sampling rates less than 16/T. It was found that for C/I 10 dB and blocklengths of K 64, CCI was not a concern for the ML block synchronizer, since RMS timing jitterdue to CCI was less than the time-quantization error for a reasonable sampling rate of 16’T. TheML block synchronizer computer simulations verified that at a sampling rate of 161T and blocklengths of 32 symbols or more, the amount of additional symbol timing jitter due to CCI at levelsof up to C/I=lOdB is not significant compared to the worst-case sampling error due to time-quantization of the sampling rate used in the algorithm.For all three synchronization techniques, the analytical results underestimated timing jitterfor low SNR, where jitter is high. Similar behavior was reported in [22], for the AWGN channel.This discrepancy is due to the failure of the linear assumption used in analysis. For the ML NDAand DA analysis, the linear PLL model was used, while for the ML block synchronizer, a truncation of a Taylor’s series was used to linearize the analysis. The main constraint of the analysis ineach case is that the symbol timing jitter remain small, so that error in the analysis remains small.Therefore, as jitter increases at low SNR, or for cases of low C/I, the jitter will increase more thanpredicted by the analysis.99Chapter 6: Conclusions and Suggestionsfor Further ResearchIn both the ML NDA and ML DA cases, the only method for reducing CCI is by reducingthe loop bandwidth of the synchronizer, although may be undesirable due to increasing synchronizer acquisition time. In the case of the ML block synchronizer, increasing the length of each processed block will decrease the effect of CCI at high SNR, provided the sampling rate is highenough that it is not the major source of error. However, increasing the block length will increaseprocessing complexity. In all cases, with CCI levels up to C/1=lOdB, the effect of realistic symbolsynchronization was negligible on the system BER performance. For the worst case simulated,with C/I=lOdB, at high SNR the symbol timing jitter remained less than 3.5% of a symbol period.Therefore for worst-case levels of CCI which might be encountered in a frequency reuse system,the effect of CCI on the ML synchronizers examined will not degrade the system BER comparedto ideal sampling for the cases of QPSK, it/4-DQPSK, or 16-QAM. Nevertheless, the analyticalresults give important insight into the behaviour of the ML symbol synchronizers in a combinedCCI environment, and allow prediction of design performance, given some limitations due to thesmall-jitter linear assumption.Finally, this thesis has presented computer simulation studies of the performance of thethree previously mentioned symbol synchronization schemes in fading channels. Both frequencyflat and frequency selective (2-ray) Rayleigh and Ricean fading channels were considered, in conjunction with the it/4-shift DQPSK modulation scheme. Symbol timing jitter and irreducible BERperformance were the measures of performance used. The obtained results have indicated that.although frequency nonselective fading increases the RMS timing jitter of the synchronizers, allthree synchronizers simulated were able to match the irreducible BER performance of ideal sampling over a wide range of fading (O.O03<BFT<O.2),for irreducible BER values of 10 and above.100Chapter 6: Conclusions and Suggestions for Further ResearchSymbol timing jitter performance was remarkably unchanged over a range of BFT, although itbegan to degrade more seriously for BFT<0. 1. Therefore, for conditions of high SNR in Rayleighor Ricean conditions, use of a well designed Ml. symbol synchronizer as examined here will nothave a significant effect on the steady-state (phase locked) symbol timing jitter of a receiver. Also,it was found that all three synchronizers operated well in most frequency selective fading environments simulated. Similar to [61], symbol timing jitter performance was near-ideal fort1<zO.2T inall cases. However, irreducible BER due to frequency selective fading was observed to increase asthe amplitude of the second ray was increased, and as td increased. For the worst-case simulated,the irreducible BER was doubled for the ML NDA scheme, was about 60% worse for the ML DAscheme, and was about 50% worse for the ML block synchronizer, compared with ideal sampling.However, in this case the in-educible BER was greater than 10-2, even with ideal sampling. Therefore, system performance would be marginal at best in this instance. Because of this result, morecomplex schemes, such as proposed m [331, may not warrant the added complexity in symbol timing recovery algorithm, unless frequency selective fading is severe.6.2 Suggestions for Further Research6.2.1 Effects of CCI and multipath fading on tracking loop acquisitiontime and cycle slippingThis thesis has examined the steady-state performance of the three symbol timing recovery techniques. In order to use the ML NDA or ML DA symbol synchmnizers examined in aTDMA system, it is necessary to ensure that timing acquisition will always be possible within eachtimeslot. To ensure this, the acquisition time problem should be studied in greater depth [7]. Aswell, cycle slipping was observed in simulations of frequency selective fading at high fading rates.101Chapter 6: Conclusions and Suggestions for Further ResearchThis phenomenon should also he examined in greater detail.6.2.2 Performance of fast acquisition digital tracking loops in fadingand CCIThe tracking loops examined have some limited application in a TDMA network due totheir strict requirements on clock frequency and carrier phase acquisition. This may be overcomeby the use of digital phase-lock loops designed for fast frequency and phase acquisition (see forexample [60]). It would he interesting to extend the work of this thesis to study these schemes forsymbol synchronization in TDMA systems in CCI and fading channels.6.2.3 Effects of slow fading on system performanceDue to limitations of the computer simulations, this thesis only reports on the case of fastfading. Therefore, individual signal fades are of relatively short duration. It is believed that the MLNDA and DA symbol tracking loop performance may serious degrade if the length of deep fades issignificant compared to lI(2BLT). It appears interesting, therefore, to investigate this problem further.102BibliographyBibliography[1] T. S. Rappaport, “The Wireless Revolution”, iEEE Comm. Magazine, pp. 52, 61-71, Nov.1991.[2] D. J. Goodman, “Trends in Cellular and Cordless Communications,. IEEE Comm. Magazine, pp. 31-40, June 1991.[3] W. C.-Y. Lee, Mobile Cellular Telecommunication Systems. New York, N.Y. McGraw-Hill, 1989.[41 Cellular Digital Packer Data System Specification, Release 1.0. Vol. I - V, AmeritechMobile Communications, Bell Atlantic Mobile Systems, et. al. July 19, 1993.[51 A. D. Kucar, “Mobile Radio: An Overview”, iEEE Comm. Magazine, pp. 72-85, Nov.1991.[6] K. Raith and J. Uddenfeldt, “Capacity of Digital Cellular TDMA Systems”, IEEE Trans.Veh. Techn., vol. VT-40, pp. 323-331 May 1991.[7] H. Meyr and G. Ascheid, Synchronization in Digital Communications: Vol 1 Phase-, Frequency-Locked Loops, and Amplitude Control. New York. N.Y., John Wiley and Sons,1990.[81 W. C. Lindsey. Synchronization Systems in Communication and Control. EnglewoodCliffs, N. J., Prentice Hall, 1972.[9] W. C. Lindsey and M. K. Simon, Phase-Locked Loops and Their Application. N. J., IEEEPress, 1978.[101 L. E. Franks, “Synchronization Subsystems: Analysis and Design”, in Digital Communications: Satellite/Earth Station Engineering. (K. Feher, ed.), ch 7, pp. 294-327, New York,N.Y., Prentice Hall, 1983.[11] L. E. Franks, “Carrier and Bit Synchronization in Data Communication -- A TutorialReview”, IEEE Trans. Commun., vol. COM-28, pp. 1107-112 1, Aug., 1980.[12] M. Moeneclaey, “Linear Phase-Locked Loop Theory for Cyclostationary Input Disturbances”, IEEE Trans. Commun., vol. COM-30, pp. 2253-2259, Oct. 1982.103Bibliography[13] J. 0. Proakis, Digital Communications. New York, N.Y., McGraw-Hill Book Co., 1989.[14] W. C. Jakes Jr., Microwave Mobile Communications. New York, N.Y., John Wiley andSons, 1974.[15] R. J. Bultitude, “A Comparison of Indoor Radio Propagation Characteristics at 910 MHzand 1.75 GHz”, J. Sd. Areas Commun., vol. JSAC-7, pp. 20-30, Jan. 1989.[161 T. S. Rappaport, “900-MHz Multipath Propagation Measurements for U.S. Digital Cellular Radiotelephone”, IEEE Trans. Veh. Techn., vol. VT-39, pp. 132-139, May 1990.[171 D. C. Cox and R. P. Leck, “Distributions of Multipath Delay Spread and Average ExcessDelay for 910 MHz Urban Mobile Radio Paths”, IEEE Trans. Ant. Prop., vol. AP-23, pp.206-213, March 1975.[18] D. D. Falconer, “Timing Jitter Effects on Digital Subscriber Loop Echo Cancellers: Part I -Analysis of the Effect”, IEEE Trans. Commun., vol. COM-33, pp. 826-832, Aug. 1985.[191 D. D. Falconer, “Timing Jitter Effects on Digital Subscriber Loop Echo Cancellers: Part II- Considerations for Squaring Loop Timing Recovery”, IEEE Trans. Commun., vol.COM-33, pp. 8 33-838, Aug. 1985.[20] M. Moeneclaey, “The Influence of Four T’pes of Symbol Synchronizers on the ErrorProbability of a PAM Receiver”, IEEE Trans. Commun., vol. COM-32, pp. 1186-1190,Oct. 1984.[211 D. Y. Kim and K. Feher, “New Carrier and Symbol Synchronization Techniques for Digital Mobile Systems”, Proc. of IEEE Veh, Techn. Conf, pp. 37 1-376, 1988.[22] M. Moeneclaey, “Two Maximum-Likelihood Symbol Synchronizers with Superior Tracking Performance”, IEEE Trans. Commun., vol. COM-32, pp. 1178-1185, Oct. 1984.[23] M. Moeneclaey, “A Comparison of Two Types of Symbol Synchronizers for Which Self-Noise is Absent”, IEEE Trans. Commun., vol. COM-31, pp. 329-334, Mac 1983.[24] M. Oerder and H. Meyr, “VLSI Implementation of Synchronization Algorithms in a 100Mbitlsec Digital Receiver”, Proc. of IEEE Global Telecommunications Conf, pp. 571-576, 1990.[25] N. R. Sollenberger and J. C. I. Chuang, “Low-Overhead Symbol ‘Timing and CanierRecovery for TDMA Portable Radio Systems”, IEEE Trans. Commun., vol. COM-38, pp.1886-1892, Oct. 1990.104Bibliography[261 J. C.-1. Chuang and N. R. Sollenberger, “Burst Coherent Demodulation with CombinedSymbol Timing, Frequency Offset Estimation, and Diversity Selection”, IEEE Trans.Commun., vol. COM-39, pp. 1157-1164, July 1991.[27] F. M. Gardner, ESA Report 6847/86INJJDG: Demodulator Reference Recoveiy Techniques Suitedfor Digital Implementation.. European Space Agency, 1988.[28] F. M. Gardner, ESA Report 802218811”IL/DG: Timing Adjustment via Interpolation in Digital Demodulators. European Space Agency, 1990.[29] J. Armstrong, “Symbol Synchronization Using Baud-Rate Sampling and Data-Sequence-Dependent Signal Processing”, IEEE Trans. Com,nun., vol. COM-39, pp. 127-132, Jan.1991.[30] E. Fogel and M. Gavish, “Performance Evaluation of Zero-Crossing-Based Bit Synchronizers”, IEEE Trans. Commun., vol. COM-37. pp. 663-665, June 1989.[31] J. B. Carruthers, D. D. Falconer, H. M. Sandier and L. Strawczynski, “Bit Synchronizationin the Presence of Co-Channel Interference”, Proc. Canadian Conf on Electrical andComputer Engineering, pp. 4.1.1-4.1.7, Sept. 1991.[32] S. 5. Soliman and R. A. Scholtz, “Synchronization Over Fading Dispersive Channels”,IEEE Trans. Commun., vol. COM-36, pp. 499-505, Apr. 1988.[33] S. S. Soliman, “Tracking Loop for Fading Dispersive Channels”, IEEE Trans. Commun.,vol. COM-38, pp. 292-299, Mar. 1990.[34] F. M. Gardner, Phase-Lock Techniques. New York, N.Y., John Wiley and Sons, 1979.[35] M. Moeneclaey, “The Influence of Phase-Dependent Loop Noise on the Cycle Slipping ofSymbol Synchronizers”, IEEE Trans. Commun., vol. COM-33, pp. 1234-1239, Dec. 1985.[36] M. Moeneclaey, “The Influence of Cycle Slipping on the Error Probability of a PAMReceiver”, IEEE Trans. Commun. ,vol. COM-35, pp. 96 1-968, Sept. 1987.[37] L. B. Franks and J. P. Bubrouski, “Statistical Properties of Timing Jitter in a PAM TimingRecovery Scheme”, IEEE Trans. Commun., vol. COM-22, pp. 913-920, July 1974.[381 W. A. Gardner and L. B. Franks, “Characterization of Cyclostationary Random SignalProcesses”, iEEE Trans. Info. Theoiy, vol. IT-2 1, pp. 4-14, Jan. 1975.[39] A. N. D’Andrea, U. Mengali and R. Reggiannini, “Carrier Phase and Clock Recovery for105BibliographyContinuous Phase Modulated Signals”, IEEE Trans. Commun., vol. COM-35, pp. 1095-1101, Oct. 1987.[40] F. Patenaude, J. H. Lodge and P. A. Galko, “Symbol Timing Tracking for ContinuousPhase Modulation over Fast Flat-Fading Channels”, IEEE Trans. Veh. Techn., vol. VT-40,pp. 6 15-626, Aug. 1991.[41] P. G. Ogmundson and P F. Driessen, “Zero-Crossing DPLL Bit Synchronizer with PatternJitter Correction”, IEEE Trans. Commun., vol. COM-39, pp. 603-6 11, Apr. 1991.[42] F. M. Gardner, “Self-Noise in Synchronizers”, IEEE Trans. Commun., vol. COM-28, pp.1159-1163, Aug. 1980.[431 M. H. Meyers and L. E. Franks, “Joint Carrier Phase and Symbol Timing Recovery forPAM Systems”, IEEE Trans. Commun., vol. COM-28, pp. 1121-1129, Aug. 1980.[44] M. Moeneclaey, “Comment on ‘Tracking Performance of the Filter and Square Bit Synchronizer’ “, IEEE Trans. Commun., vol. COM-30, pp. 407-410, Feb. 1982.[451 J. K. Holmes, “Tracking Performance of the Filter and Square Bit Synchronize?’, IEEETrans. Commun., vol. COM-28, pp. 1154-1158, Aug. 1980.[46] M. Moeneclaey, “A Class of Phase Detector Characteristics for Symbol SyncrhonizersYielding Unbiased Estimates”, IEEE Trans. Commun., vol. COM-31, pp. 1033-1036,Sept. 1983.[47] Y. Takasaki, “Optimum Pulse Shaping for Baseband Digital Transmission with Self-BitSynchronization”, IEEE Trans. Commun., vol. COM-28. pp. 1164-1172, Aug. 1980.[48] M. Moeneclaey, “The Optimum Closed-Loop Transfer Function of a Phase-Locked LoopUsed for Synchronization Purposes”, IEEE Trans. Commun., vol. COM-31, pp. 549-553,Apr. 1983.[49) S. Haykin, Digital Communications. New York, N. Y., John Wiley and Sons, 1988.[50] J. Goldman, “Multiple Error Performance of PSK Systems with Cochannel Interferenceand Noise”, IEEE Trans. Com,nun. Techn., vol. COM-19, pp. 420-430, Aug. 1971.[51] R. A. Coco, “Symbol Error Rate Curves for M-QAM Signals with Multiple Co-ChannelInterferers”, IEEE Trans. Commun., vol. COM-36, pp. 980-983, Aug. 1988.[52] M. Moeneclaey, “Timing Recovery in the Presence of a Residual Echo Signal”, IEEE106BibliographyTrans. Commun., vol. COM-35, pp. 830-833, Aug. 1987.[53] D. G. Messerschmitt, “A Tool for Structured Functional Simulation”, IEEE J. Se!. AreasCommun., vol. SAC-2, pp. 137-147, Jan. 1984.[54] M. C. Jeruchim, “Techniques for Estimating the Bit Error Rate in the Simulation of DigitalCommunication Systems”, IEEE J. Sel. Areas Commun., vol. SAC-2, 153-170, Jan. 1984.[55] A. V. Oppenheim and R. Schafer, Discrete Time Signal Processing. Prentice Hall, Engelwood Hills, N. 3., 1989.[56] D. P. Bouras, Optimal Decoding of PSK and QAM Signals in Frequency NonselectiveFading Channels, M.A.Sc. Thesis, The University of British Columbia, Sept. 1991.[57] “Dual-mode Subscriber Equipment Compatability Specification”, in EJAITIA Specification IS-54, EIAfTIA Project Number 2215, Jan. 1990.[58] G. D’Avia, “Fast Adaptive Equalizers for Narrow-Band TDMA Mobile Radio”, IEEETrans. Veh. Techn., vol. VT-40, pp. 392-404, May 1991.[59] K. Nemoto, T. Yamazato, 1. Sasase and S. Mon. “A Novel Detection Technique for CPMUsing Variable Mapping Method”, Proc. IEEE Pacific Rim Conf on Communications,Computers and Signal Processing, vol. 2, pp. 573-576, May 1993.[60] F. Sato, T. Saba, D. K. Park and S. Moni, “Digital Phase-Locked Loop with Wide Lock-inRange using Fractional Divider”, Proc. IEEE Pacific Rim Conf on Communications,Computers and Signal Processing, vol. 2, pp. 43 1-434, May 1993.[611 J. C.-I. Chuang, “The Effects of Multipath Delay Spread on Timing Recovery”, IEEETrans. Veh. Techn., vol. VT-35, pp. 135-140, Aug. 1987.[62] V. Prahhu, “Error Rate Consideration for Coherent Phase-Shift Systems With Co-ChannelInterference”, Bell Systems Technical Journal, vol. 48, pp. 743-767, May 1969.[63] D. P.-C. Wong and P. T. Mathiopoulos, “Nonmdundant Error Correction Analysis andEvaluation of Differentially Detected it/4-Shift DQPSK Systems in a Combined CCI andAWGN Environment”, IEEE Trans. Veh. Techn., vol. VT-41, pp. 35-48, Feb. 1992.[64] L. 3. Mason, “Error Probability Evaluation for Systems Employing Differential Detectionin a Ricean Fast Fading Environment and Gaussian Noise”, IEEE Trans. Comm., vol.COM-35, pp. 39-46, Jan. 1987.107Bibliography[65] D. Makrakis, P. T. Mathiopoulos, and D. P Bouras, “Optimal Decoding of Coded PSK andQAM signals in Correlated Fast Fading Channels and AWGN: A Combined Envelope,Multiple Differential, and Coherent Detection Approach”. IEEE Trans. Comm., vol COM42, pp. 6375, Jan. 1994.[66] H. Hishemi, “The Indoor Radio Propagation Channel”, IEEE Proceedings, vol. 81, pp.943-968, July 1993.108Appendix A.• Derivation of ML NDA Synchronizer Timing finer in CCIAppendix A: Derivation of ML NDA SynchronizerTiming Jitter in CCIThe effects of CCI on the NDA symbol synchronizer can be found by following themethod outlined in Section 2.4. 1. The method briefly, is to find an expression of v(t), the input tothe loop filter of the PLL, after matched-filtering, prefiltering and squaring the received waveform(see Figure 4). This is equivalent to the cyclostationary input noise term M(t) discussed in Section2.4.1. The two-dimensional autocorrelation function of this the cyclostationary noise term M(t)can then he found, and expressed in terms of a Fourier series representation, such that:2irRM (u, u + v) = Yk (v) exp (j7ku) (EQ. A.1)where:1T/2 2itYk (v) = f R (u, u + v) exp (_JTku) du. (EQ. A.2)—T/2The resultant power spectral density of the input waveform which contributes to the phase-jitter atthe output of the PLL may be expressed as:s (t) = [s0 (1÷ + S0 (f- - S2 (f+ exp (-2j0) - S (f- exp (210)] (EQ. A.3)where Sk(f)=FTV{yk(v)} and FT{.} represents the Fourier transform of the argument with respectto the time-variable v. The output timing jitter variance can then be expressed as:= (2B) St (0) (EQ. A.4)where P is the power of the mean signal component.Including AWGN and CCI with the transmitted signal, the result of this process yields twoterms, S1(J) due to the signal and AWGN and S,2(f) due to the addition of CCI. The terms are109Appendix A: Derivation of ML NDA Synchronizer Timing Jitter in CIfound to be:14S, 1(J) =—(a +a_3[(a2)2(a)J)Z0(f)fT+2[(a2)2+(G)1Zm(fZm(7+ (a2 + a) () RG (0) Z0 () ( +6- + () R (0)5 A.5)004 2 2) (N°) f G(s)J(s)SG(fs)ds5[n}+—(a +0TaN0 00+2(7) f SG(s)SG(f—s)dsS[njand:M1 4_3[(a2)2÷ (02)21)z0u)zc_.n] exp (i21t(W1/Tn)+0Ta b a 1=1MM2+ _[(a2)2+ (a)2] jz (—1)exp (j2ltnW1/flT a i1l=1m m—(—-——)1=1+(a2+a) () JG(s)G(-s)S(;f-s)dsexpU2(,/fln) (EQ.A.6)1=1MM1 n-mV+—(oa+ exp (j2it(W—W)m/T)exp (j2irn)T m i=11=1M r j21cW j2lcNJ,1Tm)+exp(T(n_rn))]+mM4+ (a2o÷aa) Zm_W/T(J)Zm_V/T(_f)m110Appendix A: Derivation ofML NDA Synchronizer Timing Jitter in CCIwhere 6(t) is the Dirac delta function and:Zm(f) = FT{g(t)g(t—mT)} = fG(s)G(f_s)exp(_j2icmrf)cis (EQ.A.7)and RG(U) is the autocorrelation function of the pulse-shape g(l)=h(t)*p(1), and SG(f)=/I-f(f)//P(f)/2is the power spectral density due to the equivalent filter hR(t)*p(t), which it the normalized powerspectral density of the input AWGN after filtering. Here the transmit and receive filter are assumedto be ,.J& raised cosine Nyquist filters.Notice that each of the M interferers add terms to S,2(J) which are identical to thosecaused by the signal inS1(f), with the exception of a phase offset due to the interferer’s timingoffset from the main signal. In addition, the last three terms ofS2(f) are due to the cyclostationaryprocess caused by (signal x inteiference) terms.Now, the expression for the jitter power in the bandwidth of the PLL can be written from,where S(f)=S,1(t)+2.t).The average over all CCI timing offsets, such that -1I(2T)< y <1/(2T).This results in:111Appendix A: Derivation of ML NDA Synchronizer Timing Jitter in CCI(EQ. A.8)S(O) = 1(a+a 3[(a2)2+(a2)21)z ( [1 -cos(ØA-26)j2 112 [1—cos(Ø8—29)1m+2()S SG(S)SQ(S)dS4+-(a÷aM[a+ j) () I IG(s)l2SG(_s)dsTab+M(a4+a43[(a2)2+ (G2)21)z(l)2+ (M2[2 + a2)21 + 2M (aa + ) JIG (s) I 2G ( - s) ds+ (M2[(a)2+(a)21+2M(aa+aa)) Z0(O)2where=(1/T) and ZZm (1/T)m112Appendix B: Simulation Error in Timing Jitter MeasurementsAppendix B: Simulation Error in Timing JitterMeasurementsDiscrete-time simulations limit the time-resolution for timing jitter estimation. The number of samples per symbol chosen for the simulation determines the lower bound on accurate timing jitter variance estimation. This is due to the zero-crossing of the timing wave being rounded tothe next discrete time value, which results in time quantization of the timing wave. Since the simulations are limited by computer memory size, the number of samples per symbol was also limitedfor ML DA and ML NDA simulations. The number of samples per symbol was chosen to be 128,which causes a limit to the measurable RMS timing jitter at 1/(2x 128) = O.0039T. For jitter valueswhich are close to this limit, time quantization may have an impact on the jitter measured by simulation. The error in simulated jitter measurement due to time quantization is discussed here.In order to estimate the effect on measurements of low jitter, a Gaussian distribution of thetiming-offset t is considered, with zero mean about the correct sampling instant, standard deviation a, and probability density function of f(t). The distribution can be divided into regions (xv,n = {O, ±1, ±2, ...} ) of size corresponding to the sampling period, d.1(t)Figure B.1: Probability density junction 1(r), of timing jitter, with samplinginstants marked.113Appendix B. Simulation Error in Timing Jitter MeasurementsAs shown in Figure B. 1, there is a finite probability that a sampling instant will fall withineach interval x,. Due to limitations of the computer simulation, any sampling instant which occursanywhere in the range x, will he rounded upwards to the next interval boundary, which is the simulated sampling instant.The probability that t falls within x, for a particular symbol period can be found by integrating the area off(t) over the area x:11 ((2n—l)d\_______P(tex)—Ierfcl I—erfcl I) (EQ.B.1)2 2oJi } 2aJ })where erfc(.) is the well known complimentary error function [49]. The variance estimate, s2, foreach sampling instant, as measured by the computer simulation is the difference between the measured sampling instant ( {±d/2, ±3d/2, ... }), and the ideal sampling instant, which is zero for thezero-mean processf(t). Therefore, for each sample, the timing jitter variance measured by the simulation for t E x, can be written as:2 (2n+l)d1= [ 2 j (EQ.B.2)with the value d dependent upon the number of samples per symbol, expressed as:T3d= (EQ.B.3)with T5 the sampling period for the simulation. d is simply the distance between sampling intervals. The total estimated variance, 2 can then be expressed as the probability of t lying withineach interval x, (Eq. B. 1) multiplied by the variance estimate for that interval (Eq. B.2, summedover all the possible regions (x, n = {O, ±1, ±2,...} ). The expression is:— [erfc27j2_erfc2tj2d)][(2t1] (EQ B4)114Appendix B: Simulation Error in Timing Jitter MeasurementsSince the tails off(t) rapidly approach zero, s2 need only be evaluated over a finite range of n.The error in jitter measurement due to time quantization of the simulation is simply thedifference between the jitter variance measured in the simulation, 2, compared to the actual jittervariance, a2. To evaluate the error, chose a jitter variance a2, evaluate d and 52, and subtract theresult from a2.The expression was evaluated numerically with -50 < n <50, for which was found to be asufficiently large range of n to evaluate the expression. The result can be summarized for the 128samples/symbol used in the ML NDA and DA simulations.Table B.1: Simulation error in estimating normalized RMS Timing Jitter, 128samples per symbol.a/T Estimation a /T Estimation(RMS Jitter) Error (RM Jitter) Error0.007 10.5% 0.010 5.2%0.008 8.4% 0.015 3.8%0.009 6.9% 0.020 2.3%Thus, RMS jitter values below O.02T will he slightly overestimated in the simulationresults.115

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