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Differential testing of CMOS integrated circuits Syal, Ashish 2002

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Differential Testing of CMOS Integrated Circuits by Ashish Syal  B.E. (Electronics and Communication Engineering), University of Delhi Delhi, India, 1999  A THESIS SUBMITTED IN PARTIAL F U L F I L L M E N T OF T H E REQUIREMENTS FOR T H E M A S T E R O F APPLIED SCIENCE D E G R E E in T H E F A C U L T Y OF G R A D U A T E STUDIES D E P A R T M E N T OF E L E C T R I C A L A N D COMPUTER ENGINEERING  We accept this thesis as conforming to the required standard  T H E UNIVERSITY O F BRITISH C O L U M B I A  March, 2002 © Ashish Syal, 2002  In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department  or by his or  her  representatives.  It  is  understood  that  copying  or  publication of this thesis for financial gain shall not be allowed without my written permission.  Department of The University of British Columbia Vancouver, Canada  Date:  DE-6 (2/88)  /IT DC*  ZbOZ •  Abstract  As CMOS technologies scale down, background leakage current increases inexorably, primarily due to device sub-threshold leakage. As a result, conventional single-threshold pass/fail IDDQ testing may no longer be valid for deep sub-micron technology. A number of alternatives to single threshold IDDQ testing have been proposed. A testing technique to complement IDDQ testing that has shown promise is thermal signature testing. The validity of using temperature as a test observable was investigated. After establishing this, the use of differential thermal sensing as a possible way of detecting bridging faults in CMOS gates was studied. Differential sensing provides high sensitivity to temperature changes generated by internal changes of the power distribution due to defects and immunity to ambient temperature changes. Different topologies for such sensors have been proposed targeting bipolar and BiCMOS. The novelty of the work is that these were the first such sensors to have been developed in CMOS technology. The thermal sensors were designed, simulated, fabricated and the chips that came back were tested. Three different types of sensors were designed and developed. They have the advantage that the performance of the C U T is unaffected by the sensors, as there is no direct electrical loading of the circuit due to them. Since these sensors do not directly load the circuit under test, they allow a non-intrusive methodology for testing. Also the sensors allow for on-line and off-line test, and diagnosis capabilities.  n  Table of Contents  Abstract  ii  List of Figures  vi  List of Tables  viii  Acknowledgement  Chapter 1  ix  Introduction  1.1 Digital Testing Overview  2  1.2  3  IDDQ Testing  1.3 Thermal Testing of Integrated Circuits  5  1.4 Scope of thesis  6  Chapter 2  Background Work  2.1  Thermal protection of microcomputer elements  8  2.2  Sensing Strategies  9  2.3  Desired Characteristics of an On-Chip Thermal Sensor  10  2.4  Absolute Temperature Sensors  12  2.5  Differential Thermal Sensors  15  Chapter 3 3.1  Feasibility of Thermal Testing  Design for Thermal Testability (DFTT) methodology  3.1.1 Sensor Features  19 20 iii  3.1.2 Placement Strategies  20  3.1.3 Readout strategy  20  3.1.4 Evaluation Strategy  21  3.2. Concept of Electrothermal Networking  22  3.3 Effect of Faults on Specific C U T  24  3.3.1 Operational amplifier design and specifications  25  3.3.2 Methodology  27  3.3.3 Power Calculation  27  3.4 Operational amplifier: Discussion and Results  Chapter 4  29  Differential Thermal Testing  4.1  Effect of temperature on mobility and threshold voltage  34  4.2  Differential Temperature Sensor Fundamentals  37  4.3  PMOS Cascoded Differential Thermal Sensor  37  4.4  N M O S Cascode Thermal Sensor  43  4.5  CMOS Differential Amplifier Thermal Sensor  47  4.5.1  Differential Amplifier  47  4.5.2 Common Mode Range Voltage  49  4.5.3 Layout and Working of the sensor  49  4.6  Testing of designed sensor  4.6.1 Test Setup  54 56  s.  4.6.2  Chapter 5  Monte Carlo Simulations  64  Conclusion  5.1 Summary of thesis  68  5.2 Future Work  69 iv  References  71  Appendix  75  v  List of Figures Fig 1.1  CMOS Inverter with voltage and current waveform  Fig 2.1  Basic architecture of an Absolute Thermal Sensor  15  Fig 2.2  Schematic of a BiCMOS differential thermal sensor  16  Fig 2.3  Cascoded BiCMOS differential thermal sensor  4  18  Fig 3.1 Serial interface of the CMOS-compatible temperature sensor  21  Fig 3.2  22  Representation of silicon surface as a R C network  Fig 3.3 Schematic of the designed operational amplifier  27  Fig 3.4. Voltage Follower Configuration  30  Fig 3.5 Points around the operational amplifier chosen for measuring the temperature change in a fault-free and faulty case 31 Fig 3.6: Temperature computed at points PI, P2, P3, and P4 as a function of Vin  31  Fig 3.7: Faults injected into the circuit  32  Fig 3.8: Temperature variation between the faulty cases and the fault free at PI  33  Fig 4.1: Variation of the MOS current with temperature  36  Fig 4.2: Schematic of the PMOS Cascode Thermal Sensor  39  Fig 4.3: Layout of PMOS Cascode thermal sensor  40  Fig 4.4: Output voltage variation of the differential sensor for different bias currents.. ..41 Fig 4.5 Variation of voltage sensitivity of sensor for different ambient temperature  42  Fig 4.6: Schematic of our NMOS Cascode Thermal Sensor  43  Fig 4.7: Layout of NMOS Thermal Cascode Sensor  44  Fig 4.8: Output voltage variation of the N M O S sensor for different bias currents (I)  45  vi  Fig 4.9: Variation of output voltage of sensor with variation in ambient temperature.. ..46 Fig 4.10: Schematic of Differential Amplifier Thermal Sensor  47  Fig 4.11: A simple source coupled differential amplifier  48  Fig 4.12: Block diagram of the differential amplifier thermal sensor  49  Fig 4.13: Layout of differential thermal amplifier sensor  50  Fig 4.14: Output voltage variation of the differential sensor for different bias currents ..53 Fig 4.15: Variation of output voltage with variation in ambient temperature  54  Fig 4.16: PMOS Cascode Temperature Sensor  54  Fig 4.17: Output voltage variation of the differential sensor for different bias currents..55 Fig 4.18: Circuit diagram of LM334  57  Fig 4.19: Voltage vs Current variation for a 10 M Q probe  58  Fig 4.20: Cascode configuration of the output  59  Fig 4.21: Voltage versus Current for a 1 Mega Ohm probe  61  Fig 4.22: Simulation results showing the effects of attaching a 1, 2.2, 3.3,10 M Q resistor to the sensor output 62 Fig 4.23: Chip results, showing the effects of attaching a 1, 2.2, 3.3,10 M Q resistor to the sensor output 62 Fig 4.24: Voltage vs Current of heat source : Simulation and Chip result Fig 4.25: Voltage vs Current when Voltage across the sensor is changed  63 64  Fig 4.26: Monte Carlo simulation for varying the input current supply  67  Fig 4.27: Monte Carlo simulations for increase in local temperature over ambient  67  vii  List of Tables Table 3.1: Power dissipation of basic CMOS gates in 0.18pm CMOS  24  Table 3.2: Temperature increase at various distances from heat source  24  Table 3.3: Widths of transistors in operational amplifier  26  Table 4.1: Temperature of M4 increased by 1°C at ambient temperature of 25°C  40  Table 4.2 Temperature of all transistors increased by 1°C at ambient temperature by 25°C 40 Table 4.3: Temperature of M3 increased by 1°C at ambient temperature of 25°C  45  Table 4.4: Temperature of all transistors increased by 1°C at ambient temperature by 25°C 45 Table 4.5: Temperature of M l increased by 1°C at ambient temperature of 25°C  52  Table 4.6: Temperature of all transistors increased by 1°C at ambient temperature by 25°C 52 Table 4.7: Device model parameter  66  viii  Acknowledgement  I would like to express my sincere gratitude to Dr. Andre Ivanov for giving me a chance to work with him and providing me with excellent guidance, encouragement, and support during the last two years. I would also like to acknowledge the support and help which I got from Dr. Res Saleh and Dr. Josep Altet and for their being there for me when I needed them. A special thanks to Mr. Roozbeh Mehrabadi for his technical and personal support in the lab. I also acknowledge Micronet, NSERC, and C M C for providing financial support and equipment for this research. I would also like to thank all the members in the SOC lab for their comments and suggestions and also my friends Karthi, Dave, and Mohsen. Finally though I cannot express it in words I express my heart felt gratitude and indebtedness to my parents who have encouraged me and helped me in all my endeavors.  ix  Chapter 1 Introduction The rapid advances in fabrication processes for integrated circuits (ICs) and the market requirements has increased the need to design complex mixed signal application specific circuits (ASIC).  The ability to build large chips of unlimited variety and functionality  introduces the problem of determining whether those chips have been manufactured correctly or not. Chip designs are simulated to ensure that the circuits compute the proper functions to a sequence of inputs chosen to exercise the chip. But every chip that comes off the manufacturing line must also undergo manufacturing test, i.e., the chip must be exercised to demonstrate that no manufacturing defects rendered it unusable. A high-speed tester that can adequately handle the millions of transistors on present day chips comes at astronomical costs [1]. Reducing the test time for a single component can help increase the throughput of the tester and has an important impact on the testing cost. This need has evolved the concept of Design for Testability (DFT), where the goal pf reducing the cost of testing is facilitated by introducing testability criteria early in the design stage. Testability criteria have become so important that they may even dictate the overall structure of the design [2]. The  most  important properties  for testability  of designs are observability and  controllability. The observability implies the ease of measuring the value of a node at the output pins. A node of high observability is one that can be observed directly at the output while one with a low observability needs a number of cycles before its state can appear at  1  the output.  Controllability measures the ease of bringing a circuit node to a given  condition using only the input pins. A n easily controllable node can be brought to a given condition by a single input vector.  1.1 Digital Testing Overview  The testing of digital circuits is usually based  on certain well-established  test  methodologies which include Ad-Hoc testing, Scan Based testing, Automatic Test Pattern Generation (ATPG), and Built-in-Self-Test (BIST). 1) Ad Hoc Testing: Ad hoc testing combines a collection of techniques that can be used to increase the observability and controllability of a design and are generally applied in an application-dependent fashion [ 1 ] . The methods includes techniques like partitioning of large state machines, addition of extra test points, provision of reset states, and introduction of test buses. 2)  Scan-Based Test: The most popular structured DFT technique used for testing is referred to as scan design as it employs a scan register. In this approach, the registers in the flip-flop are modified to support two operation modes. In the normal mode, they act as clocked registers and in the test mode, the registers are chained together as a single shift-register. This approach incurs only a minimal overhead and the serial nature of the scan chain reduces routing overhead [ 1 ] .  3 ) Boundary-Scan Design: With the introduction of new packaging techniques like surface mount and multi-chip modules, the observability and controllability provided by the bed-of-nails approach of testing for circuit boards decreased [ 1 ] . This problem was addressed by extending scan based testing to the component and board levels. This  2  approach called the boundary scan design involves connecting the input and output pins of the component board into a serial scan chain. During the normal operation, the boundary-scan pads act as normal input-output devices. In test mode, vectors can be scanned i n and out o f pads, providing controllability and observability at the boundary of the components and hence the name [2]. 4)  Built-in-Self Test (BIST): Built in Self-Test refers to the capability o f a circuit to test itself. The B I S T techniques can be classified into two categories, namely on-line B I S T , which includes concurrent and non-concurrent techniques, and off-line B I S T , which includes structural and functional approaches [2]. In on-line BIST, testing can occur during the normal functional operating conditions (concurrent BIST) i.e., the circuit under test ( C U T ) is not placed into a test mode where functional operation is locked out or during idle state (non-concurrent BIST). Off-line B I S T deals with testing a system when it is not carrying out its normal functions. Systems, boards, and chips can be tested in this mode.  1.2  IDDQ  Testing  Quiescent power supply current (IDDQ) testing o f C M O S integrated circuits is a technique for producing quality and reliability improvement, design validation, and failure analysis [3]. I D D Q plays a complementary role with logic response tests in the detection o f faults. The basic principle behind I D D Q testing is that a C M O S circuit in the normal mode o f operation would consume very little power [31] and when in standby mode it would draw practically no current, just the leakage current. I D D Q testing is performed by measuring the current o f the V D D power supply in the quiescent logic condition after the inputs have 3  changed, and prior to the next input change. Fig 1.1, shows the basic principles of IDDQ testing. In this Figure, a generalized IC has a gate oxide defect in a p-channel transistor of an internal logic gate. When the input to a logic gate changes from logic 1 to logic 0, the magnitude of IDDQ changes from a low value to an elevated value. Built-in current sensors attached to this circuit can detect elevated values of current, and if this value is above a threshold value, the circuit is declared faulty.  DEFECT *  i  D  D  j VIN  VOUT Vin * DEFECT iDD  \ NO DEFECT 'IDDQ  Fig 1.1: CMOS Inverter with voltage and current waveforms  A very critical requirement for IDDQ testing is that very small values of current be measured at the V D D and VSS supply of the circuit under test (CUT). The threshold value for a pass/fail IDDQ test is in the range of 1-10 uA [4]. For a clear decision that the C U T has passed the test, the measured value of the current must be an order of magnitude smaller than the set threshold. However the problem of diagnostics and the pass/fail decision making with IDDQ testing become increasingly difficult as the feature size and supply voltage are reduced with the scaling of technology. As CMOS processes are scaled  to the deep sub-micron region, device reliability and low power constraints enforce a reduction in the power supply voltage [5,6] which in turn necessitates lower transistor threshold voltages. For a lower threshold voltage there is an increase in the sub- threshold leakage currents. The off or standby current will increase by 100 times as we move from 0.5 micron to 0.1 micron [4]. The off current for an enhancement mode transistor is defined as the leakage current when VGS  =  0 V [2]. As a result of this scaling we see that single  threshold IDDQ testing loses its effectiveness. In order to extend the lifetime of IDDQ testing a number of new techniques have been put forward. Some of these will last for a single generation and some will last longer. Techniques such as splitting power supply lines last only a single generation but techniques such as measurement analysis which treats finding a defective current within an IDDQ measurement as a signal extraction from a noisy reading will last longer [5]. A number of new approaches that can last for longer than a generation are dynamic current measurement, energy consumption measurement, and thermal testing. The purpose of this thesis is to advance the idea of thermal testing.  1.2 Thermal Testing of Integrated Circuits In [7], a built-in dynamic thermal strategy is presented as an alternative testing technique for integrated circuits: CMOS digital circuits generally have a very low power dissipation during the quiescent phase between two logic transitions. If there is a defect in the CUT structure and a test vector activates it, an electrical path can be established between the power supply and the ground rails. Thus, it can be concluded that some MOS devices dissipate an extra amount of power, behaving as unexpected heat sources and increasing  5  the temperature around their location. The magnitude of the power dissipated by these devices depends on their dimensions, supply voltage, and topology of the defect [8]. Builtin temperature sensors can be used to detect this extra power dissipation, and therefore, to detect a defective circuit. Thus , temperature is used as a test observable. The advantage of this technique is that the temperature sensor is not electrically connected to the test circuit, preventing circuit performance degradations. Failure analysis [9] and failure prevention of the circuit under test can be done by using temperature as a measuring parameter. The heat flow path from the heat source to heat sink is modified if there are breaks in it and these can be found out by checking the absolute temperature of the IC at specific points. CMOS built-in temperature sensors have been proposed [10,11,12] in order to guarantee thermal integrity and the presence of safe values of the CUT working temperature. In [13], abnormal temperature increase profiles generated by defects in the C U T are detected by using thermographic images and liquid crystals. In [14], transient differential thermal measures of the silicon surface are taken, using a built-in temperature to build short circuit protection for a current booster.  1.3 Scope of thesis The first part of this thesis presents a broad understanding of thermal testing of integrated circuits and the latter part concentrates on a specific type of thermal testing, which is differential thermal testing. In Chapter 2, we look into the prevalent methods of thermal testing, which include differential and absolute thermal testing. A brief overview of absolute thermal testing is provided and the concept of differential thermal testing is introduced and the work done in differential Bi-CMOS thermal sensors is described by  discussing one such sensor circuit. In Chapter 3, a thermal strategy for reading out the thermal data is presented. This Chapter also covers an investigative study of the variation of the temperature across the silicon surface for a fault free and faulty Operational Amplifier. Chapter 4 presents three differential thermal sensors designed in CMOS technology. The sensors are the first such sensors to be designed in CMOS and are presented in this chapter with simulation and test results. After this the application of the developed sensors to the testing of analog circuits is shown. Chapter 5 presents a critical evaluation of the thermal testing process and recommendations for future work required in this area are given.  7  Chapter 2 Background Work  The design of an electrical circuit in ICs also creates a thermal system. The downscaling of technologies has led to greater power and packaging densities resulting in thermal effects becoming more and more significant. The increased power density results in higher chip temperatures, leading to changes in device parameters, and thereby a reduction in the reliability of the circuit. The reliability of the circuit depends exponentially on the temperature of the junction. Such small differences in operating temperature (10-15°C) can result in a ~2X difference in the life span of the devices [15]. Also, it is necessary to maintain the temperature of the device at a certain level, as the speed of the device, in many cases, depends on the operating temperature. Various tools and design methods enable thermal measurement of operating circuits and hence early detection of faults.  2.1  Thermal protection of microcomputer elements  High-clock- rate devices dissipate a considerable amount of power. Maximum power trends (e.g., for microprocessor units) are divided into two categories: 1) High performance desktop applications, for which a heat sink on the package is permitted. 2)  Portable battery operations.  In both cases, the total power consumption continues to increase, despite the use of lower supply voltage. The increased power consumption is driven by higher operating  8  frequencies and higher overall resistance of larger chips with more on-chip functions. The power consumption for today's high power applications is expected to increase from 100W in the year 2000 to 160W in 2005 [15]. Sophisticated cooling techniques such as finned dissipaters on the package, forced convection, and cooling fans reduce even such high amounts of heat. Small thermal disturbances can affect the effectiveness of the cooling process and cause unacceptable temperature increase across the chip. To avoid damage, these processors require active temperature monitoring that launch power reducing actions when the danger of overheating occurs.  2.2  Sensing Strategies  Temperature mapping reflects the temperature distribution across the chip surface. There are two general strategies for the detection of active heat sources on the chips: (1) Off-chip temperature measurement strategies. (2) On-chip temperature sensors. The most commonly used off-chip method is infrared thermography [31]. The core of the equipment is an infrared (X = 2,4,.. .12p.m) camera with its infrared detector cooled to an extremely low temperature to eliminate noise. It usually scans the image mechanically, using rotating mirrors or prisms. Infrared thermography provides a high temperature resolution, of the order of .1°C with a spatial resolution of the order of 10pm. The method is very fast and can be used to investigate transient phenomena, but it is highly expensive. Another popular off-chip method in popular use is liquid crystal thermography [17]. This is based on the fact that liquid crystals have different phases, which show different optical properties. The phase transitions occur at well-defined temperatures. The surface of the 9  chip is covered with a liquid crystal, which makes transition lines optically inspectable, and each transition represents an isotherm of the temperature map. The temperature resolution of this method is higher than 0.1 °C and the spatial resolution is about 3 pm. This method is cheaper than infrared thermography but takes a much longer time to obtain the thermal map [17].  Reflectrometric and interferon!etric techniques provide high sensitive and wide  dynamic range temperature measurements and have been used successfully for failure analysis [17]. On-chip or built-in temperature sensors, albeit an area overhead, provide flexibility for the test procedure, allowing both laboratory testing and in-field testing. Neither direct visual access to the silicon die nor a laboratory environment is required. Direct thermal coupling measurements can be taken, without being affected by any layer over the silicon. The output signal of the built-in-sensor can be proportional to absolute temperature or proportional to the difference of temperature at two points of the silicon surface.  2.3  Desired Characteristics of an On-Chip Thermal Sensor  Thermal sensors are used for a variety of purposes, for on-chip and off-chip applications. However, designing a temperature sensor for IC testing applications is a different task. A n effective sensor must have the following characteristics: small area, easy accessibility and low power dissipation in addition to high reliability and high sensitivity. A smaller sensor is easier to place and route within a large CMOS chip.  Small sensors are also more  effective in sensing defects as they can be placed closer to probable defect locations and small variations in temperature can also be detected. By reducing the distance between the  10  sensor and the defect, more sensors can be deployed to increase coverage and decrease the average distance between the sensor and a potential defect. The second criterion for a temperature sensor is easy accessibility of results. Many modern sensors can sense temperature, but extracting results from those sensors proves to be troublesome. Voltage and current output sensors are susceptible to noise from core power supply and from the automatic test equipment (ATE).  Some sensors that have digital  outputs tend to generate a clock as an output [12]. A clock output is fine for a single onchip sensor. However, it may become very time-consuming to read the results from a large number of on chip sensors within a short period of time [18]. The third criterion for temperature sensor effectiveness is power consumption. A power hungry sensor may dissipate more heat than the fault that it is trying to sense. If a large number of thermal sensors were placed within an IC, the total power consumption of the test structure may overwhelm the current handling capability of the IC. Hence, the IC would have to be modified to handle the extra current that the test structure requires when active. The fourth criterion is a high resolution of the temperature sensor. Some defects cause an increase in temperature. This increase can be high or can be very small. A sensor with a high resolution can detect very small increases in temperature. The fifth criterion is high sensitivity of the temperature sensors. Sensitivity of a sensor is determined by the amount by which the output variable, which could be current, voltage orfrequency,of the sensor is affected by the increases in temperature. For a sensor with a high sensitivity, even small changes in temperature causes the output variable to change appreciably.  11  Finally, one very important criterion for a temperature sensor is compatibility with a target process, without any additional fabrication steps. In our case this implies that the sensors be designed in CMOS technology. MOS technology is less appropriate to realize temperature sensors than bipolar process, so providing a good CMOS sensor is a real challenge today [16]. A large number of temperature sensors in CMOS technology are made using the parasitic bipolar transistors. But the use of MOS only sensors provides a better alternative as the parameters of the MOS transistors are strictly controlled whereas the control of parasitic bipolar transistors is not so. Also, this provides a process independent production as only the MOS technology parameters are to be taken care of. Two different thermal testing strategies are discussed here: differential temperature sensing and absolute temperature sensing.  Differential sensing provides high sensitivity to  temperature changes generated by internal changes of the power distribution due to defects and immunity to ambient temperature changes [17]. On the other hand, absolute temperature sensors provide information about working temperature of the C U T , information that can be important for reliability purposes.  2.4  Absolute Temperature Sensors  Absolute temperature sensors increase the system reliability by predicting eventual faults caused by excessive chip temperatures. The main objective of on-chip absolute thermal sensors, from a reliability and test point of view, is to provide continuous thermal verification, which is useful to detect the excessive power dissipation and eventually chip deterioration. Transistors, MOSFETs, and diodes can be used as absolute temperature sensors. Transistors are in general much better sensors than diodes because their base is  12  very thin and they are three port devices, makes the incorporation of these devices in electronic circuits much more convenient. The use of a transistor as a temperature sensor is based on Ic-Vb characteristics where Ic is the collector and Vb is the base to emitter voltage e  e  of the transistor. The emitter current Ie consists of a diffusion, a surface leakage and a recombination component. The collector current, Ic consists of the diffusion component, and the base current lb consists of the other two components. The expression for the dependence of Vb on collector current Ic and temperature T of the device is given by [33]: e  V  = V (0)  + (kT  g  fq)ln[Ic-  ln( KT  r  (2.1)  I rj)]  Where V (0) is the band gap voltage at 0 K , k is the Boltzman constant, T is the g  temperature in Kelvin, q is equal to the charge of an electron, I is the collector current, r is c  a constant varying between 3 to 5 for commercially available devices, and rj is the ionization factor. Based on Equation 2.1 a transistor can be used as an electrical thermometer. Making use of only one transistor, the collector current can be varied between a fairly high value I j  and a fairly low value I 2 with corresponding base values  c  Vbei and Vhe2-  C  The voltage difference is given by:  W =V -V =(kTlq)\n(I JI ) be  beX  be2  c  c2  (2.2)  13  Differentiating this voltage difference to temperature gives  a = d(AV )/dT be  = {klq)\n{I  cX  II ) c2  (2.3)  The temperature coefficient a is a constant and AVb is directly proportional to the absolute e  temperature T. Also, a and AVb are independent of materials or transistor parameters. e  Such sensors are known as Proportional to Absolute Temperature (PTAT) sensors. A number of sensors using the same principle but more sophisticated techniques have been proposed and implemented [ 3 3 ] . It is also possible to use the same idea for MOS technology sensors. It appears that a MOS transistor in weak inversion exhibits a similar exponential relationship between the control-gate voltage and the channel current as Vb  e  and le in bipolar transistors, but the spread in data is still very large [ 3 3 ] . In CMOS technology there are three possible devices which can be used as temperature sensors, which are, lateral bipolar transistors, vertical bipolar transistors, and CMOS transistors operating in weak inversion. The temperature sensed by these sensors is then converted into an oscillating signal and thus facilitates the evaluation of the temperature sensed. The basic architecture of an absolute thermal sensor is as shown in Fig 2.1 [18]. The sensor is based on the Proportional to Absolute Thermal (PTAT) current reference generator driving a counter through a ring oscillator. The delta V  g s  generator performs the  temperature sensing and a ring oscillator converts the current to an oscillating square wave. The counter measures the frequency of the ring oscillator and makes the results available to  14  a scan chain. The oscillator's frequency depends on the temperature. By counting the oscillator's pulses in a time window, we obtain a measure of the temperature.  Delta V  G  S  P T A T Current  Bias  Serial Interface  Counter  PTAT Clock Fig 2.1: Basic architecture of an Absolute Thermal Sensor  2.5  Differential Thermal Sensors  If the thermal disturbance generated by defect activation is to be used as a test observable, differential thermal testing can be used as the test strategy. Differential thermal sensors compare the temperature of the circuit under test to the ambient temperature of the silicon surface and determine whether the thermal variation of the temperature is due to defect activation or not. Previous work in differential thermal sensors has been done using BiCMOS technology. [17] provides a good perspective to the differential thermal sensors developed in BiCMOS technology. Here, we present a brief look at the concept behind these sensors by reviewing one such sensor. Fig 2.2 shows the schematic of the sensor.  15  VDD  VDD  R2  R1  VOUT  Q1 T1  Q2 T2  9  vss  Fig 2.2: Schematic of a BiCMOS differential thermal sensor  This sensor has the same structure as a differential amplifier. In the case of a differential amplifier if there is a small difference in the base-emitter voltage, it results in a different currents flowing through the two transistors. Here, however, temperatures difference between the two transistors imbalances the structure and this causes a difference in the current flowing through the two transistors QI and Q2. If the ambient temperature of the silicon surface were T, and if a heat source is activated, the temperature of the bipolar transistors will increase and will be:  16  Tl = T + ATI  (2.4)  T2 = T + AT2  where T l is the final temperature of the transistor Q l and T2 is the final temperature of the transistor Q2. ATI is the change in temperature of Q l and AT2 is the change in temperature of Q2. When the base current of the transistor Qj, is zero and R=R1= R2, Q l and Q2 would have the same operating point and thus the same small signal model. I f the temperature of Qb remains at the temperature of T, and the output resistance of the current source Ie be assumed to be infinite, then the output voltage is given by [17]:  A ^ „ , =S r R[AT\-AT2]/[2(r +R)] T  0  0  (2.5)  where r is the output resistance of Q2 and ST is the sensitivity parameter given by <9Ic/<9T. 0  Fig 2.3 shows the complete schematic of a BiCMOS thermal sensor. Devices MR1 to MR4 are connected in a cascode configuration and hence provide a high output impedance. The imbalance in current caused by a temperature differential across the sensor in the two transistors Q l and Q2, is amplified by the cascoded output configuration. Thus the presence of these sensors allows the detection of bridging faults in the circuits by using the change in temperature caused by these faults to cause a variation of the output voltage of these sensors.  17  VDD  ; 2.3: Cascoded BiCMOS differential thermal sensor  Chapter 3 Feasibility of Thermal Testing  Every circuit dissipates power within a range/distribution, when it is in a normal mode of operation.  This consumed power is converted into heat and spreads across the silicon  surface causing a thermal gradient. Each circuit forms a specific thermal gradient, which is known as the thermal signature of the circuit. This thermal signature can be determined using off-chip measurement techniques or on-chip absolute thermal sensors of a functionally correct integrated circuit. The differential thermal sensors placed near the circuit are biased based on the thermal gradient around the circuit. If there is a defect in the circuit, the thermal gradient around the circuit changes and the differential thermal sensors detect this change. The placement of the sensors on the silicon chip can be done on an adhoc basis or by using a well-defined methodology. This methodology is given the name design for thermal testability (DFTT).  3.1 Design for Thermal Testability (DFTT) methodology Recent research works have proposed that instead of ad-hoc solutions, we should establish a regular, commonly accepted methodology for insertion of thermal sensors [19]. A D F T T methodology for testing of integrated circuits should encapsulate a broad based strategy, which includes the important characteristics of the designed thermal sensors, placement strategy, a readout strategy, an evaluation strategy, and the type of faults that can be detected. This methodology would result, as is also the case with Design for Testability (DFT), with enhanced thermal testability but at the expense of excess silicon area.  19  3.1.1 Sensor Features The most important features of thermal sensors as was discussed in Chapter 2 are small area, easy accessibility, low power dissipation, high reliability and high sensitivity. The designed sensor is realized in the form of a cell that becomes part of a standard library cell. The sensor also has the advantage of portability in that its operation is independent of the type of CUT.  3.1.2 Placement Strategies The designer must decide how to place the thermal sensor to achieve the best fault coverage properties.  The placement is done either manually or by using place and route  tools. The manual placement requires that the thermal gradient of the silicon surface of a defect free integrated circuit be analyzed and the sensors be placed where there is a maximum probability of a defect and/or maximum power dissipation. Automatic place and route tools allow the sensors to be placed in a regular arrangement of 2*2 or 4*4 or n*n cells. A weakness of this approach is that the sensors would not be placed at optimum positions hence the probability of detection of faults is reduced.  3.1.3 Readout strategy The output of differential thermal sensing is a change in output voltage of the sensors. This change in output voltage is converted into a digital output, either a code word or a square wave function, using analog to digital converters. Stand-alone circuits are a possible solution to accessing the results of the output voltage of the sensors, but the better alternative is to combine the readout circuits with other built-in test hardware [12]. One such method involves combining the thermal test circuitry into the boundary scan architecture and is shown in Fig 3.1. This technique has the advantage that no extra pins are required. All the thermal sensors on the chip can be multiplexed together. They can then be 20  accessed using signals from the test access port controller.  Thermal testing can be  interfaced with other built-in self-test schemes.  Test access port Enable Capture  Temperature Sensor  Reset Counter  Serial Interface  Fig 3.1: Serial interface of the CMOS-compatible temperature sensor  3.1.4 Evaluation Strategy The simplest evaluation technique is for the test software system to scan the temperature of all sensors and compare it to a known template. If there is a variation from the known set of temperature template, then a fault has been detected. Thermal testing provides not only detection but also diagnostic abilities. Due to the diffusion nature of the thermal transfer of heat through the silicon die, simple signal processing of the waveform sensed at the monitoring point can provide the distance between the heat source and the monitoring points. Therefore, by processing the information from the various temperature sensors the exact location of the heat source can be calculated. [17]  21  3.2. Concept of Electrothermal Networking An extracted RC network was used to understand the heat flow through the substrate. This extracted RC network allows us to estimate the heat flow through the silicon substrate. The concept behind the network is the analogy that can be drawn between basic electrical and thermal variables (Fig 3.2).  1(2 um) -A/W  T(4  urn)  T(2n urn)  w v  T  Fig 3.2: Representation of silicon surface as a RC network  In Fig. 3.2 the substrate is represented as an RC network. The temperature is measured at distances of 2pm, 4pm, 6pm and so on from the heat source. Voltage difference and current flow in an electrical circuit are considered analogous to temperature difference and power flow due to heat dissipation in a thermal circuit, respectively.  An electrical  simulator gathers information on power dissipation and couples it into the R C mesh that models the heat flow in the substrate [22]. The substrate temperature information is simultaneously coupled from the thermal solver to the electrical solver. Incorporating the coupled electrothermal effects into the circuit simulator requires that the differential heat equations (3.1 and 3.2) be solved.  22  J = -kVT  (3.1)  u  pcOT/a + V.J = 0 U  (3.2)  Where / „ is the heat flux density, T is the absolute temperature, k,p, and c are the thermal conductivity, density, and specific heat of the substrate material respectively. Simulators like Sabre solve the system of equations by iterating the system variables such that component of current flow into electrical node sums to zero (Kirchoff s current law) and also the components of power flow into the thermal node sum to zero (energy conservation). The maximum power dissipated by three basic digital gates, i.e., an inverter, N A N D and NOR in .18pm CMOS technology when their NMOS transistors are short-circuited to Vdd (3.3V) with a bridging resistance of 200 Q[20] at 25°C are as shown in Table 3.1. The power dissipated depends on the topology of the circuit, the supply voltage, the technology used and the type of fault.  All the dissipated power is converted to heat. The heat  dissipated is thermally coupled to the silicon substrate and causes an increase in temperature in the region adjacent to the heat source. The heat flow through the substrate due to a device dissipating power was simulated using a RC network model [21], extracted by using the finite difference method [22]. Table 3.2, shows a set of data for the transient simulation of the temperature increase at different distances from a 16um/lpm NMOS transistor, in .18pm CMOS technology at Vdd = 3.3V. The transistor dissipates 13.8mW of power. This power is applied as a pulse (Time period=50ps, Duty cycle=50%) to the R C network. The data shows the variation of the temperature of the silicon substrate due to the heat source.  23  Digital Circuit Sizes (W/L)  Power  Power  (Steady state, W) (Fault, W) Inverter  13.80*10"  NMOS=16um/lum 3*10"  U3  12  PMOS=32um/lum NAND  NMOS=16um/lum 68*10"  7.80* 10"-  uy  0 3  PMOS=16um/lum NOR  NMOS=16um/lum 116*10"  uy  13.80*10"  UJ  PMOS=64um/lum  Table 3.1: Power dissipation of basic CMOS gates in 0.18um CMOS  Distance  Temperature  (urn)  Increase (°C)  2  3.28  4  2.24  6  1.65  10  1.12  50  0.13  100  0.02  200  76* 10"  6  Table 3.2: Temperature increase at various distances from heat source  3.3 Effect of Faults on Specific C U T  We studied the case of heat dissipation using a specific CUT in order to understand the temperature changes which occur when there is a short circuit fault. A CMOS operational 24  amplifier was simulated, designed, and fabricated in CMOS .18pm technology, and faults were induced in the operational amplifier. The operational amplifier was chosen to be the C U T for our experiment as its thermal characteristics had been studied as part of our research effort at U B C [23]. The fault free and the faulty case were analyzed and studied. 3.3.1 Operational amplifier design and specifications A two-stage differential input, single output operational amplifier was designed. Figure 3.3, shows the designed operational amplifier. The operational amplifier had the following specifications: Bandwidth: 10 MHz Slew Rate: 20 V/ps Common Mode Range: 1.4V- 1.9V Common Mode Rejection Ratio: 80 dB Gain: 83 dB The first step of the design involved choosing the device length for the transistors in the operational amplifier and was chosen to be 1 pm. This allows for the determination of the channel length parameter X. After this the determination of the compensation capacitance is done using the output capacitance attached to the operational amplifier output. In our case the output capacitance was taken to be 5pF and the compensation capacitance was calculated to be 1.2pF for a gain phase margin of 60°. The value of the widths of the MOS transistors used in the operational amplifier were calculated in accordance to the specifications of the operational amplifier to be designed.  25  Transistor No.  Width  Ml  16um  M2  16um  M3  lu.m  M4  lp.m  M5  35p.ni  M6  28p.ni  M7  24p.ni  M8  5um  M9  18pm  M10  1pm  Mil  1pm  Table 3.3: Widths of transistors in operational amplifier The transistor sizes were selected after the Spice simulations were conducted and a layout of the circuit was done.  26  VDD  Vout  M12  VSS Fig 3.3: Schematic of the designed operational amplifier  3.3.2 Methodology An operational amplifier was taken to be the circuit under test and its thermal properties were investigated. The power absorbed by the operational amplifier in its faulty and fault free states was recorded. The faults which were studied included short circuit bridging faults, short circuit node to node and node to power supply faults were investigated. The thermal mapping of the circuit is done by mapping the power consumed by each element, i.e., the MOS transistor, as it travels towards the silicon surface and the boundaries of the chip die. The test sensor determines if there is a fault in a given location by comparing the ambient temperature at a given place with its temperature in a fault free state. The sensors are placed at either the hottest regions on the chip surface and/or by placing them in places of critical importance and in places where there is a maximum probability of defects.  3.3.3 Power Calculation The power consumed by the MOS transistor was extracted using Spectre, the simulator under the environment of Cadence Analog Environment. In Analog Artist, it can be  27  automatically done by saving all the current and all the node voltages of the circuit. In order to obtain the instantaneous power of a MOS transistor, the current through the transistor is multiplied with the potential difference between the source and the drain terminals. Hence, we have :  p s(t) = MO  i {tr[v {t)-vM s  s  (3.3)  where PMOS(0 is the power consumed by the MOS transistor at a given time, Is(t) is the current through its source, Vs(t) is the voltage of the source at a given time, Vo(t) is the voltage of the drain at a given time. Obtaining the average power of a transistor of the operational amplifier is theoretically very simple. For the case where there is a constant difference in the voltage applied to the transistors M7 and M8 of the operational amplifier, the power consumed is equal to the product of the supply voltage and the sum of the currents flowing in through the various branches of the operational amplifier. For the case where the input voltage at the transistors M7 and M8 is a periodically varying signal the power of each transistor is calculated simply by dividing the instantaneous power, or the power spectral density, over one time period of oscillation. In other words,  (3.4)  where P  AVE  is the average power consumed by the transistor, and (T2-TJ)  is the time for one  period of oscillation.  28  In the Cadence simulation environment, in order to determine the average power of all transistors, when the input signal is periodically varying, Analog Artist needs to know the exact start and stop simulation times. The spectral density of each transistor is different, and hence the periods of the function are also different. Thus, determining the start and stop simulation time for one cycle of every transistor requires multiple simulations of getting one average power value at a time, making the simulations very tedious and extremely inefficient.  As an alternative, we can approximate the average power by integrating the  power density over a long period of time. The time window used was 10ns. This was because the operational amplifier had a cut off frequency of 10 M H z and hence lOps is equivalent to 100 oscillation periods of the operational amplifier.  (3.5)  Thus, although the power is averaged over a much longer period of time, multiple simulations do not have to be performed to determine the power of each transistor.  3.4  Operational Amplifier: Discussion and Results  The temperature of the operational amplifier is recorded in the fault-free state and in the faulty state under normal operating conditions. The operational amplifier is connected in the voltage follower configuration as shown in Fig 3.4. The simulation results that are shown are part of the combined work done by Lungwai et. all [30]. A D C analysis was performed, sweeping the input voltage, Vin,from0 to 3.3V.  29  VDD  Vout  VSS  Fig 3.4. Voltage Follower Configuration  Four points around the CUT were chosen and the surface temperature recorded at these specified points. Fig 3.5 displays four points around the layout of the operational amplifier. Points Pi and P3 are located near the power supply lines, point P2 was chosen randomly and point P was chosen as it was near the capacitor. Because the temperature is highly 4  dependent upon the position of sensing device, the distances between each transistor and the measuring point must be measured in the layout of the circuit. For example, the partial thermal resistances and heat capacitances of the heat flow path from each transistor dissipating power to point, Pi, contributes to the total temperature contribution at Pi. Hence the power consumed by each transistor is simulated, and fed into the RC network and the corresponding increase in temperature at point Pi is found.  30  P3  P2  P4  P1  Fig 3.5. Points around the operational amplifier chosen for measuring the temperature change in a fault-free and faulty case  Fig 3.6 displays a plot of the temperature change in a fault-free circuit at the four different points for sweeping the input voltage of transistors M7 and M8 from 0 to 3.3V. At all of these positions, it shows a decrease in temperature with increasing Vin.  4.0E-2 A  A  A  °> re  A  3.0E-2  H u  f * i- O)  in  m 1  Fault-free Circuit  A  •  A  •  I  |  3re 3sL a> 2.0E-2  •  i_ — o  CL  E — I  o ©  ® •  © © ©  1.0E-2  S  @  o  0.0E+0 0.0  0.6  • P1  1.2  1.8  P2  A P3  •  S o  2.4  O P4  •  ©  •  o  3.0 Vin  Fig 3.6: Temperature computed at points PI, P2, P3, and P4 as a function of Vin  31  The study focussed on node to node, node to power supply and node to ground bridging faults. For this reason the three faults, RI, R2, R3, shown in Fig 3.7 were investigated. VDD  M12  VSS  Fig 3.7: Faults injected into the circuit The RI is a node to ground fault, R2 is a node to power supply fault, and R3 is node to node fault. Fig 3.8 presents the simulation results due to these bridge faults at point PI. The bar graph shows the relative temperature difference between the faulty and fault-free case. For example, the relative variation for an input voltage of 0 Volts at point PI, due to fault RI is 0.59° C. That is, the temperature above the ambient in a fault free case at point PI was 0.23° C but when fault due to RI was introduced it rose to 0.82° C.  32  Fig 3.8: Temperature variation between the faulty cases and the fault free at PI  The line graph shows the relative variation in percentage terms. For point PI the increase in temperature is 120% due to fault R l as compared to the fault-free case. The simulation results show the changes in the temperature of the silicon substrate caused by these faults. If a thermal sensor, which can detect these changes in temperature, is placed in the locality of these faults, it shows the presence of these faults.  33  Chapter 4 Differential Thermal Sensors  This chapter deals with introduction to the concept of differential thermal testing, the differential sensors that were designed and the results obtained from testing one of the fabricated sensors.  4.1  Effect of temperature on mobility and threshold voltage  The current through a CMOS transistor in saturation mode be based on the Square Law model given by [29]:  (4.1)  where p is the carrier mobility, V is the threshold voltage, W is the width, and L be the t  length of the MOS device, V is the gate to source voltage of the transistor, and C gs  ox  is the  gate oxide capacitance per unit area The short channel effects assume significance at transistor lengths of 0.5pm and below. In order to avoid these effects, the minimum length of each transistor used in the temperature sensors was 1.4pm. Hence the use of quadratic model to describe the current flow through the transistor can be assumed to be valid. As the temperature across the silicon die changes, the mobility and the threshold voltage parameters of the MOS transistor are affected. The temperature dependence of mobility of the majority charge carrier in a MOS transistor is given by the equation [25]: 34  (T) = (T )-(TIT ) >  (4.2)  a  M  M  0  0  The parameter a is independent of temperature and usually set to -1.5[]. M  The rate of  change of mobility with temperature is given by:  d (T)/dT  = (T )- -(TITS'  d/u(T)ldT  = ju(T)-a IT  M  M  0  afJ  IT (4.3)  M  From Equation 4.3, the mobility of the majority charge carried decreases with an increase in temperature. The threshold voltage of a MOS transistor is given by the equation [30] V =<t> JTT  m  Q IC ss  + 2fo + AV (N ) + y(N , t ,L,W)-  ox  T  t  s  ox  J(2fo+V ) 0  (4.4)  where fo is the contact potential between gate and substrate, Q is the surface-state charge s  ss  density per unit area, fo is the Fermi potential of substrate, AVr(Ni) is the threshold shift owing to a channel implant Nj with depth d , y is the body effect coefficient depending on t  the substrate doping A^, t  ox  is gate oxide thickness, L is the channel length, and width is W  and Vo is the correction term for the threshold shift implant. [30] shows that the rate of change of threshold voltage with temperature is given by: dV ldT  = 0 IT  T  + 2</> /T + yl ^(2(j) +V )-d<f> l dT  ms  F  F  0  F  (4.5)  The temperature coefficient of the threshold voltage over a range of -100°C to 100°C is given by: TCV =\IV T  T  -dV IdT  (4.6)  T  This threshold coefficient  is used to determine the threshold voltage for a given  temperature, which is given by [30]:  35  V CT) = V (T )[1 + TCV -CT-T )] T  T  0  T  (4.7)  0  The temperature coefficient of the threshold voltage is a negative quantity and hence the value of threshold voltage decreases with an increase in temperature. At very low drain currents the decrease in threshold voltage dominates the change in drain current with temperature but at higher values of drain current the decrease in mobility dominates Fig 4.1 is the simulation results using HSPICE, where the temperature of the NMOS device is swept from -100°C to 100°C. The graph shows four points of interests, at temperatures of  -100°C, -33°C, 33°C and 100°C. For an NMOS transistor in 0.18um technology for a  value of Vgs around or below 1.4V, the higher the temperature the higher the value of the current of the NMOS device for a given value of V . For values of V g s  g s  above 1.4V, the  opposite is true, i.e., the higher the temperature the lower the value of current through it.  1m -  0  - '  J  . .-  sj I  1  1  1  1  I 0 1  1  1  1  I ZOBm 1  1  1  1  I  ' I I 400m BOOm 1  1  1  1  1  1  1  1  1  I 800m 1  1  1  1  1  ' I 1  1  1  "" 1  1  I ' 1.2  1  1  1  I ' I I ' I 1.4 1.6 1.8 Voltage X (lin) (VOLTS) 1  1  1  1  1  1  1  1  1  1  1  1  1  1  Z  I '  1  1  1  22  I  1  1  1  I ' 2.4 1  1  1  I ' 2.6  1  1  1  1  I 2.8 1  1  J  1  I  1  3  3.2  3.4  Fig 4.1: Variation of the MOS current with temperature This also holds for a PMOS transistor and forms the basis of the differential thermal sensors that were designed for this study.  36  4.2  Differential Temperature Sensor Fundamentals  The goal of a differential temperature sensor is to detect thermal gradients that appear due to heat source activation in faulty circuits. The output voltage of the sensor can be written as [18]:  V , ou  = SriT^T2)  + S c -  (  T  l  +  T  2  )  2  (-> 4  8  where Tj and T are the temperature at two points of the silicon surface, ST is the differential 2  sensitivity to temperature and S is the common sensitivity to temperature. High values of c  ST and low values of S provide high sensitivity to internal heat source activation and low c  sensitivity to ambient temperature changes. Different topologies for such sensors have been proposed targeting bipolar and BiCMOS technology [8]. The novelty of this work lies in being the first differential thermal sensor being implemented in CMOS technology. Three different types of differential sensors were designed. These are: 1) PMOS Cascoded Differential Thermal Sensor 2) NMOS Cascoded Differential Thermal Sensor 3) Differential amplifier-based Differential Thermal Sensor. These three sensors represent a subset of the sensors that can be designed. The main idea that each of these sensor uses is the change in current through the MOS transistor when there is a change in temperature. This change in current is propagated to the output of the sensor.  4.3  PMOS Cascoded Differential Thermal Sensor  The sensor circuit in Fig. 4.2 consists of six PMOS transistors and four NMOS transistors with an input current source. The circuit designed consists of three parts: the sensor  37  transistor, bias circuitry, and a high impedance cascoded output. Transistor M4 is the sensing transistor. The other nine transistors form the biasing circuit. The circuit contains two NMOS current mirrors and three PMOS current mirrors. The current source determines the gate voltage of transistor M2 and hence, also the gate voltage of M l . The current through M4 and M7 is determined by the gate to source voltage of M2 as these transistors form a current mirror. The layout is done such that the sensing transistor is placed at a large distance from the bias circuitry, i.e., the biasing circuitry is thermally isolated from the sensor. A distance of 200pm was chosen as the RC network simulation showed a negligible heating effect on the bias circuitry by a heat source placed at such a distance. In our simulations, the sensing transistor was placed near the heat source. The gate to source voltage of the sensing transistor is independent of temperature and is a constant determined by the bias circuitry. The transistor M4 is biased such that it is always in saturation and thus given by Equation 4.1. The Vgs value of the PMOS sensor is 2.3V and hence as the temperature increases the current through M4 increases. This increase in current through M4 results in a corresponding increase in current through M5 and consequently through M9. But the current through M7 is constant as it is determined by the gate voltage of M l , which remains a constant. Thus, at node V  o u t  , a difference in current is caused due to the constant  value of lag and the changing value of I49. Table 4.1, shows the simulated results when the temperature of M4 is increased by 1°C relative to the nominal temperature. The nominal temperature is 25°C and the input current is 25pA. The simulation results for the case where the temperature of all the transistors in the sensor are increased by 1 °C  are shown  in Table 4.2.The layout of the sensor is shown in Fig 4.3. As explained above, transistor  38  M3 is placed at a distance of 200 um from the bias circuitry. The layout shows the placing of the transistor. The dimensions of the transistor are given in Appendix A.  M1  J  L  M2-  & - # - C j r  J  P-t-qh  t  VDD  M4  ]  M3  M7  M8 - • V out  MO-  M9  M S  M10  T  vss  Fig 4.2: Schematic of the PMOS Cascode Thermal Sensor  The change in sensor output voltage caused by the change of temperature at M4 is given by: dV(out)/dT =  where R  out  (l -I X d8  d9  4.9  is the output resistance of the circuit at node V  out  and Ids and 1^ are the drain  currents of transistors M8 and M9. Since Ids is a constant and  has increased, a large  swing in the output voltage is caused due to the high output resistance of the cascoded output.  39  F i g 4.3: Layout o f P M O S Cascode thermal sensor  Initial  Final  Value  Value  Id4  24.97MA  25.13/xA  .16/xA  Id8  24.98/iA  25.00/iA  .02/tA  Id9  24.77/xA  24.90/M.  J3|iA  Vout  2.25V  1.13V  1.12V  Variable  Change/°C  Table 4.1: Temperature o f M 4 increased by 1 °C at ambient temperature o f 25°C  Variable  Initial Value  Final  Change/°C  Value Id4  24.96/iA  25.97MA  7.20nA  IdS  24.99MA  24.98M  .01/iA  Id9  24.77/XA  24.78/iA  8.00nA  V  2.21V  2.20V  lOmV  o u t  Table 4.2: Temperature o f all transistors increased by 1°C at ambient temperature o f 25°C  40  Results Our sensor has a differential voltage sensitivity [4] of 1.12V/°C, consumes at most 140uW of power in a 0.18pm CMOS technology for supply voltage of 3.3V at a temperature of 25°C. The layout area is 1600pm . 2  2.6  Temperature Increase (°C)  Fig 4.4: Output voltage variation of the differential sensor for different bias currents(I)  The high sensitivity of the sensor allows it to detect small increases in temperature. The differential current sensitivity of the sensing device (M4) is .16uA/°C and the common mode current sensitivity is 7.2nA/°C. Fig 4.4, shows the variation at the output node,  V  o u  t,  for different input currents, I, applied to the sensor, as the temperature of sensing device is increasing. During the normal operation of the circuit under test (CUT), the local temperature may be higher than the ambient temperature of the entire chip. In order to compensate for this, the sensor can be biased at different current values. Thus, knowing the operating temperature of a normal CUT, we can dynamically bias the sensor by adjusting the input current. The sensor is biased at the edge of the triode and saturation region in  41  order to exploit the high gain of the sensor in the saturation region. This allows for maximum amplification of small changes in temperature occurring near the sensing device.  i  1 1 1  1  -1  •  1  1  1 -800m 1  1  1  1  •i  1 1 m  -600m  i  m  -400m  1 1  1  1  m  -200m  1  1  1  1  0  m  i  1  1  1  200m  1  1  1 * 1 400m 600m 800m Parameter (lin) (dt4) 1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1  1000m  1  1.2  *  1  1 '  m  1.4  1  1  1  1  1  1.6  *i  1  1.8  •  1  1  1  1  2  1  1  1  \ j  Fig 4.5: Variation of voltage sensitivity of sensor for different ambient temperature  Fig 4.5 shows the variation of the voltage sensitivity of the sensor for different ambient temperatures. Four random ambient temperature values of-25 °C , 0 °C , 25 ° C and 50 °C were taken for simulation. This graph shows that the changes in the ambient temperature cause a minimal change in the voltage sensitivity.  42  4.4  N M O S Cascode Thermal Sensor < o o  M6  M7  M5  3—| C  M8  Vout M1  M2  M4  M9  M3  M10  <  Fig 4.6: Schematic of our NMOS Cascode Thermal Sensor The NMOS cascode thermal sensor is an inverted version of the PMOS cascode thermal sensor. As shown in Fig 4.6, the sensor circuit consists of 6 NMOS transistors and 4 PMOS transistors with an input current source. The circuit consists of three components: a sensor transistor, bias circuitry, and a high impedance cascoded output. The transistor M3 is the sensing transistor. The other nine transistors form the biasing circuit. The circuit contains three NMOS current mirrors and two PMOS current mirrors. The current source determines the gate voltage of transistor M l and hence, also the gate voltage of M2. The current through M3 and M10 is determined by the gate to source voltage of M2 as these transistors form a current mirror. The layout as shown in Fig.4.7 is done such that the sensing transistor, M3 is placed at a long distance from the bias circuitry i.e., the 43  biasing circuitry is thermally isolated from the sensor. The V  g s  of the sensing transistor is  independent of temperature and is a constant determined by the bias circuitry. The transistor M3 is biased such that it is always in saturation and the current through it is also given by Equation 4.1.  Fig 4.7: Layout of NMOS Thermal Cascode Sensor  As the temperature increases, the carrier mobility in device M3 drops due to increased thermal (lattice) scattering and its threshold voltage drops [12]. But since the transistor is in saturation, and hence the current through it is relatively high, the decrease in mobility has a much stronger effect and the current of the device decreases. This decrease in current through M3 results in a corresponding decrease in current through M5 and consequently through M8. But the current through M9 is a constant value as it is determined by the gate voltage of M l , which remains a constant. Thus, at node V  o u t  , a difference in current is  caused due to the constant value of Ids and the changing value of Id . Table 4.3, shows the 9  simulated results when the temperature of M3 is increased by 1°C relative to the nominal temperature. The nominal temperature is 25°C and the input current is 25pA. The simulation results for increasing the temperature of all the transistors in the sensor by 1°C are shown in Table 4.4.  44  "IHIHff3. - TKarH  1.4 l.Z  •  1  * i  1  1  1  1  *  1  1  •1 1  •  11  i  1 1 1  400m SOOm GOOm Parameter (lin) (dt3)  ii  11 i 11 i 700m  11  i  11 11  800m  i  11  i  11  i 11 i 11 i 900m  11 11  i  11  Fig 4.8: Output voltage variation of the NMOS sensor for different bias currents (I)  Variable  Initial Value  Final Value  AVariable/°C  Id3  14.63/xA  14.80/xA  0.16/xA/°C  Id8  14.63/iA  14.80/xA  0.16|uA/ C  Id9  14.54/iA  14.57/iA  0.03 JUA/°C  Vout  0.85V  2.21V  1.34 V / ° C  O  Table 4.3: Temperature of M3 increased by 1°C from ambient temperature of 25°C Variable  Initial Value  Final Value  AVariable/°C  Id3  1463.18nA  1463.28nA  1 nA/°C  Id8  1463.18nA  1463.28/iA  1 nA/°C  Id9  1454.43/iA  1454.50nA  .7nA/°C  Vout  0.877 V  0.875 V  2.0 mV  i  1000m  Table 4.4: Temperature of all transistors increased by 1°C from ambient temperature of 25°C  45  11 |  Results Our sensor has a differential voltage sensitivity of 1.34 V/°C, consumes at most 1 lOuW of power in 0.18pm CMOS technology for supply voltage of 3.3V at a temperature of 25°C. The layout area is 1520pm . The differential current sensitivity of the sensing device (M3) 2  is .1667uA/°C and the common mode current sensitivity of the sensor is lnA/°C. Fig. 4.8 shows the variation at the output node, V t, for different input currents, I, applied to the ou  sensor, as the temperature of sensing device is increasing. The sensitivity of the sensor for the current values of 15pA, 17.5uA and 20uA are 1.312V, 1.34V and 1.32V respectively. Fig. 4.9 shows the effect on the differential sensitivity of the sensor for  ambient  temperatures of the silicon surface of -25 °C, 0 °C, 25°C, 50 °C. We see that despite changes in the ambient temperature differential sensitivity of the sensor remains nearly constant and hence the sensor performs its function of  detecting the variations of  temperature from the ambient value.  p—i—i—[—i—I—I—I—I—i—i—i—i—|—i—i—I—I—i—I—i—I—i—]—i—i—i—i—i—I—i—I——i—I—I—I—I—I—I—I—I—|—i—i—I—I—I—I—I—I—I—|—I—I—I—I—I—I—I—I—I—|—i—r  0  ZOOm  400m  600m Parameter (lin) (dt3)  800m  1  1.Z  Fig 4.9: Variation of output voltage of sensor with variation in ambient temperature 46  M5  M6  3  1  c  -c|  M4  M3  M2  M12  M13  M14  3 — |  M1  C  I  N/111  Vout  M7  M10  M8  M9  Fig 4.10: Schematic of Differential Amplifier Thermal Sensor 4.5  C M O S Differential Amplifier Thermal Sensor  This thermal sensor consists of a differential amplifier, a current source, a voltage source, and a cascoded gain stage. As shown in Fig 4.10, the total number of transistors is fourteen. Two of these transistors, M l and M2, form a source coupled differential pair, and the other twelve are connected in a current mirror formation. The output part of the sensor is formed by four cascoded transistors and thus provides a very high output impedance to the sensor.  47  4.5.1  Differential Amplifier  A simple source coupled pair consists of two transistors M l and M 2 as shown in the Fig 4.11.  The two transistors are of equal sizes, so that p i = P2= p, where P is the trans-  conductance parameter of the transistor. Adding the dc and ac currents at the sources of M l and M2, yields Iss = ioi + i 2  (4.10)  D  Where ioi is the drain current of M l and io2 is drain current of M2.  Vg1  M2  M1  Iid1  Vg2  id2l  ISS  Fig 4.11: A simple source coupled differential amplifier The voltage applied at the gate of M l and M2 is vn and v^ respectively and their voltage difference can be written as V I D  = Vn - Vn = Vosi - V S2 G  (4.11)  When the gate of M2 is connected to ground, i.e., v^ = 0, and M l is connected to V D D , vn= V D D , that is, vn=  VDI, then  M 2 is off and M l conducts the current Iss (i-e.,  IDI  =  1DI  =  Iss). If for linear operation, M l and M 2 , are required to remain in saturation region, then  48  the point at which the input voltage turns M2 off is the same point at which all of Iss begins to flow in M l .  4.5.2 Common Mode Range Voltage When a common mode signal is applied to the gates of the transistors M l and M2, a maximum and minimum voltage exists in which the transistors fail to stay in saturation region. This range of common input signals is known as common mode range (CMR). Thus, when the range of voltage is between the CMR, the transistors of the differential amplifier remain in saturation. The objective of a differential amplifier is to amplify only the difference between two potentials regardless of the common-mode values [26]. This objective is exploited in the way the differential thermal sensor has been designed, where both the gates of the differential amplifier are supplied a common voltage  4.5.3 Working of the sensor The two transistors of the differential amplifier are laid out on chip in such a way that they are placed far apart from each other but are individually placed close to the circuit under tests as shown in the block diagram in Fig 4.12.  Sensor  I  BIAS  / \  ensor  Fig 4.12: Block diagram of the differential amplifier thermal sensor  49  The two transistors M l and M 2 , both act as the sensing transistors for this sensor. Thus, both of them can be placed separately in possible fault locations. This is shown in F i g 4.12. If we assume that the silicon surface temperature is T, and a heat source is activated, the temperature o f the C M O S transistors is increased and is given by: T 1 = T + AT1 for M O S M l T2= T + AT2 for M O S M 2  ^  mw*  "  "  '  >•  m m• *• "  *  u  m  m  a  LIT  "ii  p"ii  ii  FI  1*  Fig 4.13: Layout o f differential thermal amplifier sensor  Repeating Equation 4.8, the output voltage o f the sensor is given by  N o w replacing the value o f T l and T2 in the above equation we get t^Vou, = S , • (ATI - ATI) + S d  ct  -(T + (AT\ + AT2)/2)  (4.12)  The placement o f the temperature transducers must be such that the value o f (AT1-AT2) be different from zero when the internal heat sources are activated. In the normal working o f a differential amplifier, a small difference in gate voltages o f the source coupled transistors M l and M 2 results in a different value o f current flowing through the two transistors. This difference in current is converted into a larger difference  50  r •jj^m  of voltage by the high output impedance of the cascoded current mirrors connected to the differential amplifiers. In this case, the V  G S  of the transistors M l and M2 are the same and  hence the current flowing through them is equal as the two transistors are sized equal. As we have seen in the previous discussion in Section 4.1, as the temperature near one transistor increases, the current through it increases or decreases depending on the V value of the transistor. In our case for the NMOS transistors the value of V  G S  G S  is less than I V  and hence the current through the transistors increases with an increase in temperature. When there is a short circuit fault in the circuit under test (CUT), it may cause a rise in the temperature near the CUT. This rise in temperature is then propagated to the sensing transistor, which say in our case is M l , and there is a consequent decrease in current through the other transistor differential amplifier transistor M2, as the total sum of current through the two transistors is constant. This increase in current through M l is then propagated to transistors M3 and M4, and is mirrored to transistors M5 and M6, which then propagate this to the output transistors M10 and M9 via the current mirrors of M7 and M8 respectively. Similarly, the decrease in current through M2 is then propagated to the transistors M i l and M12. Thus, at the node V  O U T  , a difference in current is produced  between the current that sources out from transistor M i l and the current that sinks into transistor M10. Since, the output transistors M12, M i l , M10, and M9 are in cascode, the output impedance at node  V  o u  t  is very high. Since LJII has decreased and LJIO has increased,  a large swing in the output voltage is caused due to the high output resistance of the cascoded output.  51  Variable  Initial Value  Final Value  Change/°C  Id2  20.00>A  20.14^A  0.14/xA  IdlO  14.91/iA  19.80/^A  0.11/xA  Idll  20.01/xA  20.07MA  0.06/M.  Idl  20.00/xA  19.86/AA  0.14/iA  Vout  0.96V  2.40V  1.40V  Table 4.5: Increasing the temperature of M l by 1°C at ambient temperature of 25°C  Variable  Initial Value  Final Value  Change/°C  Id2  20.00jiiA  20.00/iA  0.00A  IdlO  19.91/iA  19.91/iA  0.00A  Idll  20.01/xA  20.02/iA  0.01/AA  Idl  20.00/iA  20.00jiiA  0.00/AA  Vout  0.96V  0.95V  0.01V  Table 4.6: Increasing the temperature of all transistors by 1°C at ambient temperature of 25°C  Fig 4.14, shows the variation of the output voltage due to a defect in CUT1 causing a temperature rise in transistor M l .  52  -ZOOm  -100m  0  100m  ZOOm  300m 400m SOOm Parameter (lin) (dtl)  GOOm  700m  BOOm  900m  Fig 4.14: Output voltage variation of the differential sensor for different bias currents (I)  Results Our sensor has a differential voltage sensitivity [4] of 1.40V/°C, consumes at most 140uW of power in a 0.18pm CMOS technology for supply voltage of 3.3V at a temperature of 25°C. The layout area is 2320pm . The advantage of using this structure over the thermal cascode sensors is that two transistors can be used as transducers in this structure whereas in the other sensors we can use only transistor as a transducer. This effectively doubles up the area covered by the sensor, albeit with a smaller area overhead. The differential structure also provides higher noise sensitivity, as the common noise at the gate of the two transistors is not amplified.  53  1000m  800m  p—i—i—|—i—i—i—i—i—i—i—i—i—|—i—i—i—i—i—i—i—i—i—|—i—i—i—i—i—i—i—m—|—i—i—i—i—i—i—i—i—i—[—i—i—i—i—i—i—i—i—i—[—i—i—i—i—i—i—i—i—i—|—i—r-ZOOm 0 ZOOm 400m GOOm 800m 1 P a r a m e t e r (lin) ( d t l )  Fig 4.15: Variation of output voltage with variation in ambient temperature  4.6  Testing of designed sensor  The PMOS cascode temperature sensor shown in Fig 4.16, was fabricated in 0.18um technology.  •• v  out  Fig 4.16: PMOS Cascode Temperature Sensor  54  The testing of the chip involved the comparison of the simulation results for the sensor and the chip measurements. Fig 4.17 shows the simulation results for the designed differential sensor, when a 10 M Q probe is attached to the sensor output for different input currents. The designed sensor has a differential thermal sensitivity of 1.12 V / °C. This implies that when the temperature around the sensing transistor changes by 1°C, the output voltage changes by 1.12 Volts. The test setup used included an oscilloscope with an input impedance of 10 M Q , a high precision digital multi-meter, a current source/sink, and a bread board. Two probes with impedance of 10 M Q and 1 M Q were used during the testing. The current source/sink was created using LM334, which is a three terminal device. The heat source was generated using a 16pm/lpm NMOS transistor connected in diode configuration.  2.6  Temperature Increase ( ° C )  Fig 4.17: Output voltage variation of the differential sensor for different bias currents (I)  55  4.6.1 Test Setup The test procedure involved the use of an external current source which could produce current values within the range of 5uA to 50uA. To do so, a three terminal current source/sink device, LM334, manufactured by National Semiconductors, was used. The device is a three terminal adjustable current source featuring 10,000:1 range in operating current, excellent voltage regulation and a wide dynamic current range of IV to 40V [24]. Applications for the current source  include bias networks, surge protection, low power  reference, ramp generation, L E D driver, and temperature sensing. The main features are: •  Operates from IV to 40V  •  0.02%/ V current regulation  •  Programmable from 1 uA to 40uA  •  True 2 terminal operation  56  The total current through the LM334, is the sum of the current through RSET (IR) and the LM334's bias current (IBIAS)- The final current through the current source is calculated and simplified to [24]: ISET= (VR/RSET)* 1.059= 227/RSET uV/°K  (4.13)  The first stage of testing involved the biasing of the sensing circuitry at the edge of the saturation region, so that as we increase the temperature the sensor enters the region of highest gain, and we can obtain the highest possible change in output voltage for a given change in temperature. For detecting this biasing point, current through the current source is swept and the voltage variation is noticed. The region of the highest slope is the saturation region of the sensor.  57  Volatge vs Current 3.5  n  3  > ro o  *J  >  2.5 -  Volatge c h i p l (V)  2  Voltage chip2(V)  1.5 -  Simulation  1 0.5 0 10  20  30  4  Current (uA)  Fig 4.19: Voltage vs Current variation for a 10 M Q probe. A 10 M Q resistance is placed at the output of the sensor. In Fig 4.19, we see the simulation results of the sensor showing a high sensitivity from 20uA to 25 uA, and simulations show that the PMOS sensor must be biased at 25 pA, to cause a maximum rate of change in voltage. On-chip measurements of sweeping the current of the sensor are also shown in the Fig 4.19. The measured results for two chips show the maximum rate of voltage change for one chip to be from l u A to 2.5uA and for another to be from 3pA to 4.3u,A. These changes imply higher output impedance at the output node, as compared to the simulation results. It also shows that the bandwidth of the current sweep is reduced by around 230 % for chipl and around 284 % for chip2. It further shows a change in the region where the chip goes into saturation as around 1000% for chipl and chip 2. To understand this we must look into the cascode configuration of the sensor. Fig 4.20 shows the cascode structure.  58  VDD  Bias3  Bias2  M4  c]  M3  out  V  Biasl  in  V  M2  1  M1  vss Fig 4.20: Cascode configuration of the output The minimum output voltage that will keep all the transistors in saturation will be limited by the point at which M2 becomes unsaturated. This occurs when VGS2-VTHN2 VDS2 =  where VDS2  VGS2  is the gate to source voltage of M2,  VTHN2  is the threshold voltage of M2 and  is the drain to source voltage of M2. M2 becomes saturated before M l because the  impedance of the output node is much higher than the impedance at the drain of M l and thus the voltage at the output will be decreasing at a much faster rate than the voltage at drain of M l . This is equivalent to saying that since the gain from the input to output is much higher than the gain from the input to the drain of M l , as the input voltage rises, the output voltage decreases faster than that at the drain of M l .  59  The maximum positive voltage that can appear at the output of the cascode while maintaining all the transistors in saturation will be limited by the point at which M3 becomes non-saturated. The maximum positive voltage occurs when VsG3"  VTHP3 VSD3  where  VSG3  =  is the source to gate voltage of M3,  V HP3 T  is the threshold voltage of M3,  VSD3  is the source to drain voltage of M3. Expressed in an another way, this can be written as Vo(max) =  V G3+VTH3 G  where Vo(max) is the maximum output voltage, and  V H3 T  VGG3  is the gate voltage of transistor M3,  is the threshold voltage of transistor M3.  When a 10 M Q probe is attached to the output of the cascode configuration, the rate of change of output voltage is much faster as compared to a smaller probe impedance. In Fig 4.19  as we increase input current supply, the bias voltage ,i.e., the gate voltage of M9  (V G9)also increases. But at the same time the source voltage of M9 is also increasing due G  to increased input current supply. Hence, the overall increase in the gate to source voltage of M9 is minimal. But the increase in the threshold voltage of M9 causes an increase in the threshold voltage of M9 due to body effect phenomenon. Also process variations can cause an increase in the threshold voltage of M9. This phenomenon combined with body effect can make threshold voltage of transistor M9 to become higher than the gate source voltage of M9. And as a consequence transistor M9 enters cut-off region. As observed in Fig 4.19, the output of the sensor does not saturate to 2.4 V , as seen in the simulations, but it goes to 3.3 V . This is only possible if transistor M9 enters cut-off. So when we attach lower impedance probes to the output of the sensor, the same phenomenon should be observed but at a slightly lower rate. This hypothesis is validated by experimental observations.  60  From Fig 4.19 we see that the output of the sensor becomes saturates very fast and the output voltage reaches a high value very fast for very low value of input current. Thus M9 reaches cut off stage very fast and the sensor output becomes stuck at 3.3V. The widths of the NMOS transistors M9 and M l 0 are 2pm and 16pm and width of the PMOS transistors M7 and M8 are 20pm each. This implies a higher impedance of the two NMOS transistors as compared to the PMOS transistors, but a decrease in width in the NMOS transistors, due to process variations, especially M9 would imply a much earlier saturation for these transistors as compared to what it would be if there was no change in their widths.  Current vs Voltage  •  •Voltage( Chipl)  2  5 1  Voltage( Chip2)  o  >  0 0  20  40  Simulation  Current ( u A)  Fig 4.21: Voltage versus Current for a 1 Mega Ohm probe. From  Fig 4.21, we observe that the actual measurements for chipl and chip2, have a  steady voltage change from lOuA to 20uA, thus showing a much higher impedance than the designed output resistance of the sensor, which confirms the previous observation in Fig 4.19.  61  Voltage vs Current  voltage(2.2M) voltage(1 M) voltage (3.3 M) voltage(IOM)  Current ( uA)  F i g 4.22: Simulation results showing the effects o f attaching a 1, 2.2, 3.3,10 M Q resistor to the sensor output.  Voltage vs Current  -*-Voltage(2.2 M) -»-Voltage(1 M) Volatge(3.3 M) ——Voltage(IOM)  40 Current( uA)  F i g 4.23: Chip results showing the effects o f attaching a 1, 2.2, 3.3,10 M Q resistor to the sensor output.  From F i g 4.22 and F i g 4.23, we see that the chip has a higher output than as was designed in the simulations.  This again shows the effect o f process variation and transistor  mismatches on the designed sensor. 62  Voltage vs C u r r e n t 5 0 0 0 -i  V o l t a g e ! V)  Fig 4.24: Voltage vs Current of heat source: Simulation and Chip result From Fig 4.2, we see the measurement versus simulation results for varying the voltage across the heat source which is a 16um/lum NMOS transistor connected in diode configuration when the ambient temperature is 27°C.  There is a 17 % decrease in the  current through the heat source in the chip measurements and a corresponding 17% decrease in power dissipated when the maximum voltage of 3.3 V is applied to the heat source. The actual power being consumed is 11.26mW while a value of 13.9mW is expected from simulations. Now to understand the effects of the power consumed at a sensor transistor at a distance of 11.4pm we can derive it by the RC network simulation. A 1°C rise in temperature at this distance caused by the heat source for a power consumption of 11.26mW. The following graph shows the effect on the output voltage, when the heat source is switched on. This shows that the output voltage is not affected by the heat source being turned on. The possible reasons for this are:  63  1) Process variations and transistor mismatches have caused a change in the sensitivity of the designed sensor, and thus it shows very little effect when the temperature is increased. 2) The power supply reaching the sensor is less than 3.3V due to resistance of the ground lines, pads, and the V D D line. The following graph shows simulation results for the variation of the output voltage as we decrease the voltage across the sensor. This decrease in voltage starts matching the observed output variation of the sensor.  Voltage vs Current •Voltage(Vdd=2.4 ) Voltage(Vdd=2.7  ) 20  40 Current(uA)  60  80  Voltage(Vdd=3.0 ) — — Voltage(Vdd=3.3 )  Fig 4.25 : Voltage vs Current when Voltage across the sensor is changed 4.6.2  Monte Carlo  Simulations  MOS ICs have both a major and minor statistical distribution of manufacturing tolerance parameters. The major distribution is the wafer to wafer and run-to-run variation. The minor distribution is the transistor to transistor process variation. The minor distribution is responsible for critical second-order effects, such as amplifier offset voltage and flip-flop preference [33].  64  Worst case analysis is used for design and analysis of MOS and BJT ICs. Taking all variables to their 2-sigma or 3-sigma worst case values simulates the worst case. The parameter variations allow the circuit simulator to predict the actual circuit response to the extremes of the manufacturing process. The physically measurable model parameters are called skew parameters because they are skewed from a statistical mean to obtain a predicted performance variation [33]. Skew parameters are usually independent of each other, so that a combination of parameters can be used to represent worst case values. Typical skew parameters for CMOS technology include: X L - Polysilicon C D (critical dimension of poly layer representing the difference between drawn size and actual size.) XW  n  , X W - Active CD (critical dimension of active layer representing the difference P  between actual and drawn sizes.) T O X - Gate oxide thickness D E L V T O n ,  D E L V T O : Threshold voltage variation p  The process parameters were modeled with Gaussian random variables, with variances of 3a = 10% for the device model parameters, and 5% for the geometric sizes of the MOS transistors. The accuracy of Monte Carlo simulations depends on the generation of correct probability distributions of the random values of transistor values. For a large number of samples (> 1000 samples), the sample mean and variance is close to the parameter's actual mean and variance. Table 4.7 shows 3a the worst case variations that were taken into account while doing the Monte Carlo simulations.  65  Model Parameter  Symbol  3a  1  Oxide Thickness  Tox  10%  2  Substrate doping  NSUB  10%  3  Substrate Mobility  Mo  10%  4  Threshold voltage  VTO  10%  5  Junction Depth  Xj  10%  6  Transistor Width  W  5%  7  Transistor length  L  5%  Table 4.7: Device model parameter The following graph, Fig 4.26, shows the effect of variations of the above parameters by the quantities as specified in the table. The graph show that the variation of the output voltage with different input currents for a different variations of the parameters. We see that for some variation of the parameters the output voltage saturates very rapidly and for some variations in the parameters the change in output voltage is very minimal. Thus the output voltage shows a high variation as a result of changes in the transistor parameters. The next graph, Fig 4.27, shows the variations in the output voltage for the temperature increase caused by the heat source. Here we see that the process variations can affect the sensor performance and cause a decrease in the sensitivity and in some case make the sensor circuit ineffective to the increase in temperature. These simulations show an exact matching between the desired sensor and the simulated sensor and we can thus see that process variations have clearly affected the performance of the sensors.  66  • [ | - . - i - n - ) - r r r - r r r T - T - r i T r i i p v r i T r r •I-TTTTT-T J T T T T ; T H T | I I H ] I I I T ] I I I I J T I M | I T T I | T T I I | M I I | I I I T J I r I T p n  0  2u  4u  6u  8u  T T r I I I | H I I I I I I I ] M I I | I I I I | I T T T J T I  10u 12u 14u 16u 18u 20u 22u 24u 26u 28u 30u 32u 34u 36u 38u 40u 42u 44u 48u 48u 50u Parameter (Itn) (refcurr)  Fig 4.26: Monte Carlo simulation for varying the input current supply  ^  2 i  -20  -18  -1G  -14  -12  -10  r l i i r i j r i r i | i i i r | i i i i j i r i r i i ri r | i i i i | i r i i | i i i i | i i i i | i -6  -4  -2 0 2 Parameter (tin) (dt3)  4  6  8  10  12  14  16  I-I  i'j  i-  Fig 4.27: Monte Carlo simulations for increase in local temperature over ambient  67  Chapter 5  Conclusion The purpose of this thesis was to explore the idea of using CMOS differential thermal testing of integrated circuits and to use this idea as a complementary testing technique to IDDQ. A brief introduction to IDDQ was presented and the limitations of single threshold IDDQ were stated. The first CMOS differential thermal sensors were designed, simulated, fabricated and tested. Simulation and silicon measurement results were presented. 5.1 Conclusions The concept of thermal testing of integrated circuits is an off-shoot of the problems faced by the single threshold IDDQ testing. . The main disadvantage of IDDQ is that it requires a high V to be effective and is only applicable to static circuits. As CMOS technologies scale t  down, background leakage current increases inexorably, primarily due to device subthreshold leakage [14]. As a result, conventional single-threshold pass/fail IDDQ testing may no longer be valid even for 0.25-micron technology [15]. Moreover, some analog circuits draw constant current to operate. Hence, IDDQ testing is not effective for these circuits [9]. A number of alternatives to single threshold IDDQ testing have been looked into. These solutions are both at technology and design levels [16]. This work provides a broad based idea of on-chip and off-chip thermal testing methodologies and their advantages and disadvantages. On-chip thermal testing is of two general types, absolute and differential thermal testing. This thesis looked into differential testing as a complementary methodology to IDDQ testing. Three differential temperature sensors were designed,  68  simulated, and fabricated in 0.18u.m CMOS technology. The three designed sensors were a PMOS cascode thermal sensor, a NMOS cascode thermal sensor, and a differential amplifier thermal sensor. These were then implemented in 0.18um CMOS technology. Careful layout techniques were used as part of the design process.  The PMOS cascode  thermal sensor had a differential sensitivity of 1.12 V/°C, and occupied an area of 1600um  2  and consumed a power of approximately 140u.W . The NMOS cascode thermal sensor had a differential sensitivity of 1.34 V/°C, and occupied an area of 1520um and consumed a 2  power of approximately 1 lOuW. The differential amplifier thermal sensor had a differential sensitivity of 1.40 V/°C, and occupied an area of 2320pm and consumed a power of 2  approximately 190uW. Further, research was done into the study of faults induced in an operational amplifier, and with respect to the placement of sensors around an operational amplifier. A testing methodology was proposed wherein the results of the temperature were read off the chip using boundary scan architecture. The fabricated sensors were tested and the results evaluated. The results were found not match the desired results. This was thoroughly investigated and a reason put forward for this. This helped in formulating a design strategy to be used in further sensor design. 5.2 Future Work Thermal testing of integrated circuits is a complex topic and requires a broad based understanding of thermodynamics, device physics, and analog integrated circuit design. To make this method more suitable for industrial purposes, future research must focus on the following aspects: •  More work will have to be done and much more thoroughly to the working of these sensors and how they respond to stress, and what their reliability is with time. Once 69  these tests are done, the sensor can be used as an intellectual property block and placed across the surface of the chip. More research must be done into the study of heat flow through the silicon substrate and this must be incorporated into the Spice and Spectre models. An on-chip implementation of the sensors used for testing complex integrated circuits would validate using the principles that have been put forward in this work. Future research efforts would help in knowing the area overhead, routing overhead, and in determining how effective this methodology is for industrial application.  70  References  [1]  J. Rabaey, Digital Integrated Circuit Design: A design perspective, Prentice-Hall  Inc,pp. 675-678, 1996. [2]  M . Abramovici, M. Breuer, and A. Friedman, Digital Systems Testing and Testable  Design, Engle-wood Cliffs, NJ: Computer Science Press, pp.457-458,1990. [3]  J.M. Soden, C.F. Hawkins, R.K. Gulati, and W. Mao ," IDDQ Testing: A Review",  Journal of Electronic Testing: Theory and Applications, Vol.3, No.4, pp. 291-303, Dec. 1992. [4]  Manoj Sachdev, " Deep Sub-micron IDDQ Testing: Issues and Solutions",  Computer Design and Test Conference, pp. 271- 278,1997. [5]  Carver A. Mead, " Scaling of MOS Technology to Submicrometer Feature Sizes",  Analog Integrated Circuits and Signal Processing, vol. 69, pp. 9-25,1994. [6]  B.Davari, R.H. Dennard, and G.G. Shahidi, " CMOS Scaling for High Performance  and Low Power - Next Ten years", Proceedings of the IEEE, vol. 83, No.4, pp. 595-606, April 1995. [7]  J. Altet and A. Rubio, " Built-in dynamic thermal testing technique for ICs",  Electronic Lett., vol. 32, no. 21, pp. 1982-1984, Oct. 1996. [8]  J. Altet et. all, " Differential Thermal Testing: An approach to its feasibility", / .  Electronics Testing: Theory and Applications 14, pp. 376- 385, Oct 1993. [9]  J.M Soden and R.E. Anderson, " IC Failure analysis: Techniques and tools for  quality and reliability improvement", Proc. IEEE, vol. 81, pp. 703 - 715, May 1993.  71  [10]  V.Szekely, " Thermal Monitoring of Microelectronic structures" , Microelectronics  J.,vo\. 25,pp. 157-170, 1994. [11]  K.Arabi and B. Kaminska, " Built in temperature and current sensors for on-line  oscillation-testing", Proc. Pacific Rim Itnl. Symp. Fault Tolerant Computing, pp. 198-202, 1993. [12] V.Szekely, C. Marta, Z. Kohari, and M . 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Tamamoto,  "Differential Thermal Testing: An Approach to its Feasibility", Journal of Electronic Testing: Theory and Applications, Vol. 14, pp. 57-66, 1999. [23]  A. Wong, A. Ivanov, and J. Altet," Thermal Testing of Analog Integrated Circuits",  Technical Report ECE-TR-00-001, [24]  National  University of British Columbia, December 2000.  Semiconductors  http://www.national.com/ads-  cgi/viewer.pl/ds/LM/LM 134.pdf. [25]  M.J.M Pelgrom, C.J. Duinmaijer, and A.P.G. Welbess, "Matching Properties Of  MOS Transistors ",IEEE Journal of Solid-State Circuits, Vol. 24, Issue: 5 , pp. 1433 -1440, Oct. 1989 [26]  A. Sedra and K. Smith, Microelectronic Circuits, Oxford University Press, 4  th  edition, 1997. [27]  P. Allen and D.R. Holberg, CMOS Analog Circuit Design, Oxford University Press,  1987.  73  [28]  N. Weste and K. Eshragahian, Principles of CMOS VLSI Design: A systems  perspective, Addison-Wesley Publication Co., Oct. 1994. [29]  D. Johns and K. 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[32]  Avanti," Star-HSPICE Manual", Release 2000.4, December 2000.  74  Appendix A Transistor sizes for PMOS Differential Sensor  Transistor No.  Width/Length  Ml  15um/1.4um  M2  15um/1.4Lim  M3  30um/1.4Lim  M4  30um/1.4Lim  M5  16um/1.4|j.m  M6  16um/1.4Lim  M7  20.2um/1.4urn  M8  12um/1.4Lim  M9  2.4Lim/1.4um  M10  10Lim/1.4um  Appendix B Transistor sizes for NMOS Differential Sensor  Transistor No.  Width/Length  Ml  16um/1.4um  M2  16um/1.4um  M3  32um/1.4um  M4  32p.ni/l.4um  M5  16u.m/1.4um  M6  16u.m/1.4um  M7  2um/1.4um  M8  10u.m/1.4um  M9  16um/1.4um  M10  32um/1.4u.m  Appendix C Transistor sizes for Differential Amplifier based Differential Sensor  Transistor No.  Width/Length  Ml  32u.ni/l.4Lim  M2  32um/1.4um  M3  24Lim/1.4Lim  M4  24um/1.4Lim  M5  24um/1.4Lim  M6  24Lun/1.4Lim  M7  12Lim/1.4Lim  M8  12LUTI/1.4LUTI  M9  12Lim/1.4Lim  M10  12Lim/1.4Lim  Mil  32|j.m/1.4Lim  M12  20um/1.4LLm  M13  24Lim/1.4Lim  M14  24um/1.4Lim  

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