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An all-digital VLSI minimum shift keying modem Lee, Kam O. 1992

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AN ALL-DIGITAL VLSIMINIMUM SHIFT KEYING MODEMByKam 0. LeeB.A.Sc. (Engineering Physics) University of British Columbia, 1988A THESIS SUBMmED IN PARTIAL FULF]LMENT OFTHE REQUIREMENTS FOR THE DEGREE OFMASTER OF APPLIED SCIENCEinTHE FACULTY OF GRADUATE STUDIESELECTRICAL ENGINEERINGWe accept this thesis as conformingto the required standardTHE UNIVERSiTY OF BRITISH COLUMBIAJune 1992© Kam 0. Lee, 1992In presenting this thesis in partial fulfilment of the requirements for an advanced degreeat the University of British Columbia, I agree that the Library shall make it freely available forreference and study. I further agree that permission for extensive copying of this thesis forscholarly purposes may be granted by the head of my department or by his or her representatives.It is understood that copying or publication of this thesis for financial gain shall not be allowedwithout my written permission.Electrical EngineeringThe University of British Columbia2075 Wesbrook PlaceVancouver, CanadaV6T 1W5Date: /Z/sEPT /‘1ABSTRACTA general purpose all-digital VLSI minimum shift keying (MSK) modem with novelreceiver synchronization capability is designed and implemented. The modulated output is binaryand has a centre carrier frequency to bit rate ratio of 5.75. Demodulation is performed semi-coherently using a one-bit observation interval. Other on-chip functions include carrier detection,automatic self-test, and internal loopback. Fabricated with 1.2 .tm CMOS standard celltechnology, the chip can operate at a maximum clock speed of 50 MHz, rendering 0.19 Mbpsbinary transmission with the carrier centred at 1.1 MHz.Modulation is provided with a data-controlled square-wave generating digital circuit. Noon-chip RAM is needed. This approach also has the advantages of robustness and phase stability.For ease of implementation, demodulation is accomplished with a binary quantizedcorrelation-receiver. The theoretical BER performance of this discrete-time all-digital demodulatorin AWGN with perfect synchronization is approximately 2 dB poorer than that of a continuous-time optimal detector. The demodulator’s susceptibility to imperfect carrier and bitsynchronization is also formulated.Carrier phase recovery and bit timing extraction are provided by three novel first-orderdigital phase-locked loops (DPLLs). Owing to the special phase-detection techniques employedin these DPLLs, no front-end filtering structures are required. Markovian analyses of the errorcharacteristics of these DPLLs are presented.A compact almost-all-digital modem unit based on the MSK modem chip is built tofacilitate data communications over intrabuilding powerlines at 19.2 kbps using 105.6 kHz and115.2 kHz carriers. The measured BER performance of this powerline modem in AWGN isapproximately 2 dB below theoretical prediction. When used for transmission over actualintrabuilding powerline networks where impulse noises are prevalent, the modem’s performancedepends on the powerline phase relationship between the transmit and receive points, powerlineload profile, and, to a lesser extent, channel’s physical length. Under normal circumstances witha transmitter output level of 70 dBmV rms, the BER typically ranges from 102 to iO for crossphase transmission, while a BER of iO or less may be attained for same-phase transmission.11TABLE OF CONTENTSABSTRACT iiLIST OF FIGURES viiLIST OF TABLES xiACKNOWLEDGEMENTS xii1. INTRODUCTION 11.1 Purpose 11.2 Motivations 21.3 Applications 21.4 Scope 32. THEORY OF MINIMUM SHWF KEYING 52.1 MSK Modulation 52.2 MSK Demodulation 82.2.1 Methods of MSK Detection 92.2.2 Semi-Coherent Demodulation of MSK 92.3 Analog Vs Digital 143. A DIGITAL ARCHITECTURE FOR MSK SIGNALLING 153.1 Modulation Structures 153.1.1 An All-Digital MSK Modulator 183.1.2 Performance Analysis 193.2 Demodulation Structures 193.2.1 Digital Correlation 203.2.2 Performance Analysis 231113.3 Carrier Detection 323.4 Built-In-Self-Test 334. ALL-DIGITAL RECEIVER SYNCHRONIZATION 354.1 Carrier Synchronization 354.1.1 Suppressed Carrier Recovery 364.1.2 Phase-Locked Loop Basics 364.1.3 An All-Digital MSK Carrier Synchronizer 374.1.4 Performance Analysis 424.2 Bit Synchronization 504.2.1 An All-Digital MSK Bit Synchronizer 514.2.2 Decision-Aided Phase Detection 534.2.3 Performance Analysis 545. DESIGN METHODOLOGY AND CHIP SPECIFICATIONS 575.1 Design Methodology 575.2 Digital Design 585.3 Prototyping 595.4 Modem Chip Design Specifications 605.4.1 Functions And Features 605.4.2 1/0 Specifications 615.4.3 System Clock Requirement 645.4.4 Internal Circuitry 655.4.5 Training Requirement 665.4.6 Modem Capability 666. VLSI IMPLEMENTATION OF THE MODEM 686.1 VLSI Methodology 686.2 VLSI Implementation Issues 696.2.1 Testability 69iv6.2.2 Clock Distribution.716.2.3 Power/Ground Allocation 726.3 Detailed Circuit Description 726.3.1 Top-level 726.3.2 Block Level 737. THE MAKING OF A POWERLINE MODEM 847.1 Powerlines As Communication Channels 847.2 Modem System Architecture 877.3 Modem Chip Application 907.4 DTE Interface 907.5 Powerline Interface 927.6 System-Level Design 958. TESTING AND PERFORMANCE EVALUATION 1008.1 Functional Verification Of Modem Chip 1008.1.1 Built-In Self-Test 1008.1.2 Loopback Self-Test 1008.1.3 Point-To-Point Transmission Test 1028.2 Modem Performance In A Controlled Environment 1028.2.1 Signal Quality 1038.2.2 Performance In AWGN Environment 1038.3 Modem Performance On Powerline Channels 1078.3.1 Performance Over A Small Area 1098.3.2 Performance Over A Large Area 1139. CONCLUSIONS AND DISCUSSIONS 1189.1 Conclusions 1189.2 Discussions 1199.2.1 Technological Limit 119v9.2.2 Baud Rate Selectivity 1209.2.3 Design Shortcomings and Remedies 1209.2.4 Other Improvements and Further Investigations 121REFERENCES 123APPENDIX: SCHEMATICS OF MODEM CHIP 128viLIST OF FIGURESFigure 2.1: MSK waveforms (center frequency = 110.4 kHz, bit rate = 19.2 kbps) 6Figure 2.2: MSK signal constellation 7Figure 2.3: MSK power spectrum (center frequency = 110.4 kHz, bit rate = 19.2kbps) 8Figure 2.4: Bit-by-bit semi-coherent reception of MSK 10Figure 2.5: Decision regions for semi-coherent MSK 11Figure 2.6: Theoretical BER performance of coherent PSK, coherent FSK, and semi-coherent MSK in AWGN 12Figure 2.7: Effect of imperfect synchronization on the BER performance of semi-coherentMSK in AWGN 14Figure 3.1: Functional block diagram of the MSK modem chip. 15Figure 3.2: An analog frequency shift keying modulator 16Figure 3.3: An analog I-Q type MSK modulator 16Figure 3.4: Table look-up sinewave generator 17Figure 3.5: A Johnson counter based sinewave synthesizer 17Figure 3.6: A numerically controlled oscillator (NCO) 17Figure 3.7: Architecture of the semi-coherent MSK demodulator 20Figure 3.8: An analog integrate-and-dump correlator 21Figure 3.9: A multi-bit digital correlator 21Figure 3.10: A one-bit digital correlator 21Figure 3.11: A binary partial detector for coherent FSK or semi-coherent MSK 23Figure 3.12: Subbit error caused by channel noise 24Figure 3.13: BER performance of the binary partial demodulators for coherent PSK,coherent FSK, and semi-coherent MSK 28Figure 3.14: Theoretical BER performance of the semi-coherent MSK binary demodulatorunder different conditions in AWGN 29Figure 3.15: Detection degradation effect of imperfect bit synchronization 30Figure 3.16: Built-in self-test pattern generation 33viiFigure 4.1: Squaring-loop carrier syncozer 35Figure 4.2: Costa’s loop carrier synchronizer 35Figure 4.3: Structural representation of a phase-locked loop 37Figure 4.4: Carrier synchronization on the MSK modem chip 38Figure 4.5: Phase detection for carrier recovery in the MSK modem 39Figure 4.6: Phase detection errors due to reception of a non-tracking frequencycomponent 39Figure 4.7: Lead/lag errors over one bit interval 40Figure 4.8: Improved detection of phase error 41Figure 4.9: Error states of the all-digital MSK carrier synchronizer 43Figure 4.10: State transitions in the all-digital MSK carrier synchronizer 43Figure 4.11: Simplified error state transition diagram for the MSK carriersynchronizer 46Figure 4.12: Computed output phase variance of the carrier synchronizer 47Figure 4.13: Early-late gate bit synchronizer 50Figure 4.14: Effect of carrier phase error on demodulated bit streams 51Figure 4.15: The all-digital bit synchronizer on the MSK modem chip 52Figure 5.1: Overall chip design and development methodology 57Figure 5.2: MSK modem prototype 60Figure 5.3: Transmit data transfer timing for 19.2 kbps transmission 61Figure 5.4: Receive data transfer timing for 19.2 kbps transmission 62Figure 5.5: Calculation of system clock frequency. .. 65Figure 6.1: VLSI design methodology 68Figure 6.2: System clock distribution tree 71Figure 6.3: Block diagram of the timing generator. . . 76Figure 6.4: Timing clocks and strobes 76Figure 6.5: Loopback configuration for self-test 82Figure 7.1: Model of intrabuilding powerline channels 84Figure 7.2: Intrabuilding powerline transmission paths 86Figure 7.3: MSK powerline modem I/O interface 87vmFigure 7.4: Functional block diagram of the powerline modem. 88Figure 7.5: Implementation of the powerline modem 89Figure 7.6: Schematic of the DTE interface subcircuit 91Figure 7.7: State diagram for RS232 interfacing 92Figure 7.8: Schematic of the powerline interface circuit 93Figure 7.9: Schematic of the transmit signal processing circuit. 93Figure 7.10: Schematic of the receive signal processing circuit. 96Figure 7.11: Board-level schematic of the MSK powerline modem. 96Figure 7.12: Insertion of a scrambler/descrambler circuit into the modem 98Figure 7.13: Enhanced modem with built-in scrambler/descrambler and codec 98Figure 8.1: Chip-level loopback BER test 101Figure 8.2: BER monitoring for inter-chip communications 102Figure 8.3: Modem transmit signal spectrum (vertical scale = 10 dB/div, horizontal scale= 10 kHz/div) 103Figure 8.4: Receive bit clock timing jitter (vertical scale = 5 Vldiv, horizontal scale = 10I.ts/div) 104Figure 8.5: Spectral line at receive bit clock frequency (vertical scale = 5 dB/div,horizontal scale = 250 Hzjdiv) 104Figure 8.6: Evaluation of modem performance in an AWGN channel 104Figure 8.7: BER performance of the MSK modem in an AWGN environment 106Figure 8.8: BER/BLKER measurement over intrabuilding powerlines 107Figure 8.9: Software-based packet error rate measurement 109Figure 8.10: BER/BLKER -- transmitter and receiver on power-bars 50 ft apart in thelab 111Figure 8.11: BER and BLKER performance-- transmitter and receiver on one power-barin the laboratory 111Figure 8.12: Locations of various access points in the building 113Figure 8.13: BER performance of the powerline modem for “long-distance”communications 114Figure 8.14: BLKER performance of the powerline modem for “long-distance”ixcommunications 114Figure 8.15: More BER measurements over a large area 114Figure 8.16: Packet error/loss rate for long-distance communications using the powerlinemodem 117xLIST OF TABLESTable 6.1: Macro blocks in the modem chip 74Table 6.2: Mode select truth table 74Table 7.1: 1/Os of the MSK powerline modem board 87Table 8.1: Packet error/loss rate for transmissions between two power-bars 50 feet apartin the laboratory 110Table 8.2: Power phase on various AC outlets in the building 114xiACKNOWLEDGEMENTSThanks are due to Dr. Robert W. Donaldson for his supervision, guidance, andsuggestions. I am very grateful to Aries Wong and Barry Buternowsky for their assistance in theconstruction and testing of modem prototypes. I am also indebted to Dave Gagne who, as a VLSICAD system administrator, has been very helpful and patient. Last but not the least, I would liketo dedicate this thesis to my parents: Yuk C. Lee and Ngoi H. Lee; without their support,encouragement, and teaching, this work would not have been accomplished.Financial support during the course of my M.A.Sc. study at the University of BritishColumbia has been kindly provided by the National Science and Engineering Research Councilof Canada.XII1. INTRODUCTIONNetworking facilitates the sharing and exchange of information among computing entitiessuch as mainframe computers, workstations, PCs, file servers, and print servers, which specializein the processing, acquisition, retrieval, and storage of information. Networking requires the useof communication protocols. They are rules governing the form, function, and mechanism ofnetwork messaging. CCITT’s OSI Reference Model is the international standard ofcommunication protocol architecture. The model comprises seven layers, each corresponding toa set of well-defined functions. The bottommost layer, known as “physical layer,” provides themost basic yet most important and essential function of transmitting digital data across thecommunication channel between two nodes.The physical layer implementation of a data network is largely determined by thetransmission characteristics of the channels. A variety of physical channels exists. For example,in a lOBaseT Ethernet, computers are linked by unshielded twisted-pair copper wires;connectivity in a fibre LAN is achieved with optical fibres; and a wireless LAN makes use ofnothing but free space as the transmission medium. In general, “digital” channels such as opticalfibres and coaxial cables have a wide bandwidth and can therefore accommodate basebandtransmission. On the contrary, “analog” channels have a narrow bandwidth and require passbandtransmission using a device known as “modem.” In the transmit direction, a modem modulatesby translating digital data into sinusoids; in the receive direction, it demodulates by extractingdigital information from received sinusoids. The wireless LAN is an example that utilizesmodems at the physical layer for transmission and reception.1.1 PurposeMinimum Shift Keying (MSK), one of the well-known modulation schemes, has theadvantages of bandwidth efficiency, phase continuity, and constant signal envelope. This thesisinvolves the research and development of an all-digital MSK modem chip. The chip performsMSK modulation and demodulation, with built-in carrier phase recovery units, bit synchronizer,and carrier detection circuit. The centre carrier frequency to bit rate ratio is internally fixed at15.75. Demodulation is semi-coherent using a one-bit observation interval. Depending on thesystem clock frequency, the modem’s baud rate and centre carrier frequency can reach as highas 0.19 Mbps and 1.1 MHz, respectively.1.2 MotivationsDigital implementation has several advantages: (1) the shortcomings of analog componentssuch as aging, temperature drift and need for adjustment are avoided; (2) digital circuits, ingeneral, are easier to design, analyze, as well as troubleshoot, and are more predictable andreliable than analog circuits; (3) with analog VLSI technology still very much in its infancy,digital circuits are more readily amenable to VLSI implementation than analog circuits.By means of VLSI technology, the modem’s size, power consumption, and manufacturingcost are considerably reduced. Miniaturization also enables the integration of modem functionsonto a personal computer’s motherboard, and the production of low-cost compact modem forlaptop applications.Aside from these attractions, this research project is motivated by the fact that, to the bestof the author’s knowledge, no such all-digital bit-by-bit semi-coherent MSK modems have everbeen developed, let alone implemented as a VLSI chip. Innovation is needed for the digitalimplementation of carrier and bit synchronization functions that are inherently more amenableto analog implementation. The digital architecture and techniques devised in this work can beapplied to the design and implementation of other continuous-phase frequency shift keyingsystems.1.3 ApplicationsThe modem chip may be used in MSK systems of different transmission requirements.Its baud rate and carrier frequencies are determined by the clock speed applied, which is allowedto be as fast as 50 MHz.As a specific application demonstrating the modem chip’s practicality, the chip is usedto facilitate high speed (19.2 kbps) data communications over intrabuilding powerlines. In theearly seventies, power utility companies began substantial use of powerlines for remotemonitoring and control functions [1, 2, 3]. Not long after, several powerline communication2products appeared in the market. These products employed a master/slave poffing scheme forconnection set-up, and the maximum data transfer rate they could support was typically at orbelow 2.4 kbps [4, 5, 6]. As interest in using powerlines for computer networking grew in theearly eighties, better powerline modems were developed [7, 8,9, 10]. In addition, communicationcharacteristics of powerlines were intensively studied. The possibility of applying channel codingtechniques to combat powerline noise was explored. Nectar Electronics International Ltd. [11],a UK firm, has already started marketing its own line of powerline modems and networkinterface software for the realization of powerline-based PC LANs. Recently, Onunga andDonaldson [12, 13] have successfully designed and implemented a powerline network interfacemodule that supports CSMA with priority acknowledgement. These research and developmentefforts are motivated by the following advantages of communication over intrabuildingpowerlines:1. Low cost: the use of powerlines obviates the need for specialized cabling and installationexpense;2. High convenience: powerlines have a reasonably universal building coverage and can easilybe accessed via standard wall-plugs.Powerline communication has the potential to provide a viable, cost-effective, and flexible meansof bringing networking power to the desktop workstations, and for other applications.1.4 ScopeThis dissertation presents the theory, design, implementation, and testing of the all-digitalbit-by-bit semi-coherent MSK modem chip. In Chapter 2, the theory of MSK signalling isreviewed. The two chapters that follow are concerned with the digital architecture of the chip:Chapter 3 focuses on the design and analysis of the modulator, demodulator, carrier detector, andbuilt-in self-test circuit, while Chapter 4 explains the novel digital techniques developed forreceiver synchronization. Chip design specifications are given in Chapter 5, which also includesa discussion of the design methodology. Chapter 6 examines the VLSI implementation of thedesign and describes the chip schematics given in the Appendix. In Chapter 7, the realization ofa compact almost-all-digital powerline modem using the MSK modem chip is presented, alongwith a brief review of the communication characteristics of intrabuilding powerlines. Chapter 83is dedicated to the testing and performance evaluation of the modem chip and powerline modemunit. Finally, in Chapter 9, a few conclusions are drawn, followed by discussions of designlimitations and possible improvements.42. THEORY OF MINIMUM SHW KEYINGWhen transmitting, a modem uses a data signal to “modulate” a sinusoidal carrier whosefrequency is within the passband of the channel. When receiving, a modem “demodulates”received carrier signals to recover the data. A variety of modulation schemes are available,differing in performance, bandwidth efficiency, power requirement, and ease of implementation.The well known ones include PSK, ASK, and FSK. The one chosen for implementation in thisthesis is MSK -- Minimum Shift Keying. MSK is often used as a quadrature modulation schemefor encoded symbol transmission, with demodulation based on a two-bit observation interval [14,pp. 286-298]. In the modem chip designed here, MSK is used as a binary modulation scheme forsingle bit transmission with a one-bit demodulation interval. In this chapter, the MSK modulationscheme is characterized, and the semi-coherent demodulation of MSK signals on a bit-by-bit basisis discussed with emphasis on theoretical performance in a zero-mean additive white Gaussiannoise (AWGN) environment.2.1 MSK ModulationDigital modulation is the process by which a transmitter transforms digital symbols intowaveforms that are compatible with the characteristics of the communication channel. In the caseof binary bandpass modulation, this corresponds to mapping each bit (0 or 1) of duration T intoa passband waveform s.(t) of equal duration:0 — s0(:), 0<.rT<2.1>1 —* s1(t), 0<tTUsually, sinusoidal waveforms are chosen, and they are referred to as “carriers” in the sense thatthey “carry” the digital information across the channel. A sinusoids(t) - Asin(2itft + e), 0<tT <22>is characterized by amplitude A, frequency f and phase angle 9. Modulation is achieved by5varying one or a combination of these parameters in accordance with the digital information. Forexample, in PSK, the data signal shifts the canier phase to either 0 or it. In ASK, it is the carrieramplitude that is altered between two values. FSK relies on the carrier frequency to convey data.Being a special case of FSK, MSK represents 0 and 1 with two orthogonal sinusoids. But,unlike conventional FSK, the frequency separation (f-f0) of these two sinusoids is only half thebit rate R (= lIT), which is the smallest tone spacing possible for orthogonality to prevail.Mathematically, MSK modulation can be described aso —* Asin(2iuf0t+ es), 0<tT1 —> Asin(2itft + 9), 0<tT<2.3>where €),, the phase angle of the MSK signal at the beginning of the bit interval, is chosenbetween 0 and it, whichever would maintain phase continuity at the bit boundary. Shown inFigure 2.1 is a digital data stream and its corresponding MSK waveform.A modulation scheme can also be represented geometrically by plotting the locations ofMSK WAVEFORMS(19.2 kbps, 105.6 kHz, 115.2 kHz)Figure 2.1: MSK waveforms (center frequency = 110.4 kHz, bit rate = 19.2 kbps).6sin2Uf1t____— —> sin2TIf0tS4 S2(fS3Figure 2.2: MSK signal constellation.its carrier waveforms on a signal space. The signal constellation of MSK is constituted of fourpoints on a two-dimensional signal space (Figure 2.2). Signals I’ s2, s3, and s4 together form abiorthogonal signal set, with the minimum distance between them being d = (2E)os, E denotingthe energy of individual signals. In each bit interval, only one of the two pairs of orthogonalsignals, (s1, 2) or (s3, s4), is chosen for use. The choice is governed by the condition of phasecontinuity and depends on the history of the data sequence.Another important characteristic of a modulation format is its output power spectraldensity function. It represents the distribution of average signal power in the frequency domain,and therefore defines the spectral occupancy and bandwidth of the signalling waveform. One ofthe goals in communication system design is to minimize transmission bandwidth. MSK is abandwidth efficient modulation scheme. Its power spectral density function G(/) readsG(J)—![( cos2it (f-f)/R )2 ÷ cos2it (f÷f)/R )2] <2.4>2-[4(f-.f)/R]2 1 -[4(f÷f)/R]27Figure 2.3: MSK power spectrum (center frequency = 110.4 kHz, bit rate = 19.2 kbps).where f = (f0+J)/2 is the centre carrier frequency. The envelope of G(f) falls off as f , asopposed to the slowerf2roll-off rate characteristic of such schemes as PSK and FSK [14]. Asa consequence, the side lobes in the MSK power spectrum are greatly suppressed (Figure 2.3).In fact, 99 % of the signal power in MSK is contained in a bandwidth of only about 1.2R [141.Besides bandwidth efficiency, MSK has other advantages:1. MSK waveforms exhibit phase continuity, thus minimizing any inter-symbol interferencecaused by amplifier non-linearity.2. MSK signals have a constant envelope, thus avoiding amplitude-limiting distortion thatcould be introduced by power amplifier at the transmitter.2.2 MSK DemodulationDemodulation is the process by which a receiver retrieves digital information from themodulated carrier. In binary signalling, a receiver has to decide whether it is a 0 or 1 that iscarried in each bit interval. In reality, a signal traversing the communication channel is subjectedMSK POWER SPECTRUM(bit rate 19.2 kHz)I—N(‘3E0zFrequency - kHz8to noise interference. When it reaches the receiver, the signal may be so corrupted that itmisleads the receiver to a wrong bit decision. Minimization of bit error probability is onecriterion of optimality in receiver design. Presented below is an overview of various methods ofMSK detection and a description of the suboptimal (in AWGN sense) demodulation techniquethat is implemented on the MSK modem chip.2.2.1 Methods of MSK DetectionMSK is a very special digital modulation scheme because it can be viewed either as aform of offset quadrature phase shift keying (OQPSK) with sinusoidal symbol weighting, or asa special case of continuous-phase frequency shift keying (CPFSK) [15].In the first view, MSK is considered as being composed of two orthogonal data channels:in-phase (I) and quadrature-phase (Q). Optimal demodulation can be performed with a fullycoherent I-Q receiver using a two-bit observation interval. Alternatively, differentially coherentdetection may be used, but this yields suboptimal performance [15].In the second view, MSK is treated as CPFSK with a modulation index of 0.5, and itsdetection may be either noncoherent or coherent [16]. Noncoherent detection is suboptimal,usually achieved by processing the signal over one or more bit intervals with limiter-discriminators. Optimal demodulation requires coherent detection over a two-bit observationinterval. Such a receiver has a rather complex structure [17].In the design of the MSK modem chip, the CPFSK view of MSK is adopted. Forsimplicity and other reasons to be explained shortly, the modem uses a semi-coherentdemodulation scheme based on a one-bit observation interval. This scheme is suboptimal, but hasthe advantages of ease of implementation and compatibility with conventional FSK. Also, exactanalysis of its performance in AWGN is possible.2.2.2 Semi-Coherent Demodulation of MSKMSK and conventional FSK are both a form of orthogonal CPFSK. In each bit interval,either one of the two orthogonal waveforms in <2.3> is transmitted. For conventional FSK, theinitial phase angle,€), is fixed at 0 for every bit interval. For MSK, Og may be either 0 or it,whichever is needed to maintain phase continuity at the bit boundary. To coherently receive MSK9signals using a one-bit observation interval, exact knowledge of €) is required. Under thiscondition, the coherent MSK demodulator chooses between two orthogonal signals in each bitinterval, and therefore has the same BER performance as the coherent FSK demodulator [18, pp.406-407]. (Note that in noncoherent detection, € is treated as a random variable uniformlydistributed between 0 and 2ic.)However, in practice, bit-by-bit coherent MSK demodulation is not realizable becauseexact knowledge of €) is not available at the receiver. It is true that €) might be estimated, butdoing so would require information from previous bit intervals and would have a non-zeroprobability of error.As a result of this difficulty, bit-by-bit demodulation of MSK can at best be realized semi-coherently. This is the approach used by the modem chip to receive MSK signals. Such ademodulator has the same structure as a coherent FSK detector, consisting of a pair of correlatorsand a decision device (Figure 2.4). Due to the lack of knowledge in €, there is 1800 phaseuncertainty in the two locally recovered carrier references. So, in each bit interval, thesSt)Figure 2.4: Bit-by-bit semi-coherent reception of MSK.10demodulator has to choose among four biorthogonal signals (Figure 2.5). Bit decision is basedon magnitude, not algebraic, comparison according to the following rule:1>1c 1c0 <2.5>0where c0 is the output of the space frequency correlator, and c1 is the output of the markfrequency correlator.The theoretical BER performance of this semi-coherent detector in AWGN with one-sidedpower spectral density N, eMSK’ is related to that of coherent FSK, eSK’ as follows [19, p. 244]:P —2P (1—P <2.6>e,MSK e,FSK’ e,FSK’sin2itfita—>sln2itf0tSPACEFigure 2.5: Decision regions for semi-coherent MSK.MARK1115<2.7>Under perfect receiver synchronization, cSK is given by [20, P. 252]1 IE‘eFSK - _erfc44jIn Figure 2.6, the BER curve of semi-coherent MSK is plotted together with those ofcoherent PSK [20] and coherent FSK for comparison. With semi-coherent MSK, bandwidthefficiency is attained at a slight expense of bit error performance. Note also that in the limit oflarge signal to noise ratio, eMSK is twice as much as eSK•In reality, because of hardware limitation and noise influence, perfect carrier and bitPERFORMANCE OF PSK, FSK, & MSK(AWGN channel; perfect synchronization)ci)cci1__________1 EQ 1.-1EO____1 E-02 -1E-Ozi--\.jPsKt1E-OS +__-IE-06 .1E-07-10 -5 0 5 10Enemy to Noise Ratio (E/N) - dBFigure 2.6: Theoretical BER performance of coherent PSK, coherent FSK, and semi-coherentMSK in AWGN.12synchronization is not available at the receiver. Under this circumstance, relation <2.6> still holdsbut eSK is no longer given by <2.7>. First, in the case of imperfect carrier phase recovery, eSKbecomes [21, pp. 302-336]‘3e.FSK = erfc,4J.cos213<2.8>where ft denotes the phase difference between local carriers and received carriers.Next, when bit synchronization is imperfect, the recovered bit clock is offset from theactual bit clock by t (>0) units of time. As a result, the period of integration extends not from0 to T but rather from t to T+t, thus overlapping two consecutive bits. Half of the times whenthe two overlapped bits have the same polarity, this error leads to no consequence. Half of thetimes when the two overlapped bits have opposite polarity, this error increases the probabilityof false detection. It can be shown that, for t/T << R, eSK becomes1 1 E 1 E .t2I i 2 <2.9>P_[_erfc I — + _erfc I _(1—_____)]22 2W 2 2N 3Twhere .t = 2it(t-f0).Finally, if both carrier phase error and bit timing error are present at the receiver, as isnormally the case, eFSK should be corrected to readeSK ![!erfc cos2 + cos2 (1-___)] <2.10>Performance degradation due to imprecise synchronization is illustrated by the set of BERcurves in Figure 2.7. Curve B belongs to a semi-coherent MSK receiver with 10% (= 36°) carrierphase error; curve C to one with 10% bit timing error; and curve D toone with both 10% carrierphase error and 10% bit timing error. As expected, these curves all lie above, and thus indicatea higher bit error probability than, curve A which represents the performance of a semi-coherent13Figure 2.7: Effect of imperfect synchronization on the BER performance of semi-coherent MSKin AWGN.MSK receiver under perfect synchronization condition. The effect of bit timing error is much lesssubstantial than that of carrier phase error.2.3 Analog Vs DigitalThe formula cited in this chapter are based on continuous-time analysis under theassumption that the demodulation process has an analog implementation. However, thedemodulator on the MSK modem chip is digitally implemented, and is therefore a sampled-datasystem. Its operation should be analyzed in discrete-time taking into account of sampling andquantization effects. Such an analysis is presented in the next chapter, and the result indicatesthat, not surprisingly, in terms of theoretical BER performance in AWGN, the digital system isinferior to the analog system.PERFORMANCE OF MSK IN AWGN CHANNEL(imperfect synchronization)it11111Enety to Noise Ratio (E/N) - dB143. A DIGITAL ARCHITECTURE FOR MSK SIGNALLINGInside the MSK modem chip are four main functional modules: modulator, demodulator,carrier detector, and built-in-self-test controller (Figure 3.1). In this chapter, the operationprinciples and design considerations of these digitally implemented modules are explained, andtheir performance is analyzed.3.1 Modulation StructuresMSK modulation can be realized with analog components in two ways. One is simply byusing the data to vary the output frequency of a voltage controlled oscillator (VCO) [22, pp. 189-1911 (Figure 3.2). The other is slightly more complicated: the MSK signal is obtained bysumming the output of two multipliers modulating the in-phase and quadrature-phase componentsof the centre carrier with baseband data [23] (Figure 3.3).Figure 3.1: Functional block diagram of the MSK modem chip.15d(kT) s(t)E”igure 3.2: An analog frequency shift keying modulator.There are also a few possible ways to implement MSK modulation in the digital domain.One, referred to as table look-up technique [24, pp. 37-43], is illustrated in Figure 3.4. Multi-bitdigital representation of each carrier sinusoid is pre-stored in a ROM. During each bit interval,the digital sequence corresponding to the data symbol for that interval is “looked up” from thememory and fed into a D/A converter which reconstructs the analog carrier wave. Alternatively,one may synthesize the signalling waveforms with a Johnson counter and a resistor network [25,J-1JTITIrLnJutrLfLnjkT*Tdata MSK signalFigure 3.3: An analog I-Q type MSK modulator.16Figure 3.4: Table look-up sinewave generator.Figure 3.5: A Johnson counter based sinewave synthesizer.m # of samples per canier waveformn —#of bits per sample______________LPF > s1(t)v- r->dcccr’__c LC)CK_____QOQ1234567>DL 0117p. 448]. Figure 3.5 shows an example of this which outputs an 8-level approximation to a sinewave. This approach alleviates the use of ROM and D/A convertor, but requires highly accurateresistors and is not easily amenable to VLSI implementation.3.1.1 An All-Digital MSK ModulatorIn the MSK modem chip, a different technique is used to achieve MSK modulation.Analogous to the VCO method, it makes use of a so-called numerically controlled oscillator(NCO)-- basically an adjustable divide-by-N circuit (Figure 3.6). The NCO outputs a squarewave, the frequency of which is varied betweenf0andJ according to the digital data. In addition,an external low-pass filter is needed to “smooth out” the output waveshape. The merits of thisapproach include simplicity and robustness: the NCO can easily be implemented with a binarycounter and random logic; unlike the table-look-up method, no on-chip memory nor external D/Aconverter is required.IN LELELFigure 3.6: A numerically controlled oscillator (NCO).183.1.2 Performance AnalysisModulators axe evaluated in terms of output phase stability. In the NCO-based digitalMSK modulator described above, phase stability is determined by the accuracy of the systemclock and the ratios of carrier frequencies (f0, f) to system clock frequency j. Suppose that thesystem clock has absolute jitter 6f. And let R0 bef0/J, and R1 bef/f. Then, depending on the databit, the modulator output frequency would be either f0 ± R06L or f, ± R16f. Assumingequiprobable 0’s and l’s and random Gaussian error statistics, the average output frequencyjis given byf___+_____<3.1>2 — 2The error term in the above expression corresponds to the absolute output jitter 6f0, and thepercentage output jitterfjf0 isf01, /R + R 3J <3.2>6f. R0+R1 f3.2 Demodulation StructuresThe digital demodulator in the MSK modem chip is designed to perform semi-coherentdemodulation of MSK signals over a one-bit observation interval. As shown in Figure 3.7, it isstructured as a correlation-receiver. First, the MSK signal received from the powerline isseparately multiplied by two locally generated carrier references, and the products are integratedover one bit interval. Subsequently the outputs are compared in the decision device to determinethe digital data. Also present in the demodulator are two carrier synchronizers which track thetwo orthogonal carriers, and a bit synchronizer which recovers the bit clock. Owing to the digitaloperation of this demodulator, it is necessary to digitize the received MSK signal before feedingit into the modem chip. This digitization can be achieved with either a hardlimiter or a multi-bitA/D converter.193.2.1 Digital CorrelationAn analog representation of a correlator is shown in Figure 3.8. The correlator consistsof a multiplier and a time-domain integrator. Mathematically, the correlator computes thefollowing integral:- frSwhere r(r) is the received signal, and s(t) is the local carrier reference. This integral measures thesimilarity between the two signals over bit interval T.Discretizing equation <3.3> givesc — r()s(.!i) <3.4>d T Tr (t) d(k)Figure 3.7: Architecture of the semi-coherent MSK demodulator.20with m denoting the number of equally-spaced samples taken over T. This equation suggests thata digital correlator can in general be implemented with two ADCs, a multi-bit multiplier, and amulti-bit adder, as shown in Figure 3.9. Simplification occurs when both r(n) and s(n) are 1-bitdigitized (i.e. square wave). In this special case, the correlation function can be interpreted asfollows [26]:A-D A—D 2A-m m-2DC —___________—___________—______________—______________• >b A÷D m m mr(t) c(t)s(t)Figure 3.8: An analog integrate-and-dump correlator.r(n)s(n)c(n)Figure 3.9: A multi-bit digital correlator.where A and D are, respectively, the number of agreements and disagreements in the polarities21r(n) > \ç_%\ BINARYH / :>c(k)s(n) COUNTERFigure 3.10: A one-bit digital correlator.of the two signals over T. This function Cb can easily be computed, to within a constant ofproportionality, by using a “binary correlator” like the one shown in Figure 3.10. The XOR gatecompares the polarity of the inputs while the counter tallies the number of agreements anddisagreements. This kind of implementation which considers only signal polarities is referred toas “binary partial decision” [27]. It readily lends itself to VLSI implementation.For FSK demodulation, two binary correlators, one for each carrier frequency, and adecision device are needed, as shown in Figure 3.11. The decision device identifies datum in eachbit interval according to the following rule: -1> <3.6>1<00where c0 and c1 are the output of the space and mark frequency correlators, respectively.The semi-coherent MSK demodulator on the modem chip is structurally identical to thecoherent FSK demodulator just described, except that a different decision rule is used, which now22reads1>1c 1c00sin)>)son) )d(k)Figure 3.11: A binary partial detector for coherent FSK or semi-coherent MSK.<3.7>Bit decision is based on the absolute magnitude of the two correlation outputs, and can easily beimplemented with combinational logic.3.2.2 Performance AnalysisThe BER performance of the binary quantized coherent FSK and semi-coherent MSKreceivers in AWGN under conditions of perfect synchronization and imperfect synchronizationis derived below.23Perfect SynchronizationFigure 3.12: Subbit error caused by channel noise.To begin, without loss of generality, assume that a space bit is transmitted to the binary-quantized coherent FSK demodulator via an ideal channel. During this bit interval, the spacefrequency correlator will observe m polarity agreements and 0 polarity disagreements, i.e. A0 =m and D0 = 0, m being the total number of samples or “subbits” over T. Owing to orthogonalityof the two carriers, the mark frequency correlator will observe m12 agreements and m12disagreements in the same bit interval, i.e A1 = (m/2) and D1 = (m/2). Therefore, in the absenceof channel interference, c0 = 1 and c1 = 0, and by <3.6> this will lead to a correct bit decision,as expected.Now, let the channel be noisy so that subbit error probability is non-zero (Figure 3.12).Occurrence of a subbit error may reduce A0 by 1 making c0 smaller, but can either increase ordecrease D1 by 1, depending on the position of the inflicted subbit sample. If the subbit errordoes increase D1 by 1 making c1 more positive, this is said to be an “offending” subbit error.Otherwise, it is an “innocent” subbit error because it does not reduce the “distance” between C0and c1. Owing to orthogonality of the two signals, the maximum number of offending subbiterrors is m/2, and so is the maximum number of innocent subbit errors. If in one bit interval thereare e, offending subbit errors and eg innocent subbit errors, theniiNOISERECEIVEINPUTDGZEDINPt.rr,,1/subbit error24A0— meg—eb <3.8>— eg + eb <3.9>c0 — - 2e8- 2eb) <3.10>andA —!i÷e -e <3.11>2b gD —!i-e +e <3.12>1 2 b g=>—!e,, — eg) <3.13>Substituting <3.10> and <3.13> into decision rule <3.6> shows that the following condition hasto be satisfied in order to correctly receive the datum:e<m <3.14>bIn other words, regardless of the number of innocent subbit errors, a bit decision will be wrongif the number of offending subbit errors in one bit interval exceeds m/4. So the bit errorprobability of the FSK demodulator, eSK’ is equal to the probability of having more than m/4offending subbit errors in one bit interval. That is, assuming m to be divisible by 4,25m1 m meSK [E 2 e(1e)] + [![2] ET(1e)T] <3.15>where e, the subbit error probability, is dependent upon channel noise statistics and signalamplitude. Under Nyquist sampling condition in AWGN with one-sided power spectral densityN, C is given by [28]1 E <3.16>e — _erfc—2 JnWwhere E denotes the bit energy.The demodulation mechanism of the semi-coherent MSK demodulator is identical to thatof the coherent FSK demodulator except that a different decision rule is applied. In this case, tocorrectly receive, for example, a 0, it is necessary that:1c0 > IcI 1A0—D > 1A—D <3.17>Depending on the signs of c0 and c1, this condition can be rewritten in four different ways:Case 1: (A0-D) > (A1—D)= eb < .. <3.18>Case 2: (A0-D) > (L)1-A) eg < . <3.19>Case 3: (D0-A) > (A1-D)= eg> .. <3.20>26m <3.21>Case 4: (D0-A) > (D-A1) —4Thus the probability of correctness of the MSK binary demodulator, cMSK’ is given by1 m <Jfl)‘c,MSK — P(case 1, e,<_) + P(case 2, e8<3.22>m m+ P(case , e8>_.) + P(case 4, e>_)This leads to‘c,MSK — P(e,<., eb>e8, eb<_._) + P(e1<f!., ebce8,e8<)<3.23>+ P(e eb>e8,e8>!.) + P(e>.i, eb<e8, eb>_4_)t2Simplifying,m m‘c)ifSK - P(eb<., e8<_4.) + P(eb>!!, e >!i) <3.24>84But due to orthogonality,>m >m <3.25>P(eb —) — P(e —)<4 8<4From <3.24>,‘c,MSK — (1— “eSK)2 + “eSK) <3.26>And therefore, the probability of error, eMSK’ is‘e,&fSK — 21e,FSK(1 1°e,PSK) <3.27>27which, not surprisingly, is identical to the BER expression cited in Section 3.3.2 for thecontinuous-time MSK demodulator. Again, in the limit of small E, eNSK is twice as much asFigure 3.13: BER performance of the binary partial demodulators for coherent PSK, coherentFSK, and semi-coherent MSK.Plotted in Figure 3.13 are the theoretical BER curves of the coherent PSK [27], coherentFSK, and semi-coherent MSK binary partial decision demodulators in AWGN under perfectcarrier and bit synchronization condition. As expected, coherent PSK is superior to coherent FSK,which, in turn, is ever so slightly better than semi-coherent MSK. Additionally, in terms ofenergy to noise ratio (E/N), the discrete MSK demodulator is about 2 dB less efficient than itsanalog counterpart (dotted curve). Understandably, the degradation is caused by digitalquantization and time-sampling effects.Imperfect Carrier SynchronizationConsider the reception of a space bit by the discrete FSK demodulator with imprecise‘eFSKPERFORMANCE OF DISCRETE MODULATIONS(AWGN channe’; perfect synchronization)ci)(‘5LUEnergy to Noise Ratio (EJN) - cIB28Figure 3.14: Theoretical BER performance of the semi-coherent MSK binary demodulator underdifferent conditions in AWGN.carrier synchronization. Even in the absence of channel noise, the space frequency correlator willdetect poiarity disagreement in some subbits. These “systematic” subbit errors are attributed tothe fact that the local carrier is offset from the received carrier. The number of disagreement isequal to 2nc, n being the number of subbits by which the local carrier is offset, and c the averagenumber of carrier cycles in T. Under this circumstance, an incorrect bit decision would bereached as long as the number of noise-induced (random) subbit errors exceeds— 2nc) <3.28>22So the probability of error expression eSK becomesBER PERFORMANCE OF MSK(Binary Partial Detector in AWGN)-DD20I—2wEnergy to Noise Ratio (E/N) - ciB29m m2cf \ T —flC m‘e.FSK2ncc(1—E)2[ 2.1—0 J J m_+J+1T <3.29>m.flC m j mj+ ! 2 eT(1_c)]2m j— -nc+ —4 2The probability of error of the discrete MSK demodulator, eMSK’ in the presence ofcarrier synchronization error can be obtained simply by substituting <3.29> into <3.26>. CurveC in Figure 3.14 corresponds to the AWGN performance of the discrete MSK demodulator thatsuffers from a carrier phase error of 10%.Imperfect Bit SynchronizationIMPERFECTBIT-CLOCKSYSTEMATiC SUB8IT ERRSFigure 3.15: Detection degradation effect of imperfect bit synchronization.30Assume that due to imperfect bit synchronization, the bit clock regenerated in thedemodulator is offset by ‘v (>0) units from the actual bit interval T. As a consequence, insteadof extending over one single bit, the period of integration of the correlators would overlap fromone bit to the next. This would lead to performance degradation when the two overlapped bitintervals cany opposite data, because, as illustrated in Figure 3.15, some subbit agreements wouldbe replaced with disagreements and vice versa.For discrete FSK demodulation, the number of subbit errors caused by bit timing offsetequals to the number of polarity mismatch between the two carriers in [0, t]. With this numberdenoted by g, the maximum number of noise-induced subbit errors that the demodulator canwithstand is reduced to!(.- g) <3.30>22Thus eFSK is now given by averaging <3.15> and the following:mg m gI I ei(1_)_i[ Dj—O J) mg÷j1 1<3.31>mg1 mg÷j mj+ -- (1-e) 72 mg÷j422The BER performance of the semi-coherent MSK binary partial decision demodulator cansimply be obtained by substituting <3.31> into <3.26>. Curve B in Figure 5.14 represents theresult for a bit timing error of 10%. Performance is much less sensitive to bit timing error thanit is to carrier phase error.313.3 Carrier DetectionThe carrier detector on the modem chip determines if MSK carrier waves are present inany received input signal. This function is needed to prevent the modem from transmitting whilethe channel is being utilized by another user in a multiple-access system. Otherwise, transmissioncoffisions would occur, reducing overall channel utilization.One method of carrier detection is by monitoring the average power at the receive input.When a signal is present, the power detected is usually considerably higher than backgroundnoise alone can yield. This kind of “power metering”, though, is liable to out-of-bandinterference. Besides, it can only be rendered with analog components, and is therefore notsuitable for implementation in the modem chip.Another method of carrier detection, that provides better frequency resolution, relies onthe operation of the carrier synchronizer loop [29, pp. 200-210]. When a carrier is being received,the loop would be in lock; otherwise it would become out-of-lock. So by monitoring the loop’slock condition, one can determine whether a carrier is present. But this method is not applicablehere because the special digital carrier synchronizers used do not lend itself to reliable lockdetection. As well, the detection delay associated with lock detection might be unacceptably longbecause of its direct relation to the lock acquisition time of the synchronizers.In the MSK modem chip, carrier presence is determined by counting the number ofpositive zero crossings at the receive input in intervals of duration T. In the absence of a carrier,the number of positively-going zero-crossings within an interval should ideally be zero; in thepresence of a carrier, this number should be at least f0T. But because of channel noiseimpairment (e.g. burst errors), the actual count would be below or above these levels. So somethreshold value between 0 andf0T is used to decide between carrier absence and presence. If thecount is less than the threshold, carrier absence is assumed, and vice versa. Frequency resolutiondepends on the position of the threshold value. The closer tof0T,, the threshold is, the higher theresolution becomes. The choice of T is somewhat arbitrary, but it should be large enough so thata reasonable number of zero-crossings occur in its duration, and be small enough to keep thedetection delay acceptable. The detection delay, which affects channel utilization [12], is about1.5T.32Finally, there is one subtlety associated with this carrier detection method: detectionsensitivity is limited by the threshold or “dead zone” of the external ADC which digitizes thereceived signal. Any carrier signal with an amplitude below the threshold would be undetectedbecause of lack of zero-crossings at chip input. However, if the threshold is too low, channelnoise may be mistaken by the detector as carrier. Therefore, the threshold should be set at a valueslightly above average background noise level of the channel.3.4 Built-In-Self-TestThe built-in self-test (BIST) controller provides the MSK modem chip with the capabilityto functionally verify its modulation and demodulation circuitry. BIST [30, pp. 1-10] is a quickand convenient way of checking the integrity of critical paths in a VLSI device. BIST alsocontributes to overall chip testability, and can be used as a manufacturing test on the productionfloor. The BIST test is run in real-time at normal operating speed without the use of any externaltest equipment for pattern generation and comparison. At the end of the test, a pass/fail responseis issued.STFigure 3.16: Built-in self-test pattern generation.33Upon initiation.of BIST, the modem chip enters self-test mode. In this mode, the outputof the modulator is connected to the input of the demodulator, thus forming an internal loopback.Then a sequence of test data is used to exercise the modulator. The resulting bit stream outputfrom the demodulator is compared to the input stream. It is a binary output test. Should anymismatch occurs, an error signal will be flagged.Shown in Figure 3.16 is the block diagram of the BIST controller. The circuit isresponsible for the generation of test sequence and detection of compare errors. It makes use ofa linear shift feedback register (LSFR) to generate a pseudo-random binary test sequence. AnXOR gate compares the input sequence with the output response of the demodulator. Becauseof processing delay across the loopback path, it is necessary to delay the original sequence withflip-flops before it is actually compared to the demodulated data. Detection of any compare errorsduring the self-test would set a register to indicate test failure. A “timer” is used to providetiming control. It also ensures that the error detector is not activated until a sufficient number ofbits have been transmitted to allow the demodulator to acquire carrier and bit synchronization.If the error detector was enabled too soon, the test outcome would always be negative.344. ALL-DIGITAL RECEIVER SYNCHRONIZATIONIn this chapter, the architectures of the all-digital carrier and bit synchronizers newlydeveloped for MSK demodulation are presented and analyzed.4.1 Carrier Synchronization1N_______jdMde OUTFigure 4.1: Squaring-loop carrier synchronizer.>OUTHofr FUEj (SHIFTXFigure 4.2: Costa’s ioop carrier synchronizer.35Correlator-based demodulation techniques requires time-aligned replication of signalcarriers at the receiver. These replicates are directly extracted from received signals using carriersynchronizers. Carrier synchronizers track the carriers both in frequency and in phase. In the caseof semi-coherent MSK detection, two carrier synchronizers are used at the receiver, one torecover the space frequency and the other the mark frequency. Like PSK, MSK is a suppressedcarrier modulation scheme, meaning that its signal spectrum contains no discrete components atcarrier frequencies. While suppressed carrier modulation has the merit of power efficiency [31],it complicates the carrier recovery process at the receiver.4.1.1 Suppressed Carrier RecoveryIn the analog domain, there are two methods of suppressed carrier recovery: squaring loopand Costa’s loop [31]. A squaring loop (Figure 4.1) consists of a nonlinear element whichregenerates the discrete components at an harmonic of the carrier frequencies, and a phase-lockedloop (PLL) which isolates the harmonic. A Costa’s loop, on the other hand, does not use anynonlinear element. Instead it utilizes two PLLs, employing a common controllable oscillator andloop filter, to track the two quadrature components of the incoming signal (Figure 4.2). In theory,the Costa’s loop is equivalent to the squaring loop. Yet in general the former is more difficultto analyze and more complicated to implement than the latter [18, pp. 434-453].Thus, for simplicity and ease of implementation, the all-digital carrier synchronizers onthe MSK modem chip are designed on the basis of the squaring loop approach. But, unlike aconventional squaring loop, the design contains no nonlinear element. It simply consists of adigital phase-locked loop that is capable of recovering the carrier directly from MSK signals.4.1.2 Phase-Locked Loop BasicsTypically, a PLL is made up of three components: phase detector, loop filter, andcontrollable oscillator (Figure 4.3). Its operation is based on negative feedback: the phase detectorcompares the phase of the oscillator to that of the input; the resulting error signal is used to“steer11 the oscillator so that its output tracks the input in both frequency and phase. The loopfilter conditions the error signal and controls feedback dynamics. Incidentally, when the transferfunction of its loop filter has n poles, a PLL is said to be of (n+1)th order [32, pp. 8-24].36Analog phase-locked loops (APLLs) operate in continuous-time and are implementedusing analog devices [33, pp. 9-24]. Usually, the output of an APLL is sinusoidal, generated froma voltage controlled oscillator (VCO). Digital components are used in digital phase-locked loops(DPLLs) [34, pp. 69-115]. Most DPLLs employs a digital structure called numerically controlledoscillator (NCO) to generate a square wave output. DPLLs operate in discrete-time as a sampled-data system, with phase comparison and oscillator adjustments made periodically.The performance of an APLL or DPLL is characterized by its phase error, phase jitter,and acquisition time. Phase error corresponds to the steady state average phase differencebetween recovered signal and actual signal, and is a measure of loop accuracy. Phase jitter refersto the phase variance of loop output, and is a measure of stability. Loop acquisition time is thattime required for the loop to “search for” and “lock onto” the input signal that it tracks. Theconflicting goals in PLL design are the minimization of these three parameters.4.1.3 An All-Digital MSK Carrier SynchronizerThe two carrier synchronizers on the MSK modem chip are structurally identical. Eachis a first-order DPLL, one tuned tof0 and the otherJ. According to the classification suggestedby Lindsey and Chie [35], a ZC-DPLL performs phase detection by sampling at zero-crossingsof the local signal, while a LL-DPLL determines at each cycle whether the input leads or lagsINFigure 4.3: Structural representation of a phase-locked loop.OUT37the local signal. The MSK carrier synchronizer DPLL can be considered as a hybrid of thesebecause it uses a zero-crossing-based phase detection scheme while operating like a LL-DPLL.In addition, unlike other so-called N-th order DPLLs proposed for suppressed carrier recovery[36], this DPLL does not require any zonal filter and/or nonlinear device at the front end.The carrier synchronizer’s block diagram appears in Figure 4.4. The square wave outputfrom the NCO is at twice the carrier frequency to be tracked. Its zero-crossings are used by thephase detector to sample the modulated carrier. Twice every cycle, the phase detector determineswhether the NCO output is leading or lagging the actual carrier. These lead/lag decisions aresubsequently processed by the loop filter, which then instructs the NCO to either advance ordelay its output. Finally, the coherent local carrier is obtained by dividing down the NCO output.To enable the ioop to extract the suppressed carrier from the MSK signal without usingan external nonlinear element, a special zero-crossing-based phase detection algorithm isdeveloped. This algorithm works as follows: first, the modulated signal is sampled on the risingedge of the local carrier; then another sample is taken on the falling edge; if the two samplesr(n)Figure 4.4: Carrier synchronization on the MSK modem chip.s(n)38Figure 4.5: Phase detection for carrier recovery in the MSK modem.Figure 4.6: Phase detection errors due to reception of a non-tracking frequency component.have the same polarity, the local carrier is lagging; otherwise, it is leading. Validity of this “likelag, unlike lead” algorithm is demonstrated in Figure 4.5 considering all four possibilities.Still, some of the lead/lag decisions reached by the phase detector can be erroneous. Thereare two sources of errors. First, the input signal may be randomly corrupted by channel noise.Second and more important, the phase detector tracking one carrier frequency is subjected tointerference from the other carrier frequency also present in MSK signals. This problem isRECEIVEDCARRIERLAGGINGLOCALCARRIERwmLEADINGLOCALCARRIERPERFECTLOCALCARRI ER ZLrLJLLRECEIVEDCARRIERLAGGINGLOCALCARRI ER(2 x f___fi_____Hill [IJ_ElrhflrLJ1JJ1ifL\/ xJ XI \/LEAD/LAG DECISION EPIRORS39Tfo105.6kHz_____ _____ _____ _____HILHJ1JLPILHJ1J1JL[Uxx xxxX5.5115.21kHzIIIIIIIIIIII__±+——++——++—±+——++—--++—kHrLJlsLrw_fLn_rLrw_rL -l Li Li Li Li lxix lxxixFigure 4.7: Lead/lag errors over one bit interval.illustrated in Figure 4.6. Incidence of a second carrier frequency (in this casef0) makes the localcarrier signal appear to be leading at some instants despite that it is actually lagging behind thecarrier frequency it is supposed to track. Thus it is necessary to “suppress” the effect of thesemisleading lead/lag decisions on the loop. This suppression is the responsibility of the loop filter.The loop filter is a kind of sequential filter [37]. It counts the number of leads and lagsdetected over U samples. Majority voting is then applied to decide the actual lead/lag condition.For example, if there are more leads than lags, the local signal is decided to be leading. Thisapproach is equivalent to “time averaging” the phase detector output. It is feasible for tworeasons. First, as a result of channel noise randomness, signal statistics will tend to stand outfrom noise statistics. A time averaged decision has a higher SNR than individual decisions.Second, as shown in Figure 4.7, over a bit interval in which the offending frequency is received,the lead count and lag count are approximately equal; over a number of consecUtive bit intervals,these frequency-induced errors would also be overridden by signal statistics.Next, the loop filter adjusts the NCO according to the majority lead/lag decision over U40samples. The NCO generates the local carrier by dividing down a base clock. If the local carrieris leading, a base clock cycle will be added to delay the output; if the local signal is lagging, abase cycle will be deleted to advance the output.In addition, for more versatility and higher performance, two enhancements are made, oneto the phase detector, and the other to the loop filter:1. In an initial design, it was mandatory that the input signal be hardlimited to square wave.However, the input can now also be presented to the carrier synchronizer as a 4-bit digitizedsinusoid by using an external 4-bit ADC. A multi-bit input allows the phase detector to determinenot only the direction but also the magnitude of phase difference between the input signal andlocal signal. Availability of magnitude information helps improving the accuracy andeffectiveness of loop filtering process. As before, in each signal cycle, the input is sampled twice,the first on the rising edge and the second on the falling edge. But the phase decision is now a4-bit binary number in sign-magnitude representation. Its sign reflecting the lead/lag relation isdetermined from the polarities of the two samples using the “like lag, unlike lead” rule. ItsPD1PD1 <PD2 > a< bFigure 4.8: Improved detection of phase error.41magnitude is adopted from the first sample, which, as shown in Figure 4.8, is proportional to thephase difference.2. The loop filter provides negative feedback control of the NCO according to phase detectordecisions. Initially, each NCO adjustment was limited to one base clock cycle regardless of thephase error. However, the loop filter is modified to allow correction of the NCO output by either1 or 2 base clock cycles at a time according to the size of the lead/lag statistics. Specifically, thefollowing algorithm is used to determine the number of clock cycle that is to be added or deletedfrom the NCO output:fAVG <LOW => no correctionelse fLOW < AVG <HIGH => 1-step correctionelse if HIGH <AVG => 2-step correctionwhere AVG is the computed lead/lag average, LOW the lower threshold, and HIGH the upperthreshold. This algorithm has two benefits. First, the phase jitter of DPLL output is reduced asa result of the first condition, which states that no correction will be made unless the averageexceeds the lower threshold. Second, the lock acquisition time of the DPLL is improved byintroducing the third condition, which doubles the correction step if the average exceeds theupper threshold. The algorithm’s validity is independent of the digitization level of the phasedetector, although slightly better performance is expected with multi-bit sampling [35].Note that the carrier recovered by the synchronizer can either be in-phase or 1800 out-of-phase with the actual carrier. But this phase ambiguity problem has no avail here because onlythe magnitude of the correlator outputs matter in the MSK decision rule (see <3.7>).4.1.4 Performance AnalysisDPLL operation can be analyzed theoretically in three ways. The first is by studying thedynamics of loop feedback mechanism in discrete domain. It involves discrete modelling of loopcomponents, and deriving and solving difference equations [35]. This method is generallyapplicable to any kinds of DPLL. The second approach is to model loop operation as a discreteMarkov process with a finite number of states [38, 39]. This approach involves state specificationand calculation of state transition probabilities, and is mathematically complex if not intractable,and is therefore only applicable to simple DPLL systems. A third approach is to model the DPLL42as an APLL [40]. This “equivalent analog model” technique is acceptable if the DPLL step sizeis small as compared to the period of the synchronizing signal.As shown below, the steady state and transient performance of the MSK carriersynchronizer DPLL can readily be analyzed with Markovian technique. In the analysis, thereceived carrier is assumed to be square wave and be hardlimited prior to entering thesynchronizer.Steady State Behaviour. . .-1’ • • • .+ -L -L+1 .2 -1 +1 +2 +L-1 +L -LFigure 4.9: Error states of the all-digital MSK carrier synchronizer.x. x x x xuiJNLJR::::Figure 4.10: State transitions in the all-digital MSK carrier synchronizer.The MSK carrier synchronizer is modelled as a discrete Markov process, with its statescorresponding to the timing error of its output just before it is updated. As indicated in Figure4.9, the total number of possible states N is simply T/&, with & being the size of one correctionstep. But, owing to symmetry and that we are only interested in computing the absolute error,43the number of states can be halved, with each state corresponding to the absolute offset of theloop output. State transition occurs when the NCO of the loop is updated Shown in Figure 4.10is the resulting state transition diagram. It corresponds to a multi-step random walk model withreflective boundaries. The size of each hop is limited to 0, 1, and 2. Parameters u, v, w, x, andy denote the probabilities of state transition: u or v is the probability of decreasing or increasingthe offset by & x or y is the probability of decreasing or increasing it by 2öt and w is theprobability of null correction. They are functions of phase detection error probability (fi) and loopfilter parameters (LOW, HIGH, U). Mathematically, with U, the number of lead/lag samples,assumed to be even,-ww-1u— ID 1(1_13Y’ <4.1>£-.T-HIGH1).+RIGHv[‘U ‘e f3 i( 1—13 )Ui <4.2>i—..i-LOW+1U HIGH 1T 43x — ID I . 113(’—13)’i_oy — ID 1’I 13 (1-13f <44>i44.HIGH+1 c Jw-1-u-v--x-y <4.5>Quantity fi depends on the noise statistics of the phase detection process. As mentioned before,44there are two sources of detection errors: channel noise and frequency interference. The formeris extrinsic, and is assumed here to be AWGN with one-sided power spectral density N. Thelatter is intrinsic, and is caused by frequency shifts in MSK signalling. Without loss of generality,assume that the carrier synchronizer is designed to track the space frequencyf0. Then— P(error I f, received)P(f received) <4 6>+ P(error I f1 received)P(J received)For equiprobable transmission of 0’s and l’s, <4.6> becomes— ![P(error I f0 received) + P(error I f1 received)] <4.7>The first term is attributed to channel noise only; from <3.16>,1 I £ <4.8>P(error I f0 received) — _erfc,jwhere E = bit energy, and m = number of subbits per bit interval. The second term has toaccount for both channel noise and frequency shift effect:P(error I f received) ![l_!erfcJ __] + ![!erfc,.J __] =Therefore, according to <4.7>,1 I E <4.10>= _[1+erfc.—]Now, let Pk denote the probability of occurrence of state k, k ranging from 1 to L (= NJ2).Then, based on the state transition diagram, the following stochastic difference equation can be45written:subjected to reflective boundary conditions(1—w-u)p - (u+x)p2 + xp3(1—w)p2 — (v÷x)p1 + up3 + xp4(1—w)pLl—+ Vp2 ÷ (U+Y)PL(l—w—v)pL YP12 + (v+y)pLlIn addition, for normalization, it is required thatYDPk- 1(l—w)pk—yp2 + VPk1 + UPk÷1 + XPk÷2, 2<k<L—1 <4.11><4.12><4.13>Equations <4.11-13> can be solved simultaneously to determine the state probabilities Pk’S. Oncethe Pk’S are known, the steady state tracking error variance a2 of the carrier synchronizer can becalculated as follows:a2 — (k — 1)2 3t2 Pk <4.14>___U U Uw wFigure 4.11: Simplified error state transition diagram for the MSK carrier synchronizer.w w46Figure 4.12: Computed output phase variance of the carrier synchronizer.Unfortunately, in this case, analytic solution of equations <4.1 1-13> cannot be attained.An alternative is to solve them numerically using the Gauss-Seidel iteration method, as suggestedin [41]. This method is not pursued here, though; instead, it is more useful to obtain a closed-form approximation of the solution. In order to do so, the original Markov process is treated asif it contains only unit-step transitions of size &. This approximation is reasonable because, whilein tracking mode, as opposed to acquisition mode, there would be much more zero and one-steptransitions than two-step transitions; moreover, when L is large, distinguishability between one-step and two-step transitions actually diminishes. The result is a simplified state transitiondiagram (Figure 4.11), which is equivalent to that of a classical unit-step random walk problemwith reflective boundaries [42, Ch. 14]. Its difference equations are:(l—c)pk — bpkl + apk÷l, 14c’(L(1—c-a)p — ap2 <4.15>(l—c—b)pL — bpL_lCarrier Sync Error Variation(AWGN Environment)uJci,U)cci.rz0I.ci)1.cci043)C)ccicj243)0Eneiy to Noise Ratio (EJN) - dB47In this model, the probability of reducing the error by one step, a, is simply equal to u + x; theprobability of augmenting the error by one step, b, is equal to v + y; and the probability of nullcorrection, c, is the same as w defined above. Solution to equations <4.15> subjected tonormalization is well known [42, Ch. 14]:1-a_a, k — 1,...,L <4.16>laLwhere a = b/a. In turn, the state variance is given bya2 + 8t__[—L(L÷1)a’ +2(OL_(L+1)cL + a—a <4.17>4 1—a’ 1-a (1-a)2Plotted in Figure 4.12 is the steady error tracking error performance of the MSK carriersynchronizer loop based on the above approximation.Transient BehaviourThe mean acquisition time (TA) of the DPLL is defmed as the average time taken by theloop to reach the minimum possible phase error (i.e. state 1). Under the assumption of equallylikely probabilities of initial state, TA is given byTA — !ET(k) <4.18>where Ta(k) is time taken to acquire lock when the ioop is initially at state k.In the absence of noise, it is not hard to see thatTa(k) — (k—l)•U•T, 1kL <4.19>ThusT - L - UT <4.20>A 248However, in the presence of noise, Ta(k) is governed by the following difference equation:T(k) — UT + XT(k—2) + UTa(k 1) + VT(k+ 1) + YTa(2) 3kL—2 <4.21>bounded byT(1) — 0T(2) — UT + VTa(3) + YTa(4) <4.22>T(L— 1) — UT + XT(L—3) + UT(L—2) + (V+Y)T(L)T(L) — UT + XTa(L_2) + (U+Y)T(L— 1) ÷ UTa(L)Numerical solution of the above for the Ta(k)’S is possible [41]. In general, the smaller L is, thesmaller T4 becomes. Thus a design trade-off exists between the acquisition time and trackingaccuracy of the DPLL.General Signal CaseIn the analysis presented above, the incoming signal is assumed to be square wave. Whenthis is not the case (e.g. sinusoidal input), fi, and therefore the state probabilities, are no longerconstant, but vary with the error state of the system. The consequence is a considerable increasein computational complexity [38].Frequency Lock RangeAlso worth calculating is the frequency lock range f,. of the DPLL. It refers to themaximum possible frequency deviation, or “detuning,” of loop output in tracking mode. Thisparameter is critical in designing the MSK carrier synchronizer because the incoming signalcontains two carrier frequencies separated only by R/2. To prevent false locking, the frge of thecarrier synchronizer should be much less than R/2.For large L, Jge of the carrier synchronizer is given by49The receive bit clock is required at the correlation receiver to time the demodulated dataand, more importantly, to reset the correlators at the end of each bit interval. Usually, bit clockrecovery is from demodulated baseband waveform. In a correlator-based demodulator, one cangenerate the baseband waveform by low-pass filtering the output of the multiplier. When NRZdata encoding is used, the spectrum of the baseband waveform contains no discrete componentat bit clock frequency. In such case, bit synchronization is not unlike suppressed carrier recovery.One way of bit synchronization is to use the squaring loop mentioned in Section 4.1.1. But again,a nonlinear element, not amenable to digital implementation, is needed. An alternative is theearly-late gate technique (Figure 4.13). Here a PLL is used in which phase detection is achievedf 2( maximum number of phase hops per cyclerange total number of phase states per cycle- 2()f-21* UL’wheref is the DPLL’s free running frequency.4.2 Bit Synchronization<4.23>INOUTFigure 4.13: Early-late gate bit synchronizer.50BINARY DATA_.iL__JL____DEMODULATEDSUBBIT STREAMSwith JUffiEperfect‘\_fUifr itwith /id liii [[F[11iJLLLLLLI1ii1i1JIIimperfectJi’iTEiiiLLUJItFigure 4.14: Effect of carrier phase error on demodulated bit streams.with a pair of correlators. One correlator integrates the incoming data over an early portion ofthe local bit clock, and the other integrates over a late portion. The difference between these twotime-shifted correlations provides a measure of the offset of the local bit clock from the bittiming of incoming data. Detailed discussions of early/late gate synchronizers may be found in[18, pp. 453-4601.4.2.1 An All-Digital MSK Bit SynchronizerFor use in the semi-coherent MSK modem chip, an unconventional but innovative bitsynchronizer is designed. Conventional bit synchronizer structures are inappropriate because thebaseband waveform is unavailable from the MSK demodulator for bit timing extraction. Instead,bit clock timing information is “hidden” in two subbit streams, one from each of the two XORmultipliers. The state of each stream corresponds to the polarity agreement/disagreement betweenlocal and received carriers. Zero-crossings in these streams bear no relationship to data bittransition. To make matters worse, owing to imperfect carrier synchronization, the two streams51are contaminated with high frequency transitions. They appear to be “spiky”, spike widthproportional to the carrier phase error (Figure 4.14).Nonetheless, during each bit interval, a high density of polarity agreement ordisagreement can always be found in either one of the two streams. The end of a high densityregion on one stream and the subsequent beginning of a high density region on the other streammark a data transition. This suggests that one can search the bit boundary by monitoring theconcentration of polarity agreement and disagreement in the two streams. It is exactly this factthat the MSK bit synchronizer exploits to extract bit timing directly from the two spiky streams.The block diagram of the all-digital MSK bit synchronizer is shown in Figure 4.15. Likethe carrier synchronizer, the bit synchronizer is basically a lead-lag-based first-order DPLL. Thelocal bit clock which tracks receive bit timing is generated by a NCO that is periodically adjustedvia negative feedback from the phase detector and loop filter. The phase detector determineswhether the bit clock is leading or lagging with reference to the actual bit clock embedded in thetwo input subbit streams. How this is achieved is explained in the next section. After decidingPHASE DETECTORuPsrsusarrSTREAMSFigure 4.15: The all-digital bit synchronizer on the MSK modem chip.OUTPUTBTT. cIOCK52the majority of the lead/lag statistics over J samples, the loop filter instructs the NCO to adjustthe output bit clock. When the bit clock is detected to be leading, it is retarded by one base clockcycle, and when lagging, advanced by one base clock cycle.4.2.2 Decision-Aided Phase DetectionUnlike the phase detector used for carrier synchronization, this phase detector does notuse the zero-crossings of the local clock to sample the input. Instead, inspired by the early/lategate technique, the phase detector integrates the input with the local bit clock (BCKN), an earlyversion of it (BCKE), and a late version if it (BCKL). All three clocks are generated by theNCO, with the early and late clocks at equal distance apart from the nominal clock. Each clockis used to compute two integrals, one from each of the two subbit streams. So, a total of sixintegrals are obtained, each a measure of the density of polarity agreement or disagreement inone subbit stream over a bit interval. Next, the two integrals over BCKN are compared inmagnitude. Let the greater of the two be denoted by‘N Then I is compared to the other twointegrals computed from the same subbit stream as‘N over BCKE and BCKN, Let these lattertwo integrals be denoted by‘E and ‘L’ respectively. A lead/lag decision is reached using thefollowing “maximum seeking” rule:if/IFI </IN/ </IJ => leadingelse if /IFJ > “NI > /IJ => laggingelse => inconclusiveThis decision rule is founded on the basis that the more accurate the bit clock is, the greater thecorrelation integral becomes.From the hardware implementation point of view, the two integrators timed by BCKN isequivalent to the two integrators on the two correlators. Besides, the magnitude comparatorfollowing those two integrators performs the same function as the decision device of thedemodulator. Therefore, these four structures may be omitted from the phase detector.Interestingly, the phase detection process can be said to be “decision-directed” or “data-aided”.because bit decision is relied upon to determine which one of two triplets of integrals should beselected for comparison in each bit interval.534.2.3 Performance AnalysisLike the carrier synchronizing DPLL, the bit synchronizing DPLL can readily be analyzedby using Markov theory. Here the analysis is actually simpler because only one-step phaseadjustments are allowed in this loop.Steady State BehaviourThe DPLL is modelled as a discrete Markov chain, whose states are defined as theabsolute number of phase steps by which its output clock deviates from the receive bit clock. Thechain’s state transition behaviour corresponds to a unit-step random walk (Figure 4.11),characterized by <4.13, 4.15>. The solution to this problem is given by <4.16>.The associated transition probabilities, a, b, and c, are related to the algorithm of the loopfilter and the reliability of the phase detector. Letp denotes the probability of a correct lead/lagdecision, q the probability of a wrong lead/lag decision, and r the probability of a null decision.Furthermore, without loss of generality, assume that, out off lead/lag decisions collected by theloop filter for each phase update, u of them are correct, v of them are wrong, and w of them areinconclusive. Thena - prob>q) ] (J;x] p Xq yrlxy x+1 ) p X( 1 -p <4.24>c - prob-q) J] (J_x) Xq xrJx <4.25>andb — prob(p<q) — 1- a - c <4.26>• In turn, the phase detector output probabilities, p, q, and r, depend on channel noise statistics andon error characteristic of the decision-feedback lead/lag detecting algorithm. Normally, though,54as in the carrier synchronizing loop, the intrinsic factor far outweighs the extrinsic factor. So, forsimplicity, channel noise effect is neglected in the calculation of p, q, and r. Suppose that thephase detector samples the k bit interval in which a mark bit is transmitted, and that theprobabilities of 0 and 1 in neighbouring bit intervals are equal. Thenu — 0.25 [p(correct I 0 in (k_1)th & 0 in (k÷l)th interval) +p(correct I 1 in (k_l)th & 0 in (k÷l)tk interval) + <4.27>p(correct I 0 in (k_l)th & 1 in (k+l)tk interval) +p(correct I 1 in (kl)tk & 1 in (k+l)” interval)]Based on the “maximum seeking” algorithm specified previously, it can be shown that1 1 1 1 13p _[1 + — + — + —] — —4 2 2 6 24q![o÷o+!+!]-..±. <4.28>4 2 6 247r — 1-p- qTransient BehaviourIn the noiseless case, from <4.18>, the mean acquisition time of the bit synchronizingDPLL isTA— !ET(k) - (L 1)•J•T <4.29>In the noisy case, the following difference equations, which can be solved numerically,apply:55T(k) — if + PTa(11) + bTa(k+1) 1<k<LT(1) — 0 <4.30>Ta(L) — iT + PTa( 1) + qT(L)Frequency Lock RangeThe frequency range frge of the bit synchronizing loop is given byf (1)f <4.31>range JLwhereL is the NCO’s free running frequency. The “1,’ in the numerator is attributed to the factthat individual clock phase adjustment in the loop is limited to a single step.565. DESIGN METHODOLOGY AND CHIP SPECIFICATIONSWhile the previous chapters examines the theoretical aspects of the all-digital modemchip, this chapter is concerned with the engineering aspects. The design methodology, designphilosophy, and prototyping technique are discussed. Chip functions, pinouts, internal circuitparameters, modem capabilities and training requirements are specified.5.1 Design MethodologyFigure 5.1: Overall chip design and development methodology..57Shown in Figure 5.1 is a flowchart representing the methodology used in the design anddevelopment of the MSK modem chip. After design specifications are firmed up, the first taskis to design, synthesize, and draft the circuit schematics. Next, a prototype of the design is builtand tested to determine whether it meets the functional requirements and how well the circuitperforms. If the results are unsatisfactory, the original schematics are modified or, if necessary,re-designed. Then the prototype is changed accordingly for re-verification. This design-debug-modify cycle is repeated until a design that robustly meet all functional requirements is attained.The final design is then processed for VLSI implementation.5.2 Digital DesignIn developing the digital design of the MSK modem chip, a top-down approach [43, Ch.5] is employed, with emphasis on functionality, modularity, and hierarchy. This comprises severalsteps. First, the top-level architecture of the chip is drawn, in the form of a block diagramindicating the functional blocks and their interconnections. Top-level blocks are defined byfunction rather than form; some blocks can be simple while some can be very complicated. Eachtop-level block is dedicated to a special purpose, and has a well-defined set of I/Os. For example,there are six top-level blocks in the MSK modem chip. These include the modulator whichgenerates MSK waveforms; the demodulator which decodes MSK waveforms; the carrier detectorwhich probes the receive input for carrier presence; the BIST controller which administersloopback self-test; the timing generator which produces on-chip timing clocks and strobes; andthe chip controller which configures the chip.The next step in the design process is to determine the internal hierarchy of each block.In the case of a simple block, no further partitioning is necessary. But, in the case of a complexblock, subblock partitioning is usually needed. Besides, depending on the complexity of thesesubblocks, they themselves may be divided into smaller subblocks, called submacros. Forexample, the demodulator block of the MSK modem is such a block. It is made up of two carriersynchronizer subblocks and a bit timing recovery subblock. Within each one of these subblocksare a number of submacros.The final step is to create the circuit schematics of each individual blocks, subblocks, andsubmacros. This, known as “gate-level design,” involves the design and synthesis of58combinational and sequential logic circuits. Functions are transformed into structures out of logicgates and flip-flops.At the end of the digital design, a set of circuit schematics is produced, describing thehardware implementation of the design, including both block-level organization and gate-levelcircuitry.Also worth mentioning is the design philosophy adopted in the digital design of the MSKmodem chip. It is one that stresses synchronizability and simplicity. Synchronizability requiresthe digital circuit to operate synchronously [44, p. 77]. A synchronous design has all its edge-sensitive elements responding to the same clock edge, and contains no level-sensitive storageelements. A synchronous circuit is, in general, more reliable and testable than an asynchronousone. Simplicity prescribes that the digital circuit is designed to be as simple as possible. A simplecircuit tends to be more robust and easier to debug, contains less gates and thus occupies lesssilicon area.5.3 PrototypingThe purpose of prototyping is to verify the feasibility and performance of the proposedcircuit schematics. In particular, prototyping is necessary for the study, design, and developmentof the semi-coherent MSK demodulator. Included in the demodulator are two carriersynchronizers and a bit synchronizer, which, as explained in the previous chapter, are specialpurpose DPLLs. Because of signal feedback, the operation and performance of DPLLs aredifficult to predict, analyze, and even simulate. There is always the question of whether a loopwill ever acquire lock, and, if so, how long it will take. The phase detection methods employedin the synchronizers are new and thus unproven. It is uncertain whether they would work inpractice, especially when subjected to channel noise interference. The best and easiest way toseek answers to these questions and to validate the feasibility and performance of thesynchronizing circuits is via prototyping and testing in practical situation. One can experimentwith the prototype to study its operation and gain insights into its optimization.High speed CMOS LSI components [45] are used to prototype the modem chip design.These components are mounted on vector boards, and are interconnected using wire-wrap. Shownin Figure 5.2 is a photograph of the final version of the prototype modem. It is made up of five59Figure 5.2: MSK modem prototype.boards and one “backplane” board. Board 1 contains the modulation and timing circuits; board2 contains the BIST and control circuits; carrier synchronization is provided on board 3 and 4;board 5 performs bit timing recovery and data extraction. Board-to-board interconnections areprovided on the “backplane” board.5.4 Modem Chip Design SpecificationsIn this section, the functions and I/Os of the modem chip are listed, related designequations and internal circuit parameters are discussed, including a few comments on themodem’s training requirement and transmission capability.5.4.1 Functions And FeaturesThe primary functions of the MSK modem chip are:1. MSK modulation.2. Bit-by-bit semi-coherent demodulation of digitized MSK signals.603. Detection of MSK carrier.In addition, the following auxiliary features are provided:1. Received MSK signal can be input to the chip in either 1-bit or 4-bit digitized form.2. The chip can be programmed to establish an internal loopback, which is useful for out-of-service testing.3. The chip has built-in-self-test (BIST) capability.5.4.2 110 SpecificationsThe MSK modem chip has a total of 36 pins: 11 inputs, 15 outputs, 5 power pins, and5 ground pins. The voltage levels of the 1/0 pins are CMOS compatible. Listed below are thepin names, functions and usages:tch telK -LL__fTL_fTXDATktsu thmax mm unittch 27 25tel 27 25tsu 21th 1Figure 5.3: Transmit data transfer timing for 19.2 kbps transmission.61Pin #35: TXDI - transmit data input -- it is via this pin that NRZ data from the DTE is input intothe modem chip for transmission (Figure 5.3).Pin #34: TXCK - transmit clock output -- this pin outputs a 50/50 duty cycle clock to synchronizedata transfer from the DTE to the modem (Figure 5.3).Pin #10: 7XSO - transmit signal output -- this pins outputs the MSK modulated square-wavesignal.Pin #32: RXSI3 - receive signal input bit 3 -- this pin should be connected to either bit 3 (MSB)of the 4-bit ADC output or the output of the hardlimiter, whichever is used to digitize thereceived MSK signal.ich tclRXCK__ IRXDAT_________ ____________tpmax mm unfttch 27 25 118tcl 27 25 118tp 11 0 118Figure 5.4: Receive data transfer timing for 19.2 kbps transmission.Pin #31: RXSI2 - receive signal input bit 2 -- this pin should be connected to bit 2 of the 4-bitADC output, if present; otherwise, should be pulled up or down via a 10 k2 resistor.Pin #29: RXSIJ - receive signal input bit 1 -- this pin should be connected to bit 1 of the 4-bitADC output, if present; otherwise, should be pulled up or down via a 10 k2 resistor.Pin #28: RXSIO - receive signal input bit 0 -- this pin should be connected to bit 0 (LSB) of the624-bit ADC output, if present; otherwise, should be pulled up or down via a 10 k resistor.Pin #13: RXDO - receive data output -- this pin outputs NRZ encoded data extracted fromreceived MSK signal (Figure 5.4).Pin #14: RXCK - receive clock output -- this pin outputs a 50/50 duty cycle clock in synchronismwith the receive data (Figure 5.4).Pin #11: CD - carrier detect -- this is an active-high output indicating the presence of MSKcarrier waveform at the receiye input.Pin #16: MODEl - mode select bit 1 -- in conjunction with the MODEO pin, this pin is used toconfigure the modem chip. There are four modes of operation: 1. Normal - 1-bit receiveinput (MODE1=0, MODEO=0); 2. Normal - 4-bit receive input (MODEl =0, MODEO=1); 3.Loopback - (MODE1=1, MODEO=0); 4. Self-test (MODE1=1, MODEO=0).Pin #17: MODEO- mode select bit 0 -- see MODEl.Pin #20: RESET- chip reset -- holding this pin high for ten or more system clock cycles willsynchronously clear all on-chip flip-flops, counters, and registers.Pin #09: GOOD - self-test outcome-- at the end of an automatic self-test, this pin will eitherremain high to indicate a success, or go from high to low to indicate a failure.Pin #02: SYSCK - system clock input -- it is via this pin that the system clock ( 50 MHz) issupplied to the chip for internal timing and synchronization purposes.Pin #27: ADCCK - ADC clock output -- this pin outputs a clock at the system clock frequencyto trigger the external multi-bit ADC, if one is used to digitize the MSK signal received fromthe powerline.Pin #03: SIGO- space carrier demodulated stream -- multiplied product of the input MSK signaland the local space carrier reference; for test-probing purpose only.Pin #08: SIG1 - mark carrier demodulated stream -- multiplied product of the input MSK signaland the local mark carrier reference; for test-probing purpose only.Pin #05: UDO - “up/down” in space carrier recovery loop -- it indicates whether the space carrierloop is lagging or leading the receive input; for test-probing purpose only.Pin #06: UD1- “up/down” in mark carrier recovery loop -- it indicates whether the mark carrierloop is lagging or leading the receive input; for test-probing purpose only.6Pin #23: MAXM- early receive bit clock -- this is an early version of the locally generated bitclock used for bit syncbronization; for test-probing purpose only.Pin #21: MAXP- late receive bit clock -- this is an early version of the locally generated bitclock used for bit synchronization; for test-probing purpose only.Pin #26: ADD- “add” in bit clock recovery loop -- this is a signal in the bit clock recovery loop;when it is high, the bit clock is retarded by four system clock cycles; for test-probingpurpose only.Pin #24: DEL- “delete” in bit clock recovery loop -- this is a signal in the bit clock recoveryloop; when it is high, the bit clock is advanced by four system clock cycles; for test-probingpurpose only.Pin #01, 07, 15, 19, & 25: VDD - power -- these pins should be connected to +5 V supply.Pin #04, 12, 18, 22, & 30: GND - ground -- these pins should be connected to digital groundclose to the chip.5.4.3 System Clock RequirementAll on-chip clocks and strobes are derived from the system clock. The system clockfrequencyj is required to be a coimnon denominator of the frequencies of the internal clocks andstrobes. Among these, the two carrier synchronizing frequencies are closest to each other,oscillating at 2f0 and 2f, respectively. Therefore, as indicated in Figure 5.5, f, should be set atf - !(I-I) <5.1>S 22f0f1In terms of centre carrier frequency f and centre carrier frequency to bit rate ratio c,- (8a-i_)L <5.2>2aIn the MSK modem chip, cx is fixed at 5.75. Thus— 264(±)f <5.3>64Figure 5.5: Calculation of system clock frequency.Furthermore, it can be shown thatf-46f0 <5.4>andf-48f1f-264R<5.5><5.6>Using these equations, one can determine the required system clock frequency based on thetransmission specifications of the modem system.5.4.4 Internal CircuitryModulator: Modulation is implemented with a one-bit NCO (Section 3.1.1). Based on equations<5.4-5>, the NCO divides the system clock by 46 when the datum is 0, by 48 when the1/4f0 —1/4fruI1 system clock cycle65datum is 1.Demodulator: Demodulation is coherent over a one-bit observation interval, and the method ofbinary partial decision is used (Section 3.2.1). The number of subbits per bit interval (m)equals to R/J = 264.Carrier Synchronizer: It is a first-order DPLL of the lead/lag type (Section 4.1.3). Phase detectionis by sampling the input carrier at the zero-crossings of the local carrier. Loop filtering isrealized with majority logic. The number of lead/lag decisions per phase update (U) and thenumber of phase states (NSA) are 48 and 23, respectively.Bit Synchronizer: It is a two-input first-order lead-lag type of DPLL using an maximum seekingphase detection algorithm and a majority-vote loop filter (Section 4.2.1). The number oflead/lag decisions per phase update (J) and the number of phase state (N,,1,) are 12 and 66,respectively.Carrier Detector: Carrier presence is assumed if more than 8 positive-going zero-crossings occurat the input over 16 consecutive bit intervals (Section 3.3).BIST Controller: In each run, six frames of test data is transmitted. Each frame contains 127 bits,generated from a 7-bit LSFR. The first five frames enables receiver synchronization, whileerror monitoring occurs in the last frame.5.4.5 Training RequirementTo allow the receiving modem to acquire synchronization, a training sequence of alternating0’s and l’s should be appended to the beginning of the data sequence to be transmitted. Preamblelength L1, is determined by the sum of the average lock acquisition times of the on-chip carrierand bit synchronizers. Specifically, from <4.20> and <4.29>,LN,J2- 1 j ÷ N,12- 1 <5.7>2 a 2Numerically, it can be shown that L is required to be approximately 236 bits long.5.4.6 Modem Capability66The MSK modem chip is fabricated with 1.2 pm CMOS technology, which has a maximumspeed limit of about 50 MHz. So, according to equation <5.6>, the maximum centre carrierfrequency that the modem chip can support is 1.1 MHz, corresponding to a bit rate of 0.19 Mbps.676. VLSI IMPLEMENTATION OF THE MODEMIn this chapter, some issues of VLSI implementation are discussed, and the schematics ofthe MSK modem chip are described in details.6.1 VLSI MethodologyVLSI METHODOLOGYII______v_______physical layoutfabrication IiFigure 6.1: VLSI design methodology.VLSI implementation of the modem chip is based on standard-cell design methodology [46,pp. 12-16]. A standard cell is a pre-designed full-custom circuit performing a basic logic function.The standard cell library that is available at the University of British Columbia contains most ofthe basic logic gates and a variety of flip-flops. Higher level structures such as counters and68comparators are not available from the library, and have to be assembled from basic cells by thedesigners.Depicted in Figure 6.1 is the VLSI design process. It begins with the capturing of the designschematics using cells from the standard cell library. Next, the schematics are verified usingcomputer simulation. A bottom-up approach is used, low level blocks simulated first and top-level circuitry last. In a simulation, a circuit is stimulated with a functional test pattern, and itsresulting outputs are verified. Any circuit problems unveiled, such as fan-out and timingviolations, are debugged and corrected. Simulations are repeated until the circuit is error-free.After the design schematic is thoroughly verified, a layout is created, which is a sfficon-levelphysical representation of the schematics. The layout is produced by placing cells and routingsignals as specified in the schematics.Each of the above steps leading to fabrication is performed with CAD tools on a SUNworkstation. CADENCE EDGE [47] is used for schematic capture and layout, while the SILOSsimulator [48] is used for design verification. A clock speed of 50 MHz is assumed in thesimulations. The cell library is provided by Canadian Microelectronics Corporation (CMC), aVLSI facility in Kingston, Ontario [49]. Design files containing layout information are submittedvia electronic mail to CMC for fabrication.The MSK modem chip is fabricated with 1.2 .tm CMOS technology, which can support amaximum switching speed of approximately 50 MHz. CMOS has the advantages of high density,low power consumption [50, pp. 53-66]. The chip has a die size of 140 mu x 141) mu, and ispackaged in a 68-pin Pin Grid Array.6.2 VLSI Implementation IssuesIn the design and implementation of a digital VLSI system, there are several technical issuesworthy of special attention. These issues include: testability, clock distribution, and power/groundallocation. All are crucial to a successful VLSI design, and therefore must be addressed by thedesigners. How they are handled on the MSK modem chip is discussed below.6.2.1 TestabilityTestability refers to the ease of uncovering and identifying faults in the design. For reason69of economy, a VLSI device should be as testable as possible. This requirement is not easily metbecause one has no access to any of the internal nodes of the device. Only the I/O pins areavailable for testing purposes. Nonetheless, there are so-called “design for testability” techniquesthat can be applied to improve the testability of a design. Some of these techniques are used atvarious levels in the design of the modem chip.At the logic level, the design has a high degree of synchronizability. All IJOs and internalsignals can only change states at the edges of the system clock, thereby improving both thecontrollability and observability of the chip. Also, creation of test pattern for a synchronousdesign is more readily achieved than for an asynchronous design.At the block level, a built-in-self-test (BIST) technique [51, pp. 146-190] is used to achievetestability. Testing of the modulator and demodulator blocks is automated with dedicated on-chipcircuitry (BIST controller) which includes a test pattern generator and a signature analyzer. Runin real time, the test completes in a matter of seconds, and the result is indicated with a pass/failsignal. BIST helps to shorten diagnostic time and reduce testing costs. Also, the BIST test canbe incorporated as part of the manufacturing test for the identification of defective parts in thechip factory.At the chip-level, testability is improved by adding I/O pins to probe the internal nodes ofthe chip. Connected to the critical paths in the chip core, these pins allow the designers tomonitor the internal operation of the device. Observability is thereby improved; identification andlocation of circuit faults become easier. Of the eight I/O pins dedicated to internal probing onthe MSK modem chip, four access the two carrier synchronizers, and the other four access thebit synchronizer.For higher controllability, a RESET pin is provided. By asserting this pin high for a fewsystem clock cycles, one can synchronously clear all on-chip flip-flops, counters, and registers.This not only serves for system reset purpose but also is useful for test sequence initialization.Finally, the internal loop-back feature of the modem chip contributes to system-leveltestability. This feature permits an end-user to establish an internal loopback cascading themodulator and demodulator. With this connection in place, the DTE can send data to itself, thusenabling the end-user to perform two-way testing of communication protocols in the absence ofa channel and/or receiving node.706.2.2 Clock DistributionFigure 6.2: System clock distribution tree.In a synchronous system, the system clock has to be distributed to flip-flops and other edge-sensitive elements. On its way, the clock’s edges are delayed, and its rise and fall times slowed.Owing to variability in path length and path loading, the clocks arriving at different parts of thecircuit are, in varying degree, skewed relative to one other. Such skewing might lead to timingproblems that could be detrimental if left unattended, especially in systems where the clock widthis in the same order of magnitude as one gate-level delay. A large clock skew may alsoundermine synchronizability. Therefore, the on-chip clock distribution network must be carefullydesigned to minimize clock skew.The clock disthbution network in the modem chip delivers the system clock to all parts ofthe chip in an organized, balanced, and hierarchical fashion. As shown in Figure 6.2, it has aCLOCKSOURCETOPLEVELBLOCKLEVELMACROLEVELGATELEVEL71tree-like topology. In this clock tree, each branch corresponds to a distribution path. Inverters areused as “repeaters” in each branch to buffer and drive the clock signal. Basically, for delaybalancing purpose, each top-level block in the modem chip is fed by one branch. Then, withineach top-level block, the clock signal is split into several branches feeding the subblocks. Thesame is done in each subblock to send the clock to the submacros. Simulation results indicatethat the maximum clock skew in the modem chip is approximately 5 ns.6.2.3 Power/Ground AllocationPower is provided to the chip via power and ground pins. The required number ofpower/ground pins depends on the level of ground noise the circuit can withstand. If insufficientpower/ground pins are provided, the chip may malfunction from excessive ground noise. Theamount of ground noise generated is determined by a number of factors, including gate count,switching speed, output load capacitance, and current requirement of the output pads. Takingthese factors into consideration, it is possible to estimate the ground noise level. Then, based onthis estimate, one can determine the required number of power/ground pins. Alternatively, CMCrecommends that, as a rule of thumb, for 1.2 pm CMOS technology, one power/ground pair isneeded for every 3000 gates in the chip core [52].The MSK modem chip contains about 2200 gates, which suggests at least one power/groundpair. To allow for a large margin of error, five power/ground pins are actually used on themodem chip. These pins are distributed relatively evenly around chip periphery, with power andground pins alternating.6.3 Detailed Circuit DescriptionThe circuit schematics of the MSK modem chip (a total of 20 sheets) are contained in theAppendix. This section describes the schematics from top to bottom, relating functions tostructures.6.3.1 Top-levelAn overview of the I/Os, internal signal flow, and block-level organization of the MSKmodem chip is shown on the top-level schematic (sheet 1).72Placed on the border are thirty-six pads, each of which corresponds to one pin on the chip.There are four types of pads: input, output, power, and ground. Input or output pads, which areunidirectional, buffer and protect signals entering or leaving the core.Resided in the core are six interconnected functional blocks. A digital circuit in its own right,each block has a well defined set of 1/Os and performs a specific function in synchrony withother blocks.PadsThe MSK modem chip has a total of 36 pads: 11 inputs, 15 outputs, and 5 pairs ofpower/ground pads. A descriptive list of the pinouts is given in Section 4.2. Of the 261/0 pins,only 18 are for operational use; the rest are used as test points probing internal nodes forperformance monitoring and debugging purposes.CoreSignal processing activities of the modem chip take place in the MOD, DMDV, CDT, andTEST blocks, under control and support of the CNTL and TMG blocks.MOD generates the carrier wave and frequency modulates it with binary data from the host,while DMDV acts as a bit-by-bit semi-coherent MSK demodulator retrieving information fromsignals received from the channel. CDT monitors the receive input for presence of carrier signals.TEST specializes in built-in self-test of the modulator and demodulator. Timing clocks andstrobes required for proper coordination and synchronization of these four blocks are generatedby TMG. CNTL is responsible for setting up the internal configuration of the modem.Tabulated in Table 6.1 are the gate/transistor count figures of these six top-level blocks.6.3.2 Block LevelTable 6.1 contains an alphabetical listing of all the macro blocks used in this design. Amongthem are the six top-level functional blocks, made up of random logic, flip-flips, and other subblocks. The operation and digital circuitry in each of these top-level blocks are explained below.CNTL73Block Name DescriptionnMX2 n-bit 2 to 1 multiplexerADDn n-bit full adderCnBE n-bit synchronous counterCnBA n-bit asynchronous counterCDT carrier detectorCMPn n-bit comparatorCNTL configuration controllerCRLO carrier synchronizer- space frequencyCRL1 carrier synchronizer - mark frequencyDFFn n-bit D-flip-flopDIV12 divide-by-12 circuitD1V48 divide-by-48 circuitDMDV demodulatorDVCOO numerically controlled oscillator - spaceDVCO1 numerically controlled oscillator - markLPP majority loop filterMOD modulatorNCOV numerically controlled oscillator — bitNORM magnitude calculatorPHD carrier phase detectorPLLP 3-level loop filterSPDV bit clock phase detectorSTORE 8—bit resettable registerSTRV symbol timing recovery unitTEST self-testerTMG timing generatorTable 6.1: Macro blocks in the modem chip.MODE # MODEl MODEO Description LOOP QUAD TESTA 0 0 normal - binary 0 0 0B 0 1 normal - 4-bit 0 1 0C 1 0 loopback 1 0 0D 1 1 self—test 1 0Table 6.2: Mode select truth table.CNTL controls the modem configuration which depends on user selection of one of the fourmodes via the MODE 1 and MODEO pins. In both mode-A (MODE 1 = MODEO =low) and mode-B (MODEl = low, MODE = high), the modem is set for half-duplex data transmission andreception. The difference between these two modes lies in their digitization requirement of74receive signal. For mode-A, the receive signal needs only to be 2-level quantized (e.g. using ahardilimiter). For mode-B, it has to be 16-level digitized (e.g. using a 4-bit ADC) because, in thismode, carrier synchronization relies on a multi-bit sampling scheme. In mode-C (MODE 1 = high,MODEO = low), the output of the modulator is directly fed to the input of the demodulator; thisloopback connection facilitates off-line modem testing. Mode-D (MODE 1 = MODEO = 1) is usedfor built-in self-test: in this mode, loopback is established, and upon reset, the deviceautomatically conducts a test to check the integrity of the modulation/demodulation circuitry.Three active-high internal control signals from CNTL are used to configure the modemaccording to its mode of operation. These signals, called TEST, LOOP, and QUAD, are decodedfrom MODE 1 and MODEO. The decoding logic is shown on sheet 2, and the corresponding truthtable given in Table 6.2. TEST activates the TEST block and instructs the MOD block to accepttest data from the TEST block. LOOP establishes loopback. When QUAD is asserted, the twocarrier synchronizers within the DMDV block enter multi-bit mode of operation.TMGTMG, the “timing” block, supports, coordinates, and synchronizes the signal processingactions in other blocks. As shown in its block diagram in Figure 6.3, TMG generates severaltiming waveforms, their relationships illustrated in Figure 6.4. Both C44 and ADCCK arebuffered versions of the externally supplied system clock (SYSCK). C44 is used to clock thedemodulator, while ADCCK is sent off-chip to sample the receive signal. Other timingwaveforms are derived from a branched timing chain driven by SYSCK. First, a divide-by-2circuit is used to generate C22, that clocks the modulator. Then dividing C22 by 66 andsubsequently by 2 yields C19. Pulse BP is obtained by gating the output of the divide-by-66circuit with C19. Both C19 and BP are used for bit timing control in the modulator. Next,dividing C19 by 16 gives CCD, that defines the carrier detection interval. A divide-by-4 circuitis utilized to derive C9 from SYSCK. C9 provides the time base for symbol timing recovery.Shown on sheet 3 is the detailed schematic of TMG. It contains four frequency dividers, eachmade up of a counter or flip-flop and a few logic gates. Finally, TMG is also responsible forbuffering and disthbuting the chip-reset input, RESET.75ADCCKFigure 6.3: Block diagram of the timing generator.MODMOD, the “modulator” block, encodes binary information onto a square wave carrieraccording to the MSK modulation scheme, with phase continuity maintained at bit, boundaries.As shown on the schematic of MOD (sheet 4), the carrier is derived from C22 using a counter,decoder, and flip-flop. C22 clocks the counter. Its count is decoded to determine when to clearitself and to toggle the flip-flop. In this way, the flip-flop outputs a square wave, the frequencyof which depends on the decoding threshold. MSK modulation is accomplished by adjusting thethreshold according to the transmit binary data latched in. A space bit will set the threshold at11; a mark bit will change the threshold to 10. Synchronization between the modulator andincoming bit stream is maintained by periodically resetting the counter with BP. This mechanismhelps to ensure phase continuity at bit boundaries.DMDVDMDV, the “demodulator” block, is a one-bit digital implementation of the semi-coherentRESET’ RST76SYSCK _n_I1..ilILrLn_rLJl_Ii_nil_J1_11ILJLJLJULJLJLWLELJLJLJ1ADCCK J1J1fLI1J1J1.YIJ1J1J1J1.J1J1C22 J1_i1iLT1_i1_JL.fBP IGig IC911____ __Figure 6.4: Timing clocks and strobes.MSK receiver. First, the received signal is multiplied with each of the two carrier waveforms,generated by two carrier synchronizers. The products are then processed with two integrate-and-dump filters based on bit timing recovered by the bit synchronizer. Finally, a decision devicedetermines the digital output on a bit-by-bit basis.Shown on sheet 5 is the block-level schematic of DMDV. CRLO and CRL1 each contain adigital phase-locked loop designed to recover from the receive signal the two suppressed carriers,respectively. Normally, CRLO and CRL1 requires the receive signal to be 4-bit digitized in two’scomplement representation. However, if the receive signal is hardlimited (i.e. in mode-A), thenonly one bit, indicating the polarity, is available. In this case, this 1-bit signal is input into CRLOand CRL1 via the most significant bit of the receive input, and the other three bits are controlledas follows to render the corresponding two’s complement representation:1. bit 0: set to 02. bit 1: setto 13. bit 2: set to be the same as bit 377This conversion is the function of the logic circuit preceding CRLO and CRL1. When QUAD ishigh (4-bit sampling mode), all four bits of the received signals are unchanged; however whenQUAD is low (1-bit sampling), only bit 3 is taken as is, and the other three bits are changed inthe manner just described.The carrier waveforms recovered by CRLO and CRL1 are then used to correlate the receivedsignal through two XOR gates (i.e. modulo-2 multiplication). Then the products are fed intoSTRV, a special data-aided digital phase-locked loop. STRV concurrently performs threefunctions: 1) digital integrate and dump, 2) bit-by-bit data extraction, and 3) symbol timingrecovery. The internal operations of sub-blocks CRLO, CRL1, and STRV are described below indetail.CRLOCRLO functions to regenerate and track the phase of the suppressed space carrier from thereceived signal. Because MSK waveforms contain no discrete components at carrier frequencies,CRLO first recovers the 2nd harmonic with a first order DPLL, and then divides it by two toobtain the original carrier waveform.As shown on sheet 6, CRLO itself is made up of six building blocks. Phase detection is doneby PHD in conjunction with the five flip-flops preceding it. ADD8, STORE, and PLLPcollectively play the role of a loop filter. DVCOO is equivalent to a numerically controlledoscillator, and included in it is a frequency divider required for regenerating the carrier from its2nd harmonic. Lastly, D1V48 produces timing strobes that synchronize ioop operation.For phase detection, the 4-bit received signal, in two’s complement representation, is firstsampled on the rising edge of the 2nd harmonic by four flip-flops, and its sign bit is sampledagain on the falling edge by another ifip-flop. Then the signs of the two samples are comparedto determine whether the 2nd harmonic is leading or lagging the carrier embedded in the receivedsignal. If the two samples have the same sign, the 2nd harmonic is lagging; otherwise, the 2ndharmonic is leading. Inside PHD (sheet 7) is a group of logic gates that two’s complement thesampled word, and a 4-bit multiplexer that selects either the first sample or its two’s complement,depending on the sign of the sample and the lead/lag decision reached. For example, if thesample is positive (negative) and the 2nd harmonic is lagging (leading), then the two’s78complement will be selected, and vice versa. As a result, the output of PHI) is a 4-bit number,in two’s complement representation, with its sign indicating the lead/lag condition and itsabsolute value corresponding to the magnitude of the phase error.PHD outputs one phase error datum per 2nd harmonic cycle. The data are accumulated bySTORE and ADD8. STORE (sheet 8) is an 8-bit resettable register, and ADD8 (sheet 9) is an8-bit full adder built from two cascadable 4-bit full adders. Every 48 cycles, the sum is decodedby PLLP, and STORE is subsequently cleared. PLLP (sheet 10) decides what kind of correctiveaction is needed in DVCOO according to the following rules:1. If abs(sum)<2, no correction is needed.2. If 2<abs(sum)c32, and if sum>(or <)0, then advance (or retard) carrier phase by one C44step.3. If abs(sum)>32, and if sum>(or <)0, then advance (or retard) carrier phase by two C44steps.The decision is then conveyed to DVCOO via two control signals: IDLE and UPDN.DVCOO (sheet 11), the numerically controlled oscillator, divides down C44 to generate the2nd harmonic of the space carrier (CKS). DVCOO accomplishes this with a correctable counter,a Count decoder, and a flip-flop. The counter is clocked by C44. Every time its count reaches 10,it is reset, and the flip-flop toggles once. This creates the 2nd harmonic which is then dividedby 2 to generate the space carrier. Phase adjustment is actuated via IDLE and UPDN, controlledby PLLP. With IDLE held low and UPDN held high for one C44 cycle, the count will increaseby two instead of one, thus advancing the phase of CKS by one C44 step. On the other hand,when both IDLE and UPDN are held low for one C44 cycle, the count will remain constant, thusretarding CKS by one C44 step.To synchronize the operation of the DPLL, two timing strobes, R and L, are needed. Bothsignals goes active once every 48 CKS cycles. R resets STORE, while L enables PLLP to issuea phase correction command. To generate R, D1V48 (sheet 12) divides CKS with a 6-bit counterand decoding logic, and obtains L simply by gating R rethned once by C44 with R itself.CRL1CRL1 (sheet 13) functions to recover the mark carrier. Its structure and operation are79identical to those of CRLO, except that DVCO1 is used in place of DVCOO. In DVCO1 (sheet14), the output flip-flop toggles whenever the count reaches 10, not 11, to produce the 2ndharmonic of the mark frequency.STRVThe STRV block is responsible for 1) integration of demodulated streams, 2) data extraction,and 3) symbol timing recovery. Like CRLO and CRL1, STRV is a first-order digital phase-lockedloop. As shown on sheet 15, it contains 4 sub-blocks: SPDV, LPP, NCOV, and DIV12. SPDVnot only detects phase error, but also performs data integration and extraction. LPP serves as aloop filter controlling NCOV, the numerically controlled oscillator. Loop timing is provided byDIV12..The phase detection technique used in STRV is different from that used in CRLO or CRL1.In CRLO or CRL1, it is done by comparing the polarities of the received signals sampled on therising and falling edges of the local signal. The same can not be done for symbol timing recoverybecause, 1) timing information is carried in not one, but two demodulated streams, and 2) nowell-defined state transition edges are available due to non-zero phase difference between thereceived signal and local carrier. Instead a data-aided approach based on early-late timing isadopted in SPDV (sheet 16), which makes use of three pairs of digital integrate-and-dump’s.Both data extraction and phase detection are using the same circuit.The implementation of this scheme requires not only the regular bit clock, but also an earlyand a late version of it. These clocks, supplied to SPDV by NCOV, control the interval ofintegration on three pairs of counters, acting as digital integrate-and-dump’s. The middle pairintegrates the two demodulated streams over the bit interval. The top pair does the same over anearlier interval using the early clock, and the bottom pair over a later interval using the lateclock. The final count value on each counter is a measure of the correlation between the receivesignal and one of the local carriers over the selected integration interval. Each counter is followedby a block called NORM (sheet 17) which decodes the count to yield a measure of the absolutecorrelation between the receive signal and the local carrier over the integration interval.First, data extraction is done simply by comparing the correlation values obtained from themiddle pair of counters using a 7-bit magnitude comparator (CMP7) made from two 4-bit80comparators (CMP4). If the lower counter, which monitors the mark carrier demodulated stream,presents a higher correlation, a “1” is detected; otherwise “0” is assumed. Second, to determinethe phase error, the greater of the two correlation values from the middle pair is compared tocorresponding results obtained by the other two pairs of counters over an early and late interval.For example, if the lower count exceeds the upper count over the nominal interval, then the threelower counts will be selected for phase error consideration. In essence, the selection is based onthe data detected. Hence this scheme can be referred to be data-aided. The selected set is latchedand then compared to determine the phase error according to the following rules:1. If learly correlation! > Inominal correlation! > Ilate correlation! => lagging.2. If hate correlationi > Inominal correlationi > learly correlationi => leading.3. Otherwise => inconclusive.These rules are based on the premise that the more accurate the bit clock is, the higher thecorrelation becomes. They are realized with hardwired logic including two 7-bit comparators(CMP7) and two AND gates.Using the scheme just mentioned, SPDV extracts a datum and makes a lead/lag decision foreach bit interval. The data, along with the bit clock, are exported to the host. Phase decisions areconveyed to the ioop filter (LPPL) via two active-high signals: LEAD and LAG. LPPL (sheet18), a binary sequential filter, functions to determine the ensemble average of the phase errorover 12 bit intervals. Its implementation includes two 4-bit counters, one monitoring the LEADinput, and the other the LAG input. The counters are reset by R once every 12 bit intervals. Atthe end of each reset interval, the counts stored in the two counters are compared using a 4-bitcomparator (CMP4). The majority rule applies here. If the LEAD count exceeds the LAG count,ADD will be asserted to retard the bit clock; or if vice versa, DEL will be asserted to advancethe bit clock.NVCO (sheet 19), the numerically controlled oscillator, is driven by C9. It is structurallysimilar to DVCOO or DVCO1 used for carrier synchronization. First, the early clock is generatedfrom a divide-by-66 circuit which features a 7-bit correctable counter. Second, a 15-bit shiftregister is employed to delay the early clock to produce the nominal clock. Third, the nominalclock is, in turn, delayed on another 15-bit register to render the late clock. The clock phase isadjusted via ADD and DEL. When DEL is asserted, the counter will skip a cycle, thus shifting81the clocks backward by one C9. On the contrary, asserting ADD will doubly increment thecounter and as a result shift the clocks forward by one C9.The operation of this DPLL is synchronized with two timing strobes: R and L. Strobe Rresets the sequential filter (LPPL) once every 12 C44 clock cycles. Strobe L enables theADD/DEL output of LPPL periodically. Both R and L originates from ,DIV12 (sheet 20). R isgenerated by dividing down the bit clock by 12 with a 4-bit counter, and L is obtained by gatingR delayed by one C44 with R itself.CDTShown on sheet 21 is the schematic of the CDT block which performs carrier detection. Itcontains an 8-bit up-counter that is reset by CCD. The clock input of this counter is connectedto the receive line (RXD). In the presence of a carrier signal, RXD will toggle and increment thecount value. At the end of each reset interval, the counter is decoded to determine if there isactivity on RXD. The result is updated on a flip-flop. Under normal on-line condition, the countshould reach some value in the neighbourhood of 90. But taking into consideration of channelimpairments on the receive line, an arbitrarily low decision threshold of 8 is chosen. That is, ifthe count exceeds 8, then carrier presence is assumed.STARTDIAGNOSISLOOPBACKFigure 6.5: Loopback configuration for self-test.82TESTTEST, the “test” block, performs automatic testing and functional verification of the on-chipmodulator and demodulator. As shown in Figure 6.5, when the modem is in self-test mode, testdata is looped from TEST to MOD, to DMDV, and then back to TEST. The schematic of TESTis shown on sheet 22. A 7-bit pseudo random shift register is used to generate the test pattern,each frame of which is 127 bits long. Data received from the demodulator is compared with datasubmitted to the modulator on a bit-by-bit basis using a XOR gate. Any occurrence of a compareerror will be flagged on the error register. Timing control is provided by a counter that keepstracks of the number of transmitted data frames. It ensures that the compare circuit is notactivated until five frames of test data have been transmitted, because the modem takes asubstantial amount of time to acquire carrier and symbol synchronization. After one frame ofcomparison, the test is terminated, and the outcome is indicated on the GOOD line.837. THE MAKING OF A POWERLINE MODEMTo illustrate the application of the MSK modem chip designed in this thesis, a high speedmodem unit based on the modem chip is built. The unit facilitates half-duplex data transmissionbetween two data terminal equipment (DTE) via intrabuilding AC powerlines. After a briefreview of the transmission and noise characteristics of powerlines, this chapter presents the board-level design of this compact almost-all-digital MSK powerline modem, including descriptions ofthe DTE and powerline interface circuits.7.1 Powerlines As Communication Channelsn(t)s(t) ch(t) ‘1 >r(t)Figure 7.1: Model of intrabuilding powerline channels.84The channel model of intrabuilding powerlines appears in Figure 7.1. A signal s(t) injectedinto the powerline by the transmitter will be received as r(:) at the receiver. A transformed andcorrupted version of s(t), r(t) is given byrQ) — sQ)Ø ch(t) + n(t) <7.1>where ch(t) is the impulse response of the physical channel, and n(t) stands for noise interference.Channel function ch(t). accounts for the impedance and signal attenuation effects of thechannel. It is time-varying, and depends not only on the signal frequency but also on the positionof the transmitter and receiver, and the load profile of the powerline circuit. Topology andphysical characteristics of intrabuilding power circuits are discussed in [8, 12]. Nicholson andMalack [53], and Vines, etc. [54] measured the input impedance of powerlines in commercialbuildings. This is the driving-point impedance into which the transmitter sends a signal and fromwhich the receiver extracts a signal. It is attributed to distribution transformer secondary, copperwiring, and electrical loads present in a powerline network. Chan [55] investigated the attenuationof signals propagating across intrabuilding powerline networks. Attenuation, in this case, isdefined as the ratio between the received signal amplitude and transmitted signal amplitude. Theseverity of attenuation depends, to some degree, on the phase relationship between the transmitand receive points of access to the powerline circuit. In addition, attenuation level may alsofluctuate rapidly and periodically with time, giving rise to signal fading. Signal fades of 120 kHzare observed on powerline channels. This effect is in part caused by time variation in driving-point impedance at the transmitter and receiver as a result of load switching (e.g. rectifier circuitsin power supplies). Due to the complexity and unpredictability of powerline networks, explicitrepresentation of ch(t) is not possible. Generally it has the following characteristics:1. It presents an impedance of about 10 to the transmitter and receiver in the 10 - 200 kHzrange.2. It behaves like a low-pass filter; any frequencies above 150 kHz are severely attenuated byup to as much as 50 dB.3. Signal attenuation on opposite-phase and cross-phase paths is greater than on in-phase paths(Figure 7.2).85Figure 7.2: Intrabuilding powerline transmission paths.Noise function n(t) accounts for noises inherent in a powerline channel. Like ch(t), n(t)is very much time varying. Performing spectral density measurements, Smith [56] found that thebackground noise intensity of powerlines decreases at approximately 29 dB/decade over the 10 -100 kHz range. Vines, etc. [57] characterized different types of noise sources on residentialpowerlines over the 5 - 100 MHz range. Powerline noise can generally be regarded as acombination of background noise b(t) and impulse noise i(t). Trussel and Wang [58] verified thatb(t) is typically Gaussian. The time domain characteristics, including amplitude, width, andinterarrival time of i(t) have recently been measured by Chan [59]. Depending on which noisesources and their proximity to the receiver, impulse strength can be as much as 10 - 40 dB abovebackground noise level. Impulse frequency is dominantly 120 Hz. Impulse width can vary up toa few percent of the period of a 120 Hz signal. It is the presence of 1(t) that limits the on-linebit error performance of powerline modems, especially in high speed transmission where data bitduration is comparable to or less than the impulse width.A B in-phaseA B opposite-phase867.2 Modem System ArchitecturePOWERr= rRS232 INTERFACEI MSKI — MODEM — 1 POWERUNE&)ARD =JINTERFACEF I0GONTROL I MODEO_.RESET.._.Figure 7.3: MSK powerline modem I/O interface.Pin Name Type Speed DescriptionTXD I 9.6 kHz transmit data from DTETXC 0 19.2 kHz transmit clock to DTERXD 0 9.6 kHz receive data to DTERXC 0 19.2 kHz receive clock to DTERTS I async Request_To_SendCTS 0 async Clear_To_SendDCD 0 async Data_Carrier_DetectMODEl I DC mode control -- bit 1MODEO I DC mode control -- bit 0RESET I DC synchronous resetGOOD 0 DC on-board ASIC diagnosisPLH I/O analog connect to hot wirePLN I/O analog connect to neutral wirePLE I/O analog connect to earth+5V power DC +5V DC supply+12V power DC +12V DC supply-12V power DC -12V DC supplyGND ground DC ground referenceTable 7.1: I/Os of the MSK powerline modem board87The powerline modem board supports two-way data transfer at 19.2 kbps in half-duplexmode. Its I/O is shown in Figure 7.3 and specified in Table 7.1. Communication between themodem and DTE is facilitated by a synchronous serial interface in compliance with RS232specifications [60, pp. 421-429]. At this interface, transmit and receive data are NRZ formatted,and are timed by bit clocks originated from the modem. Connection of the modem to thepowerline is achieved with a line coupling network. In transmit mode, an 8 sinusoidal MSKcarrier wave is emitted from the modem board into the powerline. The output power of thetransmitter is rated at 3 W. Depending on input data, carrier frequency is switched between 105.6kHz (space) and 115.2 kHz (mark). This corresponds to a centre carrier frequency to bit rate ratioof 5.75. The spectrum of the transmitted signal centres at 110.4 kHz and has a bandwidth ofabout 23 kHz, which is within the passband of typical intrabuilding powerlines. In receive mode,the modem extracts MSK signal from the powerline. For proper reception, the signal arriving atthe receive input is required to have an amplitude of at least 0.1 V1,, which corresponds to thequantization threshold of the modem’s input stage.Figure 7.4: Functional block diagram of the powerline modem.88Figure 7.4 shows the functional block diagram of the modem. In addition to modulation,demodulation, and carrier detection, two auxiliary functions are needed: DTE interfacing andpowerline interfacing. First, based on the synchronous RS232 protocol [60, PP. 421-429], theDTE interface is responsible for the followings:1. Serial transfer of digital data and bit clocks between the modem and DTE.2. Conditioning of interface signals to meet RS232 electrical specifications.3. Handshaking with the DTE to establish the transmit/receive status of the modem.Second, the powerline interface serves the following purposes:1. Filtering and power amplification of transmit waveforms.2. Filtering and digitization of receive waveforms.3. Two-way AC coupling of modulated signal between modem and powerline.4. Isolation of modem from 120 V AC voltage.5. Provision of impedance matching and surge protection.Physically, the modem board contains two subcircuits, a semicustom ASIC, and a crystaloscillator, as shown in Figure 7.5. Both subcircuits are made up of off-the-shelf components.Subcircuit 1, which is partly analog and partly digital, functions as the DTE interface, andsubcircuit 2, which is all analog, as the powerline interface. Modulation, demodulation, andcarrier detection are handled by the MSK modem chip, the heart of the modem unit. This chipFigure 7.5: Implementation of the powerline modem.89operates in synchronism with the 5.0688 MHz (as determined below) clock supplied by thecrystal oscillator that has an accuracy of 0.01%. In this design, because most of the signalprocessing functions, including carrier and bit synchronization, are implemented digitally, suchproblems as temperature drift and component aging are largely avoided. Furthermore, by meansof VLSI implementation, the physical size, power consumption, and manufacturing cost of themodem are considerably reduced.7.3 Modem Chip ApplicationWith the bit rate and carrier frequencies specified, the modem chip’s operationalcharacteristics can be computed by using the design equations presented in previous chapters:1. The modem chip should be driven at 5.0688 MHz in order to render 19.2 kbps transmissionon 105.6 kHz and 115.2 kHz carriers (equations <5.4-6>).2. With a system clock stability of 0.01%, the absolute and percentage phase jitter of themodulated output are approximately 7.8 Hz and 0.0071%f respectively (equations <3.1-2>).3. The two on-chip carrier synchronizers have a lock range of 6.8 kHz. (equation <4.23>). Thisrange is adequate because tone spacing is only 9.6 kHz.4. The lock range of the on-chip bit synchronizer is approximately 0.05 kHz (equation <4.31>).5. Carrier detection delay is 1.5 x 16 x 1920(Y = 1.25x103 second (Section 3.3).For decoupling purpose, several 0.1 hF capacitors are connected across power and gmundin the proximity of the modem chip. In order to avoid CMOS latch-up [50], all unused input pinsof the chip are pulled down via 10 k2 resistors.7.4 DTE InterfaceDigital information is serially transferred between the DTE and modem chip via the DTEinterface (subcircuit 1). Shown in Figure 7.6 is the schematic of this interface (adapted from R.Jeffery’s work [61]). A hybrid analog/digital circuit built with off-the-shelf components, theinterface provides the functions of RS232 signal conditioning and handshaking.A universally accepted standard, RS232 specifies the electrical and mechanical details ofthe serial interface. The bipolar signal levels used in the RS232 standard are not at all compatiblewith CMOS levels, which are unipolar. Therefore it is necessary to convert those signals going90a’ Cl,0 Ifrom the DTE to the modem from RS232 level to CMOS level, and vice versa for those signalsgoing in the opposite direction. This two-way signal conditioning function is achieved in thesubcircuit with the 1N14C88 driver ICs and 1N14C89 receiver ICs.Figure 7.7: State diagram for RS232 interfacing.With RS232, data transfer between the DTE and modem is coordinated with two signals:Request_To_Send (RTS) and Clear_To_Send (CTS). When the DTE has data to transmit, itasserts RTS high. Then, if the channel is sensed to be idle, the modem will assert CTS high topermit the DTE to start a transmission. On the other hand, if carrier presence is detected, CTSwill remain inactive thus forbidding the DTE to transmit. This kind of handshaking is controlledin the DTE interface with a simple one-flip-flop-based state machine. Figure 7.7 shows thecorresponding state diagram. Basically, the circuit sets CTS according to the status of RTS, andCarrier_Detect (CD). The latter, originating from the modem chip, is an active high signalindicating carrier presence. CTS is asserted high if and only if RTS is high and CD is low. CTSis reset when RTS is released at the end of a transmission. CTS also reflects the transmit/receivestatus of the modem: when CTS is high, the modem transmits; otherwise, the modem receives,which is the default state.7.5 Powerline InterfaceFigure 7.8 shows the schematics of the powerline interface (originally designed by R.Jeffery [611). Made up of off-the-shelf analog components, the interface includes a line couplingnetwork, a relay, a transmit signal processing circuit, and a receive signal processing circuit. Theline coupling network consists of a 1:1 transformer, a zener diode, and two capacitors. TheRTS=1&CD=ORESET RTS=O92Cl)0 (T I-’.0 P4 (t 0‘Cl priRELAYSPST,12V02I1N4148220UF—0335VL1N4148RXC1R--ADCCkIRXSO3,IRXSO2,.RXSI(•RXSO.1,.IRxSO.0,..TXCIRTXS-I-xaI030FlrHJ‘o’\o 1I4AtVIP1250VI—cJTJGE130L209PLUGACMALE0311UP—.—————.250VII028029220UF1UFDl.-5VUSE7406-T-ItiCOMMUNICATIONSLABnrnanflsrMlflFFlrflTflICALLINECOUPLING.RELAY.ANDPOWERAMP.SizeDocumentNumberREVAPLM-O0l0C)2NDORDERQUTTERWORTHLOWPASSFILTER0—1326CI—z(t 0 0 (VRI12K12KPOWERAMPLIFICATION.q.12V 1 NF100NF—12VSUPPLYDECOUPLINGNEAROPAMPCsbONECOMMUNICATIONSLABDEPARTMENTOFELECTRICALENGINEERING.UBOrItITRANSMITLOWPASSFILTERIz1ocumentI’lumb.rREVAl0PLM-002Acoupling network facilitates AC coupling of carrier signal to and from the powerline whileisolating the rest of the modem from 120 V AC. In addition, it provides impedance matching andsurge protection. The transmit and receive circuits access the line coupling network through therelay. This relay is controlled by the cTS signal from the DTB interface: when cTS is high, therelay goes on, connecting the output of the transmit circuit to the line coupling network; whenCTS is low, it goes off, connecting the output of the receive circuit to the line coupling network.In the transmit circuit (Figure 7.9), the modulated square wave carrier output of themodem chip is filtered by a 2nd-order bandpass filter, that has a bandwidth of 100 kHz, centringat 90 kHz. Before being relayed to the line coupling network, the resulting sinusoidal waveformis amplified with an audio power amplifier (LM384) that has a voltage gain of 50. The bandpassfilter also helps to suppress any spurious components generated by the modulator.In the receive direction (Figure 7.10), the analog signal received from the powerline viathe line coupling network is filtered by a 4th-order Butterworth bandpass filter to extract theMSK waveforms. This bandpass filter also prevents possible overloading of the received inputsignal by noise. The filter bandwidth is 40 kHz, centred at 110 kHz. Its output is amplified withLF356 by a factor of 20. Subsequently, a comparator (LM339) hardlimits the signal so that it canbe input to the modem chip for demodulation. Alternatively, one may use a 4-bit A/D converterto digitize the signal because, as mentioned in Section 4.2, the received input to the modem chipcan be either a 1-bit or 4-bit word.7.6 System-Level DesignFigure 7.11 contains the board-level modem schematic showing interconnections amongthe DTE interface subvircuit, the modem chip, and the powerline interface subeircuit. The modemboard requires +5 V, +12 V, and -12 V DC supplies, and has a maximum power rating of 3.5W. Also, it uses a 25-pin D-connector to communicate with the DTE, and a three-prong plug toaccess the powerline. For instance, in the case of a PC host, one end of the modem will beconnected to the serial port of the PC, and the other end plugged into an AC outlet. To utilizethis powerline modem, a DTE must be equipped with a synchronous RS232 serial card or itsequivalent. In addition, it is the DTE’s responsibility to append, probably via software, apreamble sequence to the beginning of each transmit data packet. This preamble should consist95—.-4 rJ) 0 Co 0 CD 0 (0 (0 c7q00 0 Co Cl) Cd, 02.7k4THORDERBUrrERWORTHBANDPAODFILTER(Ic—119.3kI-Iz.EW—65.8I<I-IZ)R5R95532355N+12V•12Vi--IJ.0137.010IONF1ONF012Cli1ONF1ONF—12V—12V220U3051<DlINS14R3310KCOMMUNICATIONLASDEPARTMENTOPELCTRI0ALENGINEERING.UBO20M-j-ItIRECEIVEBANDPASSFILTERSizeDocumentNumberREVAPLM-003A0wof two segments: a reversal sequence and a sync word. The former, a sequence of alternating 0’sand l’s, is recommended to be at least 236 bits long (see Section 5.4.5). It trains the receivingmodem. The latter, also known as the frame marker, is usually less than 30 bits long. It isrequired for frame synchronization by the receiving DTE. Because of their special autocorrelationproperty, the Barker sequences and Willard sequences, among others, are good sync wordselections [18].Figure 7.12: Insertion of a scrambler/descrambler circuit into the modem.Figure 7.13: Enhanced modem with built-in scrambler/descrambler and codec.98The modem board can easily be modified to accommodate additional functions in thephysical layer. One possibility is the insertion of a data scrambler between the DTE interfacesubcircuit and the modem chip (Figure 7.12). Data scrambling is highly recommended [62]because it has the merits of providing some communication security and preventing the receiverfrom loss of bit synchronization caused by long sequences of 0’s and l’s in the data pattern.Another possible enhancement is to add a FEC codec chip in the data path (Figure 7.13).Convolutional coding and bit interleaving techniques are proved useful in combating impulsenoise inherent in powerlines [63]. General purpose FEC chips are now commercially available[64, 65, 66]. As well, a special purpose FEC chip with bit interleaving capability is currentlybeing developed at the University of British Columbia to accompany the MSK modem chip aspart of a chip set for powerline LAN implementation.998. TESTING AND PERFORMANCE EVALUATIONIn this chapter, the design and performance of the MSK modem chip are tested andevaluated. This includes, first, functional verification of the integrity and operation of the chip,and, second, determination of the bit error rate, block error rate, and packet error rate of thepowerline modem unit over an AWGN channel as well as actual intrabuilding powerlines. Inaddition, the modem’s output spectrum, carrier phase and bit timing error characteristics aremeasured.8.1 Functional Verification Of Modem ChipFive modem chip samples are produced. To verify that they are properly fabricated andmeet design specifications, three different tests are performed: BIST test, loopback self-test, andpoint-to-point test. The first of these is a pass/fail test which exercises the on-chip diagnosticcircuit. In the latter two tests, the bit error performance of the chip is measured; moreover, itstest pins are probed to check the internal signals as well as to measure the carrier phase and bittiming error of the on-chip demodulator.8.1.1 Built-In Self-TestAs explained in Section 3.4, the BIST feature provides a quick and automatic means oftesting the integrity of on-chip modulator and demodulator without using special test equipment.To run this test, the chip is first programmed into test mode (MODE1=MODEO=l), and thevoltage level of the “GOOD” pin, which indicates test outcome, is displayed on an oscilloscope.Then BIST is activated by issuing a hardware reset (via the RESET pin). At the end of the testwhich lasts about 0.05 ms, GOOD should remain high if no errors are detected.The BIST test is run on each of the five samples of the MSK ASIC. All give a positiveresult.8.1.2 Loopback Self-TestThe setup for this test is depicted in Figure 8.1. With the chip in loopback mode100(MODE1=1, MODEO=O), a HP 1645A data error analyzer is used to measure the bit errorprobability of the “noiseless” loopback connection. The analyzer injects pseudo-random test datainto the modulator and monitors the resulting output of the demodulator for errors. After runningthe test at 19.2 kbps continuously for about 15 hours, the bit error probability is found to be lessthan iOu.During this loopback self-test, the signals on the eight test pins of the chip (see Section4.3) are examined with an oscilloscope. UDO and UD1 give a good indication of the propernessof the carrier synchronizing loops. One can tell whether the bit timing recovery loop is in lockor not by inspecting the ADD and DEL signals. MAXM and MAXP are the early and late.versions of the locally recovered bit clock. SIGO and SIG1 carry the demodulated subbit streams.In addition, the carrier phase error of the demodulator is determined by measuring theminimum pulse width of the SIGO and SIG1 signals. This pulse width is observed to be about0.5 Ls, which corresponds to a carrier phase error of ±3%.To measure the bit timing jitter of the demodulator, the transmit clock generated by themodulator and the receive clock recovered by the demodulator are simultaneously displayed ona dual-trace oscilloscope. The waveforms indicate a received bit clock jitter of ±0.35 p.s, whichis approximately ±4% of the period of a 19.2 kHz clock.Figure 8.1: Chip-level loopback BER test.1018.1.3 Point-To-Point Transmission TestShown in Figure 8.2 is the setup for the point-to-point transmission test. Again, the HP1645A data error analyzer is used, but this time it detemiines the bit error probability of datatransmitted from one chip to another via a copper’wire approximately one foot long. The bit errorprobability of this system is measured to be less than iOn, thus validating the operation of thetwo chips.During this point-to-point BER test, the test pins are probed to observe the operation ofsome internal circuitry. The average carrier phase error and bit timing error of the receiver aremeasured to be ±3% and ±4%, respectively.8.2 Modem Performance In A Controlled EnvironmentIn this section, the observed signal spectra and bit error rate (BER) of the MSK powerlinemodem unit in a controlled environment are reported.Figure 8.2: BER monitoring for inter-chip communications.1028.2.1 Signal QualityTo measure signal quality, a modem board is set up to transmit pseudorandom data,generated by a data error analyzer, to another modem board at 19.2 kbps via a piece of one-foot-long copper wire.First, the frequency spectrum of the transmitted signal is obtained using a HP 497Pspectrum analyzer, and it is shown in Figure 8.3.Next, the timing jitter and frequency spectra of the 19.2 kHz receive clock signal aremeasured. The results appear in Figures 8.4 and 8.5.Finally, by examining the SIGO, SIG1, and RXCK signals from the modem chip on thereceive modem, the carrier phase error and bit clock jitter of the receiver are estimated to be±4.5% and ±5%, respectively.8.2.2 Performance In AWGN EnvironmentBy using the setup shown in Figure 8.6, the bit error probability of the powerline modemFigure 8.3: Modern transmit signal spectrum (vertical scale = 10 dB/div, horizontal scale = 10kHz/div).103 C—Figure 8.4: Receive bit clock timing jitter (vertical scale = 5 V/div, horizontal scale = 10 is/div).board over an AWGN channel is determined as a function of the received energy to noise ratio(E/N). To simulate an AWGN channel, white noise (from a Bruel & Kjaer 1405 noise generator)is added (using an op-amp) to the transmitted signal before it is sent to the receive modem overa one-foot-long copper wire. At the transmit end, test data is supplied to the transmit modem byTX MODEM RX MODEPtFigure 8.6: Evaluation of modem performance in an AWGN channel.104Figure 8.5: Spectral line at receive bit clock frequency (vertical scale = 5 dB/div, horizontalscale = 250 Hz/cliv).a data error analyzer; at the receive end, another data error analyzer iseiiployed to detect andcount errors in the demodulated bit streams.The output of the receive bandpass filter is monitored with a true rims voltmeter. Energyper bit, E, is given by:ti ‘2E - <8.1>Rwhere K = constant of proportionality, V,. = voltmeter reading with the white noise generatordisabled, and R = bit transfer rate. In this case, R equals to 19.2 kbps. The noise density, N, isgiven by:(V 2N — K’_“‘ <8.2>Beq105where = voltmeter reading with the transmitter switched off, and Beq = equivalent noisebandwidth of the receive bandpass filter. By integrating the area under the frequency responsecurve of the filter, Beq is found to be about 85 kHz.Therefore from <8.1> and <8.2>,E — (Vrn.J)2BeqN V R<8.3>As a parameter, EIN is varied by adjusting the output level of the white noise generatorwhile holding Vr fixed. For accuracy and precision, several BER measurements are taken foreach E/N setting, with each BER measurement calculated from an error count of at least 100, ifpossible.theoretical measured — — theory: 4.5%/5°IoFigure 8.7: BER performance of the MSK modem in an AWGN environment.Modem Performance(AWGN)1 E+0O1E-Ol1E-01E-031E-0zLU1 E-0E1 E— -.7 8 9 10 11 12 13 14 15 16 17 18Energy to Noise Ratio (E/N) - dB106The results of this experiment are plotted in Figure 8.7. Also shown in the figure are twotheoretical BER curves computed using formula derived in Chapter 5. The first curve predictsthe AWGN performance of the binary partial decision MSK demodulator under ideal condition(i.e. perfect synchronization). The second curve takes into account of the effects of canier phaseerror and bit timing error, which are observed to be approximately ±4.5% and ±5%, respectively.The measured BER values are approximately 2 dB higher than the first curve, but are in closeagreement with the second curve. Thus the modem’s performance degradation in AWGN can beattributed primarily to imperfect carrier and bit synchronization.8.3 Modem Performance On Powerline ChannelsTo evaluate the performance of the powerline modem over intrabuilding powerlines, itsbit error rate (BER), block error rate (BLKER), and packet error rate (PKTER) for datatransmission between two points in an actual intrabuilding powerline network are measured. Thetests are conducted in the Macleod Building (Department of Electrical Engineering) located onthe University of British Columbia. campus. It is a large multi-use commercial building with fourfloors including a basement. A wide variety of loads are present, including industrial machinery,computers, and office equipment. This intrabuilding powerline network should be representativeof those found in other commercial or industrial premises.Figure 8.8: BERJBLKER measurement over intrabuilding powerlines.107The BER/BLKER test setup is diagrammed in Figure 8.8. Two modems, one as atransmitter and the other as a receiver, are plugged into separate AC outlets to access thepowerline channel. At the transmit end, test data is supplied to the transmit modem by a dataanalyzer. At the receive end, demodulated data from the receive modem is submitted to anotherdata error analyzer which measures the bit error rate and block error rate. Here the block errorrate is defined as follows:BLKER — (number of received blocks containing bit errors) <84>(total number of transmitted blocks)Each data block is 10000 bits in length.In order for a data communication system to successfully receive a data packet, thefollowing conditions must be satisfied:(1) proper training of the receiving modem;(2) recognition of the opening flag of the packet;(3) recognition of the closing flag of the packet;(4) no detected errors in data-carrying segment of the packet.If any one of (1), (2) and (3) is not met, the transmitted packet will be lost. If (4) is violated, thereceived packet will be discarded. Thus, one can defme the packet error rate as follows:PKTER (no. of lost packets) + (no. of received erroneous packet) <85>(no. of transmitted packets)While the block error rate is strictly attributed to noise-induced bit errors, the packet error ratedepends on a number of additional factors, which include modem synchronization, framesynchronization, and data link control protocol The packet error rate therefore a better and morerealistic indication of overall transmission efficiency.PKTER measurement is facilitated by specialized PC-based modem testing softwaredeveloped at the Electrical Engineering Communications Laboratory in the University of BritishColumbia. In each test run, data packets of 1000-bit long are transmitted across the powerlinefrom one PC to another; after 1000 packets are received, the test is terminated, and the108PC_____HOSTasync PROTOCO31 sync J POWERLINE],FThI Eli I k RS232 BOARD k RS232 MODEM rFigure 8.9: Software-based packet error rate measurement.percentage of transmitted packets that are lost and the percentage of received packets containingbit error(s) are determined. Because the modem testing software is designed to operate with theasynchronous RS232 serial port of a PC, the modem board which supports only synchronousRS232 interface cannot be directly connected to the PC’s serial port. This incompatibility isreconciled with the use of a protocol board (courtesy of Aries Wong), as shown in Figure 8.9.Having an asynchronous interface on its host side and a synchronous interface on its modem side,the protocol board performs frame synchronization and packet buffering.8.3.1 Performance Over A Small AreaThe BER, BLKER, and PKTER of the powerline modem for data communication withina room in the building are determined.BERJBLKER Vs Transmitted Signal Level-First, the performance of the powerline modem over actual powerline channels isdetermined as a function of the rms output level of the transmitter (Vj. V is measured in unitsof dBmV:dBmV — 20 log[ rms signal level in voltsj <8.6>0.001Values of V3 range from 0 to 70 dBmV.Two sets of measurements are made within Room 458, a research laboratory in the109building. In this room, there are ten Sun workstations, five PCs, as well as several electricalinstruments such as oscilloscopes and function generators.In the first set of measurements, the transmitter and receiver access the X, Y, and Zphases of the powerlines via outlets on two separate power-bars approximately 50 feet apart. Thecorresponding BER and BLKER results, as shown in Figure 8.10, indicate that transmissions inand between the X and Y phases are reasonably reliable. Their BERs are or lower when Vis above 55 dBmV. Performance increases with V, with in-phase transmission having a 10 dBmVadvantage over cross-phase transmission. Conversely, for those transmissions involving the Zphase, be they in-phase or cross-phase, the BERs are very high (_101) for all V values. Thisimplies that the Z phase of the powerline is relatively noisy; indeed, most workstations in theroom draw power from this phase.In the second set of measurements, the transmitter and receiver are side-by-side, accessingthe powerlines via outlets on a single power-bar. Figure 8.11 shows the results obtained for thisset of measurements. They are very similar to those of the first set of measurements, except thatconsiderably better performance is attained for in-phase transmission over the Z phase. Thisimprovement can be attributed to the fact that the corresponding transmission segment is shortand localized.Packet Error RatePower Phase Packet Error Rate Packet Loss Ratex->x- 0%-0%X->Y 0%-0%X —> Z—100%—80 %Table 8.1: Packet error/loss rate for transmissions between two power-bars 50 feet apart in thelaboratory.With the transmitter output fixed at 70 dBmV (8 the packet error rates of the MSKmodem for transmission between those two power-bars that are 50 feet apart are determined. Dataare sent from the X phase of the first power-bar to the X, Y, and Z phases of the second power-bar. The measured PKTERs of these transmissions are listed in Table 8.1. Also tabulated there11016-011E-02a- 16-65016-04IE-OE16+0616-011E-651E-O21E-016-Of60 65 40 65 0TransrM Signal Level - dBmVrne>‘16-012aa16-6565 60 65 40 45 60 65 60 65Transm SIgnal levd - dBrnVrmsL->A—.— L> Y _ L>L Z->X-.*- Z->Y —— L->tFigure 8.10: BERJBLKER -- transmitter and receiver on power-bars 50 ft apart in the lab.111a. BERforX->(X,Y,Z):::::ç::?;s::z:::16-011E-00d. BLKER forX -> (X, Y, Z):z::z.:::E:E:::s::z:z:z:56065404560656065Transm Signal Level - dBmVnm25 3) 25 40 45 50 55 60 65 0Transm Signal Level - dBmVnnaI A-> A-*- A-> Y .-— A->b. BER for Y -> (X, Y, Z)I —— -> -> —s-- X -> te. BLKER forY -> (X, Y, Z)1E-Ol16-65F-T->A-—— Y ->1 Y>t.c. BERfQrZ->(X,Y,Z)I_._v->x__*_Y->Y-.—Y->z If. BLKERf0rZ->(X,Y,Z)_16-0116-65IE-651E-O16-Of65 60 65 40 45 60 65 60 65 .0Transm Signal Level - dBmVrn25 3) 25 40 46 50 55 SI) 65 .0Transm Signal Level - dBmVrnIE-Ol1E.a. 1E.1E.G1E-icL1E.,CIE.O11E01E.O1E-O1E-OIE.o1F.-O11E-a. 1E-1E.ob. BERforY->(X,Y,Z)c. BERforZ->(X,Y,Z)I_._Z.>X_fr_Z.>Y_._.>Z I I-)A--*- £->Y _ L->LFigure 8.11: BER and BLKER performance -- transmitter and receiver on one power-bar in thelaboratory.112a. BERforX->(XY,Z) d. BLKER for X -> X, Y,Z)4O 45Tr.n1 Sçra Le dBriMn4oTrwT* gn Ledel - mVrrA-> A..— A.> V A L j I X->X—1K->Y-— A->Ze. BLKERforY->(X,Y,Z)1E-Ol1E1E-I1EeCIE-Ol1E-Tr.rr* Sgn L.ve - dBmVrn.—Y.>x.-- Y.>Y—.- Y->ZTrwnE Sgn Iwel - riMn.Y->A—— Y->T T>Lf. BLKER for Z -> (X, Y, )Trawr Sgn LweI - dBmVrn45LzeI -n*rnare the corresponding packet loss rates (PKTLR), namely, the percentage of packets that aretransmitted but not received.As expected, the PKTER of a transmission is correlative with its BERIBLKER. Over a“good” link (BER i0 or lower), the PKTER is close to zero. Conversely, over a “poor” link(BER 10.2 or higher), the PKTER and PKTLR can reach as high as 100% and 80%,respectively.K 59ft >__________________________C1 B4 LEGEND:A 4th Floor E. Wing StairwellLI B = 4th Floor N. Wing StairwellC 4th Floor N. Wing StairwellF ü G 172 D 3rd Floor N. Wing Stairwellft E=3rdFloorN.WiniStairwellF Room 214 (2nd FloorG = Room 113 (Basement)transmitter receiverBuilding Height 50 ftR•181ftFigure 8.12: Locations of various access points in the building.8.3.2 Performance Over A Large AreaDescribed below are the measured BER, BLKER, and PKTER of the powerline modemfor data communications across the building.113Designation Location Power PhaseA 4th Floor East Wing Stairwell YB 4th Floor North Wing Stairwell XC 4th Floor North Wing Stairwell ZD 3rd Floor North Wing Stairwell XE 3rd Floor North Wing Stairwell ZF Room 214 (2nd Floor) YG Room 113 (Basement) ZTable 8.2: Power phase on various AC outlets in the building.BIT ERROR RATEFOR LARGE-AREA COMMUNICATIONS1 E-O1IE-oa: :: ::::::::::::::;:::::::::::::::::::::::::::::::::::::::::::::::1EO5,1E-OQt’1E-O71E-08 APOINT OF TRANSMISSIONFigure 8.13: BER performance of the powerline modem for “long-distance” communications.BERJBLKER Vs Modem SeparationWith the transmitter output fixed at its maximum level of 70 dBmV, the bit error rate andblock error rate of the modem over powerline channels linicing different areas of the building aredetermined. Four groups of measurements are taken:1. intra-floor-44: transmission between two points on the third floor;2. inter-floor-34: transmission from an AC outlet on the second floor to one on the third floor114BLOCK ERROR RATEFOR LARGE-AREA COMMUNICATIONS10090— 80w 706050POINT OF TRANSMISSIONFigure 8.14: BLK.ER performance of the powerline modem for “long-distance” communications.3. inter-floor-24: transmission from an AC outlet on the first floor to one on the third floor;4. inter-floor-14: transmission from an AC outlet in the basement to one on the third floor.Shown in Figure 8.12 is a map indicating the locations of the AC outlets used in thesemeasurements. The power phases of the outlets are identified in Table 8.2.The modem’s BER and BLKER over each link are determined by averaging valuesobtained from several consecutive test runs, each having at least 100 accumulated bit errors. Theresults are presented in Figures 8.13 and 8.14.For thoroughness, additional BER tests are conducted using several other transmit points(unidentified in Figure 8.12) throughout the building, and the outcomes are summarized in Figure8.15.Overall, the BER performance of the MSK powerline modem ranges from 10.2 to less thaniOfl, and is fairly independent of the physical separation of the transmitter and receiver. Instead,BER depends on other factors, which, in order of importance, include:1. whether the transmission path is in-phase or cross-phase;115BER for Different Powerline Links(Transmit Signal Level =70 dBmV)I E-O1 E-OaI N K1E-ON- 1E-04N1E-O1E-Oq *NI E-Oi1 E-O8 ITF’-44 rTi-34 ITF-24 ITF-I 4Figure 8.15: More BER measurements over a large area.2. the loading profile of the channel;3. the time and day on which the measurement is taken.In general, for “large-area” communication, better performance can be achieved over an in-phasepath than an cross-phase path. The BER of transmission over an in-phase path usually falls intothe range from i0 to less than i0. When switched over to an cross-phase path, the BER isdegraded by approximately two to three order of magnitude and ranges from 102 to Thereare exceptions, however; for example, in some inter-floor in-phase transmissions, the observedBERs are in the neighbourhood of 10.Packet Error RateWith the transmitter output fixed at 70 dBmV, the packet error rates of the powerlinemodem for transmission over a large area are determined. The same access points as thoseidentified in Figure 8.12 are chosen for transmission and reception. The results are graphed inFigure 8.16, indicating both the packet error rates and the percentages of lost packets. Over a link116PACKET ERROR RATEFOR LARGE-AREA COMMUNICATIONS100: z:zzzzizzz:zz:z:[— 70 -60w 40- -- - --: :::::::::::::::::::::::::::::::::::::::::::::::::::::•::::10A0 —.i. I IA B C D E F GPOINT OF TRANSMISSION• % OF LOST PACKETS A PACKET ERROR RATEFigure 8.16: Packet error/loss rate for long-distance communications using the powerline modem.with a BER of i0 or less, the packet error rate is typically below 15%. But, if the link’s BERis above iO, the packet error rate may exceeds 90%, which is highly unacceptable. However,forward error correction can substantially reduce this packet error rate [63]. As well, furtherreduction may be obtained by using novel data link protocols [67].1179. CONCLUSIONS AND DISCUSSIONS9.1 ConclusionsThis dissertation documents the research work which involves the design, implementation,analysis, and testing of an all-digital VLSI MSK modem chip with novel synchronizationcapability. On-chip functions include: MSK modulation with a centre carrier frequency to bit rateratio of 5.75; semi-coherent MSK demodulation over a one-bit observation interval; and carrierdetection. Fabricated with 1.2 I.Lm CMOS technology, the chip is capable of MSK signalling at0.19 Mbps maximum.A standard-cell-based design (Chapter 6), the modem chip contains approximately 8500transistors, and has a total of 36 pins, including 5 pairs of power/ground pins and 8 test pins forinternal probing. In addition, to augment testability, a loopback self-test circuit is built into thechip. Design specifications of the chip are given in Chapter 5, and circuit schematics aredescribed in Chapter 6.Modulation is performed with a simple but reliable data-controlled digital square wavesynthesizer without using any on-chip RAM (Chapter 3). A very high level of output phasestability is achieved.The on-chip demodulator is implemented as a discrete-time correlation-receiver, with bitdecision based on a one-bit observation interval. The theoretical performance of this demodulatorin AWGN, as analyzed in Chapter 3, is about 2 dB poorer than that of a continuous-timerealization, which is reviewed in Chapter 2. Also, the demodulator’s susceptibility to imperfectcarrier and bit synchronization is also formulated in Chapter 3.A novel digital phase-locked loop (DPLL) is designed for suppressed carrier recovery.Unlike other Nth-order DPLLs, this DPLL obviates the need of any external zonal filter. Thismerit is largely owing to a proprietary polarity-based phase detection algorithm. Bitsynchronization is carried out with another innovative DPLL which features a maximum-seekingphase detection technique. The phase error performance of these newly developed carrier and bitsynchronizing structures are analyzed using Markov theory in Chapter 4.To demonstrate its operation, the modem chip is applied to facilitate data communications118over intrabuilding powerlines at 19.2 kbps using 105.6 kHz and 115.2 kHz carriers. In additionto the modem chip, the resulting compact MSK powerline modem unit includes a DTE interfacecircuit and a powerline interface circuit The former, which is mixed analog-digital, providesRS232 signal conditioning and coordinates the synchronous serial transfer of data between themodem and host, while the latter, which is au-analog, injects and extracts carriers to and fromthe powerlines.After fabrication, the modem chip is functionally verified by means of a BIST test, anexternal Ioopback self-test, and an inter-chip data transfer test (Chapter 7). The performance,including bit error rate (BER), block error rate, and packet error rate, of the powerline modemunit is also evaluated. Its BER performance in AWGN is found to be about 2 dB poorer thantheoretical prediction. Degradation is caused by hardware limitations, especially imperfect carrierand bit synchronization. When used for data transmission over actual intrabuilding powerlines,the modem achieves a BER in the range of 102 to i0 or less. In general, transmission on in-phase channels is more reliable than on cross-phase channels. For large area communication (i.e.>100 ft), modem performance is fairly independent of channel length.In summary, an versatile all-digital VLSI MSK modem chip with novel synchronizationmeans has been successfully designed and implemented.9.2 DiscussionsIn the following discussion, the technological limit and baud rate selectivity of the all-digital MSK modem architecture are explored, the shortcomings of the design are identified, andsome possible improvements as well as further investigations are suggested.9.2.1 Technological LimitIn theory, the principle of the all-digital MSK modulation-demodulation techniqueintroduced in this thesis can be applied to the implementation of any other FSK-like systems. Inpractice, feasibility depends on whether the required system clock speed (f) in the modem iswithin the limit of the selected digital technology. Clock speed f, is dictated by the centrefrequency (f) and bit rate (R) of the modem, as specified in equation <5.2>. Basically, f. has tobe high enough to resolve the closely spaced mark and space carrier frequencies. For example,119in the case of 19.2 kbps MSK signalling over powerline network using carrier frequencies of105.6 kHz and 115.2 kHz, the digital modem only has to operate at 5.0688 MHz, which is wellbelow the 100 MHz limit of current CMOS technology [50].With the assumption of a center carrier frequency to bit rate ratio a of 5.75 and state-of-the-art CMOS implementation, the real-time digital modem processing technique developed inthis project can be used to implement any MSK system whose centre frequency and bit rate arebelow 2.2 MHz and 0.38 Mbps, respectively. In the limit of a = 1.25, the upper bounds reach10.4 MHz and 8.3 Mbps. Of course, the faster the chosen technology (e.g. ECL, GaAs), thehigher the upper bounds.9.2.2 Baud Rate SelectivityIn the design, the modem’s centre carrier frequency to bit rate ratio a is internally fixedat 5.75. However, especially when channel condition is highly unpredictable, it is desirable tostep down the baud rate in multiples of 2 while keeping!0andJ fixed (i.e. lower the bit rate byincreasing the modulation index). For example, one way to improve the packet error performanceof the powerline modem is by reducing the transmission rate [10]. With the present modemarchitecture, this kind of baud rate selectivity can easily be accommodated. Only threemodifications are needed. First, acid a selectable divide-by-1,2,4,8 circuit to control the transmitclock frequency. Second, provide the same to adjust the receive clock frequency. Third, increasethe bit length of the digital integrate and dump’s and the decision comparators to accommodatethe increase in the number of subbit samples resulting from the rate reduction.Actually, a second version of the MSK modem chip with the above modifications hasbeen fabricated and functionally tested. Its baud rate is controlled via two new input pins. Whendriven at 5.0688 MHz, the chip can transmit at 19.2, 9.6, 4.8, or 2.4 Mbps. Performanceevaluation of this modem chip at those lower baud rates over powerline channels is encouraged.9.2.3 Design Shortcomings and RemediesWhile the modem chip presented here has the merits of simplicity, reliability, and lowspace and power requirement, it has a few shortcomings. These are identified below in order ofincreasing importance.120Modem performance depends very much on the accuracy and precision of the systemclock. Currently, crystal oscillators of very high quality (+1- 0.01% accuracy) are readilyavailable. Consequently, this shortcoming is not a real threat.2. The duty cycle of the digitized MSK signal at the receiver must be maintained to be asclose to 50/50 as possible. Otherwise, significant BER performance degradation will beincurred as a result of two ramifications. First, by design, the locally generated carrierwaveform always has a 50/50 duty cycle. When the duty cycle of the digitized input isnot symmetrical, perfect correlation between the input and local carrier will not bepossible, and this will give rise to systematic error the effect of which is similar to thatof carrier phase error. Second, the zero-crossing-based phase detection algorithmemployed for suppressed carrier recovery is sensitive to the duty cycle of the digitizedinput. Any duty cycle distortion will increase the probability of phase detection error, thusreducing carrier synchronization accuracy.3. Due to the relatively slow acquisition behaviour of the newly designed bit synchronizer,a relatively long preamble is needed for modem synchronization purpose. For example,a preamble of at least 256 bits long is recommended for the MSK modem chip. Theobvious remedy is to speed up the lock acquisition time of the bit synchronizer. Thisspeed increase can be achieved in two ways: a) by increasing the phase update frequency,b) by increasing the step size of phase correction. However, both of these modificationswill worsen the steady-state performance of the synchronizer. In light of this trade-off,a better strategy is to enhance the synchronizer’s controllability such that two modes ofoperation are available: in the acquisition mode, a higher clock update frequency and/orlarger phase correction step size are selected; in the tracking mode, these parameters arereduced to ensure a reasonably small steady-state, bit timing error.9.2.4 Other Improvements and Further InvestigationsThe modem chip designed in this thesis performs modulation, demodulation, and carrierdetection. An increased level of system integration can be attained by adding to the chip someother digitally implemented functions involved in the physical layer of a data communicationsystem. These functions include: a) RS232 handshaking, b) preamble generation/removal, c) data121scrambling/descrambling, d) FEC coding/decoding, and e) bit interleaving/deinterleaving.From a theoretical standpoint, it is interesting to systematically study the effects of signalquantization and sampling frequency on the BER performance of the all-digital demodulator.Along with imperfect carrier and bit synchronization, these are the major sources of errorsleading to significant performance degradation.The carrier synchronizer and bit synchronizer on the modem chip are designed in asomewhat ad-hoc manner. Their performance depends on a few factors, including phase updatefrequency, phase correction step size, and loop filtering algorithm. A further detailed investigationof the effects of these factors on synchronizer performance is highly recommended.Finally, attempt should be made to apply and test the MSK modem chip in othertransmission environments.122REFERENCES[1] E. Caldwell, “Economics and Requirements of Remote Meter Reading and Load ControlSystems,” Proc. 3rd mt. Conf Metering, App., Tariffs for Elec. Supply, London England,Nov. 15-17, 1977, PP. 147-149.[2] M. G. Morgan & S. N. Talukdar, “Electric Power Load Management: Some Technical,Economic, Regulatory, and Social Issues,” Proc. IEEE, vol 67, pp. 241-312 Feb. 1979.[3] 3. B. O’Neal, Jr., “The Residential Power Circuit as a Communication Medium,” IEEETrans. Consumer Electronics, vol. CE-32, pp. 567-577, Aug. 1986.[4] BSR X-1O Owner’s Manual, BSR (Canada) Ltd., Canada, 1981.[5] PowerLANTM,ExpertNets, Acton, MA, U.S.A., 1981.[6] Non-Wire Multidrop Network Users Guide, CYPLEX Division, Controlonics Corporation,MA, U.S.A., 1981.[7] B. Hirosaki, S. Hasegawa, & K. Endo, “A Power Line Home Bus System Using Spread-Spectrum Communication Technologies,” 1985 International Conference on ConsumerElectronics, 1985.[8] P. K. van der Gracht & R. W. Donaldson, “Communications Using Pseudonoise ModulationElectric Power Distribution Circuits,” IEEE Trans. Comm., vol. COM-33, pp. 964-974, Sept.1985.[9] F. K. K. Chiu, Data Communications Using Coherent Minimum Frequency Shift Keying onIntrabuilding Polyphase Power Line Networks, M.A.Sc. Thesis, Dept. of Electrical Eng.,University of British Columbia, Canada, Dec. 1985.[10] Barry Buternowsky, Design, Implementation and Testing of a Flexible, Intelligent ModemArchitecture for Power Line Communications, M.A.Sc. Thesis, Dept. of Electrical Eng.,University of British Columbia, Canada, Jan. 1992.[11] R. Broadbridge, Nectar Electronics International Ltd., UK, “Power Line Modems andNetworks,” lEE Telecommunication Transmission, conference publication #246, pp. 294-296,1985.[12] 3.0. Onunga & R. W. Donaldson, “Performance of CSMA with Priority Acknowledgements123(CSMAIPA) on Noisy Data Networks with Finite User Population,” IEEE Trans. Comm.,vol. COM-39, pp. 1088-1096, July 1991.[13] 3. 0. Onunga, “Personal Computer Communications on Intrabuilding Power Line LAN’sUsing CSMA with Priority Acknowledgments,” IEEE J.S.A.C., vol. 7, pp. 180-191, Feb.1989.[14] H. Taub & D. Schilling, Principles of Communication Systems, 2nd ed., McGraw-Hill BookCompany, New York, 1986.[15] S. A. Gronemeyer, A. L. McBrid, “MSK & Offset QPSK Modulation,” IEEE Trans.Comm., vol. COM-24, pp. 809-820, Aug. 1976.[16] W. P. Osborne & M. B. Luntz, “Coherent and Noncoherent Detection of CPFSK,” IEEETrans. Comm., vol. COM-22, pp. 1023-1029, Aug. 1974.[17] M. G. Pelchat, R. C. Davis, & M. B. Luntz, “Coherent Demodulation of Continuous PhaseBinary FSK Signals,” Proc. International Telemetering Conf, pp. 18 1-190, Washington,D.C., 1971.[18] B. Sklar, Digital Communications, Prentice Hall, New Jersey, 1988.[19] 5. Stein & J. J. Jones, Modern Communication Principles, McGraw-Hill, New York, 1967.[20] 3. M. Wozencraft & I. M. Jacobs, Principles of Communication Engineering, John Wiley& Sons, U.S.A., 1965.[21] W. C. Lindsey & M. K. Simon, Telecommunication Systems Engineering, Prentice-Hall,New Jersey, 1973.[22] K. Feher, Digital Communications, Satellite/Earth Station Engineering, Prentice-Hall,Englewood Cliff, New Jersey, 1983.[23] P. Galko & S. Pasupathy, “Linear Receivers for Correlatively Coded MSK,” IEEE Trans.Comm., vol. COM-33, pp. 338-347, Apr. 1985.[24] V. Manassewitsch, Frequency Synthesizers: Theory and Design, Wiley, New York, 1987.[25] P. Horowitz & W. Hill, The Art of Electronics, Cambridge University Press, New York,1987.[26] P. Tratton, “Correlation Properties of MSK Sequences,” Proc. National TelecommunicationsConference, pp. 554-559, San Diego, California, 1974.124[27] N. C. Beaulieu & C. Leung, “On the Performance of Three Suboptimum Detection Schemefor Binary Signalling,” IEEE Trans. Comm., vol. COM-33, pp. 241-245, Mar. 1985.[28] C. M. Chie, “Performance Analysis of Digital Integrate and Dump Filters,” IEEE Trans.Comm., vol. COM-30, pp. 1979-1983, Aug. 1982.[29] J. A. C. Bingham, The Theory and Practice of Modem Design, Wiley, New York, 1988.[30] P. H. Bardell, W. H. McAnney, & 3. Savir, Built-In Test for VLSI: PseudorandomTechniques, Wiley, New York, 1987.[31] L. E. Franks, “Carrier & Bit Synchronization in Data Communication - A Tutorial Review,”IEEE Trans. Comm., vol. COM-28, pp. 1107-1121, Aug. 1980.[32] F. M. Gardner, Phaselock Techniques, John Wiley & Sons, New York, 1979.[33] D. H. Wolaver, Phase-Locked Loop Circuit Design, Prentice-Hall, New Jersey, 1991.[34] R. B. Best, Phase-Locked Loops - Theory, Design, and Applications, McGraw-Hill, NewYork, 1984.[35] W. C. Lindsey & C. M. Chie, “A Survey of Digital Phase-Locked Loops,” IEEE Proc., vol.69, pp. 410-431, Apr. 1981.[36] W. C. Lindsey & H. C. Osborne, “Models of Digital Phase-Locked Loops for SuppressedCarrier Tracking,” NTC Conference Records, pp. 24.3.1-24.3.6, Nov. 1979.[37] H. Yamamoto & S. Mori, “Performance of A Binary Quantized All Digital Phase-LockedLoop with a New Class of Sequential Filter,” IEEE Trans. Comm., vol. COM-26, pp. 35-45,Jan. 1978.[38] J. K. Holmes, “Performance of a First-Order Transition Sampling Digital Phase-LockedLoop Using Random-Walk Models,” IEEE Trans. Comm., vol. COM-20, pp. 119-131, Apr.1972.[39] 3. R. Cessna & D. M. Levy, “Phase Noise & Transient Times for a Binary Quantized DigitalPhase-Locked Loop in White Gaussian Noise,” IEEE Trans. Comm., vol. COM-20, pp. 94-104, Apr. 1972.[40] 3. K. Holmes & C. R. Tegnelia, “A Second-Order All-Digital Phase-Locked Loop,” IEEETrans. Comm., vol. COM-22, pp. 62-68, Jan. 1974.[41] 3. P. Sandoz & W. Steenaart, “Performance Improvement of a Binary Quantized All-DigitalPhase-Locked Loop with a New Aided-Acquisition Technique,” IEEE Trans. Comm., vol.125COM-32, pp. 1269-1276, Dec. 1984.[42] W. Feller, An Introduction to Probability Theory and Its Applications, vol. 1, Wiley, NewYork, 1957.[43] B. R. Bannister & G. G. Whitehead, Fundamentals ofModern Digital Systems, MacMillan,London, 1983.[44] P. Naish, Designing ASICs, Chichester, England, Ellis Horwood, 1988.[45] Motorola Corporation, High-Speed CMOS Logic Data, 1988, U.S.A.[46] R. L. Geiger, P. E. ALilen, & N. R. Strader, VLSI Design Techniques for Analog andDigital Circuits, McGraw-Hill, New York, 1990.[47] Cadence Design Systems, Inc., U.S.A., 1989.[48] Simucad, Inc., Union City, California, U.S.A., 1989.[49] C. Hall, Guide to the Integrated Circuit Implementation Services of the CanadianMicroelectronics Corporation, Canadian Microelectronics Corporation, Kingston, Ontario,Canada, 1989.[50] T. M. Frederiksen, Intuitive CMOS Electronics, Revised ed., McGraw-Hill, New York, 1989.[51] F. C. Wang, Digital Circuit Testing, Academic Press, New York, 1991.[52] C. Hall, The CMOS4S Standard Cell Library, Canadian Microelectronics Corporation,Kingston, Ontario, Canada, Mar. 1990.[53] 3. R. Nicholson & J. A. Malack, “R.F. Impedance of Power Lines and Line ImpedanceStabilization Networks in Conducted Interference Measurements,” IEEE Trans. Electromag.Compat., vol. EMC-15, pp.84-86, May 1973.[54] R. M. Vines, H. 3. Trussel, K. C. Shuey, & 3. B. O’Neal, Jr., “Impedance of the ResidentialPower-Distribution Circuit,” IEEE Trans. Electromag. Compat., vol. EMC-27, pp. 6-12, Feb.1985.[55] M. H. L. Chan & R. W. Donaldson, “Attenuation of Communication Signals on Residentialand Commercial Intrabuilding Power-Distribution Circuits,” IEEE Trans. Electromag.Compat., vol. EMC-28, pp. 220-230, Nov. 1986.[56] A. A. Smith, “Power Line Noise Survey,” IEEE Trans. Electromag. Compat., vol. EMC-14,pp. 3 1-32, Feb. 1972.126[57] R. M. Vines, H. J. Trussel, L. J. Gales, & J. B. O’Neal, Jr., “Noise on Residential PowerDistribution Circuits,” IEEE Trans. Electromag. Compat., vol. EMC-26, pp. 161-168, Nov.1984.[58] H. J. Trussel & J. D. Wang, “The Effect of Hard Limiters on Signal Detection in HarmonicNoise Using Adaptive Noise Cancellation,” IEEE Trans. Pwr. Del., vol. PWRD-1, pp. 73-78,Jan. 1986.[59] M. H. L. Chan & R. W. Donaldson, “Amplitude, Width, and Interarrival Distributions forNoise Impulses on Intrabuilding Power Line Communication Networks,” IEEE Trans.Electromag. Compat., vol. EMC-31, pp. 320-323, Aug. 1989.[60] A. Clements, Microprocessor Systems Design, PWS-Kent, Boston, 1987.[61] R. Jeffery, “Hardware Documentation for 9600 BPS Intra-Building Power Line Modem,”internal communications, Dept. of Electrical Eng., University of British Columbia, Canada,Jan. 1990.[62] R. D. Gitlin & J. F. Hayes, “Timing Recovery and Scramblers in Data Transmission,” BellSystem Technical Journal, vol. 54, pp. 569-593, Mar. 1975.[63] M. H. L. Chan, Channel Characterization and Forward Error Correction Coding for DataCommunications on Intrabuilding Electric Power lines, Ph.D. dissertation, Dept. of ElectricalEng., University of British Columbia, Canada, Apr. 1989.[64] Sorep Technology Corp., Houston, Texas, U.S.A., 1991.[65] Qualcomm, Inc., San Diego, California, U.S.A., 1991.[66] Stanford Telecommunications, Inc., Santa Clara, California, U.S.A., 1991.[67] J. 0. Onunga & R. W. Donaldson, “A Simple Packet Retransmission Strategy forThroughput and Delay Enhancement on Power Line Communication Channels,” to bepublished in IEEE Trans. Power Delivery.127APPENDIX: SCHEMATICS OF MODEM CHIPSheet 1: Top-level chip architecture.Sheet 2: Modem control logic.Sheet 3: Timing generator.Sheet 4: MSK modulator.Sheet 5: MSK demodulator.Sheet 6: Carrier synchronizer -- space frequency.Sheet 7: Zero-crossing phase detector.Sheet 8: 8-bit resettable register.Sheet 9: 8-bit full adder.Sheet 10: Averaging loop filter.Sheet 11: Numerically controlled oscillator -- space frequency.Sheet 12: Divide-by-48 clock divider.Sheet 13: Carrier synchronizer -- mark frequency.Sheet 14: Numerically controlled oscillator -- mark frequencySheet 15: Bit synchronizer.Sheet 16: Early/late phase detector.Sheet 17: Absolute value converter.Sheet 18: Majority loop filter.Sheet 19: Numerically controlled oscillator -- bit clock.Sheet 20: Divide-by-12 clock divider.Sheet 21: Carrier detector.Sheet 22: BIST controller.128-cU)6TcntMODE 1or213IN>OUTMODEØ—0mvC1501N0OUT0TESTnor2mv1601Nh)OOUTOmvp.S2TIMINC_CENERATORThis_generates_the...clocks_and_timing...strobes_required_forthe_internal_operation_of_the_modem.p.S3148I-’MODULATORMinimumShiftKeying(MSK)modulation;squarewaveoutput;space:clockfrequency/48;mark:clockfrequency/44bitrate=clockfrequency/2644’p.S4-w-wDEMODULATORp.S5Thisisa1—bitcoherentFSKdemodulator.4’p.S6CARRIER—SYNCVer.ØspocefrequencysuppressedcarriersynchronizercEl-DCl)C-)>ri-i-o>Cl)El0El—HEl0-H0ACCUMULATOR—RECISTORod2I:1)L...ID4 IZ-.--—ri-.-—D2_4’p.S8128BHITPULLADDERD1<ø:7>0Mø:3>add4D2<0:3>S<ø:3>008<03>tjndCo—e-—c)O<ø:7>0A<I:3> odd4 S<ø:3>0o8<0:3>pcico—Bp.S900DPLL_LOOP_FILTER4’p.S1ØD44IDQtjDIGITAL_VOLTAGECONTROLLEDOSCILLATORC114115.Noor..:_______‘my‘mnv116117—._________9nv‘1gwDIVIDE—BY—484’p.S12CARRIER—SYNCVer.14%p.S13115.2kHzsuppressedcarriersynchronizerI,t%)DIGITAL_VOLTAGE_CONTROLLED_OSCILLATOR p.S4LU0H—z>-Ib-i>0C—)LU0Iz-ii0>-(-I-)LI)U)a-ci,N0U>-(I)-4-,N-Ca)143SYMBOL_PHASE_DETECTOR_VINTAGEp.S16p7HITCOMPAHATOHDI<16A<3>AGBO0°cmp4AE00gndl0AC0ALAOHvddl0AEBIflA.%.-.-ACJ>fl14,vdH!-—R-- p pcmp4AEBCAEALBCp.S17LOOPPROCESSORp.S1811$III__________________________(flykwI2121_________________________I_(flykwL1’TzCmC) >1<C)0z0P10Cl)C-)>0<z>C) P1-cI) —i.CDp00114115I..klUT1hhkwkwDIVI.DE—IY—12p.S20Ill1161$I,IIN,0UUT.,.4,myLiny‘CCARRIER_DETECT115116w_______MonitorRXinputforcarrierpresence.ocimxCDC,CCD0CCDCDCornU)-c.(I)N)

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