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An HVDC equidistant converter control model Struyk, Emile 1976

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AN HVDC EQUIDISTANT CONVERTER CONTROL MODEL . by EMILE STRUYK B.A.Sc, Waterloo U n i v e r s i t y , 1970 A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE i n the Department of E l e c t r i c a l Engineering We accept t h i s t h e s i s as conforming to the re q u i r e d standard THE UNIVERSITY OF BRITISH COLUMBIA September, 1976 ©Emile Struyk 1976 In p r e s e n t i n g t h i s t h e s i s i n p a r t i a l f u l f i l m e n t o f t h e r e q u i r e m e n t s f o r an a d v a n c e d d e g r e e a t t h e U n i v e r s i t y o f B r i t i s h C o l u m b i a , I a g r e e t h a t t h e L i b r a r y s h a l l make i t f r e e l y a v a i l a b l e f o r r e f e r e n c e and s t u d y . I f u r t h e r a g r e e t h a t p e r m i s s i o n f o r e x t e n s i v e c o p y i n g o f t h i s t h e s i s f o r s c h o l a r l y p u r p o s e s may be g r a n t e d by t h e H e a d o f my D e p a r t m e n t o r by h i s r e p r e s e n t a t i v e s . I t i s u n d e r s t o o d t h a t c o p y i n g o r p u b l i c a t i o n o f t h i s t h e s i s f o r f i n a n c i a l g a i n s h a l l n o t be a l l o w e d w i t h o u t my w r i t t e n p e r m i s s i o n . D e p a r t m e n t o f £ L E C T f f ) C A L EM6IME~£ff/A/r<, The U n i v e r s i t y o f B r i t i s h C o l u m b i a 2075 Wesbrook P l a c e Vancouver, Canada V6T 1W5 D a t e 2 7 $ trPTErM&E-tf J f 7/, ABSTRACT This t h e s i s presents the design and c o n s t r u c t i o n d e t a i l s of a p h y s i c a l model of a s i x - p u l s e HVDC converter s u i t a b l e f o r s t e a d y - s t a t e s t u d i e s . The converter rack has been b u i l t to f a c i l i t a t e simple t e s t i n g and breadboarding. A d i g i t a l e q u i d i s t a n t f i r i n g angle c o n t r o l l e r has been constructed f o r the c o n v e r t e r - r e c t i f i e r c u r r e n t c o n t r o l . An e l e c t r o n i c phase-locked loop has been used to generate an accurate c o n t r o l frequency. M o d i f i c a t i o n s have been suggested to make the r e c t i f i e r , f u l l y o p e r a t i o n a l . The c o n t r o l system has been constructed f o r f u t u r e i n v e r t e r c o n t r o l c i r -c u i t s and p o s s i b l e computer c o n t r o l . i TABLE OF CONTENTS Page ABSTRACT i TABLE OF CONTENTS i i LIST OF TABLES i v LIST OF FIGURES v. ACKNOWLEDGEMENTS v i i NOMENCLATURE v i i i 1. INTRODUCTION 1 2. BASIS FOR DESIGN OF AN HVDC CONVERTER CONTROL . . . 11 2.1 BASIC PRINCIPLE 11 2.2 RECTIFIER CONSTANT CURRENT CONTROL - THEORY 12 2.3 INVERTER CONTROL - THEORY 14 Minimum E x t i n c t i o n Angle C o n t r o l (MEA) 14 One Way Current C o n t r o l (OWCC) 16 3. CONSTRUCTION OF HVDC CONVERTER CONTROL MODEL 18 3.1 CONVERTER RACK 18 3.2 CONVERTER CONTROL 20 Generation of the C o n t r o l Frequency, f c 22 M o n i t o r i n g of Analog Q u a n t i t i e s 23 Generation of the Valve F i r i n g P u l s e . . . . . . . . . . . 24 4. DESIGN AND EXPERIMENTAL RESULTS OF THE PHASE-LOCKED LOOP AND CONTROL FREQUENCY GENERATION . . . . . . . . 26 4.1 PHASE-LOCKED LOOP INPUT CONDITIONING BOARD (PIC) . . . . . 26 4.2 ASTABLE FREQUENCY GENERATOR AND REFERENCE FREQUENCY SELECTOR 28 4.3 PHASE-LOCKED LOOP (PLL) . . . . . . . . . 31 Theory and Design Procedure . . . . . . . 32 PLL C i r c u i t D e t a i l s 3 5 Test R e s u l t s 3 8 i i 4.4 START/STOP CIRCUIT . 5. DESIGN AND EXPERIMENTAL RESULTS OF CIRCUITS TO MONITOR ANALOG QUANTITIES . 5.1 DIRECT CURRENT SENSOR (DCS) AND ERROR AMPLIFIER Theory and C i r c u i t D e t a i l s . . . . Res u l t s . 5.2 COMMUTATING VOLTAGE CROSSOVER DETECTOR (CVCD) . 5.3 ANALOG-TO-DIGITAL CONVERTER (ADC) . . . . . . . 6. DESIGN AND EXPERIMENTAL RESULTS FOR TEE EQUIDISTANT FIRING CIRCUIT 6.1 CONTROL MODE LOGIC (CML) • 6.2 FIRING PULSE GENERATOR (FPG) Main C i r c u i t . Decoder Minimum F i r i n g Angle L o g i c 6.3 SCR VALVE GATE DRIVES 7. CONCLUSIONS AND RECOMMENDATIONS BIBLIOGRAPHY APPENDICES A Function Diagrams fc.-r Integrated C i r c u i t s . . . . B Converter C o n t r o l Timing Diagram i i i LIST OF TABLES 6.1 ROUTING OF CONTROL ERROR 6.2 DATA CHANNEL SELECTOR CODING FOR ROUTING OF CONTROL ERROR iv LIST OF FIGURES 1.1 BASIC HVDC TRANSMISSION SYSTEM ,1.2 RECTIFICATION - WAVEFORMS 1.3 INVERSION - WAVEFORMS 1.4 CONVERTER V-I CHARACTERISTICS 1.5 HVDC SYSTEM CONTROL CHARACTERISTICS 1.6 EQUIDISTANT CONTROLLERS - BLOCK DIAGRAMS (a) Voltage C o n t r o l l e d O s c i l l a t o r E q u i d i s t a n t C o n t r o l l e r (b) Phase-Locked Loop E q u i d i s t a n t C o n t r o l l e r 2.1 OWCC - MEA TRANSFER CHARACTERISTIC 3.1 CONVERTER SCHEMATIC 3.2 BLOCK DIAGRAM - EQUIDISTANT FIRING CONTROL FOR HVDC CONVERTER MODEL 4.1 PHASE-LOCKED LOOP INPUT CONDITIONING SCHEMATIC 4.2 ASTABLE FREQUENCY GENERATOR SCHEMATIC 4.3 CALIBRATION CURVE FOR ASTABLE FREQUENCY GENERATOR 4.4 "AC ON" DETECTOR SCHEMATIC 4.5 REFERENCE FREQUENCY SELECTOR 4.6 BLOCK DIAGRAM OF PHASE-LOCKED LOOP 4.7 CALIBRATION CURVE FOR PLL VCM ' 4.8 PHASE-LOCKED LOOP SCHEMATIC 4.9 PLL INPUT WAVEFORMS 4.10 CIRCUIT FOR PLL STEP FREQUENCY TESTS 4.11 START/STOP CIRCUIT - BLOCK DIAGRAM 4.12 START/STOP CIRCUIT - SCHEMATIC 5.1 MONITORING ANALOG QUANTITIES - BLOCK DIAGRAM 5.2 DIRECT CURRENT SENSOR - BLOCK DIAGRAM DIRECT CURRENT SENSOR & ERROR AMPLIFIER - SCHEMATIC DIRECT CURRENT SENSOR - TRANSFER CHARACTERISTIC DIRECT CURRENT SENSOR - FREQUENCY RESPONSE COMMUTATING VOLTAGE CROSSOVER DETECTOR BLOCK DIAGRAM COMMUTATING VOLTAGE CROSSOVER DETECTOR TYPICAL SCHEMATIC COMMUTATING VOLTAGE CROSSOVER DETECTOR WAVEFORMS ANALOG TO DIGITAL CONVERTER - TIMING DIAGRAM GENERATION OF VALVE FIRING PULSES - BLOCK DIAGRAM CONTROL MODE LOGIC - SCHEMATIC CONTROL ERROR ROUTING - BLOCK DIAGRAM FIRING PULSE GENERATOR - BLOCK DIAGRAM TYPICAL SCR GATE DRIVE CIRCUIT v i ACKNOWLEDGEMENTS I wish to express my g r a t i t u d e t o my s u p e r v i s o r , Dr. M.D. Wvong. f o r h i s advice i n the p r e p a r a t i o n of t h i s t h e s i s . My thanks a l s o to Dr. H.W. Dommel f o r h i s encouragement and reading of the t h e s i s . 1 am p a r t i c u l a r l y g r a t e f u l to Tony Leugner and Gord McConnell f o r t h e i r time and advice on v a r i o u s c i r c u i t s . I am a l s o g r a t e f u l to A l MacKenzie f o r h i s encouragement and help i n p r e p a r i n g the t h e s i s . The f i n a n c i a l a s s i s t a n c e of Dr. Y.N. Yu's N a t i o n a l Research C o u n c i l Grant No. 67-3626 and the Teaching A s s i s t a n t s h i p s f o r 1970-72 i n the Department of E l e c t r i c a l Engineering are t h a n k f u l l y acknowledged. v i i NOMENCLATURE SYMBOLS C, C,, C„, C ., C „ v a r i o u s c a p a c i t o r s ' 1 2 x l x2 vol t a g e - z e r o c r o s s i n g i n s t a n t across v a l v e i E AC system l i n e - l i n e v o l t a g e , rms e current e r r o r i n analog form ( e Q = K C I ^ - I ^ ) ) f AC System Frequency (60 Hz nominal) f c o n t r o l frequency " c f ^ v a l v e f i r i n g i n s t a n t * f PLL output frequency o f PLL reference frequency r f 2.f (Output of PLL input c o n d i t i o n i n g Bd37) Hz r l * f 2 120 Hz (Output,of A s t a b l e Frequency Generator) f PLL feedback frequency v i , d i r e c t c u r r e n t , instantaneous v a l u e d I, d i r e c t c u r r e n t , mean value d I,, i n v e r t e r current order d i I * c u r r e n t margin dm I d e s i r e d reference d i r e c t c u r r e n t s e t t i n g i n ^° amperes I , r a t e d d i r e c t c u r r e n t of converter dr K, K^, constant L transformer commutating inductance P, d i r e c t c u r r e n t power d R, R-, R_, R ., R 0 v a r i o u s r e s i s t o r s ' 1 2 x l x2 tr a n s m i s s i o n l i n e r e s i s t a n c e , ohms V, d i r e c t v o l t a g e , mean value d V,. i n v e r t e r d i r e c t v o l t a g e , mean value d i v i i l V dr X r e c t i f i e r d i r e c t v o l t a g e , mean value v a l v e i transformer commutating reactance i n per u n i t mxn m i n y + i Pi T e e i ABBREVIATIONS ADC C CO, C l , C2, C3 CC CEA CML CVCD f i r i n g angle delay (° a f t e r C.^ ) * minimum allowable, f i r i n g angle f o r a v a l v e * i n v e r t e r f i r i n g angle * e x t i n c t i o n angle * minimum Y per c y c l e * overlap or commutation angle * angular frequency ( r a d i a n s / c y c l e ) c o n t r o l parameter (Lj or y) * end of v a l v e conduction i n s t a n t f o r v a l v e i f i r i n g i n s t a n t f o r v a l v e i time constant f i r i n g angle e r r o r i n 2's complement b i n a r y * f i r i n g angle e r r o r f o r v a l v e i * * A l l angles i n e l e c t r i c a l degrees. Only reference values assume a 60 Hz frequency unless otherwise noted. Analog to D i g i t a l Converter Comparator Data Channels Current C o n t r o l Constant E x t i n c t i o n Angle C o n t r o l Mode Lo g i c Commutating Voltage Crossover Detectors ix D DCS FPG HVDC IOC ISC LED LTC MEA OWCC PAC PACC PCB PIC PLL PRR PRRC SCR VCM VCO SUBSCRIPTS A, B, C d i j 1, 2, 3, 4, 5, 6 Down Counter D i r e c t Current Sensor F i r i n g P u l s e Generator High Voltage D i r e c t Current I n v e r t e r Optimum C o n t r o l I n v e r t e r Safety C o n t r o l L i g h t E m i t t i n g Diode Load Tap Changer Minimum E x t i n c t i o n Angle C o n t r o l One Way Current C o n t r o l Phase Advance R e g i s t e r Phase Advance Counter Computer Enable P r i n t e d C i r c u i t Board Phase-Locked Loop Input C o n d i t i o n i n g Board Phase-Locked Loop Phase Reduction R e g i s t e r Phase Reduction R e g i s t e r Computer Enable S i l i c o n C o n t r o l l e d R e c t i f i e r Voltage C o n t r o l l e d M u l t i v i b r a t o r Voltage C o n t r o l l e d O s c i l l a t o r AC phases d i r e c t c u r r e n t or v o l t a g e s u b s c r i p t denoting a p a r t i c u l a r v a l v e s u b s c r i p t denoting a p a r t i c u l a r c y c l e v a l v e number x NOMENCLATURE Lo g i c Symbols ( d e f i n i t i o n f o r l o g i c "1") AC ON AC system v o l t a g e i s gr e a t e r than t h r e s h o l d value ADC ADC conversion i s complete (1.5 us pulse) C comparator C output (D >_ CPRR) CC r e c t i f i e r c u r r e n t c o n t r o l i s on CC1 ADC e r r o r i s negative CP computer c o n t r o l i s on CPAC contents of the PAC = (a b i n a r y number) CPRR contents of the PRR = (a b i n a r y number) D number i n down counter D = (a b i n a r y number) G l , G2 AND gates IOC t r a n s f e r 0 from IOC r e g i s t e r to PAC (pulse) ISC t r a n s f e r 0 from ISC r e g i s t e r to PRR (pulse) OWCC i n v e r t e r one-way c u r r e n t c o n t r o l i s on PAC e r r o r goes to PAC counter PACC computer c o n t r o l e r r o r goes to PAC (pulse) PRR e r r o r goes to PRR r e g i s t e r PRRC computer c o n t r o l e r r o r goes to PRR (pulse) f i r i n g pulse output from decoder R.j p u l s e to f i r i n g p ulse monostable x i 1. INTRODUCTION High Voltage Direct Current (HVDC) transmission has become com-mercially useful since 1954 when a 20 MW submarine cable system was com-missioned for Gotland Island i n Sweden [1], [2]. Since then HVDC has found applications i n long distance bulk power transmission, underground cable power transmission, submarine cable transmission, frequency changing, asynchronous interconnection, p a r a l l e l AC/DC transmission and transmission of power without increasing the f a u l t l e v e l at the receiving end. AC systems are s t i l l used for generation, d i s t r i b u t i o n and sub-transmission because of economics and f l e x i b i l i t y but i n the area of trans-mission HVDC does offer an alternat i v e . In order for an HVDC system to be an economical a l t e r n a t i v e to an AC system, the additional expense of the converter terminal equipment must be offset by lower transmission l i n e or cable costs. The break-even d i s -tances are about 25 - 50 km f o r submarine cable and 500 - 1500 km for over-head l i n e [1]. Frequently technical requirements favour HVDC or even eliminate AC. To date a l l HVDC systems have been e s s e n t i a l l y two terminal schemes. However, with advanced control systems, or development of an HVDC breaker, multi-terminal DC systems w i l l become a r e a l i t y . HVDC sys-tems may also be used f o r s t a b i l i z a t i o n of AC systems or p a r a l l e l AC/DC t i e s . The rapid control of the HVDC power flow has seldom been used to i t s f u l l p o t e n tial but with increasing confidence i n e x i s t i n g control systems, i t s use w i l l be extended. The basic HVDC system i s shown i n F i g . 1.1. AC SYSTEM NO. ; AC HARMONIC FIL TERS LINE UN£ LINE REACTOR IMPEDANCE REACTOR l CONVERTER •3 c — E TAP-CHANGING TRANSFORMER CONTROL CONVERTER CAPACITOR BANK AC HARMONIC FIL TERS 1 TAP-CHANGING TRANSFORMER 6 AC SYSTEM NO. 2 SYNCHRONOUS CONDENSER FIGURE 1.1 BASIC HVDC TRANSMISSION SYSTEM On-load tap-changing transformers r e g u l a t e the AC v o l t a g e to the converters and allow d i f f e r e n t phase connections to minimize AC harmonic c u r r e n t s . The converters are 3-phase s t a t i c switches that a l l o w conversion of AC to DC, and v i c e - v e r s a . The l i n e r e a c t o r s smooth the converter DC vol t a g e . The l i n e impedance depends on the le n g t h and type of t r a n s m i s s i o n l i n e or cable. AC harmonic f i l t e r banks prevent AC harmonic c u r r e n t s from e n t e r i n g the AC systems. Synchronous condensers or c a p a c i t o r banks are normally r e q u i r e d to provide l a g g i n g r e a c t i v e power to both converters to enable the commutation of current from one v a l v e to another i n the conver-t e r . The HVDC system may be an asynchronous l i n k between two AC systems or may operate i n p a r a l l e l w i t h an AC t i e . A model of an HVDC system allows experimentation and development of equipment, operating techniques, and c o n t r o l systems. Many t e s t s can not be done on an a c t u a l system because of op e r a t i n g demands or f i x e d par-ameters. There i s a l s o the r i s k of damaging expensive equipment due to unknown or d e s t r u c t i v e tendencies of c e r t a i n t e s t s . A mathematical model can p r e d i c t behaviour and performance and al l o w s refinement of the model. A p h y s i c a l model d u p l i c a t i n g time c o n s t a n t s , per u n i t q u a n t i t i e s and 3. behaviour of a r e a l system provides v a l u a b l e p r a c t i c a l experience and can v e r i f y a mathematical model. This t h e s i s d e s c r i b e s the design and c o n s t r u c t i o n of a p h y s i c a l model of an HVDC converter and i t s c o n t r o l system. The model was s c a l e d to be compatible w i t h the e x i s t i n g micro-machine model of an AC system. The b a s i c converter connection f o r HVDC a p p l i c a t i o n s has been the 6-pulse 3-phase Graetz b r i d g e shown i n F i g . 1.2, however, the 12 pul s e con-n e c t i o n i s becoming pr e v a l e n t i n t h y r i s t o r i n s t a l l a t i o n s . For mercury-arc v a l v e converters a seventh v a l v e - the bypass v a l v e - i s r e q u i r e d f o r s t a r t i n g , stopping and commutation f a i l u r e recovery from arc-backs. The t h y r i s t o r v a l v e converter does not s u f f e r arc-backs so a bypass v a l v e i s unnecessary. A mercury-arc v a l v e c o n s i s t s of a common mercury p o o l cathode and m u l t i p l e anodes separated by a c o n t r o l g r i d . The v a l v e i s a s i n g l e u n i t . A t h y r i s t o r v a l v e u s u a l l y c o n s i s t s of s e v e r a l s e r i e s connected mod-ul e s each c o n t a i n i n g a number of S i l i c o n C o n t r o l l e d R e c t i f i e r s (SCRs) con-nected i n s e r i e s or s e r i e s - p a r a l l e l . The modules can be i n d i v i d u a l l y removed from a permanent v a l v e s t r u c t u r e f o r maintenance. T h y r i s t o r v a l v e s have become popular because of the absence of arc-backs and the bypass v a l v e , e a s i e r maintenance, and higher r e l i a b i l i t y . A t h i r d type of v a l v e c a l l e d the L i q u i d Metal Plasma Valve has been b u i l t and i s being t e s t e d at the time of t h i s w r i t i n g [ 3 ] . This v a l v e has an anode and cathode i n a vacuum chamber. Conduction s t a r t s by shooting a s m a l l amount of mercury plasma from the cathode to the anode. This v a l v e has p o t e n t i a l b e n e f i t s i n s m a l l e r s i z e , lower l o s s e s , increased r e l i a b i l i t y and e a s i e r maintenance. A l l types of converters a l l o w the cur r e n t s to flow i n o n l y one d i r e c t i o n , consequently the power flow i s changed by r e v e r s i n g the p o l a r i t y of the v o l t a g e across the converters. A 6-pulse SCR converter has been b u i l t f o r t h i s t h e s i s . k 37$ • sk id . T Y V \ _ POWER FLOW" f 4 4 (a) RECTIFIER BRIDGE C (b) DIRECT VOLTAGE REFERRED TO AC SYSTEM NEUTRAL -;2o°-H I 4 (c) TRANSFORMER PHASE "A" CURRENT FIGURE 1.2 RECTIFICATION - WAVEFORMS POWER FLOW (a) INVERTER BRIDGE (b) DIRECT VOLTAGE REFERRED TO AC SYSTEM NEUTRAL \ (c) TRANSFORMER PHASE "A" CURRENT FIGURE 1.3 INVERSION - WAVEFORMS The o p e r a t i o n of the converters can simply be ex p l a i n e d w i t h r e -ference to F i g . 1.2 and 1.3. D e t a i l e d e x p l a n a t i o n s can be found i n [ 1 ] , [ 4 ] , [ 5 ] . The equation f o r the r e c t i f i e r d i r e c t v o l t a g e i s : 3/2 E , 3 i) L T >. V. = (cos a I,) dr TT I T d I , = 1.35E (cos a - 0.5 ~ X ) (1.1) I , c dr The transformer leakage reactance, X and the ra t e d d i r e c t c u r r e n t , I , 0 c dr are f i x e d f o r a p a r t i c u l a r HVDC system. E i s determined by the t r a n s -former on-load tap-changer (LTC). Consequently, the r e c t i f i e r d i r e c t v o l t age i s c o n t r o l l e d by the f i r i n g angle a. The equation f o r the i n v e r t e r d i r e c t v o l t a g e i s : 3/2 E , 3 co L s V,. = (COS Y - I ,) d i TT TT d I , = 1.35 E (cos y - 0.5 X ) (.1.2) dr L i k e the r e c t i f i e r , the i n v e r t e r d i r e c t v o l t a g e i s c o n t r o l l e d by v a r y i n g the e x t i n c t i o n angle y. The angles are r e l a t e d by ct + 3 = a + (y + y) = 180° (1.3) where y i s the overlap or commutation angle. The power tr a n s m i t t e d by an HVDC system i s given by: d dr d V, • (V, - V..) dr dr d i ,.. I S = (1.4) A Note that the power i s p r o p o r t i o n a l to the d i f f e r e n c e between r e c t i f i e r and i n v e r t e r v o l t a g e s which means that l a r g e changes i n power can occur f o r r e l a t i v e l y s m a l l changes i n v o l t a g e . I t i s necessary then to s i m u l t a n -eously c o n t r o l both the r e c t i f i e r and i n v e r t e r v o l t a g e s . For t r a n s m i s s i o n schemes a communication system between converters i s necessary. U s u a l l y the i n v e r t e r maintains the system v o l t a g e and the r e c t i f i e r the d i r e c t c u r r e n t . FIGURE 1.4 CONVERTER V-I CHARACTERISTICS 7. F i g . 1.4 gives the V-I c h a r a c t e r i s t i c f o r an HVDC convert e r i n both, r e c t i f y i n g and i n v e r t i n g modes. P a r t ( l ) of the c h a r a c t e r i s t i c shows the n a t u r a l - v o l t a g e c h a r a c t e r i s t i c of the r e c t i f i e r ; t h a t i s , the output v o l t a g e f o r f i x e d delay angle, e.g., V d = 1.35 E ( l - 0 . 5 ^ - X ) (1.5) dr C P a r t @ s h o w s the v o l t a g e c h a r a c t e r i s t i c given by equation (1.1) f o r d i f f e r e n t values of a and E. P a r t ( 3 ) i s the constant c u r r e n t charac-t e r i s t i c which extends to the i n v e r t e r r e g i o n . P a r t ( 4 ) i s the constant e x t i n c t i o n angle (CEA) c h a r a c t e r i s t i c given by equation (1.2). For both mercury arc and t h y r i s t o r v a l v e s , some minimum time, Y q» i s r e q u i r e d to de i o n i z e the v a l v e ; consequently there i s no e q u i v a l e n t to the r e c t i f i e r n a t u r a l - v o l t a g e c h a r a c t e r i s t i c at a = 0. FIGURE 1.5 HVDC SYSTEM CONTROL CHARACTERISTICS 8. The o p e r a t i o n of the r e c t i f i e r and i n v e r t e r together i n a t r a n s -m i s s i o n system can be explained w i t h reference to F i g . 1.5. The r e c t i f i e r maintains the d i r e c t current w h i l e the i n v e r t e r maintains the system v o l t -age. The operating p o i n t i s at A. The v e r t i c a l d i s t a n c e "w" i s an i n d i -c a t i o n of the power t r a n s m i t t e d across the...link. Consider an AC system disturbance r e s u l t i n g i n a lower r e c t i f i e r v o l t a g e E'. The r e c t i f i e r t r i e s to maintain I , but E' i s too s m a l l and the cu r r e n t decreases. The i n v e r t -do er has a backup c o n t r o l made to r e g u l a t e the curr e n t at a s e t t i n g lower than the r e c t i f i e r c urrent order by the curr e n t margin, I^m» which i s 10%-20% of rated c u r r e n t . The i n v e r t e r now c o n t r o l s the curr e n t i n the l i n k along l i n e 1 ^ = - 1^ and the r e c t i f i e r c o n t r o l s the v o l t a g e . The op e r a t i n g p o i n t i s now at B. The tap-changers i n the r e c t i f i e r transformers are meanwhile operating to inc r e a s e the AC v o l t a g e a p p l i e d to the r e c t i f i e r . The p o i n t B s l o w l y moves up the 1 ^ l i n e u n t i l t h e r e i s s u f f i c i e n t AC v o l t a g e f o r the r e c t i f i e r to r e g a i n current c o n t r o l . This i s a simple e x p l a n a t i o n of a t y p i c a l c o n t r o l a c t i o n . A more d e t a i l e d e x p l a n a t i o n w i l l be given l a t e r f o r a p a r t i c u l a r c o n t r o l l e r . There have been two b a s i c methods used to c o n t r o l the f i r i n g angle i n HVDC converters [ 6 ] , [ 7 ] , [ 8 ] . The f i r s t i s the equal angle c o n t r o l where the f i r i n g angles f o r a l l v a l v e s are the same as measured from the i n s t a n t the v o l t a g e becomes p o s i t i v e f o r each p a r t i c u l a r v a l v e . The f i r -i n g i n s t a n t i s determined a f t e r each z e r o - c r o s s i n g and i s s e n s i t i v e to d i s t o r t i o n s and asymmetry i n the AC v o l t a g e s . For t h i s reason the o l d e r HVDC systems r e q u i r e d strong AC systems or l a r g e r e a c t i v e power s u p p l i e s . The second method i s the e q u i d i s t a n t angle c o n t r o l where the f i r i n g i n s t a n t f o l l o w s the previous f i r i n g i n s t a n t by 60° unle s s there i s an e r r o r . Apart from p r o t e c t i v e l i m i t s , the f i r i n g s are not referenced to - T Y Y V J fr* i FREQUENCY/ VOLTAGE f f f 'do VCO RING COUNTER (a) VOLTAGE CONTROLLED OSCILLATOR EQUIDISTANT CONTROLLER PLL _ / V Y \ _ l i—rorv-COUNTER (b) PHASE-LOCKED LOOP EQUIDISTANT CONTROLLER FIGURE 1.6 EQUIDISTANT CONTROLLERS - BLOCK DIAGRAM 10. the AC voltage waveform but are synchronized to the AC system frequency. Equidistant f i r i n g generates less abnormal harmonics than the equal angle f i r i n g . Consequently i t can be used on weak AC systems and requires less VAR supply. The equidistant f i r i n g can be implemented i n two ways. The f i r s t i s e s s e n t i a l l y an analog method and uses a voltage controlled o s c i l l a t o r (VCO). The input voltage corresponds to a reference voltage dependent on the AC system frequency plus the control error. The VCO output i s decoded i n a ring counter and applied to the valves. The VCO frequency increases for e a r l i e r f i r i n g and decreases for l a t e r f i r i n g . The second method i s more d i g i t a l i n nature and uses a phase-locked loop (PLL) whose output frequency tracks the AC system frequency. The analog error voltage i s d i g i t i z e d and loaded i n a counter which i s counted at a rate determined by the PLL. The counter output i s then decoded i n a ring counter before be-ing applied to the valves. The instant of f i r i n g i s varied by changing the number loaded into the counter. The second method has been implemented i n thi s thesis because i t can be interfaced with a computer more e a s i l y than the former. The ex i s t i n g UBC HVDC model converters employ a commercial "equal angle" f i r i n g c i r c u i t consisting of magnetic amplifiers. This c i r c u i t has proven to be unsatisfactory i n many respects [9] . I t i s se n s i t i v e to supply voltages, i s affected by the commutation voltage d i s t o r t i o n and becomes unbalanced f o r asymmetrical AC voltages. The c i r c u i t i t s e l f i s epoxy sealed i n a metal box making repair or modification d i f f i c u l t i f not impossible. To allow future HVDC research to be carried out more e a s i l y , i t was decided to construct a new cont r o l l e r which reflected the l a t e s t developments i n HVDC technology. An equidistant control scheme adaptable to computer control was consequently designed and i s described i n the following chapters. 11. 2. BASIS FOR DESIGN OF AN HVDC CONVERTER CONTROL This chapter describes a closed-loop c o n t r o l system [ 1 0 ] , [11] f o r High Voltage D i r e c t Current (HVDC) converters w i t h independent f e e d -back loops of d i g i t a l i n f o r m a t i o n to produce e q u i d i s t a n t f i r i n g of the HVDC v a l v e s . This e q u i d i s t a n t c o n t r o l forms the b a s i s f o r the d i r e c t d i g -i t a l c o n t r o l implemented i n the f o l l o w i n g chapters. 2.1 BASIC PRINCIPLE The f i r i n g i n s t a n t of a v a l v e V^ i s r e l a t e d to the f i r i n g i n s t a n t ^ of the previous v a l v e V_^  ^ as f o l l o w s : p i = p i - l + 6 0 ° '* 6 i ( 2 , 1 ) where 0^ i s the f i r i n g angle e r r o r f o r v a l v e i expressed i n e l e c t r i c a l degrees, and where i changes i n a c y c l i c manner from 1 to 6. Under steady-s t a t e c o n d i t i o n s , the f i r i n g angle e r r o r 6^ i s zero. Consequently, the f i r i n g i n s t a n t p^ of any v a l v e d e f i n e s completely the f i r i n g i n s t a n t s of a l l the other v a l v e s by means of a t r a i n of pulses 60° apart. We now d e f i n e the c o n t r o l parameter ((> f o r each f i r i n g i n s t a n t as the r e l a t i v e p o s i t i o n of the t r a i n of f i r i n g pulses w i t h respect to the z e r o - c r o s s i n g of the commutating v o l t a g e . The absolute v a l u e of <j> i s of l i t t l e importance s i n c e the q u a n t i t y needed as the b a s i s f o r c o n t r o l i s the v a r i a t i o n of the c o n t r o l parameter A <j>, at each f i r i n g i n s t a n t , i . e . , A <J> = 0 ± (2.2) Under stea d y - s t a t e c o n d i t i o n s aS i s constant. The proposed c o n t r o l scheme i s a negative feedback c o n t r o l w i t h the f i r i n g angle e r r o r made p r o p o r t i o n a l to the d e v i a t i o n from nominal of 12. the c o n t r o l parameter such as c u r r e n t , power, e x t i n c t i o n angle, frequency, e t c . A l l types of converter c o n t r o l attempt to optimise the f i r i n g of the valv e s w i t h respect to the parameter under c o n t r o l , s u b j e c t to requirements of r e l i a b i l i t y of ope r a t i o n and of economy. The proposed c o n t r o l scheme gives r i s e t o two c o n t r o l modes which are considered i n the s e c t i o n s to f o l l o w : 1. R e c t i f i e r Constant Current C o n t r o l (CC) and I n v e r t e r One Way Current C o n t r o l (OWCC) w i t h the DC l i n e c u r r e n t 1^ as the c o n t r o l parameter. 2. I n v e r t e r Safety C o n t r o l (ISC) and I n v e r t e r Optimum C o n t r o l (IOC) which together c o n s t i t u t e the Minimum E x t i n c t i o n Angle (MEA) c o n t r o l w i t h the e x t i n c t i o n angle y as the c o n t r o l parameter. I t should be noted that the converter c o n t r o l i s e i t h e r Current C o n t r o l f o r the r e c t i f i e r or MEA c o n t r o l f o r the i n v e r t e r r e g a r d l e s s of the c o n t r o l parameter f o r the HVDC system. 2.2 RECTIFIER CONSTANT CURRENT CONTROL - THEORY As explained i n Chapter 1, the disadvantages of the c o n v e n t i o n a l constant current c o n t r o l l i e i n the use of the f i r i n g angle a l p h a , a, as the c o n t r o l l e d q u a n t i t y . This can be overcome by us i n g a c o n t r o l parameter which i s not d i r e c t l y dependent on the waveshapes of the commutating v o l t -ages. Using equation (2.1) as the b a s i s f o r the constant c u r r e n t c o n t r o l , the f i r i n g angle e r r o r i s given by: 6 j L = K A I d = K ( I d - I d o ) (2.3) Under balanced or unbalanced steady s t a t e c o n d i t i o n s , w i t h s i n u s o i d a l or 13. d i s t o r t e d waveforms, the c o n t r o l parameter and the f i r i n g angle are con-s t a n t ( i . e . , A <j> = 6^ = 0) and the converter v a l v e s are f i r e d a t r e g u l a r i n t e r v a l s of 60°. In g e n e r a l , f i r i n g according to (2.1) w i l l r e s u l t i n s i x d i f f e r e n t f i r i n g angles, a, per c y c l e . During d i s t u r b a n c e s , v a r i a t i o n of the c o n t r o l parameter A <j> w i l l r e s u l t i n equal changes of the f i r i n g angles. i . e . , A <j> = A a = K A I d (2.4) The d i f f e r e n c e between the conv e n t i o n a l c o n t r o l method and the proposed method i s shown i n t h i s equation. With the conv e n t i o n a l method a common f i r i n g angle, a, i s generated p r o p o r t i o n a l to the d i r e c t c u r r e n t and i s the same f o r a l l the v a l v e s . With the new method, a common v a r i a t i o n of f i r i n g angles i s generated p r o p o r t i o n a l to the v a r i a t i o n of d i r e c t c u r r e n t . In the CC c o n t r o l system defined by (2.1) and (2.3) the f i r i n g angle can take any value. However, there must be a minimum AC v o l t a g e across a v a l v e before f i r i n g i s permitted. This requirement can be ex-pressed as f o l l o w s : * i * m i n ( 2 ' 5 ) where <j> . i s a . , the minimum a l l o w a b l e f i r i n g angle f o r a v a l v e . Thus Tmxn min the r e c t i f i e r operates on CC c o n t r o l when a > ct ^  and on minimum f i r i n g angle a . otherwise. For balanced c o n d i t i o n s , the l a t t e r i s a l s o r e f e r r e d & mm ' to as the n a t u r a l v o l t a g e c h a r a c t e r i s t i c of the converter. The complete equations f o r r e c t i f i e r o p e r a t i o n can now be expressed as f o l l o w s : f i = P i = "i-1 + 6 0 ° 1 6 i i f • P l ^ C i + Vn = C i + a m i n " P ± < C i + a m i n ( 2 ' 6 ) 1 4 . When o. < C. + a •, the CC c o n t r o l i s overridden by the minimum f i r i n g H i i min angle l i m i t , a m ^ n * In a d d i t i o n to the converter c o n t r o l which i s the su b j e c t of t h i s t h e s i s , there i s a converter transformer tap c o n t r o l which although much slower than converter c o n t r o l keeps the f i r i n g angle w i t h i n a range of alpha about the optimum. .2.3 INVERTER CONTROL - THEORY The i n v e r t e r has two b a s i c c o n t r o l modes, the minimum e x t i n c t i o n -angle (MEA) c o n t r o l which i s the normal c o n t r o l mode and the one way cur-r e n t c o n t r o l (OWCC) which i s used to mainta i n power t r a n s m i s s i o n when the r e c t i f i e r i s not capable of m a i n t a i n i n g the c u r r e n t . Minimum E x t i n c t i o n Angle C o n t r o l (MEA) U n l i k e conventional c o n t r o l methods f o r e x t i n c t i o n angle, the MEA i s not a p r e d i c t i v e method. With ref e r e n c e to F i g . 1.3, the f i r i n g i n s t a n t of val v e V^ i s determined at the previous z e r o - c r o s s i n g C^ + 2 and i s based on i n f o r m a t i o n about the system a v a i l a b l e a t that i n s t a n t . If system c o n d i t i o n s remain unchanged during the time i n t e r v a l C^ + 2 t o p^, then the e x t i n c t i o n angle y ^ w i l l be equal to the expected v a l u e y Q . I f , however, the system c o n d i t i o n s change, the c o n t r o l remains unchanged during the disturbance but : eadjusts the f i r i n g at the next z e r o - c r o s s i n g . The MEA can thus be described as a d i s c r e t e negative feedback c o n t r o l s y s -tem. With t h i s type of c o n t r o l , the f i r i n g angle c o r r e c t i o n i s pro-p o r t i o n a l to the d e v i a t i o n of the e x t i n c t i o n angle from the optimum v a l u e , i . e . , 0 ± = A $ = K ( y Q - y ^ ) . ( 2 . 7 ) Using equation (2.1) as the main c o n t r o l equation, steady s t a t e c o n d i t i o n s w i l l r e s u l t i n symmetrical v a l v e f i r i n g s . As a r e s u l t of the symmetrical f i r i n g , any unbalance or d i s t o r t i o n of waveshape may produce s i x d i f f e r e n t Y per c y c l e . The MEA c o n t r o l has two requirements: Y ± 1 Y Q • ^ (2-8) Y . = Y (2-9) mm o The I n v e r t e r Safety C o n t r o l (ISC) ensures that c o n d i t i o n (2.8) i s met. The f i r i n g angle e r r o r here i s given by: 6 i = K l < Y i - l " Yo> ( 2 ' 1 0 ) where Y q 1 S t n e preset e x t i n c t i o n angle f o r the convex-ter. The ISC i s a one way c o n t r o l process which r e s u l t s only i n an increase i n e x t i n c t i o n angle. The ISC i s used to prevent commutation f a i l u r e s and consequent-l y i s e f f e c t i v e on the f i r i n g f o l l o w i n g the di s t u r b a n c e . The I n v e r t e r Optimum C o n t r o l (IOC) implements (2.9) by minimiz-i n g the e x t i n c t i o n angle during the s t e a d y - s t a t e o p e r a t i o n of the i n v e r t -er. The IOC a f f e c t s the f i r i n g of a l l 6 v a l v e s i n a c y c l e o n l y a f t e r i t has been e s t a b l i s h e d that y . > y during the previous c y c l e . This can 'mm o a t - J be expressed i n the f o l l o w i n g equation: Vi -• S « W ] - ( 2- n ) L i k e the ISC, the IOC i s a one way c o n t r o l process, however, i t r e s u l t s only i n a decrease i n e x t i n c t i o n angle. The complete equations f o r i n -v e r t e r MEA c o n t r o l are: 9 i = K l ( Y i - l " Y o } f ° r Y i < Y o ( 2 ' 1 0 ) = K o ['("Y 4 )•• "Y ] f o r Y , > Y (2.11) j+1 2 'min J 'o 'min o 16. Disturbances w i l l normally cause the op e r a t i o n of the ISC f i r s t which i s then f o l l o w e d by ope r a t i o n of the IOC. A long disturbance would normally cause the i n v e r t e r transformer LTC to operate as w e l l . A more d e t a i l e d d i s c u s s i o n of the ISC and the IOC can be found i n refer e n c e [10]. I t can be seen that the two independent c o n t r o l modes of the MEA produce opposite e f f e c t s . Consequently, the o v e r a l l o p e r a t i o n of the MEA c o n t r o l i s s t a b l e s i n c e the ope r a t i o n of the IOC never t r i g g e r s the op e r a t i o n of the ISC. One Way Current C o n t r o l (OWCC) The normal i n v e r t e r c o n t r o l i s the MEA c o n t r o l discussed above. The i n v e r t e r a l s o has a p r o t e c t i v e type of curr e n t c o n t r o l c a l l e d the One Way Current C o n t r o l (OWCC) which i s used to keep 1^ from decreasing below I j ^ . This allows the r e c t i f i e r to r e g a i n c u r r e n t c o n t r o l without s h u t t i n g down the system. The OWCC can be explained by c o n s i d e r i n g the t r a n s i t i o n from MEA to OWCC and v i c e - v e r s a . F i r s t of a l l , the i n v e r t e r i s given a current s e t t i n g 1 ^ which i s l e s s than the r e c t i f i e r c u r r e n t s e t t i n g by the current margin I^m« The value of 1 ^ normally i s 10-20% of the system current r a t i n g . The OWCC process i s defined by (2.1) where the f i r i n g angle e r r o r i s given by: ^-^d - .W 1 £ ^ ^ d i = 0 i f I d >. I d o (2.12) As shown i n F i g . 2.1 c o n t r o l t r a n s f e r s from MEA to OWCC when I . < I . , and t r a n s f e r s from OWCC back to MEA when I , > I , . The OWCC pro-d — d i d — do cess only prevents 1^ from decreasing below l ^ j I t does not prevent the current from i n c r e a s i n g above 1^ because i t can only i n c r e a s e the e x t i n c -t i o n angle. 17. OWCC dm 'di Vo I FIGURE 2.1 OWCC - MEA T r a n s f e r C h a r a c t e r i s t i c 18. 3. CONSTRUCTION OF THE HVDC CONVERTER CONTROL MODEL This chapter outlines the hardware implementation of the control method proposed i n Chapter 2. The converter bridge construction i s f i r s t described and then the converter r e c t i f i e r control block diagram and asso-ciated equations are outlined. The detailed description of c i r c u i t r y and experimental results w i l l be discussed i n Chapters 4 - 6 . 3.1 CONVERTER RACK Fig 3.1 shows the main features of the Graetz bridge used to model an HVDC converter. A device to represent the mercury-arc bypass valve or the s o l i d state bypass switch has not been included because the model i s not intended for transient modelling of start-up/shut-down pro-cedures or protective actions. The model converter has been scaled to be compatible with the exi s t i n g UBC micro-machine AC system model. The control requires two inputs from the bridge: the AC voltages and the dir e c t cur-rent. Matched re s i s t o r s have been used to construct the 3 phase voltage divider which has a single phase r a t i o of 100:1. The maximum phase-phase error i s 0.17%. Although the resistance divider gave no problems, an improvement would be to use 3 potential transformers to provide complete ground i s o l a t i o n between the power and control c i r c u i t s . The 0.5 ohm resistance on the DC side gives the required voltage drop to the Direct Current Sensor which i s described i i i 5.1. The voltage and current panel meters shown i n F i g . 3.1 are mounted at the top of the rack j u s t above the converter bridge. Important nodes i n the power c i r c u i t are brought out to a coloured mimic panel f o r easy monitoring with scope or meter probes. A va r i e t y of control functions DC LINE SWITCH <—*——> SCRS GE TYPE C35S l u • o- MIMIC PANEL CONNECTION SENSOR FUSES ENGLISH ELECTRIC (y-BINDING POST ON REAR TYPE CS450/15 OF RACK FIGURE 3.1 c CONVERTER SCHEMATIC 20. are a l s o mounted on the mimic panel. A breadboard s h e l f w i t h f i v e bread-boards i s l o c a t e d j u s t below the wire-wrap p i n s of the p r i n t e d c i r c u i t board (PCB) connectors. This i s q u i t e u s e f u l f o r c o n s t r u c t i n g new c i r c u i t s and f o r modifying c i r c u i t s already on the PCBs. The main power s u p p l i e s , a convenience receptable and the power te r m i n a l s of the b r i d g e are mounted near the bottom of the rack. 3.2 CONVERTER CONTROL MODEL Chapter 2 b r i e f l y described the theory behind a new d i g i t a l con-t r o l system f o r HVDC converters. This s e c t i o n o u t l i n e s a hardware implemen-t a t i o n based on that c o n t r o l . The main d i f f e r e n c e s w i t h the c o n t r o l s y s -tem described i n [10] and [11] and the e q u i d i s t a n t f i r i n g c o n t r o l implemen-ted here are the use of an e l e c t r o n i c phase-locked-lcop r a t h e r than an electromechanical o p t i c a l encoder to generate the c o n t r o l frequency and p r o v i s i o n f o r p o s s i b l e computer c o n t r o l . This s e c t i o n gives a f u n c t i o n a l d e s c r i p t i o n of the c o n t r o l w h i l e the d e t a i l e d d e s c r i p t i o n s w i l l be given i n the f o l l o w i n g chapters. The block diagram f o r the r e c t i f i e r c o n t r o l system i s shown i n F i g 3.2. The c o n t r o l can be broken down i n t o three main p a r t s : generation of the c o n t r o l frequency f , monitoring of analog q u a n t i t i e s , and gene r a t i o n of the SCR f i r i n g p u l s e s . The c o n t r o l frequency, f , i s a m u l t i p l e of the AC l i n e frequency and remains i n synchronism w i t h i t . I t i s the master c l o c k f o r the d i g i t a l p o r t i o n of the c o n t r o l . Various analog q u a n t i t i e s -AC v o l t a g e s , d i r e c t current order and d i r e c t c u r r e n t response - are moni-tored, c o n d i t i o n e d and processed to provide t i m i n g pulses and the d i g i t i z e d current e r r o r to the c o n t r o l . Generation of the f i r i n g p ulses i s done i n >-ri o * l w <; . o o o < H M ?Cl o M n a: O ii p- CO N j o rn i r— O O rn CD to I o crj O 01 or-to 5 § rn CD MP LI ERR \j co o IER 33 o or o O A o (0 o V o or o o V A INVERTER CONTROL COMPUTER o CONTROL 'TI 22. the d i g i t a l p o r t i o n from i n f o r m a t i o n provided by the analog f r o n t end or an e x t e r n a l i n p u t . An o u t l i n e of the f u n c t i o n of the v a r i o u s b l o c k s i n the c o n t r o l i s given below. Generation of the C o n t r o l Frequency,.f Figure 3.2 shows the main b l o c k s a f f e c t i n g generation of the con-t r o l frequency. D e t a i l s of the i n d i v i d u a l c i r c u i t s can be found i n Chapter A. One AC v o l t a g e - a r b i t r a r i l y chosen as phase A - i s a p p l i e d to the Phase-Locked Loop Input C o n d i t i o n i n g (PIC) board which generates a p u l s e t r a i n at a frequency, f ^ j double that of the AC system frequency f , i . e . , f r l = 2*f (3.1) The board contains a 3-pole low-pass f i l t e r , a z e r o - c r o s s i n g comparator and two monostables. A d i g i t a l Phase-Locked Loop (PLL) i s the h e a r t of the c i r c u i t t hat generates the c o n t r o l frequency, f c - To s i m p l i f y c o n s t r u c t i o n of the PLL, the PLL input reference frequency, f ^ , i s double the l i n e frequency. Since f o r AC power systems, the r a t e of frequency change i s slow, the PLL time constant can be lon g . This r e s u l t s i n a r a t h e r long lock-up time which i s the time r e q u i r e d f o r the PLL to l o c k on to the r e f e r e n c e from i t s f r e e running frequency. This i s overcome by s u p p l y i n g a r e f e r e n c e frequency, f ^ , that i s c l o s e to the nominal frequency. This i s the func-t i o n of the Reference Frequency S e l e c t o r . I f the AC v o l t a g e i s below a t h r e s h o l d , the PLL Input C o n d i t i o n i n g board w i l l not produce a r e l i a b l e pulse t r a i n and the Reference Frequency S e l e c t o r then s e l e c t s the output of the 120 Hz A s t a b l e Generator to be a p p l i e d to the PLL. 23. i . e . , f r = f r l • (AC ON) + f r 2'(AC ON) (3.2) Consequently, the PLL either generates the desired control frequency or can generate i t quickly as soon as conditions permit. The PLL i s e s s e n t i a l l y a fixed frequency m u l t i p l i e r generating a square wave output that tracks the input pulse t r a i n £ ^ or square wave f r 2 ' ' i . e . , f = 240*f (3.3) ' o r Before the PLL output i s applied to the control, i t goes through the s t a r t / stop i n h i b i t block. The equation f o r the control frequency generator i s : f = 240*f = 480*f (3.4) c r Monitoring of Analog Quantities As shown i n Fig'. 3.2, there are three analog quantities being monitored for the r e c t i f i e r equidistant f i r i n g control - the dir e c t cur-rent response 1^, the dir e c t current order 1 ^ , and the commutating v o l t -ages. These quantities provide the control error signal 6^  of equation (2.1) and the timing pulses of equation (2.6). C i r c u i t d e t a i l s can be found i n Chapter 5. The Direct Current Sensor measures the direct current using opto-i s o l a t o r s to achieve ground i s o l a t i o n between the DC power c i r c u i t and the control system. I t s output, 1^, and the dir e c t current setting from a potentiometer on the mimic panel are applied to the Error Amplifier to produce: e •» K ( I . - I . ) (3.5) o d do which i s applied to the Analog-to-Digital Converter (ADC). The zero-voltage crossover p o i n t s of the commutating v o l t a g e s (voltages across the v a l v e s ) are determined by the Commutating Voltage Crossover Detectors (CVCD). Two outputs are r e q u i r e d . The f i r s t output . i s a pulse t r a i n of frequency 6*f to the ADC to i n i t i a t e the d i g i t i z i n g process at each z e r o - c r o s s i n g , C^. The second output i s a s e t of 6 pul s e t r a i n s , each at frequency f , to the F i r i n g P ulse Generator (FPG) f o r implementing the minimum f i r i n g a n g l e . l o g i c d e c i s i o n of equation (2.6). The ADC output, 0, i s the 2's complement b i n a r y form of e Q and i s a p p l i e d to the C o n t r o l Mode Lo g i c described i n the next s e c t i o n . Since conversion takes about 25 ys,- the updated value of 0 i s a v a i l a b l e approx-i m a t e l y 350 us before i t must be a v a i l a b l e ( f o r a . = 8° = 368 y s ) . Con-J mm v e r s i o n occurs at a p o i n t i n the d i r e c t c u r r e n t waveform where normally there are no d i s c o n t i n u i t i e s . Generation of the Valve F i r i n g Pulse As shown i n F i g . 3.2, t h i s s e c t i o n of the c o n t r o l r e c e i v e s the c o n t r o l e r r o r from one of s e v e r a l sources, processes i t and generates a f i r i n g pulse which i s a p p l i e d to the SCR gate. The d e t a i l s of the b l o c k s o u t l i n e d here are found i n Chapter 6. I n the u l t i m a t e c o n f i g u r a t i o n of the c o n t r o l system, the c o n t r o l e r r o r can come from the ADC, the i n v e r t e r c o n t r o l c i r c u i t s or from a computer c o n t r o l . I t i s the f u n c t i o n of the Co n t r o l Mode Lo g i c to determine which source i s a p p l i c a b l e and to route the d i g i t i z e d e r r o r to one of two r e g i s t e r s i n the F i r i n g P u l s e Generator. The FPG has two s e c t i o n s . The f i r s t s e c t i o n implements equation (2.1). i . e . , p. = p. . + 60° ± 'e. (2.1) l l - l i I t can be seen here that i f 0^ = 0, t h i s s e c t i o n w i l l produce f i r i n g s that are 60° apart. Hence t h i s s e c t i o n i s the heart of the e q u i d i s t a n t f i r i n g c o n t r o l system. The second s e c t i o n - the minimum f i r i n g angle l o g i c - implements equation (2.6). i . e . , f. = p. . + 60° + 0. i f p > C. + a . l i - l i i — l mm f = C. + a . i f p. < C. + a . (2.6) i i mm I i mm The output of the FPG then i s a p p l i e d to the SCR Gate Drives which produce gate s i g n a l s of about 100° d u r a t i o n f o r each v a l v e . O p t i c a l - i s o l a t o r s are a l s o used i n the Gate Drives to ensure ground i s o l a t i o n between the SCR bri d g e and the c o n t r o l system. 26. 4. DESIGN AND EXPERIMENTAL RESULTS OF THE PHASE-LOCKED LOOP AND CONTROL FREQUENCY GENERATION This chapter describes i n d e t a i l the method to generate the con-t r o l frequency, f , o u t l i n e d i n S e c t i o n 3.2. The c o n t r o l frequency t r a c k s the l i n e frequency and i s the master c l o c k f o r the d i g i t a l p o r t i o n of the c o n t r o l . The c i r c u i t d e t a i l s are given f o r each b l o c k together w i t h the experimental r e s u l t s . The design procedure f o r the Phase-Locked Loop i s a l s o i n c l u d e d . 4.1 PHASE-LOCKED LOOP INPUT CONDITIONING BOARD (PIC) As s t a t e d i n Secti o n 3.2, the PIC provides a pulse t r a i n at f ^ = 2*f Hz f o r the PLL input reference frequency. F i g . 4.1 i s the schematic diagram f o r t h i s c i r c u i t . The input f i l t e r i s a 3-pole 0.1 db r i p p l e low-pass Chebyshev f i l t e r w i t h a c u t o f f frequency of 90 Hz and i s based on a design [12] usi n g a u n i t y g a i n o p e r a t i o n a l a m p l i f i e r to achieve the complex conjugate p o l e s . The Chebyshev f i l t e r has h i g h c u t o f f r a t e . The Zero-voltage comparator i s a simple op-amp d r i v e n open loop w i t h the "Zero A d j u s t " ensuring t h a t the r i s i n g and f a l l i n g edges of the square wave output are e x a c t l y 180° apart. Various l i m i t c i r c u i t s u s i n g diodes and zener diodes were t r i e d i n the feedback loop but the open loop c o n f i g u r a t i o n was the best. The comparator output i s a p p l i e d to the dual monostables (one t r i g g e r e d on the r i s i n g edge, the other on the f a l l i n g edge) to get a pulse t r a i n w i t h pulses at every z e r o - c r o s s i n g of the in p u t v o l t a g e . Phase A must be at l e a s t 65 VAC measured at the primary of the vo l t a g e d i v i d e r to al l o w the PIC to produce a r e l i a b l e output. A 3-phase v e r s i o n of the above c i r c u i t was constructed but was abandoned because i t was q u i t e d i f f i c u l t to achieve and ma i n t a i n the l e a d -i n g edges of a l l 6 pulses e x a c t l y 60° apart. The PLL used i n t h i s imple-SINGLE PHASE INPUT { 1.2Vrms 60 Hz B38 BL2 M ZERO ADJUST 5 5 K U FIL TER COMPARATOR (IB) (1Q) SN 74123 (2A) (20) I\\-\(1A) (2B) Rx ASI J _ +5 i +5 470-a Tx II n n 0 180 350 S/V 7405 Rx c AS2 AUJ +5 IK • DUAL MON OS TABLE OR TO REFERENCE FREQUENCY SELECTOR R=116Kn Rxr-47Kn. C2 = 0.02?juf Tx =1.2-1.4 ms z= 28C C3 * 0-002y f ALL COMPONENTS ON BOARD 37 o OUTPUT PIN FIGURE 4.1 PHASE-LOCKED LOOP INPUT CONDITIONING SCHEMATIC 28. m e n t a t i o n i s f a i r l y s e n s i t i v e t o v a r i a t i o n i n t h e p e r i o d i c i t y o f the i n p u t and w i l l j i t t e r f o r an i n p u t which i s n o t p e r i o d i c . 4.2 ASTABLE FREQUENCY GENERATOR AND REFERENCE FREQUENCY 1 SELECTOR As n o t e d i n S e c t i o n 3.2, the Phase-Locked Loop (PLL) has a r a t h e r l o n g l o c k - u p t i m e . W i t h no r e f e r e n c e f r e q u e n c y a p p l i e d t o t h e phase de-t e c t o r o f the PLL, the V o l t a g e C o n t r o l l e d M u l t i v i b r a t o r (VCM) i n the PLL w i l l r u n a t i t s f r e e r u n n i n g f r e q u e n c y which i s c o n s i d e r a b l y h i g h e r th an t h e c e n t e r f r e q u e n c y o f 28.8 KHz. Upon a p p l y i n g t h e r e f e r e n c e f r e q u e n c y , the phase d e t e c t o r produces an e r r o r v o l t a g e which tends t o change the VCM o u t p u t t o the f r e q u e n c y and phase of the r e f e r e n c e . S i n c e the PLL has a l o n g time c o n s t a n t , t h i s n o r m a l l y t a k e s 10 - 15 second s . However, i t i s p o s s i b l e f o r the PLL t o l o c k i n on the 3 r d harmonic o f t h e i n p u t o r t o l a t c h i n on the f r e e r u n n i n g f r e q u e n c y due t o a m p l i f i e r s a t u r a t i o n . To overcome t h e s e problems, a r e f e r e n c e f r e q u e n c y c l o s e t o the no m i n a l f r e q u e n c y i n p u t i s always a p p l i e d t o the phase d e t e c t o r o f the PLL. The l o c k u p time i s then r e d u c e d t o about 0.1 s e c . A r e f e r e n c e f r e q u e n c y , f r 2 > 1 S g e n e r a t e d i n an A s t a b l e F r e q u e n c y G e n e r a t o r which c o n s i s t s o f a V o l t a g e C o n t r o l l e d M u l t i v i b r a t o r (VCM) f e d by a f i x e d v o l t a g e . See F i g . 4.2. F i g . 4.3 shows t h e c a l i b r a t i o n c u r v e o f the VCM f o r the chosen c a p a c i t a n c e . The o p e r a t i n g p o i n t i s chosen around the knee o f the c u r v e . F o r f ^ = 2*f n o m i n a l = 120 Hz Square Wave, C 0 = 0.0047 y f , f = 28600 Hz x2 o D i v i d e r N =. = • 2 | | ~ = 238.2 = 238 r2 i Z U = N + 16*N_ o 1 = 14 + 16 * 14 220^ SpF S-SKs<. 22 Kn Cx2 = 0-0047pF rh VCM MC4024 GATE No=14 e U S S U -CLK MC4018 RES U CLK N, =14 MC4018 0 GATE TO REFERENCE -o FREQUENCY fr2 SELECTOR (120 Hz SQUARE) FIGURE 4.2 ASTABLE FREQUENCY GENERATOR SCHEMATIC J 3.0 VIN CONTROL RANGE 2.0 1.01 -2.00-^ 1.63 L c x 2 = 0.0047juF 28600 Hz 28k J 29k 30k 1 _ i — 31k 238 242 250 N (fr2 = 120 Hz) FIGURE 4.3 CALIBRATION CURVE FOR ASTABLE FREQUENCY GENERATOR 3 PHASE INPUT FROM VOLTAGE-DI VIDER (BD 38) 1 BD 37 ~ i DIODE i i DIFFERENTIAL 1 TO BRIDGE 1 THRESHOLD _ J REFERENCE 1 AMPLIFIER THRESHOLDO— DETECTOR i FREQUENCY 1 SET FOR ! SELECTOR VAC = 6 5 BLOCK DIAGRAM 0 A O JO B O 0 c O BT2 BR2 BF2 NO$f in SCHEMATIC FIGURE 4.4 "AC ON" DETECTOR SCHEMATIC Normally £ ^ jo 28600 N 238 120.2 Hz Fig u r e 4.4 shows the "AC ON" Detector c i r c u i t . The d i f f e r e n t i a l ' a m p l i f i e r provides b u f f e r i n g between the power c i r c u i t v o l t a g e d i v i d e r and the c o n t r o l c i r c u i t . A l s o the th r e s h o l d d e t e c t o r i s set f o r a v o l t a g e where the PIC w i l l produce a r e l i a b l e £ ^. f o-AC ON ( '? '.-ON t o TO PHASE -otr LOCKED LOOP MC 7400 FIGURE 4.5 REFERENCE FREQUENCY SELECTOR Figure 4.5 shows the schematic f o r the a c t u a l Reference Frequency S e l e c t o r which implements (3.2), x. e, f = f • (AC ON) + f . r r l r2 (AC ON) Thus the Reference Frequency S e l e c t o r ensures t h a t the PLL has e i t h e r the de s i r e d i n p u t , f o r a n i n p u t , f r2> which allow s quick and r e l i a b l e trans-f e r to f .j when c o n d i t i o n s permit, r l r 4.3 PHASE-LOCKED LOOP (PLL) The c i r c u i t produces a square wave output, f , which i s an i n t e g e r m u l t i p l e of the l i n e frequency and which t r a c k s the l i n e frequency i n phase and frequency. The output i s the master c l o c k source f o r the d i g i t a l por-t i o n of the c o n t r o l to be described i n Chapter 6. An accurate and r e l i a b l e c l o c k source i s e s s e n t i a l to get the proper f i r i n g i n s t a n t . In the f o l l o w i n g s e c t i o n s , the theory and design procedure i s 32. f i r s t d e s c r i b e d , then the c i r c u i t d e t a i l s e x p l a i n e d and f i n a l l y some r e s u l t s t a b u l a t e d . Theory and Design Procedure A b r i e f d e s c r i p t i o n of the theory and design procedure i s given here. For a more d e t a i l e d e x p l a n a t i o n see [13]. The d e s c r i p t i o n that f o l l o w s i s based on a design using Motorola TTL c i r c u i t s . A b l o c k diagram f o r the PLL i s given i n F i g . 4.6. The d i f f e r e n c e i n phase between the reference frequency, f ^ , from the Reference Frequency S e l e c t o r and the feedback frequency of the PLL, f , i s determined i n the d i g i t a l phase d e t e c t o r . I f the inputs are i n phase then the phase d e t e c t o r output i s about 1.5 V. I f there i s a phase d i f f e r -ence, the d e t e c t o r produces pulses of v a r i a b l e width between 0.75 V and 2.25 V. The pulsed.output i s f i l t e r e d i n a low-pass or a l e a d - l a g f i l t e r b efore being a p p l i e d to the Voltage C o n t r o l l e d M u l t i v i b r a t o r which produces an output frequency dependent on the in p u t v o l t a g e . The c a l i b r a t i o n curve f o r t h i s VCM i s given i n F i g . 4.7. Note that the VCM i s l i n e a r o n l y over a narrow range. The output, f Q , i s d i v i d e d down by the i n t e g e r m u l t i p l e of the PLL and then fed back to the phase d e t e c t o r . In most a p p l i c a t i o n s i n v o l v i n g phase-locked l o o p s , such as f r e -quency s y n t h e s i s , the reference frequency i s f i x e d and the d i v i d e r i s pro-grammable. However, t h i s a p p l i c a t i o n r e q u i r e s that the d i v i d e r be f i x e d and output frequency t r a c k the in p u t frequency. The design procedure noted here f o l l o w s the procedure o u t l i n e d i n pages 19 - 37 of [13]. 1. Reference pulse r e p e t i t i o n frequency range nominal f r = 2*f = 120 pps maximum f = 2*65 = 130 pps r o 33. 'REFERENCE o FREQUENCY fr SELECTOR (120 PPS) PHASE DETECTOR LOW PASS FILTER Krr VCO DIVIDER KN-N (240) -of0=N.fr (28.8 kHz) FIGURE 4.6 BLOCK DIAGRAM OF PHASE-LOCKED LOOP 4.0 S3.0 —i i o cc 2.0 t~~. 5 : o o 7.0 15 o C = 0.01JJF Kv = 22kHz/V k C = 0.0069/JF Kv = 12 kHz/V _J L 20 I 25 A 30 2 1 5 • 28-S VCM FREQUENCY 35 | kHz 37.4 FIGURE 4.7 CALIBRATION CURVE FOR PLL VCM minimum f = 2*56 = 112 pps r Feedback d i v i d e r ( f i x e d ) N = 240 «= N + 16*N-o 1 = 16 + 16 * 14 f*360 f*360 . ,_ 0 / . Accuracy = f * N = 2 * f * 2 4 0 = 0 , 7 5 / P u l s e -r VCM range nominal: f = N * f nom = 240 * 120 = 28 800 Hz o r maximum: f = (1+20%) N * f max = 1.2* 240 * 130 = 37 440 Hz o r minimum: f = (1-20%) N * f min = 0.8 * 240 * 112 = 21 504 Hz o r The 20% i s a s a f e t y f a c t o r . _ .. ^o max 37 440 , v, , « c R a t i o -z — = r A / = 1.74 < 3.5 f mm 21 504 o This range can be implemented on the MC 4024 VCM. From Table 1, page 55 of [13] K l = 280 K l Therefore Tuning c a p a c i t o r C = [- , x m N — 5] pf b r x f max (MHz) o 280 _ 0.0374 - 0.0075 uf Figure 4.7 shows the c a l i b r a t i o n curve of the VCM f o r two values of capacitance. A choice was made on the b a s i s of wide bandwidth and high input v o l t a g e . i . e . , C =0.01 uf, K = 22 KHz/volt ' x v 35. 2 25 *** 0 75 Phase d e t e c t o r gain = ^ _~(-2n) = °'12 V o l t s / r a d i a n Kd> K v 2 TT * 0.12 * 22 x 1 0 3 Therefore loop g a i n , K l o Q p = = ; ^ = 69.12 sec - 1 4. For a maximum overshoot <_ 10%, choose t, = 1.13 5. Loop F i l t e r . Since the l i n e frequency f w i l l not change very f a s t even f o r s e r i o u s f a u l t c o n d i t i o n s , choose a 1 sec time constant f o r the low-pass s e c t i o n of the f i l t e r t = 1 sec = • C = 0.94, R± = 20 KQ, C± = 47 y f K Loop bandwidth % = = =8.58 rad/sec i . e . , f = 1.36 Hz n I n t e g r a t o r l a g s e c t i o n 2C 2 x 1.13 n O , o „„„ T 0 = R 0C = *±r = — n c o ' = ° - 2 6 3 s e c 2 2 OJ o.5o n Therefore R 0 = — ° ' 2 6 3 _ f i = 5.6 Kft ^ 47 x 10 1 + R 2 Cs 1 + 0 > 2 6 3 s Therefore f i l t e r t r a n s f e r f u n c t i o n K p - g jjg 0.94 s \ . 1 PLL C i r c u i t D e t a i l s This s e c t i o n o u t l i n e s the d e t a i l s of implementing the design pro-cedure noted above and notes some of the p e c u l i a r i t i e s of t h i s make of PLL. The schematic i s shown i n F i g . 4.8. I t i s e s s e n t i a l that the d i g i t a l and analog s e c t i o n s of the PLL have t h e i r own regulated power s u p p l i e s . I t i s hard to overdesign the power s u p p l i e s to the PLL. The major source of no i s e on the power s u p p l i e s X 700/// PHASE DETECTOR JOKA 10 KSI 5.6Ksi 47uf 1.2K& 0.01 uf 1 1 1 TL , u VCM 3-9KSL I 5.0 ± Uf 5.0 V REG + 5 Pl p 2 P3 GATE Q3 +N} = 14 CLK FIGURE 4.8 PHASE-LOCKED LOOP SCHEMATIC X lOOfif PHASE DETECTOR WKA IOKSI 5.6Ksi 47uf 1.2K& O.Oluf "ZL . X 1" 14 VCM ^0.47 M f 3.9KSL H h IJT 5.0 14 f 5.0 V REG + 5 Pj P2 P3 GATE Q3 +N}=14 CLK GATE CLK Q. BUSS FIGURE 4.8 PHASE-LOCKED LOOP SCHEMATIC 37. i s the VCM o u t p u t b u f f e r . The f i r s t s u p p l y i s f o r the d i g i t a l phase d e t e c -t o r and the VCM o u t p u t b u f f e r . The second s u p p l i e s power f o r the f i l t e r i n p u t b i a s i n g and t h e VCM. Even w i t h the c a p a c i t o r s and r e g u l a t o r s mounted r i g h t b e s i d e the a p p r o p r i a t e p i n s , i t s t i l l i s i m p o s s i b l e t o remove a l l t h e n o i s e from the VCM i n p u t . Even w i t h a s e p a r a t e r e g u l a t o r f o r t h e VCM b u f f e r , the b e s t s o l u t i o n may be a w e l l d e s i g n e d PCB. The d i g i t a l phase d e t e c t o r d e t e r m i n e s the phase d i f f e r e n c e be-tween t h e n e g a t i v e t r a n s i t i o n s o f the two i n p u t waveforms, f and f ^ . A charge pump produces p o s i t i v e and n e g a t i v e p u l s e s superimposed on the 1.5 VDC l e v e l c o r r e s p o n d i n g t o the phase d i f f e r e n c e . The duty c y c l e o f f and f can be d i f f e r e n t b u t s h o u l d be c l o s e . The r e f e r e n c e s i g n a l f must be v & r p e r i o d i c o r e l s e i n s t a b i l i t y and even o u t - o f - l o c k c o n d i t i o n o f t h e PLL can r e s u l t . The l o o p f i l t e r smoothes out t h e phase d e t e c t o r p u l s e p r i o r to the VCM i n p u t . Use o f the op-amp a c t i v e f i l t e r and the op-amp b i a s d e c r e -ases the l o a d i n g on t h e charge pump. S i n c e i t i s p o s s i b l e d u r i n g t r a n s i e n t s to g e t s a t u r a t i o n o f the op-amp and c o n s e q u e n t l y poor s e t t l i n g time, the i n p u t r e s i s t o r o f the i n t e g r a t o r l a g f i l t e r i s s p l i t t o make a low pass f r o n t end. Loop bandwidth co =8.58 r / s n Low pass c u t o f f = co = (5-10) co c n Choose co = 100 c T h e r e f o r e C = 2 2 c .(Rl) - n n 20 x 10-co » 100 x „ C 2. L = 2.0 y f Since the l i n e frequency changes s l o w l y and over a narrow range, a long f i l t e r time constant (T^ = 0.94'sec) i s used to help o v e r r i d e n o i s e on the ac system even though a comparatively narrow bandwidth ( f =1.36 Hz) r e s u l t s . This u n f o r t u n a t e l y a l s o r e s u l t s i n a long lockup time (10-15 s e c ) . A c h a r a c t e r i s t i c of the Motorola PLL i s th a t i t can and d i d l o c k i n on the t h i r d harmonic. To overcome these problems, the A s t a b l e Frequen-cy Generator and the Reference Frequency S e l e c t o r d escribed i n S e c t i o n 4.2 were b u i l t . The VCM produces an output square wave, f , dependent on the i n -put c o n t r o l v o l t a g e from the loop f i l t e r and the tuning capacitance C^. A tuning capacitance of 0.01 uf was chosen (see F i g . 4.7) to get a l i n e a r response over the d e s i r e d frequency range, and a high c o n t r o l v o l t a g e even though the ga i n constant was hi g h . The VCM output i s fed through a d i v i d e r , which i n t h i s a p p l i c a t i o n i s f i x e d at N = 240, to produce the feedback frequency f to the phase d e t e c t o r . A square wave output i s taken from the 1 d i v i d e r r a t h e r than the normal pulse output [pulse width = -^Q x (square wave wid t h ) ] to t r y to prevent l o c k i n g on other than the fundamental. Test R e s u l t s (120 pps) (120 Hz) fo • (28.8 KHz) •12-14 ms 'uir •34.7JLJS FIGURE 4.9 PLL INPUT WAVEFORMS 39. PLL frequency range 35 Hz - 66 Hz ( s l o w l y v a r y i n g ) Lockup time: without A s t a b l e Frequency Gen. 10 - 12 sec. w i t h A s t a b l e Frequency Gen. 0.1 sec. Allowable step frequency changes 55<->60 Hz (without l o s i n g l o c k ) 60-*-v64 Hz See F i g . 4.10 f o r t e s t c i r c u i t . Frequency steps: I n i t i a l Freq. F i n a l Freq. Time (approx.) (Hz) (Hz) (sec) 60 62 1 60 63 1 60 64 1 60 55 1 62 • 60 3 63 60 3 64 60 3 55 60 3 MOTOR ARMATURE FIELD ALTERNATOR FIELD STAT OR + o 7 75 VDC STEP N SWITCH 19SL - o~ 50JI 200*. FIGURE A.10 CIRCUIT FOR PLL STEP FREQUENCY TESTS 4.4 START/STOP CIRCUIT' The Start/Stop Circuit inhibits the PLL output f unless certain conditions have been met and i n i t i a l i z e s the control at start-up. A block diagram is shown in Fig. 4.11 and the schematic in Fig. 4.12. PLL f0O-OUTPUT CVCD OUTPUT C S ° M R T (BD 36) STOP PLL INPUT MONO ~4 us ALPHA START TIMER S°-160° MONO ~WMS > MASTER RESET o S Q p START FF \ R I CONTROL FREQUENCY OTHER STOP SIGNALS FIGURE 4.11 START/STOP CIRCUIT - BLOCK DIAGRAM The inhibit on f is removed during the normal start-up sequence. Upon energizing the AC system, the commutating voltage crossover, points, C, are detected and one of these - C, has been a r b i t r a r i l y chosen - is x 6 applied to the start toggle. Depressing the START toggle allows the out-put of comparator AB to be applied to the Alpha Timer. The output pulse width of the Alpha Timer corresponds to the desired starting f i r i n g angle. The Alpha Timer resets the control and signals the Start Monostable. The Start Monostable and other signals set the Start FF to enable the PLL out-put. For the ALPHA TIMER: Range of a start = 5° ->" 160° PLL AA1 fn O-OUTPUT ALPHA START MASTER RESET r OTHER STOP SIGNALS E>—E> AD2 fc CONTROL FREQUENCY SWITCHES ON MIMIC PANEL OTHER COMPONENTS ON BO 15 0—BOARD OUTPUT PIN FIGURE 4.12 START/STOP CIRCUIT - SCHEMATIC 43. a s t a r t - 230 us ->- 7.4 ms F o r C = 0.01 y f , R = 500" Kft P o t T h e r e f o r e T = 2RC = 0 + 10 ms = 0° -*• 216° a t 60 Hz A l t h o u g h the A l p h a Timer d e t e r m i n e s the i n s t a n t o f the f i r s t f i r i n g p u l s e , w i t h t h e p r e s e n t c i r c u i t , t h e second f i r i n g p u l s e w i l l d i f f e r depending on the e r r o r from the E r r o r A m p l i f i e r . F o r a smooth s t a r t i t may be d e s i r a b l e t o o v e r r i d e the e r r o r a m p l i f i e r o u t p u t f o r s e v e r a l c y c l e s w i t h a d e c a y i n g s t a r t o r d e r o r to r u n t h e c o n v e r t e r on f o r c e d e q u i d i s t a n t f i r i n g f o r s e v e r a l c y c l e s . The use of a v a r i a b l e s t a r t i n g f i r i n g a n g l e and a smooth s t a r t i s r e q u i r e d f o r a c c u r a t e s i m u l a t i o n o f an HVDC c o n t r o l b u t f o r most purposes i t i s not n e c e s s a r y . I t may be p o s s i b l e t o i n c o r p o r a t e t h e s i m u l t a n e o u s s t a r t up o f b o t h the r e c t i f i e r and i n v e r t e r i n a system c o n t r o l l e r . The i n c l u s i o n o f the PLL In p u t M o n o s t a b l e e n s u r e s t h a t f i s en a b l e d a t a p r e d i c t a b l e p o i n t on t h e waveform. The monostable p u l s e w i d t h s were d e t e r m i n e d f o r f = 86.4 KHz when the PIC was a 3 phase u n i t . W i t h f d e c r e a s e d t o 28.8 KHz the START/STOP has n o t behaved p r e d i c t a b l y p r o b -c a b l y because the monostable p u l s e w i d t h s s h o u l d be l e n g t h e n e d by a f a c t o r o f 3. The STOP t o g g l e and o t h e r s i g n a l s l i k e the O v e r c u r r e n t P r o t e c t i o n o u t p u t r e s e t the S t a r t FF to i n h i b i t 'f and must be r e s e t p r i o r t o s t a r t -i n g up the c o n v e r t e r . T h i s c h a p t e r has d e s c r i b e d the c i r c u i t s t o g e n e r a t e the master c o n t r o l f r e q u e n c y f . Schematics and t e s t r e s u l t s have been g i v e n as w e l l as comments on d e s i g n p r o c e d u r e s and p o s s i b l e changes. 44. 5. DESIGN AND EXPERIMENTAL RESULTS OF CIRCUITS TO MONITOR ANALOG QUANTITIES This chapter d e t a i l s the design o u t l i n e d i n S e c t i o n 3.2 f o r c i r -c u i t s m o n i t o r i n g the d i r e c t current and the commutating v o l t a g e s f o r the e r r o r a m p l i f i e r and the analog to d i g i t a l c onverter (ADC). The outputs of the ADC and the Commutating Voltage Crossover Detectors (CVCD) are proces-sed by the F i r i n g P ulse Generator (FPG) to be described i n Chapter 6. With reference to F i g . 5.1, the e r r o r a m p l i f i e r compares the d i r e c t cur-rent response, 1^, measured by the D i r e c t Current Sensor and the current s e t t i n g 1^ to provide an e r r o r s i g n a l , e Q , to the ADC f o r d i g i t i z i n g so the FPG can determine the next f i r i n g i n s t a n t . The CVCD provides pulses to the ADC to i n i t i a t e the conversion process and to the FPG f o r the min-imum f i r i n g angle l o g i c . The c i r c u i t . d e t a i l s and t e s t r e s u l t s f o r each b l o c k of F i g . 5.1 are given i n the f o l l o w i n g s e c t i o n s . 5.1 DIRECT CURRENT SENSOR (DCS) AND ERROR AMPLIFIER The D i r e c t Current Sensor (DCS) gives an i s o l a t e d l i n e a r output to the c o n t r o l corresponding to the d i r e c t c u r r e n t i n the DC L i n e . The design i s based on references [14] and [15]. Theory and C i r c u i t D e t a i l s The DCS i s based on u s i n g a matched p a i r of p h o t o - i s o l a t o r s to achieve an i s o l a t e d and l i n e a r output. With reference to F i g . 5.2, the r a t i o lo/l^ i s constant independent of i n p u t amplitude or component temp-e r a t u r e , I o CT^ ( I , T A, t ) U e ' > r = CTR 2 ( I , T A, t) = c o n s t a n t c 5 - 1 ) CURRENT SETTING do T 0 AO-2.08 VAC 0 flO 60 HZ £ CO-NO-'dc 1 INPUT DIRECT X CURRENTi BUFFER RESPONSE & FILTER J OUTPUT DRIVER SCALER ERROR AMPLIFIER ANALOG TO DIGITAL CONVERTER TO FIRING PUL SE GENERATOR COMMUTATING VOL TAGE CROSSOVER DETECTOR TO FPG -C6 To START j STOP FIGURE 5.1 MONITORING ANALOG QUANTITIES - BLOCK DIAGRAM where CTR^ and CTR 2 are the Current Tr a n s f e r R a t i o s of o p t o - i s o l a t o x s 1 and 2 r e s p e c t i v e l y . The n o n - l i n e a r i t i e s are e l i m i n a t e d by matching the photo-diode c u r r e n t s . 0-70 ADC DIFF. AMPLIFIER 3-POLE LOW-PASS, Fl LTER LINEARIZER 0--10YDC TO ERROR AMPLIFIER SEPARATE ISOLATED POWER SUPPLIES ON EITHER SIDE OF THIS LINE 0R0UND ISOLATION OCCURS HERE FIGURE 5.2 DIRECT CURRENT SENSOR - BLOCK DIAGRAM In t h i s a p p l i c a t i o n a 0.5 ohm r e s i s t a n c e i s l o c a t e d i n the DC l i n e to generate a vol t a g e which i s a p p l i e d to a d i f f e r e n t i a l a m p l i f i e r that provides impedance i s o l a t i o n between the power c i r c u i t and the DCS. The s i g n a l i s then f i l t e r e d i n a 3-pole low-pass 0.1 db Chebyshev f i l t e r w i t h f = 10 Hz. (See Se c t i o n 4.1). Since the cu r r e n t response s i g n a l 1^ i s used f o r slow speed c o n t r o l r a t h e r than f o r t r a n s i e n t c o n t r o l or fo r p r o t e c t i o n , a low c u t o f f frequency i s p e r m i s s i b l e . The v o l t a g e s i g -n a l i s converted to a c u r r e n t ^ s i g n a l to d r i v e the f i r s t o p t o - i s o l a t o r . T his o p t o - i s o l a t o r provides the ground i s o l a t i o n between the power c i r -c u i t and the c o n t r o l c i r c u i t . The s i g n a l i s then l i n e a r i z e d by us i n g a second o p t o - i s o l a t o r and f i n a l l y converted back to a s c a l e d v o l t a g e s i g -n a l . IOOKJI \ H'' 15 pf FIGURE 5.3 DIRECT CURRENT SENSOR & ERROR AMPLIFIER - SCHEMATIC 48. INPUT VOLTAGE V/N FIGURE 5.4 DIRECT CURRENT SENSOR - TRANSFER CHARACTERISTIC * 5 L FREQUENCY (Hz) FIGURE 5.5 DIRECT CURRENT SENSOR FREQUENCY RESPONSE Results The c i r c u i t was constructed on vectorboard and i s mounted on the re a r of the converter rack behind the mimic panel. Figure 5.3 shows the schematic diagram of the DCS and a l s o the e r r o r a m p l i f i e r to be discussed l a t e r . F i g ure 5.4 shows that the DCS i s l i n e a r w i t h i n 0.5% over the normal op e r a t i n g range. Figure 5.5 shows the frequency response of the DCS. The e r r o r a m p l i f i e r shown i n F i g . 5.3 provides the continuous current e r r o r to the ADC from the DCS output 1^ and the d e s i r e d c u r r e n t 1\Jq. I t i s a u n i t y gain summing a m p l i f i e r . A l l a p p r o p r i a t e p o i n t s i n the c i r c u i t are brought out to pins f o r p o s s i b l e breadboarding of s p e c i a l char-a c t e r i s t i c s i n t o the a m p l i f i e r . The a m p l i f i e r equation i s e o = K ( I d " I d o ) • ( 3 ' 5 ) - ^ " ^ o ( 5 - 2 ) 5.2 COMMUTATING VOLTAGE CROSSOVER DETECTOR (CVCD) As p r e v i o u s l y s t a t e d the Commutating Voltage Crossover Detector (CVCD) has two f u n c t i o n s : to generate "CONVERT COMMAND" pulses f o r the ADC and to generate t i m i n g pulses f o r the minimum f i r i n g angle l o g i c i n the F i r i n g P u l s e Generator. A simple block diagram i s shown i n F i g . 5.6 and the corresponding schematic i n F i g . 5.7. The c i r c u i t r y i s l o c a t e d on PCB 38. The o p e r a t i o n of t h i s c i r c u i t can best be explained w i t h reference to F i g . 5.8 which shows the r e l e v a n t waveforms and F i g . 5.6. Voltages from the p r e c i s i o n voltage d i v i d e r are compared to determine v o l t a g e crossover p o i n t s C^, C^. For example, the output of comparator AC becomes a l o g i c "1" or h i g h at ^ when V A > V £ and l o g i c "0" or low at C^ when V A < v c - Pulses of 50 . 30 JdAo-2.08 VAC 0 C o . COMPARATOR \MS > o OC; ) I M S OTHER TWO CO MR & MONOS ~°C. TO FPG '4 ' \MS CONVERT COMMAND' TO ADC FIGURE 5 .6 COMMUTATING VOLTAGE CROSSOVER DETECTOR BLOCK DIAGRAM FROM 0 C VOLTAGE BK1 Dl VI DER 0A BJt LM3II i k AV2 ^ 5 J a > - p H - | Mcesoi B2 MC8„dl Cx, • 0.047ul Txl-3'-30' R X 1 • I0KJI Cxi'330f>f TX2 ' U f l f c ALL COMPONENTS ON BOARD 38 Oj+^min "2 o3-\ Bl MCBSOI 0 AN2 r \ BC1 J>>—o c C^+ocmin AVI TO ADC FIGURE 5 . 7 COMMUTATING VOLTAGE CROSSOVER DETECTOR TYPICAL SCHEMATIC COMP AC VAN^VCN COMP CB COMP BA VCN^VBN 75 typ. C7 v C , + o c m / n to n ^ — CL UJ 5 1 o o 5: Qc Jl Jl J l Cj+octmin Jl Jl Jl i Jl Cc + oCmin Jl Jl JL ^ i n n r L n r L n j r i r ^ J U U I J U U L J U L ••CONVERT n r C0MM4/VD1IL 1 7.7 FIGURE 5 . 8 COMMUTATING VOLTAGE CROSSOVER DETECTOR - WAVEFORMS 52. predetermined width are generated by two monostables on the r i s i n g and f a l -l i n g edges of the comparator output. Cross-coupling of the monostables e l i m i n a t e s f a l s e t r i g g e r i n g due to no i s e or r i n g i n g on the comparator out-put. The pulsewidth represents the minimum angle « m ^ n a t which the SCR va l v e can be f i r e d . The monostables have a range of 150 us - 1.5 ms (3° -30°). This l i m i t represents the minimum v o l t a g e on an HVDC v a l v e to en-sure f i r i n g of a l l the SCR's i n the v a l v e . These pulsewidths are sent to the minimum f i r i n g angle l o g i c s e c t i o n of the F i r i n g P u l s e Generator. Outputs from a l l s i x monostables, C, + a , to C, + a , are r 1 mm 6 mm a l s o OR'd to produce a pulse t r a i n of frequency 6f which i s then fed to a t r a i l i n g edge monostable w i t h a pulsewidth about 1.1 ys. The r e s u l t a n t pulse t r a i n a t 6f Hz w i t h 1.1 ysec pulses i s the "CONVERT COMMAND" to the ADC. 5.3 ANALOG - TO - DIGITAL CONVERTER (ADC) The Analog - to - D i g i t a l Converter (ADC) d i g i t i z e s the curr e n t e r r o r so i t can be used i n the F i r i n g P ulse Generator to be discussed i n Chapter 6. Figure 5.1 shows how the ADC f i t s i n t o the analog c i r c u i t r y . As i n d i c a t e d i n F i g . 5.9, the sampling i n s t a n t of the curr e n t e r r o r i s about 0.5° a f t e r the commutating v o l t a g e zero c r o s s i n g and i s normally f a r from p o i n t s on the current vaveform where i r r e g u l a r i t i e s occur. Commutation of the DC to the next v a l v e u s u a l l y occurs at a = 15° - 20° f o r r e c t i f i c a -t i o n and a = 150° - 165° f o r i n v e r s i o n . A pulse t r a i n , C_^ , from the CVCD (discussed p r e v i o u s l y ) i n i t i a t e s the conversion process. The ADC i s an Analog Devices Model ADC-12Q w i t h the output 0 i n the 2's complement form of e Q. The MSB i n d i c a t e s e r r o r p o l a r i t y and b i t s 2-9 the d i g i t a l e r r o r . 53. I PHASE C CURRENT COMMUTATING VOL TAGE i — — CONVERT COMMAND —1.1 US ADC STATUS CONVERSION 25us |\ PRR/PAC INPUT 1.5us+ 1 oc =Q . ss 25,us i 1 =0° ^0.5° 15C '-20° FIGURE 5.9 ANALOG TO DIGITAL CONVERTER - TIMING DIAGRAM This chapter has described the c i r c u i t s used to measure the DC l i n e c u r r e n t , to determine the c u r r e n t e r r o r , to determine the commutating v o l t a g e crossover t i m i n g pulses and to d i g i t i z e the c u r r e n t e r r o r . Block diagrams, c i r c u i t schematics and r e s u l t s have a l s o been presented. 54. 6. DESIGN AND EXPERIMENTAL RESULTS FOR THE EQUIDISTANT FIRING CIRCUIT T h i s c h a p t e r d e s c r i b e s i n d e t a i l the e q u i d i s t a n t f i r i n g c i r c u i t as o u t l i n e d i n S e c t i o n 3.2. S i g n a l s from the c i r c u i t s d e s c r i b e d i n Chapt-e r s 4 and 5 a r e used i n t h i s e q u i d i s t a n t f i r i n g c o n t r o l l e r t o v a r y the f i r i n g i n s t a n t s u b j e c t t o c e r t a i n c o n s t r a i n t s . F i g u r e 6.1 p r o v i d e s a simp-l e b l o c k diagram o f the c i r c u i t r y . The f i r i n g a n g l e e r r o r can come from t h r e e s e p a r a t e s o u r c e s . The C o n t r o l Mode L o g i c s e l e c t s the p r o p e r s o u r c e and r o u t e s the e r r o r t o the r e l e v a n t r e g i s t e r i n the main c i r c u i t o f the F i r i n g P u l s e G e n e r a t o r . The main c i r c u i t which i n e s s e n c e i s the e q u i -d i s t a n t c o n t r o l l e r d e t e r m i n e s the new f i r i n g i n s t a n t . The decoder r o u t e s the f i r i n g i n s t a n t p u l s e t o the c o r r e c t v a l v e and the minimum f i r i n g a n g l e l o g i c e n s u r e s t h e r e i s s u f f i c i e n t v o l t a g e a c r o s s the v a l v e p r i o r t o f i r i n g . The SCR Gate D r i v e s c o n v e r t the f i r i n g i n s t a n t p u l s e i n the c o n t r o l t o a gate p u l s e on the power SCR. The f o l l o w i n g s e c t i o n s p r o v i d e more d e t a i l f o r the i n d i v i d u a l c i r c u i t s . The t h e o r y u n d e r l y i n g t h e s e c i r c u i t s can be found i n Chapter 2. 6.1 CONTROL MODE LOGIC (CML) As mentioned above the C o n t r o l Mode L o g i c (CML) r o u t e s the c o n t r o l e r r o r t o one o f two r e g i s t e r s i n the F i r i n g P u l s e G e n e r a t o r (FPG) main c i r -c u i t . A n e g a t i v e e r r o r (0 < 0) r e q u i r e s the f i r i n g i n s t a n t t o be s o o n e r , t h a t i s , t h e f i r i n g a n g l e a i s to be d e c r e a s e d . C o n s e q u e n t l y the e r r o r i s r o u t e d t o the Phase R e d u c t i o n R e g i s t e r (PRR). A p o s i t i v e e r r o r (0 > 0 ) , s i m i l a r l y , i s r o u t e d t o the Phase Advance Counter (PAC) to i n c r e a s e a. F o r z e r o e r r o r ( 0 = 0 ) a z e r o e r r o r s i g n a l i s a p p l i e d t o b o t h the PRR and PAC. A non-zero e r r o r can o n l y be i n one r e g i s t e r a t any ti m e . 55. O i—. CD O -J CONTROL STATUS c£>| SIGNALS UJ oc Uj O o CO Uj — i o Uj K , o o ct Ul CL 5: o o o ct < : o o C2 CONTROL MODE LOGIC BD 16 ^ FIRING )>PUL SE GENERATOR BD 36 Cj-C6 MINIMUM FIRING ANGLE LOGIC SCR GATE DRI VES BD 17,18 BRIDGE FIGURE 6.1 GENERATION OF VALVE FIRING PULSES - BLOCK DIAGRAM As p r e s e n t l y constructed, 0 can come from three sources: the ADC, the i n v e r t e r c o n t r o l c i r c u i t s or the computer c o n t r o l c i r c u i t s . Table 6.1 i n d i c a t e s the r o u t i n g of 0 f o r d i f f e r e n t c o n t r o l modes and p o l a r i t i e s . At t h i s time the i n v e r t e r c o n t r o l c i r c u i t s and the computer c i r c u i t s have not been connected i n t o the c o n t r o l . Consequently the s t a t u s s i g n a l s from these c i r c u i t s have been connected to switches to a l l o w t e s t i n g of the CML and the e r r o r inputs have been connected to ground or supply as a p p r o p r i -ate. Using Boolean algebra the equations f o r e n a b l i n g the two r e g i s -t e r s can be w r i t t e n from Table 6.1 as f o l l o w s : (Enable the PRR) = (PRR = 1) = ADC • CP • CC1 • CC + ADC • CP • CC1 • OWCC + ISC • CP + PRRC (6.1) (Enable the PAC) = (PAC = 1) = ADC • CP • CC1 • CC + IOC ' CP + PACC (6.2) The above two equations determine which r e g i s t e r i s to c o n t a i n the non-zero 0 and now we must choose the ap p r o p r i a t e source. Table 6.2 i n d i c a t e s the b i n a r y code on the c o n t r o l l i n e s A and B to s e l e c t the ap-p r o p r i a t e e r r o r source. The PRR r e q u i r e s an inp u t corresponding to 0 = 0. P u t t i n g a l l 8 e r r o r b i t s to "1" on channel C3 meets t h i s requirement. The equations f o r the channel s e l e c t o r s can be w r i t t e n from Table 6.2 and equations (6.1) and (6.2). Phase Reduction R e g i s t e r CO = ADC • CP • CC1 • CC + ADC ' CP • CC1 • OWCC C l = ISC • CP C2 = PRRC 57. C3 = PRR = A l l Inputs "1" . (2's complement negative zero) *. A l = ISC • CP + PRR = ISC • CP • PRR (6.3) .". B l = PRRC + PRR = PRRC * PRR (6.4) Phase Advance Counter CO = ADC • CP • CC11- CC Cl = IOC • CP C2 = PACC C3 = PAC = A l l inputs "0" (2's complement p o s i t i v e zero) A2 = IOC ' CP + PAC = IOC • CP • PAC (6.5) B2 = PACC + PAC = PACC • PAC (6.6) Implementing (6.1) and (6.2) gives: PRR = ADC • CP • CC1 • CC • ADC • CP • CC1 • OWCC • ISC • CP • PRCC (6.7) PAC = ADC ' CP ' CC1 * CC • IOC ' CP * PACC (6.8) Figure 6.2 i s the schematic showing the implementation of the above equa-tions and Fig. 6.3 i s a block diagram showing the control error routing. The CML routes the error into the appropriate regi s t e r i n the main c i r c u i t of the FPG which i s discussed next. 6.2 FIRING PULSE GENERATOR (FPG) As mentioned at the begining of th i s chapter, the F i r i n g Pulse Generator (FPG) generates the f i r i n g pulses to f i r e the valves. The main c i r c u i t implements equation (2.1), the decoder determines the next valve to f i r e and the minimum f i r i n g angle l o g i c implements equation (2.6). The following sections describe the three sections. TABLE 6.1 ROUTING OF CONTROL ERROR ERROR SOURCE & CONTROL MODE STATUS SIGNALS REGISTER PRR (0 < 0) PAC (0 > 0) ADC R e c t i f i e r Current C o n t r o l (CC = 1) CC1 = 1 CC1 = 0 X X I n v e r t e r One Way Current C o n t r o l OWCC = 1 X I n v e r t e r MEA Co n t r o l ISC = 1 IOC = 1 X X Computer C o n t r o l (CP = 1) PRCC = 1 PACC = 1 X X ADC = I i s a 1.5 ys pulse a f t e r ADC conversion i s complete. TABLE 6.2 DATA CHANNEL SELECTOR CODING FOR ROUTING OF CONTROL ERROR CHANNEL SELECTOR (MC8309) ERROR SOURCE CHANNEL CHANNEL SELECTOR INPUTS PRR (0 < 0) PAC (0 > 0) A B CO 0 0 ADC ADC C l 1 0 ISC IOC C2 0 1 COMPUTER COMPUTER C3 1 1 0 = 0 ' 0 = 0 (ALL BITS=1) (ALL BITS=0) PRRC +~S01 ABJ ENABLE OWCC AEJ_ PRRC OWCC ADC AD1 STATUS °~ AA1 ADC MSBO MONO A' SN74123 PW=t.Susec ADC CC] RECTIFIER CURRENT CONTROL AH1 CC RECT. M UlNV. COMPUTER HAN+—v CONTROL COMP X ISC +-*S>s ENABLE AF1 CP —O : AK1_ ISC IOC +-S08 ENABLE AJ1 PACC +-<J2 A y ENABLE £ IOC PACC :77> ~7Py><>Ai "^TTy^B AD2 —O PRR ENABLE PRR & PAC AF2 —O PAC FIGURE 6.2 CONTROL MODE LOGIC - SCHEMATIC 'ENABLE EO P R R PRR El SSI Cj 5 o U J Q O o o o o < Al-Bl A2-B2 • A J DATA CHANNEL SELECTOR B J E11,E12,E13,EU ALL INPUTS HIGH ALL INPUTS LOW C2 C2 CO Cl J ISC REGISTER =» ADC 3 COMPUTER => IOC REGISTER it. CO \\C1 A2 DATA CHANNEL SELECTOR B2 E6,E7/E8/E9 ENABLE PAC ALL COMPONENTS ON BD 16 FIGURE 6.3 CONTROL ERROR ROUTING - BLOCK DIAGRAM 62. FROM CML FROM START MONO FROM CML MODULO 6 RING COUNTER DECODER Q FF /? Q MS Q f7 TO 6/A7"E DRIVES 1 .... 5 FIGURE 6.4 FIRING PULSE GENERATOR BLOCK DIAGRAM 63. Main C i r c u i t The main c i r c u i t implements the e q u i d i s t a n t f i r i n g according t o : p ± = f ± - 1 + 60° ± 0 ± (2.1) For 6^ - = 0, i . e . no c o n t r o l e r r o r , t h i s c i r c u i t w i l l ensure that a l l sub-sequent f i r i n g s are 60° apart. The o p e r a t i o n of the c i r c u i t can be ex-p l a i n e d by r e f e r r i n g to F i g . 6.4. Assume that 8^ . = 0 and that both PRR and PAC c o n t a i n zero e r r o r s i . e . , CPRR = 1111 1111 and CPAC = 0000 000 r e s p e c t i v e l y . Thus the decod-ed output of PAC which i s a down counter i s high to G2 a l l o w i n g the C out-put to go d i r e c t l y to the decoder. At i n s t a n t f ^ _ ^ a number corresponding to 60° i s loaded i n t o D an up-counter and i s then counted to 0° by f the c o n t r o l frequency from the PLL (see s e c t i o n 4.4). The comparator C output goes high when the number i n D i s grea t e r than or equal to the c o n t r o l e r r o r contained i n PRR, i . e . , C = 1 = (D >_ CPRR) (6.9) C i n h i b i t s f u r t h e r counting of D. Since 6^ = 0, C goes h i g h 60° a f t e r ^ i 1 a i K* 3 ^ S s e n t t o t n e d e c Q ( i e r ' The process i s repeated when D i s reloaded a f t e r f occurs. The b i n a r y number for. 60° i s generated as f o l l o w s . Since f = 480 * f , (3.4) c 480 * f i t takes -fr. .—-r * 60 = 80 pulses of f to count 60 . Since the D out-360 * f v c put must equal CPRR = 1111 1111 a f t e r 80 pulses f o r 9 = 0 , the number 1010 1111 i s loaded i n t o D at each f , . i . e . , 1010 1111 loaded number + 0101 0000 80 =60° 1111 1111 CPRR negative zero I f the feedback d i v i d e r of the PLL i s changed, then the number loaded i n t o D must be reprogrammed a c c o r d i n g l y . D i s loaded on the i n i t i a l s t a r t by . a pulse from the S t a r t Monostable s i n c e f ^ ^ pulses are not a v a i l a b l e . Assume now that 8^ < 0 meaning that the f i r i n g should be sooner (smaller a ) . The PRR contains the c o n t r o l e r r o r 8^. The PAC contains zero and G2 i s enabled to a l l o w the C output to go d i r e c t l y to the decoder as above. At ^ s t a r t s to count up. However, PRR contains a b i n a r y number s m a l l e r than before so the C output goes high sooner by the amount of time the f i r i n g i s to be sooner. As b e f o r e , the output goes d i r e c t l y to the decoder and stops D counting. Assume now that 0^ > 0 meaning that the f i r i n g should be delayed (higher a ) . The PRR contains zero and the PAC contains 0^. G2 i s not enabled s i n c e CPAC ^ 0. As f o r the case of 8^ = 0, D i s up-counted u n t i l i t s output i s the same as the contents of PRR (CPRR = 1111 1111). This takes a p e r i o d of 60°. C now goes hig h stopping the counting of D, enabl-i n g G2 so the PAC output can go to the decoder and e n a b l i n g G l to s t a r t the down-counting of PAC. When the PAC output i s zero, the decoder r e c e i v e s a h i g h output from G2. The main c i r c u i t of the FPG generates a s e t of s e r i a l pulses corresponding to the d e s i r e d f i r i n g i n s t a n t s which are then decoded to determine which of the s i x valves i s to be f i r e d . Normally a r e c t i f i e r i s run at a = 15° - 20° and an i n v e r t e r at a = 150° - 165° which means that D i s p a r t i a l l y up-counted when the new e r r o r i s entered i n t o PRR and PAC. Since 8. i s entered about C. + 0.5° i I and f o r normal r e c t i f i c a t i o n f i r i n g i s not permitted u n t i l C^ + which i s 5° - 10° l a t e r there i s no problem. I f f i r i n g i s at say a = 60° - 70° or 120° - 130°, the current may see the commutation d i s c o n t i n u i t i e s but 65. these would be f i l t e r e d out i n the low-pass f i l t e r of the DCS described i n Sec t i o n 5.1. Decoder From the set of s e r i a l pulses from the main c i r c u i t , the decoder s e c t i o n determines which va l v e i s to be f i r e d . R e f e r r i n g to F i g . 6.4, the decoder s e c t i o n c o n s i s t s of a counter and a decoder. The module - 6 r i n g counter [16] c o n s i s t s of three J-K F l i p - F l o p s and t h e i r outputs are de-coded to give pulses which i n tu r n are NANDed w i t h G2 output to produce negative going pulses q_^  f o r the minimum f i r i n g angle l o g i c . The f a l l i n g edge of the pulse i s determined by the decoded output of the r i n g counter ( i . e . , p ^). The r i s i n g edge of the pulse i s determined by the minimum f i r i n g angle l o g i c . Minimum F i r i n g Angle L o g i c The minimum f i r i n g angle l o g i c ensures that there i s s u f f i c i e n t p o s i t i v e v o l t a g e across the v a l v e p r i o r to f i r i n g . Normal AC v o l t a g e s are assumed. Although the l o g i c i s u s e f u l during r e c t i f i c a t i o n i t does not i n t e r f e r e w i t h i n v e r t e r c o n t r o l so i s not i n h i b i t e d f o r t h a t mode of oper-a t i o n . This c i r c u i t implements the f o l l o w i n g equation f , = p = f + 60° ± 6. i f p > C. + a , (2.6) i i i - 1 i i — x min = C. + a . p. < C. + a . i min i l min Consider f i r s t the normal o p e r a t i o n of t h i s c i r c u i t i n d i c a t e d by the f i r s t l i n e of equation (2.6). R e f e r r i n g to F i g . 6.4, the C^ + a m ^ n s i g n a l from the CVCD discussed i n S e c t i o n 5.2 i s a p p l i e d to a monostable which se t s the F l i p - F l o p and d r i v e s one i n p u t of the NOR low. The NOR R^ output remains low. The monostable i s used to get a sh o r t d u r a t i o n p u l s e . 66. Normally the f i r i n g i n s t a n t i s a f t e r a ^ and when ( f i r i n g i n s t a n t from the decoder f o r the c o r r e c t valve) a r r i v e s , i t d r i v e s h i g h . This a l s o causes f ^ ^  to go h i g h and r e l o a d the up-counter D to s t a r t c a l c u l a t i o n of the next f i r i n g i n s t a n t . The C output goes low, G2 goes low and the q^ ret u r n s to the h i g h s t a t e which r e t u r n s R_^  to the low s t a t e . Consequently a short pulse R^ (pulse width equals the sum of the propagation delays i n the FPG) i s a p p l i e d to the f i r i n g p ulse monostable to g i v e two outputs. The f i r s t output i s the f i r i n g pulse to the Gate D r i v e C i r c u i t and the second output r e s e t s the FF. The pulse width has been f i x e d at about 100° to o b t a i n a h a r d - d r i v e gate pulse. Consider the second l i n e of equation (2.6) where the c a l c u l a t e d f i r i n g i n s t a n t i s sooner than i t should be. On an HVDC system t h i s can occur w h i l e the converter transformer i s undergoing a tap change or during a system disturbance. S i g n a l q^ becomes low at the c a l c u l a t e d f i r i n g i n -s t a n t but the NOR output R^ remains low u n t i l i t r e c e i v e s a low output from the FF at C. + a . . The r e s t of the sequence i s i d e n t i c a l to that i mm above. Thus the F i r i n g Pulse Generator uses the d i g i t a l e r r o r given by the CML to produce e q u i d i s t a n t f i r i n g s i g n a l s f o r the SCR Gate D r i v e s . The FPG b a s i c a l l y works but t e s t i n g w i t h a running converter can not be done as explained i n the next s e c t i o n . 6.3 SCR VALVE GATE DRIVES As mentioned i n S e c t i o n 3.2, the Gate Drives convert the f i r i n g s i g n a l s from the minimum f i r i n g angle l o g i c i n the FPG i n t o f i r i n g pulses f o r the gates of the SCR's i n the converter b r i d g e . Ground i s o l a t i o n i s achieved i n these c i r c u i t s . The Gate D r i v e c i r c u i t i s based on references [17] and [18]. 67. + 5V fi-C IKJi 2N3053 MCS-2 l_ '720* 1 39KSI BD 17, 18 SKSL 2KSL 47si ^ 0.022 8.2V HE A T SINK 1 C35S VECTOR BOARD FIGURE 6.5 TYPICAL SCR GATE DRIVE CIRCUIT R e f e r r i n g to F i g . 6.5, the f i r i n g p u l s e from the FPG d r i v e s the LED o f an opto-SCR which d i s c h a r g e s the energy s t o r e d i n the c a p a c i t o r i n -to the gate of the power SCR. The opto-SCR p r o v i d e s 1500 v o l t s ground i s o l a t i o n between t h e c o n t r o l and power c i r c u i t s . The r e s i s t o r d i v i d e r p r o t e c t s the 200 V o l t opto-SCR from the normal 30 208 VAC and a l s o d e t e r -mines the c a p a c i t o r charging- r a t e . The 47 ohm r e s i s t o r and the. z e n e r d i o d e p r o t e c t the power SCR gate from o v e r c u r r e n t and o v e r v o l t a g e r e s p e c t -i v e l y . The c i r c u i t was breadboarded i n a s i n g l e SCR c i r c u i t and work-ed w e l l f o r v a r y i n g f i r i n g a n g l e s and AC v o l t a g e s . A t h r e e phase b r i d g e was c o n s t r u c t e d f o r t h e c o n v e r t e r and i n s e r t e d i n t o the c l o s e d l o o p s y s -tem. However, the system d i d n o t work i n c l o s e d - l o o p c o n f i g u r a t i o n . The problem appears t o be i n the Gate D r i v e s s i n c e the s i x f i r i n g p u l s e s have 68. l i t t l e or no resemblance to each other nor to the expected waveshape. There were no obvious c o n s t r u c t i o n or design e r r o r s . Although the FPG was not completely debugged and trimmed i n , i t di d produce f i r i n g pulses that should have s t a r t e d the r e c t i f i e r . A number of items could be i n v e s t i g a t e d on the Gate D r i v e s . The use of a short but high current f i r i n g p u l s e , say 10 - 25 ysec w i t h 100 - 500 mA, could r e -place the present 4.6 msec, 30 mA LED p u l s e . The opto-SCR could be moved c l o s e r to the gate to minimize the d i s t a n c e the gate p u l s e must t r a v e l . The use of a pulse transformer could be t r i e d . For the use of an opto-SCR, i t may be necessary to match gate d r i v e c h a r a c t e r i s t i c s f o r each power SCR. This chapter has described the c i r c u i t s a s s o c i a t e d w i t h the Con-t r o l Mode Lo g i c (CML) which routes 'the e r r o r s i g n a l i n t o the F i r i n g Pulse Generator (FPG) so that a f i r i n g pulse 1 can be sent to the Gate D r i v e s . Block and schematic diagrams f o r the CML, the FPG and the Gate Drives have been presented. The Gate D r i v e c i r c u i t was described and s e v e r a l ideas f o r m o d i f i c a t i o n were presented to make the c i r c u i t work p r o p e r l y . 7. CONCLUSIONS AND RECOMMENDATIONS This t h e s i s has described a p h y s i c a l HVDC converter model. The design and c o n s t r u c t i o n of a 6 - pulse HVDC converter rack compatible w i t h the e x i s t i n g micro-machine AC system model has been o u t l i n e d . The theory and design of a d i g i t a l e q u i d i s t a n t c o n t r o l system f o r the convertor has been presented. The c o n s t r u c t i o n and t e s t r e s u l t s of a r e c t i f i e r c o n t r o l system has a l s o been described. Some of the f e a t u r e s of t h i s system f o l l o w . The phase-locked loop used i n t h i s c o n t r o l generates a r e l i a b l e and accurate c o n t r o l frequency. Since the phase-locked loop t r a c k s the AC system frequency over a wide range and f o r l a r g e step changes r a t h e r than depending on the AC v o l t a g e waveform, the c o n t r o l i s i n s e n s i t i v e to normal AC asymmetry and d i s t o r t i o n . This allows the converter to be con-nected to weak AC systems. A h i g h phase-locked loop frequency ensures accurate f i r i n g down to ±0.75°. A c i r c u i t to provide a l i n e a r ground i s o l a t e d s i g n a l has been constructed to measure DC l i n e c u r r e n t . The simple e r r o r a m p l i f i e r can . e a s i l y accommodate m o d i f i c a t i o n s f o r experimental work. The analog f r o n t end of the c o n t r o l p r e s e n t l y allows r e c t i f i e r c u r r e n t c o n t r o l but other c o n t r o l parameters can e a s i l y be implemented. The converter rack i t s e l f has breadboarding f a c i l i t i e s and a mimic panel to a l l o w simple t e s t con-n e c t i o n s . The f i r i n g c i r c u i t has been c o n s t r u c t e d to a l l o w a maximum expansion f l e x i b i l i t y . The c o n t r o l l o g i c can accept s i g n a l s from f u t u r e i n v e r t e r c o n t r o l or computer c o n t r o l c i r c u i t s . The SCR gate d r i v e s should be m o d i f i e d . P o s s i b l e m o d i f i c a t i o n s i n c l u d e u s i n g a short d u r a t i o n h i g h current pulse to t u r n on the opto - SCR, u s i n g another make of opto - SCR, matching i n d i v i d u a l gate c h a r a c t e r i s t i c s f o r each power SCR and us i n g p u l s e transformers. The converter rack can then be used as p a r t of a model HVDC l i n k . I n v e r t e r c o n t r o l c i r c u i t s have to be added i n order to o b t a i n a tru e b i d i -r e c t i o n a l converter. Depending on requirements, a l l or p a r t of the conver-t e r could be d u p l i c a t e d to make an e q u i d i s t a n t HVDC c o n t r o l system. The converter could then be connected to a higher l e v e l system c o n t r o l l e r which has been designated as computer c o n t r o l . The higher l e v e l c o n t r o l l e r could replace some of the e x i s t i n g c o n t r o l or could supplement i t . The model could then be used to study HVDC system c o n t r o l , v o l t a g e c o n t r o l and AC/ DC i n t e r a c t i o n s . 71. BIBLIOGRAPHY [I] E.W. Kimbark, " D i r e c t Current Transmission, Volume 1" John Wiley & Sons, Toronto, 1971. [2] C C . Tam "General Survey of HVDC P r o j e c t s " , D i r e c t Current, V o l . 1 No. 4, pp. 128-132, May" 1970. [3] M. Morgan, "DC Conversion: R e b i r t h of the Mercury V a l v e " , E l e c t r i c L i g h t and Power, February 1975. [4] A. G a v r i l o v i c , "Basic Facts of AC/DC Conversion", E l e c t r i c a l Review, pp. 296-300, 25 February 1966. [5] C. Adamson, N. Hi n g o r a n i , "High Voltage D i r e c t Current Power Trans- m i s s i o n " , Garraway, 1960. [6] M.Z. Tarnawecky, "HVDC Transmission C o n t r o l Schemes", Manitoba Power Conference EHV-DC, Winnipeg, Manitoba, Canada, June 7 - 10, 1971. [7] A. Ekstrbm, G. L i s s , "A Refined HVDC C o n t r o l System", IEEE Trans. Pwr. App. and Syst, V o l . PAS-89, No. 5/6, May/June 1970. [8] J.D. Ainsworth, "The Phase-Locked O s c i l l a t o r - A New C o n t r o l System f o r C o n t r o l l e d S t a t i c Converters", IEEE Trans. Pwr. App. and Syst., V o l . PAS-87, No. 3, pp. 859-865, March 1968. [9] R.I.D. Riches, "A Model HVDC L i n k " , M.A.Sc. T h e s i s , U n i v e r s i t y of B r i t i s h Columbia, A p r i l 1974. [10] J . A r r i l l a g a , G. Galanos, " T h e o r e t i c a l B a s i s of a D i g i t a l Method of Gr i d C o n t r o l f o r HVDC Converters", IEEE Trans. Pwr. App. and Syst., V o l . PAS-89, No. 8, pp. 2049-2055, Nov./Dec. 1970. [ I I ] J . A r r i l l a g a , G. Galanos, E.T. Powner, " D i r e c t D i g i t a l C o n t r o l of HVDC Converters", IEEE Trans. Pwr. App. and Syst. V o l . PAS-89, No. 8, pp 2056-2065, Nov./Dec. 1970. [12] R.R. Shepard, " A c t i v e F i l t e r s : Short cuts to network design", E l e c t r o n i c s , pp. 77-82, McGraw-Hill, 18 August, 1969. [13] Phase-Locked Loop Systems, Motorola Semiconductor Products I n c . , 2nd E d i t i o n , August 1973. [14] S. H a r r i s , " L i n e a r Photodiode O p t o - i s o l a t o r C i r c u i t s " , Monsanto Commercial Products Co., A p p l i c a t i o n Note AN505, October 1972. [15] G. McConnell, Personal conversations. [16] D.L. Steinbach, " D i g i t a l Instruments P a r t 2 Counting and Decoding C i r c u i t s " , E l e c t r o n i c s World, pp. 47-72, McGraw-Hill, August 1970. 72. [17] Monsanto GaAs L i t e Tips Volume 2 pp.6, Monsanto E l e c t r o n i c S p e c i a l Products, 1970. [18] SCR Manual, 4th E d i t i o n , pp, 295, General E l e c t r i c Co., 1967. •APPENDIX A FUNCTION DIAGRAMS FOR INTEGRATED CIRCUITS FAIRCHILD SEMICONDUCTOR / 780. v I N O ~ - L c , -0 . 3 3 |iF | : A 7 G X X u A 7 b . U X X -Ov0 •Although no output capacitor is needed (or stability, it does improve tran-sient response. -Required IF regulator is located an appreciable distance from power supply filter. Basic Fixed Output Regulator 9N0G/5400 , 7400 9308 77] 23] n^ l fT:l fTcl [771 (Til JTFj HT] [77] 177! [71] J L , lul  1. ,[.|lULr^TJ.X-, Lf II.'.I, .i^ H IHJJI. I.i). Ii.lnp. U 3 O3 Oa 0 2 Q| 0| Qo OCE «E"C °0 O, O, D 2 0 ? D 5 0 3 trELnirEnini^  9324 1 i A>8 A=0 A 0 A| A 2 A3 A« E A<B So s l fl2 8 3 B 1 ! 1 C-'iD 9366/54193, 74193 j"cc rl 1 1 k P A MR TCp TCu PL P ? 0 9 Oj CPD C U °C "D I" GNO 1 U U U L I J L J J U J EXAR INTEGRATED SYSTEMS INC. XF\- 2 2 0 ! 3 2 0 H I G H C U R E N T L O G I C O U T P U T ED R P71 F l R m F L LU Ld LiJ bJ LU LU LU C U R R E N T C U R R E N T S O U R C E S O U R C E I N P U T O U T P U T SET 1 S E T 2 R E S E T ( L E A D I N G ( T R A I L I N G E D G E ) E D G E I MONSANTO' MCS-2 PACKAGE DIMENSIONS C 3 5 9 MOTOROLA SEMICONDUCTOR PRODUCTS (Numbers i n parenthesis i n d i c a t e s l o a d i n g w i t h other devices i n same MC fa m i l y ) MC3000/MC3100 Quad 2-lnput NAND Gate MC3001/MC3101 Quad 2-lnput AND Gate ' p d - 6 .0 ns I V P P D = 0 8 m W l y p . - ' p k g t p 3 = 9 . 0 ns IVP P r j = 112 m W IvP'P^g MC3002/iV)C3102 Quad 2-lnput NOR Gate *pd = 6.o n s lv p P Q - 1 2 2 m W t y p / p k y MC3003/MC3123 Quad 2-lnput OR Gate MC3004/MC3104 Quad 2-lnput NAND Gate (Open Collector) MC3005/MC3105 Triple 3-lnput NAND Gate (ll 1 (D 2 (ll a <i) 5 (1) 9 (11 10 (11 12 (1) 1 3 - 3 (10 ) - - 6 (10) - 8 (10 ) - 1 1 ( 1 0 ) 8 (10 ) (1) 9 ( I I 1 0 ( 1 ) 1 1 t p d - 9 . 0 ns r y p P D * 1 5 0 m W i v p / p k g l p c J = 8 . 0 ns t y p P D = 8 8 m W t y p / p V g t p d = 6 . 0 ns t y p P D = 6 6 n-.W t y p / p k n MC3006/MC3106 Triple 3-lnput AND Gate MC3C07/MC3107 Triple 3-lnput NAND Gate (Open Collector) MC3010/MC3110 Dual 4-lnput NAND Gate (i) l -(1) 2 -(1) 1 3 -(II 3 (11 1 (1) 5 (1) 9 -(1) 1 0 -(1) 11 -1 2 ( 1 0 ) 6 (10 ) 8 (10) (1) 1 — 1 _ (1) 2 — i (11 4—' (11 5 — r (11 9 L (1) 10-T (1) 12—• (11 1 3 — r 12 » 1 . 2 « 1 3 P D - 8 4 m W t y p / p k g 12 - 1 • 2 • 13 tpd * 8 . 0 ns t y p P D = 6 6 m W t y p / p k g = 6 . 0 ns t y p -- 4 4 m W t y p / p k g MOTOROLA (cont'd) MC401S/MC4316 Programmable Modulo-N Decac'3 Counter MC4018/MC4318 Programmable ModuJo-N Hexridecirnal Counter Gate QO 0 , (8) Clock O l 0 9 (81 CO p I Q2 015 (0) V C C " P2 Q3 O l (8) Gnd P3 P E Pi 013 MH B 012 tpd- Clock to Q3 « 50 ns typ Clock to Buss = 35 ns typ PQ - 250 mW typ/pkg C O U N T h ~ . MC4023 4-Bit Universal Counter (2) 2 0 c CO CO (2! 13 0 « C l (21 1 O c C2 QI (1) 12 O c J3 (3) 3 0 c RO (3) 10 0 c n i (3) 4 0 c R2 (3) 11 0 c R3 Q3 V c c = Pin 14 Gnd = Pin 7 l pd = 16 ns typ/bit P Q = 200 mW typ/pkg f =• 30 MHz typ MC4015 Quad Type D Flip-Flop (8) H 3 0-(2) S1 5 0 -<1) D1 1 o -! pd = 1 6 n s *YP P D « 190 mW typ/pkg 3 l«io»ni clock pulw MC4024/MC4324 Dual Voltage-Controlled Multivibrator t ! l V C C : V C M =1,13 Output Euffer = 14 Gnd: V C M » 5, 9 Output Ouffer = 7 External Capacitor for Frequency Range Determination P Q » 150 mW typ/pkg f » 30 MHz typ MC4044/MC4344 Phase-Frequency Detector Amplifier UO) Output VQC " P I N 1 4 Gnd = Pin 7 l p d < MOTOROLA (cont'd) MCS40O/MC74O0 Quod 2-lnput N A N D Gato tpd - 10 ns typ P D = 40 mW typ/pkg MC5401/MC7401 Ouad 2-lnput N A N D Gam (Open Collector Output) tpd = 35 ns tvP P Q = 40 mW typ/pkg MCS402/MC7402 Quad 2-lnput NOR Gate 4 151 (101 13 [14| (101 tpd - 10 ns typ P Q = 40 mW typ/pkg MC5403/MC7403 Quad 2-lnput N A N D Gate (Open Collector Output} MC5410/MC7410 Triple 3-lnput N A N D Gato MC5420/MC7420 Dual 4 Input N A N D Gate (II (II . - , -(II (14] 13 (1) (1) (1) (II 10 (1) [10 (1) [12 12 131 (101 G [51 1101 8 [131 (101 [11 1 121 2-v_Z] V i 3 i y-141 s — r - 1  —I  1   [1 1 4 [14] 5 [61 9 17) 10 [8] 12 [9) 13 6 121 (101 8 110) (10) ipd * 3 5 n s typ P D •= 40 mW typ/pkg 'pd " 10n« typ Pn ' 30 mW typ/pkg tpd " 10 nt typ P D - 20 mW typ/pkg MC5404/MC7404 MC5405/MC7' ;S Hex Inverter Hex Inverter (Open Collector) (1l[ 1 1 1-J^ >o—2 [141(10) (1) 1 £ ^ > 0 — 2 (101 (D[ 3 1 3 - £ > o - 4 [ 2 1(10) C.) 3 P>o—4 (10) ( D l 5 1 5 - £ > < > - 6 1 6 1(10) (1) 5 J^>0—6 (10) (1)[ 7 1 9-J^>0-8 [ 8 1(10) (11 9 8 l 1 0 > (1)[9 l 11—|^>o-10(10)(10) (1) |\>o—10 (10) (1)1131 13—J^>°-12[ 121 (10) (1) 1 3 | ^ o — 1 2 (10) 2 8 1 t p d ° 1 3 n i typ 2 - 1 tpd c 35 ns typ Pp - 60 mW typ/pkg » D = 60 mW typ/pkg MC747G Dual J K Flip-Flop (2) Set 2 (II J 4 (2) Clock 1 (1) K 16 Rosot 3 Set 7 J 9 lock 6 K 12 ©set 8 J S o C K R 5 — T C K R Q 1 = 15 M H z = 80 mW typ/pkg 16 P i n P a c k a g e V c c = P i n 5, G N D = P i n 13 MOTOROLA (cont'd) MC5493/MC7493 4-Bit Binary Counter ( 2 ) 1 4 0 c C O Q O 1 2 ( 1 0 ) ( 2 ) 1 O c C 1 Q 1 9 ( 1 0 ) V c c - f i " 5 Q 2 8 ( 1 0 ) G n d " P i n 1 0 0 3 1 1 ( 1 0 ) R O (1) 2 (1) 3 t p d = 2 0 n s t y p / b i t P D - 1 6 0 m W t y p / p k g MC8309/MC9309' Dual 4-Channcl Data Selector (1) 1 0 O -( 1 ) 9 O -A z X O X I X 2 X 3 z )15 (10) ( 1 ) 4 C V -I I I s o -il) 6 O -( 1 ) 7 0 -A W — < M ( 1 0 ) B Y O v C c - P i n 1 6 Y 1 G n d = P i n 8 Y 2 Y 3 W — 0 2 ( 9 ) MC8601/MC9601 Retriggerable Monostabie Multivibrator V C C H R I N 1 4 G n d = P i n 7 ( 1 ) B l 1 ( 1 ) 8 2 2 ( 1 ) A 1 3 0 1 1 ) A 2 4 o-or T l T 2 Q > S O ( 6 . 8 ' ) ' p d p D • 2 5 ns typ ; 7 5 mW typ/pkg M C 9 6 0 1 . M C 8 6 0 1 Z - A B X O + A B X 1 • A B X 2 * A B X 3 Z - A B X O + A B X 1 + A B X 2 + A B X 3 W = A B Y O -» A 8 Y 1 + A B Y 2 -t A B Y 3 A V - A B Y O + A B Y 1 + A B Y 2 < A B Y 3 t p d « 9 . 0 t o 24 ns t y p P Q = 1 5 0 m W t y p / p k g NATIONAL SEMICONDUCTOR CORP. t* In | II In I ti 11 ra ' P I * I * ! • |> can DM70007DM8G00 (SNS400/SIN7400) Quad 2-lnput Gate 9 3 . |> |> |. |> T-CUD DM7010/DM8010 (SN5410/SN7410) Triple 3-lnput Gate II 4-i 1 L " 1 •I-' Ci 0 K CLOCK J DM7500/DM8500 (SN5476/SN7476) Dual J-K Flip Flop with Preset and Clear Inputs TEXAS INSTRUMENTS 123 D U A L R E T R I G G E R A B L E M O N O S T A B L E M U L T I V I B R A T O R S W I T H C L S A R F U N C T I O N T A B L E I N P U T S O U T P U T S C L E A R A B Q Q L X X L H X H X L H X X L L H H L t J I " L T H t H X L i r t L H X L " I X See page 138 JC C„T Ce,t IQ 20 CLR 28 2A Soe Notes X J B 1A IB 1 l Q 2CI 2 2R.A|/CND Cl .R CtMi CM| SN54123/SN74123(J, (SJ, W» SN54L123/SN74L123(J , N) OPERATIONAL AMPLIFIERS MOTOROLA NATIONAL SEMICONDUCTOR LM 311 tOFVff* APPENDIX B AC. SYSTEM LINE TO NEUTRAL VOLTAGES CONVERT COMMAND' ERROR WTV\ PAC/PRR fi )fi Ct--toe C/J-J ^ '01 mitt Bi -loo' 60° 60° o — I — IS — I — 60 75 120 I3S ERROR'Oi^O ) ocmtn = 6' ; oc=/5B ; SYMMETRICAL AC srsreM CONVERTER CONTROL TIMING DIAGRAM 

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