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A study of substrate noise in mixed-signal integrated circuits Hekmat, Mohammad 2005

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A Study of Substrate Noise in Mixed-Signal Integrated Circuits by  Mohammad Hekmat B . S c , Sharif University of Technology, 2003 A THESIS S U B M I T T E D IN P A R T I A L F U L F I L M E N T O F T H E REQUIREMENTS FOR T H E D E G R E E OF MASTER OF APPLIED SCIENCE in The Faculty of Graduate Studies ^  (Electrical and Computer Engineering)  T H E UNIVERSITY OF BRITISH C O L U M B I A July, 2005  © Mohammad Hekmat, 2005  11  Abstract Integrating analog and radio-frequency ( R F ) circuits with digital blocks on a C M O S system-on-a-chip (SoC) has drawn a lot of attention, recently.  One major obstacle at  this high level of integration is the substrate noise, which results in undesired interaction between these circuits through the common substrate. Analog circuits are the main victims of such interactions; consequently, understanding the behaviour of substrate noise and performance degradations it causes, is indispensable for analog designers. This work addresses three aspects of substrate noise. First, substrate noise is characterized in the time and frequency domains to identify major parameters that control substrate noise generation, propagation, and reception. Effects of many parameters on the amount of noise generation and coupling are also studied. Second, this thesis investigates the noise impact on analog circuits from a circuit-level point of view by introducing a new small-signal model of the M O S device, which accounts for the substrate noise effects. While most works have focused on system-level or signallevel analysis, study of the noise from a circuit-level point of view is more beneficial for analog designers because it gives them more insight on how to improve the substrate noise rejection capability of their designs. Finally, noise reduction techniques are revisited in this work. The use of passive guardrings is reviewed in detail and the effects of many design parameters on the amount of noise attenuation provided by these structures are studied. The behaviour of guard-rings in different substrates are also discussed.  iii  Table of Contents Abstract  ii  Table of Contents  iii  List of Tables  v  List of Figures  vi  List of Abbreviations  viii  Acknowledgements  ix  1 Motivation  1  1.1  Challenges of Analog C M O S Circuits i n SoCs  1  1.2  Research Goals  3  1.3  Thesis Organization  4  2 Background 2.1  6  Substrate Noise Characterization  8  2.1.1  Noise Injection into the Substrate  9  2.1.2  Noise Propagation through the Substrate  10  2.1.3  Noise Reception Mechanisms  11  2.2  Substrate Noise in Frequency Domain  12  2.3  Effects of Substrate Noise  13  2.4  Substrate Noise Simulation  15  2.5  Substrate Noise Reduction Techniques  17  3 Substrate Noise Characterization 3.1  19  Supply/Ground Noise due to Switching  21  3.1.1  M O S Device Modelling  21  3.1.2  Supply/Ground Noise in a Single Gate  23  3.1.3  Simultaneous Switching of Multiple Gates  26  3.1.4  Supply/Ground Noise Simulation Results  28  Table of Contents  4  5  3.2  Internal versus External Noise Sources  31  3.3  Substrate Noise in Frequency Domain  35  3.4  Noise versus Switching Time  35  3.5  Effect of Substrate Type on Noise  39  3.5.1  Different Substrate Types  39  3.5.2  Noise Behaviour in Different Substrates  42  3.6  P M O S versus N M O S  46  3.7  Summary  47  M o d e l l i n g the Effect of Substrate Noise  49  4.1  Noise Modelling in M O S Devices  50  4.2  M O S F E T Small-Signal Model Including Substrate Noise Effects  52  4.3  Noise Figure Calculation  55  4.4  Summary  62  E v a l u a t i o n of R e d u c t i o n M e t h o d s  63  5.1  Noise Injection Reduction  64  5.1.1  65  5.2  6  iv  Switching Activity Spreading  Noise Propagation Reduction  66  5.2.1  67  Passive Guard-Rings  5.3  Noise Reception Reduction  76  5.4  Summary  77  Conclusion and Future W o r k  79  6.1  Conclusion  79  6.2  Future Work  80  Bibliography  82  A  88  M O S F E T Small-Signal M o d e l  V  List of Tables 1.1  Some of the recently reported SoCs  5.1  Noise attenuation using G R s with different shapes  3 74  vi  List of Figures 1.1  The block diagram of a multi-standard SoC  2  2.1  Partitioning substrate noise coupling mechanism into three steps  9  3.1  Illustration of internal and external noise sources  3.2  I - V characteristic of an N M O S device in 0.18/zra technology and its linear  19  approximation  22  3.3  A typical C M O S inverter along with the package model  24  3.4  Switching noise voltage on ground line with L = InH, R = 2Q, t — 200ps, r  and N = 100 3.5  28  M a x i m u m noise on ground as a function of the number of switching gates (R = 0, t = 200ps, L = InH, C = 0)  29  r  3.6  M a x i m u m noise on ground as a function of the number of switching gates (R = 2tt, t = 200ps, L = InH, C = 1 0 0 / F )  30  r  3.7  M a x i m u m noise on ground lines as a function of the inductance in supply lines (R = 2Q, t = 200ps, C = 1 0 0 / F , N = 200)  31  3.8  Comparison of the internal and external noise sources  32  3.9  Layout of substrate noise analysis testbench  34  r  3.10 Attenuation factor as a function of frequency  36  3.11 Substrate noise waveforms for various clock rise-times  37  3.12 Peak-to-peak value of substrate noise as a function of the rise-time of the last stage  38  3.13 Two most commonly used silicon substrates  40  3.14 Resistive modelling of the substrate  41  3.15 Attenuation factor as a function of the distance between analog and digital nodes in two types of substrate (Note that the scales are different.)  . . . .  43  3.16 The dependence of the attenuation factor on the resistivity of the bulk in lightly-doped wafers  44  3.17 Illustration of geometric mean distance (d i) gm(  45  3.18 The dependence of the attenuation factor on the thickness of the epitaxial layer  46  List of Figures  vii  3.19 Frequency dependence of the additional attenuation provided by P M O S . 4.1  .  M O S F E T small-signal model, including device internal noise sources (no substrate noise modelling or body effect)  4.2  47  50  Small-signal model of a M O S F E T , including device internal noise sources, substrate noise and body effect  52  4.3  Simplified version of Figure 4.2  53  4.4  A typical inductively-degenerated L N A  55  4.5  Small-signal model of an inductively-degenerated L N A  56  4.6  Normalized device noise factor as a function of Q for different values of c.  58  4.7  Normalized substrate noise factor as a function of Q  59  4.8  Noise figure as a function of Q. The spectral density of substrate noise is given in V /Hz  60  2  4.9  Comparison of noise figure for different Qs. (The spectral density of substrate noise is given in V /Hz.)  61  5.1  Switching activity spreading  65  5.2  Effect of S A S in time and frequency domains  66  5.3  Lumped model of G R s in lightly-doped substrates  68  5.4  Attenuation as a function of frequency for different G R arrangements.  5.5  Additional attenuation provided by G R s as a function of frequency  71  5.6  G R attenuation as a function of width  72  5.7  Effect of G R placement  72  5.8  Different G R shapes  73  5.9  Lumped model of G R s in epitaxial substrates  75  2  . .  5.10 Effect of substrate type A.l  76  Detailed small-signal model of the M O S device, including device internal noise sources, parasitic capacitances, and body effect  A.2  88  Simplified M O S F E T small-signal model (parasitic capacitances, gate distributed resistance, and body effect are ignored)  A.3  70  89  M O S F E T small-signal model with a single noise source representing the effects of both channel thermal and gate-induced noise  90  A.4  M O S F E T model for the calculation of the effect of gate-induced noise . . .  90  A.5  Equivalent circuit to find Z  91  A.6  M O S F E T model for the calculation of the effect of channel thermal noise. .  92  gs  List of Abbreviations ADC  Analog-to-Digital Converter  BEM  Boundary Element Method  CBL  Current Balanced Logic  CCBL  Complementary Current Balanced L o  DAC  Digital-to-Analog Converter  DNC  Device Noise Coefficient  DNF  Device Noise Factor  FDM  Finite Difference Method  FSCL  Folded Source Coupled Logic  GPS  Global Positioning System  LNA  Low-Noise Amplifier  PLL  Phase-Locked Loop  SAS  Switching Activity Spreading  SCL  Source Coupled Logic  SNC  Substrate Noise Coefficient  SNF  Substrate Noise Factor  SNR  Signal-to-Noise Ratio  SoC  System-on-a-Chip  SOI  Silicon-on-Insulator  SSN  Simultaneous Switching Noise  VCO  Voltage-Controlled Oscillator  Acknowledgements ' This thesis would not have been completed without the appreciable help of many great people who made my life in U B C an enjoyable and enlightening experience. First of all I would like to express my gratitude to my supervisor, Dr. Shahriar Mirabbasi for giving me the opportunity to work in his group. I am greatly indebted to him for his continuous support, patience, and enthusiasm. He has been a great friend and advisor for me. I would also like to thank Professors Andre Ivanov and Resve Saleh for reviewing my thesis. I also wish to thank Dr. M a j i d Hashemi for his valuable technical comments. This research was supported in part by S i R F Technology Inc., C M C , and N S E R C . I gratefully acknowledge the support of my colleagues in System-on-a-Chip group in U B C . I'm especially thankful to Shahrzad Jalali, Pedram Sameni, Zahra Ebadi, M a r w a Hamour, Samad Sheikhaei, Dipanjan Sengupta, Y i n - T i n g Chang, Behnoosh Rahmatian, Neda Nouri, Edmund Lee, R o d Foist, Peter Hallschmid, and Howard Yang. I would also like to extend my thanks to my friends in U B C for all the memories I share with them, especially Mehran Motamed, Ehsan Dehghan, Hani Eskandari, Reza Zahiri, Sara Khosravi and also all my colleagues in E C E G S A . M y sincere thanks goes to Roberto Rosales for all his support and willingness to help. I also wish to thank Roozbeh Mehrabadi for C A D support and Sandy Scott for her ad-  i ministrative assistance in our lab. A n d the last but the most, I express my deepest appreciation to my wonderful parents and sisters for all their love and endless support. If it were not for their sincere help and encouragement, I would not have made it as far as I did.  1  Chapter 1  Motivation 1.1  Challenges of Analog CMOS Circuits in SoCs  Continuous scaling in C M O S technology has provided improved device performance and lower cost in digital circuits over the past three decades.  The proliferation of C M O S  digital circuits has augmented the demand for C M O S analog and RF circuits, which were previously implemented in Bipolar or B i C M O S technologies. However, since C M O S processes have traditionally been optimized for digital applications, they are not ideal candidates for analog purposes owing to several shortcomings such as the inherent low drive capability of active devices, the relatively poor quality of on-chip passive elements, and the low power supply requirement imposed by digital applications.  Despite these  difficulties, analog designers have managed to develop successful C M O S analog and R F blocks with novel architectures and design techniques [1]. The feasibility of using C M O S in analog circuits has motivated people toward higher levels of integration and, ultimately, a system-on-a-chip (SoC) that will be a combination of digital, analog, and R F circuits. Figure 1.1 shows a simplified block diagram of an SoC with multi-standard R F front-end, analog-to-digital converter ( A D C ) , digital-to-analog converter ( D A C ) , and baseband signal processing blocks as well as other logic and digital  Chapter 1. Motivation  GPS  CPU  ADC  GSM  2  DSP  Logic and Control Unit  Baseband Processing Unit  I/O  IEEE802.11  Memory Bluetooth  DAC I  R F Front-end  Mixed-Signal Interface  I  I  Digital Unit  Figure 1.1: The block diagram of a multi-standard SoC. units. Such SoCs will result in considerable reduction i n cost, in power consumption, and in form factor, each of which are of crucial importance in handheld devices. Recently, mixed-signal SoCs have drawn a lot of attention, as shown in Table 1.1 [2-13], especially for wireless applications; however, designing an SoC is not as trivial as putting a few blocks on the same chip. A n immediate problem in abutting analog and digital blocks , is the signal integrity issue and, more specifically, substrate noise effect, which is defined as the problem of performance degradation (mostly in analog blocks) due to the activity of neighbouring digital circuits. The substrate noise issue is even more noticeable, when one realizes that many of the works i n Table 1.1 have denoted substrate noise as their major challenge for single' chip integration. Those results are in addition to the published results on performance degradations of individual analog blocks such as A D C s , phase-locked loops ( P L L s ) , and low-noise amplifiers ( L N A s ) . Furthermore, one can anticipate that the problem will be further aggravated in future SoCs because of the increasing complexity of digital functions  Chapter  Company Alcatel [2] Atheros [3] Toshiba [4] A M D [5] Toshiba [6] Sony [7] STmicroelectronics [8] Texas Instruments [9] Broadcom [10] Atheros [11] Texas Instruments [12]  1.  3  Motivation  Application Technology Bluetooth IEEE802.11a IEEE802.11a IEEE802.11b Bluetooth GPS GPS Bluetooth IEEE802.11b IEEE802.11g GPS  0.25pm 0.25pm 0.18jLOTl  0.25^um 0.18pm 0.18pm 0.18pm 0.13pm 0.18pm 0.18pm 90nm  Date ISSCC01 ISSCC02 ISSCC03 ISSCC03 ISSCC03 V L S I Symp.03 CICC04 ISSCC04 ISSCC05 ISSCC05 ISSCC05  Table 1.1: Some of the recently reported SoCs. and faster clock switchings. A l l these issues, coupled with the overall challenges in analog C M O S design, present a picture of the problem where understanding substrate noise would obviously be indispensable.  1.2  Research Goals  This research is intended to provide an intuition into the issue of substrate noise and how it can affect the performance of critical blocks in a mixed-signal SoC, especially in R F and analog parts. It targets three research areas: the first is the study of substrate noise in both the time and frequency domains and the analysis of the effect of several parameters such as clocking frequency and package parasitics on the behaviour of the noise. Additionally, some technological aspects, such as the effect of the substrate type on noise propagation and generation, will be explored; therefore, characterization is one of the primary concerns of this part of the work. In the second part, the impact of substrate noise on the performance of L N A s , as a  Chapter 1. Motivation representative sensitive analog block, will be studied.  4 This is achieved through a new  approach using a proposed M O S device model that accounts for substrate noise effects. Previous work on the same topic has merely considered the problem from a signal analysis aspect; however, our goal is to approach it from a circuit design point of view, which allows for an intuitive perspective on how design parameters can be changed to reduce the effect of substrate noise. Efficient techniques to mitigate the performance degradation caused by substrate noise will be required more and more in future SoCs; thus in the last part of the work, we evaluate the efficiency of existing noise reduction methods and trade-offs in using them. After all, the goal of this research is to show that substrate noise has added new complexity to analog circuit design in mixed-signal SoCs; therefore, to achieve successful designs, it is necessary to take substrate noise into account during the design stage.  1.3  Thesis Organization  This thesis is organized as follows: first, Chapter 2 gives an overview of the substrate noise problem and briefly, discusses the previous research on this topic. Next, Chapter 3 discusses the characterization of substrate noise both theoretically and through simulations. Supply noise as a main contributor to external substrate noise sources will be studied in detail. This chapter also analyzes the impact of the substrate type on noise propagation behaviour, as well as the effect of various parameters on the amount of noise both in the time and frequency domains. Modelling the effect of substrate noise on the performance of analog C M O S circuits  Chapter 1. Motivation  5  is of crucial importance; therefore, a separate chapter focuses on this topic. As such, Chapter 4 will review a general model for noise analysis in M O S circuits, which will be • modified for substrate noise analysis purposes.  Based on the new model, the effect of  substrate noise on a typical L N A in an R F system will be studied. Chapter 5 explores substrate noise reduction techniques. The relationship between the efficiency of these methods and several parameters such as frequency, digital activity, and physical separation will be investigated. Finally, Chapter 6 presents concluding remarks and suggestions for future work.  6  Chapter 2  Background Most modern communication systems use complicated digital signal processing blocks, the activity of which affects the performance of sensitive analog circuits through interactions ' v i a the on-chip parasitics and the common substrate. Such interactions are mostly classified as noise because, by definition, any unwanted fluctuation in analog or digital signals will be considered as noise. In this thesis, substrate noise is meant to be the undesired effects of neighbouring blocks on each other in an SoC, which is propagated through the common substrate. It should be noted that, in contrast to white noise, this type of noise is not totally random but depends on the activity in different parts (mainly digital of the chip); therefore, one can consider it as pseudo-random noise. In general, the maximum tolerable amount of noise is determined by the application and the standard. In some applications such as G P S a very stringent noise requirement is imposed, whereas others, such as Bluetooth, have a more relaxed noise margin. This has been the main obstacle in achieving single-chip solutions in certain applications. For example, as was shown in Table 1.1, the single-chip G P S was introduced much later than other wireless standards despite its relative simplicity. The problem of performance degradation due to the activity of digital circuits was first observed in the 1980s [14], even before the introduction of mixed-signal SoCs. Most  Chapter 2. Background early researchers studied this phenomenon under the name of switching  7 noise. However,  this type of noise applies mostly to digital circuits and refers to the variations of supply and ground voltage due to the switchings in digital circuits. Analog circuits are affected by switching in digital parts not only by supply and ground variations but also by other mechanisms such as body effect that are not addressed in switching noise analysis; therefore, analog circuits do not fit exactly into the context of switching noise, but as will be seen, substrate noise is closely related to switching noise; therefore, understanding the behaviour of switching noise is helpful in substrate noise analysis. Early researchers in the field of switching noise mostly focused on the calculation of the maximum amount of noise without taking into account its time or frequency domain behaviour [15, 16]. It was not until the early 1990s that the first report on the substrate noise problem was published in [17]. Later, a seminal work in the study of substrate noise was reported in [18], where substrate noise was studied in the time-domain, and mostly < the capacitive coupling of the noise was taken into account; therefore, packaging issues and the relationship between supply noise and substrate noise were neglected. Furthermore, a simple digital circuit had been used in their analysis; therefore, in later studies more complicated digital blocks were used as noise generators to explore the effect of various switching patterns on the behaviour of noise [19, 20]. In addition to the behaviour of noise in time domain, the frequency content of the noise is important in R F applications because mainly the in-band portion of the noise or those components that may create in-band intermodulation terms are of significance; therefore, subsequent researchers included the analysis of noise in the frequency-domain in their studies [19-21].  Chapter 2. Background  8  In general, the research o n s u b s t r a t e noise falls i n t o one of four m a j o r categories:  • T h o s e focusing o n substrate noise c h a r a c t e r i z a t i o n either i n the t i m e or frequency d o m a i n [18-20, 22].  • T h o s e s t u d y i n g the effect of s u b s t r a t e noise o n the performance of c e r t a i n a n a l o g blocks [21, 23-25].  • T h o s e concerned a b o u t the m o d e l l i n g of the noise a n d C A D t o o l development [2629].  • T h o s e c o n c e n t r a t i n g o n noise r e d u c t i o n techniques [30-32].  In the following sections, we w i l l e x p l a i n the basic aspects of s u b s t r a t e noise p r o b l e m a n d c o m m e n t o n issues i n its c h a r a c t e r i z a t i o n a n d m o d e l l i n g . W e w i l l also r e v i e w the p r i o r w o r k o n this t o p i c a n d discuss t h e i r m e r i t s a n d s h o r t c o m i n g s .  2.1  Substrate Noise Characterization  T h e s u b s t r a t e noise c o u p l i n g m e c h a n i s m c a n be m o d e l l e d i n three steps, as c o n c e p t u a l l y i l l u s t r a t e d i n F i g u r e 2.1 [21]. F i r s t , the noise is generated a n d injected b y d i g i t a l c i r c u i t r y i n t o the substrate.  N e x t , it travels t h r o u g h the s u b s t r a t e a n d finally couples back to  sensitive a n a l o g nodes. A s s h o w n i n this figure, there exists another w a y for the noise t o ' transfer to a n a l o g nodes, w h i c h is b y means of s u p p l y lines. It s h o u l d be n o t e d t h a t the s u b s t r a t e is well connected t o the s u p p l y lines t h r o u g h s u b s t r a t e contacts; therefore, a n y voltage v a r i a t i o n o n the s u p p l y lines w i l l couple to the s u b s t r a t e a n d reach a n a l o g b u l k nodes.  W e w i l l address this issue later, because even t h o u g h i n t h i s case the noise does  Chapter 2. Background  9  Supply network  \  Noise coupling back to analog nodes  Noise coupling through supply lines incs  Analog circuits  Digital circuits  f3-No  l-Noise injection^ by digital switching  ise reception by analog bulk node  2-Noisc propagation through substrate  Common Substrate  F i g u r e 2.1: P a r t i t i o n i n g s u b s t r a t e noise c o u p l i n g m e c h a n i s m into three steps. not d i r e c t l y go t h r o u g h the substrate, it couples back to the a n a l o g nodes u s i n g s u b s t r a t e contacts.  A s a result, t h i s noise manifests itself t h r o u g h s u b s t r a t e contacts a n d changes  ' the s u b s t r a t e voltage, hence it c a n be considered as s u b s t r a t e noise.  2.1.1  Noise Injection into the Substrate  A l l currents injected i n t o the s u b s t r a t e w i l l cause v a r i a t i o n s of s u b s t r a t e voltage t h a t c a n couple back t o the a n a l o g nodes. T h e s e currents c a n o r i g i n a t e from various sources, such as the c h a r g i n g a n d d i s c h a r g i n g o f l o a d or p a r a s i t i c capacitances, device leakage currents, etc. I n d i g i t a l C M O S c i r c u i t s , s u b s t r a t e noise is generated b y t w o m a j o r m e c h a n i s m s , n a m e l y the c a p a c i t i v e c o u p l i n g from the s w i t c h i n g nodes ( m a i n l y t r a n s i s t o r t e r m i n a l s ) a n d the noise from s u p p l y or g r o u n d lines due to the p a r a s i t i c i m p e d a n c e s of these lines [33]. W h i l e the former comes f r o m the d i r e c t c o u p l i n g of d i g i t a l switchings t h r o u g h p a r a s i t i c capacitances to the substrate, the l a t t e r m a i n l y results from the voltage d r o p across parasitics of b o n d w i r e s a n d package pins.  It s h o u l d be n o t e d t h a t the c a p a c i t i v e c o u p l i n g  Chapter 2. Background  10  is inevitable because the parasitic capacitances of diffusion areas are due to the physical layout of the circuit and cannot be eliminated; however, the noise due to supply can be reduced using better packaging (with lower parasitic inductance) or on-chip decoupling capacitances.  2.1.2  Noise Propagation through the Substrate  , Once the noise is generated in the digital blocks, it will propagate all over the chip through the common substrate.  U p to several G H z , the silicon substrate can be considered a  resistive medium [26]; therefore, any perturbation at any node of such a network will potentially cause voltage fluctuations at all other points.  While the amount of noise  injection and reception depends on the impedance of the injection and reception points ' and supply contacts, the key parameter in noise propagation is the impedance of the substrate path. Since the electrical properties of the substrate are the main factors in the noise propagation behaviour, various studies have focused on investigating the effect of substrate type on the noise [18, 21, 22, 33-35]. Typically, the higher the resistance of the substrate the better the noise rejection performance; therefore, more advanced processes, such as SOI, are anticipated to be better in terms of substrate noise rejection. Interestingly, it has been found that even though these processes are more favourable from a noise propagation perspective at low frequencies, their advantage is compromised with increasing frequency mostly because of the capacitive nature of the substrate impedance [34]. Additionally, it has been shown that the effectiveness of many isolation schemes depends on the properties of the substrate; consequently, understanding the propagation behaviour of the noise in  Chapter 2. Background  11  various types of substrate is important in both noise characterization and reduction.  2.1.3  Noise Reception Mechanisms  Substrate noise can impact analog circuits through two different mechanisms: directly, by affecting the signal at the output or input nodes and, indirectly, by changing the design parameters of the circuit. One of the direct mechanisms is capacitive reception in which the voltage fluctuations * of the substrate directly couple to the drain and source terminals of a M O S F E T through the parasitic capacitances of these diffusion areas [36]. Another direct method is the noise coupling to the channel through depletion capacitances; however, this method can be seen as an extra contribution to the noise injected into the source and drain [36]. In many cases, this noise can be treated as common-mode noise, which can ideally be suppressed using ' differential structures; however, in practice, owing to nonlinearities and asymmetries, it cannot be removed completely. In addition to the terminals of active devices, passive on-chip devices such as capacitors, spiral inductors, and resistors can also act as receptors for substrate noise [37]. One of the major indirect noise reception mechanisms is body effect. This phenomenon changes the large and small-signal behaviour of the M O S device, which influences analog performance. It should be noted that, while capacitive coupling can happen in any active device ( M O S F E T , B J T , or diode), body effect is specific to M O S devices. Other indirect mechanisms, such as the variation of the capacitance of varactors or changes in the biasing conditions of the circuit, are also important in certain applications, e.g., in V C O s and P L L s [23, 38]. However, for the purpose of this work, i.e., the effect of  Chapter 2. Background  12  substrate noise on L N A s , we will focus only on body effect.  2.2  Substrate Noise in Frequency Domain  Most analog circuits work in a specific frequency band. As such, studying the frequency content of the substrate noise is of interest, since out-of-band noise can be easily removed by filtering. Most previously reported work has focused on substrate noise in time domain, and only a few have investigated high-frequency content of the noise and its relationship to other parameters, such as the clocking scheme of digital blocks [19-21, 39]. A n extension of the time-domain work in [18] for G P S applications was demonstrated in [21], which covered substrate noise in frequency domain. A theoretical treatment of the noise was also given; however, it is difficult to get a clear view of the noise frequency content from the formulation. The experimental results were based on a more complicated (yet with a well-defined switching pattern) digital circuit; therefore, the noise peaks in frequency were observed at multiples of clock frequency. Also predicted by this work was that the spectrum of the noise depends not only on the clock frequency but also on the switching patterns of the digital circuits, and as the switching in the digital blocks becomes more random, the noise will eventually be distributed equally over the frequency. Another work presented in [19] used direct measurements to find the frequency content of substrate noise.  One shortcoming of their technique was the limited bandwidth of  the measurement system used, which limited their results to a few 100MHz. The same result as [21] was obtained, i.e., noise peaks occurred at multiples of the clock frequency. Additionally, their results supported the dependence on the switching pattern of the digital  Chapter 2. Background  13  circuit; as an example in [19] the digital circuit had a divide-by-2 nature; consequently, in addition to the main harmonics of the clock frequency, noise peaks were observed at half of the clock frequency, as well. One of few measurement results based on an actual SoC was reported in [20], where it was shown that different cores on an SoC can generate peaks at different frequencies, which is a more realistic approach compared to the totally random activity of digital circuits in [21].  2.3  Effects of Substrate Noise  Substrate noise can affect both digital and analog circuits in an SoC; however, its effect on analog circuits is more pronounced for two reasons: first, analog circuits in general have a more limited noise budget due to the small amplitude of their input signal. Second, the mechanisms through which the noise affects their performance are more diverse in these circuits because, as discussed before, other than direct coupling of the supply noise to the input and output nodes of the circuit, and capacitive couplings through junction and device capacitances, a significant noise reception mechanism is body effect, which is not important in digital applications. The study of noise in analog circuits is also more complicated, owing to the importance of the analysis of the noise in frequency domain. In digital circuits, substrate noise can result in false switching, erroneous storage into flip-flops [40], double clocking, and missing clocked pulses [41]. Another observed phenomenon is the change in the delay of the datapath due to substrate noise that can potentially exceed the predefined clock period.  Chapter 2. Background  14  The effect of substrate noise on analog systems can be analyzed from a signal degradation point of view. Three mechanisms can be distinguished through which substrate noise degrades analog signals [36]: 1. Direct coupling 2. Intermodulation  3. Sampling Substrate noise contains high frequency components that can fall into signal band through the direct coupling of the substrate to the output nodes of the analog circuit. This process can degrade the signal-to-noise ratio (SNR) directly. In addition to direct coupling, in' band noise can be generated through the intermodulation of the noise signals due to nonlinearities in analog circuits [21]. Another consequence of modulation is variations in the bias conditions in bandgap references. A n example of such effects is introduced in [38], where substrate noise in the bandgap reference circuit has resulted in a D C shift of the output voltage. The last mechanism is sampling, which is a common process in A D C s . The noise coupled to the analog circuit preceding the A D C , at an out-of-band frequency, can fold back into signal band through this process [36]. L N A s , P L L s , voltage-controlled oscillators ( V C O s ) , operational amplifiers (op amps), and A D C s are common analog and R F blocks in mixed-signal SoCs; therefore, extensive research has been done on the study of the effects of substrate noise on the operation of these blocks. The impact of noise on operational amplifiers was considered in [42]. In [21] the effect of noise on the performance of a G P S L N A was reviewed from a signal point of view. A  Chapter 2. Background  15  s t u d y of the effect of noise o n oscillators was given i n [23]. I n oscillators, s u b s t r a t e noise c a n change the value of the varactors, w h i c h i n t u r n causes the o u t p u t frequency t o vary, thus generating e x t r a j i t t e r or phase noise. I n [43], the effect of s u b s t r a t e noise on t i m i n g j i t t e r of a P L L was e x p l o r e d u s i n g a stochastic a p p r o a c h to s u b s t r a t e noise. C o m p a r a t o r s are another t y p e of a n a l o g c i r c u i t w i d e l y used i n A D C s .  A common  a r c h i t e c t u r e of c o m p a r a t o r s is c o m p o s e d of a n a m p l i f i c a t i o n stage followed b y a l a t c h . T h e speed of such c o m p a r a t o r s is a f u n c t i o n of the t r a n s c o n d u c t a n c e of transistors i n the l a t c h . Since the t r a n s c o n d u c t a n c e is affected b y the s u b s t r a t e noise t h r o u g h b o d y effect, the speed of the c o m p a r a t o r w o u l d also change due to the s u b s t r a t e noise. T h i s effect c a n be considered as the o u t p u t s i g n a l j i t t e r t h a t w i l l decrease the S N R of the A D C [44]. It was s h o w n i n [25] t h a t the o u t p u t of a n A D C c a n be h i g h l y d i s t o r t e d due to s u b s t r a t e noise. F u r t h e r m o r e , s u b s t r a t e noise c a n s i g n i f i c a n t l y l i m i t the m i n i m u m detectable level of the s i g n a l t h a t c a n degrade A D C ' s r e s o l u t i o n a n d decrease its effective n u m b e r of b i t s . A l t h o u g h i n most cases s u b s t r a t e noise o n l y degrades the performance of the c i r c u i t , examples of m a l f u n c t i o n i n g are also r e p o r t e d i n the literature. A n e x a m p l e of failure was r e p o r t e d i n [45] where a n 8-bit, semi-flash p i p e l i n e d v i d e o A D C c o n t i n u e d t o fail several specifications after three design f a b r i c a t i o n iterations.  2.4  Substrate Noise Simulation  T h e accurate m o d e l l i n g of s u b s t r a t e noise requires the precise m o d e l l i n g of the w h o l e layout a n d substrate, m e a n i n g t h a t i n f o r m a t i o n a b o u t the geometry of a l l wells, well contacts, diffusion areas, trenches, etc.  are needed as well as a t h r e e - d i m e n s i o n a l (3D)  Chapter 2. Background model of the substrate.  16  Even in a small circuit, this comprehensive modelling entails a  huge network of elements whose governing equations will not be tractable. Furthermore, since the modelling depends on the final layout of the chip, it would be difficult for designers to get an insight into the effects of substrate noise at the early stages of the design. Accurate modelling techniques use various methods, such as the finite difference (FDM)  or the boundary  method  element method ( B E M ) , and Green's function to accurately 1  solve physical equations of the substrate and model it with a large and accurate R C .network [27, 28, 45, 46]. Conventional tools available for substrate noise analysis, such as S P A C E  [47] and  S N A [48], use 3D modelling of the substrate and create macromodels of the digital noise and substrate and solve the resulting network using several simplification algorithms.  2  Some works have suggested small models consisting of a few lumped elements to be added ' t o each transistor [18, 19, 34]. One major drawback of these models is that they are applicable only to epitaxial substrates owing to some special properties of these substrates  3  that renders them impractical for lightly-doped ones; nonetheless, since they can be applied to simulations at the schematic level, they can be used even before the final layout is drawn. In addition to substrate modelling, calculation of the switching digital noise is another part of substrate noise simulation that should be addressed in C A D tools. Due to the large number of elements on current chips, the accurate simulation of switchings results in a prohibitively large computation cost; therefore, various methods are proposed in the The Green's function is the potential at any point in a medium with suitable boundary conditions due to a unit current injected at a point within the medium. In this thesis, we use SeismIC noise analysis tool for the study of substrate noise, which is a part of Substrate Noise Analyst (SNA) by Cadence™. W e will discuss the difference between epitaxial and lightly-doped substrates in detail in Chapter 3. 1  2  3  Chapter 2. Background  17  literature for macromodelling digital noise [49-51]. A simple approach is to use a properlysized chain of inverters instead of a large digital block to reduce the calculation cost.  2.5  Substrate Noise Reduction Techniques  Several existing substrate noise reduction techniques can be found in the literature. The use of passive guard-rings was studied in [34]. A simple substrate contact was used as a noise sensor, which is resistively connected to the substrate, whereas in a more realistic approach analog nodes are connected to the substrate both resistively and capacitively. Active noise suppression is another method, which was explored i n [30, 31]. The basic idea is to measure the amount of noise and inject an inverted version of the noise into the substrate to cancel out the original noise. This approach suffers from two shortcomings: first, this technique will cancel the noise locally and cannot be applied to a large area unless , multiple measuring points and circuitry are used.  Additionally, i n contrast to passive  methods that do not impose power overhead, this method involves power consumption for noise reduction circuits, which is not desirable in low-power or handheld applications. In addition to passive and active guard-rings, digital activity can be modified to generate less noise. This reduction is usually achieved either by reducing the amount of activity ' or distributing it over time. Many low-noise digital families are proposed, including cur4  rent steering logic (CSL), current balanced logic ( C B L ) , complementary current balanced logic ( C - C B L ) , source-coupled logic (SCL) and folded source-coupled logic ( F S C L ) [52-54]. Output drivers are typically one of the major contributors to substrate noise due to the Note that most of these techniques are similar to those used in low-power digital design because both try to reduce instantaneous current or simultaneous switching. 4  Chapter 2. Background  18  large instantaneous current t h e y d r a w from the supplies. T h e design of low-noise o u t p u t d r i v e r s was also addressed i n [41, 55]. A n e x a m p l e of a c t i v i t y d i s t r i b u t i n g techniques is  switching activity spreading, w h i c h was presented i n [21, 56]. A l t h o u g h this technique reduces the r m s value of the noise, this r e d u c t i o n does not necessarily m e a n t h a t the noise content i n the frequency b a n d of interest is also decreased; therefore, these approaches s h o u l d be used w i t h c a u t i o n i n R F a p p l i c a t i o n s [21].  19  Chapter 3  Substrate Noise Characterization Voltage variations in the substrate are caused by various sources. These sources can be classified into two major types: internal and external noises. These terms refer to the way that the generated noise couples to the substrate of analog circuits and not the propagation properties of the noise through the substrate. Figure 3.1 illustrates this concept.  V  Off-chip supply network Analog  Digital  v_  ~r.  A/  -r  Internal Noise  External Noise  Figure 3.1: Illustration of internal and external noise sources.  Internal noise refers to the case where the switching of on-chip digital gates is internally coupled to the substrate through the parasitic capacitances of active devices, wells and interconnects; therefore, it directly couples to the substrate and transmits to sensitive nodes, i.e., everything happens internally, within the silicon substrate.  O n the other  hand, external noise applies to the situation in which a part of the noise path from digital to analog nodes falls outside of the chip substrate (e.g., on supply lines). A n example of  Chapter 3. Substrate Noise Characterization  20  s u c h noise is w h e n s w i t c h i n g d i g i t a l gates i n d u c e noise o n s u p p l y / g r o u n d l i n e s a n d t h e n 1  the r e s u l t i n g noise is c o u p l e d back t o the s u b s t r a t e t h r o u g h s u b s t r a t e a n d s u p p l y contacts i n t h e v i c i n i t y of a n a l o g c i r c u i t s . N o t e t h a t b o t h the i n t e r n a l a n d e x t e r n a l sources are consequences of s w i t c h i n g i n d i g i t a l parts, b u t t h e y use different p a t h s t o reach a n a l o g nodes. In a d d i t i o n t o t h e noises d u e t o s w i t c h i n g a c t i v i t y , other noises exist t h a t are indep e n d e n t of s w i t c h i n g i n d i g i t a l gates a n d are m o s t l y due t o leakage currents. of such sources are impact  ionization  current  a n d photon  induced  current.  Examples  However, it  has been s h o w n t h a t these types of noise have less of a n i m p a c t o n t h e o v e r a l l s u b s t r a t e noise [19, 33], a n d thus t h e y are i g n o r e d i n o u r study. In t h e f o l l o w i n g sections, a review o f s u p p l y / g r o u n d noise as a m a j o r c o n t r i b u t o r t o e x t e r n a l noises is given first. N e x t , t h e effects of several parameters o n t h e i n t e r n a l a n d e x t e r n a l sources are a n a l y z e d .  T h i s s e c t i o n is followed b y a d i s c u s s i o n o n t h e relative  i m p o r t a n c e of i n t e r n a l a n d e x t e r n a l sources t o i d e n t i t y t h e d o m i n a n t noise m e c h a n i s m . F i n a l l y , t h e effect of s u b s t r a t e t y p e o n noise p r o p a g a t i o n b e h a v i o u r is s t u d i e d u s i n g s i m u l a t i o n results from S e i s m I C s u b s t r a t e noise analysis t o o l . It s h o u l d be n o t e d t h a t S e i s m I C is one of t h e few s u b s t r a t e noise analysis tools c o m m e r c i a l l y available, t h e a c c u r a c y of w h i c h is verified b y e x p e r i m e n t a l results [57, 58].  This noise is sometimes referred to as ground/supply bounce, switching, or ^ noise.  Chapter 3. Substrate Noise Characterization  3.1  21  Supply/Ground Noise due to Switching  , The inductance of package pins and bondwires, along with the transient currents, are the main causes of supply or ground noise in digital circuits. The transient current during digital transition in a C M O S logic circuit comes from two sources: the main source of this current is the charging or discharging of the load capacitance of each gate through the positive supply (VDD)  o  r  negative supply (V$s), respectively, and the second source is the  • short circuit current between VDD and Vss during the switchings. To explore the behaviour of this current, in the following section, we develop a simplified M O S F E T model, which allows for the analytical study of the switching behaviour.  3.1.1  M O S Device Modelling  Early work in the field of switching noise assumed square-law operation for the M O S device [15, 59]; however, the model now widely in use for short-channel devices is the a-power law model that accounts for velocity saturation effects [60]. Based on this model, the drain current of a M O S device in the saturation region can be approximated using the following equation:  I = K(V -V r D  GS  th  where V h is the M O S F E T threshold voltage and a is a technology-dependent t  (3.1) parameter,  derived to be equal to 2 for long-channel transistors and closer to 1 for deep submicron devices. Using Equation 3.1 in supply/ground noise analysis leads to a system of nonlinear ' differential equations that is difficult, if not impossible, to solve analytically. Different approximation techniques have been proposed to simplify and/or linearize the resulting  Chapter 3. Substrate Noise Characterization  22  Figure 3.2: I - V characteristic of an N M O S device i n 0.18pm technology and its linear approximation. equations [15, 16]. In this section a linear approximation of the M O S device characteristic - is used, which results i n a set of linear differential equations [61]. Figure 3.2 shows the I-V characteristic of an N M O S device along with its linear approximation. In this figure, S P I C E simulations for 0.18um C M O S technology were used to obtain the N M O S I-V characteristic. As Figure 3.2 shows, the linear approximation is in close agreement with the actual ' I - V characteristic, especially i n the active region. This property is favourable, since the switching N M O S transistor will most likely remain in the active region during switching from high to low; therefore, it is expected that the linear approximation will give accurate results in switching analysis. This is particularly true for output drivers where, due to the large capacitive load, the output voltage remains almost constant during the switching of the transistor. Using data obtained from Figure 3.2, we can write the linear approximation  Chapter 3. Substrate Noise Characterization  23  of the M O S device as:  ID  where K~i is a constant and  =  K (V -VGSO) 1  VGSO  GS  for  Vs G  (3.2)  VGSO  >  is the intersection point of the approximation line and the  VQS axis, which is not necessarily equal to V h of the M O S device. Simulation results show t  that changes of VDS, within supply limits, have a negligible effect on the I-V characteristic and is thus ignored in the calculations of this section. It should be further emphasized that the more linear behaviour of the device, the better this approximation, meaning that this model is expected to be more accurate for more deep submicron devices.  3.1.2  Supply/Ground Noise in a Single Gate  Figure 3.3 shows a typical C M O S inverter, along with package and bondwire parasitics. In this figure, the parasitics of the power supply and ground lines are represented using a lumped R L C model. The capacitive load of the inverter is shown by CL, and the input signal is modelled with a ramp signal, changing from ground to supply with a finite risetime: Vm  — —VDD  for 0 < t < t  (3-3)  r  To derive an analytical formula for ground variations due to switching, we assume 2  the noise on the ground line to be initially zero. The N M O S transistor is also initially in the cut-off region and starts conducting after the input signal reaches  VGSO-  The following  Due to the similarity of switching noise calculations on supply and ground lines, only the corresponding derivations for ground lines are presented here. The results can be readily modified to obtain equations for power-supply noise. 2  Chapter 3. Substrate Noise Characterization  24  Figure 3.3: A typical C M O S inverter along with the package model. equations capture the behaviour of the circuit:  IN =  K ^ - V n - V c s o )  IT, =  IN  V  N  =  RI  C+  L  (3-4) (3.5)  dt L  dt  (3.6)  ^  where IN is the current of the N M O S source terminal, II is the current through the parasitic inductance and V is the noise voltage at the substrate node. Combining Equan  tions 3.4-3.6, we have:  L C ^  + (LK  RC) ^ d  t  +  + (l + RK )V X  = L K ^  + RK V x  in  - RKMso  (3.7)  which is a second-order linear differential equation that can be solved analytically.  It  should be noted that this linear equation is a result of the linear approximation of the I - V  Chapter 3. Substrate Noise Characterization  25  characteristic of the M O S device. The analytical solution of the differential equation has the following form:  V =V +V n  h  (3.8)  p  where, V is the particular solution and V is the general solution of the homogeneous p  h  equation, and is given by: V = de  xl  h  x  + de  (3.9)  X2  2  Ai and A2 are the roots of the characteristic equation that can be complex and d\ and d  2  are constants that are calculated based on the initial conditions of the circuit. Assuming a linear ramp approximation, as i n Equation 3.3, V has the following form: p  V = at + b  (3.10)  p  where:  a =  K B  X  { ^  =~ ^  {l  + R )t Kl  (  3  1  1  )  r  - RVGSO) - (LK,  TSTG  +  RC) a  "  ( 3 1 2 )  Chapter 3. Substrate Noise Characterization  3.1.3  26  Simultaneous Switching of Multiple Gates  It is a common practice in large circuits to replace individual logic blocks with a large inverter or a chain of inverters that generate the same amount of switching current. This approach decreases the computational complexity of simulations and is used in many noise macromodelling applications [49]. The derivations of the previous section can be extended to the case of N simultaneously switching gates or, equivalently, a large inverter with N times the width of a single inverter. The equations can be derived in the same manner; the final equation is as follows:  dV  dV dt  2  L  C  N  ^z  +  dt L  K  (NLKi  ^  + R C ) ^  + NRKiVin  at  -  +  (1 + NRK )V  =  X  (3.13)  NRK.VGSO  The solution of this differential equation can be used to find the maximum peak-topeak value of the switching noise. First, we look at the characteristic equation of this differential equation:  LCA + 2  A =  + RC)X + (1 +  (NLKi  (NLKi  -  RC)  2  - 4LC  RNK ) t  =  0  (3.14) (3.15)  Depending on the value of the parameters and N, the discriminator of the quadratic equation, A , can be either positive, negative, or zero. We define N^t as the value of N for which A is zero:  Chapter 3. Substrate Noise Characterization For N  >  N  c r i t  the e q u a t i o n has t w o real roots, w h i c h is most l i k e l y to h a p p e n for  Ncrit  large values of N.  27  N o t e t h a t , as K\ increases (for e x a m p l e w h e n u s i n g larger t r a n s i s t o r s ) ,  decreases, w h i c h is the case for large o u t p u t drivers. I n cases where N < N  c r i t  the  ,  b e h a v i o u r of the noise is different, a n d r i n g i n g due t o the o n - c h i p p a r a s i t i c c a p a c i t a n c e a n d i n d u c t a n c e is observed. Since o u t p u t drivers, due to t h e i r large transient currents, are the m a j o r c o n t r i b u t o r s to s w i t c h i n g noise, here the e q u a t i o n is solved a s s u m i n g N >  N  c r i t  .  I n this case, b o t h A i a n d A are negative real n u m b e r s , r e s u l t i n g i n a d e c a y i n g e x p o n e n t i a l 2  t e r m i n the noise expression.  M o r e o v e r , i t c a n be s h o w n t h a t u n d e r the c i r c u m s t a n c e s  m e n t i o n e d above the m a x i m u m s w i t c h i n g noise w i l l always o c c u r at the e n d of the i n p u t t r a n s i t i o n t i m e , a n d its value c a n be c a l c u l a t e d from the following f o r m u l a :  Vn  = (-a t  max  n  0  -b  n  + ^)e  A 2  ^-*o)  +  j  a r  +  b  n  (  where A i a n d A are real roots of the c h a r a c t e r i s t i c e q u a t i o n a n d | A i | 2  >  3  1  7  )  | A | , to is the 2  t i m e at w h i c h the t r a n s i s t o r starts c o n d u c t i n g a n d c a n be a p p r o x i m a t e d b y the f o l l o w i n g formula:  to = ¥r^t VDD  I n E q u a t i o n 3.17, a  n  and b  n  (3.18)  r  are m o d i f i e d versions of a a n d b c a l c u l a t e d for the case of N  s i m u l t a n e o u s l y s w i t c h i n g gates a n d are g i v e n by: RNK V X  a n  n  _ NK^Zto* ~  DD  = (1 + NRKJU  -  RVGSQ)  - (NLK, +  l + NRK,  ( 3  '  1 9 )  RC)a  n  -  [d 2U)  Chapter 3. Substrate Noise Characterization  3.1.4  28  Supply/Ground Noise Simulation Results  S P I C E simulations were performed in a C M O S 0.18//m technology to evaluate the accuracy of the proposed model. Figure 3.4 presents the transient behaviour of the noise using the linear approximation of Section 3.1.1. This figure verifies that the proposed approach closely follows S P I C E simulation results, especially when the transistor is fully conducting.  100  150 200 Time (psec)  250  350  Figure 3.4: Switching noise voltage on ground line with L = InH, and N = 100.  R = 2il, t = 200ps, r  The maximum value of the simultaneous switching noise ( S S N ) as a function of the 3  number of switching gates is plotted in Figures 3.5 and 3.6. For the purpose of comparison, the results of two other works are also included in these figures. To make a fair comparison, the values of package resistance and capacitance are set to zero in Figure 3.5. The effect T h i s term is frequently used in the literature to represent the noise appearing on supply and ground lines due to the simultaneous switching of digital gates. 3  29  Chapter 3. Substrate Noise Characterization  0  50 100 150 N u m b e r of Switching G a t e s  200  Figure 3.5: M a x i m u m noise on ground as a function of the number of switching gates  (R = 0,t = 200ps, L = InH, C = 0). r  of these parasitics are included in Figure 3.6, where a resistance of 2fi and a capacitance of 1 0 0 / F are added in the supply parasitic network. A s can be seen in Figure 3.5, there is - a large discrepancy between S P I C E results and those predicted by the approach presented in [15], which is primarily due to neglecting the effect of velocity saturation in that work. In the other work, the effects of package capacitance and resistance were ignored, resulting in underestimating noise values. The results of the proposed model are within 2% of S P I C E simulations i n Figure 3.5. The accuracy decreases as the number of gates increases due to ' the increase i n the approximation error used in determining the initial conditions of the differential equation and neglecting subthreshold current. Equation 3.17 can be used to analyze the effect of several parameters, such as the power supply voltage, the parasitic inductance of the package and bondwires, and the number of simultaneously switching gates, on the maximum amount of noise i n the circuit.  Chapter  0  3. Substrate Noise  30  Characterization  50 100 150 N u m b e r of S w i t c h i n g G a t e s  200  Figure 3.6: M a x i m u m noise on ground as a function of the number of switching gates (R = 2 0 , t = 200ps, L = InH, C = 1 0 0 / F ) . r  While parasitic resistance has been neglected in simultaneous switching noise calculations in [15, 16, 62], simulation results show that as C M O S technology scales down and the integration level and transient currents increase the voltage drop across this resistance can potentially be important; more specifically, Equation 3.17 suggests that this resistance creates a term that increases linearly with time; hence it is more significant in slower parts of the circuit, such as output drivers, that have larger switching time and contribute more to noise. Equation 3.17 verifies the previous result observed in [15] and [16] that the S S N maximum value is a sublinear function of the inductance as shown in Figure 3.7. This can be considered a consequence of the built-in negative feedback of the M O S device, which does not allow the noise to increase unboundedly. Due to this built-in negative feedback, the drain current decreases as the voltage of the source of the M O S transistor increases, hence  Chapter 3. Substrate Noise Characterization  31  1000  F i g u r e 3.7: M a x i m u m noise on g r o u n d lines as a f u n c t i o n of the i n d u c t a n c e i n s u p p l y lines (R = 2Q, t  r  = 200ps, C = 1 0 0 / F , N = 200).  decreasing the a m o u n t of transient current t h r o u g h the p a r a s i t i c s .  4  A n i m p o r t a n t note is t h a t , as c a n be seen i n the results of this section, the noise o n s u p p l y lines c a n p o t e n t i a l l y be large. O n c e a noise s i g n a l of hundreds of m i l l i v o l t s appears o n s u p p l y n e t w o r k of the c h i p , it c a n p r o p a g a t e t h r o u g h the s u b s t r a t e v i a s u p p l y a n d s u b s t r a t e contacts a n d couple to the s u b s t r a t e node of a n a l o g devices; hence, this noise c a n c o n s t r u c t the m a j o r p a r t of the e x t e r n a l noise sources.  3.2  Internal versus External Noise Sources  ' I n the previous sections, s u p p l y / g r o u n d noise was discussed as one of the m a j o r c o n t r i b u tors t o e x t e r n a l noise sources; nonetheless, the c o n t r i b u t i o n of each of the t w o i n t r o d u c e d 4  Here it is assumed that the gate potential is constant.  Chapter 3. Substrate Noise Characterization  32  L e n g t h of B o n d w i r e (urn)  Figure 3.8: Comparison of the internal and external noise sources.  sources (external and internal noises) to the total substrate noise is an interesting parameter to observe. Since external noise sources are typically much larger than internal sources they can potentially dominate the overall noise. Especially if the analog and digital circuits share the same supply lines, any noise on digital lines will directly couple to i  the substrate area in the proximity of analog devices through substrate contacts of that area, which will drastically increase the amount of noise; whereas in the case of separate supplies, the only way for the noise on digital supply lines to disturb analog nodes is to couple to the substrate through substrate contacts of the digital circuits. Figure 3.8 represents SeismIC simulation results of the substrate noise at the bulk node  * of an analog N M O S located 100pm away from a chain of inverters. The total substrate noise is plotted as a function of the length of the bondwire, which can be translated into  Chapter 3. Substrate Noise Characterization  33  the amount of inductance. Two cases are plotted in this figure; in the first one the analog 5  and digital supplies are separated, which means that the total noise is due only to internal ' sources, whereas in the second one supply lines are shared; therefore, both internal and external noise sources contribute to the overall noise. Figure 3.8 reveals an important point: the amount of noise increases significantly if the supply lines of the analog and digital circuits are the same. A n immediate implication of this observation is that using separate supplies for analog and digital sections significantly ' reduces the interaction between these two parts. In cases where use of separate supplies is not possible, the total noise can be reduced using a low-inductance package such as flip-chip. In fact based on Figure 3.8 for the circuit used in these simulations, the noise coupling from supply lines will be dominant if the amount of the inductance is larger than 200pH, which means that above this value, most of the noise would be due to supply noise rather than the direct effect of switching in digital cores. In other words, external noise 6  sources dominate very quickly as the inductance in the package increases. Hereafter, unless otherwise specified, it is assumed that digital and analog supply lines are separated, implying that only internal noise sources are causing noise at the substrate of analog nodes. In most parts of this work, a simple inverter in C M O S 0.18/txm is used as a testbench to study the effect of various parameters on substrate noise. The layout of the test circuit is shown in Figure 3.9. The noise is measured at the substrate of digital 7  N M O S and a dummy N M O S , which is used to represent a sensitive analog device. As a rule of thumb the inductance is linearly proportional to the length of the bond wire with the slope of I n H / m m . Note that 200pH is very small compared to the inductance of most available packages. , For more information on the layout of other testbenches please refer to [63] 5  6  7  Chapter 3. Substrate Noise Characterization  34  Figure 3.9: Layout of substrate noise analysis testbench.  To quantify the noise behaviour, the noise attenuation factor is used in this study, which is defined as the ratio of the peak-to-peak value of the noise at the bulk node of the N M O S in the inverter to the peak-to-peak value of the noise at the bulk node of the dummy N M O S : AttPmmrinn  -  V  PP'  D i  9  i t a l  (3.21)  'pp,Analog  The attenuation factor depends on a variety of parameters, such as substrate type and digital activity. The following sections deal with the characterization of substrate noise using the attenuation factor.  Chapter 3. Substrate Noise Characterization  3.3  35  Substrate Noise in Frequency Domain  T h e dependence of noise a t t e n u a t i o n o n the frequency of o p e r a t i o n is a n i m p o r t a n t p a rameter i n noise analysis i n high-frequency a p p l i c a t i o n s .  F i g u r e 3.10 presents S e i s m I C  s i m u l a t i o n results of the dependence of the a t t e n u a t i o n factor on frequency for v a r i o u s distances between n o i s y a n d sensitive parts.  A s c a n be seen, the noise a t t e n u a t i o n i m -  proves as the frequency increases i n F i g u r e 3.10(a). T h i s o b s e r v a t i o n is i n t e r e s t i n g because one m i g h t t h i n k t h a t at higher frequencies there is m o r e c o u p l i n g between n o i s y p a r t s a n d the substrate.  However, a l t h o u g h the a m o u n t of noise c o u p l i n g increases at higher fre-  quencies due to the c a p a c i t i v e b e h a v i o u r of the i m p e d a n c e c o u p l i n g the s w i t c h i n g nodes t o the substrate, the a m o u n t of s u b s t r a t e c o u p l i n g to quiet lines increases at the same t i m e due t o a s i m i l a r effect. T h i s c a n be s h o w n b y c o n n e c t i n g a n o i s y g r o u n d to the c i r c u i t a n d m e a s u r i n g the a m o u n t of a t t e n u a t i o n , as d e p i c t e d i n F i g u r e 3.10(b). I n this figure there has been a I n H i n d u c t a n c e o n s u p p l y lines t h a t resulted i n a n o i s y g r o u n d a n d supply. A s a result, the a m o u n t of noise a t t e n u a t i o n decreased s i g n i f i c a n t l y at higher frequencies due t o the increased c o u p l i n g of the c i r c u i t t o n o i s y lines. F u r t h e r m o r e , the l o c a l m a x i m u m observed i n F i g u r e 3.10(b) is a n evidence of the existence of the t w o c o m p e t i n g m e c h a n i s m s m e n t i o n e d above.  3.4  Noise versus Switching Time  A n o t h e r i m p o r t a n t p a r a m e t e r is the a m o u n t of noise as the s w i t c h i n g t i m e of the c i r c u i t changes. F i g u r e 3.11 depicts waveforms of s u b s t r a t e noise i n t i m e - d o m a i n for various i n p u t clock rise-times. T h e waveforms represented i n F i g u r e 3.11(a) show the case i n w h i c h there  Chapter- 3. Substrate Noise Characterization  36  35  30 CD C  o  '% 25 CD  • d=5 um •d=10u.m • d=50um •d=100um  20  ?00  400  600  800 1000 1200 Frequency (MHz)  1400  1600  (a) Dependence of coupling on the frequency (no noise on supplies).  500  1000 1500 Frequency (MHz)  2000  (b) Dependence of coupling on the frequency (noisy power supply). F i g u r e 3.10: A t t e n u a t i o n factor as a f u n c t i o n of frequency.  Chapter 3. Substrate Noise Characterization  37  t = 1ns r  t = 500ps t =100ps /:  1 \-' \  I; 1:  § 10  too  i \  .' J V  101  \  t =10ps .  i » \  102 103 Time (nsec)  104  105  (a) Without noise on supply lines.  50  9  i! i  •i  i  m  0  '! |!  -50  :: Ii r. ii  ,i H  : j 5  -100 100  t = 1ns  I  r  t = 500ps  = ! ' : 1 1 101  f  t =100ps 102 103 Time (nsec)  104  105  (b) W i t h noise on supply lines. F i g u r e 3.11: S u b s t r a t e noise waveforms for various clock rise-times.  is no i n d u c t a n c e i n s u p p l y lines, i.e., there is no s u p p l y noise, a n d F i g u r e 3.11(b) is the same e x p e r i m e n t b u t w i t h a n i n d u c t a n c e of I n H i n the s u p p l y p a t h , w h i c h has i n t r o d u c e d r i n g i n g . A s c a n be seen, there is no significant change i n the m a x i m u m value of the noise or even the waveform, w h i c h c a n be e x p l a i n e d u s i n g the fact t h a t the m a j o r c o n t r i b u t o r s to the noise are those parts of the c i r c u i t t h a t d r a w the largest a m o u n t of current f r o m the supplies, e.g., the o u t p u t stage, a n d since c h a n g i n g the i n p u t clock rise-time does not affect  Chapter 3. Substrate Noise Characterization  38  the rise-time of the o u t p u t stage, the noise has not changed significantly.  O n the other  450  1 5  °0  500  1000 1500 2000 2500 Output Stage Rise-Time (psec)  3000  F i g u r e 3.12: P e a k - t o - p e a k value of s u b s t r a t e noise as a f u n c t i o n of the rise-time of the last stage.  h a n d , i f the s w i t c h i n g t i m e of the o u t p u t stage changes, e.g., b y c h a n g i n g its c a p a c i t i v e l o a d , t h e n the peak-to-peak value of noise w i l l vary, as s h o w n i n F i g u r e 3.12. T h e flat p a r t of the p l o t shows the s i t u a t i o n i n w h i c h the noise of the o u t p u t stage is not d o m i n a n t ; therefore, a further increase i n its rise-time does not decrease the noise. B a s e d o n these observations, it c a n be c o n c l u d e d t h a t i n c r e a s i n g the s w i t c h i n g t i m e of the o u t p u t d r i v e r s is a n effective w a y of r e d u c i n g noise (however, at the expense of a slower system) b u t it does not help i f the noise due to those p a r t s is not d o m i n a n t .  Chapter 3. Substrate Noise Characterization  3.5  39  Effect of Substrate Type on Noise  As discussed in Chapter 2, substrate type plays an important role in noise behaviour, especially in noise propagation properties. Due to its resistive nature, the silicon substrate itself exhibits attenuation to some extent; however, the amount of attenuation depends on several parameters, such as substrate resistivity and structure. To characterize noise coupling in different substrates used in C M O S technology, first, two major types of silicon wafers will be reviewed, and the dependence of noise propagation on a number of process and layout parameters will be studied in the following sections.  3.5.1  Different Substrate Types  Figure 3.13 shows the two most commonly used substrate types in C M O S integrated circuits.  The lightly-doped substrate (shown in Figure 3.13(a)) is the simplest silicon  substrate in terms of manufacturability; however, owing to its high susceptibility to latchup, this type of wafer was replaced by epitaxial substrates (shown in Figure 3.13(b)) in older C M O S technologies. In an epitaxial wafer, a thin layer of silicon is deposited on top of a heavily doped bulk several hundred micrometers thick. Active devices are built into , this thin high-resistivity layer. This type of substrate circumvents the problem of latch-up and allows for better device performance due to the better controllability of the doping profile of the epitaxial silicon [64]. Currently, the most widely used wafer in digital C M O S applications is the epitaxial substrate. The heavily-doped portion has a resistivity of several milliohm-cm (mfi.cm). The resistance of the epitaxial layer is typically 2-3 orders of magnitude higher than the  Chapter 3. Substrate Noise Characterization  40  300pm P"-Bulk (15n.cm)  (a) A typical lightly-doped substrate.  i_ 10/im  P -Epi layer(15f2.cm)  NWell  300/mi P+-Bulk (0.05rml.cm)  (b) A typical epitaxial substrate (not to scale).  Figure 3.13: Two most commonly used silicon substrates. bulk substrate, i.e., its resistivity is in the same order as the resistivity of a lightly-doped substrate. Although epitaxial substrate has a better latch-up performance, there is a compromise between substrate noise attenuation and latch-up immunity depending on the thickness of the epitaxial layer; i.e., as the thickness of the epitaxial layer increases, the noise suppression of the substrate improves, while the latch-up characteristic deteriorates [65]. It should be noted that the scaling of CMOS technology and the use of lower supply voltages in new CMOS generations has decreased the probability of latchup. Additionally, lightly-doped substrates exhibit better R F performance, e.g., better on-chip spiral inductors, compared to their epitaxial counterparts [66]; therefore, recently, there has been an increasing interest in using lightly-doped substrates due to their lower manufacturing cost [35].  Chapter 3. Substrate Noise Characterization  41  Heavily-doped bulk  (b) Epitaxial substrate (not to scale) F i g u r e 3.14: R e s i s t i v e m o d e l l i n g of the substrate.  A s discussed before, the s u b s t r a t e is a resistive network; therefore, a s i m p l e resistive m o d e l c a n be used to a n a l y z e noise p r o p a g a t i o n b e h a v i o u r .  F i g u r e 3.14 i l l u s t r a t e s one  s i m p l e representation of such a m o d e l . A s s h o w n i n this figure, the h e a v i l y - d o p e d b u l k i n e p i t a x i a l substrates c a n be considered a single node due to the l o w r e s i s t i v i t y of the b u l k s i l i c o n [18]. T h i s is p a r t i c u l a r l y i m p o r t a n t i n the noise p r o p a g a t i o n b e h a v i o u r because this ' e q u i p o t e n t i a l layer ( h e a v i l y - d o p e d b u l k ) c a n act as the m a j o r noise p a t h f r o m d i g i t a l to a n a l o g nodes i n s t e a d of the surface p a t h t h r o u g h the e p i t a x i a l layer. T h e presence of the b u l k node is the m a i n reason for the different b e h a v i o u r of the noise dependence o n the layout p a r a m e t e r s i n the t w o types of substrate. It is also the  Chapter 3. Substrate Noise Characterization  42  basis for the development of l u m p e d - e l e m e n t m o d e l s for the substrate [18, 19] because the b u l k defines a single n o d e t h a t is c o n n e c t e d t o a l l devices t h r o u g h the resistances of the e p i t a x i a l layer; whereas, i n l i g h t l y - d o p e d substrates, the d i s t r i b u t e d n a t u r e of the s u b s t r a t e does not allow for s m a l l l u m p e d - e l e m e n t m o d e l s .  F r o m the m o d e l presented  i n F i g u r e 3.14, one c a n expect t h a t i n l i g h t l y - d o p e d substrates, i n c r e a s i n g the d i s t a n c e between d i g i t a l a n d a n a l o g nodes decreases the a m o u n t of c o u p l i n g because of the increase i n the i m p e d a n c e of the noise p a t h , whereas i n e p i t a x i a l wafers, i n c r e a s i n g the s e p a r a t i o n is not a n effective way, since the noise propagates m o s t l y t h r o u g h the h e a v i l y - d o p e d b u l k t h a t has negligible resistance.  3.5.2  Noise Behaviour in Different Substrates  F i g u r e 3.15 shows the dependence of noise a t t e n u a t i o n factor o n the distance between d i g i t a l a n d a n a l o g c i r c u i t s i n b o t h t y p e s of substrate.  A s c a n be seen, the a t t e n u a t i o n  m o n o t o n i c a l l y increases i n l i g h t l y - d o p e d substrates as the d i s t a n c e increases, w h i l e i n the , e p i t a x i a l substrates, i n c r e a s i n g the distance above a c e r t a i n l i m i t does not increase the a t t e n u a t i o n of the noise. T h e increase i n noise a t t e n u a t i o n at short distances i n the e p i t a x i a l substrate c a n be a t t r i b u t e d t o the fact t h a t at short distances a significant p o r t i o n of noise propagates t h r o u g h the h i g h - r e s i s t i v i t y e p i t a x i a l layer; therefore, there is no difference between the ' p r o p a g a t i o n b e h a v i o u r of l i g h t l y - d o p e d a n d e p i t a x i a l substrates; however, w i t h the i n crease i n s e p a r a t i o n , the noise penetrates m o r e t h r o u g h the b u l k , hence r e d u c i n g the effect of surface a t t e n u a t i o n .  A s a rule of t h u m b , i n c r e a s i n g the d i s t a n c e between the  d i g i t a l a n d a n a l o g nodes b e y o n d 4 times the thickness of the e p i t a x i a l layer has a negli-  Chapter 3. Substrate Noise Characterization  100 Distance (um)  50  43  200  150  _ 3 0 co C  o  Epitaxial substrate  *= 2 5 CD  <  20  f  0  J  1  20  40  1  1  60 80 Distance (um)  L  100  120  F i g u r e 3.15: A t t e n u a t i o n factor as a f u n c t i o n of the distance between a n a l o g a n d d i g i t a l nodes i n t w o types of s u b s t r a t e ( N o t e t h a t the scales are different.)  gible i m p a c t o n the noise a t t e n u a t i o n [18]. T h i s c a n also be e x p l a i n e d u s i n g the s i m p l e resistive m o d e l s of F i g u r e 3.14.  B a s e d o n the e p i t a x i a l s u b s t r a t e m o d e l , i n c r e a s i n g the  p h y s i c a l s e p a r a t i o n does not increase the resistance of the noise p a t h ; thus no further noise a t t e n u a t i o n is p r o v i d e d . A n o t h e r p a r a m e t e r of interest is the dependence of noise on the r e s i s t i v i t y of the b u l k i n l i g h t l y - d o p e d substrates.  F i g u r e 3.16 depicts the s i m u l a t i o n results of the inverter  c i r c u i t for different values of s u b s t r a t e r e s i s t i v i t y . T h e a t t e n u a t i o n factor at large p h y s i c a l separations has a d  a  b e h a v i o u r , w i t h a d e p e n d i n g o n the r e s i s t i v i t y of the b u l k . T o j u s t i f y  this effect, a n u n d e r s t a n d i n g of the dependence of the s u b s t r a t e resistance o n the d i s t a n c e between two p o i n t s is r e q u i r e d .  A l t h o u g h the c a l c u l a t i o n of the a c t u a l resistance i n a  real c h i p is q u i t e c o m p l e x due to the effects of various parameters i n c l u d i n g n e i g h b o u r i n g  Chapter  3. Substrate Noise  44  Characterization  Bulk resistivity = 1 0 Q . c m B u l k resistivity = 1 5 Q . c m B u l k resistivity = 2 0 £ X c m 50  100 Distance (um)  150  200  F i g u r e 3.16: T h e dependence o f t h e a t t e n u a t i o n factor o n t h e r e s i s t i v i t y of t h e b u l k i n l i g h t l y - d o p e d wafers.  contacts a n d devices, i n a s i m p l e case o f o n l y t w o contacts (shown i n F i g u r e 3.17) o n a l i g h t l y - d o p e d substrate, t h e following e q u a t i o n c a n be used [67]:  kdgmd  Rij —  where a a n d k are process-dependent  fitting  (3.22)  parameters, areai a n d areaj  are t h e areas of  the contacts, a n d d d is t h e geometric m e a n distance between t h e t w o contacts, defined gm  as: dgmd —  SL2 fw SL! V 3  r.dx .dy .dx .dy  Wi.Li.W2.L2  1  1  2  2  (3.23)  E q u a t i o n 3.22 implies a linear increase i n t h e resistance at large distances a n d faster t h a n l i n e a r at short distances [67]; thus t h e observed b e h a v i o u r i n F i g u r e 3.16 is i n c o m p l i -  Chapter 3. Substrate Noise Characterization  H  W  2  45  »4  F i g u r e 3.17: I l l u s t r a t i o n of g e o m e t r i c m e a n d i s t a n c e  {d d). gm  ance w i t h the e q u a t i o n of the resistance, v e r i f y i n g t h a t the t o t a l a t t e n u a t i o n is p r o p o r t i o n a l t o the resistance of the s u b s t r a t e p a t h . I n e p i t a x i a l substrates, the s t u d y of the r e l a t i o n s h i p between the a m o u n t of the a t t e n u a t i o n a n d the thickness of the e p i t a x i a l layer is i n s t r u c t i v e . O n e c a n expect increased ' a t t e n u a t i o n i n t h i c k e r e p i t a x i a l layers due to the increased resistance of the noise p a t h t o sensitive devices. T h i s result c a n also be c o n c l u d e d from F i g u r e 3.18, w h i c h shows the s i m u l a t i o n results for three different e p i t a x i a l layer thicknesses. T y p i c a l l y , the higher the r e s i s t i v i t y of the s u b s t r a t e the b e t t e r the i s o l a t i o n perform a n c e ; therefore, l i g h t l y - d o p e d substrates m a y seem t o be advantageous i n t e r m s of noise ' suppression. H o w e v e r , there are c o n t r o v e r s i a l v i e w s o n t h i s argument; the conflict arises from the c o m p r o m i s e between two basic m e c h a n i s m s t h a t c o n t r o l noise a t t e n u a t i o n .  In  general, the a m o u n t of noise at sensitive nodes c a n be r e d u c e d either b y d i r e c t i n g the noise t o a quiet line (such as s u p p l y or g r o u n d line) or the noise s h o u l d be a t t e n u a t e d o n its w a y t o a n a l o g nodes (e.g, b y the resistance of the substrate).  T h e high resistivity substrate  Chapter  3. Substrate Noise  46  Characterization  •Epi thickness = 7 u m • E p i t h i c k n e s s = 10u.m • E p i t h i c k n e s s = 15u.m 40  60 80 Distance (um)  120  Figure 3.18: The dependence of the attenuation factor on the thickness of the epitaxial layer.  seems to be better in the sense that its higher impedance results in more attenuation of noise on its path from the digital source to the analog circuit. O n the other hand, a heavily doped substrate provides a low impedance path that can transfer noise to the ground, hence decreasing the effect of the noise on analog blocks [68].  3.6  PMOS versus NMOS  Since P M O S devices are capacitively isolated from the substrate by the underlying n-well, one may think that they are less susceptible to substrate noise. To verify this argument, a P M O S was used as a sensitive device, and the results were compared to that of an N M O S . The additional attenuation provided by P M O S as a function of frequency is plotted in  Chapter 3. Substrate Noise Characterization  47  Figure 3.19. Based on this figure, P M O S has significantly better noise isolation; however, the advantage is compromised as the frequency increases due to the capacitive behaviour of the isolation. The considerable amount of noise attenuation in P M O S even at high  70 r 65|60-  co  '(3 55C  CD  < 50 454  °0  200  400 600 Frequency (MHz)  800  1000  Figure 3.19: Frequency dependence of the additional attenuation provided by P M O S .  frequencies suggests that it is beneficial to use P M O S for sensitive nodes of the circuit such as the input stage transistors of an L N A from the substrate noise point of view . However, one should be aware of the inferior performance of P M O S as compared to N M O S , due to the lower mobility of carriers, which leads to lower transconductance values and, consequently, a lower gain and a larger overall noise figure.  3.7  Summary  In this chapter, various aspects of substrate noise were studied. The dependence of supply/ground noise on switching activity and package parasitics were analyzed. Further-  Chapter 3. Substrate Noise Characterization  48  more, it was shown that using the same supply line for analog and digital circuits will substantially increase the amount of substrate noise, mainly because supply lines will add an additional source of the noise to analog circuits. It was also shown that the effect of external noise sources can be mitigated using lower-inductance packages, even though, this will not be helpful if internal noise sources are dominant; a situation that requires other techniques (e.g., lowering the switching time of the output drivers) to decrease the amplitude of the noise. It was shown that the substrate type has a crucial influence on the behaviour of the noise; therefore, the effect of various parameters such as substrate resistivity and thickness (for epitaxial wafers) on noise propagation properties was also studied. Finally, it was shown that P M O S devices have better substrate noise performance as compared to N M O S transistors, due to the extra isolation provided by their underlying n-well. However, two considerations should be taken into account: first, P M O S is typically inferior to N M O S in terms of device performance, due to its lower carrier mobility and, second, the advantage decreases as the frequency of operation increases.  49  Chapter 4 M o d e l l i n g the Effect of Substrate Noise Substrate noise affects analog circuits in a multitude of mechanisms. Body effect is one of them, which is defined as the modulation of the threshold voltage of a M O S device due to variations in the source-bulk potential. It is shown that with body effect, the threshold voltage of a M O S transistor can be written as:  (4.1)  where V ho is the threshold voltage when source-bulk potential is zero, e i is the substrate t  dielectric permittivity, N  S  A  is the substrate doping, C  ox  is the gate oxide capacitance per  unit area, <£/ is the surface inversion potential, and V b is the source-bulk potential. Vari3  ations of Vth will impact both the large and small-signal behaviour of the device; i.e., it changes the drain current as well as the transconductance of the M O S transistor.  The  influence of body effect is typically accommodated in the small-signal model with an additional voltage-controlled current source connected between the drain and source terminals of the device.  Chapter 4. Modelling the Effect of Substrate Noise  50  In addition to body effect, substrate noise can directly couple to the analog nodes through supply lines and the neighbouring supply or substrate contacts and junction capacitances; however, here we assume that the supply lines of the analog and digital parts are separated; therefore, the common substrate is the main means of communication between noisy digital and sensitive analog nodes. This chapter begins with a review of the M O S device noise model. Next, a modified version of the existing model is introduced that incorporates substrate noise effects. F i nally, the impact of substrate noise on a typical L N A is studied based on the proposed model.  4.1  Noise Modelling in MOS Devices  A simplified M O S F E T small-signal model, including device intrinsic noise sources, is shown in Figure 4.1, where all internal noise sources are combined and represented by a single noise source at the output [69].  1  Figure 4.1: M O S F E T small-signal model, including device internal noise sources (no substrate noise modelling or body effect). ^ h e reader is invited to refer to Appendix A for the full development of this model.  51  Chapter 4. Modelling the Effect of Substrate Noise  T w o m a j o r device noise sources have been i n c o r p o r a t e d i n t h i s figure: channel thermal noise a n d gate-induced noise.  T h e c u r r e n t source, i d , n  g  represents t h e effect o f b o t h o f  these noises a n d is g i v e n b y : i-ndg  =  where g  m  9mZg i g  + T)i d  S n  (4-2)  n  is t h e t r a n s c o n d u c t a n c e of t h e device, i d a n d i n  g a t e - i n d u c e d noises, respectively, a n d Z  a n d 77 are g i v e n b y :  gs  Z  =  represent c h a n n e l t h e r m a l a n d  ng  1 "  || Zdeg + Z  (4.3)  g  sC  1+  gs  T) — 1 — ( ^ ^ m  g Zdeg m  d e 9  \Z  (4-4)  B a s e d o n E q u a t i o n 4.2, t h e mean-square value (i.e., power) o f t h e noise, w h i c h is a m o r e m e a n i n g f u l q u a n t i t y i n noise a n a l y s i s , c a n b e f o u n d as:  i ndg — inc ind 2  9  =  i nd(\v\ 2  2  + 2Re{c  ng  n  9  9S  nd  J  1  nd  n  9m\ 17 gs\ 2  Zj  I  2  (4.5)  where c is t h e c o r r e l a t i o n coefficient between c h a n n e l t h e r m a l noise a n d g a t e - i n d u c e d noise: nd ng  %  c =  %  (4.6)  nd ng 0  W e define device noise coefficient ( D N C ) as a measure of h o w i n t r i n s i c device noise sources are scaled w h e n t h e y are transferred t o t h e o u t p u t ;  DNC =  t^1 nd  \n\ + 2 i ? e | c 2  \  ^g nd  m V  therefore:  *Z  g s  \  ^Lg \Zgi 2  +  2  m  (4.7)  nd  T h e m o d e l s h o w n i n F i g u r e 4.1 c a n b e used i n t h e noise figure c a l c u l a t i o n o f a g i v e n c i r c u i t ; however, i t does n o t account for t h e effect of s u b s t r a t e noise, s i m p l y because i t  Chapter 4. Modelling the Effect of Substrate Noise neglects b o t h the s u b s t r a t e noise source a n d b o d y effect.  52  I n the f o l l o w i n g section, we  i n c l u d e the effect of s u b s t r a t e noise i n the current m o d e l , to derive a general m o d e l for s u b s t r a t e noise analysis purposes.  4.2  M O S F E T Small-Signal Model Including Substrate Noise Effects  T h e i m p a c t of s u b s t r a t e noise c a n be a d d e d b y m o d e l l i n g it w i t h a voltage source connected t o the s u b s t r a t e of the M O S device, as s h o w n i n F i g u r e 4.2. A n e w t e r m i n a l is a d d e d to  G r -o  •n  +  •a  V gs •  Cgs  D lout  Q"mVgs  Cb s  B' ©  v \\z s  deg  F i g u r e 4.2: S m a l l - s i g n a l m o d e l of a M O S F E T , i n c l u d i n g device i n t e r n a l noise sources, s u b s t r a t e noise a n d b o d y effect.  the p r e v i o u s m o d e l representing the b u l k n o d e a n d is connected t o v  ns  noise source.  as the s u b s t r a t e  C b is also a d d e d to F i g u r e 4.2 because it is the largest c a p a c i t o r a m o n g S  a l l s u b s t r a t e p a r a s i t i c capacitances t h a t connect the b u l k node t o transistor's t e r m i n a l s . It s h o u l d be n o t e d t h a t here we have t a c i t l y assumed t h a t i n c l u d i n g b o d y effect has a negligible i m p a c t o n E q u a t i o n 4.5; therefore, i d n  g  i n this figure is the same as F i g u r e 4.1.  Chapter 4. Modelling the Effect of Substrate Noise  53  ^out  Cb s  \ s  +  F i g u r e 4.3: S i m p l i f i e d v e r s i o n o f F i g u r e 4.2. S i m i l a r t o t h e previous section, t h e effect o f t h e a d d i t i o n a l noise source, v , c a n b e ns  c o m b i n e d w i t h t h e i n t e r n a l noise sources, i d , i n order t o have a single source representing n  a  a l l e x i s t i n g noises i n t h e device. T o find t h e o u t p u t noise c u r r e n t d u e t o s u b s t r a t e noise, we s i m p l i f y F i g u r e 4.2 t o o b t a i n F i g u r e 4.3, where Z is t h e t o t a l i m p e d a n c e seen at t h e s  source t e r m i n a l : Z  S  = (Zg +  •'deg  sG  (4.8  a n d K is given b y :  K =  ~9n  sC (R gs  + sL ) + 1  s  (4.9)  g  B a s e d o n t h i s figure, we c a n c a l c u l a t e t h e o u t p u t noise current d u e t o t h e s u b s t r a t e noise. T h e f o l l o w i n g equations c a n b e w r i t t e n :  2  tout = KV + g V S  mb  (4.10)  bs  Vs  sC,sb  (4.11)  + v;  Note that since we are interested in the transfer function from v sources including i d should be disabled.  (4.12)  2  ns  n  g  to the output, all other independent  Chapter 4. Modelling the Effect of Substrate Noise where i  out  54  is the output current of the device (drain current), i is the current through s  C , and V is the source potential. B y manipulating Equations 4.10-4.12, we have: sb  s  iout _ 9mb(sC + l/Z ) + sC {K - g ) sb  v  s  sb  (4.13)  mb  sCsb + 1/Z - K + g  ns  S  mb  Similar to D N C , we define substrate noise coefficient (SNC) as:  S  N  C  =  t p = V ns  \9mb(sC + l/Zs) + sC {K - g ) sb  sb  mb  sC + l/Zs - K + g sb  (4.14)  mb  Consequently, a modified version of the total noise current, including the effect of substrate noise, would be:  3  ^  s  =D N C x ^  d  +SNCx^  (4.15)  n s  where the first and the second terms on the right-hand side represent the effect of device and substrate noise, respectively. The final model is the same as Figure 4.1, except that the noise current source,  id, n  g  will be modified to  id , n  gs  given by Equation 4.15. The reader  may wonder why the final model does not include body effect and C . These components sb  were omitted because it is assumed that they have negligible effect on the transfer function from the input to the output; nonetheless, their effect in the transfer function from the substrate to the output is already taken into account by  i d s2  n  g  It should be noted that here we have assumed that the internal noise sources and the substrate noise are uncorrelated. 3  Chapter 4. Modelling the Effect of Substrate Noise  4.3  55  Noise Figure Calculation  The model developed i n the previous section can be used to study the effect of substrate noise on an inductively-degenerated L N A as a sample analog circuit. The purpose of using such L N A as a benchmark for our analysis is twofold: first, L N A s are among the most sensitive analog circuits to noise because of the extremely low amplitude of the signal at their input.  4  Second, this type of L N A is the most commonly used topology in practice;  therefore, it can well represent one of the critical blocks in mixed-signal SoCs. Figure 4.4 shows a generic schematic of such an amplifier. lout  Figure 4.4: A typical inductively-degenerated L N A .  In this circuit, Lri is used to create a real component in the input impedance of the eg  circuit that can be tuned for input impedance matching and L is included to control the g  resonance frequency. In general, the noise factor, F, of an amplifier is defined as:  p _  Total output noise power Output noise due to input source  _  i  t(tot)  2 nou  i  2  ,^  ^  , r,„> +  / b\J tt/b \ bib )  To calculate 4  i t(tot) nou  and  i out(in), n  we refer to the M O S small-signal model introduced in the  As an example, the power of GPS signal can be as low as -130dBm [70].  Chapter  4.  Modelling  the Effect of Substrate  Noise  56  V, ir  F i g u r e 4.5: Small-signal m o d e l of an inductively-degenerated L N A . previous section, based on which, we construct the small-signal m o d e l of the inductivelydegenerated L N A as shown i n Figure 4.5. A s s u m i n g that the amplifier is matched to the output resistance of the input source, R , we have: s  V  =  — R  +  s  (—— Zi  JUJQC,as  n  1  2R ju, <V  u C 2R T  v  S  ^ nout(in)  where e  ns  0  ga  ~  a  7  (9.\-  ^ ^nout(in) 2  0  9m\ • j^-ns J  =  {9mQ) C  (4.17)  2 n  is the input noise of the L N A (due to R ), LOQ is the center frequency, and Q is a  the quality factor of the input network of the amplifier. Therefore, the noise factor w i l l be:  F  J9mQ)  s  &2 n  "F l^ndgs _ ^ _|_  (g Q) e  2  m  Recalling i d 2  n  gs  ^ndgs  (g Q) e  2  2  (4.18)  m  from E q u a t i o n 4.15, we have:  F= 1 +  D N C x i\d (9mQ)  + SNC x 2  x e  2  v\  (4.19)  Chapter 4. Modelling the Effect of Substrate Noise  57  w h i c h c a n be w r i t t e n i n t h e following f o r m :  F = 1 + DNF(Q) + S N F  W  (4.20)  )  w h e r e D N F ( Q ) a n d S N F ( Q ) are the d e v i c e a n d s u b s t r a t e noise factors, r e s p e c t i v e l y .  DNF(Q)  accounts for t h e effect of i n t e r n a l noise sources of t h e d e v i c e , whereas S N F ( Q ) shows t h e 5  c o n t r i b u t i o n of s u b s t r a t e noise; more specifically, S N F ( Q ) is g i v e n b y the f o l l o w i n g e q u a t i o n :  where k is B o l t z m a n n ' s constant a n d T is t h e t e m p e r a t u r e .  T h i s e q u a t i o n shows t h e effect  of s u b s t r a t e noise o n t h e noise figure of the L N A . F u r t h e r m o r e , as w i l l be discussed shortly, it reveals t h e trade-off between s u b s t r a t e noise a n d i n t r i n s i c device noise m i n i m i z a t i o n . F i g u r e 4.6 depicts D N F as a f u n c t i o n of Q i n a t y p i c a l L N A i n 0 . 1 8 ^ m t e c h n o l o g y for . different values of c. A s defined i n E q u a t i o n 4.17, Q is t h e q u a l i t y factor of t h e i n p u t n e t w o r k of t h e L N A . Since Q is inversely p r o p o r t i o n a l t o C , gs  a w i d e r transistor.  a lower Q corresponds t o  A s c a n be seen, for a given c, a n o p t i m u m Q exists t h a t yields t h e  m i n i m u m D N F ( Q ) ; thus, t h e overall noise figure w o u l d also be m i n i m u m ( a s s u m i n g t h a t there is n o s u b s t r a t e noise). However, i n m a n y cases, u s i n g t h i s o p t i m u m Q leads t o a ' large power c o n s u m p t i o n i n t h e device; therefore, designers m a y consider u s i n g a higher Q t o decrease power c o n s u m p t i o n , w h i c h as i m p l i e d b y F i g u r e 4.6, entails increased noise figure from device noise perspective. T o further s t u d y t h e effect of s u b s t r a t e noise, various L N A s w i t h different Q values 3  For the complete equation of DNF(Q) please refer to [69].  Chapter 4. Modelling the Effect of Substrate Noise  | 0.2 0 1  ' 2  1  4  1  Q  6  58  c=0.8j | 1  1  8  10  Figure 4.6: Normalized device noise factor as a function of Q for different values of c.  were designed in 0.18//m technology.  The topology of the circuit was the same as the  one shown in Figure 4.4. A n additional M O S transistor was used as cascode device to increase the isolation between the input and the output and also reduce Miller effect. To analyze the effect of substrate noise, it is instructive to study the dependence of S N F on Q in Equation 4.21. The required data for this study such as the value of parasitic elements and transconductance of the input device were extracted from simulation results of the designed L N A s . B y substituting values in Equation 4.14 and using the results in Equation 4.21, we obtain S N F as shown in Figure 4.7. A s depicted in this figure, S N F appears to be a decreasing function of Q. Indeed, considering the fact that C , gs  g, m  and  g b are inversely proportional to Q, one can show that S N F is a decreasing function of Q. m  The behaviour of S N F with respect to Q reveals an important compromise between  Chapter 4. Modelling the Effect of Substrate Noise  59  substrate noise and device noise m i n i m i z a t i o n . A s shown i n Figure 4.7, SNF(Q) exhibits an opposite trend as compared to D N F ( Q ) , i.e., substrate noise effect is more significant at low values of Q, whereas at high values of Q the dominant noise mechanism would be the intrinsic noise of the device.  Figure 4.7: N o r m a l i z e d substrate noise factor as a function of Q .  To verify the preceding argument, the L N A s were simulated using Agilent A d v a n c e d Design System ( A D S ) simulator.  T o include substrate noise effect a noise source was  connected to the bulk node of the input transistor and the resulting noise figure was measured. Figure 4.8 depicts the noise figure for various levels of substrate noise and Qs. A s can be seen, at low values of Q , substrate noise is dominant; however, as Q increases the p o r t i o n of the noise figure due to substrate noise decreases substantially. O n the other hand, at high values of Q , device noise starts dominating.  Chapter  4. Modelling  the Effect of Substrate  Noise  60  2.5  -e-SN=0 -A-SN=4 -»-SN=16 -»-SN=25  2 CQ  o 1.5h  0.5  0. 0  2  4  6 Q  8  10  12  F i g u r e 4.8: N o i s e figure as a f u n c t i o n of Q . T h e s p e c t r a l d e n s i t y of s u b s t r a t e noise is g i v e n  in  V /Hz. 2  T h e noise figure as a f u n c t i o n of frequency is p l o t t e d i n F i g u r e 4.9 for t w o different Qs. T h i s figure conveys i m p o r t a n t i n f o r m a t i o n a b o u t t h e b e h a v i o u r of t h e noise  figure.  F i r s t , as e x p e c t e d , t h e effect of s u b s t r a t e noise is less i n F i g u r e 4.9(b) ( w h i c h corresponds to a c i r c u i t w i t h a higher Q ) . A n o t h e r i m p o r t a n t result is t h a t a frequency  (f t) exists op  at w h i c h t h e noise figure i n the presence of s u b s t r a t e noise is a l m o s t t h e same as t h a t w i t h o u t a n y s u b s t r a t e noise. T o elaborate more o n this p o i n t , i t s h o u l d be n o t e d t h a t a l l L N A s were designed for 1 . 5 G H z , however,  f  opt  is observed at 1.4GFfz, w h i c h means t h a t power m a t c h i n g a n d  noise suppression have n o t o c c u r r e d at t h e same frequency. A more careful s t u d y of these figures shows t h a t i n t h e absence of s u b s t r a t e noise t h e m i n i m u m noise figure is achieved at 1 . 6 G H z w h i c h is s t i l l different from t h e center frequency. T h i s d i s c r e p a n c y was e x p e c t a b l e  Chapter 4. Modelling the Effect of Substrate Noise  61  7  O  1  1  1  1  1.2  1  1.4 1.6 Frequency (GHz)  1.8  2  (a) Noise figure as a function of frequency (Q=1.8).  7  1  1  1  1  SN=25  6  /  SN= 1 6 \ ^ ^ ^ ^ ^ ^ y /  -  -  SN=4  /  SN=0  \V  \^  opt  /  / /  f  ^ ^ ^ ^  011  1  ,  1  1.2  ,  1.4 1.6 Frequency (GHz)  ,  1.8  2  (b) Noise figure as a function of frequency (Q=10).  Figure 4.9: Comparison of noise figure for different Qs. (The spectral density of substrate noise is given in V /Hz.) 2  Chapter 4. Modelling the Effect of Substrate Noise  62  because our design method is based on the power matching at center frequency and not on the noise matching. In fact, this type of behaviour is commonly encountered in L N A design. Various L N A design methodologies are either based on noise or input matching or they try to balance these two parameters [69, 70]. However, as suggested by the results of 6  this section, the effect of substrate noise can be minimized by compromising the amount of device noise or power matching.  4.4  Summary  In this chapter, M O S F E T small-signal model was revisited. A new small-signal model was proposed that accommodates the effects of substrate noise. Based on this model, the noise performance of an inductively-degenerated L N A was studied. It was shown that increasing the quality factor of the input network alleviates substrate noise problem to some extent, but at the same time increases the effect of device noise sources.  Based on the results in this chapter, to achieve the best noise performance  substrate noise effect should be taken into account since it changes the overall noise figure characteristic of the amplifier, i.e, merely considering the effect of device noise will result in solutions that may exhibit poor substrate noise performance.  6  I n some cases, power consumption requirement is also added to the matching criteria.  63  Chapter 5  E v a l u a t i o n of R e d u c t i o n M e t h o d s Substrate noise cannot be eliminated completely, but its deleterious effects can be controlled or minimized. Many noise reduction methods have been used by analog designers to mitigate the influence of the noise; however, the effectiveness of these techniques de' pends on a multitude of parameters, such as the properties of the substrate, the circuit's clocking scheme, etc., that need to be studied in order to implement them properly. In general, substrate noise reduction methods can be categorized into three different classes: the first class consists of methods aimed at reducing the noise generated by digital blocks; the second class focuses on reducing the noise propagated through the substrate, and the last class tries to design noise-tolerant analog circuits. In this thesis, these classes will be referred to as noise injection reception  reduction,  noise propagation  reduction,  and  noise  reduction.  This chapter provides a review of noise reduction techniques.  Since each of these  methods can be a topic for a separate research, only a brief introduction to some of them is given, except for more detailed studies of two popular techniques, namely switching activity spreading and the use of passive guard-rings (GRs), from the first and the second classes, respectively.  Chapter 5. Evaluation of Reduction Methods  5.1  64  Noise Injection Reduction  In general, techniques used i n low-power design c a n be used to reduce s w i t c h i n g noise, especially i f t h e y a t t e m p t t o reduce c i r c u i t a c t i v i t y . However, care s h o u l d be t a k e n since i n some cases u s i n g low-power techniques c a n even aggravate the noise [40]. A s a n e x a m p l e of a low-power technique, lower power supplies c a n be used for d i g i t a l p a r t s (not a n a l o g p a r t s ) .  A lower s w i n g for d i g i t a l nodes decreases the  instantaneous  current d r a w n f r o m the s u p p l y ; also use of a larger s u p p l y for a n a l o g c i r c u i t s increases t h e i r relative noise m a r g i n [56]. O n e disadvantage of u s i n g this technique is t h a t it m a y cause increased delay i n logic gates, w h i c h reduces the speed of the c i r c u i t ; however, it , s h o u l d be n o t e d t h a t i n a logic b l o c k not a l l the gates need to s w i t c h q u i c k l y ; therefore, less c r i t i c a l gates c a n be o p e r a t e d w i t h lower s u p p l y voltages. A n o t h e r disadvantage of t h i s m e t h o d is the e x t r a r o u t i n g a n d package pins r e q u i r e d for different s u p p l y lines o n the c h i p , w h i c h are not favourable i n i n t e g r a t e d c i r c u i t s . S w i t c h i n g a c t i v i t y s p r e a d i n g is a n o t h e r technique t h a t changes the s u p p l y current ' w a v e f o r m b y i n t r o d u c i n g delays i n t o the c l o c k d i s t r i b u t i o n network.  T h i s w i l l spread  the s w i t c h i n g a c t i v i t y of logic gates i n t i m e , thus r e d u c i n g the n u m b e r of s i m u l t a n e o u s l y s w i t c h i n g gates. Since this technique i n t r o d u c e s design c o m p l e x i t y i n large d i g i t a l c i r c u i t s , the i d e a c a n be a p p l i e d o n l y t o those p a r t s of the c i r c u i t t h a t c o n t r i b u t e the most t o the noise, such as blocks t h a t d r i v e large c a p a c i t i v e loads.  F u r t h e r m o r e , a l t h o u g h this  ' technique has been p r o v e n useful i n the t i m e - d o m a i n , its efficiency for R F a p p l i c a t i o n s , i.e., i n f r e q u e n c y - d o m a i n , needs to be verified.  Chapter 5. Evaluation of Reduction Methods  5.1.1  65  Switching Activity Spreading  Figure 5.1 illustrates the idea of switching activity spreading (SAS). In staggered digital 1  circuits, part of the switching gates will be triggered with a properly delayed clock with respect to the rest of the circuit; therefore, the number of simultaneously switching gates will be reduced. Input Clock  Clock Region I  Clock Region III  Figure 5.1: Switching activity spreading.  To investigate the effectiveness of this technique, the following experiment was performed. First, two chain of inverters were simultaneously switched, and the noise waveform was observed at the bulk node of a single transistor used as the noise sensor. Next, the same experiment was repeated by applying S A S , i.e., the clock signal of one of the chains was delayed by \ of the clock period with respect to the other one. The results of both experiments are shown in Figure 5.2. A s can be seen in Figure 5.2(a), the peak value of the noise has decreased by almost a factor of 2. In addition to time-domain waveforms, the frequency content of the noise in both cases is shown in Figure 5.2(b). This graph reveals an important point; i.e., even though the noise frequency content has considerably decreased at some frequencies, this result is not a general rule. For example in Figure 5.2(b), the noise content at 650MHz has remained 1  Also known as activity staggering.  Chapter 5. Evaluation of Reduction Methods  400 600 Frequency (MHz)  20 Time (nsec)  (a) Noise waveform in time-domain.  66  1000  (b) Frequency content of the noise.  Figure 5.2: Effect of S A S in time and frequency domains. almost unchanged after applying S A S . Therefore, care should be taken in R F applications to make sure that S A S decreases the in-band noise.  5.2  Noise Propagation  Reduction  Another noise reduction method is to prevent the noise from propagating through the substrate. Two strategies can be used: one is to increase the attenuation of the noise path, and the other one is to block the noise propagation. The simplest reduction scheme to increase the attenuation of the noise path is to increase the physical distance between the digital and analog circuitry. The efficiency of this technique was discussed in Chapter 3, where it was shown that the effectiveness of physical isolation is limited to lightly-doped substrates; moreover, this technique involves wasting of precious silicon area; therefore, several alternative methods have been exploited. Many of these techniques, such as the use of G R s , trenches, buried n-wells are studied in the literature [32, 65, 71]. It should  Chapter 5. Evaluation of Reduction Methods  67  be noted that all of these techniques, except for passive guard-rings, require additional process features that might not be available or economically viable in all technologies. So far, passive G R s have been the most commonly used technique due to their effectiveness and relative simplicity; therefore, we will review their properties i n more detail.  5.2.1  Passive Guard-Rings  Passive guard-rings are protective structures located around either the noise generating or sensitive blocks and are connected to dedicated supplies. There are two types of G R s : p  +  and n-well G R s , which operate based on totally different principles, although their  purpose is the same. p  +  G R provides a low-impedance path to the ground so that the noise travelling  through the substrate is directed mainly to the ground before reaching sensitive devices. , O n the other hand, n-well G R tends to increase the impedance of the noise path, which will effectively push the noise into deep parts of the substrate and provide a higher impedance path or equivalently, more attenuation. In both cases, the G R is more effective if most of the noise travels through the surface of the chip. Some of the following questions may arise during the course of G R design:  • How do the properties of the G R change with frequency?  • W h a t are the optimum dimensions of the G R ?  • Where should it be placed?  • Should the G R fully enclose the noisy or sensitive part?  Chapter 5. Evaluation of Reduction Methods  68  • How does the substrate type affect the efficiency of the G R ?  SeismIC simulation results presented in the following sections reveal that in all cases the use of G R s significantly helps decreasing the amount of noise; therefore, passive G R s are an effective way to reduce substrate noise. To study G R properties, a simple lumped model representation of p  +  and n-well G R s will be used, as shown in Figure 5.3. In this  figure, Rsub represents the substrate resistance, RGR is the resistance of the G R , RA and CA are the resistance and capacitance connecting the bulk of the sensitive device to the substrate, and RL is the lateral resistance between G R and the noise sensing node. In the ' n-well G R model (shown in Figure 5.3(b)) CQR is added to reflect the capacitance of the n-well to the substrate. P+ GR  Digital  Analog  p+ GR  p~ substrate  (a) p  +  G R enclosing sensitive devices.  Digital  n-woll GR Analog  p  I  n-woll GR  substrate  (b) n-well GR enclosing sensitive devices.  Figure 5.3: Lumped model of G R s in lightly-doped substrates.  It can be shown that in p  +  G R s , the lower the impedance of the G R (RGR) the better  Chapter 5. Evaluation of Reduction Methods the noise suppression performance.  69  I n fact, the i m p o r t a n t parameters, w h i c h d e t e r m i n e  the efficiency of the G R , are the ratios of the G R i m p e d a n c e to the i m p e d a n c e of the s u b s t r a t e a n d the i m p e d a n c e c o u p l i n g the sensitive node to the substrate.  O n the other  h a n d , i n n - w e l l G R s , a higher G R i m p e d a n c e is m o r e favourable, because the increased i m p e d a n c e w i l l p u s h the noise t o deep p o r t i o n s of the substrate,  hence i n c r e a s i n g the  overall i m p e d a n c e of the noise p a t h a n d consequently, increase the a t t e n u a t i o n .  Frequency Dependence of GR Properties T h e G R m o d e l i n t r o d u c e d i n the previous section suggests t h a t i n p  +  G R s , the effectiveness  of the G R decreases as the frequency increases because the r a t i o of the i m p e d a n c e of the G R to the i m p e d a n c e of the sensitive node increases; therefore, less noise is d i r e c t e d t o the g r o u n d t h r o u g h the G R . O n the other h a n d , i n the case of n-well G R , t h i s m i g h t not be t r u e because t w o c o m p e t i n g m e c h a n i s m s exist t h a t c o n t r o l the i m p e d a n c e r a t i o . W h i l e the c o u p l i n g of sensitive nodes to the s u b s t r a t e increases at higher frequencies, at the same , t i m e the i m p e d a n c e of the G R decreases, w h i c h c a n effectively decrease the i m p e d a n c e r a t i o . T h e s e arguments were investigated u s i n g S e i s m I C s i m u l a t i o n results for a c h a i n of inverters. F i g u r e 5.4 shows s i m u l a t i o n results of the a m o u n t of noise a t t e n u a t i o n for various G R arrangements. T o c o m p a r e the effectiveness of G R s , the a m o u n t of a d d i t i o n a l i s o l a t i o n p r o v i d e d b y each G R c o n f i g u r a t i o n as a f u n c t i o n of frequency is s h o w n i n F i g u r e 5.5, where • the c u r v e m a r k e d as ' N o i s o l a t i o n ' i n F i g u r e 5.4 is used as the reference.  2  A s s h o w n i n F i g u r e 5.5, w h i l e the performance of n - w e l l G R s has i m p r o v e d w i t h i n I n this case the noise attenuation is due merely to the physical separation of the noisy and sensitive parts. 2  Chapter 5. Evaluation of Reduction Methods  70  - a - n - w e l l GR - © - p a n d n-well "  10"  +  0  500  1000 1500 Frequency (MHz)  2000  2500  Figure 5 . 4 : Attenuation as a function of frequency for different G R arrangements.  creasing frequency, for the other G R the results are the opposite. Another interesting point in the model for n-well G R s is that since at high frequencies the impedance due to CQR decreases, n-well G R can act as a sink path to A C ground. As a result, one can think of n-well G R s as p  +  G R s at very high frequencies. This argument is in agreement with  Figure 5 . 5 where at high frequencies the two plots of p  +  and n-well G R tend to converge.  In all cases, it is important to connect the G R to a dedicated supply; otherwise the G R itself can provide an extra path for noise injection into the substrate. The results shown in Figure 5 . 5 contrast with the previously reported results in [34] that the efficiency of p  +  G R s is independent of frequency. The conflict comes from the  fact that in the experiment in [34] a simple substrate contact was used as the noise sensor and no capacitive component was taken into account; thus the isolation did not change  Chapter 5. Evaluation of Reduction Methods  71  35  - ^ - p GR only — a — n-well GR only -•-Both +  500  1000 1500 Frequency (MHz)  2000  2500  Figure 5.5: Additional attenuation provided by G R s as a function of frequency,  with frequency.  Effect of GR Width Figure 5.6 presents the isolation provided by p  +  G R as a function of its width. A s can be  seen, the isolation increases monotonically as the width of the G R increases, suggesting that the wider the G R the lower the noise. These results could be predicted from the G R model because, as the width of the G R increases, the impedance of the noise return path to ground decreases, and so does the propagated noise.  Effect of GR Placement Another important property to observe is the effect of the distance of the G R from the noise generation point. Figure 5.7(a) depicts the simulation results of the testbench introduced  Chapter 5. Evaluation of Reduction Methods  10  15 20 GR width (urn)  25  72  30  F i g u r e 5.6: G R a t t e n u a t i o n as a function of w i d t h .  20 40 60 80 Distance from noise generator(u.m)  (a) Results for single inverter.  20 40 60 80 Distance from noise generator(n.m)  100  100  (b) Results for a more complicated digital circuit.  F i g u r e 5.7: Effect of G R placement.  Chapter 5. Evaluation of Reduction Methods  73  in Chapter 3, using a fixed-width G R at different distances from the noise generator. The physical separation between analog and digital circuits in this figure is lOOyum. A s can be seen, more attenuation is achieved when the G R is located closer to the sensitive device. The worst isolation is achieved when the G R is placed halfway between the analog and digital blocks. Figure 5.7(b) illustrates the results of the same experiment using a more complicated digital circuit. The same behaviour is observed, but the location of the local minimum has changed, which is due to the change in the amount of the total capacitance in the digital circuit.  Effect of G R shape Since the only operation of the p  +  G R is to provide a path to a stable supply, one may  wonder if it is necessary to implement a full ring G R , while open guards may have the desired performance.  To show the effect of G R shape, three different G R s (shown i n  ' Figure 5.8) were examined using a chain of inverters circuit as a benchmark. Table 5.1 lists the results. Sensitive N M O S  \^45pm—\  20 firn  W i t h o u t protection  («— 45/xm—*(  G R with one side removed  Protection w i t h a single barrier  45/im—-\  Full G R  Figure 5.8: Different G R shapes.  Chapter 5. Evaluation of Reduction Methods  P r o t e c t i o n Scheme  Attenuation(dB)  Without protection  27.0  Protection with barrier  39.8  G R with one side removed  45.2  Full-ring G R  46.6  74  Table 5.1: Noise attenuation using G R s with different shapes. As shown in Table 5.1, the amount of isolation provided by a full G R is more than a single barrier; however, even using a barrier has a significant effect on the amount of noise propagation; therefore, one may consider using a barrier instead of a full-ring G R to save area in certain applications.  Effect o f s u b s t r a t e t y p e Section 3.2 discussed that noise propagation properties through the substrate depend on the type of the substrate and its characteristics. Since the performance of G R s also depends on the impedance of the paths in the substrate and the G R , it is expected that the substrate type plays an important role in the efficiency of G R s . Although Figure 5.7(a) shows that the placement of the G R is important in its isolation properties, this does not hold for epitaxial substrates. It should be noted that G R s are more effective in cases in which most of the noise travels through the surface of the chip; however, in epitaxial substrates, due to the low-resistivity of the bulk, the main path for noise propagation is through the deep portion of the substrate.  In effect, increasing  Chapter 5. Evaluation of Reduction Methods  75  , the distance between the points does not increase the attenuation, as was observed before. The independence of the attenuation from the distance in epitaxial substrates is also inferred from the G R model in epitaxial substrates, as shown in Figure 5.9. A s can be seen, only vertical impedances are important; therefore, increasing the distance does not change the G R ' s noise attenuation.  3  n-weil G R  Digital  Analog  n-woll G R  Heavily-doped bulk. •  (a) p Digital  +  G R enclosing sensitive devices. P  +  GR  Analog  p+ G R  Heavily-doped bulk  (b) n-well G R enclosing sensitive devices.  Figure 5.9: Lumped model of G R s in epitaxial substrates.  Simulation results also verify the previous discussion on the dependence of attenuation on the distance in various substrates. The results are shown in Figure 5.10. A s can be seen, , while the attenuation in lightly-doped substrates decreases monotonically as the distance increases, in epitaxial ones increasing the distance does not affect the attenuation. I t should be noted that all the models used in this chapter apply only to moderate and large separations between analog and digital blocks. At very short distances the effect of lateral surface resistances should also be taken into account. 3  Chapter 5. Evaluation of Reduction Methods  14 sr  76  —1  T  - e - Epitaxial - a - Lightly-doped  1 2  § 1 0  o co c o ro c  -  CD <  -e 0  10  0  20 30 Distance (urn)  0  (  40  50  Figure 5.10: Effect of substrate type.  5.3  Noise Reception  Reduction  This class of reduction techniques is typically used by analog designers to increase the immunity of their circuits to substrate noise. The most popular technique is the use of differential structures. Since substrate noise is mostly considered as common-mode noise, ideally it can be suppressed by differential signalling; however, due to the mismatches and the delay of noise propagation between the two inputs of the differential stage, they are not able to fully remove substrate noise. To increase the noise rejection capability, the layout must have the same parasitics coupling to each of the two differential branches, which requires a symmetric layout that can be achieved either by mirror or common-centroid symmetry. On-chip decoupling capacitor is another technique that can be used to reduce both  Chapter 5. Evaluation of Reduction Methods  77  noise generation and reception [72]. This technique is used both in digital and analog circuits to decouple power supply and ground lines.  The additional capacitor placed  • between supply and ground, can act as an extra source of charge for transient currents in switching parts; therefore, a smaller transient current will be drawn from supplies; hence, less noise is induced on power lines. As discussed in Chapter 3, use of P M O S transistors for signal handling parts, such as differential pair input transistors, and current mirrors will decrease the amount of noise ' reception because these devices are further isolated from the substrate by the underlying n-well. Finally, using a different supply line for analog circuits will decouple them from the noise on the supply lines of digital blocks.  5.4  Summary  In this chapter, various noise reduction techniques were introduced and discussed. Switching activity spreading was studied in time and frequency domains. It was shown that even though this technique is useful in time-domain, for R F applications it might not be helpful, since the frequency content of the noise at specific frequencies may remain unchanged ' after applying this technique. In addition to SAS, passive G R s were also reviewed in detail, and the impact of several parameters on their effectiveness was investigated. Lumped models for G R s in different substrates were introduced and used to justify the simulation results. It was shown that, while the isolation property of p  +  G R s deteriorates as the frequency increases, n-well G R s  might show an opposite trend; i.e., depending on the layout and structure of the circuit  Chapter 5. Evaluation of Reduction Methods  78  the effectiveness of this type of G R may improve. Furthermore, it was shown that at high frequencies, n-well G R s can act as p  +  G R . Finally, some general strategies for designing  noise-tolerant analog circuits were given.  79  Chapter 6  Conclusion and Future Work  6.1  Conclusion  In this thesis, substrate noise, as one of the main obstacles in highly-integrated circuits, was studied from three different aspects. First, the behaviour of the noise was explored in the time and frequency domains. Internal and external noise sources were considered and it was shown that external noise sources quickly dominate the overall noise as the inductance in power supply lines increases. The dependence of noise on a variety of parameters such as switching time and frequency of operation were also analyzed.  The dependence of  the noise behaviour on the substrate type was extensively studied and the differences between noise propagation properties in two most commonly used substrates, lightlydoped and epitaxial, were analyzed. The difference between P M O S and N M O S devices was also investigated and it was shown that, P M O S devices exhibit superior substrate noise performance as compared to N M O S transistors owing to the additional isolation provided by their underlying n-well. Second, the effect of substrate noise on a typical L N A was investigated from a circuitlevel point of view rather than the signal-level approach exploited by previous works. A new M O S F E T model that includes substrate noise effects was introduced. It was shown  Chapter 6. Conclusion and Future Work  80  that, while with lowering the quality factor of the input network the noise figure of the L N A improves from the intrinsic device noise perspective, it deteriorates due to the effect of the substrate noise; therefore, there is a compromise between substrate noise and intrinsic device noise minimization inductively-degenerated L N A s . T h i r d , the properties of passive G R s , as the most popular noise reduction technique, were studied. It was shown that in contrast to previous results, the isolation efficiency of n-well G R s can improve by increasing frequency. In fact, an n-well G R at high frequencies can act as a p  +  G R . Furthermore, the dependence of the additional isolation provided  by G R s on several parameters such as the width, placement, and shape of the G R were investigated.  6.2  Future  Work  Experimental verification of the approach proposed in Chapter 4 is a further step that should be taken as future work. Another possible extension to this work can be the study of the performance degradation of more analog circuits using the proposed M O S F E T small-signal model. Furthermore, in addition to inductively-degenerated L N A , many other L N A configurations exist that require further research to identify the least sensitive L N A architecture to substrate noise. In the software and C A D tool area, there are many opportunities that await exploration. The only commercially available substrate noise analysis tool is Substrate Noise Analyst by Cadence™, performance of which is mostly limited to digital circuits, i.e., the spectral analysis of substrate noise, which is crucial to noise analysis, is not addressed in  Chapter 6. Conclusion and Future Work  81  t h i s t o o l ; therefore, there is a need for a t o o l w i t h R F c a p a b i l i t i e s . T h e current t o o l does not a l l o w for s i m u l t a n e o u s s i m u l a t i o n s of noise figure a n d s u b s t r a t e noise analysis; as a result, d e v e l o p m e n t of a t o o l w i t h t h e c a p a b i l i t y of c o s i m u l a t i o n of R F a n d s u b s t r a t e noise w i l l b e e x t r e m e l y v a l u a b l e t o a n a l o g designers. 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Y u e , " O n - c h i p R F i s o l a t i o n techniques," i n Proc. of Bipolar/BiCMOS  Circuits  and Technology  Meeting,  Sept. 2002, p p . 2 0 5 - 2 1 1 .  88  Appendix A  M O S F E T Small-Signal M o d e l T h i s a p p e n d i x reviews the s m a l l - s i g n a l m o d e l of the M O S t r a n s i s t o r used i n noise analysis. 1  F i g u r e A . l i l l u s t r a t e s the comprehensive s m a l l - s i g n a l m o d e l of the M O S device i n c l u d i n g p a r a s i t i c capacitances a n d various device noise sources.  p  G  agd  z-ngpar  D  -MSN-  *nff(T) Cb s  9g^.C gs  = Vgs  gV m  gs  r >  -g bV m  ind(\^)  0  s  Cdb--  T  I  F i g u r e A . l : D e t a i l e d s m a l l - s i g n a l m o d e l of the M O S device, i n c l u d i n g device i n t e r n a l noise sources, p a r a s i t i c capacitances, a n d b o d y effect.  I n this figure,  R  gpar  and  e  ngpar  represent the p a r a s i t i c resistance of the gate a n d t h e  noise associated w i t h i t , g accounts for the effect of the d i s t r i b u t e d n a t u r e of the c h a n n e l , g  id  represents c h a n n e l t h e r m a l a n d flicker noise, a n d i  n  ng  represents g a t e - i n d u c e d noise.  P a r a s i t i c capacitances between t e r m i n a l s o f t h e device are also s h o w n .  Note that the  s u b s t r a t e is assumed t o b e connected t o the s m a l l - s i g n a l g r o u n d . T o s i m p l i f y this m o d e l , we m a k e some assumptions: 1  T h e material presented in this appendix are from [69].  we ignore  R  gvar  and  e  , for  ngpar  Appendix A. MOSFET Small-Signal Model t h e y c a n be m i n i m i z e d by p r o p e r l a y o u t techniques; g  g  89  is also neglected because its value  is significant o n l y at v e r y h i g h frequencies, i.e., frequencies close t o the cut-off frequency of the device, a n d finally, we ignore b o d y effect a n d p a r a s i t i c capacitances (except  C ); gs  therefore, the s i m p l i f i e d version of the m o d e l is as i l l u s t r a t e d i n F i g u r e A . 2 .  Figure A.2: Simplified  MOSFET  s m a l l - s i g n a l m o d e l (parasitic capacitances,  gate dis-  t r i b u t e d resistance, a n d b o d y effect are ignored).  I n this figure, t w o m a j o r device noise sources are i n c l u d e d (i.e., i  nd  a n d i ),  the power  ng  s p e c t r u m of w h i c h are g i v e n by:  i\  d  = 4kT Af  + §  19d0  Af  (A.l)  f  n  j2  =  (A.2)  WT6g Af g  where g o is the drain-source c o n d u c t a n c e at zero VDS, 7 d  noise coefficients , respectively, Kf  a  n  d S are c h a n n e l noise a n d gate  is a n e m p i r i c a l coefficient a n d p a r a m e t e r g  g  9g =  is:  (A.3)  50 dO  N o w , we a p p l y s u p e r p o s i t i o n to t h i s m o d e l t o find the t o t a l o u t p u t c u r r e n t due to these noise sources a n d replace t h e m w i t h a single noise source, i g, nd  as s h o w n i n F i g u r e A . 3 .  Appendix A. MOSFET  Small-Signal Model  G o—  90  D  -o +  I  Cgs — — Vgs OmVgs ^  ^  ^ndg ^  ^  F i g u r e A . 3 : M O S F E T s m a l l - s i g n a l m o d e l w i t h a single noise source representing the effects of b o t h c h a n n e l t h e r m a l a n d g a t e - i n d u c e d noise.  T h i s single noise source c a n be w r i t t e n as:  (A.4)  tndg — ^n,ng ~b ^n,nd  where i  n m  and i , d n n  represent the p o r t i o n of the t o t a l noise due to g a t e - i n d u c e d  and  c h a n n e l t h e r m a l noises, respectively. F i r s t , we find the noise o u t p u t current due to g a t e - i n d u c e d noise (i ,ng)n  Since the  t o t a l o u t p u t noise depends o n the i m p e d a n c e s c o n n e c t e d t o the gate a n d the source, these c o m p o n e n t s are also i n c l u d e d i n F i g u r e A.4 a n d d e n o t e d b y i n t h i s figure, the o u t p u t current due to i  ng  Z  g  and  Zri . eg  A s c a n be seen  c a n be f o u n d u s i n g the f o l l o w i n g e q u a t i o n :  F i g u r e A.4: M O S F E T m o d e l for t h e c a l c u l a t i o n of t h e effect of g a t e - i n d u c e d noise  Appendix A. MOSFET Small-Signal Model  91  O  + Zdeg  Vi  F i g u r e A . 5 : E q u i v a l e n t c i r c u i t to find Z  gs-  t  (A.5)  i"n,ng — 9m,Zg i ng S  where Z  gs  is the i m p e d a n c e seen between the gate a n d the source. T o find t h e value of t h i s  i m p e d a n c e , we use F i g u r e A . 5 , based o n w h i c h , b y w r i t i n g K C L equations at the source and the gate of the t r a n s i s t o r we have:  _.  Vtest _ Vl ,, N i 9mVteat rv *-l\ ^gs) ^deg Vtest + Vl _ . Vtest ~ — test + Itest +  1  (A.6)  s  %  1/sC,  Therefore, Z  gs  (A.7)  c a n be f o u n d as:  z =  Vtest hest  1  I, Z  + Z  SCg  "1+0  mZdeg  deg  S  g  (A.8)  T o c a l c u l a t e t h e effect of i d, we use F i g u r e A . 6 , based o n w h i c h , the f o l l o w i n g equations n  Appendix A. MOSFET Small-Signal Model  92  F i g u r e A . 6 : M O S F E T m o d e l for t h e c a l c u l a t i o n of t h e effect of c h a n n e l t h e r m a l noise. can be w r i t t e n :  (A.9)  l>n,nd — ind ~P QvnYgs  Vns  =  V(sCg ) l/{sCg ) + Zg s  -Vl  (A.10)  S  Vl  = i ,nd( deg  ||  Z  n  +  (All)  Z )) g  therefore: 1n,nd  ( i - ( 7 % ) ^ ) " ^ ' Zdeg +  Z  =  V nd l  (A.12)  g  V  N o w , u s i n g s u p e r p o s i t i o n p r i n c i p l e we find  i  ndg  i n F i g u r e A . 3 as:  I'ndg — V^nd A~ 9m,Zgs^ng  (A.13)  A s discussed i n C h a p t e r 4, t h e mean-square valueof t h e noise (i.e. i t s power) is t h e m a i n  Appendix  A. MOSFET  Small-Signal  Model  93  p a r a m e t e r used i n t h e noise figure c a l c u l a t i o n s , w h i c h c a n be found as follows:  ndg = iWndg  = (V*i*nd + 9mZ* i* ){r]i +  i2  gs  ng  = M ind^nd + indingdmV*Zgs  + i i (g T]*  = \v\ i nd + 2Re{i i g rf  Z ]  2  nd ng  -  \\i 2  V  m  + 2Re{  2 nd  nd ng  gs  gZi )  nd  Z )*  m  + i  m  gs  2 n s  gs ng  +  i i \g Z, ng ng  m  |#mZ,  y* nd^ ngQmV ^gsj ' 1  (AAA)  nglym^i  d^ng  R e c a l l i n g t h a t c was defined as t h e c o r r e l a t i o n factor between c h a n n e l t h e r m a l noise a n d g a t e - i n d u c e d noise, we c a n rearrange this e q u a t i o n i n the following form:  i nd 2  = i nd\H 2  9  2  + 2Re{c  '2 "2 L M „ n*7 AgsJ \ -L.+-H£.n \7 gs\ \ \ j ^—9mV ^^9m\ 1 nd 1 nd %  2  2  (A.15)  Zj  w h i c h is t h e e q u a t i o n used i n C h a p t e r 4 t o derive t h e noise figure of the amplifier; therefore, the final M O S F E T Equation A.15.  s m a l l - s i g n a l m o d e l is as s h o w n i n F i g u r e A . 3 w i t h i  2 ndg  given b y  94  Index A c t i v e noise suppression, 17 A D C , see Analog-to-digital converter Analog-to-digital converter, 1, 14, 15 B a n d g a p reference, 14 B E M , see B o u n d a r y element method BiCMOS, 1 Bipolar, 1 B J T , 11 B l u e t o o t h , 3, 6 B o d y effect, 7, 11-13, 15, 49, 52, 54, 88, 89 Bondwire, 9, 21, 23, 29, 32 B o u n d a r y element method, 16 Cascode, 58 C h a n n e l thermal Noise, see Noise C o m p a r a t o r , 15 Complementary current balanced logic, 17 Correlation factor between channel thermal and gate-indi noises, 51, 93 Current balanced logic, 17 Current mirror, 77 Current steering logic, 17 Decoupling, 76 Device noise coefficient, 51, 54, 56 Device noise factor, 57-59 Diode, 11 D N C , see Device noise coefficient D N F , see Device noise factor F D M , see F i n i t e difference method F i n i t e difference method, 16 F l i p - c h i p package, 33 Flip-flop, 13 Folded source-coupled logic, 17 G a t e noise coefficient, 89 Gate-induce noise, see Noise  Geometric mean distance, 44 G P S , 3, 6, 12, 14, 55 Green's function, 16 G r o u n d bounce, 20 Guard-ring, 17, 66-75 frequency response, 69-71 modelling, 68, 75 placement, 71-73 shape, 73-74 w i d t h , 71 IEEE802.il, 3 Impact ionization, 20 Intermodulation, 7, 14 Latch-up, 39, 40 Leakage current, 9, 20 L N A , see L o w noise amplifier L o w noise amplifier, 14, 47 inductively-degenerated, 55 Low-noise amplifier, 56, 57, 59, 60, 62 Low-noise digital design, 17 Matching impedance, 55 noise, 62 power, 60 M i l l e r Effect, 58 M i s m a t c h , 76 MOS modelling, 21-23 small-signal model, 49-54, 88-93 threshold voltage, 21, 23, 49 Multi-standard, 1 Noise attenuation factor, 34, 35, 42, 43 channel thermal, 88-93 power spectrum, 89 channel thermal, 51 common-mode, 11, 76  Index external, 19, 31-33 flicker, 88 gate-induced, 51-93 power spectrum, 89 internal, 19, 31-33 mean-square value, 51, 92 simultaneous switching, 28, 30 switching, 7, 20, 21, 23, 26, 27 white, 6 Noise factor device, 57, 59 substrate, 57-62 Noise figure, 47, 55-62 Operational amplifier, 14 O u t p u t driver, 22, 27, 38 low-noise, 18 Phase locked loop, 11, 14, 15 Photon-induced current, 20 P L L , see Phase locked loop P M O S , 46, 47 Power matching, 60 Q u a l i t y factor, 56-62 Sampling, 14 S A S , see Switching activity spreading SeismIC, 16, 20, 68 Signal-to-noise ratio, 14, 15 S N C , see Substrate noise coefficient S N F , see Substrate noise factor S N R , see Signal-to-noise ratio S o C , see System-on-a-chip S O I , 10 • S p i r a l inductor, 11, 40 Staggering, 65 Substrate epitaxial, 16, 39-46, 74, 75 lightly-doped, 16, 39-46, 66, 68, 75 resistance, 44 modeling, 41 Substrate noise coefficient, 54, 56 Substrate noise factor, 57, 59 Subthreshold current, 29 Switching activity spreading, 18, 64-66  95 Symmetry common-centroid, 76 mirror, 76 System-on-a-chip, 1, 2, 13, 14, 55 Transconductance, 15, 47, 49, 58 V a r actor, 11, 15 V C O , see Voltage-controlled oscillator Velocity saturation, 21, 29 Voltage-controlled oscillator, 11, 14  

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                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            src="{[{embed.src}]}"
                            data-item="{[{embed.item}]}"
                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
                            data-width="{[{embed.width}]}"
                            async >
                            </script>
                            </div>
                        
                    
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