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Parasitic substrate effects in gallium arsenide monolithic MESFETs 1992

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PARASITIC SUBSTRATE EFFECTS IN GALLIUM ARSENIDE MONOLITHIC MESFETS DAVID DIMA SHULMAN B.Sc., Technion — Israel Institute of Technology, 1983 M.Sc., Technion — Israel Institute of Technology, 1986 A THESIS SUBM1ITbD IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY in THE FACULTY OF GRADUATE STUDIES (The Department of Electrical Engineering) We accept this thesis as confonning to the required standard THE UNIVERSITY OF BRITISH COLUMBIA June 1992 ©David Dima Shulman Signature(s) removed to protect privacy In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. (Signature) __________________________________ Department of E€L1ThC 5Iterr The University of British Columbia Vancouver, Canada Date . DE-6 (2/88) Signature(s) removed to protect privacy Signature(s) removed to protect privacy Abstract The present large scale GaAs integrated circuit industry is based on the fabrication of metal- semiconductor field-effect-transistors (MESFETs) on semi-insulating GaAs substrates which provide the device isolation. High-resistivity in semi-insulating GaAs is achieved by the delicate balance between shallow donors and acceptors, and deep levels. The semi-insulating substrates, however, do not provide perfect isolation and do allow crosstalk between neighboring MESFETs. One source of the crosstalk is sidegating, usually defined as the change in drain current of one MESFET as a result of applying a negative potential to a nearby contact of another MESFET. In addition, the interaction of each MESFET with the semi-insulating substrate is strong enough to affect the electrical properties of the device, the most important being the change of the output conductance with frequency. This work is concerned with the above two parasitic effects with the main focus on sidegating, which is the major obstacle for developing large scale GaAs integrated circuits. Electron injection into the vicinity of a MESFET from a nearby contact via a semi-insulating substrate is known to produce the sidegating effect. This process is known as single injection, because the injection is due to a single carrier type. In this work we present a novel study of sidegating in the frequency domain (AC sidegating) and a new mechanism of DC sidegating in which holes are injected into a semi-insulating substrate from the gate of a MESFET and electrons are injected into a semi-insulating substrate from a nearby contact. This process is known as double injection. We distinguish between high- and low-level double injection where the low-level injection is referred to a condition in which the excess carrier concentration is much smaller than the majority carrier concentration in semi-insulating GaAs, while the low-level injection is referred to a condition in which the concentration of injected excess carriers exceeds the majority carrier concentration in semi-insulating GaAs. High-level double injection results in a drastic variation of a MESFET drain current at voltages lower that those predicted by the single-carrier injection model. It also results in hysteresis in current 11 voltage characteristics as observed in experiments. It is shown that sidegating may occur under conditions of low-level double injection, because of the resultant excess trapped charge distribution which produces non-linear potential profiles across the semi-insulating substrate. The contribution of hole injection and recombination processes to the non-linear potential profile is discussed. We found that AC sidegating at least up to and including the kHz range is related to DC sidegating, in a way that upon increasing a negative sidegate voltage the AC drain current is decreasing. Upon applying small negative or positive sidegate voltages, thus preserving the conditions of low-level injection, this work predicts a strong sidegating effect in the kHz-MHz range due to the decrease by a few orders of magnitude of the resistance of semi-insulating substrates. This is because semi- insulating GaAs transfonns in this frequency range from what is called a “lifetime semiconductor”, in which quasi-neutrality of free carriers is preserved, to a “relaxation semiconductor”, in which separation of electrons and holes in space exists through zero local recombination. The present treatment predicts that this form of AC sidegating will be only weakly sensitive to hole injection, and will increase and start at lower frequencies on decreasing the distance between the MESFETs. The peculiar electrical properties of the semi-insulating GaAs in the frequency-domain are used to explain the frequency dependence of the output conductance of GaAs MESFETs on semi-insulating substrates. One result of the model developed in this thesis for the output admittance of GaAs MESFETs is that while the magnitude of the admittance can change by a factor of two or three, the variation of its phase is negligible. The results of this work indicate that device performance is strongly influenced by the properties of the semi-insulating substrate. One result is that device characteristics are not determined solely by the most dominant trap in the undoped SI substrate EL2, but also by recombination centers (which are not EL2) and shallower traps. 111 Table of Contents Abstract. List of Figures Glossary Acknowledgements Introduction 2 AC Sidegating 2.1 Introduction 2.2 AC Sidegating in GaAs n-i-n structures. 2.2.1 Experimental Procedure 2.2.2 Results 2.2.3 Discussion 2.3 AC Sidegating in GaAs MESFETs 2.3.1 Modeling 2.3.2 Detemiination of model parameters 2.3.3 Comparison with experimental results 2.3.4 Discussion 2.4 Summary 3 The 3.1 3.2 5 5 6 2.6 7 8 17 17 22 23 24 30 32 32 32 32 33 36 43 48 58 58 59 62 70 71 71 71 76 83 84 GaAs MESFETs 85 85 85 89 93 II vi Xi XII role of minority carriers in the sidegating effect Introduction Sidegating effect under conditions of low-level injection 3.2.1 Introduction 3.2.2 Sidegating model 3.2.3 Detailed analysis 3.2.4 Discussion 3.3 Evaluation of hole injection 3.4 High-level double carrier injection in the sidegating effect 3.4.1 Introduction and Model 3.4.2 Experiments 3.4.3 Analysis and Discussion 3.5 Summary 4 Low-frequency transport in semi-insulating GaAs 4.1 Introduction 4.2 Analysis and results 4.3 Discussion 4.4 Applications to AC sidegating 4.5 Summary 5 Modeling frequency dependence of the output conductance of 5.1 Introduction 5.2 Modeling 5.3 Comparison with experimental and numerical data 5.4 Summary iv 6 Conclusions 95 References 99 A Potential distribution in the uniform channel 106 B Potential distribution in the exponentially tapered channel 107 V List of Figures 1.1 Sources of parasitic effects in GaAs MESFETs on a SI substrate. Lines 1—4 visualize interaction mechanisms between two MESFETs on a SI substrate, which can be sources of sidegating: 1—2 interaction between the source/drain to the sidegate, 3 interaction between the sideate to the gate on a doped channel, 4 interaction between the sidegate to the portion of the gate on a SI substrate (the dashed line shows the edge of the active channel area): Line 5 shows drain-to-source leakage current, which contributes to the increase of an output conductance of a MESFET 3 2.2 Signal attenuation at low frequencies for the 20gm long structure (for sidegate voltage VSG = —6V) measured using the low-frequency measurement setup 7 2.3 Signal attenuation vs. negative sidegate voltage at lkHz(pluses), lOkHz(x-marks), and lOOkHz(circles) measured using the low-frequency measurement setup for 3m long structure 8 2.4 Signal attenuation vs. negative sidegate voltage at lkHz(pluses), lOkHz(x-marks), and lOOkHz(circles) measured using the low-frequency measurement setup for i4m long structure 9 2.5 Signal attenuation at radio frequencies for the 201im long structure (for sidegate voltage = —6V) measured using the high-frequency measurement setup. . . 10 2.6 Signal attenuation at radio frequencies for the 450[tm long structure (for sidegate voltage = —6V) measured using the high-frequency measurement setup. . . 11 2.7 Physical system corresponding to the differential equation 2.4 which is used for investigating frequency-dependent transients in SI GaAs. At t=0 the switch is closed and the DC biasing voltage V0 and the sinusoidal input V(t) are applied to a bar of SI GaAs, which is initially biased at V 13 2.8 Schematic AC current-voltage characteristics for space-charge-limited conduction in SI GaAs at two frequencies f2 > f1. The current will be confined in the triangle bounded by the lines formed by the DC traps-filled-limit voltage, the trap-free square law and the ohmic conduction 15 2.9 Schematic space charge distribution in a GaAs MESFET operating in the saturation region with a negative gate bias 18 2.10 Distributed network for a GaAs MESFET in the saturation region 20 2.11 Experimental (dashed line) and calculated (solid line) dependences of AC sidegating on the gate bias for a depletion-mode GaAs MESFET operating at VDD = O.5V, —3V, 100kHz. Parameters: cb = 15.4fF, Tb = 1.1GI1, r5 = 0.06Gl, c = 15ff. Zero bias gate capacitance is 90ff 24 2.12 Experimental (dashed line) and calculated (solid line) dependences of AC sidegatin on the gate bias for a enhancement-mode GaAs MESFET operating at VDD = 0.5V, VSG = —1V, 100kHz. Parameters: cb = 17ff, rb= 2.8GfZ, r5= 0.15G, c 15ff. Zero bias gate capacitance is 10ff 25 2.13 Experimental (dashed line) and calculated (solid line) dependences of AC sidegating on the gate bias for a depletion-mode GaAs MESFET at VDD = 3V, VSG —1V, 100kHz. Parameters: Cb = 17ff, Tb = 2.8Cfl, r5 = 0.l5G, C 15fF 26 vi 2.14 Experimental (dashed line) and calculated (solid line) dependences of AC sidegating on the drain-to-source voltage for a depletion-mode GaAs MESFET operating at VG = OV, VSG = —2V, 100kHz. Parameters: cb = 16.3ff, r = 3.2Gf, r3 = 0.17G, c = 15ff, rh3 2101, c33 84ff 27 2.15 Experimental (dashed line) and calculated (solid line) dependences of AC sidegatin on the sidegate bias for a depletion-mode GaAs MESFET operating at VG = OV, VDD = 0.5V, 10kHz. Parameters: Vchs = 175Q, C33 = 90ff, C3 = 15ff 28 2.16 Experimental (dashed line) and calculated (solid line) frequency dependence of sidegating for depletion-mode GaAs MESFET operating at VG = OV, VDD = 0.5V, VSG = —1V. Parameters: Tchs = 175f1, C33 = 90ff, Cb = 17ff, Tb 2.8011, Ts = 0.15011, C = 15ff. . . . 29 3.17 Typical drain and gate currents as a function of sidegate voltage (VD = 2 V, VG = 0 V). The measurements were performed in the dark on depletion-mode MESFETs fabricated by ion implantation into a SI substrate. The typical threshold voltage was —0.6 V. The gate length was l[tm and width 4im. The gate-source and gate-drain distances were 2im. The ohmic contact of the adjacent MESFET, which served as a sidegate in our measurements, was placed parallel to the source at a distance of 8im and was 23tm from the gate 34 3.18 Hole injection from Schottky gate. (a) For a small sidegate voltage. (b) For a large sidegate voltage 35 3.19 Schematic band diagram of the gate-sidegate structure in equilibrium 37 3.20 Concentration profile of trapped and free excess carriers in the 20gm long model structure. The solid line corresponds to trapped carriers, dashed line to electrons, and dashdots to holes. The carrier densities are normalized to the equilibrium electron concentration The sidegate voltage is —5V, the equilibrium electron concentration is 7 x 106 crn3, the equilibrium hole concentration is 2 x i05 Cm3, the electron mobility is 4 x i03crn2/Vsec, the hole mobility is 400 Cm2/Vsec, and the lifetime is 1 nsec. EL2 is assumed to be 0.75eV from the conduction band, its density 1016 cm3, and the ratio of its capture cross sections for holes and electrons i0. The recombination center is assumed to be 0.65eV from the conduction band, with density 10i5 Cm3, and the ratio of its capture cross sections 100 40 3.21 Concentration profile of trapped excess carriers as in Fig. 3.20, but only in the vicinity of hole injecting edge (x=0). The charge profile changes polarity at around0.4gm 41 3.22 Electric field profile in the investigated structure with the same parameters as in Fig. 3.20, but for different densities of recombination centers: dots correspond to 1016 cm3,dashed line to 1015 cm3, and solid line to i014 m3 42 3.23 Potential profile corresponding to the conditions described in Fig. 3.22 43 3.24 Electric field profile in the investigated structure with the same parameters as in Fig. 3.20, but for different values of the minority carrier injection (n): dots correspond to i,=l, dashed line to 0.5, and solid line to 0 44 3.25 Potential profile corresponding to the conditions described in Fig. 3.24 45 3.26 Schematic superimposition of the potential profile across the investigated structure in the presence of a sidegate voltage Vo (dashed line), and for zero applied voltage (solid line). W1 designates the width of the substrate-channel depletion layer 46 vii 3.27 Drain (solid line), gate (circles), and sidegate (asterisks) currents vs. sidegate voltage (VD = 2V, VG = OV). The gate current changes its polarity at about —3V. The gate and sidegate currents coincide at the voltages more negative than-8V 51 3.28 Channel punch-through in low pinch-off GaAs MESFETs (VD = 2V, VG: OV to — O.2V): (a) gate current increases rapidly when a MESFET is nearly pinched off as a result of applying a negative sidegate voltage. (b) the corresponding sidegate current 52 3.29 Hole injection and a corresponding energy-band diagram for a (a) quasi-neutral MESFET, (b) MESFET with a large negative sidegate voltage applied. The combination of the inversion layer, n-channel and semi-insulating substrate creates a P-N-P looks like structure 54 3.30 (a) Cross section of the investigated three-terminal structure consisting of two MESFETs. Using a Schottky (gate) and an ohmic contact (source/dram) of one MESFET together with an ohmic contact of the other MESFET, the structure acts as a surface-barrier transistor with a gate operating as an emitter. (b) An equivalent bipolar transistor structure with a long collector region 55 3.31 Measured currents vs. collector voltage characteristics. The solid line corresponds to the emitter (gate) current ‘E and the dashed line to the collector (sidegate) current 1c. The leakage current IL (designated by dots) is the current between base and collector when the emitter is floating 56 3.32 Calculated hole injection ratio, defined as (I — IL)/iE for the emitter-base bias of 0.1 V (solid line) and 0.2 V (dashed line). ‘E”C and ‘L are defined in caption of Fig. 3.31 57 3.33 Schematic layout of the mirror-image structure of two MESFETs that were used in the sidegating measurements. The channel width, gate length, gate-source and gate-drain spacings were 4 pm, 1 pm, 2 pm and 2 pm respectively. The dotted area is the active layer area of the MESFETs. When one of the MESFETs was biased, the other’s ohmic contact served as a sidegate. The sidegate was 8 pm from the source and 23 pm from the gate. . . . 60 3.34 Drain, gate and sidegate currents as a function of sidegate voltage (VD=2V,VG=OV) 61 3.35 Drain current versus sidegate voltage for a MESFET with a floating gate (VD: 1—5V) 62 3.36 Hysteresis in the drain current (VD = 2V, VG = OV), and in the gate-sidegate current (source and drain are floating). The solid line represents a decreasing (more negative) sidegate voltage, while the dotted line represents the opposite direction 63 3.37 Schematic energy-band diagram of a MESFET gate on a SI substrate 65 3.38 Hysteresis in the gate-sidegate structures under increasing illumination (VSG = OV, drain and source are floating). The solid line corresponds to the data obtained in the dark, dashed line corresponds to the data obtained with room lights, and the open circles correspond to the data obtained under microscope lamp illumination. Results obtained in the dark or with room lights show hysteresis, while those obtained under direct illumination show no hysteresis. . . 68 3.39 Schematic top view of the area (designated by gray pattern) that is affected by hole injection from the gate on a SI substrate 69 viii 4.40 Schematic equilibrium band diagram of the semi-insulating structure of a length L between zero-field points in the vicinity of N+ and Schottky contacts 72 4.41 Concentration profile of excess trapped and free carriers in the 50tm long model structure at 1Hz with no hole injection (i=O). The solid line corresponds to trapped carriers, dashed line to electrons, and dots to holes. The amplitude of AC applied voltage is 5OmV, the equilibrium electron concentration is 7 x 10b cm3, the equilibrium hole concentration is 2 x i05 cm3, the electron mobility is 4 x iücm2/Vsec, the hole mobility is 400cm2/Vsec, and the lifetime is 10 nsec. The deep donor is assumed to be 0.75eV from the conduction band, its density 2 x 1016 cm3, and with the capture cross section of 1 x lO3cm2for electrons and 1 x lO6cm2for holes . The deep acceptor is assumed to be 0.65eV from the conduction band, with density 5 x 1015 cm3, and with the capture cross section of 1 x lO3cm2for holes and 1 x 10’6cm2for electrons 75 4.42 Concentration profile of trapped and free excess carriers at 1MHz with no hole injection. The rest of the parameters are given in Fig. 4.41 76 4.43 Concentration profile of trapped and free excess carriers at 1Hz in the presence of hole injection (i=1). The rest of the parameters are given in Fig. 4.41 77 4.44 Concentration profile of trapped and free excess carriers at 1MHz in the presence of hole injection (=1). The rest of the parameters are given in Fig. 4.41 78 4.45 Frequency dependence of the conductance of the SI structure calculated using eq. (4.64). The dashed line corresponds to the conductance in the presence of hole injection (ij=l) and the solid line to the conductance when no hole injection occurs (i=O). The rest of the parameters are given in Fig. 4.41 79 4.46 Frequency dependence of the capacitance of the SI structure calculated using eq. (4.64). The dashed line corresponds to the capacitance in the presence of hole injection (7t1) and the solid line to the capacitance when no hole injection occurs (i=0). The rest of the parameters are given in Fig. 4.41 80 5.47 Schematic cross section of a MESFET and an AC potential profile across the drain-substrate-source region. LF corresponds to the profile at low frequencies, HF at high frequencies 86 5.48 Small-signal equivalent circuit of a GaAs MESFET at low frequencies 89 5.49 The impact of the device structure on the frequency dependence of the output admittance. The first row shows MESFETs with a p-type buried layer. A deep p layer reduces the frequency dependence, while a shallow p layer may increase it. The second row shows the effect of the gate location on the frequency-dependent output admittance: placing gate closer to the source enhances the frequency dependence, while placing it closer to the source may reduce the effect 91 5.50 Drain conductance vs. frequency. Results of the present model (solid line) are superimposed on numerical results (dashed line) [7], and experimental data (circles) [20]. Parameters used: T = 300 K, ND = 107cm3, NA = 6 x 105cm3,VDS = 2.5V, VDST = 1.45V, 1sg = 1dg = lzrn, 1 = 1.2,um, e x 1O7cm3,p lO5cm , for trap at 0.69 eV;N1 = 5 x 106cm3, = 2 x 104cm2 0p1 = 2 x 1O8cm2for trap at 0.5 eV;N2 = 5 x 105cm3,a = 5 x 103cm2,,°2 = 5 x 107cm2. . . . 92 ix 5.51 Drain conductance vs. frequency at 325 K and 375 K. Results of the present model (solid line) are superimposed on experimental data (circles and asterisks) after Canfield et. al [4]. Parameters used: NEL2 = 5 x 1016cm3,NA = 5 x 1O5cm, 1sg = 1dg = = litm, VDS = 3V, VDST = 1.6V 93 x Glossary MESFET — metal-semiconductor field-effect-transistor SI — semi-insulating VLSI — very-large-scale integration LSI — large-scale integration IC — integrated circuit TFL — trap-filled-limit SCL — space-charge-limited MMIC — monolithic microwave integrated circuit J — electric current density I-V — current-voltage DC — direct current AC — alternate current — minority carrier injection ratio T — carrier lifetime q — magnitude of the electronic charge — electron mobility — hole mobility — equilibrium electron concentration 6n — excess electron density — equilibrium hole concentration — excess hole density xi Acknowledgements I would like to thank my supervisor Professor Lawrence Young for his help and support during the course of this work. Kerry Lowe from BNR (Ottawa) is thanked for providing the test devices used in this research. This work is dedicated to my parents. xii Chapter 1 Introduction In present GaAs technology, MESFETs are the only devices which have approached the VLSI level of integration. This is due to the simplicity of their fabrication: all we need is two ohmic contacts (source and drain) and a Schottky contact (gate) on a conductive layer (channel). However, with all its simplicity a MESFET exhibits numerous parasitic effects. This work is concerned with parasitic effects in GaAs MESFET integrated circuits, which hinder high-level integration. The VLSI level of integration requires the fabrication of MESFETs on semi-insulating (SI) sub strates, which makes the GaAs technology especially attractive because they reduce the interconnect capacitances and make device isolation simple. The MBE-grown buffer layers are currently too costly for use in the VLSI technology [1]. But the SI GaAs does not act as a mere mechanical support with high resistivity, and does allow leakage currents through the SI substrate between neighboring devices, as well as the leakage current between source and drain of each device. These currents originate effects which affect device performance. Rather than review these effects here, the reader is referred to the recently published text book on GaAs integrated circuits by Long and Burner [2]. In addition, there are review articles on the parasitic effects in GaAs integrated circuits by Rocchi [3] and more recently by Koyama et at. [4] and Salmon [5]. Many effects in GaAs MESFETs were investigated using the techniques that had already been developed for Si devices. But it is important to stress that there is a significant difference in the treatment of substrate effects in GaAs and Si devices. Probably the most fundamental difference is associated with the relaxation time in Si and SI GaAs substrates. While the relaxation time of a typical Si substrate is in the range of picoseconds, the relaxation time of a SI GaAs substrate is typically in the range of milliseconds-microseconds. This means that the charge injected into the bulk SI GaAs will not disappear as fast as in Si substrates. Consequently, the parasitic substrate effects will occur beyond the conventional silicon transistor bandwidth, but inside the bandwidth of GaAs MESFETs. Additional parasitic effects are associated with a Schottky MESFET gate. It is interesting to note that Schottky junctions have never been used in the VLSI Si technology, and their most popular 1 usage found place in the earlier digital LSI technology (TTL). In comparison to p-n junctions many properties of Schottky junctions are much less understood. A Schottky gate is, however, an essential part of the GaAs MESFET technology, and, therefore, its contribution to the parasitic effects in GaAs MESFETs should be considered. The major parasitic effect in GaAs integrated Circuits is sidegating, the change in drain current as a result of applying a negative potential to a nearby contact (sidegate). The earlier attempts to explain this effect suggested electron injection into the device channel-substrate interface as the main source of sidegating [6]. This explanation was based on the one-dimensional Lampert’s model of high-level carrier injection into the insulator with traps, according to which the current increases sharply at a certain threshold voltage [7]. Considering high trap densities in SI GaAs and typical distances between a MESFET and a sidegate, this model has difficulty in explaining the low voltages at which sidegating is often observed. To overcome this difficulty conduction through surface states was suggested [8, 9]. While some of the reported experimental results regarding sidegating could be explained in terms of surface conduction, there are many reports of sidegating in large-geometry devices and in layout arrangements in which the sidegating should have been greatly reduced if the surface had played a major role, but instead a strong effect was observed. According to the the recent review paper by Salmon, circuit manufacturers have developed processes, which control the surface properties, so that, “the surface component of backgating is negligible compared with the bulk backgating” [5]. Sidegating is a complicated phenomenon, in which several mechanisms of transferring charge into the vicinity of the MESFET channel may occur. In certain structures, and, depending on substrate properties, one of the mechanisms can prevail, but on the other hand some mechanisms can occur simultaneously. Fig. 1.1 visualizes some of the sources of parasitic effects in GaAs MESFETs on a SI substrate, that are discussed in this work. Although the present work has focused on GaAs MESFETs, many of the results are applicable for other devices that incorporate SI material. MESFETs are used here as a probe of parasitic phenomena occurring in SI substrates. Being simpler than other GaAs-based transistors, they provide a tool for 2 SEMI-INSULATING SUBSTRATE Figure 1.1: Sources of parasitic effects in GaAs MESFETs on a SI substrate. Lines 1—4 visualize interaction mechanisms between two MESFETs on a SI substrate, which can be sources of sidegating: 1—2 interaction between the source/drain to the sidegate, 3 interaction between the sidegate to the gate on a doped channel, 4 interaction between the sidegate to the portion of the gate on a SI substrate (the dashed line shows the edge of the active channel area). Line 5 shows drain-to-source leakage current, which conthbutes to the increase of an output conductance of a MESFET. understanding of the interaction with the SI GaAs of more complicated devices such as HEMTs [10] and HBTs [11]. Although measurements by the author are reported throughout this work, the emphasis is not on the measurement techniques, but on the analysis and modeling of the experimental results. The reason for this is that many of the results in this work are similar to those reported by other research laboratories during the last decade. Since the general behavior of the device is known, the major task for researchers is the understanding and interpretation of this behavior. The emphasis was put on an analytical treatment, since it usually provides more insight into device physics than do numerical methods. The present state of the GaAs MESFET technology still requires understanding of the basic phenomena occurring in the integrated circuits, and, therefore, in my opinion, such analysis should precede, or at least be in parallel to, numerical analyses. For example, in order to simplify computation many numerical analyses of sidegating do not consider the continuity equation for holes, and thus eliminate from the discussion many effects predicted by the analytical analysis, which takes the participation of holes into account. An additional reason for analytical modeling is to make results useful for circuit designers by providing closed-form expressions through which a clear relationship is established between design goals and physical device parameters. 2P29 DEVICE 1 DEVICE 2 3 In Chapter 2 the experimental investigation and R-C network modeling of AC sidegating are reported. In Chapter 3 the sidegating under conditions of low-level injection into the SI substrate and the role of double injection in the sidegating effect are discussed. In Chapter 4 the extension of the low-level analysis to the frequency domain is presented. This frequency-domain analysis confirms and provides a new interpretation for the experimental results shown in Chapter 2. Chapter 5 shows how the frequency-domain analysis is applied to modeling of the frequency-dependent output conductance of GaAs MESFETs. Finally, conclusions are presented in Chapter 6. 4 Chapter 2 AC Sidegating 2.1 Introduction Crosstalk between GaAs MESFETs on SI GaAs substrates can severely affect device isolation and is a major obstacle to the miniaturization of GaAs integrated circuits. An important source of crosstalk is sidegating. Most reports of sidegating have been for DC conditions [12—14]. The results have been subject to different interpretations [12, 15, 8] . AC measurements and their analysis may provide a tool to decide which of various postulated mechanisms is currently occurring. Recently Chen et al. [161 addressed AC sidegating (at 40MHz and 2GHz). They concluded that it must be considered in designing GaAs monolithic microwave integrated circuits. Thus modeling of sidegating, which will predict at least the trends in device behavior, is needed in designing GaAs integrated circuits. The need to extend the investigation of sidegating to the frequency domain is fuliher shown by the following. As with silicon CMOS technology, in which the development of digital circuits was followed by the development of analog circuits, to provide an interface between the digital circuitry and the external world, the implementation of complex digital-analog systems on a GaAs single chip may soon be at issue. An understanding of the interaction between the analog and digital portions of the system will then be required. The investigation of this interaction is expected to be particularly troublesome at low frequencies, at which anomalies in GaAs monolithic MESFETs are observed. At high frequencies understanding crosstalk is important because of the tendency to combine microwave or RF circuits with their digital control circuits, e.g. RF switches with a driver circuit. Sidegating in GaAs digital integrated circuits has been investigated by applying a pulse train to the sidegate, but only the DC component of the pulse waveform has been considered [16, 17]. The effect, for example, of the pulse train repetition rate on sidegating has not been examined. 5 2.2 AC Sidegating in GaAs n-i-n structures MESFET interaction has usually been simulated by applying a negative potential to a sidegate contact on the semi-insulating GaAs substrate and examining its effect on a nearby device located on the same substrate, rather than having two MESFETs. According to the TFL model [12] sidegating is caused by electron injection into the channel-substrate interface of a MESFET and this process occurs due to the space-charge-limited conduction between the sidegate and the drain. Therefore, the sidegate-SI-drain interaction dominates sidegating, and, consequently, in the present section a simpler structure (n-SI-n) has been investigated, which avoids the complex electrical field distribution under the MESFET that otherwise complicates the analysis and the interpretation of the experimental results. 2.2.1 Experimental Procedure The measurements were performed on planar structures of ohmic contacts on semi-insulating GaAs substrates. Both the input contact, which represent the sidegate, and the output contact, which represent the drain, were n+ Si implanted directly into SI substrate. The two electrodes were separated by distances of 3 zm to 450 m of semi-insulating material. For measurement between 100Hz and 100kHz, the input of the sample was connected to a signal generator, while the output was connected to a Princeton Applied Research(PAR) 5204 lock-in analyzer via a PAR 113 low-noise amplifier, which was used in order to bring the signal to the level detectable by the lock-in analyzer. A different experimental arrangement was used for measuring the sidegating between 500kHz and 500MHz: the sidegate was connected through a high frequency probe to the HP 8656 signal generator, while the output was connected through another high frequency probe to a HP 8558 spectrum analyzer. Note that amplification of the signal in these two experimental set-ups is different. In the low- frequency set-up the voltage gain of the low-noise amplifier is set to 2 x 1O and its input is shunted by a 150 !l resistor. The output resistance of the amplifier is 600 Q and it is connected to the PAR lock-in analyzer with an input impedance equivalent to a 1 MIl resistor in parallel with a 30 pF capacitor. In the high-frequency set-up the output is connected to a 50 l input of the spectrum analyzer. 6 z C z Figure 2.2: Signal attenuation at low frequencies for the 2Opm long structure (for sidegate voltage VSG = —6V) measured using the low-frequency measurement setup. 2.2.2 Results The measured signal attenuation through the semi-insulating substrate is piotted as a function of frequency for the range 100Hz - 100kHz in Fig. 2.2. The linear fit exhibits 20dB per decade change of the output signal level with frequency. The signal attenuation at low frequencies for structures with distances of 3m and 14itm between the contacts is plotted as function of a sidegate voltage in Figs. 2.3 and 2.4. The 3 m long structure shows stronger sidegate voltage dependence than the 10 im long structure at the same range of applied voltages. This effect becomes more pronounced for lower frequencies. The measured RF signal attenuation is plotted ys. frequency for the range of 500kHz - 500MHz in Fig. 2.5. The output signal level increased 20dB per decade with frequency. Another set FREQUENCY (Hz) 7 z 0 z z CD Figure 2.3: Signal attenuation vs. negative sidegate voltage at lkHz(pluses), lOkHz(x-marks), and lOOkHz(circles) measured using the low-frequency measurement setup for 31tm long structure. of measurements (Fig. 2.6) at radio frequencies was performed on the structure with two contacts separated by 450 tm. 2.2.3 Discussion Several mechanisms contribute to the crosstalk phenomena. For a given arrangement of conduc tors if the spacing is small, the electric and magnetic fields of the conductors will overlap sufficiently, so that a wave propagating in one of them will induce a wave in the others. Thus part of the AC sidegating is caused by the coupling between two metal pads through an air and a dielectric material [18, 19]. Capacitive coupling is of course directly proportional to the frequency and will increase 20dB per decade with it (see Figs 2.2 and 2.5). -90 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 SIDEGATE BIAS (V) 8 -45 -50 - z o 60 -65 -70 z ct c1 -75 -80 -85 -5 SIDEGATE BIAS CV) Figure 2.4: Signal attenuation vs. negative sidegate voltage at lkHz(pluses), lOkHz(x-marks), and lOOkHz(circles) measured using the low-frequency measurement setup for l4pm long structure. Another mechanism contributing to. the sidegating involves the conduction current through the insulating substrate with traps. At low voltages an ohmic current will be observed. With increasing applied voltage the injected carriers fill up the traps in the substrate arid as the voltage reaches a certain threshold (trap-filled-limit voltage), at which all the traps are full, a steep rise in the current will occur [201. According to Lee et al. [12] a trap-filled space-charge-limited current is observed in semi-insulating GaAs samples. The more detailed models of this phenomenon proposed by Léhovec et al. [21] and Horio et at. [22] suggest that the space-charge-limited current through the semi insulating GaAs increases abruptly when the sidegate voltage exceeds a certain threshold and causes the substrate resistance to be reduced over a certain range of voltages. Avalanche breakdown [8] can also produce a threshold effect. -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 9 -40 -50 -60 -70 -80 ci, -90 -100- 10 l0 Figure 2.5: Signal attenuation at radio frequencies for the 20,um Long structure (for sidegate voltage VSG = —6V) measured using the high-frequency measurement setup. However, the models proposed to explain the sidegating in semi-insulating GaAs concentrate on the investigation of DC current-voltage characteristics only. Semi-insulating GaAs is known to contain both electron and hole traps [23]. The dependence of the space-charge-limited conduction upon frequency is expected to be influenced by the effects of trapping [24, 25]. The frequency dependence arises from the finite time constant associated with the charging and discharging of the traps in semi-insulating GaAs. We will consider only one electron trap, commonly referred to as EL2, which is the most important trap in determining the properties of semi-insulating GaAs [261. The trap filling can be analyzed using the Shockley-Read-Hall model for recombination through a single level, which, of course, neglects hot electron and field enhanced detrapping effects, which conceivably may be important in the present situation. The rate equation of the full traps on a single + + + + + 106 l0 108 FREQUENCY (Hz) 10 —55 I I I I I I I I liii -60 , -65 -70 - -80 -85 -90 -95 I I I I I I I 106 10 108 10 FREQUENCY (Hz) Figure 2.6: Signal attenuation at radio frequencies for the 450im long structure (for sidegate voltage VSG = —6V) measured using the high-frequency measurement setup. level is given by [27]: NT = NT[(cn + e)(1 — f) — (Cpp + en)fj; (2.1) where NT = density of traps, f = fraction of traps occupied by electrons, n, p = electron and hole densities, e, e = emission rates for electrons and holes, c, c7, = capture probabilities for electron and holes This equation can be simplified when the concentration of one carrier largely exceeds the concentration of the other. This is true for the single carrier high injection into the substrate. Furthermore, for EL2 the emission rates for electrons are much greater than that of the holes [28]. Next, we express the electron concentration around its steady state value: n(t) = no + n(t). Under 11 these conditions the trap filling equation reduces to: • dflT — = —(n + n1)cnT + flCNTdt (2.2) = —[no + In(t) + nh]CnflT + [n0 + In(t)]cNT; where T = NTf, n1 = electron density if the Fermi level were at the trap energy level. For small variations in electron concentration around its steady state value [no>> zn(t)j the time constant associated with the traps is given by [291: = 1/c(no + n1). (2.3) Since the steady state electron concentration can be much greater than its equilibrium value the time constant associated with the small variations in electron density also can be much larger than the emission time constant in equilibrium. Under these conditions the time constant does not vary with time. However, it is important to stress that the electron density and consequently the time constant vary across the region between two electrodes. If the electron concentration is 1 x 1013, using the equilibrium EL2 emission time constant given by [28], the time constant can be estimated to be about 20 1us. For large transient variations in electron concentration the exact solution of 2.2 is complicated. However, assuming n0 >> n1, so that we can write n0 no + n1, which is true for high applied voltages or for traps lying below the Fermi level, the solution of equation 2.2 for n(t) = cos (wt) is given by: nT(t) = NT + [flT(0) — NTjexp{—c[(no + ni)t + flmaxSfl(Wt)/Wj} (2.4) where T (0) = initial density of the full traps. The physical system corresponding to the eq. 2.4 is shown in Fig. 2.7. Equation 2.4 allows an examination of the trap filling time and shows that it is frequency- dependent. At high frequencies the transient response of the traps is not affected by the variations in free electron density because flmas/W is small, but at low frequencies the variations in the free 12 V(t) SI GaAs V0 Figure 2.7: Physical system corresponding to the differential equation 2.4 which is used for investigating frequency-dependent transients in SI GaAs. At t=O the switch is closed and the DC biasing voltage V0 and the sinusoidal input V(t) are applied to a bar of SI GaAs, which is initially biased at V1. electron ‘density are important in determining the transient response. For a very short period of time sin(wt) wt and the time constant is given by: = 1/c(no + fli + ‘flmar). (2.5) For large t the exponential decay will be determined by exp[—cn(no + ni)t]. Thus the trap filling time constant will vary with time under transient conditions. This time constant can be in the nanosecond range at the initial stage of transient response and will be equal to r8 as approaching the steady state. The charge on the deep level adjusts with a time constant T which varies from r0 to i-s. In the frequency domain this means that for frequencies f >> 1/(2iri-) the deep level cannot follow the variations in the electron concentration, which respond very fast to the changes in the applied voltage. However, the time constant r is both time and spatially distributed and therefore there will be a transitional frequency region in which the traps will partly respond. The charge injected into the semi-insulating substrate is equal to the free and trapped charge. At low frequencies [f << 1/(2irr)j the quasi-thermal equilibrium between the free and trapped electrons is maintained. Therefore, the applied voltage modulates both the free and trapped charge. However, only free electrons contribute to the conduction. Thus the low-frequency current-voltage characteristics will be t=O + + Vi 13 similar to the static ones, including a steep rise in the current at the trap-filled-limit voltage. At high frequencies [f>> l/(27rT)] the traps cannot follow the changes in the applied voltage. Therefore, only the free charge is modulated and the substrate behaves as a trap-free material. Thus the high- frequency current-voltage characteristics will exhibit a trap-free square law without a steep rise in the current at any voltage. Therefore the set of dynamic current-voltage characteristics will be confined in the triangle formed by the trap-filled-limit, trap-free square, and Ohm’s laws as shown in Fig. 2.8. This can be interpreted in terms of the frequency-dependent trap-filled-limit voltage, which will be confined by the DC trap-filled-limit voltage in its upper low-frequency limit, and by the voltage in which the transition from the Ohm’s law to the trap-free square law occurs in its lower high-frequency limit. Thus the substrate small-signal resistance will exhibit a frequency dependence at moderate frequencies, but will act as a simple resistance at low and high frequencies (neglecting the electron transit-time effects). This frequency dependence is expected to occur in the megahertz range, which is above the frequency limit (100kHz) of our low-frequency experimental arrangement that was used to investigate the AC sidegating as a function of sidegate voltage. The above analysis shows that the semi-insulating GaAs can be represented as a bias and frequency dependent conductance and capacitance in parallel. The impact of the resistive component will be more pronounced for low frequencies and for lower resistance. The resistance can be reduced for example by: 1. decrease in the sidegate - output pad separation 2. increase of the magnitude of the applied negative bias voltage Thus, one might observe this effect at low frequencies for the structures with a short separation. The experimental results between 1kHz - 100kHz for these structures are shown in Figs. 2.3 and 2.4. At these frequencies the conduction in the substrate is not expected to be frequency dependent. The measured DC voltage at which the decrease of a small-signal resistance occurs is l.6V and O.3V for the l4m and 3m long structures respectively. At 1kHz and 10kHz the coupling variation with the sidegate potential is clearly shown. This dependence is stronger for the shorter structure. At 100kHz the sidegating is dominated by the capacitive coupling and therefore exhibits a weaker bias dependence. 14 c-) VOLTAGE Figure 2.8: Schematic AC current-voltage characteristics for space-charge-limited conduction in SI GaAs at two frequencies f2 > f1. The current will be confined in the triangle bounded by the lines formed by the DC traps-filled-limit voltage, the trap-free square law and the ohmic conduction. The capacitance between two long metal electrodes located on the dielectric substrate is deter mined by the ratio between the metal pad width and the separation distance [19]. A larger separation between the sidegate and the output contact weakens the coupling by decreasing the capacitance and increasing the resistance between the two electrodes. It also increases the voltage required to initiate the trap-filled space-charge-limited conduction in the semi-insulating GaAs substrate. For the applied voltages well below the trap-filled-limit voltage, ohmic current through the semi-insulating substrate is expected. One may anticipate typical parallel RC network bias-independent behaviour in the frequency domain under these conditions. However, the experimental results which are shown in Fig. 2.6 indicate different frequency dependence: output signal level increases with frequency until it saturates at approximately 40MHz and increases again at higher frequencies (above 150MHz). One possible explanation of the experimental data is by the frequency dependence of the conductivity in semi-insulating material which stems from the potential fluctuations resulting from the non-uniform distribution of donors and acceptors and the lack of screening by free carriers. Potential fluctuations TRAP - FREE SQUARE LAW increasing frequency 15 in p-n Si junctions have been discussed by Shockley [30], who pointed out that this phenomenon is important in highly-compensated material. Potential fluctuations existing in compensated and lightly doped semiconductors were discussed in more detail by Shklovskii and Efros [31]. Recently this theory was applied to the semi-insulating GaAs by Pistoulet et at. [32]. According to their model the AC conductivity starts from rDC, grows as w3 (s close to 1) over a wide range of frequencies and then saturates as w continues to increase. Jonscher et a!. [33] also indicate the frequency-dependent conductivity of semi-insulating GaAs. The experimental data presented in Fig. 2.6 for large sidegate - output separation behaves below 150MHz qualitatively similar to the data shown by Pistoulet et at.. The high frequency response (above about 150MHz) is determined by the increasing capacitive coupling. In conclusion the AC conductivity in the semi-insulating substrate was investigated over a wide range of frequencies. Analysis of the mechanisms conthbuting to the AC sidegating shows that for short distances between the ohmic contacts on the same semi-insulating GaAs substrate, the capacitive-resistive coupling will be predominant. The resistive coupling, which probably stems from the trap-filled space-charge-limited conduction through the semi-insulating substrate, is bias dependent and will be important for large sidegate voltages and for low frequencies. The resistive coupling is also expected to be frequency-dependent at moderate frequencies, which are estimated to be in the megahertz range. At low applied voltages, where the capacitive coupling prevails, the experimental arrangement can be used for measuring the capacitance between the input and output electrodes following the procedure described in Ref. [34] applied to the two-terminal structure. For larger distances the coupling is reduced, and the AC sidegating will be characterized in terms of the inherent AC conductivity properties of semi-insulating GaAs as described in Ref. [32]. The frequency dependence in this case stems probably from the potential fluctuations exhibited in compensated and semi-insulating materials as a result of the non-uniform distribution of donors and acceptors and the absence of screening by free carriers. The relationship between DC and AC sidegating mechanisms has yet to be established . This relationship is not obvious: the trap-filled space-charge-limited current is not the only conduction mechanism that should be considered. Additional mechanisms are possible and some of them can be 16 obscured by others. For example, because of the possible surface conduction between the devices, the space-charge-limited current through the substrate can be masked. In this case one can expect a smaller resistance at DC than at some higher frequencies where the surface states will not respond. This work shows that the frequency-domain measurements and analysis are important tools in the crosstalk investigation, which allow the separation of the various effects contributing to the sidegating. 2.3 AC Sidegating in GaAs MESFETs MESFET interaction has been simulated by applying a negative potential to a sidegate contact on the SI GaAs substrate and examining its effect on a nearby MESFET located on the same substrate, e. g. [6]. This interaction requires an understanding of both the conduction mechanism through the SI GaAs substrate and the electric field distribution under the MESFET gate which depends on the bias voltages. Improvements in GaAs technology, such as higher “quality” SI substrates, better control of fabrication steps, introduction of new processing techniques and new device structures will eventually reduce sidegating. One aim of the present analysis is to seek conditions for minimization of sidegating through an understanding of the relation of thesidegating to the electric field distribution in the MESFET channel as determined by the bias voltages. The analytic expression for AC sidegating, derived in section 2.3.1 by using a distributed network, relates it in a simple manner to gate and sidegate voltages. The model parameters are evaluated in Section 2.3.2. The experimental data are presented in Section 2.3.3. The results of this work are discussed in Section 2.3.4. 2.3.1 Modeling An equivalent circuit, which is distributed so as to be applicable to high frequencies, was used. To include substrate effects, iti particular conduction through the SI substrate, a 4-terminal network representation of the MESFET is required, where the fourth terminal represents the nearest sidegate contact. The elements of the equivalent circuit are closely related to MESFET physical parameters corresponding to the shape of the space charge distribution in the device as shown in Fig. 2.9. The active layer is bounded by a Schottky barrier contact and a SI substrate. The space charge regions, 17 0 Ls L I Ix GATE I I n+ n + SOURCE n - channel DRAIN channel - atedep1etio region SEMI-INSULATING GaAs Figure 2.9: Schematic space charge distribution in a GaAs MESFET operating in the saturation region with a negative gate bias. which are responsible for the channel current modulation, are modified as a result of applying a voltage to the gate and to the sidegate contact and are affected by the surface states on the GaAs surface. Several assumptions have been made. 1. A channel is assumed to be uniformly doped in order to relate in a simple manner the elements of the equivalent circuit to the bias voltages. Ion implantation into SI GaAs substrate is the most widely used technique for fabrication of GaAs integrated circuits and our measurements were performed on low pinch-off ion-implanted GaAs MESFETs. However, in such devices a Gaussian profile can be approximated by an effective uniform doping profile [35]. 2. The parasitic capacitances and resistances associated with gate-drain and gate-source regions have been omitted in the distributed network. This is because the surface depletion layer that exists in these regions causes a series resistance and a gate capacitance to be added to the intrinsic MESFET [36] only at low frequencies (below 10kHz) where the surface states can respond [37]. At higher frequencies the gate-drain and the gate-source regions can be represented by pure resistances and the drain resistance is simply added to the external load resistance. The absence of the source resistance in the network can be justified because it is virtually grounded to the 18 AC grounded gate through the gate capacitance at high gate bias voltages. With decrease in the gate bias the gate capacitance decreases and thus cannot serve as an AC ground, but the channel resistance becomes larger and the source resistance can be neglected with respect to it. It is important to stress that the source resistance must be considered for the MESFET with double-gate excitation (gate and sidegate) since the gate is not AC grounded in this case. 3. The distance between the sidegate and the source is assumed to be much larger than the drain- to-source distance. This allows the region between the sidegate and the MESFET channel to be represented as a uniform R-C network. 4. The shunt leakage resistance of the gate depletion layer is neglected. This resistance may introduce a large time constant which may affect the analysis at low frequencies. In the linear mode of MESFET operation for small drain-to-source voltages the intrinsic MESFET can be represented by an R-C transmission line [38, 39] with the channel resistance rh and the gate capacitance c3 per unit length as parameters. Shulman and Young [40] have suggested that the region of semi-insulating material between two ohmic contacts can be modeled as a R-C network. Thus a R-C network, where the resistance r5 represents the conduction through the GaAs SI substrate, the series capacitance cb represents the space charge region formed at the substrate-channel interface, the resistance Tb represents the conduction through the substrate-channel interface, the parallel capacitance c5 describes the coupling between the sidegate electrode and the MESFET channel, was added to the circuit. In saturation the longitudinal MESFET cross-section can be roughly divided into two regions according to the electric field distribution in the channel. We assume that the electron velocity saturates when the electric field reaches E5 at distance i. from the source, which corresponds to the boundary between two regions in the device. The resultant network is shown in Fig. 2.10. The network parameters in the first region (0 < x < 1) are evaluated as follows. The gate depletion layer thickness at distance x from the source is given by: d(x) = — VG — V(x)j/qND, (2.6) where is the permittivity of GaAs, IV is effective uniform donor density, VB is the built-in voltage, VG is the gate potential relative to source and V(x) is the channel potential at distance x from the 19 Drain - Figure 2.10: Disthbuted network for a GaAs MESFET in the saturation region. source, which is E5x. The channel resistance and gate capacitance can be approximated as: 1 Th(X) = qNDw{a — d(x)] k I E3k2 1 (2.7) qNDwa(k — 1) [1 + 214(k — w 1 c(x) [1 2(VB VG)Xj (2.8) where is the low-field electron mobility, w is the device width, a is the channel thickness, = qNDa2/2E is the pinch-off voltage and k = — VG). Eqn. (2.7) and (2.8) can be considered as first-order approximations of exponential functions, so that we can write [38] rh(x) rh0e (2.9) and c(x) (2.10) where Tcho = qNDwa(k — 1)’ (2.11) k2E a = 2(k 1)’ (2.12) = Ewk/a (2.13) - Gate 1 iO Sidegate 1Ls 20 and = 2(VB- VG) (2.14) The differential equation for the first region for the sidegate excitation is given by: 02’v Ov — a— — rh(x){jw[c3( )+ c5] + ys}V = Tch(X)(jWCs +y5)V9, (2.15) where the AC potentials of the channel and sidegate were designated correspondingly by v and v, and Ys = [r5 + r&/(1 + jwcbrb)] . An analytic solution of (2.15), given in Appendix B, can be obtained by assuming that wc,(x) >> wc, Ys and a = 3. The first assumption is reasonable for a MESFET operating at intermediate and high frequencies and for relatively low substrate conduction between the sidegate terminal and the MESFET. The second requirement imposesl’, = 4(VB — VG), which corresponds to the condition that the gate depletion layer at the source end is equal to half of the device thickness. This condition may appear to severely restrict our analysis since it becomes valid only for one particular value of the gate voltage. However, this gate biasing voltage corresponds to the normal mode of MESFET operation. Thus, the following analysis can serve as indication of the sidegating dependence on the gate bias around its typical value. Furthermore, no restrictions were made on the drain-to-source voltage. Therefore, the sidegating behavior due to the variations in drain-to-source voltage can be investigated. In the second region (i < x < 1) the channel resistance and the gate capacitance are assumed to be constant and are given by Tchs = Tchoe1’and c =c0e(°”). The differential equation for the second region is given by: 02 v — [jwQ33 + c5) + ys]rchsv (jWCs + Ys)Th5v g . (2.16) The solution of the above equation is given in Appendix A. Combining (2.15) and (2.16) with the boundary conditions zero potential at z = 0 and x I and current and potential continuity at x = yields the following expression for sidegate transconductance [i(l)/vsgj: — WC5 + y 1A+ pe /2)1[1 — coth(p15)]— e(’’)[a/2 —pcoth(p13)] 2mb — Au jwc0rhS/u2 (2.17) _e[_u(l_1)][u — a/2 —pcoth(p15)j—pcoth(pi3)— 21 where p = + jwrchocjo, u = i.,/Tchs[JW(Cjs + c8) + y5] and A = [c/2 +pcoth(p13)]sinh[u( — la)] + ucosh[u(l — For practical device parameters eqn. (2.17) reduces to: mb (jwc8 + ys)/U. (2.18) 2.3.2 Determination of model parameters The method used to evaluate the MESFET equivalent circuit parameters was simple and fast at some expense of accuracy. The channel resistance was obtained from the current-voltage character istics of the MESFET operating in the linear region using an HP 4145A semiconductor parameter analyzer (SPA). The substrate resistance was evaluated from the sidegate current-voltage measure ments using the SPA. The substrate resistance measured between 0 and -3 volts was 2GQ. The resistance was drastically reduced below -3V. Interpretation of the sidegate current-voltage char acteristics is difficult and can lead to significant errors in the resistance evaluation [41]. Our DC measurements [42, 43] and the hysteresis observed by other researchers [15] suggest the possibility of double injection into the semi-insulating substrate. Even a small amount of hole injection from the channel into the substrate will result in most of the resistance being near the hole-injecting contact [41]. Consequently we assigned rb to be 95% of the measured resistance. The coupling capacitance between the sidegate and the channel was estimated to be 15fF using the graphs of the characteristic impedance of coplanar strips given in [19]. Measurements of the small- geometry MESFET gate capacitance followed a procedure similar to that in [34]. The source and drain terminals were fed from a common AC source. The AC current through the gate was fed into a Keithley 417 high speed picoammeter, whose output was connected to a Princeton Applied Research 5204 lock-in amplifier. The capacitance was evaluated from the measurements of the capacitive part of the AC current through a Schottky barrier. The measured gate capacitance of the depletion-mode 22 MESFET for VG = —O.1V at 1kHz was 80fF. The measurements at lower frequencies showed higher values of the gate capacitance. This is consistent with effects due to the presence of the deep levels in the device [44] and to the presence of the surface states in the gate-source and gate-drain spacings which increase the effective gate capacitance [36]. To avoid these problems the measurements at higher frequencies are preferred, which in our case were limited to 1kHz by the frequency response of the system. The capacitance of ion-implanted devices for the gate voltages lower and higher than VG = —O.1V were found by [45] c30(1 — VG/O.75V)’33, (2.19) where c30 is zero-bias gate capacitance. Measurement of the capacitance associated with a channel- substrate interface is difficult due to the existence of a very high series resistance presented by the substrate [46] and therefore it was calculated using the equation for the width of the channel-substrate depletion region as a function of voltage given in [47]. 2.3.3 Comparison with experimental results Experiments were performed on recessed-gate depletion and enhancement mode ion-implanted GaAs MESFETs made at a commercial foundry. The gate length of the transistors was 1 pm and their width was 52 pm. The length of the regions between the gate and the source and between the gate and the drain was 2 pm. The sidegate was located parallel to the source at a distance 14 pm. An HP 4145A SPA was used to bias a GaAs MESFET: the drain terminal was connected to the parameter analyzer through the load resistor(l50 ohm), while the gate was biased directly and the source was grounded. The sidegate was negatively biased with respect to the source and was connected to the signal generator, while the drain was connected to the lock-in amplifier. Figures 2.11-2.16 compare the sidegating experimental data as a function of frequency and various bias conditions with results calculated by (2.18). AC sidegating as a function of the gate bias for the depletion mode MESFET operating at small drain-to-source voltage is shown in Fig. 2.11. Fig. 2.12 shows the AC sidegating dependence on the gate bias for the enhancement mode transistor operating at small drain-to-source voltage. The dependence of AC sidegating on the gate bias for 23 -50 I I I I -55 -60W ‘1 75 I I I I I -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 GATE BIAS (V) Figure 2.11: Experimental (dashed line) and calculated (solid line) dependences of AC sidegating on the gate bias for a depletion-mode GaAs MESFET operating at VDD = 0.5V, VSG = —3V, 100kHz. Parameters: cb = 15.4fF, r = 1.1G2, r3 = O.O6GQ, c8 = 15fF. Zero bias gate capacitance is 90fF. the depletion mode transistor operating at large drain-to-source voltage is shown Fig. 2.13. The dependence of sidegating on the drain-to-source voltage is presented in Fig. 2.14. The sidegating exhibits less than 1dB variation over the range of 2-4 volts. AC sidegating as a function of the sidegate bias is shown in Fig. 2.15. The sidegating increases below -3V which corresponds to the threshold voltage in the DC sidegate current-voltage characteristics (see subsection 2.3.2). Finally the sidegating frequency dependence is shown in Fig. 2.16. 23.4 Discussion The assumptions in the above analysis restrict its validity at low frequencies. Surface states asso ciated with gate-source and gate-drain spacings may cause these regions to respond to the variations 24 z0.6 GATE BIAS (V) Figure 2.12: Experimental (dashed line) and calculated (solid line) dependences of AC sidegating on the gate bias for a enhancement-mode GaAs MESFET operating at VDD = O.5V, VSG = —1 V, 100kHz. Parameters: C6 = 17fF, 1b= 2.8G2, r3= 0.15Gl, c = 15ff. Zero bias gate capacitance is 10fF. in the sidegate potential. A recent analysis of low-frequency dispersion of gate transconductance in GaAs MESFETs, which relates it to the surface states, indicates that it will be important below 1kHz [48]. The frequency response of the sidegating shown in Fig. 2.16 can be roughly divided into two regions. The frequency response below 5kHz is probably controlled by the surface states. The frequency response above 10kHz is due to the capacitive and resistive coupling between the side- gate and the MESFET channel. The present experimental data confirm the theory in that at higher frequencies, in which MESFETs normally operate, the sidegating grows as wi!2. The dependence of the sidegating on the gate bias given by (2.18) originates from the following relation: mb 1/TchsCjs — d) (2.20) -95 0.1 0.2 0.3 0.4 0.5 25 z 0 z rz Figure 2.13: Experimental (dashed line) and calculated (solid line) dependences of AC sidegatmg on the gate bias for a depletion-mode GaAs MESFET at VDD = 3V, VSG —1V, 100kHz. Parameters: cb = 17fF, r, = 2.8G2, r3 = O.15GQ, c3 = 15ff. Thus, a parabolic dependence of AC sidegating on gate bias with a maximum at the bias corresponding to a half-depleted channel is expected. Generally, this behavior was indeed observed for MESFETs operating at small drain-source voltage as shown in Fig. 2.11 and 2.12. Sidegating for depletion mode GaAs MESFETs exhibits a maximum as a function of gate potential due to the fact that the conductive layer in these transistors can change drastically in thickness as it goes from a fully open channel to a very thin layer as a result of applying a gate bias and the condition of a half-depleted channel can be reached. The channel in the enhancement mode transistors is already depleted for zero gate bias. This means that the fully open channel can be achieved only at high gate voltages. As a consequence, the gate bias for which maximum sidegating is obtained shifts to higher voltages (see Fig. 2.12). For large drain-to-source voltage the sidegating increases and eventually saturates with gate bias (see Fig. -74 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 GATE BIAS (V) 26 -40 I -45 . -e - 0 -55. -60 -65 -70 1 1.5 2 2.5 3 3.5 4 DRAIN-TO-SOURCE VOLTAGE (V) Figure 2.14: Experimental (dashed line) and calculated (solid line) dependences of AC sidegating on the drain-to-source voltage for a depletion-mode GaAs MESFET operating at VG = OV, VSG = —2V, 100kHz. Parameters: cb = 16.3ff, rb = 3.2GQ, r3 = O.17G0, c = 15fF, rChS 210Q, c5 84ff. 2.13). The minimal thickness of the gate depletion layer in the high-field region is determined by the drain voltage. This results in a conductive layer that normally is well below half the device thickness for any gate bias. Therefore the sidegating does not exhibit a maximum as a function of gate voltage but rather increases monotonically with it. Our calculated results show good qualitative agreement with data for devices biased far away from pinch-off. This is probably due to the slowly-varying R-C product of the channel under these biasing conditions. At high gate voltages the leakage resistance must be taken into account. At lower gate voltages near pinch-off our calculations indicate lower sidegating, because eqn. (2.19) overestimates the gate capacitance in this region. Our experimental observations indicate that, when the device is biased near pinch-off, AC sidegating diminishes drastically in magnitude and is often accompanied by oscillations which makes 27 -.1 z C.) -65 Figure 2.15: Experimental (dashed line) and calculated (solid line) dependences of AC sidegating on the sidegate bias for a depletion-mode GaAs MESFET operating at = 0V, VDD = 0.5V, 10kHz. Parameters: rh, = 1752, c = 90fF, c = 15ff. it very difficult to perform accurate measurements. This abrupt decrease in sidegating is due to a very large Tch8Cj5 product. Lehovec and Zuleeg [491 evaluated the R-C product of the channel near the pinch-off region. They suggested that its large value is due to very low mobilities of electrons at the channel-substrate interface caused by extensive trapping. Therefore the channel resistance will be determined mostly by the properties of the semi-insulating substrate. The observed low- frequency oscillations are supporting evidence for this interpretation since they have been observed in semi-insulating GaAs [501. The sidegating depends on drain-to-source voltages only by way of channel-length modulation. Therefore, the sidegating in the saturation region, will not be too sensitive to the variations in drain- to-source voltage as indeed was observed in the experimental results shown in Fig. 2.14. -75 -6 -5.5 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -l SIDEGATE BIAS (V) 28 -60 -62 -64 Z -66 z - z -70 -72 -74 -76 -78 102 FREQUENCY (Hz) Figure 2.16: Experimental (dashed line) and calculated (solid line) frequency dependence of sidegating for depletion-mode GaAs MESFET operating at VG = 0V, VDD = 0.5V, VSG = —1V. Parameters: rhS = 175, c = 90fF, cb = 17fF, rb = 2.8G, i’3 = 0.15G2, c8 = 15fF. Fig. 2.15 shows a strong dependence of AC sidegating on sidegate voltages between -3 and -6 volts. These experimental observations are in qualitative agreement with the modeling results which predict that as the negative sidegate bias increases in magnitude the substrate resistance diminishes, thus increasing the sidegating intensity. The abrupt change in the sidegating as a result of applying a sidegate voltage below -3V has been taken as indicating the possibility of the injection current conduction in the semi-insulating substrate. However, r5 is not the only parameter that relates the sidegating to the sidegate bias: cb which represents the the space charge region at the channel substrate interface may play a significant role in determining AC sidegating. When the sidegate voltage increases in magnitude more and more electrons are injected into the substrate. Due to the injection effects the channel-substrate capacitance will be probably higher than that evaluated in 10 10 10 29 this work. This could explain the large discrepancy between the calculated results and the data at high sidegate voltages. The network parameters r3 and cb are expected to be frequency dependent. The substrate resistance is expected to be smaller at higher frequencies for short distances between MESFET and sidegate [401. The capacitance is expected to be larger at low frequencies because of the finite time constant associated with the charging and discharging of the traps in semi-insulating material [51]. In conclusion, distributed network analysis has been applied to the interpretation of the sidegating effect in GaAs MESFETs. Analytic expressions for the sidegating were derived and using a simple model were related to the bias voltages. Results presented in Fig. 2.15 show that AC conduction through the substrate plays an important role in determining the sidegating. The accuracy of the present model could be increased by retaining the same equivalent circuit but using more sophisticated models for the network parameters. The experimental data presented in this thesis agree qualitatively with the sidegating model expressed as a function of the frequency and bias voltages. The sidegating for the MESFET operating in the saturation region will not be sensitive to the variations in the drain- to-source voltage. The main conclusion which can be drawn from this work is that the sidegating effect can be reduced by applying the lowest possible gate bias to MESFET or in other words, by operating the device at low current. 2.4 Summary The mechanisms of crosstalk in n-SI-n GaAs structures were investigated over a frequency range of lOOHz-500MHz. The sidegating mechanism was found to be dependent on the frequency and on the distance between the sidegate and the output contacts. The crosstalk can be represented as a parallel RC network, where the capacitance is associated with the interaction of fringing fields around the input and output electrodes. For shorter distances the resistive component represents a conductive path through the semi insulating GaAs substrate normally associated with the trap-filled space-charge-limited current. In general the resistance will be bias-dependent. Furthermore, it is expected to be frequency-dependent 30 because of the finite time constant associated with the charging and discharging of the traps in semi-insulating GaAs. For longer distances the capacitive coupling is reduced. Also a higher biasing voltage is required in order to initiate the space-charge-limited current for the distant input and output contacts. Thus at low voltages the resistive component is associated with the ohmic leakage current through the substrate. This resistance exhibits a frequency dependent conductivity, which is a result of potential fluctuations in the compensated semiconductor. At low frequencies the capacitive coupling is reduced and the resistive coupling tends to prevail. At high enough frequencies capacitive coupling dominates disregarding the distance between the input and output electrodes. The bias and frequency dependence of AC sidegating in GaAs MESFETs was modeled using a distributed R-C network. The resultant analytic expression for the sidegate transconductance was compared with experimental results over the range of 100Hz - 100kHz. They agreed in that the sidegating at small drain-to-source voltage exhibits a maximum as a function of gate bias, while at large drain-to-source voltage the sidegating increases and eventually saturates with gate voltage, and is not sensitive to drain-to-source voltage. The present experimental measurements show that AC sidegating (like DC) is greatly enhanced after a negatively biased sidegate reaches a threshold. Both experimental data and the model show that AC sidegating increases approximately as wh/2 at high frequencies. 31 Chapter 3 The role of minority carriers in the sidegating effect 3.1 Introduction A field-effect transistor has been always a synonym to a unipolar transistor in the literature [52, 53]. This is not surprising, considering the nature of contacts, that constitute a MESFET: source and drain are ohmic contacts and therefore are unable to inject holes, and Schottky contacts practically do not inject holes according to the early studies by Scharfetter [54] and Yu and Snow [551. We, however, show in this chapter that the gate of a MESFET can inject holes and this results in parasitic effects that severely degrade the MESFET performance. In Section 3.2 we investigate sidegating under conditions of low-level injection, for which the excess free holes and electrons are much less than equilibrium hole and electron concentrations respectively. Without further assumptions we solve analytically continuity equations for holes and electrons plus Poisson’s equation. The results show that the presence of recombination centers in the SI substrate and even weak hole injection from the gate significantly enhance sidegating. In Section 3.3 we propose a mesurement technique to evaluate this hole injection, and our experimental results confirm the participation of holes in sidegating. In Section 3.4 our analysis deals mainly with high- level hole injection and we discuss hysteresis in current-voltage characteristics, geometrical effects and process-related issues in sidegating as a result of hole injection. 3.2 Sidegating effect under conditions of low-level injection 3.2.1 Introduction Weak sidegating has been observed for small sidegate voltages and currents by many researchers, e.g. [8]. In spite of the insulating substrate the sidegate acts as if it were close to the MESFET channel, suggesting that there is a mechanism which transfers the applied voltage to the vicinity of MESFET. 32 Most research has concentrated on strong sidegating accompanied by high-level electron injection into the substrates and predicting the magnitude of a threshold voltage, at which a sharp decrease in the drain current occurs [22, 56]. In this chapter an analysis of weak sidegating is given, which occurs below the threshold voltage. In this range of voltage only low-level injection occurs i.e. the injected densities of free carriers are much less than the equilibrium free carrier densities. While the restrictions on the concentration of injected minority carriers are harsh in the case of an extrinsic semiconductor, they are less severe for SI GaAs in which the equilibrium carrier densities of electrons and holes are not very different from each other. The low-injection regime is valid up to the voltage at which a deviation from ohmic behavior occurs. For material with deep traps, the threshold is the traps-filled-limit voltage or the voltage, at which negative resistance appears[7]. This threshold depends on material properties such as trap densities and distribution, minority carrier lifetime, and homogeneity of the substrate. The threshold voltage could be measured and provided to circuit designers as a designation of the “disaster” area, similar to providing maximum operating drain voltages. The modeling of the low-injection region is more relevant to them, since it occurs in the operating region of transistors. The results of the analysis are provided with flexible boundary conditions, which allow the investigation of a variety of physical situations. 3.2.2 Sidegating model Many numerical studies of isolation in GaAs integrated circuits, performed on symmetrical n-i-n structures, have been published recently[22, 57, 56]. Some of the studies deal with transport equations for majority carriers only, e.g. [56], while others provide more general analysis, but assume restrictive boundary conditions such as ohmic contacts at the edges of the structure [221. These studies do not consider the interaction between gate and sidegate. Our measurements shown in Fig. 3.17 and experimental data by other researchers [58] indicate interaction between gate current and sidegate voltage. The gate current consists of the saturation current of a Schottky diode and the current to a sidegate. Since the saturation current is small, changes in the gate current upon applying sidegate voltage can be easily observed. In Fig. 3.17 the gate current is negative for sidegate 33 160 1o 10_li 0 -2 -4 -6 -8 -10 SIDEGATE VOLTAGE (V) Figure 3.17: ‘Trpical drain and gate currents as a function of sidegate voltage (VD = 2 V, VG = 0 V). The measurements were performed in the dark on depletion-mode MESFETs fabricated by ion implantation into a SI substrate. The typical threshold voltage was —0.6 V. The gate length was 1pm and width 4pm. The gate-source and gate-drain distances were 2pm. The ohmic contact of the adjacent MESFET, which served as a sidegate in our measurements, was placed parallel to the source at a distance of 8pm and was 23pm from the gate. voltage between 0 and —2 V and it is positive for sidegate voltages more negative than —2 V. Also noteworthy is a rapid increase in the gate current when the MESFET is almost pinched off. High Schottky barriers in MESFETs are beneficial, because they increase the noise margin in GaAs digital integrated circuits. But high barriers create an inversion layer beneath the gate, which may inject holes under forward bias conditions, although there is some controversy regarding the magnitude of hole injection[59]. Thus n-i-n structures, in which hole injection is negligible, represent only one particular case of channel-substrate interaction. These structures may represent the conductive path from sidegate to drain and source, but not necessarily that from sidegate to channel. The channel region of the MESFET is sandwiched between two closely spaced depletion regions, which are associated with the. Schottky barrier and the channel-substrate interface. Since the Schottky depletion region is thin, the study of hole injection from the gate should be based on thermionic 120 80 40 l08 l0 1 0 10 34 (b) Distance Figure 3.18: Hole injection from Schottky gate. (a) For a small sidegate voltage. (b) For a large sidegate voltage. emission theory[60}. Figure 3.18(a) depicts the situation for a small sidegate voltage, when the channel is not depleted and a negligible hole current is expected. The drain current decreases upon applying a negative voltage to a sidegate. Larger negative voltages cause a reach-through depletion of the channel as shown in Fig. 3.18(b). A situation similar to reach-through has been analyzed by Wager and McCamant [61], who showed using thermionic emission theory that the hole current can GATE CHANNEL SUBSTRATE Electron Energy A EF Jp (a) Ec Ev Ev Jp. EF— 35 greatly exceed the electron current. We suggest that the sidegating is accompanied by an increase in hole current at the gate. By applying a negative voltage to the sidegate the conductive part of the channel shrinks, allowing more holes to reach the substrate. As we shall see in the next section the hole injection creates a field overshoot causing a high voltage drop in the vicinity of the channel- substrate interface. Consequently, most of the additional applied voltage will drop near this region causing an even stronger depletion of the channel. This will lower the hole injection barrier allowing for many more holes to be injected. Thus this process is self-supporting and for high enough voltages will result in a reach-through depletion of the channel and a rapid increase in the gate (hole) current. An additional source of holes is the avalanche process due to high drain voltage. Electron-hole pairs are generated in the channel. The holes are attracted to the substrate due to an assisting field at the channel-substrate interface, while the electrons “see” an energy barrier of approximately half the band-gap. 3.2.3 Detailed analysis An analytical study of the potential distribution in SI substrates has been made by Ohno and Goto [62]. Their analysis was based on the assumption of local space-charge neutrality, but we report an analysis free of this assumption. Manifacier and Henisch have investigated minority-carrier injection into semiconductors with and without traps by solving linearized transport equations[63, 64, 411. Their detailed analysis was applied mainly to semi-infinite and long structures. We have extended the analysis of Manifacier and Henisch by incorporating both recombination centers and traps into Poisson’s equation. We report a closed foim for the space-charge, electric field and potential distribution in SI short structures. The schematic equilibrium band diagram of the structure analyzed in this paper is shown in Fig. 3.19. The sidegate n+ region is assumed to inject only electrons, while the other contact is assigned a variable injection ratio Additional boundary conditions, which simplify the solution, are zero field at x 0 and x = L [41]. Because of short carrier lifetimes in SI GaAs and distances between MESFETs in integrated circuits, which are typically long in comparison to diffusion length, recombination must be considered. Even though GaAs is a direct band-gap material, the presence 36 GATE CHANNEL SUBSTRATE SIDEGATE Electron Energy Distance Figure 3.19: Schematic band diagram of the gate-sidegate structure in equilibrium. of a high density of deep levels in this material dominates the recombination process[65]. The insulating properties of the GaAs substrate are based on the balance between shallow donors and acceptors, and deep levels. The mid-gap deep donor EL2 with a concentration of about 1016 cm3 plays an dominant role in the compensation mechanism[26]. Nevertheless EL2 acts as a trap rather than a recombination center because of its small hole capture cross section. SI GaAs may contain high densities of deep acceptors in addition to EL2[66, 67]. Wong et al. have proposed some of them as recombination centers with an estimated concentration of at least 5 x 1015 cm3[681. Any general discussion of transport in semi-insulating GaAs should include a dominant recombination center in addition to EL2. Under conditions of low-level injection the recombination rate determined by Shockley-Read-Hall model is given by [41]: fl+fle6p (321) — T(Pe+fle) where 6n, 5p are excess free electrons and holes, e Pe are equilibrium electron and hole concentra tions, and r is the lifetime. The linearized current density and continuity equations can be written as[63, 64] b / d6N 1 + Fe j\E + (3.22) I I 37 -‘1’ ipe(E_) (3.23) ej +_1p(Pe6N+6P)=;O (3.24) __ _ — Pe — 1+.Pe (Pe6N + 6P) = 0 (3.25) with = E/q/nr(ne +pe), (3.26) where- q is the magnitude of the electronic charge, is electron mobility, e is the dielectric constant, and b is ratio of electron to hole mobility. The parameters 61’J, 6P and Fe represent excess free carriers and equilibrium hole concentration respectively, normalized to the equilibrium electron concentration. The field is normalized to kT/qLD, the current density to /tpkT(fle + Pe)/LD and X = X/LD, where = ./[ekT/q2(n + Pe)] (3.27) Poisson’s equation can be written for the general case of non-interacting multiple traps. The concentration of the jth trap occupied by electrons under steady-state condition is given by[691 Nt (c n + et )q = - p (3.28) cn+e+c,p+e where N is the th trap density, e, e, are its emission rates for electrons and holes,c, c, are the capture probabilities for electrons and holes, and n, p are electron and hole concentrations. In equilibrium the occupied density of the jth trap is given by q = (3.29) ie where n is equilibrium electron concentration, and n is electron density if the Fermi level were at the energy level of the th trap. The excess trapped carrier density is (q — q). (3.30) 38 It can be expressed under low-level injection as 6q = cp — (3.31) with NCfle (3.32) = N’e (333) (n+ne)(e+cne+e,+c,pe) In this work we consider only EL2 and a dominant recombination center. The Poisson equation is modified to include these two traps: dE 1 — l+FeP_N+6’+6C2 (3.34) where 6Q, CQ are the concentrations correspondingly of the deep traps (EL2) and recombination centers occupied by electrons and normalized to the equilibrium electron density. Carrier concentra tion, field, and potential profiles are obtained from eqs. (3.22)-(3.25), and (3.34): M cosh (X/i) — R cosh ((L — X)J) 6N(X) = /sinh(L/) + Fe cosh (x) + K cosh ((L — (3.35) sinh (L/) 6P(X) = A[MPC cosh (X) + K cosh ((L — X))i/sinh (L.,/) (3.36) M cosh(X/) — Rcosh((L — X)’)1 /7sinh(L\/) E(X) = A{’ + i3) — M(1 + sinh (X) — K sinh ((L — X)/) + An(Pe + b) sinh (L’) (337) M sinh (X) + R sinh ((L — X)/) -R}+ sinh(L,/) V(X) = ;(1 + cx)M —(1 + 3) An(Pe + b) F(cosh (Xv’) — i) + K[cosh ((L — X)1j) — cosh (L1/)] + i/sinh (L/) (3.38) — M(cosh (X/) — 1) — R[cosh ((L — X)/) — cosh (LI)] + RX} /sinh (L/) 39 10 102 iO- 10-10 -.- -•- - :------. 1 0—13 I I I I 0 2 4 6 8 10 12 14 16 18 20 MICROMETERS Figure 3.20: Concentration profile of trapped and free excess carriers in the 2Opm long model structure. The solid line corresponds to trapped carriers, dashed line to electrons, and dashdots to holes. The carrier densities are normalized to the equilibrium electron concentration The sidegate voltage is —5V, the equilibrium electron concentration is 7 x 106 cm3, the equilibrium hole concentration is 2 x iO cm3, the electron mobility is 4 x iOcm2/Vscc, the hole mobility is 400 cm2/Vsec, and the lifetime is 1 nsec. EU is assumed to be 0.75eV from the conduction band, its density 1016 cm3,and the ratio of its capture cross sections for holes and electrons iO. The recombination center is assumed to be 0.65eV from the conduction band, with density 1015 cm3, and the ratio of its capture cross sections 100. with p = [P(1+)+(i+fl)j/(1+P), = An(Pe+1)/(1+Pe), K = (b+Pe) — Fe, M = (1+3—Ab)/(1+a—A), R = ii(b—M)+M, A = J(1+Pe)/b(M+Pe).Thezero potential reference point is taken at x=0 (see Fig. 3.19). The parameter A is determined by the applied voltage at x=L. Fig. 3.20 shows the distribution of trapped and free carrier concentrations throughout the structure with t’pical trap densities in SI GaAs (N1 = 1016 cm3,N2 = 1015 cm3) and for an applied voltage of —5 V. The MESFET was assumed to inject holes only. The results shown on Fig. 40 101 >- C,, 10° L) N C z 10-1 MICROMETERS Figure 3.21: Concentration profile of trapped excess carriers as in Fig. 3.20, but only in the vicinity of hole injecting edge (x=0). The charge profile changes polarity at around 0.4pm. 3.20 indicate that the local space-charge neutrality is not preserved at any point along the structure. The investigated structure (see Fig. 3.18) represents only part of the two-terminal system, which is confined between two zero-field points. This means that the total excess charge in the structure is zero. Thus the total space-charge neutrality in the structure is preserved, even though local is not. Excess free carrier densities in the structure are below carrier equilibrium values in agreement with conditions of low-level injection. The densities of excess free carriers are far below the trapped carrier density, which means that only the trapped carriers need be considered in the Poisson’s equation. Fig. 3.21 presents a more detailed picture of the trapped carrier concentration in the vicinity of the hole injecting edge. The trapped charge is positive in the very narrow region adjacent to the edge, but is negative throughout rest of the structure. This is a reason for an electric field overshoot 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 41 35 30 25 10 5 0 0 Figure 3.22: Electric field profile in the investigated structure with the same parameters as in Fig. 3.20, but for different densities of recombination centers: dots correspond to 1016 cm3, dashed line to 1015 cm3, and solid line to 1014 cm3. at about 0.4 i.im from the edge as shown in Fig. 3.22. This figure also illustrates the effect of the concentration of recombination centers on the field profile, while keeping the EL2 trap density fixed at 1016 cm3. Reduction of the recombination center density results in a decrease of the field overshoot. In the remaining portions of the structure the electric field is far below the value anticipated for the case of ohmic conduction (5V/20un = 2.5kV/cm). Fig. 3.22 shows that for material with a high density of traps most of the applied voltage drops across the region adjacent to the hole injecting edge, as expected from the presence of the field overshoot depicted in Fig. 3.23. The effect of hole injection on the field and potential profiles is shown in Fig. 3.24 and 3.25 respectively. Hole injection increases the field overshoot and creates a non-uniform voltage distribution across the structure. 2 4 6 8 10 12 14 16 18 20 MICROMETERS 42 -3.5 -4.5 Figure 3.23: Potential profile corresponding to the conditions described in Fig. 3.22. 3.2.4 Discussion Our analysis indicates that the availability of recombination centers and hole injection in the substrate significantly increase the voltage drop in the vicinity of the channel-substrate interface, which in turn may modulate the carrier concentration in the channel or in other words cause sidegating. While the presence of a high density of recombination centers is confirmed by experimental data [681, there are not many studies on hole injection into a SI substrate. As was mentioned, the existence of the inversion layer beneath the gate due to the high Schottky barrier makes hole injection from the gate into the channel possible. Scharfetter has shown that the minority carrier injection in Schottky diodes is negligible because of the small voltage drop across the neutral part of the Schottky diode over a wide range of currents [54]. He, however, considered epitaxial diodes which were long in comparison to the channel thickness of about 0.1 — 0.2 um in modem GaAs MESFETs. Furthermore, 0 -0.5 —1 -1.5 -2 -2.5 -3 -4 -5 0 MICROMETERS 43 25 E 20.f\ l5 U — U 10 5 Od —:-- MICROMETERS Figure 3.24: Electhc field profile in the investigated structure with the same parameters as in Fig. 3.20, but for different values of the minority carrier injection (ij): dots correspond to ij=1, dashed line to 0.5, and solid line to 0. most MESFETs are fabricated by ion implantation, which creates a non-uniform impurity profile and consequently a built-in field. This field will assist holes to move into the SI substrate, while impeding electrons. Zero field is assumed at the edges of the structure, which implies no space-charge in the structure in equilibrium (zero current). But the edges are located at the junctions between doped and SI regions, which exhibit a built-in field and space-charge. Although our analytic results are thus not valid in equilibrium, with structures some tens of micrometers long, only a small error is introduced in the overall potential profiles under non-equilibrium conditions. This is because of a small voltage drop across the heavily doped regions. The depletion region into the channel is small and the zero-field point at the edge of this region will not be far away from the channel-substrate interface. With 44 -0.5 -2.5 -3.5 -4.5 20 increase in applied voltage there will be an extension of the depletion region into the channel. But this extension will be small in comparison to the overall structure. So the boundary conditions introduce only a small error in the overall potential profile across the SI material. The extension of the depletion layer into the channel upon increasing a negative bias on the sidegate may be small in comparison to the sidegate-gate distance, but significant with respect to the channel thickness. To obtain a quantitative picture we superimpose a potential profile of channel- substrate junction in equilibrium with a non-equilibrium potential profile across the SI substrate as shown schematically in Fig. 3.26. Over a wide range of biasing conditions the substrate space- charge density at the channel-substrate junction is a sum of density of deep(Nda) and shallow(Nsa) acceptors[70]. The space-charge may be even higher because of the possible presence of deep levels at the channel-substrate interface created by implantation damage. We assume an abrupt channel- MICROMETERS Figure 3.25: Potential profile corresponding to the conditions described in Fig. 3.24. -1 -1.5 -5 0 2 4 6 8 10 12 14 16 18 45 CHANNEL SUBSTRATE SIDEGATE Figure 3.26: Schematic superimposition of the potential profile across the investigated structure in the presence of a sidegate voltage V0 (dashed line), and for zero applied voltage (solid line). W1 designates the width of the substrate-channel depletion layer. substrate junction with the depletion layer consisting mostly of the substrate depletion region, which is consequently given in equilibrium by: W1 1/2Vbj/q(Nda + Nsa) (3.39) where is the built-in potential of the channel-substrate interface, which is approximately equal to but less than half the band-gap. The voltage across the channel-substrate junction is given by eqn. (3.38) at x = W1. This voltage can be used in evaluating a pinchoff voltage of ion-implanted MESFETs following the procedures in [351. The width of the channel depletion region is [71] — /‘bi_V(Wl))(17da+Nsa) 340 — V q&h(Nh + Nda + Nsa) where Nh is the channel donor density. We have presented a one-dimensional analysis of sidegating, which ignores the drain-source field. The next question that we should ask is how the gate can communicate with the sidegate in the presence of a large drain voltage. For a MESFET biased in saturation, a high-field region is established in the gate-drain region, while the field of about 2 — 3 kV/cm is sustained in the Wi L 46 gate-source region. Since the gate-sidegate field can be comparable to that in the latter region, some of the holes that are injected from the gate towards the source can reach the substrate. To obtain quantitative results a two-dimensional analysis is needed. The phenomenon of sidegating recovery under conditions of large drain voltage has been discussed by several authors, who attributed it to hole injection from the channel due to an avalanche effect[72, 73]. In our experiments this phenomenon occurred only upon applying a very high drain voltage and was not correlated with the appearance of an excess gate current. We suggest that it was due to inhibition of the gate-sidegate communication: for large enough drain voltages, the field in the gate-source region increases and prevents from most of the holes reaching the substrate. Our analysis does not take into account the non-linear velocity-field relationship. The results presented in this paper show that in the presence of hole injection the electric field can only be high only over a very narrow region and in the remaining portions of the structure it is below its ohmic value. Consequently the electron velocity can reach saturation only in the vicinity of the hole-injecting electrode, where it would probably result in an even higher voltage drop in this region. An increase in the voltage drop indicates that a larger portion of the sidegate voltage will be in the vicinity of the channel thus enhancing sidegating. Gunn effect (instabilities due to intervalley electron transfer) has been invoked to explain sidegating and oscillations in GaAs MESFETs[74]. The present work indicates that because of the very low field throughout almost the entire structure in the presence of hole injection, intervalley electron transfer is unlikely to occur. The experiments on semiconductors with traps showed a greatly reduced region of negative mobility in I-V characteristics [75, 76] and, therefore, even at higher fields it is difficult to explain sidegating in terms of the Gunn effect. As has been already pointed out Lee etal. [12] suggested a mechanism of a charge transport in SI GaAs in sidegating effect. Their traps-filled-limit model was based on the high-level injection theory of Lampert and Mark[7]. This model qualitatively explains sidegating, but has some difficulties in explaining it quantitatively [8]. Lampert theory is based on carrier transport by drift only. In contrast, under conditions of low-level injection both the diffusion and drift components of the current are important. Low-level and high-level analyses are just two extremes of the injection phenomenon into 47 semiconductor with traps; namely its small and large-signal analyses. Another important difference between the above two analyses is that they treat different geometries: while the Lampert theory is applicable for long structures, our analysis has been applied to configuration of two relatively closely-spaced contacts, which is a typical case for integrated circuits. Still, both of the theories are important as mentioned before: the results of the small-signal analysis should be useful for circuit designers, while large-signal analysis is useful for predicting abrupt variations in I-V characteristics. In conclusion, sidegating in GaAs MESFETs was investigated using analytical techniques. One- dimensional expressions for carrier concentration, field, and potential profiles in a SI substrate were obtained without some of the assumptions, which are usually made in analytic approaches, such as local space-charge neutrality, neglect of recombination, and diffusion or drift component of the current. A variable boundary condition on the channel side of the structure allowed investigation of injection into a SI substrate. Although only one-dimensional the present analysis provides new insight into device physics. In the presence of hole injection it was shown that: 1. The local space-charge neutrality is not preserved. 2. Both diffusion and drift component currents are important in transport in short SI GaAs structures. 3. The Gunn effect is unlikely to occur in short structures. The analysis was performed on a configuration of two closely-spaced contacts, but the results, such as an appearance of the field overshoot in the presence of hole injection, are similar to those obtained for longer structures [41]. Therefore, the low-injection analysis may explain the long-range sidegating. In our physical model of sidegating hole injection from the gate plays a major role and this is consistent with our experimental observations (see Fig. 3.17), which showed that the gate current is a better indicator of sidegating than the sidegate current. 3.3 Evaluation of hole injection When sidegating occurs the negative sidegate voltage progressively depletes the channel and reduces its electron concentration. Consequently, the potential barrier for holes is reduced and more 48 holes are injected into the channel. Since the channel of low pinch-off ion-implanted MESFETs is very thin, few holes are lost due to recombination in neutral channel, and most of them reach the substrate. Furthermore, due to the impurity profile of ion-implanted devices there is a built- in electric field, which assists holes to move into a substrate. The hole current through the gate may exceed the electron current in the gate-channel-SI-sidegate structure. To show this consider the energy band diagram in Fig. 3.18. Upon applying a negative bias to a sidegate the depletion edge of the channel-substrate junction is pushed into the channel. When two depletion regions merge the electron barrier is reduced allowing more electrons to be injected into the gate. The number of available electrons, however, is limited by their supply from the sidegate determined by the resistance of a SI region. Thus the maximum electron current can be estimated from the electron ohmic current density through a SI substrate: Je = qneVa/L (3.41) where Va is the applied gate-sidegate voltage, and L is the distance between gate and sidegate. On the other hand we can find the hole current from the thennionic emission theory [601, which is applicable here due to a very thin Schottky depletion region. Thus the maximum hole current density is given by: Jpm = A;T2e_01T (3.42) where is the hole barrier height [77] and A is the effective Richardson constant for holes. For = 0.6eV, e = 107cm3,p,, = 4000cm2/Vsec, L = 20im and T’ 3V the hole and electron currents are 5.69 x iO— A/cm2, and 9.6 x 106A/cm2 respectively. Clearly the maximum hole current will strongly depend on the Fermi level at the surface of the channel. For instance, for = 0.55eV we obtain Jpm = 3.9 x 103A/cm2. In low pinch-off MESFETs the distance between the edges of a Schottky gate depletion region and a channel-substrate junction is normally in the range of Debye length. So even for a small decrease in the thickness of the undepleted channel the channel electron concentration deviates drastically from its equilibrium value [271. The maximum electron concentration in the channel can be expressed 49 as [781: no =n1exp(Uo) (3.43) with Uo = sinh1(ND/2n){1 — O.5exp[—(d.— WG — (3.44) where LD is defined in (3.27), n, is intrinsic carrier concentration, d is the channel thickness, WG is the thickness of a Schottky gate depletion region, and Wj is the extension of the channel-substrate junction into the channel. The thermionic emission hole current density can be expressed in temis of the maximum electron concentration in the channel: J8 = A;T2e_(P+vD_)/kT = A;T2Ne_E9/kT/,10 (3.45) where N is the effective conduction band density of states in the conduction band, Eg is the energy band-gap, VD is the built-in potential of the Schottky contact [771, and Vas is the applied voltage on a Schottky contact. Using eqn. (3.43)-(3.45) it is possible to calculate the hole current from the gate into the substrate as a function of a sidegate voltage by determining wj from the sidegating experiment. Our calculations of the hole current as a function of wj reveal that the hole current density does increase significantly when Wj is approaching d — wG, but it is still much smaller than the electron ohmic current density. Upon increasing the negative sidegate voltage the condition of channel punch-through is achieved. With further increase in voltage the hole current increases rapidly until reaching its maximum value, given by (3.42). Our analysis is confirmed by the measurements of the gate current in MESFETs that exhibited a gradual decrease in the drain current upon applying a negative sidegate voltage. The measurements, which are shown in Fig. 3.27, indicate that as the drain current is reduced with a sidegate voltage, the gate and sidegate current increase and above around — 8V they coincide. This indicates that as the channel is progressively depleted, more holes are injected from the gate, increasing the gate current, and more of these holes reach the substrate, where they recombine with the electrons coming from the sidegate. As shown in Fig. 3.28. the gate current and the corresponding sidegate current depend only weakly on the gate bias. This may seem surprising because the gate bias alters the thickness of the undepleted channel and therefore should 50 1 0-3 10-6 —S •e. — 10-v - z 10-s - 10-s - *00* * 0 *** Oo *** 00 ****** 10-10 00000 ******** - 00 0000o8Q 10-11 - 0 0 - 10—12 I I I I I I -14 -12 -10 -8 -6 -4 -2 0 SIDEGATE VOLTAGE (V) Figure 3.27: Drain (solid line), gate (circles), and sidegate (asterisks) currents vs. sidegate voltage (VD = 2V, VG = OV). The gate cia-rent changes its polarity at about —3V. The gate and sidegate currents coincide at the voltages more negative than —8V. affect the voltage, at which punch-through condition occurs. However, it is probably due to the two-dimensional nature of hole injection through the channel, which involves both the gate-sidegate and drain-source interaction. The hole injection is strongest in the region where the drain-source electric field is weakest, namely, between gate and source: By applying more negative gate bias the hole injection from the gate is enhanced, but the electric field in the gate-source region increases as well, resulting in less holes being able to get through the channel. Thus these two effects balance each other resulting in the gate current rise occurring approximately at the same sidegate voltage. In the above section we have proposed a sidegating model based on hole injection from the gate. The purpose of the following section is to report experimental results [421 which confirm the participation of hole injection in sidegating. So far, experimental observation of the participation of 51 180 120Fz U 60 0 0 -5 -10 -15 SIDEGATE VOLTAGE (V) (a) 600. 200 H 0 180 600 120 400 60 200 C/) SIDEGATE VOLTAGE (V) (b) Figure 3.28: Channel punch-through in low pinch-off GaAs MESFETs (VD = 2V, VG : OV to — O.2V): (a) gate current increases rapidly when a MESFET is nearly pinched off as a result of applying a negative sidegate voltage. (b) the corresponding sidegate current. holes in the sidegating effect has been reported only when large drain voltages were applied, and under such biasing conditions the holes are believed to be generated by impact ionization in the channel, 0 -5 -10 -15 52 from where they can be injected into the SI substrate[72, 79, 73]. We report hole injection from the Schotiky gate when no drain voltage is applied. Hole injection from the Schottky metal on a SI substrate has been reported previously [61]. In contrast, we focus on hole injection from the Schottky metal on the doped channel and show that it can be significant for a large negative sidegate voltage. Minority carrier injection in epitaxial Schottky diodes increases with current under conditions of high forward bias[54]. This is related to an increase in the electric field in the quasi-neutral region of the diode. However, since the voltage drop across this region is very small in practical situations, the injection of minority carriers is negligible. The situation is very different in the Schottky gates of MESFETs fabricated by shallow ion implantation into SI GaAs substrates, illustrated by a schematic band diagram shown in Fig. 3.29(a). The structure consists of two closely spaced depletion regions which are associated with the Schottky barrier and the channel-substrate interface. Since the Fermi level is pinned at the channel surface at about 0.8eV from the conduction band [61], there is an inversion layer beneath the gate, that is, at the surface the number of holes exceeds the number of electrons. Under forward-bias conditions the holes are injected from the gate into the channel and are subject to an assisting field due to a steep impurity profile. On applying a negative voltage to the substrate, only a small portion of the applied voltage drops across the Schottky barrier, most is absorbed at the channel-substrate barrier and in the SI region. As a result, the two depletion regions start to merge, and the potential barrier for holes starts to decrease, causing more holes to be injected into the substrate, as shown in Fig. 3.29(b). Manifacier and Henisch have shown that the hole injection into a SI substrate may result in a very large electric field overshoot in the vicinity of the channel [411. This will cause an even higher voltage drop in the channel-substrate depletion region, consequently extending it into the channel and lowering further the hole injection barrier[80]. This process is self-regenerating. At high enough applied voltages it will result in the punch-through of the channel and a rapid increase in the gate current. To test the model, measurements were performed on a structure consisting of two low-pinch-off MESFETs shown in Fig. 3.30. The MESFETs were fabricated in a commercial foundry using direct n and n+ Si ion implantation into undoped liquid encapsulated Czochralski GaAs substrates. The channel width, gate length, gate-source and gate-drain spacings were 4 ,um, 1im, 2 m and 2 ,um, 53 GATE INVERSION LAYER CHANNEL P N Distance Figure 3.29: Hole injection and a corresponding energy-band diagram for a (a) quasi-neutral MESFET, (b) MESFET with a large negative sidegate voltage applied. The combination of the inversion layer, n-channel and semi-insulating substrate creates a P-N-P looks like structure. respectively. The MESFETs had a threshold voltage of about —0.7 V and we estimated the channel thickness to be0.15 pin and the maximum election concentration in the channel to be 1017 cm3. The gate and ohmic contacts of device 2, which were slightly forward-biased, and a negatively biased SUBSTRATE P Electron Energy Jp (a) Ec EF Ev Ec EV ‘p. EF— (b) 54 C4 I I I I DEVICE 1 23 urn 2 urn B I I I I DEVICE 2 SEMI-INSULATING SUBSTRATE (a) (b) Figure 3.30: (a) Cross section of the investigated three-terminal structure consisting of two MESFETs. Using a Schottky (gate) and an ohmic contact (source/drain) of one MESFET together with an ohmic contact of the other MESFET, the structure acts as a surface-barrier transistor with a gate operating as an emitter. (b) An equivalent bipolar transistor structure with a long collector region. ohmic contact of device 1 were used to simulate the interaction between MESFETs. Under these conditions this three-terminal structure functions as a surface-barrier transistor [81, 55] that features hole injection based on the punch-through of the channel as a result of applying a negative collector (sidegate) voltage. Since the channel width is much smaller than the emitter-base distance, most of the injected holes are collected by the substrate. Because of the large emitter-collector distance, the injected holes will recombine with the electrons coming from the collector terminal. Thus the current measured at the collector contact is roughly the hole current of the Schottky diode. A more E (GATE) C (SIDEGATE) lB (SOURCE) 55 x101° F C.) Figure 3.31: Measured currents vs. collector voltage characteristics. The solid line corisponds to the emitter (gate) current JE and the dashed line to the collector (sidegate) current Ic. The leakage current IL (designated by dots) is the current between base and collector when the emitter is floating. accurate estimate of the hole current is obtained by subtracting the base-collector leakage current from the measured collector current. The measured currents are presented in Fig. 3.31. The hole injection ratio, which is the ratio of the hole-to-emitter current, is shown in Fig. 3.32 as a function of collector bias and emitter-base bias as a parameter. The hole injection is negligible for collector bias between zero and— 1.5 V, but increases significantly for more negative voltages, in good agreement with the model. -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 COLLECTOR VOLTAGE (V) 56 0c) COLLECTOR VOLTAGE (V) 0 Figure 3.32: Calculated hole injection ratio, defined as (Ic — IL)/IE, for the emitter-base bias of 0.1 V (solid line) and 0.2 V (dashed line). ‘E”C and ‘L are defined in caption of Fig. 3.31. -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 57 3.4 High-level double carrier injection in the sidegating effect 3.4.1 Introduction and Model We have already noted that Lee et at. [12] found a correlation between substrate current and sidegating and explained it by the traps-filled-limit model (TFL) [20]. According to Lee et at. [12] electron injection from the sidegate to the MESFET channel-substrate interface is initiated at a certain threshold voltage, determined by the sum of sidegate and drain voltages. However, TFL model predicts threshold voltages larger than normally observed [8, 9]. Also, some sidegating experiments have been reported, where no dependence on drain voltage was found [8]. Furthennore, the oscillations which have been observed by several researchers (e.g. [741) and the recently reported hysteresis in the sidegate current [15] are difficult to explain in terms of single carrier space-charge- limited conduction. In the above studies of sidegating the interaction between gate and sidegate has not been considered, and measurements of the gate current were not reported. It has been established that in Schottky barriers consisting of metal on n-type doped semiconductor under forward bias minority carriers can be injected from the metal into the semiconductor [82], although there is some controversy regarding the magnitude of hole injection in Schottky diodes [59]. Hole injection from positively biased metal pads into the semi-insulating GaAs substrates was discussed by Wager and McCamant [61]. Goto et at. [83] analyzed the sidegating effect, based on the numerical simulation of a structure that included Schottky metal on the SI substrate, and explained it in terms of hole injection from the gate. Their results did not show hysteresis in I-V characteristics and consequently in their analytical model they did not try to explain the instabilities often observed in sidegating effect. Recently a series of measurements by Liu et at. [58] showed that a small portion of the gate that overlaps the n-channel on to the SI substrate can play an important role in the sidegating effect. Our physical model is based on experimental observations of strong dependence of the gate current on the sidegate voltage, and new results, which relate the gate current jumps to hysteresis in test devices [43]. We propose that these phenomena originate from double injection into the SI 58 substrate. We suggest that the gate, when biased positively with respect to the sidegate, is a major source of hole injection frito the SI substrate. At low sidegate voltages low-level double injection creates a non-linear potential profile across the SI substrate, resulting in a significant portion of the sidegate voltage being applied on the channel- substrate junction. For a high enough sidegate voltage the transit time of holes from the gate to the sidegate across a SI substrate becomes less than their lifetime. The holes reach the vicinity of the electron injecting sidegate, compensate the negative space charge formed there by the trapped electrons, and consequently cause a steep rise in the sidegate and gate currents. This is a high-level double injection mechanism, which is known to produce a negative resistance in I-V characteristics often exhibited through hysteresis and oscillations [20, 84]. Reduction of the space charge in the vicinity of sidegate results in many more electrons being injected into the channel-substrate interface. The injected electron charge is compensated by further extension of the depletion layer into the channel, resulting in a sharp reduction of the drain current. Our experimental results confirm the importance of hole injection as proposed by Goto et at. [83], but our model suggests a new and more general interpretation of their results. 3.4.2 Experiments We now report some new experiments which indicate double injection in the sidegating effect. Low pinch-off (threshold voltage — O.7V) depletion mode ion-implanted GaAs MESFETs fabricated at a commercial foundry were used with gate length 1 pm and width 4 pm. The gate-source and and gate-drain spacings were both 2 pm. The sidegate was 8pm from the source and 23 pm from the gate. The layout of the test structure is shown in Fig. 3.33. An HP 4145A semiconductor parameter analyzer was used to obtain I-V characteristics at room temperature in the dark. Fig. 3.34 shows MESFET drain, gate, and sidegate currents versus sidegate voltage. The drain voltage was 2V and the gate was grounded. The drain current gradually decreased starting from a sidegate voltage of -3V. Jumps in the currents occurred at a sidegate voltage of about -6V. Correlation between gate and sidegate currents was apparent not only in that jumps in each occurred at the same 59 Figure 3.33: Schematic layout of the mirror-image structure of two MESFETs that were used in the sidegating measurements. The channel width, gate length, gate-source and gate-drain spacings were 4 pm, 1 pm, 2 pm and 2 pm respectively. The dotted area is the active layer area of the MESFETs. When one of the MESFETs was biased, the other’s ohmic contact served as a sidegate. The sidegate was 8 pm from the source and 23 pm from the gate. sidegate voltage, but also in that they then exhibited the same magnitude. Changes in drain voltages (VD : 0.5 — 4V) had no effect on the sharp threshold voltage. The drain current as a function of sidegate voltage for a MESFET with the gate floating and the drain voltages from 1 to 5V is presented in Fig. 3.35. At drain voltages below 3V a soft threshold behavior was exhibited with no evident current jumps. Also no jumps were observed in the sidegate current (not shown in Fig. 3.35). However, with increasing drain voltage a jump in the drain current appeared, which corresponded to the jump in the sidegate current. The current between the grounded gate and the biased sidegate as a function of a negative sidegate potential, with the remaining electrodes floating, is shown in Fig. 3.36. This figure also shows MESFET current-voltage characteristics when the source and drain are biased. Both the gate and drain currents exhibited hysteresis with the same two threshold voltages at about -5V and -6V. The hysteresis behavior described here was reproducible when long integration time and small voltage 60 z 4 I z w cx D () w I— 4 CD 4 z D C-) w I.— “ 4 CD w (I)10 Figure 3.34: Drain, gate and sidegate currents as a function of sidegate voltage (VD = 2V, VG = OV). 150 I— Z 100 Li ‘-‘50 0 iO—8 10 1010 108 10 0 —2 SIDE GATE —4 —6 VOLTAGE (V) 61 400 3 300 z LIJ D200 U z 4 100 0 0 —2 —4 —6 SIDEGATE VOLTAGE (V) Figure 3.35: Drain current versus sidegate voltage for a MESFET with a floating gate (VD : 1 — 5V). steps were used in the measurements. For the sidegate positively biased with respect to the gate neither current jump nor hysteresis were observed. Note that Li et at. have shown that the hysteresis in sidegating is an artifact of the voltage-controlled measurement and in the current-controlled case the current-voltage characteristics exhibit negative resistance [15]. We, however, haVe performed our measurements by applying constant sidegate voltages, because these measurements imitate the real-life environment in the GaAs integrated circuits, in which the worst-case sidegating is determined by the negative voltage supply (which ideally is a supplier of unlimited current). 3.4.3 Analysis and Discussion Double injection into a semiconductor with traps is known to produce a negative resistance regime [20, 84], which exhibits current jumps, oscillations and hysteresis as found in sidegating 62 108150 100 i0 F— C.) c_) z 50 1010 0 10h1 -1 -2 -3 -4 -5 -6 -7 SIDEGATE VOLTAGE (V) Figure 3.36: Hysteresis in the drain current (VD = 2V, VG = OV), and in the gate-sidegate current (source and drain are floating). The solid line represents a decreasing (more negative) sidegate voltage, while the dotted line represents the opposite direction. experiments. The following observations in our experiments, even if separately they do not prove the double injection mechanism, together provide strong evidence for it. I. Sidegate and gate currents were found to be equal after a threshold sidegate voltage was reached. This indicates direct communication between gate and sidegate. 2. Hysteresis and current jumps in the gate-sidegate structure did not appear upon applying a positive sidegate voltage, but only under forward bias conditions (negative sidegate voltage), for which hole injection from the Schottky gate is possible [821. 3. Drain current-voltage characteristics exhibited hysteresis with threshold voltages corresponding to the ones observed in a gate-sidegate structure. Thus MESFET characteristics are directly related to the transport mechanism between gate and sidegate. 0 63 4. Hole injection is not expected in MESFETs with a floating gate operating at low drain voltages and, consistently, no jumps in the drain or sidegate currents were observed in our experiment under such biasing conditions as shown in Fig. 3.35. However, for larger drain voltages Fig. 3.35 shows jumps in the drain current accompanied by jumps in the sidegate current. It is possible that the gate obtains an intermediate value between drain and source voltages, which cause it to be forward-biased. In this case there is no difference between these results and those shown in Fig. 3.34. However, the prebreakdown impact ionization effects, observed by Tsironis [85] in GaAs MESFETs and epitaxial layers for drain voltages higher than 4-5 volts, also may explain our observations. Thus, the prebreakdown impact ionization generates pairs of holes and electrons in the channel. Because of the energy barrier at the channel-substrate interface only high-energy electrons can be injected into the SI substrate. By contrast, holes have an assisting field at the interface and consequently are attracted by the negatively biased sidegate and participate in the double injection process causing the current jump. Fig. 3.34 shows that soft and sharp gate current reduction corresponds to soft and sharp and drain current reduction with a threshold at -3V and -6V respectively. It is difficult to explain the sharp current reduction by electron injection from the sidegate for a drain-sidegate distance of 26km, a drain voltage of 2V and a sidegate voltage of only -6V. For instance, a recent numerical analysis of n-SI-n structures indicates that electron current increases significantly at about 1OV applied on aS m one-dimensional structure [56]. Even higher threshold voltages were obtained for two-dimensional structures. Furthermore, as already mentioned in subsection 3.4.2, the sharp threshold voltage did not change due to variations in a drain voltage. This is not expected from the TFL model, which predicts a decrease in the sidegate threshold voltage with increasing drain voltage. Fig. 3.36 indicates that the drain current reduction is caused by the gate-source interaction. The current jumps and hysteresis in gate-sidegate structure were observed at an applied field of 2.5kV/cm, which is too small to initiate impact ionization, that can also produce hysteresis in I-V characteristics [15]. Furthermore, Fig. 3.34 shows clearly that the gate current is a strong function of sidegate voltage. Even before the current jump, a sidegate voltage of -3V is enough to reverse the gate current polarity, which indicates abnormal MESFET operation. If we consider a MESFET 64 Ec EF Ev Distance Figure 3.37: Schematic energy-band diagram of a MESFET gate on a SI substrate. on a SI substrate as a combination of three Schottky diodes, then the experiments show that for high enough sidegate voltage the gate-sidegate diode is dominant. We, therefore, concentrate on the gate-sidegate interaction. As shown in Fig. 3.33 there is a part of Schottky metallization that is on a SI substrate. Fig. 3.37 depicts the energy levels in equilibrium of a gate on a SI substrate. The Fermi level is pinned at about 0.8 eV [601 from the conduction band and as a result an inversion layer is formed beneath the gate. The thickness of the Schottky depletion region is given by [861: ‘Wdep /2cVD/qNEL2 (3.46) where VD is a Schottky built-in potential. For VD = 0.15eV and IEL2 = 106cm3we obtain Wdep O.15im. If a negative bias is applied on the sidegate the gate becomes forward biased. Since the Schottky depletion region is thin we can discuss the transport across the Schotiky contact in terms of thermionic emission theory [601. Under these conditions the hole injection from the metal was shown largely to exceed the electron injection [61]. Thus, the gate-SI-sidegate structure acts as a P-I-N diode with a heavily compensated intrinsic region. For low sidegate voltages we deal with low-level double injection between gate and sidegate. Under these conditions the potential distribution across a SI substrate can be calculated using eqn. (3.38). Fig. 3.25 shows the results of this calculation which indicate that a significant portion of the Energy GATE SI GaAs 65 voltage across a SI substrate is dropped in the vicinity of the hole-injecting boundary. This potential profile is a result of the dipole, consisting of positive and negative excess trapped carriers, which is formed in the close neighborhood to the hole-injecting interface [80]. Three major contributors to the formation of the dipole are high trap densities, high ratio of electron to hole mobility, and low lifetime in SI GaAs [41]. When only a small portion of the applied gate-sidegate voltage is dropped across a Schottky depletion region, the results in Fig. 3.25 show that in the presence of hole injection a significant portion of the applied voltage is dropped across the channel-substrate interface. A gradual increase in the applied negative voltage will result, consequently, in a gradual decrease in the drain current as shown in Fig. 3.34 for low sidegate voltages. During the double low-level injection a negative space-charge region is formed in the vicinity of sidegate by the electrons trapped in deep EL2 levels. For higher sidegate voltages the transit time of holes across a SI substrate becomes comparable to their lifetime. They reach the vicinity of a sidegate electrode and reduce the negative space-charge. As a result many more electrons are injected into the substrate and reach the channel-substrate depletion region. The injected negative charge is compensated by the depletion of the channel, resulting in a strong decrease in the drain current. During the injection process some holes are captured by the recombination centers. As a result hole lifetime increases and consequently a smaller voltage is needed to bring holes to the sidegate electrode. This is the source of the appearance of a negative resistance in double injection process according to Lampert’s theory [20]. In our experiments the devices that exhibited sharp sidegating also exhibited hysteresis. We have investigated an appearance of hysteresis in the gate-sidegate structures. The source and drain were floating, the sidegate was grounded, and the gate was positively biased. The negative resistance regime started typically between 5 to 6V and was accompanied by a strong increase in the current as shown in Fig. 3.38. The location of the second threshold varied from device to device over the range of 6 to 1 8V. Neither hysteresis, nor current jumps were observed in gate sidegate structures when the gate was negatively biased with respect to the sidegate. According to Lampert’s theory [20] the current increase in the negative resistance regime should be approximately given by the ratio of the recombination center density to the equilibrium free electron concentration. For a recombination center density of 105cm3and the electron concentration of 107cm3 in SI 66 GaAs we should expect an abrupt increase of eight orders of magnitude in the current. But in our experiments we observed an increase of a maximum of five orders of magnitude in the current. Our results are in agreement with the studies of GaAs P — I — N diodes reported by Weiser and Levitt [87], and Seiway and Nicolle [88]. They found the appearance of a negative resistance at voltages and currents smaller than those predicted by the Lampert [201 or Ashley-Milnes [84] theories and explained it in terms of an optical feedback mechanism suggested in GaAs by Dumke [89, 84]. Additional mechanisms of double injection such as filament formation were proposed for GaAs [84]. According to Dumke’s model under increasing external illumination the negative resistance should decrease and disappear. We performed this experiment on our gate-sidegate structures and the results, which confirm Dumke’s theory, are shown in Fig. 3.38. Nevertheless, the threshold voltage for the end of a negative resistance regime in double injection process according to the Lampert’s one-dimensional model for an insulator with length L [20]: Vth =L2/21.tr; (3.47) are in the range normally observed, e.g., taking L 23iim, = 320cm/Vsec [90], and a typical hole lifetime in high-resistivity GaAs r = lnsec [91] we obtain a threshold voltage of 8.3V. Geometrical effects in sidegating become very important when holes are injected from only a small portion of the gate that is on a SI substrate. In this case the double injection process occurs only beneath part of the channel, as visualized in Fig. 3.39. Thus the sidegating effect can be analyzed using an equivalent circuit consisting of two MESFETs in parallel. One of them will be cut off under conditions of strong double injection, while the other is not influenced by it. This may explain why the MESFET in Fig. 3.34 was not completely cut off after a jump in the gate current had occurred. Not all gate-sidegate structures on the same wafer exhibited hysteresis. We suggest that this is due to substrate inhomogeneity involving variations in the concentration of the recombination centers either present in the as prepared wafer or process-induced, for example as a result of ion implantation. In addition, double injection is expected to be strongly dependent on the thickness of the oxide layer, which is normally present between a gate and a SI substrate. The non-uniformity of the oxide layer across the substrate can result in different sidegating behavior for devices on the same 67 10-s 10-a io- 10-6 Q 10 10-s 10-s C 10-10 10-11 10-12 Figure 3.38: Hysteresis in the gate-sidegate structures under increasing illumination (VSG OV, drain and source are floating). The solid line corresponds to the data obtained in the dark, dashed line corresponds to the data obtained with room lights, and the open circles correspond to the data obtained under microscope lamp illumination. Results obtained in the dark or with room lights show hysteresis, while those obtained under direct illumination show no hysteresis. wafer. Therefore, the gate formation processing steps, particularly oxide removal before depositing a Schottky metal, can be important in determining sidegating. In this case, the sidegating effect can be different from one process run to another, even if identical substrates are used. Since the negative resistance in gate-sidegate structures may appear at sidegate voltages, for which a MESFET is already cut off, it may easily be overlooked. But the hole injection from the gate on a SI substrate is still present, resulting in a soft, but not necessarily a weak, sidegating effect. In conclusion, double injection should be considered in investigating sidegating associated with a sharp threshold behavior. We propose a physical model, which accounts for abrupt current variations 0 2 4 6 8 10 12 14 16 18 20 SCHOTrKY GATE VOLTAGE (V) 68 GATE Figure 3.39: Schematic top view of the area (designated by gray pattern) that is affected by hole injection from the gate on a SI substrate. and hysteresis in sidegating. Our measurements of hysteresis are in general agreement with Dumke’s model for double injection in GaAs. The predominant mechanism of double injection, however, is probably to be determined by device geometry and material properties. The role of hole injection in enhancing soft sidegating effect was discussed through the analytical expression for the potential distribution across a SI substrate. Our model accounts for sidegating light sensitivity [13] because photo-generated hole-electron pairs will participate in the double injection process: the generated holes will be attracted to the negatively biased sidegate through a SI substrate, in a similar way of attracting holes generated by a prebreakdown impact ionization. It was shown that a channel punch-through may result in significant hole injection from the gate. Our analysis of hole injection does not take into account the difference in the gate and sidegate areas, which can be significant. Hole injection for small-area Schottky diodes was shown by numerical analysis to be much higher than that for the large contact devices [92]. More accurate treatment will require two-dimensional SIDEGATE 69 analysis, which is beyond the present scope of this work. Our results show the need to include gate current measurements in investigating the sidegating. 3.5 Summary Double injection into the SI GaAs substrate was investigated as a mechanism of sidegating in GaAs MESFETs. We propose a physical model for sidegating based on a series of measurements, which show change of gate current with sidegate voltage and correlation between abrupt variations in drain, gate and sidegate currents and instabilities in test devices. An analytical treatment of carrier, field, and potential distribution in a SI substrate under conditions of low-level injection shows that an electric field overshoot may develop in the vicinity of the MESFET when hole injection occurs. This results in a large portion of the applied voltage being dropped across the channel-substrate interface and, consequently, in sidegating. Sharp sidegating, exhibited through an abrupt decrease of the drain current, is explained by high-level double injection. Measurements of currents in gate-source-sidegate structures, when the gate is slightly forward- biased and the sidegate is negatively biased with respect to the source, showed that significant hole injection from the gate occurs for large sidegate voltages. This is in agreement with a proposed model, in which the presence of an inversion layer under the Schottky gate due to the pinning of the Fermi level at the channel surface causes hole injection into the channel when the gate is positively biased with respect to the sidegate. Upon increasing negative sidegate voltage the substrate-channel depletion region is expanded, and consequently, the neural region of the channel is shrunk. This results in more holes being injected into the substrate from the gate. 70 Chapter 4 Low-frequency transport in semi-insulating GaAs 4.1 Introduction In silicon the presence of deep levels was shown to introduce low-frequency dependence into the capacitance and conductance of a p-n or metal-semiconductor junction [29, 51, 69, 44]. It is also well known that many of the parameters of GaAs MESFETs on SI substrates exhibit low- frequency-dependent behavior. While the frequency dependence of some of the parameters (e.g. transconductance) has usually been attributed to the surface states [481, it has been pointed out by many researchers, e.g. [93], that the frequency dependence of the output conductance is due to the properties of the SI substrate. The analysis of transport in SI GaAs in the frequency domain is therefore vital for understanding many of the properties of GaAs MESFETs at low- frequencies. Furthermore, this analysis contributes to the understanding of crosstalk between two adjacent MESFETs on a SI substrate [40, 94]. 4.2 Analysis and results We assume that both deep donors and deep acceptors are present in the SI GaAs one-dimensional structure confined between two contacts: contact 2 is an ohmic contact which can inject only electrons, while contact 1 is a Schottky contact which may inject holes and is assigned a variable injection ratio (j=0 corresponds to zero hole injection, and =1 to zero electron injection). The schematic equilibrium band diagram of the structure is depicted in Fig. 4.40. In Chapter 3 we reported an analytical study of the DC charge, field and potential distribution in such structures [801. Our analysis was based on the investigation of minority-carrier injection into semiconductors with traps by Manifacier and Henisch [64, 41]. We assume that the deep levels in the structure do not interact and thus separate rate equations can be written for each level. If we restrict the magnitude of excess charge densities to small variations around their equilibrium values then the rate equation for a single 71 CONTACT 1 CONTACT 2 Electron C Energy Semi-insulating GaAs fl+ 0 Distance L Figure 4.40: Schematic equilibrium band diagram of the semi-insulating structure of a length L between zero-field points in the vicinity of N+ and Schottky contacts. deep level is given by [29]: döN 6N( + e + CpPe + e) + n1V — öPIVt c (4.48) where N is the density of a deep level, e, e are the emission rates of a deep level for electrons and holes,c, c, are the capture probabilities of a deep level for electrons and holes, and e Pe are the equilibrium electron and hole concentrations, n1 is the electron density if the Fermi level were at the energy level of the deep level. We decompose the excess free electron, free hole and trapped electron densities respectively into AC and DC components to yield: n(x) = bnd(x) + ön(x)eWf (4.49) öp(x) = bPdc(X) + 6pac(x)eLi, (4.50) öNt(x) = 6N(x) + JV(x)&wt. (4.51) 72 Substituting (4.49)-(4.51) into (4.48) to obtain: 6N(x) = /36ac() — ae5Pac(x) (4.52) with D ATT TT (453) rD(1+jwr) r(1+jwr)n D A — TT TT (4.54) rD(1+jwr) p where indexes D and A designate deep donors and deep acceptors respectively, 1/T’4 CAfle + e + CpDAPe + el)A (4.55) D,A D,A I DA = cDAN fli /ifle + i ), (4.56) l/r1)A = CpNPAfle/(ne + DA) (4.57) For w = 0 a and yield DC solutions [801 as expected. The linearized [63] time-dependent continuity equations for electrons and holes, and Poisson’s equation can be written as: a2iv 8E A F) = qL (4.58) 8X2 kTr ___ _ OE Ab 6F) = qL 06P (4.59) aX2 _Fe_i+p(Fe5N+ ikTôt dE 1 dX — 1 + Fe [(1 + c46F — (1 + 3)6N] (4.60) with LD =5,/[kT/q2(n + pe)j, A = e/qpnr(n + Pe), where a and /3 are defined in (4.53) and (4.43), q is the magnitude of the electronic charge, p is the electron mobility, jt,,, is the hole mobility, b = r is the lifetime, is the dielectric constant, 5N, 6F and Fe are the excess 73 free carriers and equilibrium hole concentration respectively, normalized to the equilibrium electron concentration. The field is normalized to kT/qLD, the potential to kT/q, the current density to ,upkT(ne + Pe)/LD and the distance to LD. Substitution of (4.60) into (4.58)-(4.59) and decomposing the excess electron and hole densities into the DC and AC components yields two coupled differential equations, which can be separated into DC and AC parts. For frequencies much below the reciprocal of carrier lifetime the AC and DC sets of equations are identical, except in the AC set and /3 are given by (4.53) and (4.54). As a result excess carrier concentration and potential profiles in the frequency domain are readily obtained from the DC solution for zero field boundary conditions [801: 6Nac(X) A[Mc0sh — Rcosh((L — X)/) + Fe cosh (xj) + K cosh ((L — (4.61) /sinh(Lv”) 6Pac(X) = A[MPe cosh (X.J) + K cosh ((L — X)/) -,/sinh (L/’) (4 62) — Rcosh((L — X’)1 4/sinh (Lj) v (l+)M—(1+/3)( — A(P6+b) Fe(cosh (X/) — i) + K{cosh ((L — X)./r) — cosh (L/’)] + v”sinh (L/) (4.63) — M(cosh (X’) — 1) — R[cosh ((L — X)) — cosh (L1/)} + RX} ,/Z sinh (L/) with v = [Pe(1+)+(1+/3)j/(1+Fe), = An(Fe+b)/(l+Fe), K = — PC, M = (1+/3—Ab)/(1+a—A), R ii(b—M)+M, \ Jac(l+Pe)/b(M+1e). The normalized admittance Y is obtained from (4.63): = tlac/Vac(L) = G + jwC. (4.64) The distribution of excess trapped and free carriers calculated from eqs. (4.52), (4.61), (4.62) for the hole injection ratio i=0 is shown in Figs. 4.41—4.42 for 1Hz and 1MHz correspondingly. Figs. 74 10 10 10-1 10 10 -- - - — - - — — -- -- — — — — — 10-13 - -. - 10—16 I I I I — 0 5 10 15 20 25 30 35 40 45 50 MICROMETERS Figure 4.41: Concentration profile of excess trapped and free carriers in the 5Opm long model structure at 1Hz with no hole injection (j=O). The solid line corresponds to trapped carriers, dashed line to electrons, and dots to holes. The amplitude of AC applied voltage is 5OmV, the equilibrium electron concentration is 7 x 106 cm3, the equilibrium hole concentration is 2 x iO cm3, the electron mobility is 4 x iOcrn2/Vsec, the hole mobility is 400cm2/Vsec, and the lifetime is 10 nsec. The deep donor is assumed to be 0.75eV from the conduction band, its density 2 x 1016 cm3,and with the capture cross section of lx 10’3cm2for electrons and 1 x 106cm2for holes. The deep acceptor is assumed to be 0.65eV from the conduction band, with density 5 x 1015 cm3,and with the capture cross section of 1 x 103cm2for holes and 1 x 106cm2for electrons. 4.43—4.44 show the distribution of excess trapped and free carriers calculated for =1 at 1Hz and 1MHz correspondingly. Fig. 4.45 shows conductance as a function of frequency evaluated from the real part of eq. (4.64) for =t0 and =1. Fig. 4.46 shows the capacitance as a function of frequency evaluated from the imaginary part of eq. (4.64). 75 10-s 10-a 10-i 10-6 CID U 10-10 10-11 Figure 4.42: Concentration profile of trapped and free excess carriers at 1MHz with no hole injection. The rest of the parameters are given in Fig. 4.41. 4.3 Discussion The solution of the transport equations in semiconductors was shown by van Roosbroeck and Casey [95] to be largely dependent on whether dielectric relaxation time is smaller or larger than carrier lifetime, and, consequently, they classified semiconductors into lifetime or relaxation types. In the latter. no local space charge neutrality but rather charge separation through zero net local recombination is established. When the local space charge neutrality (6IV = .5F) is not assumed the solution of the continuity equations and Poisson’s equation under conditions of low- level injection results in terms containing exp(tXy’) and exp(tXv’). The parameters and can be expressed in terms of a static screening length L3 and an ambipolar diffusion length LDa [96] respective1y:/ = LD/L8, LD/LDa. Manifacier and Henisch modified 0 5 10 15 20 25 30 35 40 45 50 MICROMETERS 76 10 I I 10 10- •—-- - N 10 10 — —. — — —— —— — — 10—13 I I I I 0 5 10 15 20 25 30 35 40 45 50 MICROMETERS Figure 4.43: Concentration profile of trapped and free excess carriers at 1Hz in the presence of hole injection (ij=1). The rest of the parameters are given in Fig. 4.41. the criterion suggested by van Roosbroeck and Casey [95] and classified semiconductors with traps into a lifetime or relaxation case according to the ratio LDa /L3 with a large ratio corresponding to lifetime semiconductors and the small to relaxation semiconductors [96]. When frequencies approach 1/TT both excess trapped and free carriers become frequency-dependent through cr and (see eqs. (4.53)-(4.54)). Note that TT does not depend on the trap density and thus the frequency dependence is not necessarily initiated by the trap with largest density. Indeed, in our case rF is about O.O3sec, while T is about 0.4sec and determines the range of frequencies in which frequency-dependent phenomena appear. Thus at 1Hz LDa is about 3j1m and the absolute value of L3 is about O.08itm. At 1MHz the ambipolar diffusion length is the same but L3 changes significantly and it now stands at about 34gm. Consequently, SI GaAs exhibits lifetime-like behavior at low, frequencies, but behaves 77 10-2 10-6 10-v 10-8 10- Figure 4.44: Concentration profile of trapped and free excess carriers at 1MHz in the presence of hole injection (= 1). The rest of the parameters are given in Fig. 4.41. like a relaxation semiconductor at high frequencies. Note that the assumption of local space-charge neutrality results in the solution containing only exp( tX./). which are frequency-independent at low frequencies (much below the reciprocal of carrier lifetime). At 1Hz (see Figs. 4.41 and 4.43) the distribution of excess trapped and free carriers in the bulk of SI GaAs is dominated by exp( tXv’Z’) since the diffusion length is much larger than the screening length. When hole injection occurs (see Fig. 4.43) the electrons move so as to neutralize the injected holes. The excess hole and electron densities are both positive and have similar exponential distribution throughout the structure, which is expected for a lifetime semiconductor. But in contrast to the classical lifetime behavior the local space charge neutrality is not preserved due to the high density of the traps in the SI substrate. At 1MHz the charge distribution in the SI structure is becoming 1 0- 10-i 10-s 10-10 0 5 10 15 20 25 30 35 40 45 50 MICROMETERS 78 L) F L) N 0 z Figure 4.45: Frequency dependence of the conductance of the SI structure calculated using eq. (4.64). The dashed line corresponds to the conductance in the presence of hole injection (17=1) and the solid line to the conductance when no hole injection occurs (17=0). The rest of the parameters are given in Fig. 4.41. less sensitive to the presence of hole injection (see Figs. 4.42 and 4.44). Since the screening length now is larger than the ambipolar diffusion length when hole injection occurs the effect of the latter on the carrier distribution appears only within the distance LDa from the hole-injecting contact. After this the material is dominated by the zero net local recombination, which is typical of relaxation semiconductors, resulting in 6P(X) PeN(X).[4lj. Normally in SI GaAs Fe = Pe/fle < 1 and hence the excess hole and electron densities have opposite signs with the electron density being larger. This is observed in Figs. 4.42 and 4.44. Since the zero field boundary conditions dictate the total excess charge neutrality the excess carrier density changes sign around the middle of the structure. Comparison between the carrier profiles at lHzand 1MHz reveals that the ratio of free to trapped carriers increases with frequency. The charge injected into the SI structure consists of a free and 10-8 10-1 100 101 102 l0 10 iO 106 lO 108 lO FREQUENCY [Hz] 79 1 0- I I 10-8 - 1 O- 10-10 10-1 10° 10’ 102 10 10 iO 106 iO 108 10 FREQUENCY [Hz] Figure 4.46: Frequency dependence of the capacitance of the SI structure calculated using eq. (4.64). The dashed line corresponds to the capacitance in the presence of hole injection (ij=l) and the solid line to the capacitance when no hole injection occurs (=O). The rest of the parameters are given in Fig. 4.41. trapped charge. At 1Hz most of the injected carriers will be trapped which results in low conduction. At high frequencies few injected carriers are immobilized in traps and thus most contribute to the free carriers resulting in higher conduction. Fig. 4.45 shows that at low frequencies the conductance is reduced in the presence of hole injection. This is because the injected holes attract the much more mobile electrons to the vicinity of a hole-injecting contact. At low frequencies the spatial distribution of injected free electrons resembles the distribution of free holes, as a result of the attempt to preserve local space charge neutrality. This results in a diffusion of the electrons in the same direction as the holes, thus decreasing the total current and, consequently, the admittance [411. At higher frequencies this phenomenon is eliminated due to the fact that the free carrier distribution is detemined by zero local recombination. This 80 results in the frequency response being insensitive to hole injection. At low frequencies in the presence of hole injection both the hole and electron traps play an important role in determining the charge distribution as shown in Chapter 3 and in Ref. [80], and, therefore, their frequency responses determine the frequency dependence of the conductance. The conductance starts to increase at about 0.4 Hz, which corresponds to the time constant associated with the hole trap r. This is due to the fact that a reduction in the hole trap density in the presence of hole injection will increase the conductance [41]. This increase saturates at about 5 Hz, which corresponds to the time constant associated with the electron trap r. This is because at this frequency the electron trap density starts to decrease, and thus compensates the reduction of the hole trap density. In the absence of hole injection an ohmic conduction will dominate the transport in SI GaAs at low frequencies, and therefore the frequency response of the deep levels has almost no effect on the conductance as can be seen in Fig. 4.45. There is another bump on the conductance curves, which occurs between I kllz and 50 kHz. This frequency range is determined by the frequencies at which 1/31 = Ab and = A. The first frequency can be evaluated to be fi J1/(TAb)2 — 1/(rf)2/2ir, and the second one is f2 /1 / (rA)2 — 1 / (r )2/27r. Note that fi, f2 depend on the traps characteristics through r, and TT, and on the mobility and lifetime through A. The conductance increases a few orders of magnitude in the MHz frequency range and then saturates with frequency. The sharp increase begins at about 0.5 MHz when L1/i1 1, and ceases at about 0.5 0Hz when l/l 1. Clearly, the frequency at which the conductance starts to increase depends not only on the frequency response of the deep levels, but also on the distance between two electrodes: it decreases as the distance decreases. If hole traps are not included in the simulation, or their density is greatly reduced the discrepancy in the curves due to hole injection vanishes. If several electron traps are included in the simulation, their effect on the admittance can be examined in terms of their contribution to /3 which dominates over a because for an electron trap 3 >> a due to the difference in the trap capture cross-sections for holes and electrons. In the absence of hole injection the trap with the highest density will normally be dominant at frequencies up to the corresponding 1/TT, after that the dominance is transferred to the trap with the second largest density, which has a higher frequency response, etc. Thus in this case a low-density trap would determine the admittance behavior in a 81 certain frequency region, if it outlived rest of the higher-density traps. A shalio electron trap will normally have a higher frequency response than a deep electron trap, if both of them have similar cross sections for electrons. Therefore, inclusion of a shallower electron trap in addition to EL2 will result in the strong increase of the conductance starting at higher frequencies. Fig. 4.46 depicts the frequency dependence of the capacitance. In the presence of hole injection the capacitance starts to decrease at about 5 Hz, which corresponds to r and then saturates at about 50 kHz, which corresponds to f2 discussed above. At low frequencies the capacitance increases with hole injection, because the latter forms a trapped charge dipole in the vicinity of the hole-injecting electrode [80]. As in the case of conductance, not including hole traps in the simulation results in the curve which is insensitive to hole injection. The resultant shape of the curve is similar to that shown in Fig. 4.46 in the presence of hole injection: namely it exhibits the transition of the capacitance from high to low values, which was observed in silicon p-n junctions with deep traps [51, 69]. As shown in Fig. 4.46 at higher frequencies the capacitance becomes insensitive to hole injection. The results presented in Figs. 4.45 and 4.46 are in good agreement with experimental data for SI GaAs [32], namely small bumps on the conductance curves, that can be seen at low frequencies and high temperatures and a drastic increase in the conductance at higher frequencies (Fig. 3 in [32]), and a transition of the capacitance from the high to low values (Fig. 4 in [32]). Although Pistoulet et at. [32] explained some of the results in terms of their potential fluctuations theory, our work shows that the principal features of their data for SI GaAs can be reproduced by solving continuity and Poisson’s equations in the frequency domain. The validity of our results becomes questionable at frequencies above the reciprocal of carrier lifetime, which is about 20 MHz in our calculations. However, the sharp increase in the conductance was shown to be dependent on the distance between the electrodes and on the traps characteristics, and it is possible to show that by changing these parameters the strongly transitional region of the conductance can be shifted to lower frequencies in which our analysis is definitely valid. Physically the sharp increase in the conductance in the MHz range occurs probably due to the fact that the SI GaAs transforms in this frequency range from a lifetime semiconductor to a relaxation semiconductor. Because of zero-field boundary conditions only a diffusion component of the total 82 current plays a role in determining the conductance. At low frequencies there is quasi-neutrality of excess free carriers in the SI GaAs: the excess holes and electrons have similar distribution in space, and, consequently, the hole and electron diffusion currents have opposite signs, decreasing the total current. With increasing frequencies the shape of the excess free holes and electrons change from being similar to a mirror image (with unequal magnitudes). Thus at higher frequencies the diffusion currents of holes and electrons sum up, increasing the total current. In conclusion, the free and trapped carrier profiles and the potential profile in SI GaAs were found to be frequency-dependent. At lower frequencies the material behaves like a l{fe:ime semiconductor, in which electrons are trying to neutralize the injected holes. At higher frequencies charge separation occurs, typical of relaxation semiconductors. It was shown that the local space charge neutrality is not preserved in both low and high frequencies. It was found that up to about 100 kHz the admittance can be represented by an equivalent circuit consisting of a frequency-dependent conductance and a more strongly frequency-dependent capacitance. At low frequencies the conductance decreases, while the capacitance increases in the presence of hole injection. At higher frequencies the conductance increases by a few orders of magnitude. This increase occurs at lower frequencies for shorter distances between the contacts. The comparison between the structures with two ohmic contacts and the structures with one ohmic and one Schottky contact reveals that their admittances differ at very low frequencies but are very similar at higher frequencies. 4.4 Applications to AC sidegating The above results indicate an increase of a few orders of magnitude in the SI GaAs conductivity in the kHz-MHz range, depending on the trap parameters and device geometry. The increase in the conductivity will be higher and will be stretched over a wider frequency range by decreasing spacings between devices. Thus, in addition to the DC sidegating effect due to hole injection or space-charge limited currents in the SI substrate, discussed in Chap. 2, a strong AC sidegating effect may exist. This effect has been overlooked, probably because for GaAs MMIC’s capacitive coupling is assumed as the only way of crosstalk, while for GaAs digital integrated circuits only DC sidegating has been investigated. However, for wide-bandwidth circuits, such as operational amplifiers this effect cannot 83 be ignored. Furthermore, switching waveforms in digital circuits will normally have higher frequency hannonics besides DC components, which may affect significantly the crosstalk between devices. In [94] we analyzed AC sidegating in GaAs MESFETs and the calculated results, shown there, while they agreed with trends in the experimental data, underestimated the magnitude of the crosstalk. These calculations were based on the parameters evaluated from DC measurements: specifically the substrate admittance was evaluated from DC measurements. However, considering the frequency dependence of the admittance of the GaAs SI substrate, presented in this chapter, it is clear that the admittance might have been a few orders of magnitude larger than its DC value, resulting in a better agreement of the calculations with the experimental results. In the next Chapter we will see applications of the results derived in this section to modeling of the output conductance of GaAs MESFETs on SI substrates. 4.5 Summary By extending to the frequency domain the analysis of transport in semi-insulating GaAs two- terminal structures, in which one terminal injects only electrons and the other may inject holes, closed form solutions were obtained for AC charge and potential distribution under conditions of low-level injection. The presence of deep traps results in frequency dependence of both the excess free and trapped carriers. At low frequencies free electrons move so as to neutralize injected holes, but at higher frequencies charge separation of free carriers through the zero local recombination, typical of relaxation semiconductors, occurs. The corresponding admittance can be represented by an equivalent circuit consisting of a frequency-dependent conductance in parallel with a frequency- dependent capacitance. At very low frequencies the conductance decreases with increasing hole injection. At higher frequencies it increases and then saturates with frequency. At low frequencies the capacitance is a strongly decreasing function of frequency. At higher frequencies the admittance depends only weakly on the hole injection ratio. Although we focus on semi-insulating GaAs, the equations presented are in a general form, which is applicable to the frequency-dependent transport in a variety of other semiconductors under conditions of low-level injection. 84 Chapter 5 Modeling frequency dependence of the output conductance of GaAs MESFETs 5.1 Introduction The output conductance of a GaAs MESFET is one of the major parameters, which determine device performance, and, consequently, its variation with frequency has attracted the attention of many researchers recently [93, 97—99]. In these papers the output admittance is modeled as a single time constant (zero-pole) function. Although this function can be tailored to fit the variation with frequency of the output admittance magnitude, the phase change calculated using this approach is greatly overestimated [93, 45], suggesting a more complicated behavior in the frequency domain. The numerical simulations of the output conductance dispersion provide more understanding of the phenomenon [6, 100], but do not produce an adequate model for circuit simulation. 5.2 Modeling The frequency dispersion of the output conductance, expressed as a drain-lag effect in the time domain [45], has been widely ascribed to the channel-substrate interface [93, 97, 6, 101]. To illustrate the channel-substrate interaction consider the cross-section of a GaAs MESFET shown in Fig. 5.47. The conductive channel is bounded by the gate and channel-substrate depletion regions. The saturation current in GaAs MESFETs, assuming a constant electron concentration ND, is given in the velocity saturation region by: I qNDZVS(A — d — h) (5.65) where q is the magnitude of the electron charge, Z is the device width, d is the thickness of the gate depletion region, h is the extension of the channel-substrate depletion region into the channel, and v is the saturation velocity. Using the abrupt depletion region approximation, we evaluate d and h at the drain edge of the gate (l = + 1, in Fig. 5.47): d = 4/2 - VDST — VG) (5.66) V qN 85 h — /2E(VBCS + VDST — VSB(ll))NA (5 67 —v qND(NA+ND) where c is the permittivity, VBSC is the Schottky gate built-in voltage, VDST and VSB are the channel and substrate voltages respectively at l, VBCS is the built-in voltage of the channel-substrate interface, VG is the gate voltage, and NA is the sum of density of shallow and deep acceptors [70]. We can write the drain conductance as: fd __ Gd = —qNDZv3 T7 + Ty (5.68) \UVDS CIVDSJ The first term in the brackets is due to the displacement of the velocity saturation point and the consequent channel widening [1021. The second term represents the modulation of the width of the channel-substrate depletion layer through the SI substrate by a drain voltage, and can be interpreted as an electrostatic drain feedback effect [1031. Although the potential profile in the channel changes GATESOURCE — i ; DRAIN 1sgg DISTANCE FROM SOURCE Figure 5.47: Schematic cross section of a MESFET and an AC potential profile across the drain-substrate-source region. LF corresponds to the profile at low frequencies, HF at high frequencies. n+ n+ Semi-insulating GaAs Substrate 86 with the drain voltage, its variation is much weaker than that in the substrate, and, therefore, we assume that the modulation of h is due to the latter only. As we shall see in the following analysis, the potential distribution across the drain-substrate-source region is frequency-dependent, as shown in Fig 5.47, and, thus, the modulation of the width of the conductive channel, and, consequently, the output conductance depend on frequency. Our analysis is restricted to drain voltages which satisfy the condition of low-level injection into the substrate. In non self-aligned transistors the typical distance between source and drain is about 3—6 m, and for such distances two-dimensional numerical analysis of n-SI-n structures predicts high-level electron injection occurring at voltages larger than 5 V [56]. Abrupt current increase in such structures has been reported previously at lower voltages, but it has been attributed to surface effects [104]. We, however, consider the SI region under the channel, which is not normally affected by the surface states, particularly in large-geometry devices. An analytic expression for the potential distribution in one-dimensional Si GaAs structures has been obtained previously by solving the time-dependent continuity equations for holes and electrons and Poisson’s equation under conditions of low-level injection, without further assumptions such as space charge neutrality and neglect of the diffusion component of the current [105]. The solution is restricted to the range of frequencies below the reciprocal of the carrier lifetime in GaAs, which is sufficient for discussing the frequency-dependent effects in GaAs MESFETs. This restriction is not necessary for obtaining analytic expressions, but greatly simplifies them. For the boundary conditions of zero field and zero hole current, the obtained DC potential profile is almost insensitive to the substrate properties, exhibiting nearly linear distribution [80]. But the AC potential profile, given by in the following expression, is frequency-dependent and is sensitive to the density and location in the energy band of the traps in the SI material [105]. - F cosh(x/)— cosh((l— x)/i)+ cosh(1/i)V3b(x,w)=A{MIx— . +/sinh(1/i) P[(1 + a)M — 1 — fi] cosh (x) — cosh ((1 — x)) + cosh (l) — (5.69) An(Pe + b) v’sinh (l/) with ii = [Pe(1 + a) + (1 + 3)]/(1 + Fe), 87 = An(Pe+b)/(1+Pe), M = (1+/3—Ab)/(1+a—A), = TT/[T(1 +jWTT)], /3 = TT/[Tfl(1+jWTT)], where 1/TT = Cr4 fle + en + CpPe + e, i/Tn = CnNTfl1/(fle+fll), 1/Tn = CPNTfle/(fle + ii1), w is the angular frequency, NT is the density of a deep level, e, e are the emission rates of a deep level for electrons and holes, c, c, are the capture probabilities of a deep level for electrons and holes, e, pe are the equilibrium electron and hole concentrations, Fe = Pe / e, n1 is the electron density if the Fermi level were at the energy level of the deep level, 1 is the drain-source spacing. In (5.69) the distance x is normalized to /EkT/q2(ne + pa), and the parameter A can be determined by the drain voltage. Substituting (5.69) into (5.68) and separating the obtained result into DC and AC parts yields the AC component of the drain admittance: Zv [17Sb(11, w) — VSb(ll,0)] / qCNN gd = VSb(l) \/ 2(NA + ND)(VBCS + VDST — VSB(l1)) (5.70) The drain conductance is given by the real part of (5.70). The parameter VDST will depend on the device geometry: in non self-aligned devices biased in saturation most of the drain voltage is dropped across the gate-drain region, and, therefore, VDST is only slightly higher than the saturation voltage, but in self-aligned transistors this will not be the case [1061. Therefore, in this work VDST is used as a fitting parameter. The DC component of the output conductance can be evaluated from DC I-V characteristics, and the total output conductance is thus obtained by summing up the AC and DC components. The resulting equivalent circuit of a MESFET is shown in Fig. 5.48. In Fig. 5.48 R0 is: the DC output conductance, g is the transconductance, g is defined in eq. (5.70), Rb and Csub represent the substrate admittance, which is due to the conduction between source and drain through the SI substrate [105]. Note that the above equivalent circuit includes frequency-dependent 88 GATE DRAIN Csub SOURCE Figure 5.48: Small-signal equivalent circuit of a GaAs MESFET at low frequencies. elements gd’ Rsub and Csub, and in that it is different from the previously proposed circuits, for example, the ones suggested by Scheinberg et a!. [107 1 and by Lee and Forbes [98). The output admittance is given by: Y0 = + +JtVCsub +gd (5.71) In comparison to other models our model has a certain degree of predictability, since its inputs are parameters of the traps that are present in the SI substrate and device geometry. 5.3 Comparison with experimental and numerical data The analysis of the AC potential distribution across the source-substrate-drain structure under conditions of low-level injection is valid for a wide range of drain voltages, and, therefore, it can be used for investigation of drain-lag effects and AC I-V characteristics. This is confirmed by the fact that the drain current overshoot and the drain conductance dispersion were observed at drain voltages as low as 1 V [101, 991, indicating that these phenomena are not originated, but perhaps enhanced, by high-level injection into the SI substrate. To test the validity of the model, we examine first if it predicts the major trends in device behavior. According to the model the frequency-dependent component of the drain conductance increases with the acceptor density in the substrate in agreement with numerical simulations [6]. However, controversial results have been reported regarding the effect of a buried p layer beneath the channel: 89 while it is established that the buried layer improves DC characteristics of GaAs MESFETs, there is no consensus whether it reduces the AC/transient-dependent effects [108, 1011. Our model predicts that a p layer slightly beneath the channel will increase the frequency dependence of the drain conductance through the increase of the shallow acceptor density, while it will not affect the frequency-dependent potential distribution in the substrate, altogether making the frequency dispersion of the output conductance even worse. But a deep implant, which provides in addition to the depletion layer a conductive layer beneath the channel, will eliminate the frequency dependence. This is in agreement with the reported experimental data: when a deep implant was used no drain current transients were observed [109, 1081, but when a shallow implant was used in order to keep the p-layer completely depleted, the drain current transients increased [101]. To examine AC I-V characteristics we replace the DC voltage VSB (li) in (5.67) by its AC value evaluated from (5.69). The resultant eq. (5.65) yields a higher current, since 17sb (li) increases with frequencies in the low-frequency range. This is in agreement with the measured data, which indicate larger saturation currents at kHz range [98, 99]. According to the AC potential profile shown in Fig. 5.47, it is possible to devise structures, for which the frequency-dependent effects are reduced. Minimum effect will occur when the drain side of the gate is about the middle of the drain-source distance, that can be expressed as: (& + Ig)/lcig 1. Maximum effect will occur when the drain side of the gate is about 1/4 from the drain, that can be expressed as: (l + ig)/ldg 3. The predictions of this simple analysis are in agreement with experimental data of drain current overshoots as a function of gate-drain and gate-source spacings [101]. The results of this analysis for MESFETs with and without p-type buried layer are visualized in Fig. 5.49. Direct comparison between our model and measured data requires knowledge of substrate properties. The analysis is further complicated by the fact, that in the substrate region beneath the channel, in addition to the presence of the traps, originated in as-grown SI substrates, deep levels may be induced by processing [110]. Our model allows incorporation of multiple non-interacting traps in the analytic expression for the AC drain conductance as described in [80, 105]. We have compared our results with the numerical and measured data extracted from [111, 100]. The numerical analysis suggested that in addition to EL2, there is a shallower electron trap, which plays a role in 90 BAD GOOD S G D n fl+ jfl+ Lp layer SI SUBSTRATE S G D S G D n n+ p layer SI SUBSTRATE S G D Figure 5.49: The impact of the device structure on the frequency dependence of the output admittance. The first row shows MESFETs with a p-type buried layer. A deep p layer reduces the frequency dependence, while a shallow p layer may increase it. The second row shows the effect of the gate location on the frequency-dependent output admittance: placing gate closer to the source enhances the frequency dependence, while placing it closer to the source may reduce the effect. the frequency-dependent effects [1001, and, consequently, we used similar parameters to those in the numerical simulation. Our results, calculated by (5.70), are in very good agreement with the numerical and measured data, as shown in Fig. 5.50. Not shown in Fig. 5.50, but noteworthy, is the fact that the phase variation over the frequency range 1 — io Hz , calculated by (5.70), is less than 2°. We have examined the temperature effects by considering temperature-dependent emission rates for EL2 [1121: e = 2.83 x lO7T2exp(—0.814/kT) s’ and e = 1O3e, and the temperature nil ___ I÷i SI SUBSTRATE n n+ n+ SI SUBSTRATE 91 C c-) C dependence of the carrier concentration and the EL2 energy level. Fig. 5.51 shows drain conductance versus frequency at two different temperatures, calculated by (5.70) assuming only one deep level (EL2) in the substrate, together with the measured data extracted from [99]. Our results reflect the trend in device behavior, which is the shift of the frequency-dependent region of the drain conductance to higher frequencies at higher temperatures. Experimental results indicate a smoother increase in the drain conductance, suggesting presence of additional traps in the substrate. 6.5 6 5.5 5 4.5 4 3.5 3 2.5 2 100 FREQUENCY [Hzl Figure 5.50: Drain conductance vs. frequency. Results of the present model (solid line) are superimposed on numerical results (dashed line) [7], and experimental data (circles) [20]. Parameters used: T = 300 K, ND = lO’7cm3,NA = 6 x 105cm3,VDS 2.5V, VDST = l.45V, = ldg 1pm, 1 = 1.2pm, 7 x 1Ocm,p 105cm3,for trap at 0.69 eV;N1 = 5 x 106cm3O1 = 2 x 10’4cm2 0p1 = 2 x 108cm2for trap at 0.5 eV;N2 = 5 x lO’5cm3,0n2 = 5 X 1O’cm2,,p2 = 5 10’7cm2. 101 102 10 10 iO 92 EE L) z 0 U 0 106 FREQUENCY [Hz] Figure 5.51: Drain conductance vs. frequency at 325 K and 375 K. Results of the present model (solid line) are superimposed on experimental data (circles and asterisks) after Canfield et. a] [41. Parameters used: NEL2 = 5 x 106cm3,NA = 5 X lO’5cm3,1 Idg = 1 = ljITfl, VDs 3V, VDsT 1.6V. In conclusion, physically based model of the frequency-dependent drain conductance has been developed. It allows an examination of the impact of device geometry and substrate properties, particularly the presence of multiple traps, on GaAs MESFET characteristics. The model reflects major trends in the output admittance, namely: low-frequency dependence, temperature dependence, negligible phase variation, dependence on drain voltages. Being analytical, it should be useful for circuit simulations. 5.4 Summary The small-signal output conductance of GaAs MESFETs on SI substrates is known to exhibit 2.5 100 101 102 10 10 105 93 frequency dependence. So far this phenomenon has been modeled using equivalent circuits and numerical techniques. In contrast, we propose an analytical physically-based model. The model accounts for alteration of the thickness of the conductive channel through the channel-substrate junction modulation by the drain voltage. Because of the presence of deep levels the AC potential distribution across the SI material between drain and source will be frequency dependent, and, consequently, will result in a different AC voltage drop across the channel-substrate interface at different frequencies. This will result in a change of the output conductance with frequency. A closed fonn for the AC potential distribution across the SI material was obtained by solving the continuity equations for holes and electrons plus Poisson’s equation under conditions of low-level injection and low frequencies without some commonly used assumptions, such as local space-charge neutrality, neglect of recombination, and diffusion or drift component of the current. The solution for the AC potential distribution is affected by the density and location of deep levels in the SI substrate, and can be easily extended to the general case of non-interacting multiple traps. Thus, the model provides a tool for investigating the effect of trap parameters on the frequency characteristics. It reproduces experimentally observed and numerically simulated results for the output conductance. Being analytical, the expression for the frequency-dependent output conductance is suitable for incorporation in circuit simulators. 94 Chapter 6 Conclusions The majority of text books on semiconductor devices are based on the research spanning the last four decades on silicon. Many concepts developed for and commonly used in the silicon device theory, such as space charge neutrality, neglect of recombination in short structures etc. are entirely misleading when dealing with GaAs devices on SI substrates. This is due to the fact that trap densities in SI GaAs are much higher than in Si, while carrier lifetimes are much shorter. Examining eqn. (3.34) leads to the conclusion, that under non-equilibrium conditions space charge neutrality in SI GaAs is rather an exception than a rule, and occurs only when the concentrations of excess trapped holes and electrons are equal. Van Roosbroeck , who introduced the concept of ambipolar transport to the semiconductor theory [113] , based on local quasi-neutrality of the excess free carriers, was the one (with Casey), who classified some of the materials as relaxation semiconductors, in which separation of the excess free electrons and holes is established through zero local recombination [95]. In addition, ambipolar approach omits from the analysis the Poisson’s equation [1141. This omission is not justified for SI GaAs, in which the excess trapped carrier densities are much higher than the excess free carrier densities. The ambipolar approach is commonly used in analysis of silicon devices [114]. In comparison to silicon SI GaAs has much higher resistivity and much shorter lifetimes. The clues for different treatment of such materials were discussed by McKelvey [1151. But since at the time these materials were not a part of the mainstream research effort, many of the conclusions regarding them have been overlooked. One of the main conclusions of my work is that many concepts developed for Si should be reexamined when talking about the GaAs technology. The borrowing of concepts from Si technology may lead to severe errors in understanding GaAs devices on SI substrates. In Chapter 1 the use of MESFET as a tool for investigating of the interaction with the SI substrate of more complicated devices was suggested. It is interesting to note that the gate, which was identified as one of the main players in the sidegating effect in MESFETs [43], was also found to play a major role in the sidegating effect in HEMTs [116]. Sidegating remains the major obstacle 95 to fabrication of high density GaAs integrated circuits [5]. This work contributes to understanding and modeling of this problem by: 1. Identification of hole injection from the gate as one of the possible sources of sidegating. The hole injection from the portion of the gate on a SI substrate was shown numerically by Goto et at. [83] and experimentally by Liu et at. [58] to play an important role in sidegating. Our results show the possibility of hole injection from the gate on a doped channel and also provide a new interpretation of the results in Refs. [83] and [58], namely, appearance of hysteresis as a result of a strong hole injection into the SI substrate and the effect of weak hole injection on sidegating. 2. Identification of the role of recombination processes and, consequently, recombination centers (that are different from EL2) in sidegating. 3. Application of the analysis of low-level injection reported first by Manifacier and Henisch [41] to sidegating problem. Low-level analysis has not been applied before to sidegating, since it is usually assumed that “nothing happens” under these conditions because the carrier transport is dominated by ohmic conduction. This work shows that even though the I-V characteristics may be nearly ohmic, many physical processes may occur under conditions of low-level injection resulting in such effects as non-linear voltage distribution across a SI substrate. The processes leading to such behavior have been discussed in this work. The resultant non-linear potential profiles were used to explain sidegating at low sidegate voltages and long range sidegating. 4. Providing close form expressions for the potential distribution across a SI GaAs substrate and the output admittance of GaAs MESFETs on SI substrates, which should be useful in circuit simulations. 5. Extension of the low-level injection analysis to the frequency-domain. 6. Application of the above analysis to modeling the frequency dependence of the output impedance. 7. Investigation of sidegating in the frequency domain (AC sidegating). It was shown that a strong sidegating effect may exist due to inherent properties of SI GaAs. While it was shown that hole injection plays an important role in the DC sidegating effect, the sidegating effect in the kllz MHz range does not depend on hole injection and does not require specific biasing conditions [105]. This effect will have most impact on wide-band circuits used in analog and mixed analog- 96 digital systems. The analysis of sidegating in the frequency domain can also be used as a tool for separating various processes occurring at the same time in sidegating effect, since they are expected to have different frequency responses. The results presented in Chapters 3—5 indicate that device characteristics depend strongly on the substrate properties which, in turn, are determined by trap parameters. Under non-equilibrium conditions even shallow traps may affect the device characteristics. Thus different combinations of multiple trap parameters will result in different device behavior [117]. Even if the properties of the as-grown substrate are completely controlled, additional traps may be induced by processing steps. Despite the difficulties in obtaining reproducible performance for devices on SI substrates, the continuation of this work is necessary because there will be always demand for GaAs technology, particularly in optoelectronic circuits [118]. The problems may not be solved, but understood, and, consequently, predicted (=modeled) and controlled. It is possible that innovative circuit techniques will contribute to this. Future work may include: 1. Measurements of and modeling the hole injection from the gate of a GaAs MESFET. This means more studies towards understanding of the nature of Schottky contacts on GaAs, particularly the effect of a Schottky contact area on hole injection. 2. Incorporation of the results of Chapter 4 in investigating crosstalk in GaAs integrated circuits. 3. In Chapter 1 sidegating was presented as a three-dimensional effect. Therefore, the extension of the existing one-dimensional analysis to two and three dimensions by numerical techniques should provide more insight into sidegating. 4. Extension of the low-level injection analysis into the time domain. 5. Extracting the trap parameters from the AC measurements of the conductivity of a SI GaAs substrate. 6. Identification and characterization of recombination centers, which is according to my work as important as an investigation of EL2. 7. Sidegating is known to be a temperature-dependent effect [119], and, therefore, the results presented here should be analyzed as a function of temperature. 97 8. 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(B.73) The solution is given by: v(x) = (jwc3 +y3)evsg/jwcj0+ Ee[(/2)x] + (B.74) where E and F are constants to be determined by the boundary conditions. The current in the channel is given by: i(x) = —(1/rh0e)(Ov/Ox). 107

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