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UBC Theses and Dissertations

Implementation and evaluation of various stop and wait type II hybrid ARQ schemes for mobile radio Agostino, Remo L. 1993

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IMPLEMENTATION AND EVALUATION OF VARIOUS STOP AND WAIT TYPE II HYBRID ARQ SCHEMES FOR MOBILE RADIO by REMO L. AGOSTINO B. A. Sc., University of British Columbia, 1990.  A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE  in THE FACULTY OF GRADUATE STUDIES Department of Electrical Engineering  We accept this thesis as conforming to the required standard  THE UNIVERSITY OF BRITISH COLUMBIA September 1993 © Remo L. Agostino, 1993  In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission.  (Signature)  Department of  ...-/et^Cze  The University of British Columbia Vancouver, Canada  Date  DE-6 (2/88)  ABSTRACT This thesis investigates the design and implementation issues involved in the development of various Stop-and-Wait (SW) Type II Hybrid Automatic Repeat reQuest (ARQ) strategies. The modulation scheme utilized is the North American digital cellular standard known as 7r/4—shift DQPSK. The general Complementary Punctured Convolutional (CPC) SW Type II ARQ scheme is presented and numerically analyzed in both an AWGN channel and a combined AWGN and Rayleigh fading channel. The three variations of the general scheme implemented are: Rate 3/4 CPC SW Type II ARQ, Rate 3/4 CPC SW Type II ARQ with Code Combining, and an Adaptive CPC SW Type II ARQ scheme. The prototypes are implemented with two Spectrum TMS320C30 Digital Signal Processing (DSP) cards and a host IBM PC. The experimental data for the prototypes were verified and were in good agreement with the numerical results. This validated the prototypes' correct and proper operation along with the DSP software modules used by the prototypes. It is shown that the upgrade of the CPC SW Type IT ARQ scheme to a Code Combining and an Adaptive scheme requires small software modifications. It is the versatility and flexibility of the DSP cards which allow these upgrades to be easily accomplished and extremely cost effective. The Code Combining upgrade increased the throughput performance of the general rate 3/4 scheme at low SNR levels. The Adaptive scheme resulted in an increase at both low and high SNR levels with a slight degradation at medium SNR levels with respect to the throughput curve of the general rate 3/4 scheme.  Contents ABSTRACT ^  ii  List of Tables ^  vi  List of Figures ^  vii  Acknowledgments ^  ix  Introduction ^  1  ARQ Schemes ^  1  1.1.1  Stop-and-Wait ARQ ^  1  1.1.2  Type I Hybrid ARQ ^  3  1.1.3  Type II Hybrid ARQ ^  4  1.2  Thesis Goals ^  4  1.3  Thesis Organization ^  6  Chapter 1 1.1  Chapter 2  7/4—Shift DQPSK Modulation Scheme ^ 8  2.1  Introduction ^  8  2.2  Transmitter Model ^  8  2.3  DSP Implementation of the Phase Shift Encoder and Baseband Generator ^  11  2.4  RF Modulator/Demodulator and Channel ^ 14  2.5  DSP Implemented Baseband Differential Detector ^ 16  2.6  Theoretical Analysis and Prototype Performance ^ 18  2.7  Conclusions ^ 111  21  ^  Chapter 3^Application of Complementary Punctured Convolutional Codes to a SW Type II ARQ Scheme ^ 22 3.1^Introduction ^  22  3.2^Review of Complementary Punctured Convolutional Codes (CPC) ^ 3.2.1^CPC Codes ^  22 23  3.3^Generalized CPC SW Type II Hybrid ARQ Algorithm . . ^ 24 3.4  DSP Implementation of a CPC SW Type II ARQ Scheme . 25  3.4.1  Frame Structure ^  28  3.4.2  Frame Synchronization ^  29  3.4.3  Encoder/Transmitter DSP Card ^  33  3.4.4  Receiver/Decoder DSP Card ^  36  3.4.4.1  Viterbi Decoder ^  39  3.4.4.1.1  Numerical Analysis ^  41  3.4.4.1.2  Computer Simulation ^  42  3.4.4.1.3  Viterbi Decoder Performance ^  42  Prototype Performance ^  43  Throughput Analysis ^  44  Numerical Results ^  45  3.5.2  Experimental Throughput ^  46  3.5.3  Rayleigh Fading Channel ^  48  3.5 3.5.1 3.5.1.1  iv  ^ ^  3.6^CPC SW Type ll ARQ Scheme with Code Combining . . 50 3.7^Conclusions ^  53  Chapter 4^An Adaptive SW Type ll ARQ Scheme ^ 54 4.1^Introduction ^  54  4.2^The Adaptive Coding Rate Algorithm ^ 54 4.3^DSP Implementation of the Adaptive Scheme ^ 56 4.4^Performance Evaluation ^  57  4.5^SW ARQ Scheme Comparisons ^  63  4.6^Conclusions ^  65  Chapter 5^Conclusions and Future Research ^ 66 5.1^Conclusions ^  66  5.2^Future Research ^  69  5.2.1^Symbol Synchronization ^  69  5.2.2^Selective Repeat Upgrade ^  69  5.2.3^Adaptive Header ^  69  5.2.4^FEC Schemes ^  70  Bibliography ^  71  Appendix A^Software Listings ^  74  List of Tables Table 1^Phase Shift as a function of Information Symbol. ^ 11 Table 2^7r14 Shift DQPSK State Encoder Look Up Table. ^ 13 Table 3^Distance Spectrum of Code with Rate 1/2 ^ 42 Table 4^Distance Spectra of Rate 3/4 Punctured Convolutional Code of Memory m=4. ^  vi  45  ^  List of Figures Figure 1.1^Stop-and-Wait ARQ Scheme ^  2  Figure 1.2^Typical Type I Hybrid ARQ System ^ 3 Figure 2.1^Block Diagram of the 7r/4 shift DQPSK Transmitter. . . . ^ 9 Figure 2.2^State-space diagram of the 7r/4 shift DQPSK modulated carrier at sampling points  10  Figure 2.3^Flow chart representing baseband transmission algorithm ^  12  Figure 2.4^Modulator, Demodulator, and Channel simulator. ^ 15 Figure 2.5^DSP Baseband Differential Detector Block Diagram ^. ^ 16 Figure 2.6^BER Performance in AWGN. ^  19  Figure 2.7^BER Performance of 7r/4—shift DQPSK in a Rayleigh Fading Channel for Various BDT. ^ 21 Figure 3.1^Block Diagram of Prototype SW Type ll ARQ Scheme. . ^ 26 Figure 3.2^Detailed Structure of Frame. ^  28  Figure 3.3^Correlation Sidelobes of Flag used in Prototype ^ 30 Figure 3.4^(a) and (b) Effects of Changing Threshold value used for Flag Correlation ^  32  Figure 3.5^Frame Encoding and Construction Algorithm of DSP Transmitter Card. ^  35  Figure 3.6^Frame Decoding Algorithm of DSP Receiver Card.^. ^ 38 Figure 3.7^Choosing a Path Survivor ^  40  Figure 3.8^Rate 1/2 Soft Decision Viterbi Decoder Performance. . . ^ 43 vii  Figure 3.9^Numerical and Experimental Throughputs ^ 46 Figure 3.10^Throughput of Prototype in a Rayleigh Fading Channel. ^ 49 Figure 3.11^Throughput of CPC SW Type ll ARQ Scheme with and without Code Combining ^  51  Figure 3.12^Histograms for Rate 3/4 CPC SW Type II ARQ with and without Code Combining ^  52  Figure 4.1^Threshold Regions Defining Coding Rates. ^ 55 Figure 4.2^Experimental Throughputs of rate 1/2, 3/4, and 1 ^ 57 Figure 4.3^Adaptive CPC SW Type ll ARQ Throughput. ^ 58 Figure 4.4^Affect of varying N for the Adaptive Scheme's Throughput ^  59  Figure 4.5^Adaptive CPC SW Type ll ARQ in Rayleigh Channel.. . ^ 60 Figure 4.6^Adaptive CPC SW Type II ARQ in a Rayleigh Channel for Various B D T Products ^  62  Figure 4.7^Effect of varying N for the Adaptive Scheme in a Fading channel. ^  viii  63  Acknowledgments I would like to thank my mother and aunt, Maddalena and Maria Taddei, for their continuous moral support and constant encouragement throughout my academic career. I would also like to issue a special thanks to my uncle, Tony Bolognese, for having played a major role in my decision to enter the exciting field of communications. I am enormously grateful to my supervisors, Dr. Samir Kallel and Dr. V. C. M. Leung, for their constant guidance, moral support, and invaluable experience which allowed me to complete this thesis. I would also like to thank my fellow students and especially Dimitrios P. Bouras and William Cheung for their insightful and stimulating discussions. Finally, I would like to acknowledge the assistance provided by the B.C. Science Council.  ix  Chapter 1  Chapter 1 Introduction Section 1.1 ARO Schemes The problem of providing an efficient reliable data communications link in a land mobile radio channel is of great practical importance. Automatic Repeat reQuest (ARQ) protocols or similar custom tailored Radio Data Link Protocols are commonly used to provide a virtually error free data link for the radio channel. The ARQ protocol ensures a consistent data quality under varying channel conditions. The functions the ARQ protocol must accomplish can be divided into two different classes: low level functions involved with encoding and decoding of protocol information in the data packets and high level functions concerned with the request retransmission algorithm to support frame transmission services. The message itself is contained in the data packet of the frame, whereas the destination address and other pertinent information is contained in the header which precedes the data packet. A code with good error detecting capability is used to encode the header and data packet separately. Typically, a Cyclic Redundancy Code (CRC) is used [1]. The header is independently encoded to allow all mobile radio users to decode it in order to distinguish if the frame is addressed to them and decide whether to process the data packet.  1.1.1 Stop-and-Wait A RQ In a Stop-and-Wait ARQ (SW ARQ) scheme, the transmitter sends a single frame and stops to await the reply of the receiver. No other frame can be sent until the receiver's reply arrives at the transmitter. Three possible events may arise once a transmission has taken place. The receiver may send an acknowledgment (ACK) to indicate that the Section 1  Chapter 1  frame was received error free; or a negative acknowledgment (NACK) if it was received in error; or no reply if the frame was so corrupted by noise as not to be received. To account for this last event, the transmitter is equipped with a timer. Once a frame has been sent, the transmitter awaits for a recognizable reply (ACK or NACK). If no such reply is received during the time-out period, the frame is retransmitted. Therefore, any reply other than an ACK will result in the transmitter retransmitting the same frame again. Figure 1.1 illustrates the SW ARQ scheme. It is inefficient to utilize a SW ARQ protocol in a single frequency system because the time required for the transmitter to await the receiver's reply is wasted air time. The typical mobile radio system uses a number of frequencies to communicate between the base stations and the mobile users. This configuration allows the SW ARQ protocol to make efficient use of its air time. For example, after the base transmits a message to mobile A, it can send another message to any other mobile while awaiting the reply of mobile A on the return channel. In this respect the SW ARQ protocol can be well suited for mobile radio systems.  Idle time^  Retrans ission  Transmitter  Receiver  Figure 1.1 Stop-and-Wait ARQ Scheme  Section 1  ^  2  Chapter 1  1.1.2 Type I Hybrid ARQ A hybrid ARQ system utilizes both Forward Error Correction (1-EC) coding and error detection coding (incorporated in the ARQ scheme). The FEC code is used to reduce the number of retransmissions. In a Type I Hybrid ARQ scheme the message and its error detecting parity bits (typically CRC), are further encoded with a FEC code. At the receiver, the FEC parity bits are used to correct channel errors. The FEC decoder (typically a Viterbi Decoder) outputs an estimate of the received message and its error detecting parity bits. This estimate is tested by the error detection decoder (CRC checker) to determine if the message is error free. Figure 1.2 depicts a Type I Hybrid ARQ communication system.  Message  CRC ENCODER  •  CONVOLUTIONAL ENCODER  NOISE  ACK NACK •^  CRC CHECKER  VITERBI DECODER  Figure 1.2 Typical Type I Hybrid ARQ System  The efficiency of a Type I ARQ system in comparison to a plain ARQ system depends on the level of noise corrupting the channel. If the Signal-to-Noise Ratio (SNR) is high, the Type I ARQ scheme does not result in any improvement. The FEC parity bits are wasted, as a result of the signal strength being strong enough to deliver error free messages. On the other hand, the Type I system does show an increase in efficiency Section 1^  3  Chapter 1  at low SNR levels, and since the signal strength is so poor, error free reception is very unlikely and the FEC parity bits are utilized to correct channel errors.  1.1.3 Type II Hybrid ARQ In a Type II ARQ scheme, the FEC parity bits are only sent if the received message contains errors. The transmitter would alternate between sending the message with its error detection parity bits on one transmission, and the FEC parity bits on the next. Note that the FEC parity bits are only sent if the received message contains errors. With this scheme, any error free reception of the message with its error detection parity bits delivers the message. If the FEC parity bits are invertible, any error free reception of the FEC parity bits also delivers the message. Finally, if both the message with its error detection parity bits and the FEC parity bits are in error, combining these two frames for error correction may successfully deliver the message. The Type II system offers the benefit of performing as a plain ARQ scheme at high SNR and performing as a Type I system at low SNR.  Section 1.2 Thesis Goals The disadvantage of Type I and Type II hybrid ARQ schemes is the failure to provide a useful throughput at high channel error rates. Application of code combining to hybrid ARQ schemes to achieve a useful throughput has been investigated [2, 3]. Code combining involves taking frames received in error and optimally combining them with their repeated copies. Therefore, the receiver would process a combination of all received sequences for that frame, rather than only the two most recently received ones as in the conventional Type II system. Section 1^  4  Chapter 1  An adaptive hybrid ARQ system utilizing code combining would be optimal. Adaptive refers to the FEC coding scheme being able to adjust to the channel conditions and data protection needs. Typically, a fixed code with a certain error rate and correction capability matched to the protection requirement of the data and the worst channel conditions is used. Unfortunately, different data (voice, FAX, computer data files, all using the same channel) have different error protection needs and what may be appropriate for one type may be inappropriate for another. Another problem, is the mobile radio channel conditions are constantly changing due to its multipath and time varying characteristics. Therefore, an adaptive code combining hybrid ARQ scheme would generally yield a higher throughput than a non-adaptive scheme in a radio channel [4]. Motivated by the above, this thesis investigates the design, implementation issues, and performance evaluation of various adaptive and non-adaptive FEC coding schemes of a Type II SW ARQ system. The research contributions can be summarized as follows: 1. The Software design, implementation, and test of a Digital Signal Processing (DSP) Module Library for the Spectrum TMS32C30 DSP card housed in an IBM PC platform. The library consists of the following modules: •  CRC Encoder/Decoder  •  Rate 1/2 Convolutional Encoder  •  Puncturing Module  •  Rate 1/2 Soft Decision Viterbi Decoder  •  Block Interleaver  •  Soft Data Deinterleaver  •  Queueing Module  Section 2^  5  Chapter 1  .  71/4—shift DQPSK Baseband Transmitter/Receiver  2. The Software implementation and evaluation of a Complementary Punctured Convolutional (CPC) coding scheme for the SW Type II ARQ system with and without code combining utilizing the DSP library in an AWGN channel and a combined AWGN and Rayleigh Fading channel. 3. Software upgrade and performance evaluation of an Adaptive CPC SW Type II ARQ scheme utilizing the DSP library in an AWGN channel and a combined AWGN and Rayleigh fading channel.  Section 1.3 Thesis Organization The thesis consists of five chapters and one appendix. It is organized as follows: •  Chapter 2 discusses the 7r/4—shift DQPSK modulation system implemented and its theoretical and practical performance.  •  Chapter 3 explains the generalized Complementary Punctured Convolutional (CPC) coding scheme for a SW Type II ARQ protocol with and without code combining. It also discusses in detail the DSP prototype CPC SW Type II ARQ scheme implemented. Finally, the prototype's performance is analyzed and evaluated.  •  Chapter 4 presents the Adaptive CPC SW Type II ARQ scheme implemented and its performance evaluation. This chapter will also compare the three ARQ schemes implemented and discuss their performances.  •  The thesis' conclusions and suggestions for future work are cited in Chapter 5.  •  Appendix A contains the software listings for the DSP Module Library, the Adaptive SW Type II ARQ Protocol, the Transmitter DSP card, and the Receiver DSP card.  Section 2^  6  Chapter 1  The CPC scheme's software is a subset of the Adaptive scheme and is therefore not listed.  Section 3^  7  Chapter 2  Chapter 2 7114-Shift DQPSK Modulation Scheme  Section 2.1 Introduction The 7r/4 shift Differential Quadrature Phase Shift Keying (DQPSK) modulation scheme has become the modulation standard for the North American and Japanese digital cellular communications system [5]. This modulation scheme is used in the implementation of the SW Type II ARQ scheme for mobile radio communications in order to get practical results which are of interest to the cellular industry. The organization of this chapter is as follows. Section 2 will review the 7r/4 shift DQPSK modulation technique. Sections 3 to 5 will describe the DSP software and the RF hardware required to construct the system. A performance comparison between the theoretical and implemented modulation scheme is presented in Section 6.  Section 2.2 Transmitter Model Figure 2.1 illustrates the transmitter model of the 7/4 shift DQPSK system. The Phase Shift Encoder and Baseband Generator Block produce the unfiltered rectangular pulse waveforms which are denoted as u(t) and v(t) in the Inphase (I) and Quadrature (Q) channels respectively. The waveforms u(t) and v(t) are Nyquist filtered and passed to the RF modulator which mixes the I and Q components to form the RF modulated signal.  8  Chapter 2  Equations 2.1 and 2.2 represent the RF modulated signal. si(t) =  Sz (t)  \/271E, cos (wct 2;) (2.1)  2E^7F . 7F i}^i= 0, 1, • • • , 7.^(2.2) wct sin — { cos wct cos —z — 4^4  In Equation 2.2, E repesents the energy per symbol, T, is the symbol duration, and tv, is the carrier frequency. Figure 2.2 is the state-space signal diagram which illustrates the possible 8 modulated carrier signals at their sampling instants. The state-space diagram shows that the transmitted signals are chosen from two signal groups, the circles (even numbered points {0, 2, 4, 6}) and the crosses (odd numbered points {1, 3, 5, 7}). If the current signal is at one of the four phase states designated by a circle, it shifts to one of the four phase states designated by a cross at the next symbol transition and vice versa. The current signal is not allowed to shift to a fellow member of its phase state at the next symbol transition (i.e., circle to circle or cross to cross). As a result of this constraint, the differential phase shift between two consecutive symbols can only be k7r/4, where Section 2^  9  Chapter 2  k = +1 or ±3. Consecutive phase shifts of ±7r/2 and 7r are inhibited. The connections in  the state-space diagram indicate the possible phase transitions.  u( i)  Figure 2.2 State-space diagram of the r/4 shift DQPSK modulated carrier at sampling points [5].  The differential phase shift encoding operation can be mathematically represented by Equations 2.3, 2.4(a), 2.4(b), and Table 1 [6]. s(t)  =  2E Ts  { uk cos wt — vk sin wt}  sin Ok^  (2.4a)  sin Ok vk_i cos Ok•^  (2.4b)  uk = uk_i cos Ok — vk_i  vk^uk_i  (2.3)  In Equations 2.4(a) and 2.4(b), uk and vk are the signal levels of the pulse amplitudes of  Section 2^  10  ^  Chapter 2  Information Symbol  ek  11  7r/4  01  37r/4  00  -  10  37r/4  -7r/4  Table 1 Phase Shift as a function of Information Symbol.  u(t) and v(t) for a period equal to the symbol duration. The signal levels uk and vk are determined from the previous signal levels, uk_j and vic_i and the phase shift,  k  resulting  from the current information symbol. The relationship between the phase shift and the current information symbol is given in Table 1. From Equations 2.4(a) and 2.4(b), it can be seen that the amplitudes of u(t) and v(t) can take the values of 0 +'`L 2 ' or ±1. For example, assume the current signal is so(t) (i.e., Bo = 0, uo = 1, and vo = 0 during  t r.fs). At time t = Ts, the information symbol 11 is sent. Therefore, 9]=7/4 and from ,^,ting signal si(t). Equations 2.4(a) and 2.4(b), tti=^and^deno From the state-space diagram and the mathematical model it follows that the information symbol is contained in the phase difference between two consecutive sampling instants. The receiver only requires the phase difference between two consecutive sampling intervals in order to retrieve the transmitted information symbol. As a result, the receiver does not need to phase synchronize with the transmitter.  Section 2.3 DSP Implementation of the Phase Shift Encoder and Baseband Generator The transmitter and receiver is implemented utilizing the Texas Instruments TMS320C30 DSP chip. The DSP platform consists of a Spectrum TMS320C30 card and software development tools for an IBM PC. The TMS320C30 DSP cards were choSection 3^  11  Chapter 2  sen due to their availability and excellent software support. A software based DSP design is more versatile, flexible, and modular than an all hardware design. The DSP system allows the user to make changes and updates to their software algorithms in a fraction of the time required for a hardware update. The flowchart shown in Figure 2.3 describes the baseband transmission algorithm.  The algorithm is interrupt driven by one of the two timers that the TMS320C30 chip features. The timer is set to 6.6 its, which is the upper limit available on the Spectrum card Section 3^  12  Chapter 2  housing the TMS320C30. The timer value has a direct result on the rate of transmission. The smaller the timer value, the higher the transmission rate. The baseband transmission routine is interrupt driven to allow the DSP chip to encode and construct other frames for transmission while the current frame is being transmitted. Therefore, even though a SW ARQ scheme is being used, the scheme may be upgraded to a Selective Repeat (SR) ARQ with little or no change to the transmission algorithm. The Baud rate, which is the number of symbols transmitted per second, is determined by the number of times the routine is executed per symbol or dibit. The variable symbol_duration_count keeps track of this value, which is compared to a user set limit.  In the algorithm shown in Figure 2.3, the limit is set to a value of 8 and gives rise to a baud rate of 18.939kHz according to equation 2.5. Baud rate = {(symbol_duration_count Limit)* 6.6 us}l . (2.5) Every time the interrupt routine is executed, the symbol_duration_count is checked. If a new symbol or dibit is required, it is fetched from memory and the amplitudes uk and vk, of the baseband signals u(t) and v(t), are chosen from the 7r/4 shift DQPSK encoder  look up table displayed as Table 2. Table 2 shows all possible state transitions given the  Current Symbol  I^ 1 2 0  00 01 10  5 3  6 4  7  0  11  1  2  Previous Signal s1(t)  3  7  0  5 1 3  6 2 4  4 1 7  3 5  5 2 0 4 6  6 3 1 5 7  7  4 2 6 0  Table 2 7r/4 Shift DQPSK State Encoder Look Up Table.  previous signal s1(t) and the current symbol or dibit to be transmitted. This table is a direct Section 3  ^  13  Chapter 2  result of equations 2.4(a), 2.4(b), and Table 1. Once the values for uk and vk are chosen, they are written to the Digital to Analog registers, which in turn outputs an analog voltage on the I and Q channels. Note the transmitter outputs a +5 volt synchronization pulse on the TMS320C30 digital channel at approximately the middle of the symbol duration. The baseband waveforms u(t) and v(t) are filtered before being sent to the RF modulator. In the transmitter model discussed in Section 2.2, Nyquist filters were used in order to eliminate Intersymbol Interference (ISI) and maximize the Signal-to-Noise Ratio (SNR). Butterworth filters, which are contained on the Spectrum DSP cards, were used in the prototype implementation. As a consequence of not using Nyquist filters, the received noise power will be greater in the Butterworth filter case.  Section 2.4 RF Modulator/Demodulator and Channel A detailed block diagram of the hardware implemented RF modulator/demodulator is shown in Figure 2.4 and presented in [7]. The modulator and demodulator are designed to operate at the relatively low carrier frequency of 1.5 MHz. The carrier frequency enters the modulator to be divided into its I and Q components by a 900 splitter. The carrier's I and Q components are then mixed with the I and Q baseband signals and summed by a signal combiner. The resulting RF modulated carrier is amplified and passed to the channel module, which allows fading to be simulated by the use of the Digital Fading Simulator presented in [8]. White Gaussain noise is also added to the channel from a White Noise Generator whose band coverage is 6 kHz to 25 MHz. The modulated carrier and white noise is filtered by a Band Pass Filter (BPF), which has a 3 dB bandwidth of 200 kHz centered at the carrier frequency of 1.5 MHz. The bandwidth of the BPF Section 3^  14  Chapter 2  is much greater than that of the Low Pass Filters (LPF) at the demodulator and is used to minimize noise. The demodulator takes the received RF modulated carrier and splits it into its I and Q components, which are then coherently mixed down to the baseband signals. The baseband I and Q signals are passed through Low Pass Filters (LPF) and fed to the DSP card for Differential Baseband Detection.  Figure 2.4 Modulator , Demodulator, and Channel simulator. Section 4^  15  Chapter 2  Note the symbol synchronization pulse is directly connected from the transmitter DSP card to the receiver DSP card. In practice a local oscillator, closely tuned to the symbol rate of the I and Q channels, would trigger the receiver. This procedure was investigated, but it resulted in a synchronization problem. It was observed that approximately 150-200 symbols were correctly received, immediately followed by 50-100 incorrect symbols and then the cycle begins again. The local oscillator drifted in and out of synchronization with the I and Q channels' symbol rate. In order to obtain optimum synchronization, a Phase Locked Loop (PLL) circuit was employed. The PLL worked and the results were encouraging but required further research. Since the investigation of symbol synchronization effects is beyond the scope of this thesis, we opted to use the transmitter DSP card to trigger the receiver.  Section 2.5 DSP Implemented Baseband Differential Detector The block diagram of the Differential Detector is shown in Figure 2.5 [6]. Once Symbol Sync Signal  Low Pass Filter r(t)  ü(t)  Sample & Butterworth -IHold LPF ADC  cos(wt) ^ ii  sin(wt) Low Pass Filter  qr)  •  kI  k  Sample & Hold Butterworth ^ LPF ADC  Decision Rules DSP Receiver Card  RF Demodulator  Figure 2.5 DSP Baseband Differential Detector Block Diagram  the RF modulated carrier is converted into its I and Q baseband signals  et(t)  and 1/(t), it  is ready to be processed by the DSP Differential Detector. The DSP card drives each baseband signal through a Butterworth filter, a Sample and Hold circuit, and an Analog Section 4^  16  Chapter 2  to Digital Converter (ADC). It is the digital output of the ADC that the TMS320C30 addresses in order to obtain a real floating point representation of the amplitudes Ilk and 14 of the received baseband signals. The DSP detector samples each symbol and uses equations 2.6(a) and 2.6(b) in order to transform the DQPSK real data Ilk and 14, to QPSK real data wk and zk [6]. ^Wk = iik_iiik + 2,k_124 = cos (Ok  —  Ok i)  ^  —  (2.6a)  = iik—V3k — 14—iiik = sin (Ok — Ok—i) -^(2.6b)  ^zk  This transformation of 7r/4—shift DQPSK data to QPSK data makes each symbol no longer dependent on the previous symbol for decoding purposes. Note that wk and zk are equivalent to sin (Ok — Ok—i) and cos (Ok — Ok_i), where Ok — Ok—i is the phase shift. It follows that, since the phase shift can only be k7r/4, where k = ±1 or ±3, wk and zk  ,\/ The real floating point values obtained for wk and zk will be approximately +—T.  may be fed into a soft decision Viterbi decoder or can be hard decoded according to the following decision rules: SI = SQ  1 if wk > 0^SI = 0 if  wk < 0  = 1 if zk > 0^SQ = 0 if zk < 0  (2.7)  where Si. and SQ are the least and most significant bit of the symbol respectively. Note the prototype system utilizes the same carrier frequency for both the modulator and demodulator. In practice a local oscillator tuned to the same frequency as the transmitter is used to demodulate the received carrier. This local oscillator will have a constant phase difference but it has been shown that the phase error is cancelled through differential detection [6]. Section 5^  17  Chapter 2  Section 2.6 Theoretical Analysis and Prototype Performance The probability of a binary digit error for four-phase DPSK with Gray coding in an AWGN channel is given by [9] as —2 Eb ^{  P4b(e) = e N°  k=0(.\/ — 1)k Ik(  _Eb^1 T^'N,Eb (2.8) No^2A°^N^'^  where Ik is the kth order modified Bessel function of the first kind. The Bit Error Rate (BER) curve based on Equation 2.8 is plotted in Figure 2.6. Figure 2.6 also shows two experimentally measured curves of the prototype modulation scheme in an Additive White Gaussian Noise (AWGN) channel. The curve labelled as "Uncoded BER with Butterworth Filtering" is the actual performance of the prototype implemented. There is a considerable degradation of 6 dB as compared to the theoretical ideal curve. This degradation is primarily due to the substitution of the required Nyquist filters with 4th order Butterworth filters. The required Nyquist filters were unavailable and the Butterworth filters are contained on the DSP cards. The effect of the Butterworth filter is to allow more noise to pass through to the receiver and cause 1ST in comparison to the Nyquist case. As a result, the prototype will have worse performance since the SNR after the receiver filter will be less than the Es/No which would exist when employing a square root Nyquist filter. Through the use of a computer simulation, which used the Butterworth and Nyquist filters' bandwidths as parameters, it was found that the difference between the Butterworth and Nyquist case is approximately 5 dB. The curve labelled as "Uncoded BER with Nyquist correction" is a result of this correction factor. Note that this is an approximation, the true Nyquist correction factor must also account for the added ISI caused by the Butterworth filter. The prototype's corrected performance Section 6^  18  Chapter 2  is relatively close to the theoretically expected performance with a maximum degradation of 1 dB. This deviation is attributed to the following factors. •  The non-ideal signal space at the demodulator output, due to the imperfect RF components.  •  The imperfect timing of the software controlled symbol synchronization signal.  •  The ISI caused by the Butterworth filters.  For convenience, all subsequent performance curves of the implemented system will be adjusted by this "Nyquist correction factor". This also holds for the coded case, since Section 6^  19  Chapter 2  the performance is plotted against the SNR level. The SNR level that would exist with the Nyquist case is just a simple adjustment as above. Figure 2.7 presents the measured BER performance of the modulation system in a combined AWGN and Rayleigh fading environment with BDT equal to 0.0043, 0.0022, and 0.00084. The BD T products correspond to a 7r/4 shift DQPSK system operating with a carrier frequency of 900MHz, a baud rate of 19.2kBaudis, and vehicle velocities of 100, 50, and 20km/hr respectively. Also shown in the graph, is the theoretical BER results for a static multipath fading channel. Static refers to the channel having a constant phase modulation (i.e., the receiver or vehicle is at rest). The experimental results are for vehicles in motion and therefore, are expected to be worse than the theoretical curve for a vehicle at rest. It is evident that the theoretical and experimental results are in close agreement until a residual error floor is established by the experimental curves. This error floor is a result of the random phase modulation caused by the doppler spread obtained from the vehicle being in motion. An increase in the doppler spread results in an increase in the level of the error floor. The experimental results are less than an order of magnitude higher than the computer simulated results of Feher [10] and Bouras [7]. This deviation is due to the imperfections in the modulation scheme and the hardware Rayleigh simulator, as well as the Receiver DSP Card clipping the input voltage waveforms of the I and Q channels to ±3 volts even though the amplitude periodically fluctuates beyond these limits.  Section 6^  20  Chapter 2  Section 2.7 Conclusions The operation of the prototype 7r/4 shift DQPSK system was verified through experimental measurements. The BER performance data obtained for the AWGN channel and the combined AWGN and Rayleigh Fading Channel were in very good agreement with the expected theoretical results illustrating the proper operation of the prototype modulation scheme.  Section 7^  21  Chapter 3  Chapter 3 Application of Complementary Punctured Convolutional Codes to a SW Type II ARQ Scheme Section 3.1 Introduction Recently, Kallel has introduced a new class of punctured convolutional codes which are complementary [11]. In this Chapter we will briefly review Complementary Punctured Convolutional (CPC) Codes and their structure. Section 3 will present the generalized CPC SW Type II Hybrid ARQ algorithm, and Section 4 will discuss its specific implementation using DSP cards housed in an IBM PC. The performance of the implemented prototype will be compared to numerical and computer simulated models in Section 5.  Section 3.2 Review of Complementary Punctured Convolutional Codes (CPC) In general, a high rate (b/N) punctured convolutional code can be constructed from a rate 1/N0 mother code by periodically and selectively deleting (bNo—N) code bits according to a specific perforation pattern [12]. The function of deleting code bits is usually performed by the use of a perforation matrix which consists of b columns and No rows for a rate of b/N punctured code. Each column is associated with one encoding  cycle, and each row is associated with each coded bit stream from the No modulo-2 adders of the 1/N0 encoder. The perforation matrix consists of ones and zeros which corresponds to transmitting and not transmitting code bits. An example, of a rate 3/4 punctured convolutional code of period 3 obtained from a rate 1/2 code is given by _ [^ o^ot 1 . - 1 1^_I 22  (3.1)  Chapter 3  An equivalent punctured code can be obtained by likewise cyclically shifting the No rows. At the most, this will yield b distinct codes which have the same distance properties and error performance capabilities [13]. As a result, P2, which is given by P2 =  [0 1 1 1^0^1]'  (3.2)  and Pi are equivalent perforation matrices.  3.2.1 CPC Codes Allow Pi, i=1,2, p, to denote the perforation matrices of p equivalent CPC codes of rate b/N obtained from a rate 1/N0 mother code, where p=r14=1• The result of perforation matrix Pi is code CPCi. Define the matrix PTOTAL as PTOTAL^Pz •^  (3.3)  i=1 The p equivalent codes CPC,, i=1,2, p, are said to be Complementary if every element of PTOTAL is greater than or equal to one. Note that for convenience the p equivalent codes were denoted as CPC, but if they do not met the above restriction associated with PTOTAL, they should not be referred to as CPCi. The rate of PTOTAL is given by b/(pN)  which results in two possible cases. If N = N0, we have p = b and the rate of PTOTAL will be b/(bN) = 1/N0, which is the original mother code. On the other hand, if N>N0 and p<b matrices are chosen to satisfy Equation 3.3, then some elements of PTOTAL will be greater than one and the combined rate is b/(pN). As an example, the two previous matrices Pi and P2 of rate 3/4 are combined to form PTOTAL and yield a resulting code rate of 3/8. PTOTAL = [2  Section 2^  23  (3.4)  Chapter 3  Section 3.3 Generalized CPC SW Type ll Hybrid ARQ Algorithm Allow Pi, i=1, 2, ..., p, to denote the perforation matrices of p CPC codes of rate b/N obtained from a rate 1/N0 mother code, as discussed above. The result of perforation  matrix Pi is code CPC. The scheme begins by appending ndp detection parity bits and m tail bits, corresponding to the encoder's memory, to each k-bit data packet. The resulting sequence is encoded by the rate 1/N0 mother code and then punctured and transmitted according to the following algorithm [11]. 1. Level 1: Puncture the sequence with 131, resulting in packet A of code CPC/ which  is transmitted. The receiver decodes packet A using a rate 1/N0 Viterbi decoder and perforation matrix 13/. The error detection decoder checks the decoded sequence consisting of data bits and parity bits. If the sequence is declared error free, transmission of A is complete. Otherwise, the received sequence is stored for future decoding attempts and the algorithm moves up to the next level. 2. Level i, I< i <p: Transmit packet A of code CPC, resulting from Pi. Initially, use  Viterbi decoding with perforation matrix Pi. If the decoded sequence is declared error free, transmission of A is complete. Otherwise, reapply Viterbi decoding but on the combination of all i sequences, previously stored up to this level, and using perforation matrix PTOTAL=P 1+P 2+ . • .4-P i • If the resulting sequence is declared error free, transmission of A is complete. Otherwise, the current sequence is stored and the algorithm moves to the next level. 3. Level p: Send packet A of code CPC,. As above, initially decode using only the received sequence. If unsuccessful, decode using all p sequences. If the resulting Section 3^  24  Chapter 3  sequence is still in error, discard the received sequence of code CPC] and the algorithm moves to the next level. 4. Level (p+j), j=1,2,... : Send Packet A of code CPC,. Decode using the received sequence in conjunction with perforation matrix Pi. If unsuccessful, decode using all p sequences. In the event that decoding is still unsuccessful, discard received sequence at level j+1 and the algorithm moves to the next level. It should be pointed out, that the above encoding and transmitting strategy did not discuss the implications of appending a flag and a header to packet A. In the event that a flag is not found in the implemented prototype, the receiver will time out, and the algorithm will reinitialize at the current level. In practice it is the transmitter which times out if it receives no response from the receiver. If a header failure is detected, the current packet is discarded and the algorithm also reinitializes at the current level. Since the transmitter and receiver DSP cards are contained in the same PC they are initialized and synchronized by the Host ARQ protocol.  Section 3.4 DSP Implementation of a CPC SW Type ll ARQ Scheme The Stop and Wait Type II Hybrid ARQ Protocol is written in Borland C++ and resident on the host PC. The protocol behaves as discussed above with p=2 CPC codes of rate 3/4 from a rate 1/2 mother code. The two perforation matrices used by the DSP transmitter card for encoding the data packet are given by [i 0 11^n^1 11 -r 2— 1 1 0^1 0 1  (3.5)  Figure 3.1 shows the physical block diagram of the prototype communication system. The protocol constructs the header and random data packet, places them in the Dual Access Section 4^  25  Chapter 3  Memory (DAM), and strobes the DSP transmitter card to send and the DSP receiver card to listen. The DSP transmitter card retrieves the header and data packets and encodes them according to the information placed in the header. Once the frame is constructed, it is transmitted through the channel to the DSP receiver card, which is contained in the same PC. The DSP receiver card processes the received frame and either places an acknowledgment (ACK) or negative acknowledgment (NACK) in the DAM and strobes the protocol. Once the protocol fetches the DSP receiver's reply, two events may occur. If an ACK was sent, the protocol will construct a new header and a new random data packet to place in the DAM. If a NACK was sent, the protocol will keep the data packet but construct a new header which indicates the new Pi to be used for encoding the data packet. Note that if a frame is lost, the DSP receiver is equipped with a time-out feature which will result in a NACK.  Figure 3.1 Block Diagram of Prototype SW Type II ARQ Scheme. It  is during the construction of the header, that the protocol decides which perforation  matrix P1 or P2 to use for encoding the data packet based on the receiver's reply. Along with the NACK, the receiver sends the motive which may be either a Header CRC Failure or a Data CRC Failure. In the event of a header failure or lost frame (time-out), the protocol will not switch perforation matrices. In the event of a data failure, the protocol Section 4^  26  Chapter 3  alternates between P1 or P2. The result of this algorithm is to maximize throughput. This algorithm ensures that if a corrupted data sequence of code CPC1 is received, the next data sequence received can only be encoded by P2 and be of code CPC2. If the data sequence of code CPC2 is unsuccessfully decoded, it may be combined with the data sequence of code CPC1 for subsequent decoding. The modulation scheme used by the SW Type II ARQ Protocol for transmission, is the 7r/4 Shift DQPSK discussed in detail in Chapter 2. The following assumptions or simplifications are incorporated in the implemented prototype which consists of the DSP transmitter and receiver cards in the same Host PC under the control of the SW ARQ protocol. •  As a consequence of the transmitter and receiver DSP cards being in the same Host PC, they are initialized and synchronized by the ARQ Protocol running on the Host PC. In practice, there is an initialization and synchronization process to be executed by the independent transmitter and receiver.  •  In practice a noisy return channel is used to send the receiver's reply. In the prototype, the receiver's reply is passed internally through the PC via the DAM. This is a noise free return channel.  •  As a result of the ARQ protocol controlling both the transmitter and receiver, it is the receiver which times out if a flag is not found. Again, in practice it is the transmitter that times out if it does not get a response from the receiver.  •  Symbol Synchronization is accomplished by hard wiring the transmitter and receiver. The actual symbol timing signal is software generated and is not ideal. A practical system would have the receiver utilize a Phase Locked Loop or some other synchro-  Section 4^  27  Chapter 3  nization circuit to obtain symbol synchronization with no link to the transmitter. These simplifications do not compromise the accuracy of the experimental results. The prototype is used to evaluate various FEC strategies which are unaffected by the above simplifications.  3.4.1 Frame Structure The detailed structure of the frame used for transmission in the prototype system is illustrated in Figure 3.2. Excluding the preamble and flag, the maximum length the encoded frame may attain is 1024 bits. The frame begins with an 8 bit Symbol Sync Preamble. Since a Stop and Wait scheme is implemented, the channel will always be idle before a transmission and the preamble allows the receiver to realize symbol synchronization and stabilize before the remaining portion of the frame arrives. Immediately following the preamble is the Flag or Frame Sync, whose purpose is to present the receiver with a unique bit pattern so that the receiver may synchronize itself with the data stream's frame structure. The receiver is continuously hunting for the flag pattern and the actual procedure and choice of flag is investigated in the next section. 8 BITS^  r4  BITS 128 ENCODED BITS  I  4  PREAMBLE FLAG HEADER CRC 16 TAIL  896 ENCODED BITS 4^ ^  DATA BITS  ^  635 DATA BITS  AA  •  ^  FCS32 TAIL  32 BITS 5 BITS  2941B3  •^ 16 BITS  Pi  LENGTH  ADDRESS 4  •  P4  6 BITS^10 BITS  2 BITS  RESERVED^FCS16 TAIL  ••  • •^• • 9 BITS^16 BITS 5 BITS  Figure 3.2 Detailed Structure of Frame.  Section 4^  28  Chapter 3  Control information is contained in the 64 bit header, which includes a 16 bit Frame Check Sequence (FCS) and a 5 bit tail for decoding. The header's address field is used to identify the station that is to receive the frame. The next two fields, Ns and l■Ir are sequence numbers used to number the frames. The sequence numbers are not required for the operation of the prototype but has been included for future upgrading to a Selective Repeat scheme. The next field contains the length of the data packet following the header. The following field consists of two bits which indicate the perforation matrix Pi used in the puncturing operation during the encoding of the data. Reserved is the  next field which consists of 9 bits and is not used by the current version of the protocol. The remaining 16 bits represent the FCS which is a result of the generator polynomial CRC—CITT defined as G16 (x) = x16 + x12 + x5 + 1. The information or data bits are contained in the data packet of the frame. This consists of a maximum of 896 CPC encoded bits. As a result of using a perforation matrix which yields a rate of 3/4, the maximum number of information bits which the data packet can contain is (896) — 32 — 5 = 635 bits. The length of the entire frame consisting of preamble, flag, header, and data packet is 1056 bits. The generator polynomial used for the FCS is the CRC32 given as G32 (X) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + xl + 1.  3.4.2 Frame Synchronization The 24 bit flag, denoted in hexadecimal as 2941B3, is used by the receiver to synchronize itself with the data stream's frame structure. A good flag sequence has the property that the absolute value of its correlation sidelobes is small. A correlation sidelobe is the value obtained by correlating a flag sequence with a time-shifted version Section 4^  29  Chapter 3  of itself. Therefore, a correlation sidelobe value, Ck, for a k-symbol shift of a N bit flag sequence ffjj, is given by Ck =  N—k ^  FjFj+k ,^  (3.6)  3=  where Fi (1 i 1\1) is an individual bit taking values of ±1, and the adjacent bits (associated with index values i>N) are assumed to be 0 [14]. The actual flag was found through the use of computer simulations. Figure 3.3 shows the correlation sidelobes of the flag used in the prototype. The sidelobes are very low when compared to the main lobe of Co, which yields a value of 24. This sidelobe profile ensures a very high probability that the receiver will find the exact starting point of the flag rather than a bit shifted version of it. 30  Correlation Sidelobes of Flag 2941B3 hex  25  20  0 -1  15  10  o 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Ck  Figure 3.3 Correlation Sidelobes of Flag used in Prototype.  The following procedure is followed to allow the receiver to locate the flag. The receiver correlates the known flag pattern to the incoming data. If the incoming data does not contain a flag, the correlation value will be low. On the other hand, when a flag is Section 4^  30  Chapter 3  encountered the correlation value will be very high. The correlation value, C, for a 24 bit flag pattern {TV and a 24 bit data sequence {Di] is given by C  24 =^F.)^,^  =i  (3.7)  where Fi and Di take on values of +1 or —1 representing bits 1 and 0 respectively. The maximum value of C is 24 which indicates a flag with 0 bit errors has been located. The prototype compares C to a user set threshold value which limits the number of bit errors which will be accepted in the flag and still ensure frame synchronization (i.e., a threshold value of 16 indicates that 20 bits of the data sequence match the flag pattern). The optimum threshold value was found through experimentation. For each SNR tested, a 1000 uncoded frames were sent to the receiver whose correlation threshold value was altered over the range of 10 to 24. Referring to Figure 3.3, it is seen that the highest sidelobe has a value of 5. A starting point for the threshold value is to take twice the highest sidelobe value which is 10. Figure 3.4(a) illustrates that the probability of a bit error is relatively equal for threshold values of 24 to 10. However, lowering the threshold value below 10 results in the prototype operating very slowly because it must process a large number of false flags. The lower the threshold value, the larger the amount of false flags that the prototype must process. Figure 3.4(b) shows the percentage of flags successfully found given the different threshold values. It is seen that the lower the threshold value, the greater the success of finding the flags. Another observation is that decreasing the threshold value below 12 has a marginal affect on the flag success rate. A balance must be found in which a threshold value that gives a good flag success rate does not burden the prototype with false flags. The two curves representing threshold values of 10 and 12 give the best success rates and are relatively equal. It is obvious from Section 4^  31  100  10 10 10 10  -2  •^  -3  -4  10 10 10 10  -6  -7  -8  2^4^6^8^10 12 Eb/1\10 1oll3 Uncoded Frame using threshold = 10 ^ • ^ Uncoded Frame using threshold = 12 ^3 ^ Uncoded Frame using threshold = 14 ----In--Uncoded Frame using threshold = 16^a Uncoded Frame using threshold = 20 ^ Uncoded Frame using threshold = 24 ^  14  2^4^6^8^10^12  14  0.9 0.8 r,^0.7 X,^0.6  §  0.5  ±1^0.2 0.1  Lb/Ne  Uncoded Frame using threshold = 10 ^ • ^ Uncoded Frame using threshold = 12 ^ Uncoded Frame using threshold = 14 ---11^ Uncoded Frame using threshold = 16 Uncoded Frame using threshold = 20 Uncoded Frame using threshold — 24  Figure 3.4 (a) and (b) Effects of Changing Threshold value used for Hag Correlation  Section 4^  32  Chapter 3  By comparing the correlation value, C, to a threshold value, a certain number of false flags will be located. The prototype receiver implemented is "smart" enough to eliminate the majority of false flags. When a flag is located, the header is immediately decoded and two events may occur. 1. If the header fails the CRC check, the next subsequent flag is located and the new header is decoded. If the CRC check fails again, the process repeats itself until the header CRC is passed. 2. If the header passes the CRC check, the length of the frame is obtained and all the false flag occurrences falling within the range of the frame are ignored. By using this simple procedure a very large majority of the false flags are ignored.  3.4.3 Encoder/Transmitter DSP Card The Encoder/Transmitter DSP Card contains the following C software modules: •  CRC Encoder is responsible for calculating the Frame Check Sequence (FCS) bits and is able to use generator polynomials up to 32 bits.  •  Rate 1/2 Convolutional Encoder outputs two data streams representing the two modulo-2 adders of the encoder. A simple module named Combine is required to interleave the two outputs of the adders. The two generator polynomials are Gi (x) = x4 + X3 + 1 and G2 (X) = X4 + X2 + X1 + 1 and are user configurable.  •  Puncture Module individually punctures the two data stream outputs of the rate 1/2 convolutional encoder. The module punctures according to the perforation matrix Pi which is chosen by the host SW ARQ protocol. Combine is required in order to interleave the two punctured outputs of the encoder adders.  Section 4^  33  Chapter 3  •  Block Interleaver accepts the coded symbols in 128, 256, or 512 bit blocks. The interleaver may be visualized as a rectangular array of I rows and n columns. The encoded symbols are read into the array by rows and read out by columns. The vertical dimension of the array, I, is called the interleaving degree and is user configurable by selecting values of 4, 8, and 16. The prototypes tested used an interleaving degree of 16.  •  Queueing Module manages an 8 slot queue and is responsible for beginning and terminating the operations of the 7r/4 shift DQPSK baseband generator.  It is the main program written in DSP Assembly language which utilizes the above software modules and provides the encoding and transmitting services required by the host protocol. Figure 3.5 is a detailed description of the self explanatory procedure followed by the main program to encode and construct a frame. The two final operations not shown would be to interleave the frame and place it in the queue for transmission. The header and data are fetched from the Dual Access Memory.  Section 4^  34  Chapter 3  Section 4^  35  Chapter 3  3.4.4 Receiver/Decoder DSP Card The Receiver/Decoder DSP card contains the following DSP Assembly software modules: •  Flag Correlator is used to locate the occurrence of a flag in a data stream according to a user set threshold value. Section 3.4.2 gives a detailed explanation of this software module.  •  Transform is responsible for transforming the soft 7r/4 shift DQPSK data to soft QPSK data and as a result eliminate the dependency between neighboring symbols. Section 2.5 discusses this transformation and its results.  •  Soft Data Deinterleaver is required to deinterleave the soft QPSK data. This module operates on soft data as compared to its inverse module Block Interleaver which operates on hard data.  •  CRC Encoder is the same module used by the transmitter DSP card. The difference is that the calculated Frame Check Sequence (FCS) is compared to the received FCS in the decoding mode.  •  Data Sequence Combiner is responsible for combining soft data sequences of different codes, such as CPC1 or CPC2, to form a more powerful code for error correction purposes.  •  Rate 1/2 Soft Decision Viterbi Decoder is utilized to decode the header and data according to the perforation matrix used in the encoding process.  •  In the CPC SW Type II ARQ scheme with code combining, an additional module called Code Combining, which optimally combines data sequences of equal codes such as CPC], is required.  Section 4^  36  Chapter 3  Figure 3.6 is a detailed flow chart of the Receiver/Decoder DSP algorithm. The algorithm is a direct result of the general scheme presented in Section 3.3 with p=2 CPC codes of CPC1 and CPC2. As shown in Figure 3.6, the replacement of a module is necessary in order to incorporate code combining. Rather than simply save the most current corrupted data sequence of code CPC1 or CPC2, the module combines the current sequence with all previous corrupted sequences of the same code for further subsequent decoding.  Section 4^  37  •  START  FIND FLAG OCCURENCE  GET CODED DATA  TRANSFORM DQPSK TO QPSK SOFT DATA  CHOSE PUNCTURE MATRIX PI or P2  HAVE BOTH CPC I & CPC2?  NO  SEND NACK  YES  DEINTERLEAVE REAL DATA  COMBINE CPC I & CPC2  GET CODED HEADER  RATE 1/2 SOFT DECISION VITERBI  RATE 1/2 SOFT DECISION VITERBI  CRC DECODER  YES FCS OK?  CRC DECODER  YES  SAVE COPY OF CURRENT CODED DATA CPC I or CPC2  SEND ACK  SEND NACK  NO SEND NACK COMBINE CURRENT COPY OF CODED DATA CPC1 or CPC2 WITH EXISTING COPIES  THIS MODULE IS SUBSTITUTED FOR THE ONE ABOVE IT IF CODE COMBINING IS REQUESTED.  Chapter 3  Viterbi Decoder A 16 state rate 1/2 soft decision maximum likelihood Viterbi Decoder is the heart of the receiver. It is entirely written in DSP Assembly Language for speed and efficiency. The soft decision decoding scheme makes use of past information bit history and a metric function to decode the incoming data. It follows, that the performance of the Viterbi decoder is primarily influenced by the choice of path history length and the metric function. It is common practice to select a path history length equivalent to four or five times the constraint length of the encoder which results in negligible degradation from the optimum decoder performance [14]. In the case of the prototype, the constraint length is 5 and the path history length utilized is 32 information bits. The Viterbi decoder operates on soft QPSK data which is the product of the transformation of soft 7r/4 shift DQPSK data. The metric chosen is the Euclidean distance based on the signal constellation of the QPSK signals. The Euclidean distance is defined as D = \ I(X c — X11)2 + ( Yc — YR)2 ,^  (  3.8)  where Xc and Yc are the coordinates of the signal on the constellation for QPSK and XR and YR are the coordinates of the received data. Calculating the metric as defined in equation 3.8 is a very tedious and time consuming operation. The square root operation is not performed, and although it is not a linear function, distance values without the square root operation work well because the relationship between x and VT( is one-to-one and monotonic. To further simplify 3.8, one may expand the brackets and discard the squared terms to yield D = XcXR d-YcYR•  ^  There is a considerable amount of time saved in calculating 3.9 as opposed to 3.8. Section 4^  39  (3.9)  Chapter 3  Once the Viterbi decoder is initialized, it will keep track of 16 surviving paths through the trellis. As depicted in Figure 3.7, at each new decoding instant, each survivor leads to two new states or paths, thereby yielding a total of 32 new paths. The decoder calculates the branch metrics ,3 and y, related to the two new states, and then adds them to the accumulated metric a resulting in new accumulated metrics of cH-13 and a+-y. The smallest new accumulated metric will be chosen as the new surviving path. PREVIOUS^ STATE^  CURRENT STATES  ^4 10 so ,41•  ^a + 13  BRANCH METRICS  a  Si^+ y  PREVIOUS^ ACCUMULATED^ METRIC^  NEW ACCUMULATED METRICS  Figure 3.7 Choosing a Path Survivor.  In practice, it is not possible to continue to accumulate the metric distances without encountering an overflow problem. Therefore, a weighted accumulation method is used to determine the accumulated metric and is given as Dnew  = 13Dold + (1 — MDbranch,^  where 0<</3<1 denotes the weighting factor, Dbranch is the branch metric, and Doid are  (3.10) D„,„  and  the new and old accumulated distances respectively. This ensures that the new  accumulated metric is bound. The value of /3 is a performance parameter which is chosen to be 0.98 in the implemented Viterbi decoder. Section 4^  40  Chapter 3  Numerical Analysis Given the free distance df„, and the distance spectra  ad  and cd,  where ad is the number of incorrect paths of Hamming weight d that diverge from the correct path and remerge with it sometime later, and cd denotes the total number of bit errors in all the paths having Hamming weight d, the probability of a bit error for Viterbi decoding is upper bounded [15] by co  P(B) <^CdPd • ^  (3.11)  d=df,„  Pd  is the probability that a wrong path at distance d is selected and depends only on the  channel and modulation scheme used [9]. For an AWGN channel and R-14 shift DQPSK, Pd may be obtained as follows. The probability of a binary digit error for four-phase signalling over L statistically independent AWGN channels is given by [16] as  E  k=0  yrbL)^12./0( V-2_,\ErobL)  (\/-1)ki-k(\/—  L  P4b(C)^C  L-1 (.\/^(,\TEabL) 71.1CnM + ^  1  (3.12)  ( 1^ 2L — 1 ) where CT, = 22L-1^ k^} • k=0  Pd  is the probability that a wrong path at distance d is selected and may be obtained  from Equation 3.12 by substituting d for L. Using 3.11 and 3.12 with the substitution, an upper bound for the performance of the rate 1/2 Viterbi decoder was calculated. Figure Section 4^  41  Chapter 3  3.8 depicts the resulting upper bound using a rate 1/2 code with weight spectrum given by Table 3.  Generator Rate  (adfree+j 1 j=0,  dfiee  {Cdftee+j,  Polynomials 1/2  23, 35  1, ...4)  j=0,^1, ...41  (2, 3, 4, 16, 37)  7  {4, 12, 20, 72, 2251  Table 3 Distance Spectrum of Code with Rate 1/2.  Computer Simulation A C computer simulation was used to verify the prototype Viterbi decoder's performance. The computer model simulates the prototype which uses a 7/4 shift DQPSK modulation system with the receiver transforming the soft DQPSK data to soft QPSK data for decoding purposes. Figure 3.8 shows the BER curve resulting from the computer simulation. As a result of transmitting 106 bits for each SNR level tested, the BER curve is accurate for points above 10-5. The simulation BER curve is below the upper bound curve for all accurate SNR levels tested.  Viterbi Decoder Performance Figure 3.8 illustrates the probability of a bit error for the Viterbi decoder implemented. For each SNR level tested, the Viterbi decoder processed 107 bits. As is evident, the prototype curve is slightly worse than the simulation curve but close to the upper bound curve. This is expected since the simulation cannot take into account implementation losses. The small deviation between the simulated and prototype curves is due to the imperfect modulation system and synchronization timing. The rate Section 4^  42  ^  Chapter 3 Pi/4 QPSK Modulation Scheme  1 0°  •  10 10  -2  \mi 10  10  10  10  10  10  -3  -4  -5  -6  -7  -8  0  ^  2^4^6^8  ^ ^ ^ 12 14 10  Eb/No [dB]  ^Computer Simulation for Rate 1/2 Viterbi Decoding^• • Prototype BER for Rate 1/2 Viterbi Decoding ^ Numencal Analysis for Rate 1/2 Viterbi BER ^• Uncoded theoretical BER Curve ^ Figure 3.8 Rate 1/2 Soft Decision Viterbi Decoder Performance.  1/2 soft decision Viterbi decoder implemented operates as expected and its performance is verified by the computer simulation and upper bound curves.  Section 3.5 Prototype Performance In this section the throughput performance of the prototype CPC SW Type II ARQ system in AWGN is compared to the ideal numerical results. The prototype's throughput performance in a Rayleigh fading channel is also presented and discussed. Section 5^  43  Chapter 3  3.5.1 Throughput Analysis The throughput 7/ is defined as the average number of accepted information bits per transmitted channel symbol and has a maximum possible value of 2 for DQPSK modulation. In general, 71 may be defined as RIN, where R is the code rate and N is the average number of packets transmitted per correctly decoded packet. If the error detection parity bits along with the overhead of the header and flag are taken into account, the resulting throughput is R  71 =^LED "JOH  where  and  LED  ^  (3.13)  k + ndp +  (k ndp  m)  Lau = ^ *(k ndp^h +f  The factor LED is the loss in throughput due to the addition of parity bits ndp and the tail of m known bits. The factor  Loll is the loss in throughput as a result of the overhead  incurred by the frame for appending a rate 1/2 header, h, and a flag, f, to each block of k information bits. The average number of packets transmitted per correctly decoded packet, N, for a CPC SW Type II ARQ scheme is given in [11] as p-1 1 + EPr{Dd(z)})1_ Pr{Dd(P)}  (3.14)  where Dd(j) is the event {decoded sequence obtained by combining j equivalent codes, is detected in error}. As in [11], Pr{Dd(j)}, assuming the undetected error probability is negligeable, is bounded as Pr{Dd(j)} <1— (1— P(E))1 , ^ (3.15) Section 5^  44  Chapter 3  where P(E) is the error event probability of Viterbi decoding with a code obtained by combining j equivalent CPC codes (i.e., CPC1+CPC2+...+CPC1) and where 1 is the number of trellis level (1,-(k+ndp)1b). P(E) is bounded as [15], 00  P(E) <  ^  (3.16)  d=d3free  where Pd is the probability that a wrong path at distance d is selected, and where c/frel and  al are the free distance and weight spectra of the code obtained by combining j equivalent CPC codes. Pd is dependent on the channel and modulation scheme employed [9]. Numerical Results Table 4 contains the distance spectra for the rate 3/4 punctured convolutional code used in the CPC SW Type II Scheme. Pd is given in Equation 3.12, Code  CPC1  Perforation Matrix  [1^0^1 i 110  cpc2  dfree  (ad+j,  j=0,1..5)  3  (1, 2, 23, 124, 576, 2852)  3  (1, 2, 23, 124, 576, 2852)  8  (1, 4, 3,^11, 18, 38)  J  [1^1^0-1 011 ]  CPC1 + CPC2  [2^1^1 1 121 i  Table 4 Distance Spectra of Rate 3/4 Punctured Convolutional Code of Memory m=4.  where d is substituted for L. Using the values in Table 4 and Equations 3.13, 3.14, 3.15, Section 5  ^  45  Chapter 3  and 3.16 a lower bound on the throughput for an AWGN channel with 7r/4 shift DQPSK modulation can be calculated. The resulting lower bound is plotted in Figure 3.9. 3.5.2 Experimental Throughput  The rate 3/4 CPC SW Type II ARQ scheme is tested over several SNR levels by executing the scheme until 1000 frames are successfully delivered. The resulting throughput is plotted in Figure 3.9 along with the previously calculated lower bound. Note that the throughput, which is the average number of information bits accepted per symbol, can be greater than one. This is a consequence of using 7r/4 shift DQPSK which has a maximum throughput of 2 information bits per accepted symbol. For medium to Rate 3/4 CPC SW Type II ARQ Scheme in AWGN  •^  U  1 0.9  0.7 0.6 0.5 0.4 0.3 0.2 0.1 2^4^6^8  ^  Es/No [dB]  10  12  Ideal Lower Bound Throughput Experimental Prototype Throughput Adjusted Throughput for Header & Frame Loss Figure 3.9 Numerical and Experimental Throughputs.  Section 5^  46  •  ^  14  Chapter 3  high SNR levels, the experimental curve and the lower bound are in good agreement. This is expected, since the Viterbi BER curve plotted against its upper bound is also in good agreement. At low SNR levels, the prototype throughput has a maximum degradation of I dB. The calculated lower bound does not take into account header failures or lost frames. Whereas when the prototype encounters a lost frame or header failure, the entire data packet is discarded and taken into consideration for the throughput calculation. If header failures and lost frames are accounted for, the throughput of the system in question will suffer a decrease. To further prove this point, Figure 3.9 also plots a curve labelled as "Adjusted Throughput for Header & Frame Loss". This curve is obtained by ignoring lost and header damaged frames in the prototype system. Recall, that the receiver is capable of transmitting a NACK which indicates whether the frame had a header failure or data failure. The transmitter keeps track of the type of NACKs, as well as the lost frames (time-outs). It is this information which is used to adjust the throughput for header failure and frame loss. It is clear that this adjusted curve is in good agreement with the lower bound with slight degradation at low SNR levels resulting from implementation losses which are critical at lower SNR levels. The scheme is able to correct a certain number of errors. At medium to high SNR levels, the scheme easily corrects the channel errors as well as the errors associated with the implementation losses. At low SNR levels, the number of channel errors in addition to the implementation loss errors places a load on the scheme and results in a negligeable degradation of 0.5dB (maximum) from the lower bound curve. The implementation losses are factors such as: •  imperfect symbol synchronization,  •  non-ideal modulator and demodulator, and  Section 5^  47  Chapter 3  •  1ST from the Butterworth filtering. It is clearly evident that since the prototype rate 3/4 CPC SW Type II ARQ scheme  is in very good agreement with the lower bound, it is correctly operating and behaves as expected.  3.5.3 Rayleigh Fading Channel The throughput of the prototype rate 3/4 scheme was also investigated in the combined AWGN and Rayleigh fading channel environment. The measurements were obtained for three BDT products of 0.0043, 0.0022, and 0.00084. These BDT products correspond to a 7r/4 shift DQPSK system operating with a carrier frequency of 900MHz, a baud rate of 19.2kHz, and vehicle velocities of 100, 50, and 20km/hr respectively. The throughput curves are plotted in Figure 3.10. For comparison purposes, a lower bound on the throughput for a combined AWGN and a static multipath fading channel is also plotted. The lower bound is calculated in the same fashion as before, by using Equations 3.13, 3.14, 3.15, and 3.16. The probability of a binary digit error for four-phase signalling over L statistically independent AWGN with static multipath fading is given by [16] as i \^1^  P4blel — -- [ 1^ V2  it  k L-1, ( 2k) (1 — /12 ) ]  — it2 k=0  k^4 — 2,u2  'Yc  where ft = 1 +  (3.20)  and -T, is the average received SNR.  Section 5^  48  Chapter 3  Rate 3/4 CPC SW Type II ARQ Scheme in Rayleigh Fading 1.4 1.3 1.2  •  ••  1.1  •  0 .9 5^ 0.8 0.7 0.6 0.5  •  0.4 0.3 0.2 0.1 00  5^10^15^20^25^30  Es/No [dB]  Experimental Throughput for BT=0.00084 Experimental Throughput for BT=0.0022 Experimental Throughput for BT=0.0043 Static Fading Lower Bound  • • •  Figure 3.10 Throughput of Prototype in a Rayleigh Fading Channel.  As before, Pd is obtained from equating 3.20 by substituting d for L. The resulting lower bound is for a static multipath fading channel. The term static refers to the phase modulation of the multipath channel being constant (i.e., the receiver or vehicle being at rest). It is obvious that the three throughput curves obtained for the various vehicle speeds should be worse than the lower bound since the vehicle is not at rest. When the vehicle is in movement, the Doppler spread causes random phase modulations which in turn is responsible for the existence of residual error floors in the bit error rate as discussed in Section 2.6. In effect, the lower bound may actually be viewed as an upper bound when it is being compared to the prototype throughput at various vehicle speeds.  Section 5^  49  Chapter 3  Section 3.6 CPC SW Type II ARO Scheme with Code Combining The upgrading of the CPC SW Type II ARQ scheme to accommodate code combining is very simple. Only the receiver must be modified by the replacement of ten lines of DSP Assembly Language code. The new code or module ensures that the most currently received corrupted data sequence of code CPC1 or CPC2 will be combined with all previous corrupted copies of the same code (if the copies exist). The non—code combining scheme simply discards the previous copy of the corrupted data sequence once a new data sequence is received. It has been shown that code combining will increase the throughput of the scheme at low SNR levels [3]. Figure 3.11 illustrates the experimental results for the rate 3/4 CPC SW Type II ARQ scheme with and without code combining. As expected, the code combining case resulted in an increase in throughput to a maximum of 1dB. If the code combining curve is adjusted for header failure and lost frames, it is expected to perform better than the ideal Type II lower bound curve. Recall, that the Type II lower bound curve does not take into account lost or header damaged frames. Figure 3.11 also displays the "Adjusted Throughput for Header & Frame Loss with Code Combining", which as expected has a substantial  performance gain in throughput in comparison to the ideal Type II lower bound. To further verify the code combining scheme, measurements counting the number of frames transmitted to successfully deliver each of the 1000 frames at a certain SNR level were accumulated. Figures 3.12(a) and 3.12(b) are histograms representing the accumulated data for the non—code combining and code combining cases at a SNR level of 3.32dB. In comparing the two histograms, it is evident that the code combining case requires fewer transmitted frames to successfully deliver a frame since it is constantly combining data Section 6^  50  Chapter 3  sequences. This results in the number of transmitted frames being concentrated toward the lower end of the histogram, as opposed to the non-code combining case where the number of transmitted frames are spread out. These experimental results verify the correct operation of the code combining scheme.  Kate 3/4 uru s w 1 ype  11 IkKl,2 Jcneme  in HWU1N •  • TT 7.ell•  1.4 1.3  iii(5, /,  1.2  Ai.-  AS A  • • • I  1.1  //  1  1  0.9 0.8 0.7  1  0.6 0.5 0.4 0.3  1-.• • •i /  0.2 0.1 0  /^2^4^6^8^10^12^1 Es/No [dB] Ideal Lower Bound Throughput Experimental Prototype Throughput • Adjusted Throughput for Header & Frame Loss Experimental Prototype throughput with Code Combining • Adjusted Throughput for Header & Frame Loss with Code Combining  Figure 3.11 Throughput of CPC SW Type II ARQ Scheme with and without Code Combining  Section 6^  51  Chapter 3 500 Type II ARQ scheme using CPC Codes without Combining  400  300 (§)  200  100  A. Z. A .4! A o 0^2  3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Number of Successive Transmissions Required to Deliver a Frame SNR = 3.32dB with No Code Combining  500  Type II ARQ scheme using CPC Codes and Combining  400  300  200  100  o 0^2  3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Number of Successive Transmissions Required to Deliver a Frame SNR = 3.32dB with Code Combining  Figure 3.12 Histograms for Rate 3/4 CPC SW Type II ARQ with and without Code Combining  Section 6^  52  Chapter 3  Section 3.7 Conclusions A prototype rate 3/4 CPC SW Type II ARQ scheme of memory m=4 was implemented utilizing a host IBM PC, two TMS320C30 DSP cards, an existing RF modulator/demodulator, and an existing channel simulator. The rate 1/2 soft decision Viterbi Decoder was thoroughly tested in section 1 and behaved as expected according to both computer simulations and numerical results. The throughput of the prototype was experimentally measured for both an AWGN channel and a combined AWGN and Rayleigh Fading channel. The experimental results for the AWGN channel were in very good agreement with the numerical results. In the case of the combined AWGN and Rayleigh channel, the throughput curves were referenced to numerical results obtained for a static multipath fading channel. The experimental curves behaved as expected indicating proper operation of the prototype. When code combining was added to the prototype, the throughput at lower SNR levels increased. There is no extra cost associated with upgrading the prototype to a code combining scheme. It only requires the replacement of ten lines of DSP Assembly Language code. The code combining prototype was also verified for proper operation by comparing the histograms at certain SNR levels which counted the number of transmissions required to successfully deliver a frame. The comparison of the experimental data of the prototype's performance to the numerical results clearly validate the proper and correct operation of the implemented scheme.  Section 7^  53  Chapter 4  Chapter 4 An Adaptive SW Type II ARQ Scheme Section 4.1 Introduction The previous chapter illustrated how the CPC SW Type II ARQ scheme utilizing code combining achieved an increase in throughput at low SNR levels as compared to the same scheme without code combing. This chapter will focus on increasing throughput at all SNR levels by employing an adaptive coding rate to the CPC SW Type II ARQ scheme. The adaptive scheme uses Channel State Information (CSI) to decide which coding rate is the most appropriate to encode the data packet. Section 2 will present the algorithm used to adapt the coding rate to the AWGN or combined AWGN and Rayleigh channel. Section 3 will discuss the necessary software modifications to the existing DSP Assembly code and host IBM Protocol software. Section 4 will present the performance of the adaptive scheme for both the AWGN and combined AWGN and Rayleigh channel. Finally, all three implemented variations of the CPC SW Type II ARQ scheme will be compared and discussed.  Section 4.2 The Adaptive Coding Rate Algorithm A very simple and effective algorithm is used to select the current coding rate of the adaptive prototype. The algorithm calculates the throughput of the most recent N frames transmitted. The throughput is a measure of the channel state condition for the time interval required to transmit N frames. Based on this throughput, the algorithm decides which of the available coding rates to use from a user defined table. A user defined 54  Chapter 4  threshold diagram which utilizes three coding rates is illustrated in Figure 4.1 It follows  THRESHOLD VALUE 2 THRESHOLD VALUE 1  Figure 4.1 Threshold Regions Defining Coding Rates.  that the performance of the adaptive scheme is influenced by the selection of the value N and the threshold values. The smaller the value of N, the quicker the scheme adapts to the changing channel conditions. The threshold values are obtained from the throughput curves of the individual rates. In essence, one would superimpose the throughput curves and select threshold values to maximize the overall throughput of the scheme over all SNR values (i.e., select threshold values that will yield an overall maximum throughput equivalent to the maximum envelope of the individual throughputs). The generalized adaptive coding rate algorithm is best described by the following procedure. 1. Level 0: Select the most powerful coding rate (Rate 1) and transmit using this rate for N frames. The algorithm moves up to the next level. 2. Level 1: Calculate the throughput of the last N frames transmitted. If the throughput is less than THRESHOLD VALUE 1, continue using Rate 1 to send the N frames and the algorithm remains at this level. Otherwise, if the throughput is greater than THRESHOLD VALUE 1, select Rate 2 to transmit the N frames and the algorithm moves up to the next level. Section 2^  55  Chapter 4  3. Level i, i>1: Calculate the throughput for the most recent N frames transmitted. If the throughput is less than THRESHOLD VALUE i-1 select Rate i-/, transmit N frames, and move down to the next level. If the throughput is between THRESHOLD VALUE i-1 and THRESHOLD VALUE i, continue using Rate i, transmit N frames,  and remain at this level. If the throughput is greater than THRESHOLD VALUE i, select Rate i+1, transmit N frames, and move up to the next level. In the prototype, code rate synchronization is obtained by using two bits in the rate 1/2 header to indicate the coding rate of the data packet following.  Section 4.3 DSP Implementation of the Adaptive Scheme The adaptive coding algorithm is contained in the SW ARQ protocol running on the host PC. The transmitter and receiver DSP boards require minor software modifications to be able to encode and decode any of the supported coding rates. The other necessary modification is to use 2 of the 9 bits, labelled as RESERVED in the header, to indicate which rate is currently being used to encode the data packet. In the adaptive prototype scheme, N is chosen to be 5 and the coding rates used are 1/2, 3/4, and 1. The adaptive SW ARQ protocol can also be forced to transmit at one of the three code rates. Figure 4.2 depicts the experimental throughputs obtained for the three individual coding rates. Referencing Figure 4.2, THRESHOLD VALUE 1 is selected to be 0.77 and THRESHOLD VALUE 2 is 1.2. From the above algorithm, the rates of 1/2, 3/4, and 1 correspond to the code Rates of 1, 2, and 3 respectively. Notice by selecting THRESHOLD VALUE 2 to be 1.2, there will be a region of the overall throughput which will be less than the maximum envelope of any of the three individual throughputs. Maximizing the throughput over all SNR levels is not always possible. The Section 2^  56  Chapter 4  CPC SW Type II ARQ Scheme in AWGN .^•  1.6  I  *  1.5 1.4 1.3 1.2  ,  1 en  0.9 0.8  j  •  a  /  /  •  •  /  r  /  0.7  / / ,./•  0.6 0.5  /  /  •  •  /  0.4 0.3 0.2 0.1  1^41  +/  1.1  0  A—  / 1  /  i  i  2^4^6^8  ^ ^ ^ 10 12 14  Es/No [dB]  ^Experimental Throughput of Rate 1/2 Scheme ^ Exioerimental Throughput of Rate 3/4 Scheme— A^Experimental Throughput of Rate 1 Scheme ^• ^ Figure 4.2 Experimental Throughputs of rate 1/2, 3/4, and 1.  specific SNR area is between 8dB and 10.5dB. If 1.2 is selected as a threshold value and the current rate is 3/4, once the throughput reaches 1.2 it switches to rate 1. This takes place at approximately 8dB where the throughput of a rate 3/4 system is 1.2 but the throughput of a rate 1 system is 0.85. As a result the adaptive scheme constantly switches between rate 1 and rate 3/4 within this region and maximum throughput is not obtained. The expected result is to obtain an average between the throughput curves of rate 3/4 and rate 1 in this region.  Section 4.4 Performance Evaluation Recall that the goal of the Adaptive CPC SW Type II ARQ protocol is to increase Section 4^  57  Chapter 4  or equal the throughput at all SNR levels as compared to the rate 3/4 CPC SW Type II ARQ protocol. The prototype is tested over several SNR levels by executing the scheme until 1000 frames are successfully delivered. Figure 4.3 displays the resulting Adaptive CPC SW Type II ARQ throughput in an AWGN channel. As expected, the throughput has increased at all SNR levels excluding the area between 7dB and 10dB. The slight degradation in this area was predicted and is a factor of the selection of THRESHOLD VALUE 2. It is observed that the throughput curve has a stair case shape. This is due  to rate 1/2 being utilized at low SNR levels, rate 3/4 at medium SNR levels, and rate 1 at high SNR levels. The results in Figure 4.3 clearly validates the operation of the adaptive scheme. CPC SW Type II ARQ Scheme in AWGN 1.6 1.5 1.4 1.3 1.2  Ir-  1.1 1 -c to 0.9 z 0 0.8 E-1^0.7  •  0.6 0.5 0.4 0.3 0.2 0.1 00  2^4^6^8^10  Es/No [dB]  12  ^ ^ 16 14  Experimental Throughput of Adaptive Rate Scheme Experimental Throughput of Rate 3/4 Scheme^AFigure 4.3 Adaptive CPC SW Type II ARQ Throughput. Section 4^  58  • Chapter 4  Figure 4.4 displays the adaptive scheme's throughput for various values of N. N is a performance parameter which adjusts how quickly the scheme reacts to changes in the channel conditions. It is observed that changing the value of N between 5 and 15 (i.e., approximately 5000 to 15000 bits) has marginal effect on the performance of the scheme in an AWGN channel. This can be accounted to the fact that an AWGN channel's SNR level is constant for all practical purposes as compared to the instantaneous SNR level of the Rayleigh fading channel which fluctuates according to a rayleigh distribution. Changing the value of N for the combined AWGN and Rayleigh channel is expected to affect throughput performance. CPC SW Type II ARQ Scheme in AWGN 1.6 1.5 1.4 1.3 1.2 1.1 1 • (on  O  0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0  0^2^4^6^8^10  Es/No [dB]  12  ^  14  Experimental Throughput of Rate Adaptive Scheme with N=5 Experimental Throughput of Rate Adaptive Scheme with N=10 Experimental Throughput of Rate Adaptive Scheme with N=15  16  •^  Figure 4.4 Affect of varying N for the Adaptive Scheme's Throughput. Section 4  59  Chapter 4  Figure 4.5 illustrates the Adaptive CPC SW Type II ARQ scheme in a combined AWGN and Rayleigh fading channel for a BDT product of 0.00084. The value for N is 5 and the threshold values chosen are 0.76 and 1.19. The threshold values are slightly lower than those used in the AWGN channel as the fading channel is a very harsh environment and it is more difficult to reach and maintain the threshold values. For comparison purposes, the experimental throughput for the rate 3/4 CPC SW Type II ARQ is also plotted. As in the AWGN channel, the throughput is increased at lower SNR levels, Adaptive CPC SW Type II ARQ Scheme in Rayleigh Fading 1.4 1.3  •  1.2 1.1  •  1 0.9 to  •  •  0.8  •  0.7 F-4  •  0.6 0.5  •  0.4 0.3 0.2 0.1  ^  5  10^15^20  Es/No [dB]  ^ ^ 25 30  Experimental Throughput for Adaptive N-5 Rate 3/4 Experimental Throughput for BT=0.00084  •  Figure 4.5 Adaptive CPC SW Type II ARQ in Rayleigh Channel.  degraded at medium SNR levels, and increased at high SNR levels. Again the stair case Section 4^  60  Chapter 4  shape is evident. As in the AWGN channel, it is a result of the rate 1/2 code being used at low SNR levels, rate 3/4 at medium SNR levels, and rate 1 at high SNR levels. Figure 4.6 depicts the remaining  BDT  product curves for the adaptive scheme. It  is observed that the slower the vehicle speed (i.e., the smaller the  BDT  product) the  quicker the maximum throughput is reached at the higher SNR values. This is a very important observation which implies that the set of code rates used must be optimized to the set of BDT products representing the average vehicle speeds and transmission rate used. The three  BDT  products of 0.0043, 0.0022, and 0.00084 correspond to a 7r/4 shift  DQPSK system operating with a carrier frequency of 900MHz, a baud rate of 19.2kHz, and vehicle velocities of 100, 50, and 20 km/hr respectively. It is observed that the code rates of 1/2, 3/4 and 1 results in a relatively good throughput for the 20km/hr case as compared to the non-adaptive scheme. The same cannot be said about the remaining two speeds of 100 and 50km/hr which will eventually reach the maximum throughput but at a higher SNR level. This implies that a different set of code rates is required to give better performance. The random phase modulation caused by the increase in vehicle speed cannot be overcome by the Rate 1 code (uncoded). It requires higher SNR values to successfully deliver the frame as opposed to the 20km/hr case. In other words, a more powerful code than Rate 1 but weaker than 3/4 is required. Figure 4.7 shows the effect of varying the value of N which changes the amount of time it requires for the adaptive scheme to react to channel conditions. When larger values of N are chosen, which indicates the adaptive scheme will take longer before reacting to the channel conditions, the performance degrades. This is due to the time varying characteristic of the Rayleigh channel. By selecting a smaller value of N, the Section 4^  61  Chapter 4  scheme can quickly adapt and maximize its throughput as opposed to a larger value of N which makes the scheme more lethargic. In other words, the smaller the value of N, the more successfully the adaptive scheme can track the channel conditions.  Adaptive CPC SW Type II ARQ Scheme in Rayleigh Fading  ^IR  •• 1  1^  •  0.9 taA  0.8 0.7 a  0.6 0.5 0.4 0.3 0.2 0.1 5  ^  10^15^20 Es/No [dB]  ^ ^ 25 30  Experimental Throughput for Adaptive N=5 Experimental Throughput for Adaptive N=5, BT= 0.0043 Experimental Throughput for Adaptive N=5, BT= 0.0022 Experimental Throughput for BT=0.00084 Experimental Throughput for BT= 0.0022 Experimental Throughput for BT= 0.0043  •  • •  Figure 4.6 Adaptive CPC SW Type II ARQ in a Rayleigh Channel for Various BDT Products.  Section 4^  62  ^  Chapter 4 Adaptive CPC SW Type II ARQ Scheme in Rayleigh Fading  0.9 0.7 0.6 0.5 0.4 0.3 0.2 0.1 5^10^15^20 Es/No 1cIB1  25  ^  30  Adaptive BT= 0.0043, N=15 Adaptive BT= 0.0043, N=5 ^0 Adaptive BT= 0.0022, N=15 Adaptive BT= 0.0022, N=5^&Adaptive BT=0.00084, N=15 ^ Adaptive BT=0.00084, N=10 ^ Adaptive BT=0.00084, N=5 ^ Figure 4.7 Effect of varying N for the Adaptive Scheme in a Fading channel.  Section 4.5 SW ARO Scheme Comparisons The three CPC SW Type II ARQ schemes implemented are listed below and ranked according to throughput performance. 1. Adaptive CPC SW Type II ARQ Scheme 2. Rate 3/4 CPC SW Type II ARQ Scheme with Code Combining 3. Rate 3/4 CPC SW Type II ARQ Scheme Section 5^  63  Chapter 4  All three schemes are based on the CPC SW Type II ARQ protocol and utilize the identical general DSP software library. The performance of the rate 3/4 scheme was verified by the use of numerical results. The rate 3/4 code combining case resulted in an increase at low SNR levels. In code combining, repeated copies of the identical coded data sequences are optimally combined for subsequent decoding. This upgrade consisted of replacing 10 lines of DSP Assembly code. It does not require any additional memory because the receiver stores the combined data sequence and discards the most recent single copy (i.e. the most recent corrupted data sequence is combined with the previous copies of identical coded data sequences from a certain memory slot and then stored in that same memory slot). In order to obtain a greater increase in throughput over a larger region of SNR levels, the adaptive scheme was implemented. In comparison to the rate 3/4 scheme, the adaptive scheme's throughput increased for low and high SNR levels and decreased for medium SNR levels. As discussed above, the slight degradation ( less than 1 dB) in the medium range is the result of the threshold value and the shapes of the individual rate throughput curves. The compromise of a slight degradation is well worth the gain in performance at lower and higher SNR values. It was also observed that the adaptive scheme's performance varied as a result of the system's which implies using a set of codes that are optimized for a set of  BDT  BDT  product  products. The  actual adaptive upgrade consisted of adding case statements in DSP Assembly code to account for the various code rates. The threshold values and selection of the coding rate was added to the Host PC protocol program. The only other modification was to utilize 2 of the 9 Reserved bits of the header to indicate the rate of the data packet.  Section 5^  64  Chapter 4  Section 4.6 Conclusions An Adaptive rate CPC SW Type II ARQ scheme was implemented using the existing prototype of Chapter 3 with software modifications. The goal was to utilize the existing general software modules in order to minimize any cost associated with the upgrade. The Adaptive coding rate algorithm was presented and explained. The throughput of the adaptive prototype was experimentally measured for both an AWGN channel and combined AWGN and Rayleigh fading channel. In both channels, the experimental throughput showed a general increase in performance. More specifically, the adaptive scheme's throughput increased for low and high SNR levels and decreased for medium SNR levels in comparison to the rate 3/4 scheme. The compromise of a slight degradation is well worth the gain in performance at lower and higher SNR values. The effect of varying N, which controls the reaction time of the adaptive scheme, was also investigated. It was found that the value of N had marginal affect on the throughput in an AWGN channel. In a combined AWGN and Rayleigh fading channel, as N is decreased the throughput performance increases. The Rayleigh channel is time varying and the smaller the value of N, the more successfully the adaptive coding rate can track the channel conditions. The experimental results indicate that the upgrade of the CPC SW Type II ARQ protocol to an adaptive scheme was successful.  Section 6^  65  Chapter 5  Chapter 5 Conclusions and Future Research Section 5.1 Conclusions This thesis investigated the design, implementation issues, and performance evaluation of various adaptive and non-adaptive FEC coding schemes of a Type II SW ARQ system. The research contributions can be summarized as follows: 1. The Software design, implementation, and test of a Digital Signal Processing (DSP) Module Library for the Spectrum TMS32C30 DSP card housed in an IBM PC platform. The library consists of the following modules: •  CRC Encoder/Decoder  •  Rate 1/2 Convolutional Encoder  •  Puncturing Module  •  Rate 1/2 Soft Decision Viterbi Decoder  •  Block Interleaver  •  Soft Data Deinterleaver  •  Queueing Module  •  7r/4 shift DQPSK Baseband Transmitter/Receiver  2. The Software implementation and evaluation of a Complementary Punctured Convolutional (CPC) coding scheme for the SW Type II ARQ system with and without code combining utilizing the DSP library in an AWGN channel and a combined AWGN and Rayleigh Fading channel. 66  Chapter 5  3. Software upgrade and performance evaluation of an Adaptive CPC SW Type II ARQ scheme utilizing the DSP library in an AWGN channel and a combined AWGN and Rayleigh Fading channel. In this thesis a general algorithm for Complementary Punctured Convolutional Coding applied to a Stop-and-Wait ARQ scheme was presented. A rate 3/4 CPC SW Type II ARQ protocol was implemented with the use of two Spectrum TM5320C30 DSP cards and a host IBM PC. The following assumptions or simplifications are incorporated in the implemented prototype which consists of the DSP transmitter and receiver cards in the same Host PC under the control of the SW ARQ protocol. •  As a consequence of the transmitter and receiver DSP cards being in the same Host PC, they are initialized and synchronized by the ARQ Protocol running on the Host PC. In practice, there is an initialization and synchronization process to be executed by the independent transmitter and receiver.  •  In practice a noisy return channel is used to send the receiver's reply. In the prototype, the receiver's reply is passed internally through the PC via the DAM. This is a noise free return channel.  •  As a result of the ARQ protocol controlling both the transmitter and receiver, it is the receiver which times out if a flag is not found. Again, in practice it is the transmitter that times out if it does not get a response from the receiver.  •  Symbol Synchronization is accomplished by hard wiring the transmitter and receiver. The actual symbol timing signal is software generated and is not ideal. A practical system would have the receiver utilize a Phase Locked Loop or some other synchronization circuit to obtain symbol synchronization with no link to the transmitter.  Section 1^  67  Chapter 5  These simplifications do not compromise the accuracy of the experimental results. The prototype is used to evaluate various FEC strategies which are unaffected by the above simplifications. The rate 3/4 CPC SW Type II ARQ scheme was numerically analyzed for both an AWGN channel and a combined AWGN and Rayleigh fading channel. The experimental data obtained from the prototype was in good agreement with the numerical results validating the implementation and correct operation of the scheme. The rate 3/4 CPC SW Type II ARQ scheme was upgraded with Code Combining in an effort to gain an increase in the throughput performance. This allows the receiver to optimally combine copies of the same coded sequence for subsequent decoding. The experimental throughput performance increased at low SNR levels as compared to the non-code combining case verifying its proper operation. The upgrade consisted of replacing 10 lines of DSP Assembly Language. The memory requirement remains constant since one data sequence, which consists of the combined copies, is kept rather than the individual copies. In an effort to further increase the throughput performance of the prototype, the CPC SW Type II ARQ protocol was upgraded with an Adaptive Coding Rate. The resulting experimental throughput showed an increase at low and high SNR levels and a slight degradation at medium SNR levels with respect to the throughput of the original rate 3/4 prototype. The compromise of a slight degradation is well worth the gain in performance at lower and higher SNR values. This degradation is due to the selection of threshold values used in the adaptive coding rate algorithm. The three implemented schemes behaved as expected and their experimental throughSection 1^  68  Chapter 5  puts verified their correct operation.  Section 5.2 Future Research  5.2.1 Symbol Synchronization The 7r/4 shift DQPSK modulation system used by the prototypes suffers from imperfect symbol synchronization. As a result, the throughputs of the prototypes are degraded at lower SNR levels. It would be interesting to further investigate the symbol synchronization of the system.  5.2.2 Selective Repeat Upgrade Although a Stop-and-Wait ARQ protocol was used for the prototypes, the software modules and the design of the system were such that an upgrade to a Selective Repeat (SR) Protocol is possible. It would be interesting to have the prototypes upgraded to SR as this would only require software modifications but the majority of DSP library modules do not have to be modified.  5.2.3 Adaptive Header The implemented adaptive scheme varied the coding rate of the data packet while the coding rate of the header remained constant (rate 1/2). If the coding rate of the header is also made adaptive the throughput will increase. At high SNR levels, a powerful code is not required and a larger data packet can be sent resulting in greater throughput. At lower SNR levels, a more powerful coded header will deliver the data packet and reduce the number of retransmissions for header failures. The coding rate for the header should always be more powerful than the coding rate of the data packet. In order to indicate the rate of the header, a miniature header should proceed the header. Section 2^  69  Chapter 5  5.2.4 FEC Schemes With the existing testbed used for the prototypes and the modular structure of the DSP library software, this leads to endless possible FEC schemes that may be investigated and explored.  Section 2^  70  Bibliography [1] S. Lin and J. D. J. Costello, Error Control Coding: Fundamentals and Applications. Prentice Hall, 1983. [2] J. Hagenauer, "Rate-compatible punctured convolutional codes (RCPC codes) and their applications," IEEE Trans. Commun., vol. 36, pp. 389-400, Apr. 1988. [3] S. Kallel, "Analysis of a type II hybrid ARQ scheme with code combining," IEEE Trans. Commun., vol. 38, pp. 1133-1137, Aug. 1990. [4] K. J. Guth and T. T. Ha, "An adaptive stop-and-wait ARQ strategy for mobile data communications," in the Proceedings of IEEE the 40th Vehicular Technology Conference, pp. 656-661, Apr. 1990. [5] D. P. C. Wong and P. T. Mathiopoulos, "Nonredundant error correction analysis and evaluation of differentially detected 7/4-shift DQPSK systems in a combined CCI and AWGN Environment," IEEE Trans. Veh. Tech., vol. 41, pp. 35-48, Feb. 1992. [6] C. L. Liu and K. Feher, "Noncoherent detection of 7/4-QPSK systems in a CCIAWGN combined environment," in the Proceedings of the 39th Vehicular Technology Conference, pp. 83-94, May 1989. [7] D. P. Bouras, "Optimal decoding of PSK and QAM signals in frequency nonselective fading channels," Master's thesis, University of British Columbia, 1991. [8] E. Casas and C. S. K. Leung, "A simple digital fading simulator for mobile radio," IEEE Trans. Veh. Tech., vol. 39, pp. 205-212, Aug. 1990. [9] J. G. Proakis, Digital Communications. New York:McGraw-Hill Book Company, 2 ed., 1989. [10] C. L. Liu and K. Feher, "Performance of Non-coherent 7/4-QPSK in a frequencyselective fast Rayleigh fading channel," in the Proceedings of SUPERCOM/ICC 90, Atlanta GA, pp. 335.7.1-335.7.5, Apr. 1990. [11] S. Kallel, "Complementary Punctured Convolutional (CPC) Codes and their use in hybrid ARQ schemes," in the Proceedings of IEEE Pacific Rim Conference, pp. 186-189, May 1993. [12] S. Kallel and D. Haccoun, "Generalized type II hybrid ARQ scheme using punctured convolutional coding," IEEE Trans. Commun., vol. 38, pp. 1938-1946, Nov. 1990. 71  [13] G. Begin and D. Haccoun, "High rate punctured convolutional codes: structure properties and construction techniques," IEEE Trans. Commun., vol. 37, pp. 1381— 1385, Dec. 1989. [14] J. A. Heller and I. M. Jacobs, "Viterbi decoding for Sattelite and space communication," IEEE Trans. Commun., vol. 19, pp. 835-848, Oct. 1971. [15] A. J. Viterbi, "Convolutional Codes and Their Performance in Communication Systems," IEEE Trans. Commun., vol. 19, pp. 751-772, Oct. 1971. [16] J. G. Proakis, "Probabilities of Error for Adaptive Reception of M-Phase Signals," IEEE Trans. Commun., vol. 16, pp. 71-80, Feb. 1968. [17] P. F. Driessen, "Performance of frame synchronization in packet transmission using bit erasure information," IEEE Trans. Commun., vol. 39, pp. 567-573, Apr. 1991. [18] T. Matsumoto and F. Adachi, "BER analysis of convolutional coded DQPSK in digital mobile radio," IEEE Trans. Veh. Tech., vol. 40, pp. 435-442, May 1991. [19] D. Chase, "Code Combining- a maximum-likelihood decoding approach for combining an arbitrary number of noisy packets," IEEE Trans. Commun., vol. 33, pp. 385— 393, May 1985. [20] J. Hagenauer, "Forward Error Correction coding for fading Compensation in Mobile Sattelite Channels," IEEE Journal Select. Areas Commun., vol. 5, pp. 215-225, Feb. 1987. [21] N. R. Sollenberger, J. C. I. Chuang et al., "Architecture and implementation of an efficient and Robust TDMA frame structure for digital portable communications," IEEE Veh. Trans., vol. 40, pp. 250-260, Feb. 1991. [22] J. B. Cain, G. C. Clark Jr., and J. M. Geist, "Punctured Convolutional codes of Rate (n-1)/n and simplified maximum likelihood decoding," IEEE Trans. Inf. Theory, vol. 25, pp. 97-100, Jan. 1979. [23] J. C. I. Chuang, "Comparison of two ARQ protocols in a Rayleigh fading channel," IEEE Veh. Trans., vol. 39, pp. 367-373, Nov. 1990. [24] C. S. K. Leung and A. Lam, "Forward error correction for an ARQ scheme," IEEE Trans. Commun., vol. 29, pp. 1514-1519, Nov. 1981. [25] R. W. Lucky, J. Salz, and E. J. Weldon, Jr., Principles of Data Communication. McGraw-Hill Book Company, 1968. 72  [26] W. C. Lindsey and M. K. Simon, Telecommunication Systems Engineering. PrenticeHall Inc., 1973. [27] P. Bylanski and D. G. W. Ingram, Digital Transmission Systems. Peter Peregrinus Ltd., 1976. [28] K. Feher, Digital Communications: Satellite/Earth Station Engineering. Prentice Hall Inc., 1983. [29] K. Feher, Digital Communications: Microwave Applications. Prentice Hall, 1981. [30] A. M. Michelson and A. H. Levesque, Error-Control Techniques for Digital Communications. John Wiley & Sons, 1985. [31] S. Haykin, An Introduction to Analog and Digital Communications. John Wiley & Sons, 1989. [32] K. Feher and Engineers of Hewlett Packard Ltd., Telecommunication Measurements, Analysis, and Instrumentation. Prentice Hall, 1987. [33] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing. Prentice Hall, 1989.  73  Appendix A Software Listings The software listings appear in the following order: CSUB.0 — DSP Module Library. ADAPT.0 — Adaptive SW Type II ARQ Protocol for IBM Host PC. •  XMITADAP.ASM — DSP Assembly code for Transmitter DSP card.  •  RCVRADAP.ASM — DSP Assembly code for Receiver DSP card.  •  VARSRCVR.ASM — Variables, definitions, and memory locations used by the assembly code for the transmitter and receiver DSP Cards.  74  Oct 6 1993 14:18:30^CSUB.0^Page 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56  Oct 6 1993 14:18:30^CSUB.0^Page 2  #include <stdlib.h> #include <stdio.h> #include <math.h> main()  57 58  /*******************************************************************  62 63 64  59 60 61  ******  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * make * y X°K  er &  polydiv^v1.02^Feb 93 This module implements a linear feedback shift register for polynomial division.^It is used for CRC calculation and the decoding of convolved data chunks. This module requires 5 parameters: K^- constraint length valid up to 33 decimal MESGDATA^- pointer to message or data (dividend) POLY^- polynomial to be divisor TOTAL^- length of dividend in 32 bit words RESULT^- pointer where quotient is to be stored The resulting LFSR will be: I^>x0^I^>xl^I^>x2-^>x(K^1)-^I^> where the connections are determined by POLY. NOTE:^POLY is read from right to left ie 1+x+x'4^---->^10011 . POLY RESULT POLY^I^MESGDATA^REMAINDER  65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85  The data is feed into the LFSR msb first and lab last ie address^data 300^25a4e845 301^84fe68dc "548e4a52cd86ef48"  ^LFSR  Decoder Notes: 1>^Give all 5 parameters and use quotient stored at *RESULT.^Remainder can be discarded. CRC Notes: 1>^If calculating the CRC it is your responsibility to sure the data is premultiplied (padded with zeros) b 2>^The REMAINDER is the CRC value indexl^  -general variable used as loop count  86 87 88 39 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106  *^ current 32 bit word *^index2^ -current bit position in 32 bit word (0-31) *^infobit^ -input bit to LFSR *^outputbit -output bit from LFSR *^ sshift^ -amount to shift LFSR to get output bit *^shreg^ -contents of LFSR *^feedback^ -feeback value for LFSR *^connections^-bits representing connections of LF SR *^temp^ -temp storage of outputs of LFSR *^remainder^-remainder of polynomial division ******************************************************************** *******/  long unsigned polydiv(int K, long int *MESGDATA,^long unsigned int P OLY, int TOTAL,^long int *RESULT) 1  der;  t.  se ns*/  int index?,^index2,^infobit,^outputbit,^shift; long unsigned int shreg, ^feedback, connections, ^temp,^remain  shift.0; temp.0; shreg^0; connections =0; /*The standard used is to read polynomials from right to lef This module needs them in left to right format so we rever the bits of POLY^ie 0010 --> 0100. The following code reverse POLY and stores it in connectio for^(index?^K-1;^index? > 0;^index?--) if^(^((POLY)^&^(1 «^index?^-1))^:=^0) connections^I. 1^( K-1 - index?^); )^/* end of reversal routine */  ter */  /*This section of code determines the amount to shift the register by.^This is needed because if the constraint length is,^for example,^7 but we only use the first two registers^(ie POLY^0000011)^then we must shift the register by 5 positions to get the output of the 2nd regis for^(index?^K;^indexl >. 0;^index?--) if^(^(POLY &^(1«^(index1-1))) ^!=0) shift.(K-indexl);  Oct 6 1993 14:18:30^CSUB.0^Page 3 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141  index1=-1; }/* end of finding shift amount */ if^(K==33)^  t CRC/  /*exceptional case with 32bi  shift=0;^ /*and we don't require a shi  ft^*/  outputbit = 0; /*This next section implements the LFSR and feeds the entire encoded message through it. ^The msb of the polynomial/mes  sage  is feed into the LFSR first. ie encoded message is "F78jNd" ^dNj87F---->LFSR  *7  for^(indexl = TOTAL -1;^indexl >=0;^indexl--) for^(index2 = 31;^index2^>= 0;^index2--)  1=^0  /*lets get bit to input into LFSR */ infobit=0; if^(^(*(MESGDATA + indexl^)^&^(1 « index2)) )  infobit =1; /* if output=1 then feed it back */ if^(outputbit^== 1) feedback . Oxffffffff & connections; else feedback = 0; shreg = feedback^((infobit « K - 2)^I^shr  eg»1);  outputbit=(^shreg>>^(shift)^)^& 1;  with the */  /* this shift register SHREG is implemented /* lsb being the msb of the shift register  Oct 6 1993 14:18:30^CSUB.0^Page 4 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192  142  /*^cab^ lsb  143  /*^ie^.^r4 r3 r2 rl r0  193 194 195 196  /*^x0 xl x2 x3 x4 c--- powers o  197  if^(index2^==^0)  198 199 200 201  144 145 146 147 148 149 150 151 152 153 154 155  f poly  */  remainder = shreg; *( RESULT + indexl ) ^. temp; temp = outputbit cc 31; else  (temp)^I= outputbit cc^(index2^- 1);  202 203 204 205 206  }  /*END = return(remainder);  #define K^((Int^*)0x809c00) #define POLY1^((Int^*)0x809c01) #define POLY2^((Int^*)0x809c02) /******************************************************************* ***** * CONV^V1.02^Feb 93  * * OLY1 * OLY2 * *  This module implements a convolutional encoder of rate 1/2 with variable length K and generator polynomials POLY1 and POLY2. This module requires 5 parameters: *MESG^- pointer to data to be convolved *MESGP1^- pointer to convolved data as a result of P *MESGF2^- pointer to convolved data as a result of P SIZE^- # of 32 bit words to convolve ^> POLY 1  P1  I^1^I^2^  * * he *  ma  Is  POLY 2 ^>  bits  I^K^I P2  bits  The encoder is implemented by polynomial multiplication of t data and POLY1 and POLY2 polynomials respectively. This is achieved by shifting and exclusive ORing. Notes: 1> When using cony be sure to have a storage area with K ext bits so that none of the convovled data bits are lost. ie 16 bits of data K =4 ^ > requires 20 hi of storage spa  ce  vmesg[]^- vector containing data to be convolved vmesgPl[]^- vector containing convolved data from POLY 2  vmesgP2[]^- vector containing convovled data from POLY temp[]^indexl^index2^index3^-  intermediate general loop general loop general loop  storage vector index index index  Oct 6 1993 14:18:30^CSUB.0^Page 5 207  208 209  * *  210 211 212 213 214  * *  215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247  248 249 250 251  252 253 254 255 256 257  in  firstbit^- firstbit of current 32 bit word lastbit^- 32nd bit of current 32 bit word mask^- used to select which term of POLYx is used multiplication byte^-intermediate storage variable  * RETURNS^- nothing .................................................................... / void conv(^long unsigned int *MESG, ^long unsigned int *MESGP1, long unsigned int *MESGP2,^int SIZE) ( [33];  */ */  long unsigned int^temp[33],^vmesg1331, ^vmesgP1[33],^vmesgP2 int indexl,^index2,^index3,^firstbit,^lastbit,^mask; long byte; /* get message into vector for processing */ for^(indexl . 0;^indexl < SIZE;^indexl++) { vmesg[indexl)^. *(MESG + indexl); temp[index1].0; vmesgPl[index1].0; vmesgP2[indexl]=0; } /* convolution using polynomial multiplication of POLY1 and /* POLY2.^Implemented by shifting and XOR vextors. mask . 11; for(indexl^= 0;^indexl < *K;^indexl++) ( firstbit^. 0; lastbit .^0;  .7 .7 .7  /* shifting routine which shifts entire contents of /* vector.^Note that shifting does occur across /* element boundaries. for(index2^. 0;^index2 a SIZE;^index2++) { if^(indexl^==^0) { }  else {  temp[index2]=vmesg[index2];  byte = temp[index2]; lastbit.byte & 0x80000000; temp[index2].^(byte « 1)1^(firstbit if^(lastbit^!.^0)  Oct 6 1993 14:18:30^CSUB.0^Page 6 258 259 260 261 262 263 264  else  firstbit .^01; 1 }/*end of shifting^(polynomial multiplication)*/ ./  265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303  304  305 306 307 308 309 310  firstbit = 11;  or*/ */  /* add the terms of the polynomial multiplication to /* the appropriate vector according to their generat /* polnomials POLY1 and POLY2. if^((*POLY1 & mask)^!. 0) ( for(index3.0;^index3<SIZE;^index3++) vmesgPl[index3]^^=temp[index3]; ) if^((*POLY2^& mask)^!.^0) { for(index3.0;^index3<SIZE;^index3++) vmesgP2[index3]^^=temp[index3]; } mask . mask « 1; (7* end of adding up terms */ /* now place the convolved messages P1 and P2 in the Dual */ /* memory so that the PC host can retrieve it.^*/ for(indexl . 0;^indexl < SIZE;^indexl++) { *(MESG^+ indexl)^= vmesg[indexl]; *(ME5GP1 + indexl) ^= vmesgPl[indexl]; *(ME5GP2 + indexl)^. vmesgP2[indexl]; }  return; } /................................................................... ../ /* The parameters chosen are used in interleaving by 128 bit blocks which represent 128/2 . 64 SYMBOLS .7 #define RS*/ #define *define #define #define  ROW^  16^/* BLOCK INTERLEAVING PARAMETE  COLUMN^  16  BITS PER_SYMBOL^2 SYMB3L S_PER LINE^16^/*LINE . 32 BIT WORD*/ FLAG1^Ox0T)000003^/* FLAG1 MUST CORRESPOND TO  BITS PER SYMBOL  .7  /................................................................... interleaver^V1.00^Jan 93 This module will take the data given by pointer DEINT_ADDR  Oct 6 1993 14:18:30^CSUB.0^Page, 7 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358  and interleave it according to the parameters above and then place it starting at pointer INT_ADDR. This module is a block interleaver. eg Given: 8 symbols/line 4 bits/symbol  [^4 X 4]^Result: 12345678^159D^ 159D26AE 9ABCDEFO^26AE^ 378F4800 37BF 48C0  alculate rd.  The module uses the current row and column of the array to c the symbol to be placed in the resulting interleaved data wo  Oct 6 1993 14:18:30^CSUB.0^Page 8 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376  Once the symbol is known, the module calculates how much to increment the data pointer DEINT_ADDR, and how much to shift the FLAG1 . Next,^the module gets the symbol and stores it temporarily i n TEMP. When enough symbols have been obtained to write a 32 bit wor d, the module places the interleaved word (TEMP) at INT_ADDR an d increments the pointer.  377 378 379 380  Note: Regardless of the dimensions of the array the module w  386 387 388 389 390 391 392 393 394 395 396 397  ill ith ata.  always place the result in 32 bit lengths.^As shown above w the 4X4 array giving rise to 2 32 bit lines of interleaved d  INT ADDR^-pointer to interleaved data DEIRT_ ADDR^-pointer to deinterleaved data  t  cur_row^-current row cur_column^-current column addr^-amount to increment DEINT_ADDR pickbit^-bit amount to shift FLAG1 so that correct symbol is obtained shift^-bit amount to shift symbol before placing i in TEMP mod^-intermediate calculation used for pickbit symbol^-current symbol symbol_counter^-used to count symbols and write in 32 bit lengths  ******************************************************************** **********/ void interleaver(long int *DEINT_ADDR, ^long int *INT_ADDR)  381 382 383 384 385  398 399 400 401 402 403 404 405 406  { int cur row,^cur_column,^pickbit,^addr, mod,^shift=0; int symol=0; int symbol_counter=0; long unsigned int TEMP . 0; for(cur_row=1; cur_row<=ROW; cur_row++) {  ITS_PER_SYMBOL;  for(cur_column=0; cur_column<COLUMN; cur_column++) 1 symbol = cur_row + cur column * ROW; addr =^(symbol - 1)^/^-YMBOLS PER_LINE; mod . (symbol 8 SYMBOLS_PER_LYNE); if^(mod =0) pickbit .^(SYMBOLS_PER_LINE - 1)^* B else  L;  pickbit .^( mod - 1)^*BITS_PER_SYMBO  symbol_counter++; shift = pickbit -^(symbol_counter - 1)^* BIT  S_PER_SYMBOL;  shift = shift * /*The above line ensures the compiler compil  es the shift  as a LSH rather than an ASH^DO NOT REMOVE*/  « pickbit))«shift;  TEMP . TEMP I^(*(DEINT_ADDR + addr) & ^(FLAG1  /*if enough symbols for 32 bit word then write */ if (symbol_counter == SYMBOLS_PER_LINE) { *(INT ADDR++ )^. TEMP; symboi_counter=0; TEMP = 0; ) 1  } 1 /******************************************************************* ***/ int^RATES[8][6]^={ {1,^1,^0,^1,^1,^01,^/*import^value^"0" */ {0,^1,^1,^0,^1,^11,^/*import value^"1" */ {1,^0,^1,^1,^0,^11,^/*import^value^"2" */ {1,^1,^0,^1,^1,^01,^/*import value^"3" */ (0,^1,^0,^1,^0,^1),^/*import^value^"4" */ (1,^0,^1,^0,^1,^0),^/*import^value^"5" */ (1,^0,^1,^0,^1,^0),^/*import^6*/  Oct 6 1993 14:18:30^CSUB.0^Page 9 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464  {0,^1,^0,^1,^0,^1));^/*import^7*/ void puncture(int CHOSENRATE,^long int *NEW,^long int *OLD,^int TOTA L) { int^array[6]; unsigned long int mask=1; int^index,^value,^bits,^newbits=0; for^(index=0;^index<6;^index++) array[index]=RATES[CHOSENRATE][index]; for(bits=1;^bits<=TOTAL;^bits++) value= array( bits % 6]; if^(value==1)^  /*keep bit*/  if^(^(*OLD & mask)^> 0^) *NEW^I=^(^1 « newbits); newbits++;  465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482  /*^else if^(value>1)  483  for(index=0;^index<value;^index++) if^(^(*OLD & mask)^> 0^) *NEW I=^( 1 « newbits); newbits++; if^(newbits==32) newbits=0; NEW++; )^*/  Oct 6 1993 14:18:30^CSUB.0^Page 10  )  mask«=1; if(mask==0) OLD++; mask=1; ) if^(newbits==32) newbits=0; NEW++; } /******************************************************************* ***  484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515  combineheader^v1.02^Feb 93 * *^This module is used to combine the outputs of the adders of the *^convolutional encoder to form the header. ^The header will e ither *^be rate 1/2,^3/4 or 1/3. * */ void combineheader(long int *P1, ^long int *92,^long int *HEADER,^int NEWBITS) { int bits,^counter=0; unsigned long int templow=0; unsigned long int temphigh=0; unsigned long int mask=1; unsigned long int maskhigh=0x10000; /* NEWBITS must be halfed and rounded up since every word yo u give this module it automatically combines it into 2 words. ^S o if NEWBITS=64^the module changes it to 64/2=32 since it wor ks on the high^(16-31)^and low (0-15) bits simultaneously givin g rise to 2 bits for every one that NEWBITS counts. NEWBITS =^(NEWBITS/2)+^(NEwBITS%2); for^(bits=1;^bits<=NEWBITS;^bits++) /*^if^(^((*P1^& mask)^I^(*P2^& mask)<<l)^>^0^) templow 1= 1 « counter; if^(^((*P1 & maskhigh)^I^(*P2 & maskhigh)«1)^>0^) temphigh 1= 1 « counter; ^*/  templow^I=^(^(*Pl&mask)^I^(*P2&mask)«1^)«counter; (15-counter);  temphigh^1-=(^(*Pl&maskhigh)»1^I^(*P2&maskhigh)^)» counter +=1; mask«=1; maskhigh<<=1; if^(maskhigh==0) mask=1; maskhigh=0x10000; *HEADER++=templow; *HEADER++=temphigh; counter=0; templow=0; temphigh=0; Pl++;  CSUB.0^Page 11  Oct 6 1993 14:18:30 516  517 518 519  P2++;  522  if^(maskhigh^!=0) re not^*/ ( ivisable*/ *HEADER++=templow; maining */ *HEADER++=temphigh;  523 524  ) )  520 521  /* Finished in loop but if we we /* not given an amount of bits d /* by 32 then we must get the re /* bits that are combined.  Oct 6 1993 14:23:52^ADAPT.0^Page 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  #include^<stdlib.h> *include^<stdio.h> *include^<graphics.h> #include^<conio.h> #include^ "c:\lib\tms30.h "  54 55 56 57 58 59 60  #define CONTROL WORD^(0X30008) #define VIRGIN HEADER^(0x30010) #define VIRGIN_DATA^(0x30013)  61 62 63 64 65 66 67 68 69 70 71 72  #define ACKO^(0x3007b) #define STROBE_RCVR^(0x3007c) #define STROBE HOST ^(0x3007d) #define FLAGOPT^(0x30000) #define MENU OPTION^(0x30006) #define NOT _READY^01 #define READY^11 #define TROUBLE^(0x30130) #define RUN^Offffl /..............................*****.........*******......******.... ..*. .^ADAPT.0^SEPT 1993 Adaptive Complementary Punctured Convolutional Coding Scheme for a *^Conventional Type II Stop and Wait ARQ System. Using rate 1,^3/4,^and 1/2 codes derived from a rate 1/2 mother code. See DSP software for actual perforation matrix and generator polynomials. *^Frame Structure: its  8 bit preamble + 24 bit flag^  .^AA^294153 . * CONVOLVED RATE 1/2 HEADER^ its  32 b  128 b  *^address^I^Na^I^Hr^I^length^I *^14^4^4^10 ^ >32 bits P1 or P2^I^CSI^I^Reservedl^CRC^I^Tail^I 2^2^7^16^5 ^ >32 bits * CONVOLVED DATA^ bits ---bits  Oct 6 1993 14:23:52^ADAPT.0^Page 2  864  1024  * UNCONVOLVED DATA - for use with rate 3/4 punctured from a rate 1/2  73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110  . *^Data^I^CRC^I^Tail^I *^3/4^635^32^5 *^1^859 *^1/2^411 . ...*..............**..........********...........*****..........***** ..../ struct^window (  int int int int };  left; right; top; bottom;  void main(void) { FILE *fp; int header[4],^transmit[64],^rovr[64],frame[1000],output[20] int menu,^rate,^packet,^control,^midx, midy,^locx,^boy; float ber2, value; int indexl; char beep = 7; unsigned long int current,^index2; unsigned int temp,berword; unsigned long int ber,symbols, oldber; int ack,^nack,^trans,^oldtrans,^oldnackr0; int CPC1,^CPC2,^CPC1CPC2; int headfail,^crcfail,^lost,^tot; int^noldtrans,^N; float^noldinfobits,^ninfo,^rat,^blockn=0; int errorcode; short errormsg; long int STRT,^temps,response; struct window rcv, ^xmit,^stat;  2;  int^address,^Hr,^Na,^length,^PlorP2,^CSI; int successframe, headllow, headlhigh, head2low, head2high; float^infobits,^totalbits,^infoconstant,^Current_factor=1.  /*graphics variables*/ int gdriver=DETECT, gmode,bkco1=DARKGRAY,maxx, maxy; char msg[120]; for^(index1=0;^indexl<1000;^indexl++) frame[index1]=0;  /*Initialize graphics screen*/ initgraph(&gdriver,^&gmode, errorcode . graphresult();  Oct 6 1993 14:23:52^ADAPT.0^Page 3 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168  e));  if^(errorcode^!= grOk) f printf("graphics error:%s\n", ^grapherrormsg(errorcod printf("Press any key to halt:"); getch(); exit(1); } cleardevice(); setbkcolor(bkcol); maxx=getmaxx()-2; maxy=getmaxy(); midx = maxx/2; midy . maxy/2; setlinestyle(SOLID_LINE,^1,^THICK_WIDTH); rectangle(0,^0,^maxx,^maxy*.15); rectangle(0,^maxy*.15,^maxx*.5,^maxy*.5); rectangle(maxx*.5,^maxy*.15,^maxx,^maxY*.5); rectangle(0,^maxy*.5,^maxx,^maxy); setlinestyle(SOLID LINE,^1, NORM_WIDTH); sprintf(msg,^"STATUS WINDOW"); outtextxy(10,^maxy*.5+5,^msg); rcv.top =^.24*maxy; rcv.bottom =^.48*maxy; rcv.left^=^.83*maxx; rcv.right =^.99*maxx; xmit.top =^.24*maxy; xmit.bottom =^.48*maxy; xmit.left^=^.33*maxx; xmit.right .^.48*maxx; stat.top = maxy*.56; stat.bottom = maxy*.6; stat.left^=^10; stat.right^. maxx*.98;  /* Set Text and Headings for the display screen ^*/ settextjustify(CENTER_TEXT,^TOP_TEXT); sprintf(msg,^"Statistics Module for:"); outtextxy(midx,^15,^meg); sprintf(msg,^"Adaptive Complementary Punctured Convolutional Stop and Wait Type II ARQ scheme"); outtextxy(midx,^25,^meg); sprintf(msg,^"PI74 DQPSK Modulation Scheme"); outtextxy(midx,^35,^meg); sprintf(msg,^No Code Combining"); setcolor(RED); outtextxy(midx,^45,^meg); setcolor(WHITE); sprintf(msg,^"Transmitter DSP Board 0x390"); outtextxy(maxx/4,^85,^msg); settextjustify(LEFT_TEXT, ^TOP_TEXT); sprintf(msg,^"Total Frames sent:"); outtextxy(10,^115,^msg); sprintf(msg,^"Baud Rate"); outtextxy(10,^125,^nag); sprintf(msg,^"# of ACKs arrived:");  Oct 6 1993 14:23:52^ADAPT.0^Page 4 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228  outtextxy(10,^135,^msg); sprintf(msg,^"# of NACKs arrived:"); outtextxy(10,^145,^meg); sprintf(msg,^"Current Frame #^(of 1000):"); outtextxy(10,^155,^msg); sprintf(msg,^"Current Rate:"); outtextxy(10,^165,^msg); settextjustify(CENTER_TEXT, TOP TEXT); sprintf(msg,^"Receiver DSP Board 0x290"); outtextxy(maxx*.75, ^85,^msg); settextjustify(LEFT_TEXT,^TOP_TEXT); sprintf(msg,^"Error Free Rcvd Farmes:"); outtextxy(midx+10,^115,^meg); sprintf(msg,^"8 of lost Frames:"); outtextxy(midx+10,^125,^meg): sprintf(msg,^"# of error Frames:"); outtextxy(midx+10,^135,^meg); sprintf(msg,^"Throughput:"); outtextxy(midx+10,^145,^meg); sprintf(msg,^"Total ACKs"); outtextxy(10,^maxy*.5+20,^msg); sprintf(msg,^"CPC Code 1"); outtextxy(210,^maxy*.5+20,^msg); sprintf(msg,^"CPC Code 2"); outtextxy(360,^maxy*.5+20,^meg); sprintf(msg,^"CPC 1 & CPC 2"); outtextxy(510,^maxy*.5+20,^msg); sprintf(msg,^"Total NACKs"); outtextxy(10,^maxy*.5+50, ^nag); sprintf(msg,^"Header Failure"); outtextxy(210,^maxy*.5+50,^nag); sprintf(msg,^"Data CRC Failure"); outtextxy(360,^maxy*.5+50,^nag); sprintf(msg,^"Lost Frame"); outtextxy(510,^maxy*.5+50,^msg); /*End of text set up */ errorcode=SelectBoard(0x290); if^( errorcode == 0^) printerror(1); errorcode=LoadObjectFile("RCVRADAP.OUT"); if^(errorcode^!=^0) printerror(2); Reset(); setcolor(RED); settextjustify(CENTER_TEXT,^TOP_TEXT); sprintf(msg,^"Loaded and running..."); outtextxy(maxx*.75,^95,^meg); for(index1=0;^indexl<3000;^indexl++); errorcode=SelectBoard(0x390); if^(^errorcode == 0^) printerror(3);  Oct 6 1993 14:23:52^ADAPT.0^Page 5 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271  errorcode=LoadObjectFile("xmitadap.out"); if^(^errorcode^!.^0^) printerror(4); Reset(); sprintf(msg,^"Loaded and running..."); outtextxy(maxx/4,^95,^msg); settextjustify(LEFT_TEXT, TOP_TEXT); setcolor(WHITE); N=0; rat.0.0; noldtrans.0; noldinfobits.0.0; ninfo.0.0; blockn.0.0; oldtrans.0; trans.0; ack =0; CPC1.0; CPC2.0; CPC1CPC2.0; nack=0; headfail=0; crcfail=0; infobits=0.0; totalbits.0.0; infoconstant.0.0; tot.0; successframe.0; bar =^0; oldber=0; nack .0; lost=0; locy=0; locx.10; current . 01; response .01; Put32Bit(ACKO,^DUAL,^69691); ****/  272 273 274 275 276 277 278 279 280 281 282 283 284 285  e^*/  */  /*******************************.**..***********************  /*^Initialize Header variables*/ address = Ox1000;^ Ns .^0; Hr .^0; length . 608;^ PlorP2^. 1;^  /* full frame */ /* which code to us  CSI = 3;^  /*channel state info  /* 14 bit address*/  for^(index1.0;^successframe<1000;^indexl++) 1 for^(index2.0;^index2<64;^index2++)  Oct 6 1993 14:23:52^ADAPT.0^Page 6 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345  transmit(^index2^]^. 0;  out:  out2:  /*rate decision must be made here*/ N.trans-noldtrans; ninfo.infobits-noldinfobits; if^(N>=5) { blockn.(2.0*(ninfo/(1056.0*N))); if^(CSI^..^1) i if^(blockn<1.18) { CSI^.^2; goto out; ) } else if^(CSI^.. 2) f if^(blockn>1.19) { CSI = 1; gob o out; } else if^(blockn<.77) 1 CSI^= 3; gob o out; } ) else if^(CSI^.. 3) { if^(blockn>.76) { CSI . 2; goto out; } ) ninfo.0.0; noldinfobits . infobits; N.0; noldtrans . oldtrans; goto out2; }  {  if^(CSI^..^1)  tot.52; infoconstant.859.0; } else if^(CSI^..^2) { tot . 38; infoconstant-635.0; ) else if^(CSI == 3) ( tot = 24; infoconstant = 411.0;  Oct 6 1993 14:23:52^ADAPT.0^Page 7 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361  }  &^Ox07ff;  363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397  ruvr[^index2^]^. 0; /*generate 608 random^data bits to be transmitted *  /  } /*transmit[37]=0;*/  ******/  362  for^(index2=0;^index2<tot;^index2++) ( transmit[^index2^]^= rand(); if^(^(index2^+^1)^%^8^==^0) transmit[index2]^= transmit[index2]  */  /***************************************************  /* Build Header address . address +1; PlorP2=1;  lternate*/  do( trans++; if^(response > 1000)^/*^if retransmit a t  }  if^(response^!= 9999) ( if^(PlorP2^== 1^) PlorP2 . 2; else PlorP2 = 1; )  for^(index2=0;^index2<4;^index2++) header[^index2]^. 0; header[0]^. Ns «14^I^address; header[1]^.^(Ns » 2)^I^(Nr « 2)^I^(length «6); header[2]^=^(PlorP2)^I^(CSI «2);  */ ******/  mit);  WrBlkInt(VIRGIN_HEADER,^DUAL,^2,^header); /* Header built and sent to DSP transmitter /***************************************************  errorcode . WrBlkInt(VIRGIN_DATA, DUAL, tot/2,^trans if^(errorcode^!=^0) printerror(5);  Oct 6 1993 14:23:52^ADAPT.0^Page 8 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456  menu = Oxl; rate . 0x4; packet = 0; control= menu^I^rate^I^packet; errorcode . Put32Bit(CONTROL_WORD, ^DUAL,^control); if^(errorcode^!.^0^) printerror(6);  ttom,^1);  /*frame transmitted*/ setviewport(xmit.left,^xmit.top,^xmit.right,^xmit.bo clearviewport(); sprintf(msg,^"^%d",^trans); outtextxy(10,^0,^msg); sprintf(msg,^"^18.93^kHz"); outtextxy(10,^10,^meg); sprintf(msg,^"^%d",^ack); outtextxy(10,^20,^meg); sprintf(msg,^"^%d",nack); outtextxy(10,^30,^msg); sprintf(msg,^"^%d",^index1+1); outtextxy(10,^40,^meg); if^(CSI^==^1) rat=1.0; else if^(CSI == 2) rat= .75; else if^(CSI == 3) rat=.5; sprintf(msg,^"%3.3E",rat); outtextxy(10,^50,^msg);  errorcode.WarmSelect(0x290); if^(^errorcode .. 0^) printerror(1); menu . 3; Put32Bit(MENU_OPTION, DUAL, menu); for(index2=0;^index2<30000;^index2++); for(index2=0;^index2<30000;^index2++); for(index2=0;^index2<30000;^index2++); for(index2=0;^index2<30000;^index2++); Put32Bit(STROBE_RCVR,^DUAL,^Oxffffl); for(index2=0;^index2<30000;^index2++); for(index2=0;^index2<30000;^index2++); for(index2.0;^index2<30000;^index2++); for(index2=0;^index2<30000;^index2++); while(Get32Bit(sTROBE_HOST,^DUAL)=.01);  Oct 6 1993 14:23:52^ADAPT.0^Page 9 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514  Put32Bit(STROBE HOST, ^DUAL,^01); response = Get3Bit(ACKO,^DUAL); Put32Bit(ACKO,^DUAL,^88881); if^(response < 1000) ( ack++; successframe++; infobits +=infoconstant; totalbits +=1056.0; if^(response == 100) CPC1++;  else if^(response == 200) CPC2++;  else if^(response == 300) CPC1CPC2++; } else (  }  nack++; totalbits +.1056; if^(response == 9999) headfail++; else if^(response == 6666) crcfail++; else if^(response == 8888) lost++;  RdBlkInt(FLAGOP1,^DUAL,^tot/2+5,^rcvr); )  last:  setviewport(rcv.left, ^rcv.top,^rcv.right,^rcv.bottom  ,^1);  clearviewport(); sprintf(msg,^"^%d",^ack); outtextxy(10,^0,^meg); sprintf(msg,^"^%d",^lost); outtextxy(10,^10,^meg); sprintf(msg,^"^%d",^crcfail+headfail); outtextxy(10,^20,^meg); sprintf(msg,^"^%7.4E",2.0*infobits/totalbits); outtextxy(10,^30,^meg);  ttom,  1);  setviewport(stat.left,^stat.top,^stat.right,^stat.bo clearviewport();  Oct 6 1993 14:23:52^ADAPT.0^Page 10 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572  setcolor(GREEN); sprintf(msg,^"^%d",^ack); outtextxy(15,^5,^msg); sprintf(msg,^"^%d",^CPC1); outtextxy(215,^5,^msg); sprintf(msg,^"^%d",^CPC2); outtextxy(365,^5,^msg); sprintf(msg,^"^%d",^CPC1CPC2); outtextxy(515,^5,^msg); setviewport(stat.left, ^maxy*.63,^stat.right,^maxy*.6  7, 1);  clearviewport(); setcolor(BLUE); sprintf(msg,^"^%d",^flack); outtextxy(15,^5,^meg); sprintf(msg,^"^%d",^headfail); outtextxy(215,^5,^msg); sprintf(msg,^"^%d",^crcfail); outtextxy(365,^5,^msg); sprintf(msg,^"^%d",^lost); outtextxy(515,^5,^meg); setcolor(WHITE); setcolor(WHITE); WarmSelect(0x390); }while^(response , 10001); frame[indexl]^= trans - oldtrans; oldtrans = trans; } printf("%c",beep); printf("%c",beep); printf("%c",beep); printf("%c",beep); for^(index1=0;^indexl<20;^indexl++) output[indexl]=0; for^(index1=0;^indexl<1000;^indexl++) output[frame[indexl]]++; setviewport(stat.left,^maxy*.7,^stat.right,^maxy*.97,^1)• sprintf(msg,^"Number of Transmissions required for Reception outtextxy(5,^5,^meg); for^(index1=0;^indexl<20;^indexl++) ( sprintf(msg,^"^%d",^indexl); outtextxy(30*indexl,^20,^meg); setcolor(GREEN); sprintf(msg,^"^%d^",^output[indexl]); outtextxy(30*indexl,^30,^meg);  ^  Oct 6 1993 14:23:52^ADAPT.0^Page 11 ^ 573 setcolor(WHITE); 574 575 576 577^/* ^ 578^ for (index2=0; index2<64; index2++) 579 printf("%x ",transmit[ index2 1); 580^ 581^printf("\n"); 582^ for (index2=8; index2,64; index2++) 583 printf("%x ",rovr[ index2 1); 584^ 585 exit (1) 586 587 588 589 590^} 591 592^ 593 printerror(int number) 594 ^ 595^char msg[80); 596 int maxy; 597 ^ 598 switch (number) 599 ^ 600 case 1:sprintf(msg, "Select Board 290h has failed.") 601^ 602^ 603^ 604^  break; case 2:sprintf(msg, break; case 3:sprintf(msg,  "Loading RCVR.out has failed."); "Select Board 390h has failed.")  605^ break; 606^ case 4:sprintf(msg, "Loading F.OUT has failed."); 607^ break; 608^ case 5:sprintf(msg, "Downloading transmission frame to DSP board has failed."); 609^ break; 610^ case 6:sprintf(msg, "Writing Control Word to transmi tter has failed"); 611^ break; 612^ default:sprintf(msg, "Problem with error print mutt ne."); 613 614 } 615 maxy=getmaxy(); 616 setcolor(GREEN); 617 setbkcolor(WHITE); outtextxy(10, maxy*.7+15, msg); 618 619 /*getch();*/ 620 exit )l) 621 return(S); 622 623^}  ^  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 1  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 2  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  ,•  ; ent, , ace , ; le , ; ,  nker) too  coding outine  RESET ass INTO reti INT1 INT2 INT3 XINTO RINTO XINT1 RINT1 TINTO TINT1 DINT  ;  XMITADAP.asm^V1.00^Dec 92 V1.01^Jan 93 V1.02^Mar 93 v1.03^Apr 93 V2.00^Aug 93 V2.01^Sept 93 The purpose of this code is to set up the dsp board environm  51  52 53 54 55 56 57 58 variables,^and memory.^This code is used as the main interf 59 60 between the PC and the dsp board. It places all necessary 61 assembler and C routines in memory and then awaits in a simp 62 63 loop, where the ARQ shell can poke the appropriate info into 64 DSP memory and then run the appropriate routine. 65 66 67 68 69 .include VARS.ASM 70 .global^.bss 71 .global cinit^ ;init table^(from li 72 .global _c_in 73 ;starting address^(C standard) .global _interleaver 74 .global _puncture 75 .global _combineheader 76 .global^_conv^ ;the convolutional en 77 78 ;routine 79 .global^_polydiv^;polnomial division r 80 81 82 83 .sect^".init"^ ;interrupt section 84 .word^_c_int00^ ;RESET -> start addr 85 86 .word^NO^ ;all others to dummy 87 88 .word^INT_TRANSMISSION^;except the sync int 89 .word^NO 90 .word^NO 91 .word^NO 92 .word^NO 93 .word^NO 94 .word^NO 95 .word^NO 96 .word^NO 97 .word^NO 98 99 100 101 Data section to initially be loaded at $30000h but then 102 moved to $809c00^(on chip ram). 103 104 .data 105 .word^5^;constraint length 106 .word^19h^;polynomiall .11001.1+x°3+x^ 107  4 x°4  9C18 TAB_ENC  ICHAN  .word  7h  ;Polynomial2 .10111,1+x+x°2+  .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word  9665 374732215 B1492AAh  ;CRC-CCITT ;CRC-32 ;flag for packet ;Q_START --> 809c06 ;Q_START(1) ;Q_START(2) ;Q_START(3) ;Q_START(4) ;Q_START(5) ;Q_START(6) ;Q_START(7) ;Q_END --> 809c0e ;Q_END(1) ;Q_END(2) ;Q_END(3) ;Q_END(4) ;Q_END(5) ;Q_END(6) ;Q_END(7) ;Q_START --->809c16 ;Q_END --->809c17 ;DIGITAL PORT ADDRESS --->80  .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD  09c06h 09c0Eh 0804214  ;pi/4 QPSK encoding table ;---> 809c19  fff0000H a780000H  ;IBIT CHAN^1 volt ;0.707  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 3 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156  .WORD^0^;0.00 .WORD^-5a780000H^;-0.707 .WORD^-7fff0000H^;-1.00 .WORD^-5a780000H^;-0.707 .WORD^0 .WORD^5a780000H .WORD^0 .WORD^5a780000H .WORD^7fff0000H .WORD^5a780000H .WORD^0 .WORD^-5a780000H .WORD^-7fff0000H .WORD^-5a780000H .WORD^809C19H .WORD^809C39H .WORD^809C41H  157 158  Variables to be ued for initialization.  174  QCHAN  STACK  159 160 161 162 163 164 165 166 167 168 169 170 171 172 173  .usect^".stack",STACK_SIZE  175  .text .word^STACK^ .word^cinit^  STACK_ADDR ;address of stack INIT_ADDR ;address of mit tab les PRIMCTRL .word^00808064h^;primary bus control address EXPCTRL .word^00808060h^;expansion bus contr ol address TIMECTL1 .word^808030H^ ;timer 1 control SERIAL() .word^808042h^ ;FSX/DX/CLKX port co ntrol TIMECTL2 .word^808020h^ ;timer 2 control RSTCTRL .word^601h^ ;reset value for tim era PERIOD .word^808038h^ ;timer 1 period COUNT .word^55^ ;period value for ti mar 1 SETCTRL .word^6c1h^ ;set value for timer s RAM1 .word^809c00h^ ;On chip ram area DUALSTART .word^30000h^ ;temp variables DUALEND .word^33300h^ ;change for 64k DUALMEM .word^300BFh :******************************************************************* ***  The following code sets up the stack pointer and then initializes the DSP hardware as outlined in the Technical Reference Manual. _c_int00: address to SP  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 4  LDP^CODES^  ;get page of stored  LDI^@STACK_ADDR,^SP^;load the address in LDI^SP,^FP^  ;and into FP too  176 177 178 179 180 181 182 183 184 185 186 187 188  LOT^@PRIMCTRL, ARO^;Hardware specific i  nit  LOT^INITIAL,^RO STI^RI,^*ARO LOT^@EXPCTRL, ARO LOT^NULL,^RO STI^RI,^*ARO LOT^@SERIALO, ARO^;SET DIGITAL OUTPUT  TO 0  LDI^2H,^RO STI^ED,^*ARO  This portion of code is absolutely necessary when mixing C modules with assembly language.^It ensures that the variables defined in the C module are properly initialized. LDP^CODES^  address  ;get page of stored  LDI^@INIT_ADDR, ARO^;get address of mit  tables  CMPI^-1, ARO^ ;if RAM model,^skip  mit  BEQ^init_done LOT^*ARO++, R1^;get first count BZD^init_done^;if 0,^nothing to do LOT^*ARO++, AR1^;get dest address LDI^*ARO++, RI^;get first word SUBI^1,^121^ ;count^-^1  do_init: II o R1  RPTS^R1^ STI^NO,^*AR1++ LDI^*ARO++, ^RI LDI^RI,^R1^  ;block copy ;move next count int  BNZD^do_init^ ;if there is more,^r  epeat  LDI^*ARO++, AR1^;get next dest addre  SS  189 190 191 192  LDI^*ARO++, ^RI^;get next first word SUBI^1,^R1^ ;count - 1  193  This code block copies all of the variables placed at $30000  194 195 196 197 198 199 200 201 202 203  00  and moves them to the on chip memory area at $809c00 - $80a0  init_done: LDI LDI LDI 0  RPTS LDI  @DUALSTART, ARO @RAM1, AR1 *ARO++,^RO^;since parallel instruction ;coming up must initialize R DATALENGTH *ARO++,^RI  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 5 204 205 206 207  IISTI^RO,^*AR1++  208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258  LDI @DUALSTART, R6 LDI @DUALEND, R7 CALL CLEAR  ;clear DUAL memory ;$30000^-->$33300  LDP ONCHIP LDI 0, RI^ ;used LDI 0,^R1 LDI^32,^R2 STI RI, @SINE POINTER STI RI,^@COSIT4E POINTER STI R2, @POINT EOUNT STI R1,^@DATA in-TORD STI R1, @CURRNT ADDRESS OTT R1, @END ADDiESS STI R1, @Q_OTFS ET STI R1,^@TRANSMISSION STI R1, @Q_OFF TRANS STI R1, @GET_NWFRAME_FLAG LDI 40H,^BK  ;initialize variables in transmission interrupt ;routine ;sine_pointer = $809c08 ;cosine_pointer.$809c08 ;point_count = 32 ;data_word . 0 ;current_address = 0 ;end address . 0 ;q_oTfs et . 0 ;transmission = 0^(not busy) ;q_off_trans . 0 ;flag .^0 ;BK . 40H  This section places the flag for the frames in the appropria te ;^memory locations. ADD_FLAG: LDP ONCHIP LDI @FLAG,^RI LDP CODES LDI @FLAGOP1, AR1 ;LDI^15,^RC ;RPTB ENDLOOP1 addi 63h,^an eras lean!! OTT RO,^*AR1 ENDLOOP1: ;ADDI 21h, ART  ;16 packets ;cut it out because interef ;with combine area must be c  ;get next flag address  ;strip information from CONTROL_WORD START_OF_MAIN_ROUTINE: LDP MENU:^LDI LDI AND  DUAL @CONTROL WORD, RI MENU_MASi, R1 RI,^R1,^R2  ;get MENU_OPTION  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 6 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316  STI R2, @MENU_OPTION BZ MENU^ ;LSH -2,^RO ;AND RI,^121,^R3^ ;STI R3,^ORATE LSH LDI AND OTT  ;if no choice loop back  ;get^data RATE  -2,^RI PACKET_MASK, R1^;get PACKET_NUM RI, R1, R4 R4, @PACKET_NUM  LDP CODES LDI @VIRGIN_HEADER, AR1 LDI *AR1++, RI LOT LENGTH MASK, R1 ^;get LENDATAO LSH -22,^RI AND RI, R1, R5 ldi*arl,^r0 and 3,^r0^ ;get puncture matrix# ldi *arl,^rl and 12,^rl lsh -2,^rl^ ;get rate to be used LDP DUAL sti rO,^@CODE sti rl,^ORATE STI R5, @LENDATAO CMPI 1,^R2 BZ OPTION1 CMPI 2,^R2 BZ OPTION2 CMPI 3,^R2 BZ OPTION3 LDI 2,^R7 BR ERROR DEAR: BR DEAR ;******************************************************************* *** OPTION 1 - ADAPTIVE SCHEME Construct frame from given header and data. Use rate 1/2 for header and appropriate CPC matrix ; chosen rate of data packet. OPTION1: ****  ;*********************************************************** ;CRC calculation and appending to header information stored ;at VIRGIN_HEADER LDP LOT LOT LDI LDI  CODES @VIRGIN_HEADER, AR1^;get original header and place *AR1++, RI^ ;at HEADBUF1 padded with x°16 *AR1,^R1^ ;zeros @HEADBUF1, AR5  LDI @HIGH MASK, R2 LSH 16, RI  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 7 317 318 319 320 321 322 323 324 325 326  AND RO,^R2,^R3 LSH -16,^R3 OR R1,^R3 LSH 16,^RO STI RU,^*AR5++ STI R3,^*ARS__  words  327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371  needed  LDI 17,^RO^ K constraint length LOT POND CCITT, R1^ POLY divisor LDI 2, RI^ length of header in 32 bit LDI @HEADBUF2,^R3^  where to place RESULT^(not in this CRC case)  PUSH PUSH PUSH PUSH PUSH PUSH  AR1^ R3^ R2^ R1^ AR5^ RU^  CALL _polydiv^ 0 SUBI 5,SP^ POP AR1^ LSH 5, RU^ LDI *AR1, R1^ OR R1,^RU STI RU,^*AR1  save VIRGIN_HEADER+1 *RESULT . HEADBUF2 TOTAL . 2 POLY . CRC_CCITT MESGDATA = HEADBUF1 K = 17 Do CRC calculation CRC checksum returned in R  clean stack get back VIRGINHEADER+1 shift CRC before placing in VIRGIN_HEADER+1  ;End of CRC calculation and appending to header info **  ;*********************************************************** ;Convolutional encoding of header information stored at ;VIRGIN HEADER.^Resulting encoded header is stored at ; AdderT output encoded header bits ^ > HEADBUF1 ; Adder2 output encoded header bits ^ > HEADBUF2  lye  LDI LDI LDI LDI  @VIRGIN HEADER, ARO^; data to OHEADBUT.1, AR1^; address @HEADBUF2, AR2^; address 2,^RO^ ;^# of 32  PUSH PUSH PUSH PUSH  RU^ AR2^ AR1^ ARO^  ;^SIZE ; MESGP2 ; MESGP1 ; MESG  CALL _conv SUBI 4,^SP ;End of convolutional encoding of header  be convolved of adderl bits of adder2 bits bit words to convo  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 8 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429  LDP LDI LDI LDI LDI  CODES OFRAMEBUFP1, AR3^;where to place result 64, RO^ ;bit length of adderl @HEADBUF1, ARO^;adder 1 output bits OHEADBUF2, AR1^;adder 2 output bits  PUSH NO PUSH AR3 PUSH AR1 PUSH ARO CALL^combineheader SUBI^.,^SP ;End of header construction ******  ;*********************************************************** ;^Data CRC calculation  LDI @VIRGIN_DATA, ARO^;start of data LDI 33,^RO^ ;K constraint length LDI @CRC 32,^R1^ ;POLY LDI ODATT,BUFP1,^R3^;address to store RESULT LDI @VIRGIN_DATA, AR3^;*MESGDATA SUBI 1, AR3^ ; same as premultiply by x^K LDP DUAL LDI ORATE, R7 LDP CODES CMPI 1,57 LDIZ 27, R2^ CMPI 2,^R7 LDIZ 20, R2^ CMPI 3,^R7 LDIZ 13, R2^ CMPI 0,^R7 BZ ERROR  rds +  ;26 DATA WORDS + BLANK CRC ;19 DATA WORDS + BLANK CRC ;12 DATA WORDS + BLANK CRC  LDI R2,^R7 PUSH R7 PUSH R3^ PUSH R2^  ;*RESULT^(not used) ;TOTAL = length in 32 bit wo  PUSH R1^ PUSH AR3^ PUSH RU^  ;^1 for CRC32 ;POLY . CRC_32 ;MESGDATA = VIRGIN_DATA ;K = constraint length  CALL _polydiv SUBI 5,^SP ADDI 1, AR3^ _...-  ;Point to @VIRGIN_DATA  Oct 6 1993 14:48:30^XMITADAP.ASM^Page, 9 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485  POP R7 SUBI^1,^R7 ADDI R7, AR3 OTT RO,^*AR3^  ;place CRC at end of data  ;At this point the data exists @VIRGIN_DATA with a 32 bit CR  C  ;appended to it right after the last data bit ;0X30013^-^0X30025 DATA^CRC^@ 30026  ******  ,*********************************************************** ;Convolutional encoding of data information @VIRGIN_DATA. ;Resulting encoded data is stored at: ;^P1 encoded data ---> DATABUFP1 ;^P2 encoded data ---> DATABUFP2  K  ;need to get number of 32 bit words to convolve and also add ;^(constraint length)^bits to 1> rounded up word count, and 2> bit count of encoded data LDP CODES LOT @VIRGIN DATA, ARO LDI @DATABUET 1, AR1 LOT @DATABUFP2, AR2 LDP DUAL LOT @RATE,^R7 LOP CODES CMPI 1,R7 LDIZ 28, R4^ CMPI 2,^R7 LDIZ 21, R4^ CMPI 3,^R7 LDIZ 15, R4^ PUSH R4^ PUSH AR2^ PUSH AR1^ PUSH ARO^  ;26 DATA WORDS + BLANK CRC ;19 DATA WORDS + BLANK CRC ;12 DATA WORDS + BLANK CRC ;SIZE ;MESGP2 ;MESGP1 ;MESG  CALL _conv  ****  SUBI 4,^SP ;End of convolutional encoding of data ;*********************************************************** ; Construct frame 91 and P2 and place at: ;^frame P1 ---> FRAMEBUFP1 ;^frame P2 ---> FRAMEBUFP2 ; This procedure is made a bit tedious because if the header ;^length is not a multiple of 32 then we must shift and OR ; all the data bits so that they can be appended directly ;^after the header bits!!  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 10 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543  LDI LDI LDI LDI  ******  @DATABUFP1, ARO^;pointer @DATABUFP2, AR1^;pointer @FRAMEBUFP1, AR2^;pointer @FRAMEBUFP2, AR3^;pointer  to to to to  data bits P1 data bits P2 frame P1 frame P2  ;*********************************************************** ;Puncture and combine bits of adderl and adder2  PUNCTURE AND COMBINE: EDP El UAL LOT @RATE, R7 LDP CODES CMPI 1,R7 BZ RATE1 CMPI 2,^R7 BZ RATE75 CMPI 3,^R7 BZ RATES CMPI 0,^R7 BZ ERROR ;data bits of adder 1 are @DATABUFP1 ;data bits of adder 2 are 9DATABUFP2 RATE1:  RATE75:  RATES:  LDP DUAL LOT @CODE, R7 ldp CODES CMPI 1,^R7 BZ CODE1 CMPI 2,^R7 BZ CODE2 BZ ERROR LDP DUAL LOT @CODE, R7 ldp CODES CMPI 1,^R7 BZ CODE75 CPC_ONE CMPI 2,^117 BZ CODE75_CPC_TWO BZ ERROR LDP CODES LOT 9DATABUFP1, ARO LOT @DATABUFP2, AR1 BR RATE_HALF  PUSH_AND_CALL: PUSH RO^ ; Routine used by all rates to push PUSH AR1^ ; parameters and call puncture modul e  Oct 6 1993 14:48:30^XMITADAP.ASM 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 611  Page 11  PUSH AR3 PUSH R1 CALL _puncture SUBI 4,^SP RETS CODEl: 2  CODE2: 2  LDI^896,^RO LOT^4,^R1  ; Puncture Adderl bits by 1/  LDI 8DATABUFP1, AR1 LET @DATABUFP3, AR3 CALL PUSH_AND_CALL LDI^896,^RO LDI^5,^R1 LDI @DATABUFP4, AR3 LDI @DATABUFP2, AR1 CALL PUSH AND_CALL BR COMBINE1 LDI^896,^RI LDI 6,^R1  ;Puncture Adder2 bits by 1/2  ; Puncture Adderl bits by 1/  LDI @DATABUFP1, AR1 LDI @DATABUFP3, AR3 CALL PUSH_AND_CALL LDI^896,^RI LDI 7,^R1 LDI @DATABUFP4, AR3 LDI @DATABUFP2, AR1 CALL PUSH AND_CALL BR COMBINE] .  CODE75_CPC ONE: LDY 672,^RO LDI^0,^R1 4 LDI 8DATABUFP1, AR1 LDI @DATABUFP3, AR3 CALL PUSH_AND_CALL LDI^672,^RO LDI^1,^R1 LDI 8DATABUFP4, AR3 LDI @DATABUFP2, AR1 CALL PUSH AND_CALL BR COMBINE CODE75_CPC TWO: LDT 672,^RI LDI^2,^R1 LDI @DATABUFP1, AR1 LOT 8DATABUFP3, AR3 CALL PUSH_AND_CALL  ;Puncture Adder2 bits by 1/2  ; Puncture Adderl bits by 3/  ;Puncture Adder2 bits by 3/4  ;Puncture Adderl by 3/4  Oct 6 1993 14:48:30^XMITADAP.ASM 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660  Page 12  LDI 672,^RO LDI 3, R1^ ;Puncture Adder2 by 3/4 LDI @DATABUFP4, AR3 LDI @DATABUFP2, AR1 CALL PUSH AND_CALL BR COMBINE RATE_HALF: LOT 448,^RI LDI @FRAMEBUFP2, AR3 PUSH RO PUSH AR3 PUSH AR1 PUSH ARO CALL^combineheader SUSI IT , ^SP BR CONSTRUCT COMBINE1: LDI @DATABUFP3, ARO LDI @DATABUFP4, AR1  ;14 WORDS * 32 BITS  LDP CODES LDI @FRAMEBUFP2, AR3 LDI 896,^RD PUSH RI PUSH AR3 PUSH AR1 PUSH ARO CALL^combineheader SUET 7i,^SP BR CONSTRUCT COMBINE:  ;21 WORDS * 32 BITS  LDI @DATABUFP3, ARO LDI @DATABUFP4, AR1 LDP CODES LDI @FRAMEBUFP2, AR3 LDI 672,^RI PUSH RO PUSH AR3 PUSH AR1 PUSH ARO CALL^combineheader SUBI Z,^SP  ;21 WORDS . 32 BITS  ;End of header construction CONSTRUCT: LDP CODES LOT @FRAMEBUFP1, AR1 ADDI 4,AR1 LDI 8FRAMEBUFP2, ARO ldp DUAL LDI 27,^RI  ;copy possible 27 words if r  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 13 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714  ate^1/2  LDI^*ARO++,^R1 RPTS RO  LET^*ARO++,^R1 IISTI^R1,^*AR1++  BR TRANY  *******  ;End of constructing Frames P1 and P2 ;.********************************************************** ,•^Now we must save the frame P2 for future possible ,•^retransmission and interleave frame P1 which will also be save and then queued for transmission. Save frame P2^---> @PACKETxHARDP2 Interleave P1 and save ---> @PACKETxHARDP1  nop nop nop ldi BLOCKS,^r2 INTERLEAVE MORE: PUSH R2 PUSH AR2 PUSH ARO CALL _interleaver POP ARO POP AR2 POP R2 ;ADDI 4, AR2^ ;not required,^subroutine au tomatically ADDI DEINT_ROW, ARO^ ;increments AR2 cont ants SUBI^1,^R2 BNZ INTERLEAVE_MORE P2 ****  ;Completed interleaving of frame P1 and saving of frame P1 & :*********************************************************** ;Now set up for transmission LDI @PACKET3HARDP1, ARO SUBI 1,^ARO LDI ARO, AR3 AUDI 34,^AR3 LDI ARO, R7 LDI AR3, R6 CALL QUEUE  Oct 6 1993 14:48:30^XMITADAP.ASM 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773  Page 14  LDP DUAL LDI 0,^R6 STI R6, @CONTROL_WORD LDP CODES LDI @FRAMEBUFP1, R6 LDI R6,^R7 ADDI 40H, R7 CALL CLEAR LDI @DATABUFP3, R6 LDI R6,^R7 AUDI 200h,^R7 CALL CLEAR BR START_OF_MAIN_ROUTINE  TRANY:  3  LDI LDP LDI LDI  31,^RO CODES @FRAMEBUFP1, ARO @PACKET3HARDP1, ARC  LDI *ARO++,^R1 RPTS RO LDI *ARO++,^R1 IISTI R1,^*AR1++ ;Now set up for transmission LDI @PACKET3HARDP1, ARO SUBI 1, ARO LDI ARO, AR3 ADDI 33, AR3 LDI ARO,^R7 LDI AR3,^R6 CALL QUEUE LDP DUAL LDI^0,^R6 STI R6, @CONTROL_WORD LDP CODES LDI @FRAMEBUFP1, R6 LDI R6,^R7 ADDI 40H,^R7 CALL CLEAR LDI @DATABUFP3, R6 LDI R6, R7 AUDI 200h, R7 CALL CLEAR BR START_OF_MAIN_ROUTINE  ;COPY FRAME TO SLOT  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 15 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826  ,*******************************************************************  ******  ;  The purpose of this option is to encode the data using a rat  ; ; ough ; ; terbi  1/2 convolutional encoder and the two polynomials defined in VARS.ASM. The encoded data is placed in a frame and sent thr  OPTION2: convolve  o encode  the channel. Main purpose for this option is to test perfomance of the Vi Decoder in the RCVRCPC.ASM module. LDP CODES LDI @VIRGIN_HEADER, ARO ^ ;address of data to LDI @FRAMEBUFP1, AR1^ LDI @FRAMEBUFP2, AR2^ LDI 16,^HO^ PUSH PUSH PUSH PUSH  HO^ AR2^ AR1^ ARO^  CALL _conv^ SUBI 4,^SP  ;Pl bit buffer ;P2 bit buffer ;# of 32 bit words t ;SIZE ;MESGP2 ;MESGP1 ;MESG ;convolve data  ;Now the P1 bits and P2 bits must be combined LDI LDI LDI LDI  d data  512,^RO @FRAMEBUFP1, ARO @FRAMEBUFP2, AR1 @DATABUFP1, AR3  PUSH HO^ PUSH AR3^  ;# BITS ;address of convolve  PUSH AR1^ PUSH ARO^  ;Pl bits ;P2 bits  CALL _combineheader SUBI 4,^SP ;Now set up to interleave & transmit frame through channel LDI @PACKET3HARDP1, AR2^;slot address of frame LDI @DATABUFP1, ARO^;random data start address  ldi BLOCKS,^r2 INTERLEAVE_MORE2: PUSH R2 PUSH AR2 PUSH ARO  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 16 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860  CALL _interleaver POP ARO POP AR2 POP R2 ;ADDI 4, AR2^ ;not required,^subroutine au tomatically AUDI DEINT_ROW, ARO^ ;increments AR2 cont ents SUBI 1,^R2 BNZ INTERLEAVE_MORE2 ;frame is now interleaved and placed into the slot 30123 ;and it also has a flag appended to it  of frame  next  861 862 863 864 865 866  ldi @PACKET3HARDP1, ar2 SUBI 1, AR2^  ;AR2 points to flag @ start  ldi ar2,^ar0 ADDI 34, ARO LDI AR2,^R7^ LDI ARO,^R6^ CALL QUEUE^  ;start address of frame ;end address + 2 ;transmit frame  LOP CODES^ ;clear memory 8$30000 to LDI @DUALSTART, R6^;$300bf and branch back for LDI @DUALMEM, R7^ ;option CALL CLEAR BR START_OF_MAIN_ROUTINE  OPTION 3 - Take 992 random data bits delivered @VIRGIN_HEADE  mit  and look at control word in order to determine which P1 frame slot to place data in.^Then trans random UNCODED data with a flag. The purpose of this option is to allow the user t  867  obtain the Bit Error Rate (with a PC host Program  868 869 870 871 872 873 874 875 876 877  of the modulation scheme being used.^This option takes the random data, adds a flag and just transmits the 1024 bit frame through the channel. OPTION3: LDP CODES LDI @PACKET3HARDP1, AR2^;slot address of frame LDI @VIRGIN_HEADER, ARO^;random data start address  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 17 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931  932 933 934 935  ldi BLOCKS,^r2 INTERLEAVE_MORE3: PUSH R2 PUSH AR2 PUSH ARO  936 937 938 939 940 941  CALL _interleaver POP ARO POP AR2 POP R2 ;ADDI 4, AR2^ ;not required,^subroutine au tomatically ADDI DEINT_ROW, ARO^ ;increments AR2 cont ents SUSI^1,^R2 BNZ INTERLEAVE_MORE3 ;frame is now interleaved and placed into the slot 30123 ;and it also has a flag appended to it  of frame  next  ldi @PACKET3HARDP1,^ar2 SUBI 1, AR2^ ldi ar2,^ar0 ADDI 34, ARO LDI AR2,^R7^ LDI ARO,^R6^ CALL QUEUE^  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 18  ;AR2 points to flag @ start  ;start address of frame ;end address + 2 ;transmit frame  LOP CODES^ ;clear memory @$30000 to LDI @DUALSTART, R6^;$300bf and branch back for LDI @DUALMEM,^R7^ ;option CALL CLEAR BR START_OF_MAIN_ROUTINE  942 943 944 945  QUEUE: LDP LDI KEEPCOING: LDI LDI ng until BNZ  ONCHIP @Q_START, ARO @Q_OFFSET,^IRO *+ARO(IRO),^R1^;QUEUE is full so keep loopi KEEPGOING^  ;this slot is available  STI R7,^*+ARO(IRO)^;Place start and end address  s used  if not  LDI^IRO,^RO^  ;Adjust offset value which i  ADDI 1, RO^  ;to make the QUEUE a circula  CMPI 8,^RU^ LDIZ 0,^RO STI RO,^@Q_OFFSET  ;buffer  LDI @TRANSMISSION, RO^;Check if busy transmitting BZ BEGIN_TRANS^ RETS  ;begin transmission  946  This section of code is used to begin transmission of a fram  947 948 949 950  and initialize various parameters for transmission interrupt routine. It is used for the first frame transmission as well as any subsequent frame transmission when the interrupt has disable  951 952 953 954 955 956 957 958 959 960 961 962 963 964  This section of code places the start and end address of a frame to be transmitted in the queue. Note: before calling this routine ensure that R6^end address of frame + 2 locations R7 = start address of frame  LDI @Q_END, AR1^ ;QUEUE STI R6,^*+AR1(IRO)  965 966 967 968 969 970 971 972 973 974 975 976 977 978 979  its^self. BEGIN_TRANS. Set up timer 1 which will be used to trigger interrupt 1 every 6.6 mircoseconds.^55/.12 = 6.6mircoseconds LDP CODES LDI^@TIMECTL2, AR1 LDI^@TIMECTL1, ARO LDI^@RSTCTRL, RO STI^RO,^*ARO STI^RO,^*AR1^ ;Reset timers 0,^and 1 LDI @PERIOD, AR1^ ;Set timer 1 to trig  ger  LDI @COUNT,^RO^  ds  sy  LDP LDI LDI STI  ;every 6.6microsecon  STI RO,^*AR1 LDI @SETCTRL, RO STI RO,^*ARO ONCHIP OFFFFH, RE @Q_START,ARO RO,^@TRANSMISSION^;set transmission flag to bu  LDI @Q_OFF_TRANS,^IRO LDI *+ARO(IRO), AR3 ^;AR3 = address of frame star KEEP_TRANS:  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 19 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035  RD  ;LDI @SINEO,^RO LDI 0,^RO STI RD.^@SINE_POINTER^;sine_pointer = 809c08 STI RD.^@COSINE_POINTER^;cosine_pointer^809c08 LDI 8,^RD STI RO,^@POINT_COUNT^;point_count = 8 ldi^16,^r0 sti rO,^@DIBIT_COUNT LDI *AR3++, ^RD^ ;place first data in DATA_WO STI RO, @DATA_WORD LDI AR3,^RD STI RO,^@CURRENT_ADDRESS^;save incremented pointer LDI @Q_END, ARO LDI^*+ARO(IRO),^RD STI RO, @END_ADDRESS^;save end address ldi^0,^r0 sti^rO,^*+ar0(ir0) ldi @Q_START,^ar0 sti^rO,^*+ar0(ir0)  QUEUE  1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049  ERROR: DEAD  LDP DUAL STI R7, @ERROR_NUM BR DEAD  , * *************** ** *************** ** *************** * **************** ****  of ump  This interrupt 1 is responsible for the actual transmission the frame.^It consists of 30 instructions^(if it does not j to get a NEWDIBIT). 30 X 6Ons = 1800ns Interrupt 1 occurs every^55^(count value)/.12 = 6.6 microse  1050 1051 1052 1053 1054  6.6microsec/60ns = 110 instructions 110 - 30 = 80 instruction between interrupts Note: NEWDIBIT is called after 32 points have been output fo  LDI IRO,^RD^  ;Adjust offset used to make  1055  each symbol.^NEWDIBIT is very time consuming and woul  AUDI 1,^RD^ CMPI 8,^RO LDIZ 0,^RI STI RI, @Q_OFF_TRANS  ;a circular buffer  1056 1057 1058 1059 1060 1061 1062 1063  practically take the entire 6.6 microseconds.  LDI @GET_NEWFRAME_FLAG, RD BZ ENABLE_RET LDI^0,^RD STI RI, @GET_NEWFRAME_FLAG RETS ENABLE_RET: OR 2H,^IN^ OR 2000H, ST^ RETS  ;ENABLE INTERRUPT 1 ;ENABLE GLOBAL INTERRUPTS  ;This section clears memory chunks specified by ARO --› AR1 CLEAR:  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 20  SUBI R6,^R7 LOIN 1,^R7 BN ERROR LDI NULL,^RD LDI R6,^ARO RPTS R7 STI RD.^*ARO++ RETS ;******************************************************************* **** ;This section is used for debugging various errors  1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087  INT_TRANSMISSION:  them  PUSH ST XOR 2000H,^ST PUSH RD^ PUSH PUSH PUSH PUSH PUSH  R1^ R2 ARO AR1 AR3  ;save registers before using ;in interrupt routine  push ir0 PUSH DP LDP ONCHIP LDI @IBIT_POINTER, ARO^;ar0 = sine table pointer LDI @QBIT_POINTER, AR1^;arl = cosine table pointer LDI @SINE_POINTER,^IRO  te  LDI *+ARO(IRO),^R1^;output value to channel and upda LDI *+AR1(IRO),^R2^;table pointers respectively STI R1, OADCHANA STI R2, @ADCHANB  ldi^@SERIAL°, AR3 LDI^2H,^R2 STI^R2,^*AR3  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 21 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144  ol  LDI @POINT_COUNT, RD ;SUBI^1,^RD CMPI 4,^RD  ;check if 32 points per symb ;has been output to channel  BNZ NOPULSE PULSE_RCVR:  t NOPULSE:  LDI^6H,^R2 STI^R2,^*AR3 SUBI 1,^RI STI RO,^@POINT_COUNT BZ NEWDIBIT  FINISH:  FINISH2: turning  ;if 16th point then output ;a pulse on the serial 0 por  ;STI ARO,^@SINE POINTER ;STI AR1,^@COSIRE _POINTER POP DP pop ir0 POP AR3 POP AR1 POP ARO POP R2 POP R1 POP RI POP ST OR 2000h,^ST RETI  NEWDIBIT: LDI @GET_NEWFRAME_FLAG, RD BN NEWFRAME LDI^8,^RI LDI^3,^R1 STI RI,^@POINT_COUNT LDI @DATA WORD, RI AND3 RI,^17d,^R2 LSH -2,^RI STI RI,^@DATA WORD LDI @DIBIT_COTINT,^RI SUBI 1,^RI STI RO,^@DIBIT_COUNT  ;if so get another dibit ;save new pointers  ;restore registers before re ;from interrupt routine  1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181  ;if newframe flag set ;get newframe ; R1 = 3 mask for 2 lsb's ;initialize POINT_COUNT . 32 ; RO = DATA_WORD ; R2 = DATA_WORD & 3 ;shift DATA_WORD by 2  hnz NEXT ;ldi @COSINE_POINTER, ^ar0 ;ldi^*ar0++,^r0 ;sti rO,^@DATA_WORD ;ldi^ar0,^r0 ;cmpi^Offffh,^r0  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 22  ;random bit stream output  1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201  ;1diz^0,^r0 ;sti rO,^@COSINE_POINTER ;ldi^16,^r0 ;sti rO,^@DIBIT_COUNT ;ldiz @FLAG,^r0^ ;continuous flag output ;sti rO, @DATA_WORD ;LDI^16,^RD ;STI RI,^@DIBIT_COUNT BZ NEWWORD^  ;frame output  NEXT:^LDI @SINE_POINTER, RI^ ide how much MPYI 8,^R2 ADDI R2,^RD LDI RI,^IRO LDI @TABLE ENC, ARO LDI *+ARO(TR O),^R1 STI R1,^@SINE_POINTER  ;use DIBIT to dec  BR FINISH2 NEWWORD:  emit  ad  SETFLAG:  LDI 16,^RD STI RO,^@DIBIT_COUNT LDI @CURRENT_ADDRESS, AR3^;get pointer to data to tran LDI *AR3++,^RD^ ;get data pointed to STI AR3, @CURRENT ADDRESS^;save incremented pointer STI ED, @DATA_WORE^;save data CMPI @END_ADDRESS, AR3^;check if end of frame reach BZ SETFLAG OR NEXT^  ;if not do NEXT  LDI -1,^RD STI RI, @GET_NEWFRAME_FLAG BR NEXT  NEWFRAME: ;MIGHT WANT TO ADD TIME DELAY BETWEEN FRAMES LDI @Q_START, ARO LDI @Q_OFF_TRANS,^IRO LDI *+ARO(IRO),^AR3 LDI AR3,^RI^ :RI will set ST flag BZ STOP TRANS CALL KEEP TRANS BR FINISH-i STOP_TRANS: LDI 0,^RI  Oct 6 1993 14:48:30^XMITADAP.ASM^Page 23 1202 1203 1204^STI RO, @TRANSMISSION 1205^STI RO, @GET_NEWFRAME_FLAG 1206 1207^POP DP^ ;restore registers before re turning 1208^pop ir0 1209^POP AR3^ ;from interrupt routine 1210^POP ARO 1211^POP ARO 1212^POP R2 1213^POP R1 1214^POP RO 1215^POP ST 1216^XOR 2000H, ST 1217^RETI 1218 1219 UPDATE1: 1220^LDI *ARO--(DELTA)%, RO ^;output value to channel and update 1221^LDI *AR1++(DELTA)%, R1 ^;table pointers respectively 1222 1223^; SUBI DELTA, ARO 1224^; ADDI DELTA, AR1 1225^; BR UPDATE2 1226^;******************************************************************* *** 1227 ;^All other interrupts simply return 1228 1229 NO:^RETI 1230 1231 1232 1233 .end  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 2 51  RCVRADAP.asm^V1.00^Dec 92 V1.01^Apr 93 V2.00^Sept 93  52  ; ,•^The purpose of this code is to set up the dsp board environm ent, ,^variables,^and memory.^This code is used as the main interf ace ,^between the PC and the dsp board. It places all necessary ;^assembler and C routines in memory and then awaits in a simp le ,^loop, where the ARQ shell can poke the appropriate info into ,•^DSP memory and then run the appropriate routine.  .include VARSRCVR.ASM .global^.bss .global cinit^  nker) standard)  coding outine  ;init table^(from li  .global _c_int00^ ;starting address^(C .global _interleaver .global _puncture .global _combineheader .global^_conv^ ;the convolutional en ;routine .global^_polydiv^;polnomial division r  .sect^".init"^ ;interrupt section RESET^.word^_c_int00 ^ ;RESET -> start addr ess INTO^.word^NO^ ;all others to dummy reti INT1^.word^RCV^ ;except the sync int INT2^.word^NO INT3^.word^NO XINTO^.word^NO RINTO^.word^NO XINT1^.word^NO RINT1^.word^NO TINTO^.word^NO TINT1^.word^NO DINT^.word^NO  Data section to initially be loaded at $30000h but then moved to $809c00^(on chip ram). .data .word^5^;constraint length  53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107  4 x^4  9C18 TAB_ENC  ICHAN  .word  9h  ;polynomiall =11001=1+x^3+x^  .word  7h  ;polynomial2 =10111.1+x+x^2+  .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word  9665 374732215 B1492AAh  ;CRC-CCITT ;CRC-32 ;flag for packet ;Q_START --> 809c06 ;Q_START(1) ;Q_START(2) ;Q_START(3) ;Q_START(4) ;Q_START(5) ;Q_START(6) ;Q_START(7) ;Q_END --> 809c0e ;Q_END(1) ;Q_END(2) ;Q_END(3) ;Q_END(4) ;Q_END(5) ;Q_END(6) ;Q_END(7) ;Q_START --->809c16 ;Q_END^>809c17 ;DIGITAL PORT ADDRESS --->80  .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD .WORD  09c06h 09c0Eh 08042H  ;pi/4 QPSK encoding table ;--->^809c19  AA50000H  ;IBIT CHAN^1 volt  Oct 6 1993 14:39:55 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158  QCHAN  RCVRADAP.ASM^Page 3  .WORD^1E280000H^;0.707 .WORD^0^ ;0.00 .WORD^-1E280000H^;-0.707 .WORD^-2AA50000H^;-1.00 .WORD^-1E2800001-1^;-0.707 .WORD^0 .WORD^1E280000H .WORD^0 .WORD^1E2800001-1 .WORD^2AA50000H .WORD^1E2800001-1 .WORD^0 .WORD^-1E280000H .WORD^-2AA50000H .WORD^-1E280000H .WORD^809C19H^;TABENC ---> .WORD^809C39H^;IBIT CHAN .WORD^809C41H^;QBIT CHAN^--->  ;444********************************************44******4444.4*****4 444*** ;^Variables to be used for initialization. STACK  .usect^u.stacku,STACK_SIZE  Oct 6 1993 14:39:55 159 160 161 162 163 164 165 166 167 168 169 170 171 172  176 177  179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196  _c_int00:  LDP^CODES^  ;get page of stored  nit  199 200 201 202 203 204  RCVRADAP.ASM^Page 4  LDI^@STACK_ADDR, SP^;load the address in LDI^SP, FP^  ;and into FP too  ^LDI^@PRIMCTRL, ARO^;Hardware specific i  TO 0  LDI^INITIAL, RI STI^RI, *ARO LDI^@EXPCTRL, ARO LDI^NULL, RI STI^RI, *ARO ;LDI^@SERIAL°, ARO ^;SET DIGITAL OUTPUT ;LDI^2H, RI ;STI^RI, *ARO  This portion of code is absolutely necessary when mixing C modules with assembly language. It ensures that the variables defined in the C module are properly initialized. address  ^LDP^CODES^  ;get page of stored  LDI^@INIT_ADDR, ARO^;get address of init  tables ^CMPI^-1, ARO^ ;if RAM model, skip mit BEQ^init_done LDI^*ARO++, R1^;get first count BZD^init_done^ ;if 0, nothing to do LDI^*ARO++, AR1^;get dest address LDI^*ARO++, RI^;get first word SUBI^1, R1^ ;count - 1 do_init:^RPTS^R1^ ;block copy STI^RI, *AR1++ II^LDI^*ARO++, RI LDI^RI, R1^ ;move next count int o R1 BNZD^do_init^ ;if there is more, r epeat ^ LDI^*ARO++, AR1 ;get next dest addre ss LDI^*ARO++, RI ^;get next first word SUBI^1, R1^ ;count - 1  197  ***  The following code sets up the stack pointer and then initializes the DSP hardware as outlined in the Technical ;^Reference Manual.  to SP  173 174  178  .text STACK_ADDR .word^STACK^ ;address of stack .word^cinit^ INIT_ADDR ;address of mit tab les PRIMCTRL .word^00808064h^ ;primary bus control address EXPCTRL .word^00808060h^ ;expansion bus contr ol address TIMECTL1 .word^808030H^ ;timer 1 control SERIAL° .word^808042h^ ;FSX/DX/CLKX port co ntrol TIMECTL2 .word^808020h^ ;timer 2 control RSTCTRL .word^601h^ ;reset value for tim ers PERIOD .word^808038h^ ;timer 1 period COUNT .word^55^ ;period value for ti met 1 SETCTRL .word^6c1h^ ;set value for timer s RAM1 .word^809c0Oh^ ;on chip ram area DUALSTART .word^30000h^ ;temp variables DUALEND .word^33300h^ ;change for 64k DUALMEM .word^3008Fh REALSTART .word^31000H REALEND .word^32fffH ;.*************444444********************444444*****************444*  address  This code block copies all of the variables placed at $30000 00  and moves them to the on chip memory area at $809c00 - $80a0  init_done: LDI^@DUALSTART, ARO LOT^@RAM1, AR1 LDI^*ARO++, RI  ;since parallel instruction ;coming up must initialize R  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 5 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 20 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259  0  260 RPTS^DATALENGTH LDI^*ARO++,^RI IISTI^RI,^*AR1++  LDI @DUALSTART, R6 LDI @DUALEND, R7 CALL CLEAR  261  ;clear DUAL memory ;$30000^-->$33300  ldf^0,^r0 ldi @RCVD_SIGNAL_ENERGY,ar0 stf^rO,^*ar0  276  ldi^@CPC2Q,^r6 ldi^r6,^r7 addi 300h,^r7 call CLEARFLOAT  t  277 278 279 280  LDI OFFFH,^BK  ;set circular length of inpu  OR 2H,^IE OR 2000H,^ST  ;buffers ;enable interrupt 1 ;enable global interrupts  BOSS: ldp DUAL ldi @STROBE_RCVR,^r0 bnz GOAHEAD hr BOSS STROBETHEHOST: ldp DUAL ldi^0,^r0 sti rO,^@STROBE_RCVR ldi^255,^r0 sti al,^@STROBE_HOST hr BOSS GOAHEAD:  LDP CODES LDI @CURRENT_FLAG, ARO  262 263 264 265 266 267 268 269 270 271 272 273 274 275  LDI @CPC1I,^R6 LDI @REALEND, R7 CALL CLEARFLOAT  er  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 6  ;get latest found flag point  BACKUP:^LDI *ARO,^RO BZ STROBETHEHOST^;check if flag found LDI 0,^R1 STI R1,^*ARO ;if found reset pointer to z ero  281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312  next ON of  NORESET:  AG  the red  LDI ARO, R1^  ;& increment flag pointer to  ADDI 1,^R1^  ;position in table.^If BOTT  CMPI @TABLE_BOTTOM, R1^;table reached reset pointer BNZ NORESET^ ;to TOP LDI @TABLE_TOP, R1 STI R1, @CURRENT FLAG ;At this point RIT) contains address of real data value of the ;very last dibit of FLAG SUBI 17,^RO^  ;point to first dibit of FL  cmpi @CIRC BOTTOM, r0 bge NO _ADJUST 2^r0 addi 0Iffh , ;This next section of code is used to check the validity of ;FLAG found.^That is,^it checks if the flag found has occur ;in a frame of data thus resulting in a false flag.  NO_ADJUST: LDI @START_FRAME, R1^;start add of last frame dec oded LDI @STOP_FRAME, R2^;stop add of last frame deco dad LDI RI,^R3^ ;R3 . flag address CMPI 121,^R2^ ;STOP > START? BP NO CIRC_ADJUST^;yes, no adjustment required ldi r,^r4 ADDI 100061,^R2^ ;NO,^adjust^for circular cmpi r4,^r3 bp NO CIRC_ADJUST ADDI 100 0H, R3^ ;buffer by adding circular ;length NO_CIRC_ADJUST: ;IF ( FLAG ADD > START FRAME^&^FLAG_ADD < STOP_FRAME ) ,^FLAG IS INVALIB ;OTHERWISE PROCESS DATA CMPI R1, R3^ BLE VALID CMPI R2,^R3^ BGE VALID BR BOSS • ; ; VALID:  ;FLAG - START ;FLAG - STOP  A this point we have a valid flag and will now select which mode the user has chosen for the RCVR. LDP DUAL LDI @MENU OPTION, R1 AND 3h, RT.  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 7 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368  CMPI^1,^R1 BZ MODE1 CMPI 2,^R1 BZ MODE2 CMPI 3,^R1 HZ MODE3 BR VALID  369  ;*******************************************************************  ;^MODE 1  This mode makes the rcvr simply hard decode the data rcvd, place it at slot P1 0,^and send an ACK. No decoding is done since,^it is assumed that no coding was performed.^This mode allows the ser to check the channe conditions of the system with no coding. Requires: RD^real data flag start Modifies: RU,^R1,^R2,^R3,^R4,^R5,^R6,^R7 ARO,^AR1,^AR2 Returns: Nothing  MODEl:  LDP DUAL^ ;insure ACKO is clear LDI 0,^R7 STI R7,^@ACK° LDP CODES LDI @FLAGOP1,^R6^ ;clear slot 0 area of P1 LDI @PACKET1HARDP1,^R7 CALL CLEAR sti rO,^@CURRENT_START  LDI 16,^R1^ ;hard decode flag LDI @FLAGOP1, AR2^;slot to store decoded data CALL HARDDECODE_CHUNK^;decode chunk of length^R1 ;and place starting at AR2  K data  NO_ADJ1:  LDI @CURRENT_START, RO ADDI 10H,^RU^  data  ;transform DQPSK data to QPS  cmpi @CIRC_TOP,^r0 BLT NO_ADJ1 SUBI OFFFh,^RI CALL DQPSK_DEINT LDI @BUFP1, ARO^ LDI @BUFP2, AR1^  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 8  ;Zk value ;Wk value  LDI 512,^R1^ ;hard decode flag LDI @PACKETOHARDP1, AR2^;slot to store decoded  370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423  R1  CALL QPSK1^  ;decode chunk of length ;and place starting at AR2  on  ;Refresh start and stop frame pointers used in flag validati LDI @CURRENT_START, RU STI RU,^@START_FRAME ADDI 21014,^RU LDI @CIRC_TOP, R1 CMPI R1,^RU BLT NO_SUB1 SUBI^100014,^RU  NO_SUB1:STI RI, @STOP_FRAME LOT 1, R1^;send an ACK° to HOST PROGRAM LDP DUAL STI R1,^@ACK° LDP CODES BR BOSS  ; MODE VITERBI DECODE CHANNEL This mode assumes that the frame rcvd contains a flag with 4  96 bits ASM  convolved with a rate 1/2 code given by polynomials in VARS. and constraint length K=5. The frame^32 bits --> flag 992 bits^convolved data 1024 bit frame  MODE2:  LDP DUAL^ ;insure ACED is clear LDI 0,^R7 STI R7,^@ACK° LDP CODES LDI @FLAGOP1,^R6^ ;clear slot 0 area of P1 LDI @PACKET1HARDP1, R7 CALL CLEAR sti rO, @CURRENT_START  LDI 16,^R1^ ;hard decode flag LDI @FLAGOP1, AR2^;slot to store decoded data CALL HARDDECODE_CHUNK^;decode chunk of length = R1 ;and place starting at AR2  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 9 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480  K data  N0_ADJ2:  LDI @CURRENT_START, RD AUDI 10H,^RD  ;transform DQPSK data to QPS  cmpi @CIRC TOP,^r0 BLT NO ADJ SUBI OTFF h,^RD CALL DQPSK_DEINT LDI @BUFP1, ARO LDI @BUFP2, AR1  ;Zk value ;Wk value  LDI^512,^R1 LDI @FLAGOP1, AR2 ADDI 1, AR2 LDI^7,^RU STI RO, @ADDER_ONE_PUNC STI RO,^@ADDER_TWO_PUNC CALL START_VITB  on  ;Refresh start and stop frame pointers used in flag validati LDI @CURRENT START, RD STI RD.^@STAT2T_FRAME ADDI 210H,^RO LOT @CIRC TOP,^R1 CMPI R1,^13-0 BLT NO SUB2 SUBI^1-0-00H,^RD  NO_SUB2:STI RU,^@STOP_FRAME LDI^1,^R1 LDP DUAL STI R1,^PACED LDP CODES BR BOSS LDP DUAL LDI^0,^R7 STI R7,^@ACKO LOP CODES LDI @FLAGOP1,^R6 LDI @PACKET1HARDP1, R7 CALL CLEAR STI RD, @CURRENT_START LDI 496,^R1 ;CALL DATA_CHUNK_FULL ng  ;send an ACED to HOST PROGRAM  ;insure ACED is clear  ;clear slot 0 area of P1  ;496 dibits . 992 bits ;insure all 496 dibits rcvd ;before any further processi  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 10 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538  LOT 16,^R1 LDI @FLAGOP1, AR2  ;hard decode flag  CALL HARDDECODE_CHUNK  K data  LDI @CURRENT_START, RD ADDI 10H, RD  ;NO_ADJ: LDI RD, ARO LOT RO, AR1 ADDI 10008, AR1 LDF STF LDF STF  *ARO++(1)%,^R2 R2,^@OLDI *AR1++(1)%,^R2 R2,^@OLDQ  LDI @BUFP1, AR3 LDI @BUFP2, AR4 LDI 496,^R4 ;MORE:  LDF @OLDI, RD LDF @OLDQ, R1 LDF *ARO++(1)%,^R2 LDF *AR1++(1)%,^R3 PUSH R4 CALL DIFFERENTIAL_PHASE_DECODING POP R4 STF R6,^*AR4++(1)% STF R7,^*AR3++(1)% STF R2,^@OLDI STF R3, @OLDQ SUBI 1,^R4 BP MORE flop LOT @BUFP1, ARO LOT @BUFP2, AR1 LDI 64,^R1 LDI @FLAGOP1, AR2 ADDI 1, AR2 CALL START_VITB  on  ;transform DQPSK data to QPS  cmpi @CIRC_TOP,^r0 BLT NO ADJ SUBI^0-F -EFh,^RD ;real I values ;real Q values ;initialize OLDI & OLDQ  ;I  ;4  ;length to decode  ;Wk LSB ;Zk MSB ;branch symbol ZkWk ;or IQ  ;Zk value ;Wk value  ;Refresh start and stop frame pointers used in flag validati  LDI @CURRENT START, RU STI RD,^@STATt.T_FRAME addi 200h,^r0 cmpi 3200h,^r0 bit NO SUB subi 1T)00h,^r0 ;NO_SUB: sti rO, @STOP_FRAME  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 11 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596  ;SUBI^1,^AR2 ;LDI AR2,^R6 ;STI R6,^@STOP_FRAMF LDI LDP OTT LDP  1, R1^;send an ACK° to HOST PROGRAM DUAL R1,^@ACKO CODES  BR BOSS  ; ; MODE ADAPTIVE CPC DECODING ;^This mode allows the receiver to decode a rate 1/2 header ;^either a rate 1,^3/4 or 1/2 data packet.  MODE3:  LDP DUAL^ ;insure ACED is clear LDI 8888,^R7 STI R7,^@ACK° LDP CODES LDI @FLAGOP1,^R6^ ;clear slot 0 area of P1 LDI @PACKET1HARDP1, R7  CALL CLEAR  STI RU, @CURRENT_START LDI 16, R1^ LDI @FLAGOP1, AR2  ;hard decode flag  CALL HARDDECODE_CHUNK  K data  NO_ADJ:  LDI @CURRENT_START, NO ADDI 10H,^RD^  ;transform DQPSK data to QPS  cmpi @CIRC_TOP,^r0 BLT NO_ADJ SUBI OFFFh,^RD CALL DQPSK_DEINT LOT 9BUFP1, ARO^ LDI @BUFP2, AR1^ LDI^64,^R1 LDI @FLAGOP1,^1R2 ADDI 1, AR2 LDI 3fh,^RU STI NO, @ADDER_ONE_PUNC STI RO, @ADDER_TWO_PUNC  ;Zk value ;Wk value  CALL START_VITB ;HEADER SOFT DECODED AND PLACED 9 300C1--300C2  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 12 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655  ader  LDP LDI LDI LDI LDI LDI AND LSH LDI AND  CODES @PACKETOHARDP1, AR1 *AR1++,^RO *AR1,^R1 R1,^R4 @CRC MASK, R2 R2,^1.4 -5,^R4 31,^R2 R2, Ni  ;R4 . CRC ;mask out TAIL & CRC from he  LDI 9HEADBUF1, AR5 LDI @HIGH MASK, R2 LSH 16, RT AND NO,^R2,^R3 LSH -16,^R3 OR R1, R3 LSH 16,^RD STI RO,^*AR5++ STI R3,^*ARS--  LDP CODES LDI 17,^NO LDI @CRC CCITT,^R1 LDI^2,^R. LDI @HEADBUF2, R3 PUSH PUSH PUSH PUSH PUSH CALL SUBI  R3 92 R1 AR5 RO _polydiv 5,^SP  CMPI RU,^R4 LDINZ 9999,^R1 BNZ NACK  ;if CRC fails send NACK ;otherwise strip info from header ;and decode data packet  ldi @PACKETOHARDP1, AND LDI *++ARO,^RU ;get 2nd word of header ldi rO,^rl AND 3,^RD and 12,^rl LDIZ 9999,^R1 BZ NACK ;if rate is wrong header is NFG LDP DUAL lsh -2,^rl STI Ni,^@RATE ;get rate of data packet sti rO,^@CODE ;get CPCi code to use i=1,^2 LDP CODES  ;^1^- CPC1 ;^2^- CPC2  Oct 6 1993 14:39:55 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715  RCVRADAP.ASM^Page 13  LDI @BUFP1, ARO LOT @BUFP2, AR1 ADDI 64, ARO ADDI 64, AR1 CMPI^1,^R1  BZ RATE1 CMPI 2,^R1 BZ RATE75 CMPI 3,^R1 HZ RATE50 LDI 9999,^R1 BR NACK  RATE1:  LDI 896,^R3 LDI 27,^R4 CMPI^1,^RO  LDIZ 15H,^R1 LDIZ 2AH,^R2 LDIZ 100,^R7 CMPI^2,^RO  RATE75:  LDIZ 2AH,^R1 LDIZ 15H,^R2 LDIZ 200,^R7 BR DECODE LDI^672,^R3 LDI^20,^R4 CMPI^1,^RO  LDIZ 2dh,^131 LDIZ lbh,^R2 LDIZ^100,^R7  RATE50:  CMPI 2,^RI LDIZ 36h,^R1 LDIZ 2dh,^R2 LDIZ 200,^R7 BR DECODE LOT^448,^R3 LDI 13,^R4 CMPI^1,^RU  LDIZ 3fh,^R1 LDIZ 3fh,^R2 LDIZ 100,^R7 CMPI 2,^RU LDIZ 3fh,^R1 LDIZ 3fh,^R2 LDIZ 200,^R7 BR DECODE  ;rate 1 ;rate 3/4 ;rate 1/2  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 14 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775  DECODE:  LDI @PACKETOHARDP1, AR2 ADDI 3, AR2^;leave blank word for CRC calc  STI R1, @ADDER_ONE_PUNC STI R2, @ADDER_TWO_PUNC LDI R3, R1^;BIT LENGTH TO DECODE PUSH R7 PUSH R4 CALL START_VITB ;CRC calculation for data packet LDI @PACKETOHARDP1, AR3 ADDI 2, AR3 LDI 33,^RO LDI @CRC 32,^131 LDI @DATT,BUFP1, R3 POP R4^ LDI R4,^R2 PUSH R4 PUSH PUSH PUSH PUSH PUSH  ;# OF DATA WORDS  R3 R2 R1 AR3 RO  CALL _polydiv SUSI 5,^SP LDI @PACKETOHARDP1, ARO POP R4 ADDI R4, ARO ADDI 2, ARO LDI *ARO,^R1 POP R7 CMPI EU,^R1 LDIZ R7,^R1 HZ ACK LDP DUAL LDI @CODE,^RO LDP CODES LDI @SEQUENCES, R1 CMPI 1,^RU^  ;if rate CPC1 load pointers LDIZ @CPC1I, ARO^ ;and update sequence count LDIZ @CPC1Q, AR1 LDIZ 1,^R2 CMPI 2,^RU^  ;if rate CPC2 load pointers LDIZ @CPC2I, ARO^ ;and update sequence count LDIZ @CPC2Q, AR1 LDIZ 2,^E2  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 15 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828  OR R2,^R1 STI R1,^@SEQUENCES^;write sequence count ;save CPCx code to appropriate slot for possible combination  a packet ng  LDI @BUFP1, AR2 LDI @BUFP2,^AR3 ADDI 64, AR2^  ;point to real values of dat  ADDI 64, AR3 LOP *AR2++,^SO^  ;preload registers for copyi  LDP *APO++, R1 LDI lffh, RC^ RPTB COPY_SEQUENCE  ;copy 512 WORDS  ;ldf^*ar2++,^r0 ;ldf^*ar0,^rl ;addf^rO,^rl ;stf rl,^*ar0++ ;ldf^*ar3++,^r0 ;ldf^*arl,^rl ;addf rO,^rl ;COPY_SEQUENCE:^stf rl,^*arl++ ning  ;The above commented out instructions are used in Code Combi  LDF *AR2++, ^SO IISTF RO,^*ARO++ COPY_SEQUENCE: LDF *AR3++, ^51 IISTF R1,^*AR1++ . ;currently rcvd data packet placed in CPC1 or CPC2 slot LDI @SEQUENCES,^SO  uences  decode ointers  ues  CMPI^3,^RO LDINZ 6666,^51^ BNZ NACK^  ;combine CPC1 and CPC2 LDI 32,^RO^  ;do we have at least two seq ;to combine ;NO - send NACK ;YES - combine sequences and ;initialize all necessary p  STI SO,^@PUNC_COLUMN^;and variables for combining LDI lbh,^SO^ LDI 2dh,^R1 LDI 36h,^R2 LDI^15h,^R3 LDI 2ah,^R4 ldi^3fh,^r5  ;CPC1 and CPC2 I and Q val  Oct 6 1993 14:39:55^RCVRADAP.ASM 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888  Page 16  LDP DUAL LDI BRATS, R7 ldp CODES CMPI 1,^R7 BZ RATE1A CMPI 2,^R7 BZ RATE75A CMPI 3,^R7 BZ RATE50A RATE1A:  RATE75A:  RATE50A:  STI 53, @ADDER_ONE_PUNC STI 54, @ADDER_TWO PUNC STI R4, @ADDER_1PRIME_PUNC STI R3, @ADDER_2PRIME_PUNC LDI 896,^RC LDI 27,^R2 BR CONTINUE STI R1, @ADDER_ONE_PUNC STI RO, @ADDER_TWO PUNC STI R2, @ADDER_1PRTM E_PUNC STI 51, OADDER_2PRIME_PUNC LDI 672,^RC LDI 20,^R2 BR CONTINUE  STI R5, @ADDER_ONE_PUNC STI R5, @ADDER_TWO PUNC STI R5, @ADDER_1PRYME_PUNC STI R5, @ADDER_2PRIME_PUNC LDI 448,^RC LDI 13,^R2 BE CONTINUE CONTINUE: PUSH R2 LDI @CPC1I, ARO LDI @CPC1Q, AR1 LDI @CPC2I,^A52 LDI @CPC2Q, AR3 LDI 9BUFP1, AR4 LDI @BUFP2, ARS ;combine 512 words for each I and Q RPTB COMBINE LDI @PUNC COLUMN, 51 MPYI 2, RT CMPI 64,^51 LDIZ 1,^R1 sti rl, @PUNC_COLUMN TSTB OADDER_ONE_PUNC, R1 LDFZ 0,^R2 BZ OVER1 LDF *ARO++, R2  OVER1:^TSTB OADDER_1PRIME_PUNC, R1 LDFZ 0,^R3 BZ OVER2  ;R2^. Ii  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 17 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948  LDF *AR2++,^R3^  ;R3 - 12  OVER2:^TSTB @ADDER_TWO_PUNC, R1 LDFZ 0,^R4 BZ OVER3 LDF *AR1++,^R4^  ;R4 = Ql  OVER3:^TSTB @ADDER_2PRIME_PUNC, R1 LDFZ 0,^R5 BZ OVER4 LDF *AR3++,^R5^  ;R5 = Q2  OVER4:  ADDF R2,^R3 ADDF R4,^R5  STF R3,^*AR4++ COMBINE:STF R5,^*AR5++ ;clear memory at PACKETOHARDP1 LDI @PACKETOHARDP1, R6 ADDI 3,^R6 LDI @PACKET1HARDP1, R7 CALL CLEAR ;viterbi decode rate 1/2 combined sequences ldp CODES ldi @BUFP1,^ar0 ldi @BUFP2,^AR1 ldi @PACKETOHARDP1,^ar2 addi 3,^ar2 LDI^3fh,^RU STI RU, @ADDER_ONE_PUNC STI RU, @ADDER_TWO_PUNC LDP DUAL LDI @RATE, R7 ldp CODES CMPI 1,^R7 ldiz^896,^rl CMPI 2,^R7 ldiz^672,^rl CMPI 3,^R7 ldiz^448,^rl CALL START_VITB ;check CRC again ;CRC calculation for data packet LDI @PACKETOHARDP1, AR3 ADDI 2, AR3 LDI^33,^RU  Oct 6 1993 14:39:55^RCVRADAP.ASM 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 939 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007  Page 18  LDI @CRC_32,^R1 LDI @DATABUFP1, R3 POP R2 PUSH R2 PUSH PUSH PUSH PUSH PUSH  R3 R2 R1 AR3 RU  CALL _polydiv SUBI 5,^SP LDI @PACKETOHARDP1, ARO POP R2 ADDI R2, ARO ADDI 2, ARO LDI *ARO,^R1 and @MASK1,^r0 and @MASK1,^rl CMPI RU,^R1 BZ CLEAN_COMBINE LDI^6666,^R1 BR HACK CLEAN_COMBINE: LDP CODES LDI^0,^R1 STI R1,^@SEQUENCES LDI^300,^R1 BR ACK  on ACK:  ;Refresh start and stop frame pointers used in flag validati ;LDI 1,^R1 LOP DUAL STI R1,^@ACK° LDP CODES ldi 8BUFP1,^r6 ldi r6,^r7 addi Oeffh,^r7 call CLEARFLOAT ldi @CPC2Q,^r6 ldi r6,^r7 addi 300h,^r7 call CLEARFLOAT  CLEANER:  LDI @CURRENT START, RU STI RU,^@STAFT .T_FRAME addi 210h,^r0 ldi @CIRC_TOP,^rl cmpi rl,^r0 bit NO SUB subi 100h,^r0  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 19 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063  NO_SUB: sti rO,^@STOP_FRAME BR BOSS NACK:  ;LDI 9999, R1^;send an NACKO to HOST PROGRAM LDP DUAL STI R1,^@ACK° LDP CODES cmpi^6666,^rl bz CLEANER ;BR POLIZIA BR BOSS  ;******************************************************************* * ; This section of code is responsible for hard decoding a chun k of data given: ; ; Requires: ; RD^= start of real data I channel R1^. length to decode in Dibits ; ; AR2 . where to place hard data ; Modifies: R1,^R2,^R3,^R4,^R5,^R6,^R7 ; ARO, AR1,^AR2 ; Returns: ; Nothing ; HARDDECODE CHUNK: L]:)-^0,^R2 STF R2,^@OLDI^ STF R2,^@OLDQ ref ptr  ;initialize OLDI & OLDQ  LDI RO, AR7^  ;store flag start for future  LDI NO, ARO^ LDI RO, AR1^  ;ARO . I channel pointer ;add offset to get Q channel  ADDI 1000H, AR1^ LDI 16,^R4^  ;AR1 = Q channel pointer ;R4 . dibit count  ldf^*ar0++(1)%,^r2 stf r2,^@OLDI ldf^*arl++(1)%,^r2 stf r2,^@OLDQ MORE_DIBITS: ldi 8TROUBLE2,^ar3 LOT ARO,^R2 LDI AR1,^R3 sti^r2,^*ar3++ sti^r3,^*ar3++ ldf^*ar0,^r2 ldf^*arl,^r3 stf^r2,^*ar3++  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 20 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 _  stf r3,^*ar3++ LDF *ARO++(1)%,^R2^ IILDF *AR1++(1)%,^R3^ ;ldi @TROUBLE2,^ar3 stf r2,^*ar3++ stf r3,^*ar3++ ldf @OLDI,^r5 stf r5,^*ar3++ ldf OOLDQ,^r5 stf r5,^*ar3  ion  ;load real data I ;and Q  PUSH R1 PUSH R4 ldf @OLDI,^r0 ldf @OLDQ,^rl CALL HARDDECODE^  ;hard decode it  POP POP STF STF  ;refresh OLDI & OLDQ  R4 R1 R2,^@OLDI R3,^@OLDQ^  LDI *AR2,^R2^  ;place dibit @ current boat  LSH -2,^R2 LSH 30,^NO OR RU, R2 STI R2,^*AR2 SUBI 1, R4^ BNZ NO_MEM INC ADDI 1, A.^ irt LDI 16,^R4^  NO_MEM_INC: SUBI 1,^R1^ BNZ MORE_DIBITS^ RETS^  ;decrement dibit count ;increment memory pointer ;reset dibit count ;length . 0^? ;no, branch back ;yes,^return  ;******************************************************************* * ;^This section of code checks to insure that the necessary dat a ;^chunk has ALL been rcvd (real data) before any further proce ssing ;^done ;^Requires: ;^ RU . start of flag pointer ;^ R1 . # of dibits that chunk consists of ;^Modifies: ;^ R1,^R2 ;^Returns: ;^ Nothing DATA_CHUNK FULL: LOT RO, R2  ___^,  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page, 21 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129  1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175  ;ADDI 16,^R2^ nter GO:  WAIT2:  WAIT:  GETOUT: eft loop  ADDI R1, R2^  ;R2 . start of data chunk ;R2 now contains address poi ;for last dibit  ;cmpi @CIRC TOP,^r2 S1,^r2 cmpi @CIRCLES bit WAIT2 subi OFFFh,^r2  ;reached last dibit^? ;no,^then wait  ldi 9TROUBLE3, ar0^;debug code to check when 1 sti^rl,^*ar0++ ldi rl,^arl ldf *arl,^rl sti rl,^*ar0 RETS^  1176 1177 1178 1179 1180 1181 1182 1183 1184  ldi @REAL_IBIT_POINTER, rl cmpi r2,^rl bnz WAIT2  ;LDI @REAL IBIT_POINTER, R1 ;CMPI R2,^lil^ ;BLT WAIT^  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 22  ;yes,^then return  ;******************************************************************* *** ;^This section of code is responsible for decoding the differe ntial ;^phase from the real data. ^It operates on the real data from ;^the I and Q channel and outputs real data which is no longer ;^dependent on the previous real data.^That is it transforms ;^pi/4 - DQPSK real data to QPSK real data for hard decoding. ;^The mapping of this transform is given by Wk and Zk. ; ;^Requires ;^RI . oldI ;^R1 = oldQ ;^R2 . newI ;^R3 = newQ ;^Modifies: ;^R4,^R5,^R6,^R7 ;^Returns: ;^R6 = Wk . oldI * newI + oldQ * newQ ;^R7 . Zk = oldI * newQ - oldQ * newI ; DIFFERENTIAL PHASE DECODING: MPYF^RI,^1-22,^R4^ ;R4 = oldI * newI MPYF3 R1,^R3,^R5^ ;R5 . oldQ * newQ ADDF R4,^R5,^R6^ ;R6 . R4 + R5 MPYF3 R1,^R2,^R4^ ;R4 = oldQ * newI  1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233  MPYF3 RO, R3,^R5^ ;R5 = oldI * newQ SUBF R4,^R5,^R7^ ;R7 . R5 - R4 ;At this point R6 . Wk and R7 = Zk RETS ;******************************************************************* *** ;^This section of code is responsible for the actual hard deco ding ;^It references Wk and Zk and uses these real values to decide ;^which dibit was sent. ;^Requires ;^RO = oldI ;^R1 . oldQ ;^R2 . newI ;^R3 . newQ ;^R6 = Wk ;^R7 . Zk ;^Modifies: ;^RI,^R4,^R5,^R6,^R7 ;^Returns: ;^RI . dibit received HARDDECODE: CALL DIFFERENTIAL_PHASE_DECODING ;if^(Wk > 0 & Zk > 0) CMPF 0,^R6 BLE Li CMPF 0,^R7 BLE Li ; dibit is decoded as 3 LDI 3,^RO RETS Li:^;else if^(Wk > 0 & Zk < 0) CMPF 0, R6 BLE L2 CMPF 0, R7 BGE L2 ;dibit is decoded as a 2 LDI 2,^RI REIS L2:  ;else^if^((6k <^0^&^Zk > 0) CMPF 0,^R6 BGE L3 CMPF 0,^R7 BLE L3 ;dibit is decoded as a 1 LDI 1,^RI RETS  L3:  ;Otherwise dibit is decoded as a 0 LOT 0,^RI RETS  7 *******************************************************************  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 23 ***  1234  1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285  ;^This section of code uses a shift register which is shifted and ORed ;^with the most recent decoded dibit.^This register is then ;^compared to the flag and if it matches the address which poi nts ;^to the occurrence of this flag (in real data)^is saved in ;^the FLAG_ADDRESS_TABLE. ; ;^Requires: ;^RO = contains most recent decoded dibit ;^Modifies: ;^RO,^R1,^AR2 ;^Returns: ;^Nothing FLAG_CHECKER: LDI @FLAG TO_BE, R1 ^;load current decoded word LSH -2, RI^ ;shift word right by 2 LSH 30,^RO^ ;shift dibit left by 30 OR RO, R1^ ;OR dibit with current word STI R1,^@FLAG_TO_BE lsh -8,^R1 n  CMPI @FLAG_COMP, R1 ^;compare word to flag patter ;BNZ ENDS BNZ^CORRELATE^;if no match,^then return  FLAG_FOUND: LDI @FLAG_ADDRESS_TABLE, AR2^;yes,^flag found g end  ed  LDI @REAL_IBIT_POINTER,^RD^;get address location of fla STI RO,^*AR2++^ ;store in FLAG_ADDRESS_TABLE LDI AR2,^RO CMPI @TABLE_BOTTOM, RO^;if FLAG_ADDRESS_TABLE reach  BNZ UPDATE_TABLE^ ;bottom of buffer LDI @TABLE_TOP,^RO^;reset to top of buffer UPDATE_TABLE: STI RO, @FLAG_ADDRESS_TABLE ENDS:^RETS CORRELATE: LDI @FLAG COMP, R2 XOR R1,^R,^R3^ NOT R3,^R4^ LDI 0,^R5^ its LDI 0,^R6^ its LDI 24,^R7^ TEST: TSTB 1,^R3 BZ LOOK_POS ADDI 1,^R5 LOOK_POS:  ;R3^. negative l's ;R4 . positive l's ;R5 . number of negative 1 b ;R6 = number of positive 1 b ;correlate for 24 bit length  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 24 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342  OVER:  TSTB 1,^R4 BZ OVER ADDI 1,^R6 LSH -1,^R3 LSH -1,^R4 SUBI 1,^R7 BP TEST  SUSI R5,^R6 CMPI @THRESHOLD, R6 BGE FLAG_FOUND BR ENDS ;.****************************************************************** ;^This section of code is responsible for hard decoding a chun k ;^data given: ;^Requires: ;^ARO^. start of MSB data Zk Q ;^AR1^= start of LOB data Wk I ;^R1^. length to decode in Dibits ;^AR2 = where to place hard data ;^Modifies: ;^R1,^R2,^R3,^R4,^R5,^R6,^R7 ;^ARO,^AR1,^AR2 ;^Returns: ;^ Nothing QPSK1: LDI 16,^R4^ MORE_DIBITS1: LDF *ARO++,^R7^ IILDF *AR1++,^R6^ PUSH R1 PUSH R4 CALL QPSK2^  ;R4 = dibit count ;load real data MSB ;and LSB  ;hard decode it  POP R4 POP R1 ion  LDI *AR2,^R2^  ;place dibit @ current locat  LSH -2,^R2 LSH 30,^RO OR RU,^R2 STI R2,^*AR2 SUBI 1,^R4^ BNZ NO_MEM INC1 ADDI 1, ARI^ LDI 16,^R4^  ;decrement dibit count ;increment memory pointer ;reset dibit count  NO_MEM_INC1: SUBI 1,^R1^ ;length . 0 ? BNZ MORE_DIBIT51^ ;no, branch back RETS^ ;yes,^return  . . _.  ; *****.************************************************************* -^  Oct 6 1993 14:39:55^RCVRADAP.ASM^Pee 25 *** 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399  ; ding ; ; ; ; ; ; ; ; ; ; ; QPSK2:  L11:  L12:  This section of code is responsible for the actual hard deco It references Wk and Zk and uses these real values to decide which dibit was sent. Requires  R6 = Wk R7 . Zk Modifies: R6,^R7 Returns: RI . dibit received ;if^(Wk >^0^&^Zk > 0) CMPF 0,^R6 BLE L11 CMPF 0,^R7 BLE Lll ;^dibit is decoded as 3 LDI^3,^NO RETS ;else^if^(Wk >.^0^& Zk <^0) CMPF 0,^R6 BLE L12 CMPF 0,^R7 BGE L12 ;dibit is decoded as a 2 LDI^2,^RO RETS ;else^if^(Wk <^0 & Zk a 0) CMPF 0,^R6 BCE L13 CMPF 0,^R7 BLE L13 ;dibit is decoded as a 1 LDI^1,^RO RETS  L13:  ;Otherwise dibit is decoded as a 0 LDI^0,^RO RETS ;******************************************************************. ** ; ; This code transforms real DQPSK data to real QPSK data and ; then deinterleaves the data placing it 880FP1 and @BUFP2 ; for either hard decoding by QPSK or soft decoding. ; ; ; Requires: ; RO . start address of real I data in receiver buffer ; ; Returns: ; BUFP1 contains Zk real values MSB ; BUFP2 contains Wk real values LSB ; -^--  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 26 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459  ;^Deinterleaver currently set for 256 bit blocks ;^which is 8 ROWS by 16 COLUMNS of SYMBOLS ;^can handle up to 256 bit block if a larger ;^size is required the DSP board requires more memory ;^to handle the operation and FREE1 and FREE2 should be ;^changed to reflect the increase in memory as well as ;^the MAP.CMD file used for compiling and linking. DQPSK_DEINT: LOT RO, ARO^ ;real I values LOT NO, AR1 ADDI 1000H, AR1^ ;real Q values LDF STF LDF STF  *ARO++(1)%,^R2 R2,^@OLDI^ *AR1++(1)%,^R2 R2,^@OLDQ  ;initialize OLDI & OLDQ  LOT @BUFP1,^AR3^ LOT @BUFP2, AR4^ ldi^512,^r4 ;LOT 496,^R4^ MORE:  ;I ;4 ;length to decode  LDF @OLDI,^RO LDF @OLDQ, R1 LDF *ARO++(1)%,^R2 LDF *AR1++(1)%,^R3 PUSH R4 CALL DIFFERENTIAL_PHASE_DECODING POP R4 STF R6,^*AR4++(1)%^ STF R7,^*AR3++(1)%^ STF R2,^@OLDI STF R3,^@OLDQ SUBI 1,^R4 BP MORE  ;Wk LSB ;Zk MSB ;branch symbol ZkWk ;or IQ  ;AT THIS POINT Zk VALUES ARE AT @BUFP1 AND Wk AT @BUFP2 ;DEINTERLEAVE THE DATA LOT @FREE1,^R6 LOT R6,^R7 ADDI 600H,^R7 CALL CLEARFLOAT LDI LDI LDI LDI  @BUFP1, @BUFP2, @FREE1, @FREE2,  ARO AR1 AR2 AR3  LDI 0,^RI^ KEEP_DEINT: LDI^0,^R1^  ;RO is block count ‹. 8 ;R1^. ROW .^0,1,2,3  Oct 6 1993 14:39:55 ^RCVRADAP.ASM^Page 27 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515  SYMBOL:  LDI^0,^R2^  ;R2^= COLUMN =^0,1,2,3,..,15  LDI R2,^R3^ MPYI DEINT ROW, R3 AUDI R1,^" irt LDI R3,^IRO  ;R3 . SYMBOL  LDF *ARO++,^R4^ ;pick the symbol from interleav  ed  LDF *AR1++,^R5^ ;buffer and place in deinterlea  ved  STF R4,^*+AR2(IRO)^ STF R5,^*+AR3(IRO)  ;buffer  AUDI 1,^R2^ CMPI 16,^R2^ BNZ SYMBOL  ;COLUMN++ ;IF COLUMN<=15 GOT() SYMBOL  ADDI^1,^R1^ LDI 0,^R2^ CMPI DEINT_ROW, R1 BNZ SYMBOL^  ;ROW++ ;COLUMN . 0 ;IF ROW<=3 GOTO SYMBOL  ;1 128BIT BLOCK DEINTERLEAVED AND READY TO BE COPIED BACK ;TO THE BUFFER IT CAME FROM  @BUFP2  LDI @BUFP1, ARO LDI @BUFP2,^AR1 LDI RO,^R1 MPYI DEINT BLOCK, R1 ADDI R1, A50^ AUDI Ni, AR1  LDF *AR2++,^R6 LDF *AR3++,^R7^ ock below ldi DEINT BLOCK,^RC SUBI 1,^RE RPTB DEINT  DEINT:  ;Adjust the pointers @BUFP1,  LDF *AR2++,^R6 IISTF R6,^*ARO++ LDF *AR3++,^R7 IISTF R7,^*AR1++ ;clear @FREE1 and @FREE2 LOT @FREE1,^Ni LOT R6,^R7 ADDI^600H,^R7 CALL CLEARFLOAT LDI LDI LDI LDI  @BUFP1, @BUFP2, @FREE1, @FREE2,  ARO AR1 AR2 AR3  ;preload registers before bl ;is executed  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 28 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572  ADDI 1, NO^ LDI NO,^R3 MPYI DEINT BLOCK, R3 ADDI R3, A170 ADDI R3, AR1 INT  CMPI BLOCKS, NO^  ;BLOCK COUNT++  ;BLOCK COUNT<=7 KEEP DE  BNZ KEEP_DEINT  ;******************************************************************* ** ;^This is the beginning of the Viterbi decoding algorithm.  START_VITB: LDP CODES LDI 32,^RI STI RI, @PUNC_COLUMN LDI 2,^NO STI NO,^@DEEP^ ize trellis LDI 0,^RO STI NI, @FORCE_END_ZEROS subi 4,^rl^ PUNC: LDI 0,^NO CMPI 5,^R1 LDILE OFFFFH, NO STI RO, @FORCE_END_ZEROS LDI @PUNC COLUMN, RO MPYI 2,^RT) CMPI 64,^NO LDIZ 1,^NO STI RO,^@PUNC COLUMN TOTS @ADDER_ORE _PUNC, NO LDFZ 0,^R2^ BZ GET_Q_VALUE LDF *ARO++,^R2^ GET_Q_VALUE: TSTB @ADDER_TWO_PUNC, RI LDFZ 0,^R3^ BZ SKIP OVER LDF *ARY+ +, R3^  ;used to intial  ;length-4  ;stuff zero as I value ;get I value from data  ;stuff zero as Q value ;get real Q value from data  ;LDF *ARO++(IRO),^R2^;get real I value ;LDF *AR1++(IR1),^R3^;get real Q value SKIP_OVER: ,.^....  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 29 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626  is  LDI^16,^RO LOT @FORCE_END_ZEROS, R4  ;force zero for last 5 symbo  LDINZ 16,^RO STI RI,^@PATH ;LDFNZ^-7.07E-1,^R3  _vitb deep. e Sal  TOP:  LDI @DEEP,^RI CMPI 16,^RI BLE INIT_VITB  ;if trellis is not initialized ;4 branches deep then call mit  ;At this point the Viterbi Decoder is initialized 4 branches ;That is there are 16 survivors and now we can go through th  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 30 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639  ;repeat process of looking at all 32 paths, ^calculating part  1640 1641  ;metrics,^and decoding.  1642  LDI^0,^RO ;^SUBI^4,^R1  LDI rO,^R4 base addr MPYI 7,^R4 LDI @STATE TABLE, AR3 ADDI R4, ATO LDF *++AR3,^R4 LDF *++AR3,^R5 LDF *++AR3(2),^R6 LDF *++AR3,^R7 ;This is the short cut metric ;^MPYF R2,^R4 ;^MPYF R3,^R5 ;^ADDF R4,^R5 negf r5 MPYF R2,^R6 MPYF R3,^R7 ADDF R6,^R7 ;^negf r7 ;This is the distance squared subf r2,^r4 subf r3,^r5 mpyf r4,^r4 mpyf r5,^r5 addf r4,^r5 subf subf mpyf mpyf addf  r2,^r6 r3,^r7 r6,^r6 r7,^r7 r6,^r7  ;R1 = length - 4 ;calculate offset to add to  ;add offset to base addr ;^Ri'Rq' ;R4 = Ri'^0 ^ 0 ;R5^= Rq'^/ ;^ / ;R6 = Ri"^/^Ri"Rq" ;R7 = Rq"^0/  ;R5 = top partial metric  ;R7 = bottom partial metric  1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681  state us state  ldi^*-ar3(2),^r4 ldi^*+ar3,^r6  ;top partial metric previous ;lower partial metric previo  PUSHF R3 PUSH R3 PUSHF R2 PUSH R2 CALL FIND_CORRECT_SURV  h ch ch  ;CMPF R5,^R7 ;BGT UPPER_BRANCH  ;R7 - R5 ;R7 > R5 choose upper branc  ;LDI *++AR3,^R4  ;R7 < R5^choose lower bran  ;CALL FIND_CORRECT_SURV  ;R5 >= R7 choose lower bran  ONWARD: POP R2 POPF R2 POP R3 POPF R3 ADDI 1,^NO CMPI @PATH,^RO BN TOP LDI @SURV_STATE TABLE, AR4 LDI @NEXT 16_SUV, AR5 LDI^15,^li. RPTB BLOCKS  ;repeat for all 32 paths  ;update survivors  LDI *AR5++,^R2 STI R2,^*AR4++ LDF *AR5++,^R2 STF R2,^*AR4++ LDI *AR5++,^R2 STI R2,^*AR4++ BLOCKS: ADDI 1, AR4  LOT @SURV_STATE_TABLE, AR3 LDI 15, RC LDF *++AR3,^R2 ldi ar3,^ar4 RPTB BLOCKS LDF *++AR3(4),^R3 CMPF R3, R2 LDFGT R3, R2 BLOCK6: LDIGT AR3, AM  ;find smallest accum metric ;R2 = accumulated metric ;ar4 = address of min metric ;R2-R3 ;R2 > R3 so take r3 as min  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 31 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736  metric Y  ;At this point R2 . minimum metric & AR4 the address of this  LDI *--AR4,^R3^  ;R3 = output bit path histor  AND 1,^R3^  ;R3 = output bit  LDI @BIT COUNT, R4 LOB R4,^1723 ldi^*ar2,^r5 OR R3,^r5 sti^r5,^*ar2 ADDI 1,^R4 CMPI 32,^R4 BNZ NO_BIT_COUNT_RESET LDIZ 0,^R4 ADDI 1,^AR2 NO_BIT_COUNT RESET: STI 17(4,^@BIT_COUNT  SUBI^1,^R1^ last  ;length -1 ;could add force to zero for ;5 data bits????  BNZ PUNC ding  1755 1756 1757 1758 1759 1760 1761 1762 1763  LDI *AR4,^R3^  1764 1765  ;NEGI R4,^R5^ LDI R3,^R6  CLOSE:  1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754  ;Input data is finished so clean up and wrap up Viterbi deco  LSH -1,^R3^  utput  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 32  ;get path history ;lose first bit which was ;output just above ;negate bit count  ;addi^1,^r4 LSH R4,^R3^ ldi *ar2,^r7^ OR R3,^r7 sti^r7,^*ar2++  ;shift path history ;before writing to buffer  LDI 33,^r5^  ;check if any more bits to o  SUBI R5,^R4 bp CLOSE ldi^*ar2,^r7 LSH R4,^R6 OR R6,^r7 sti^r7,^*ar2 ;reset the survivor table to original values ;ldi^*+ar4,^r6 ;ldi @TROUBLE6,^ar4 ;sti^r6, *ar4 LDI @SURV STATE_TABLE, AR3 LDI 15,^RE  1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791  LDI 0,^R2 LDF 0,^R3 RPTB BLOCK7 STI STF STI BLOCK7: STI  R2,^*AR3++ R3,^*AR3++ R2,^*AR3++ R2,^*AR3++  LDI^-27,^R2 STI R2,^@BIT_COUNT RETS  er  ;This section of code is usedto initialize the viterbi decod  INIT_VITB: LDI @STATE TABLE, AR4 TOP2:  urvivor a match metric  LDI @SURV_TATE_TABLE, AR3 LDI 0,^RD  ;ADDI 1,^AR2 LDI^*+AR3(2),^R6  ;get last state of current s  LDI^*++AR4(3),^R7  ;compare to state table for  CMPI R6,^R7 CALLZ INIT_METRIC  ;if matches calculate branch  LDI^*++AR4(3),^R7 CMPI R6,^R7 CALLZ INIT_METRIC  ;repeat for lower branch  ADDI 1,^RO CMPI 16,^NO addi 1,^an BNZ TOP2 LDI @SURV_STATE_TABLE, AR3 LDI 0,^R3 LDI 15,^RC RPTB BLOCK2 LDI^*++AR3(3),^R2 STI R3,^*AR3 STI R2,^*-AR3 BLOCK2: ADDS 1, AR3  for  ;copy next state fields to ;last state fields of ;SURV_STATE_TABLE  LDI @DEEP,^R2  ;make sure the proper number  MPYI 2,^R2  ;of survivors is initialized  STI R2,^@DEEP  ;the first 4 branches ;will^be^(2,^4,^8,^16)  CMPI 16,^R2 BGT PUNC  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 33 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845  survivor  MPYI 2,^R2  LDI @SURV STATE_TABLE, AR3 LDI AR3,^T:R4 ADDI R2, AR4 LDI *AR3++,^R3 SUBI 1,^R2 RPTS R2 LDI *AR3++,^R3 IISTI^R3,^*AR4++ BR PUNC  ;copy all 5 fields for each  ;go back for more data  INIT_METRIC; LDF *-AR4(2),^R4 LDF *-AR4, R5 ;MPYF R2,^R4 ;MPYF R3,^R5 ;ADDF R4,^R5 c ;negf r5 cuff cuff mpyf mpyf addf tic of  >=8  or  ;R5 . partial metri  r2,^r4 r3,^r5 r4,^r4 r5,^r5 r4,^r5  LDF ***AR3,^R4 mpyf BETA,^r4 mpyf ONE_MINUS_BETA, r5  metric  ;R4 . state table I ;R5 . state table Q  ;get accumulated met ;current survivor  ADDF R4,^R5 STF R5,^*AR3  ;add branch metric ;update accumulated  LDI^*--AR3,^R4 LSH -1,^R4 LDI 0,^R5 CMPI 8,^RO  ;get output history ;R4 » 1 ;output^"0" ;if RClecurrenc state  LDIGE @BIT_MASK, R5 OR R5,^R4 STI R4,^*AR3  ;then output^"1"  STI RO,^*++AR3(3)  ;save next state  ADDI 1, AR3  ;move to next surviv  ;update path history  RETS  ;This next section is used to find the correct survivor FIND_CORRECT_SURV: ;R4 last state for top partial metric ;R5 top partial metric ;R6 last state for lower partial metric  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 34 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898  ;R7 lower partial metric LDI 15,^RC LDI @SURV STATE TABLE, AR4 LDI^*++AR74( 2),^TR.-3 RPTB BLOCK4  anch branch  ;load last state of SURV  CMPI R4, R3  ;cmp to last state of top br  ldiz ar4,^ar5 cmpi r6,^r3  ;top branch ;cmp to last state of lower  ldiz ar4,^ar6  ;lower branch  NOP BLOCK4:^LDI *++AR4(4),^R3  ;get next last state  ;ARS address of last state for top branch ;AR6 address of last state for lower branch LDF *-AR5, R4 mpyf BETA, r4 mpyf ONE_MINUS_BETA, r5 anch met  ADDF R4, R5  ;r5=accum metric with top br  LDF *-AR6,^R6 mpyf BETA, r6 mpyf ONE_MINUS_BETA, r7 ADDF R6, R7 branch met  5 R7  ;R7=accum metric with lower  CMPF R5,^R7  ;^R7 - R5  BGT UPPER_BRANCH  ;R7 > R5 choose top branch R  ldi ar6,^ar4  ;R5 > R7 choose lower branch  CALL UPDATE_SURV REIS  UPDATE_SURV: ;we have the correct survivor so now we update it ;R7 = accumulated metric ;ar4= last state SURV_TABLE LDI @NEXT 16_SURV, AR5 LDI RO, lj MPYI 3,^R3 o base add ADDI R3, AR5 STF R7,^*+AR5  ;get offset to add t  ;save annum metric  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 35 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957  ;save bit LDI^*-AR4(2),^R5 LSH -1^,^R5 LDI^0,^R6 CMPI 8,^RO LDIGE @BIT_MASK, R6 OR R6,^R5 STI R5,^*ARS^ STI RO,^*+AR5(2)^ RETS  UPPER BRANCH: ldf r5,^r7^ LDI AR5, AR4^ CALL UPDATE_SURV RETS  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 36 1958 1959 1960 1961  ;save past history ;save last state  ;R5 metric in R7 ;choose upper branch  Interrupt 1 is responsible for obtaining real data from the I and Q channels and then hard decoding each dibit while simultaneously searching for the occurence of a flag. Interrupt 1 occurs once every symbol duration time period. Currently a symbol lasts for: 6 *^6.6micros . 39.6 micros 39.6ms/60ns^= 660^instructions This allows for the execution of 660 instructions between interrupt trigger times. Currently this interrupt consists of ^xx instructions giving rise^to^: 660 - xx = yy instructions of main code. Requires: Nothing Modifies: RO,^R1,^R2,^R3,^R4,^R5,^R6,^R7 ARO,^AR1,^AR2 Returns: Nothing  1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013  ;******************************************************************* *** RCV: F  PUSH ST^  ;IMPORTANT MUST USE OTHERWISE REST 0  ;PROGRAM WILL NOT WORK PROPERLY XOR 2000H,^ST^;disable interrupts PUSH DP^ push push push push push push push push push  ;save register contents  ir0 irl bk ie if iof rs re rc  PUSH RO pushf r0 PUSH R1 pushf rl PUSH R2 pushf r2 PUSH R3 pushf r3 PUSH R4 pushf r4 PUSH R5 pushf r5 PUSH R6 pushf r6 PUSH R7 pushf r7 PUSH ARO PUSH AR1 PUSH AR2 LDP LDI LDI LOT LLD'  float  CODES @ADCHANA1, ARO^;read I channel 8ADCHANB1, AR1^;read Q channel *ARO, RO *AR1, R1  ash -16,^r0 ash -16,^rl FLOAT RO, R2^  MPYF @SCALE, R2^ MPYF @SCALE, R3  t  ;convert A to D hex value to  FLOAT R1,^R3 ;scale float value down  At this point R2 and R3 contain a scaled down floating poin ..^;,...  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 37 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2060  ;representaion of the I and Q channel just read d Q  LDI @REAL_IBIT_POINTER, ARO ^;get current pointer to I an LDI @REAL_QBIT_POINTER, AR1 ^;real data STF R2,^*ARO++(1)%^;save real value I and Q in STF R3,^*AR1++(1)%^;circular memory  a  rence  ountered  STI ARO,^@REAL_IBIT_POINTER^;update pointers to real dat STI AR1, @REAL_QBIT_POINTER ldf @OLDI_INT,^r0 ldf @OLDQ_INT,^rl CALL HARDDECODE^ ;decode current dibit STF R2,^@OLDI_INT^ ;save current dibit for refe STF R3,^@OLDQ_INT^ ;by the next future dibit CALL FLAG_CHECKER^ ;checks if flag has been enc POP AR2 POP AR1 POP ARO popf r7 POP R7 popf r6 POP R6 popf r5 POP R5 popf r4 POP R4 popf r3 POP R3 popf r2 POP R2 popf rl POP R1 popf r0 POP RI pop pop pop pop pop pop pop pop pop  rc re rs iof if ie bk in ir0  POP DP POP ST OR 2000h,^ST RETI ;******************************************************************* ********  Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 38 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2080 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103  ;^All other interrupts simply return NO:^RETI ;******************************************************************* ******* ;^This section clears memory chunks specified by ARO --> AR1 CLEAR: SUBI R6,^R7 LDIN 1,^R7 BN ERROR LDI R6,^ARO LDI 0,^R6 RPTS R7 STI R6,^*ARO++ REPS ;******************************************************************* ******* ERROR: LDP DUAL STI R7, @ERROR_NUM DEAD:^BR DEAD ;******************************************************************* ****** ;^This section clears memory chunks specified by ARO --> AR1 CLEARFLOAT: SUBI R6,^E7 LDIN 1, R7 BN ERROR LDI R6, ARO LDF 0,^R6 RPTS R7 STF R6,^*ARO++ REPS  .end  Oct 7199301:57:01^VARSRCVR.ASM^Pa g e 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59  VARS.asm^V1.00^JAN 93 ,-^This file is used to set variables which are constantly ,•^used throughout the assembly section of the code. ,• .text STACK_SIZE^.set^400h^;size of system stack FP^.set^AR3^;frame pointer DELTA^.set^2^;amount to jump in SIN table INITIAL^.set^800h NULL^.set^0 DATALENGTH^.set^100h CODES^.set^0 DUAL^.set^30000h ONCHIP^.set^809C0Oh DEINT_ROW^.set^16 DEINT BLOCK^.set^256^;symbols per block BLOCKS^.set^2 K^.set^809c0Oh POLY1^.set^809c01h POLY2^.set^809c02h CRC_CCITT^.word^69665 CRC 32^.word^4374732215^;problem with length FLAG-^.s et ^809c05h MENU MASK^.set^3h PACKET_ MASK^.set^7h LENGTH MASK^.set^3ffh CRC _MASK^.word^01FFFEOH HIGE_MASK^.word^Offff0000h CPC_ONE_ADDER1^.set^Oh CPC_^_^ ONE ADDER2 .set^lh CPC_TWO_ADDER1^.set^2h CPC_TWO_ADDER2^.set^3h ADCHANA^.set^804000H ADCHANB^.set^804001H TROUBLEA^.WORD^31000H Q_START^.set^809c16H^;contains add of Q table Q_END^.set^809c17H^;contains add of Q end tabl e SERIALO^.set^809C18H TABLE_ENC^.set^809C49H^;CONTAINS POINTER TO TAB_ENC IBIT_POINTER^.set^809C4AH^;contains IBIT pointer QBIT_POINTER^.set^809C4BH^;contains Qbit pointer SINE POINTER^.set^809D0OH COSINE_POINTER^.set^809D01H POINT _COUNT^.set^809D02H DATA^.set^ 'WORD 809003H CURRENT ADDRESS .set^809004H END_ADDEESS^.set^809D05H Q_OFFSET^.set^809006H  Oct 7 1993 01:57:01^VARSRCVR.ASM 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117  TRANSMISSION^.set Q_OFF_TRANS^.set GET NEWFRAME_FLAG .set DIBET_COUN T^.set  809d07H 809D08H 809D09H 809D0AH  ;RCVR VARIABLES ADCHANA1 ADCHANB1 ;SCALE SCALE  .word^804000h .word^804001h .float^3.052e-5 .float^9.155553e-5  REAL_IBIT_POINTER .word 1000h REAL_QBIT POINTER .word 2000h FLAG_ADDRESS _TABLE .word 3000h TABLE_TOP .word 3000h TABLE BOTTOM .word 3Offh FLAG_EOMP .word B1492H MASK .word FFFFFFOOH MASK1 .WORD Offffffh OLDI .float OLDQ .float OLDI_INT .float OLDQ_INT .float FLAG TO BE .word START_FEA ME .word 2000h s STOP_FRAME .word 2fffh s CURRENT FLAG .word 3000h CIRC_BOTTOM . word 1000h CIRC TOP .word 2000H TROUBLE .word 0100h TROUBLE2 .word 00F0h TROUBLE3 .word 0110h TROUBLE4 .word 0120h TROUBLE6 .word 0130h HD LENGTH .word DIEI T .word THRESHOLD .word 2 CIRCLESS1 .word lfffh RCVD SIGNAL_ENERGY .word 000fh SYMBOLS .word 0010h but .word 1000h buf2 .word 2000h CURRENT START .WORD ;VITERBT DECODER TABLES & VARIABLES BETA ONE_MINUS_BETA BIT_MASK BIT COUNT DEEP d PATH FORCE END ZEROS PUNC EOLUe4-N ADDEE_ONE_PUNC ADDER_TWO PUNC ADDER_1PRTME_PUNC  .set^9.9e-1 .set^1.0e-2 .word^80000000h .word^-27 .wor ^2 .word^16 .word^0 .word^1 .word^7 .word^7 .word^7  Page 2  ;init to dummy value ;init to dummy value ;init to table_top  Oct 7 1993 01:57:01 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177  ADDER_2PRIME_PUNC SEQUENCES  VARSRCVR.ASM .word .word  7  .label  TABLE_STATE  .float .float  -7.07e-1 -7.07e-1  .word  .word  .float .float .word .word  .float .float .word  .float .float .word .word  .float .float .word  .float .float .word  .word  .float .float .word  .float .float .word .word  .float .float .word  .float .float .word  .word  °float .float .word  .float .float .word  .word  .float .float .word  .float .float .word  Page, 3  0 0 0  7.07e-I 7.07e-1  ;state 0 ;I(s) ;4(s) ;s  ;I(s+1) ;4(s+1)  1  ;s+1  1  7.07e-1 -7.07e-1 2 -7.07e-I 7.07e-1 3  ;state I ;I(s) ;4(s) ;s ;I(s+1) ;Q(s+1) ;s+1  2 -7.07e-1 7.07e-1 4 7.07e-1 -7.07e-1  ;state 2 ;I(s) ;(2(s) ;s ;I(s+1) ;4(s+1)  3 7.07e-1 7.07e-I 6 -7.07e-1 -7.07e-1 7  ;state 3 ;I(s)  4 -7.07e-1 7.07e-1 8 7.07e-1 -7.07e-I 9  ;state 4 ;I(s) ;4(s) ;s ;I(s+1)  5 7.07e-1 7.07e-1  ;state 5 ;I(s) ;4(s)  -7.07e-1  ;I(5+1)  5  10  -7.07e-1 11  6 -7.07e-1 -7.07e-1 12 7.07e-I 7.07e-1 13  ;s+1  ;Q(s)  ;s ;I(s+1) ;Q(s+1) ;s+1  ;0(s+1) ;s+1  ;s  ;Q(s+1) ;s+1  ;state 6 ;I(s) ;4(s) ;s ;I(s+1) ;4(s+1) ;s+1  Oct 7 1993 101:57:01 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237  VARSRCVR.ASM .word  Page 4  7 7.07e-1 -7.07e-1 14 -7.07e-1 7.07e-1 15  ;state 7 ;I(s) ;4(s) ;s ;I(s+1) ;Q(s+1) ;s+1  .float .float  8 7.07e-1 7.07e-1  ;state 8 ;I(s) ;Q(s)  .float .float  -7.07e-1 -7.07e-1  ;I(s+1) ;Q(s+1)  .float .float .word  .float .float .word  .word .word  .word .word  .float .float .word  .float .float .word  .word  0  1  ;s  ;s+1  9 -7.07e-1 7.07e-1 2 7.07e-1 -7.07e-1 3  ;state 9 ;I(s) ;4(s) ;s ;I(s+1) ;Q(s+1) ;s+1  10  ;state 10 ;I(s) ;4(s) ;s ;I(s+1) ;Q(s+1)  .float .float  7.07e-1 -7.07e-1 4 -7.07e-1 7.07e-1  .word  11  -7.07e-1 -7.07e-1 6 7.07e-I 7.07e-1 7  ;state 11 ;I(s) ;4(s) ;s ;I(s+1) ;Q(s+1) ;s+1  12 7.07e-I -7.07e-1 8 -7.07e-1 7.07e-1 9  ;state 12 ;I(s) ;4(s) ;s ;I(s+1) ;Q(s+1) ;s+1  .float .float  13 -7.07e-1 -7.07e-1  ;state 13  .float .float  7.07e-1 7.07e-1  ;I(s+1) ;Q(s+1)  .word  14 7.07e-1 7.07e-1 12  .float .float .word  .word  .float .float .word  .float .float .word .word  .float .float .word  .float .float .word  .word .word  .word  .float .float .word  5  10  11  ;s+1  ;I(s) ;4(s) ;s  ;s+1  ;state 14 ;I(s) ;4(s) ;s  Oct 7 1993101:57:01 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297  VARSRCVR.ASM  Page 5  .float .float .word  -7.07e-1 -7.07e-1 13  ;I(s+1) ;Q(s+1) ;s+1  .word .float .float .word .float .float .word  15 -7.07e-1 7.07e-1 14 7.07e-1 -7.07e-1 15  ;state 15 ;I(s) ;4(s) ;s ;I(s+1) ;Q(s+1) ;s+1  .label .word .float .word .word  TABLE_SURV 0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV1  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV2  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV3  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV4  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV5  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV6  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV7  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURVO  Oct 7 1993 01:57:01 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357  VARSRCVR.ASM  Page 6  SURV8  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV9  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV10  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV11  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV12  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV13  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV14  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  SURV15  .word .float .word .word  0 0 0 0  ;past history ;accumulated metric ;last state ;next state  .label .word .float .word  TABLE_NEXT_16 0 0 0  ;past history ;accumulated metric ;last state  .word .float .word  0 0 0  ;past history ;accumulated metric ;last state  NEXTSURVO  NEXTSURV1  Oct 7 1993 01:57:01 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417  VARSRCVR.ASM  Page 7  NEXTSURV2  .word .float .word  0 0 0  ;past history ;accumulated metric ;last state  NEXTSURV3  .word .float .word  0 0 0  ;past history ;accumulated metric ;last state  NEXTSURV4  .word .float .word  0 0 0  ;past history ;accumulated metric ;last state  NEXTSURV5  .word .float .word  0 0 0  ;past history ;accumulated metric ;last state  NEXTSURV6  .word .float .word  0 0 0  ;past history ;accumulated metric ;last state  NEXTSURV7  .word .float .word  0 0 0  ;past history ;accumulated metric ;last state  NEXTSURV8  .word .float .word  0 0 0  ;past history ;accumulated metric ;last state  NEXTSURV9  .word .float .word  0 0 0  ;past history ;accumulated metric ;last state  NEXTSURV10  .word .float .word  0 0 0  ;past history ;accumulated metric ;last state  Oct 7 1993 01:57:01 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468  NEXTSURV11  .word .float .word  0 0 0  ;past history ;accumulated metric ;last state  469 470 471 472  VARSRCVR.ASM^Page 8  NEXTSURV12  .word .float .word  0^;past history 0^;accumulated metric 0^;last state  NEXTSURV13  .word .float .word  0^;past history 0^;accumulated metric 0^;last state  NEXTSURV14  .word .float .word  0^;past history 0^;accumulated metric 0^;last state  NEXTSURV15  .word .float .word  0^;past history 0^;accumulated metric 0^;last state  STATE TABLE SURV_TATE TABLE NEXT_16_SUiV  .WORD .WORD .WORD  TABLE_STATE TABLE_SURV TABLE_NEXT_16  ;^Memory Map of On chip memory $30000 - $3ffff ;^v1.00  Feb 93  LENHEADO .set LENDATAO .set LENHEADENC .set LENDATAENC .set PACKET_NUM .set RATE .set g MENU OPTION .set ERROi_NU M .set CONTROL WORD .set LENHEADT,1 .set s LENHEADP2 .set s LENDATA_WORD .set LENDATA BIT .set ta chunk TOTAL_WORDS .set e CODE .set ;unused 30009-3000f  30000h 30001h 30002h 30003h 30004h 30005h  ;length of unencoded header ;length of unencoded data ;length of encoded header ;length of encoded data ;packet number Ns ;rate to be used for encodin  30006h 30007h 30008h 3000ah  ;menu option 1,^2,^or 3 ;error number ;control info from protocol ;bit length of P1 header bit  3000bh  ;bit length of P2 header bit  3000ch 3000dh  ;word length of data chunk ;# of left over bits from da  3000eh  ;word length of current fram  3000fh  ; Careful^!!^these are pointers to specific memory locations  Oct 7 1993 01:57:01 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507  .text VIRGIN_HEADER^.word TAIL1^.set VIRGIN_DATA^.word TAIL2^.set HEADBUF1^.word HEADBUF2^.word HEADBUF3^.word HEADBUF4^.word  VARSRCVR.ASM^Page 9 30010h 30012h 30013h 30030h 30031h 30033h 30035h 30039h  ;start of virgin header ;used for header CRC calc ;start of virgin data ;space to store data CRC ;header buffer 1 ;header buffer 2 ;header buffer 3 ;header buffer 4  DATABUFP1^•word DATABUFP2^.word ;7bh--->7fh Unused ACK()^.set STROBE_RCVR^.set STROBE_HOST^.set  3003dh 3005ch  ;data buffer 1 ;data buffer 2  3007Bh 3007ch 3007dh  ;ACKO  FRAMEBUFP1^.word FRAMEBUFP2^.word  30080h 300a0h  ;frame buffer 1 ;frame buffer 2  FLAGOP1^.word PACKETOHARDP1^.word PACKET1HARDP1^.word BUFP1^.word BUFP2^.word CPC1I^.word CPC1Q^.word CPC2I^.word CPC2Q^•word FREE1^•WORD FREE2^.WORD  300c0h 300c1h 300e2h 30100H 30500H 30900H 30b0OH 30d0OH 33800H 33100H 33400H  ;flag for frame 0,^P1  

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