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Implementation and evaluation of various stop and wait type II hybrid ARQ schemes for mobile radio Agostino, Remo L. 1993

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IMPLEMENTATION AND EVALUATION OF VARIOUS STOP ANDWAIT TYPE II HYBRID ARQ SCHEMES FOR MOBILE RADIObyREMO L. AGOSTINOB. A. Sc., University of British Columbia, 1990.A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFMASTER OF APPLIED SCIENCEinTHE FACULTY OF GRADUATE STUDIESDepartment of Electrical EngineeringWe accept this thesis as conformingto the required standardTHE UNIVERSITY OF BRITISH COLUMBIASeptember 1993© Remo L. Agostino, 1993In presenting this thesis in partial fulfilment of the requirements for an advanceddegree at the University of British Columbia, I agree that the Library shall make itfreely available for reference and study. I further agree that permission for extensivecopying of this thesis for scholarly purposes may be granted by the head of mydepartment or by his or her representatives. It is understood that copying orpublication of this thesis for financial gain shall not be allowed without my writtenpermission.(Signature)Department of ...-/et^Cze The University of British ColumbiaVancouver, CanadaDateDE-6 (2/88)ABSTRACTThis thesis investigates the design and implementation issues involved in the de-velopment of various Stop-and-Wait (SW) Type II Hybrid Automatic Repeat reQuest(ARQ) strategies. The modulation scheme utilized is the North American digital cellularstandard known as 7r/4—shift DQPSK. The general Complementary Punctured Convolu-tional (CPC) SW Type II ARQ scheme is presented and numerically analyzed in both anAWGN channel and a combined AWGN and Rayleigh fading channel. The three varia-tions of the general scheme implemented are: Rate 3/4 CPC SW Type II ARQ, Rate 3/4CPC SW Type II ARQ with Code Combining, and an Adaptive CPC SW Type II ARQscheme. The prototypes are implemented with two Spectrum TMS320C30 Digital SignalProcessing (DSP) cards and a host IBM PC. The experimental data for the prototypeswere verified and were in good agreement with the numerical results. This validated theprototypes' correct and proper operation along with the DSP software modules used bythe prototypes. It is shown that the upgrade of the CPC SW Type IT ARQ scheme toa Code Combining and an Adaptive scheme requires small software modifications. It isthe versatility and flexibility of the DSP cards which allow these upgrades to be easilyaccomplished and extremely cost effective. The Code Combining upgrade increased thethroughput performance of the general rate 3/4 scheme at low SNR levels. The Adaptivescheme resulted in an increase at both low and high SNR levels with a slight degradationat medium SNR levels with respect to the throughput curve of the general rate 3/4 scheme.ContentsABSTRACT ^  iiList of Tables  viList of Figures ^  viiAcknowledgments  ixChapter 1 Introduction ^ 11.1 ARQ Schemes 11.1.1 Stop-and-Wait ARQ ^ 11.1.2 Type I Hybrid ARQ 31.1.3 Type II Hybrid ARQ ^ 41.2 Thesis Goals 41.3 Thesis Organization ^ 6Chapter 2 7/4—Shift DQPSK Modulation Scheme ^ 82.1 Introduction ^ 82.2 Transmitter Model 82.3 DSP Implementation of the Phase Shift Encoder andBaseband Generator ^ 112.4 RF Modulator/Demodulator and Channel ^ 142.5 DSP Implemented Baseband Differential Detector ^ 162.6 Theoretical Analysis and Prototype Performance ^ 182.7 Conclusions ^ 21111Chapter 3^Application of Complementary Punctured ConvolutionalCodes to a SW Type II ARQ Scheme ^ 22^3.1^Introduction ^ 223.2^Review of Complementary Punctured ConvolutionalCodes (CPC) ^ 223.2.1^CPC Codes 233.3^Generalized CPC SW Type II Hybrid ARQ Algorithm . . ^ 243.4 DSP Implementation of a CPC SW Type II ARQ Scheme . 253.4.1 Frame Structure ^ 283.4.2 Frame Synchronization 293.4.3 Encoder/Transmitter DSP Card ^ 333.4.4 Receiver/Decoder DSP Card 363.4.4.1 Viterbi Decoder ^ 393. Numerical Analysis 413. Computer Simulation ^ 423. Viterbi Decoder Performance ^ 423.5 Prototype Performance 433.5.1 Throughput Analysis^ 443.5.1.1 Numerical Results 453.5.2 Experimental Throughput^ 463.5.3 Rayleigh Fading Channel 48iv^3.6^CPC SW Type ll ARQ Scheme with Code Combining . . 503.7^Conclusions ^ 53Chapter 4^An Adaptive SW Type ll ARQ Scheme ^ 544.1^Introduction ^ 544.2^The Adaptive Coding Rate Algorithm ^ 544.3^DSP Implementation of the Adaptive Scheme^ 564.4^Performance Evaluation ^ 574.5^SW ARQ Scheme Comparisons ^ 634.6^Conclusions ^ 65Chapter 5^Conclusions and Future Research ^ 665.1^Conclusions ^ 665.2^Future Research 695.2.1^Symbol Synchronization ^ 695.2.2^Selective Repeat Upgrade 695.2.3^Adaptive Header ^ 695.2.4^FEC Schemes 70Bibliography 71Appendix A^Software Listings ^ 74List of TablesTable 1^Phase Shift as a function of Information Symbol. ^ 11Table 2^7r14 Shift DQPSK State Encoder Look Up Table. ^ 13Table 3^Distance Spectrum of Code with Rate 1/2 ^ 42Table 4^Distance Spectra of Rate 3/4 Punctured ConvolutionalCode of Memory m=4. ^ 45viList of FiguresFigure 1.1^Stop-and-Wait ARQ Scheme ^  2Figure 1.2^Typical Type I Hybrid ARQ System  3Figure 2.1^Block Diagram of the 7r/4 shift DQPSK Transmitter. . . . ^ 9Figure 2.2^^State-space diagram of the 7r/4 shift DQPSK modulatedcarrier at sampling points   10Figure 2.3^Flow chart representing baseband transmissionalgorithm ^  12Figure 2.4^Modulator, Demodulator, and Channel simulator. ^ 15Figure 2.5^DSP Baseband Differential Detector Block Diagram^. ^ 16Figure 2.6^BER Performance in AWGN. ^ 19Figure 2.7^BER Performance of 7r/4—shift DQPSK in a RayleighFading Channel for Various BDT. ^  21Figure 3.1^Block Diagram of Prototype SW Type ll ARQ Scheme. . ^ 26Figure 3.2^Detailed Structure of Frame. ^ 28Figure 3.3^Correlation Sidelobes of Flag used in Prototype^ 30Figure 3.4^(a) and (b) Effects of Changing Threshold value used forFlag Correlation ^  32Figure 3.5^Frame Encoding and Construction Algorithm of DSPTransmitter Card. ^  35Figure 3.6^Frame Decoding Algorithm of DSP Receiver Card.^. ^ 38Figure 3.7^Choosing a Path Survivor^ 40Figure 3.8^Rate 1/2 Soft Decision Viterbi Decoder Performance. . . ^ 43viiFigure 3.9^Numerical and Experimental Throughputs ^ 46Figure 3.10^Throughput of Prototype in a Rayleigh Fading Channel. ^ 49Figure 3.11^Throughput of CPC SW Type ll ARQ Scheme with andwithout Code Combining ^  51Figure 3.12^Histograms for Rate 3/4 CPC SW Type II ARQ with andwithout Code Combining ^  52Figure 4.1^Threshold Regions Defining Coding Rates. ^ 55Figure 4.2^Experimental Throughputs of rate 1/2, 3/4, and 1^ 57Figure 4.3^Adaptive CPC SW Type ll ARQ Throughput. ^ 58Figure 4.4^Affect of varying N for the Adaptive Scheme'sThroughput^  59Figure 4.5^Adaptive CPC SW Type ll ARQ in Rayleigh Channel.. . ^ 60Figure 4.6^Adaptive CPC SW Type II ARQ in a Rayleigh Channel forVarious BDT Products^  62Figure 4.7^Effect of varying N for the Adaptive Scheme in a Fadingchannel. ^  63viiiAcknowledgmentsI would like to thank my mother and aunt, Maddalena and Maria Taddei, for theircontinuous moral support and constant encouragement throughout my academic career. Iwould also like to issue a special thanks to my uncle, Tony Bolognese, for having played amajor role in my decision to enter the exciting field of communications. I am enormouslygrateful to my supervisors, Dr. Samir Kallel and Dr. V. C. M. Leung, for their constantguidance, moral support, and invaluable experience which allowed me to complete thisthesis. I would also like to thank my fellow students and especially Dimitrios P. Bourasand William Cheung for their insightful and stimulating discussions. Finally, I wouldlike to acknowledge the assistance provided by the B.C. Science Council.ixChapter 1Chapter 1 IntroductionSection 1.1 ARO SchemesThe problem of providing an efficient reliable data communications link in a landmobile radio channel is of great practical importance. Automatic Repeat reQuest (ARQ)protocols or similar custom tailored Radio Data Link Protocols are commonly used toprovide a virtually error free data link for the radio channel. The ARQ protocol ensuresa consistent data quality under varying channel conditions. The functions the ARQprotocol must accomplish can be divided into two different classes: low level functionsinvolved with encoding and decoding of protocol information in the data packets andhigh level functions concerned with the request retransmission algorithm to support frametransmission services. The message itself is contained in the data packet of the frame,whereas the destination address and other pertinent information is contained in the headerwhich precedes the data packet. A code with good error detecting capability is used toencode the header and data packet separately. Typically, a Cyclic Redundancy Code(CRC) is used [1]. The header is independently encoded to allow all mobile radio usersto decode it in order to distinguish if the frame is addressed to them and decide whetherto process the data packet.1.1.1 Stop-and-Wait A RQIn a Stop-and-Wait ARQ (SW ARQ) scheme, the transmitter sends a single frame andstops to await the reply of the receiver. No other frame can be sent until the receiver'sreply arrives at the transmitter. Three possible events may arise once a transmissionhas taken place. The receiver may send an acknowledgment (ACK) to indicate that theSection 1Chapter 1frame was received error free; or a negative acknowledgment (NACK) if it was receivedin error; or no reply if the frame was so corrupted by noise as not to be received. Toaccount for this last event, the transmitter is equipped with a timer. Once a frame hasbeen sent, the transmitter awaits for a recognizable reply (ACK or NACK). If no suchreply is received during the time-out period, the frame is retransmitted. Therefore, anyreply other than an ACK will result in the transmitter retransmitting the same frameagain. Figure 1.1 illustrates the SW ARQ scheme.It is inefficient to utilize a SW ARQ protocol in a single frequency system becausethe time required for the transmitter to await the receiver's reply is wasted air time. Thetypical mobile radio system uses a number of frequencies to communicate between thebase stations and the mobile users. This configuration allows the SW ARQ protocol tomake efficient use of its air time. For example, after the base transmits a message tomobile A, it can send another message to any other mobile while awaiting the reply ofmobile A on the return channel. In this respect the SW ARQ protocol can be well suitedfor mobile radio systems.Idle time^ Retrans issionTransmitterReceiverFigure 1.1 Stop-and-Wait ARQ SchemeSection 1^ 2MessageCRCENCODER• CONVOLUTIONALENCODERNOISEACKNACK•^VITERBIDECODERCRCCHECKERChapter 11.1.2 Type I Hybrid ARQA hybrid ARQ system utilizes both Forward Error Correction (1-EC) coding and errordetection coding (incorporated in the ARQ scheme). The FEC code is used to reducethe number of retransmissions. In a Type I Hybrid ARQ scheme the message and itserror detecting parity bits (typically CRC), are further encoded with a FEC code. Atthe receiver, the FEC parity bits are used to correct channel errors. The FEC decoder(typically a Viterbi Decoder) outputs an estimate of the received message and its errordetecting parity bits. This estimate is tested by the error detection decoder (CRC checker)to determine if the message is error free. Figure 1.2 depicts a Type I Hybrid ARQcommunication system.Figure 1.2 Typical Type I Hybrid ARQ SystemThe efficiency of a Type I ARQ system in comparison to a plain ARQ systemdepends on the level of noise corrupting the channel. If the Signal-to-Noise Ratio (SNR)is high, the Type I ARQ scheme does not result in any improvement. The FEC paritybits are wasted, as a result of the signal strength being strong enough to deliver errorfree messages. On the other hand, the Type I system does show an increase in efficiencySection 1^ 3Chapter 1at low SNR levels, and since the signal strength is so poor, error free reception is veryunlikely and the FEC parity bits are utilized to correct channel errors.1.1.3 Type II Hybrid ARQIn a Type II ARQ scheme, the FEC parity bits are only sent if the received messagecontains errors. The transmitter would alternate between sending the message with itserror detection parity bits on one transmission, and the FEC parity bits on the next. Notethat the FEC parity bits are only sent if the received message contains errors. Withthis scheme, any error free reception of the message with its error detection parity bitsdelivers the message. If the FEC parity bits are invertible, any error free reception ofthe FEC parity bits also delivers the message. Finally, if both the message with its errordetection parity bits and the FEC parity bits are in error, combining these two framesfor error correction may successfully deliver the message. The Type II system offers thebenefit of performing as a plain ARQ scheme at high SNR and performing as a TypeI system at low SNR.Section 1.2 Thesis GoalsThe disadvantage of Type I and Type II hybrid ARQ schemes is the failure toprovide a useful throughput at high channel error rates. Application of code combiningto hybrid ARQ schemes to achieve a useful throughput has been investigated [2, 3].Code combining involves taking frames received in error and optimally combining themwith their repeated copies. Therefore, the receiver would process a combination of allreceived sequences for that frame, rather than only the two most recently received onesas in the conventional Type II system.Section 1^ 4Chapter 1An adaptive hybrid ARQ system utilizing code combining would be optimal. Adap-tive refers to the FEC coding scheme being able to adjust to the channel conditions anddata protection needs. Typically, a fixed code with a certain error rate and correctioncapability matched to the protection requirement of the data and the worst channel con-ditions is used. Unfortunately, different data (voice, FAX, computer data files, all usingthe same channel) have different error protection needs and what may be appropriate forone type may be inappropriate for another. Another problem, is the mobile radio channelconditions are constantly changing due to its multipath and time varying characteristics.Therefore, an adaptive code combining hybrid ARQ scheme would generally yield ahigher throughput than a non-adaptive scheme in a radio channel [4].Motivated by the above, this thesis investigates the design, implementation issues,and performance evaluation of various adaptive and non-adaptive FEC coding schemesof a Type II SW ARQ system. The research contributions can be summarized as follows:1. The Software design, implementation, and test of a Digital Signal Processing (DSP)Module Library for the Spectrum TMS32C30 DSP card housed in an IBM PCplatform. The library consists of the following modules:• CRC Encoder/Decoder• Rate 1/2 Convolutional Encoder• Puncturing Module• Rate 1/2 Soft Decision Viterbi Decoder• Block Interleaver• Soft Data Deinterleaver• Queueing ModuleSection 2^ 5Chapter 1. 71/4—shift DQPSK Baseband Transmitter/Receiver2. The Software implementation and evaluation of a Complementary Punctured Convo-lutional (CPC) coding scheme for the SW Type II ARQ system with and without codecombining utilizing the DSP library in an AWGN channel and a combined AWGNand Rayleigh Fading channel.3. Software upgrade and performance evaluation of an Adaptive CPC SW Type II ARQscheme utilizing the DSP library in an AWGN channel and a combined AWGN andRayleigh fading channel.Section 1.3 Thesis OrganizationThe thesis consists of five chapters and one appendix. It is organized as follows:• Chapter 2 discusses the 7r/4—shift DQPSK modulation system implemented and itstheoretical and practical performance.• Chapter 3 explains the generalized Complementary Punctured Convolutional (CPC)coding scheme for a SW Type II ARQ protocol with and without code combin-ing. It also discusses in detail the DSP prototype CPC SW Type II ARQ schemeimplemented. Finally, the prototype's performance is analyzed and evaluated.• Chapter 4 presents the Adaptive CPC SW Type II ARQ scheme implemented andits performance evaluation. This chapter will also compare the three ARQ schemesimplemented and discuss their performances.• The thesis' conclusions and suggestions for future work are cited in Chapter 5.• Appendix A contains the software listings for the DSP Module Library, the AdaptiveSW Type II ARQ Protocol, the Transmitter DSP card, and the Receiver DSP card.Section 2^ 6Chapter 1The CPC scheme's software is a subset of the Adaptive scheme and is therefore notlisted.Section 3^ 7Chapter 2Chapter 2 7114-Shift DQPSK Modulation SchemeSection 2.1 IntroductionThe 7r/4 shift Differential Quadrature Phase Shift Keying (DQPSK) modulationscheme has become the modulation standard for the North American and Japanesedigital cellular communications system [5]. This modulation scheme is used in theimplementation of the SW Type II ARQ scheme for mobile radio communications in orderto get practical results which are of interest to the cellular industry. The organizationof this chapter is as follows. Section 2 will review the 7r/4 shift DQPSK modulationtechnique. Sections 3 to 5 will describe the DSP software and the RF hardwarerequired to construct the system. A performance comparison between the theoreticaland implemented modulation scheme is presented in Section 6.Section 2.2 Transmitter ModelFigure 2.1 illustrates the transmitter model of the 7/4 shift DQPSK system. ThePhase Shift Encoder and Baseband Generator Block produce the unfiltered rectangularpulse waveforms which are denoted as u(t) and v(t) in the Inphase (I) and Quadrature (Q)channels respectively. The waveforms u(t) and v(t) are Nyquist filtered and passed to theRF modulator which mixes the I and Q components to form the RF modulated signal.8Chapter 2Equations 2.1 and 2.2 represent the RF modulated signal.\/271E, cos (wct 2;)si(t) =2E^7F .Sz (t) { cos wct cos —z — wct sin —7F i}^i= 0, 1, • • • , 7.^(2.2)4^4In Equation 2.2, E repesents the energy per symbol, T, is the symbol duration, and tv, isthe carrier frequency. Figure 2.2 is the state-space signal diagram which illustrates thepossible 8 modulated carrier signals at their sampling instants. The state-space diagramshows that the transmitted signals are chosen from two signal groups, the circles (evennumbered points {0, 2, 4, 6}) and the crosses (odd numbered points {1, 3, 5, 7}). If thecurrent signal is at one of the four phase states designated by a circle, it shifts to one ofthe four phase states designated by a cross at the next symbol transition and vice versa.The current signal is not allowed to shift to a fellow member of its phase state at the nextsymbol transition (i.e., circle to circle or cross to cross). As a result of this constraint,the differential phase shift between two consecutive symbols can only be k7r/4, whereSection 2^ 9(2.1)Chapter 2k = +1 or ±3. Consecutive phase shifts of ±7r/2 and 7r are inhibited. The connections inthe state-space diagram indicate the possible phase transitions.u( i)Figure 2.2 State-space diagram of the r/4 shift DQPSK modulated carrier at sampling points [5].The differential phase shift encoding operation can be mathematically represented byEquations 2.3, 2.4(a), 2.4(b), and Table 1 [6].s(t) = 2E { uk cos wt — vk sin wt}Ts (2.3)uk = uk_i cos Ok — vk_i sin Ok^ (2.4a)vk^uk_i sin Ok vk_i cos Ok• (2.4b)In Equations 2.4(a) and 2.4(b), uk and vk are the signal levels of the pulse amplitudes ofSection 2^ 10Chapter 2Information Symbol ek11 7r/401 37r/400 -37r/410 -7r/4Table 1 Phase Shift as a function of Information Symbol.u(t) and v(t) for a period equal to the symbol duration. The signal levels uk and vk aredetermined from the previous signal levels, uk_j and vic_i and the phase shift, k resultingfrom the current information symbol. The relationship between the phase shift and thecurrent information symbol is given in Table 1. From Equations 2.4(a) and 2.4(b), it canbe seen that the amplitudes of u(t) and v(t) can take the values of 0 +'`L ' or ±1. For2 example, assume the current signal is so(t) (i.e., Bo = 0, uo = 1, and vo = 0 duringt r.fs). At time t = Ts, the information symbol 11 is sent. Therefore, 9]=7/4 and from^,^,Equations 2.4(a) and 2.4(b), tti=^and denoti g signal si(t).From the state-space diagram and the mathematical model it follows that the infor-mation symbol is contained in the phase difference between two consecutive samplinginstants. The receiver only requires the phase difference between two consecutive sam-pling intervals in order to retrieve the transmitted information symbol. As a result, thereceiver does not need to phase synchronize with the transmitter.Section 2.3 DSP Implementation of the PhaseShift Encoder and Baseband GeneratorThe transmitter and receiver is implemented utilizing the Texas InstrumentsTMS320C30 DSP chip. The DSP platform consists of a Spectrum TMS320C30 cardand software development tools for an IBM PC. The TMS320C30 DSP cards were cho-Section 3^ 11Chapter 2sen due to their availability and excellent software support. A software based DSP designis more versatile, flexible, and modular than an all hardware design. The DSP systemallows the user to make changes and updates to their software algorithms in a fractionof the time required for a hardware update.The flowchart shown in Figure 2.3 describes the baseband transmission algorithm.The algorithm is interrupt driven by one of the two timers that the TMS320C30 chipfeatures. The timer is set to 6.6 its, which is the upper limit available on the Spectrum cardSection 3^ 12Chapter 2housing the TMS320C30. The timer value has a direct result on the rate of transmission.The smaller the timer value, the higher the transmission rate. The baseband transmissionroutine is interrupt driven to allow the DSP chip to encode and construct other framesfor transmission while the current frame is being transmitted. Therefore, even though aSW ARQ scheme is being used, the scheme may be upgraded to a Selective Repeat (SR)ARQ with little or no change to the transmission algorithm.The Baud rate, which is the number of symbols transmitted per second, is determinedby the number of times the routine is executed per symbol or dibit. The variablesymbol_duration_count keeps track of this value, which is compared to a user set limit.In the algorithm shown in Figure 2.3, the limit is set to a value of 8 and gives rise to abaud rate of 18.939kHz according to equation 2.5.Baud rate = {(symbol_duration_count Limit)* 6.6 us}l . (2.5)Every time the interrupt routine is executed, the symbol_duration_count is checked. Ifa new symbol or dibit is required, it is fetched from memory and the amplitudes uk andvk, of the baseband signals u(t) and v(t), are chosen from the 7r/4 shift DQPSK encoderlook up table displayed as Table 2. Table 2 shows all possible state transitions given theI^Previous Signal s1(t)Current Symbol 0 1 2 3 4 5 6 700 5 6 7 0 1 2 3 401 3 4 5 6 7 0 1 210 7 0 1 2 3 4 5 611 1 2 3 4 5 6 7 0Table 2 7r/4 Shift DQPSK State Encoder Look Up Table.previous signal s1(t) and the current symbol or dibit to be transmitted. This table is a directSection 3^ 13Chapter 2result of equations 2.4(a), 2.4(b), and Table 1. Once the values for uk and vk are chosen,they are written to the Digital to Analog registers, which in turn outputs an analog voltageon the I and Q channels. Note the transmitter outputs a +5 volt synchronization pulse onthe TMS320C30 digital channel at approximately the middle of the symbol duration.The baseband waveforms u(t) and v(t) are filtered before being sent to the RFmodulator. In the transmitter model discussed in Section 2.2, Nyquist filters were usedin order to eliminate Intersymbol Interference (ISI) and maximize the Signal-to-NoiseRatio (SNR). Butterworth filters, which are contained on the Spectrum DSP cards, wereused in the prototype implementation. As a consequence of not using Nyquist filters, thereceived noise power will be greater in the Butterworth filter case.Section 2.4 RF Modulator/Demodulator and ChannelA detailed block diagram of the hardware implemented RF modulator/demodulator isshown in Figure 2.4 and presented in [7]. The modulator and demodulator are designed tooperate at the relatively low carrier frequency of 1.5 MHz. The carrier frequency entersthe modulator to be divided into its I and Q components by a 900 splitter. The carrier'sI and Q components are then mixed with the I and Q baseband signals and summed bya signal combiner. The resulting RF modulated carrier is amplified and passed to thechannel module, which allows fading to be simulated by the use of the Digital FadingSimulator presented in [8]. White Gaussain noise is also added to the channel from aWhite Noise Generator whose band coverage is 6 kHz to 25 MHz. The modulated carrierand white noise is filtered by a Band Pass Filter (BPF), which has a 3 dB bandwidthof 200 kHz centered at the carrier frequency of 1.5 MHz. The bandwidth of the BPFSection 3^ 14Chapter 2is much greater than that of the Low Pass Filters (LPF) at the demodulator and is usedto minimize noise.The demodulator takes the received RF modulated carrier and splits it into its I andQ components, which are then coherently mixed down to the baseband signals. Thebaseband I and Q signals are passed through Low Pass Filters (LPF) and fed to the DSPcard for Differential Baseband Detection.Figure 2.4 Modulator , Demodulator, and Channel simulator.Section 4^ 15Symbol Sync SignalButterworthLPF -I-Sample & HoldADC^ iik I kSample &Butterworth ^ HoldLPF ADC Decision RulesDSP Receiver Cardü(t)r(t)qr)•Low PassFilterLow PassFiltercos(wt)sin(wt)RF DemodulatorChapter 2Note the symbol synchronization pulse is directly connected from the transmitter DSPcard to the receiver DSP card. In practice a local oscillator, closely tuned to the symbolrate of the I and Q channels, would trigger the receiver. This procedure was investigated,but it resulted in a synchronization problem. It was observed that approximately 150-200symbols were correctly received, immediately followed by 50-100 incorrect symbols andthen the cycle begins again. The local oscillator drifted in and out of synchronizationwith the I and Q channels' symbol rate. In order to obtain optimum synchronization,a Phase Locked Loop (PLL) circuit was employed. The PLL worked and the resultswere encouraging but required further research. Since the investigation of symbolsynchronization effects is beyond the scope of this thesis, we opted to use the transmitterDSP card to trigger the receiver.Section 2.5 DSP Implemented Baseband Differential DetectorThe block diagram of the Differential Detector is shown in Figure 2.5 [6]. OnceFigure 2.5 DSP Baseband Differential Detector Block Diagramthe RF modulated carrier is converted into its I and Q baseband signals et(t) and 1/(t), itis ready to be processed by the DSP Differential Detector. The DSP card drives eachbaseband signal through a Butterworth filter, a Sample and Hold circuit, and an AnalogSection 4^ 16Chapter 2to Digital Converter (ADC). It is the digital output of the ADC that the TMS320C30addresses in order to obtain a real floating point representation of the amplitudes Ilk and14 of the received baseband signals. The DSP detector samples each symbol and usesequations 2.6(a) and 2.6(b) in order to transform the DQPSK real data Ilk and 14, toQPSK real data wk and zk [6].^Wk = iik_iiik + 2,k_124 = cos (Ok — Ok — i)^(2.6a)^zk = iik—V3k — 14—iiik = sin (Ok — Ok—i) -^(2.6b)This transformation of 7r/4—shift DQPSK data to QPSK data makes each symbol nolonger dependent on the previous symbol for decoding purposes. Note that wk and zkare equivalent to sin (Ok — Ok—i) and cos (Ok — Ok_i), where Ok — Ok—i is the phase shift.It follows that, since the phase shift can only be k7r/4, where k = ±1 or ±3, wk and,\/zk will be approximately +—T. The real floating point values obtained for wk and zkmay be fed into a soft decision Viterbi decoder or can be hard decoded according to thefollowing decision rules:SI = 1 if wk > 0^SI = 0 if wk < 0(2.7)SQ = 1 if zk > 0^SQ = 0 if zk < 0where Si. and SQ are the least and most significant bit of the symbol respectively. Notethe prototype system utilizes the same carrier frequency for both the modulator anddemodulator. In practice a local oscillator tuned to the same frequency as the transmitteris used to demodulate the received carrier. This local oscillator will have a constant phasedifference but it has been shown that the phase error is cancelled through differentialdetection [6].Section 5^ 17Chapter 2Section 2.6 Theoretical Analysis and Prototype PerformanceThe probability of a binary digit error for four-phase DPSK with Gray coding in anAWGN channel is given by [9] as^{P4b(e) = e N°—2 Eb k=0(.\/ — 1)k Ik(_Eb^1 T^'N,EbNo^2A°^N^'^(2.8)where Ik is the kth order modified Bessel function of the first kind. The Bit Error Rate(BER) curve based on Equation 2.8 is plotted in Figure 2.6.Figure 2.6 also shows two experimentally measured curves of the prototype modula-tion scheme in an Additive White Gaussian Noise (AWGN) channel. The curve labelledas "Uncoded BER with Butterworth Filtering" is the actual performance of the prototypeimplemented. There is a considerable degradation of 6 dB as compared to the theoreticalideal curve. This degradation is primarily due to the substitution of the required Nyquistfilters with 4th order Butterworth filters. The required Nyquist filters were unavailableand the Butterworth filters are contained on the DSP cards. The effect of the Butterworthfilter is to allow more noise to pass through to the receiver and cause 1ST in comparisonto the Nyquist case. As a result, the prototype will have worse performance since theSNR after the receiver filter will be less than the Es/No which would exist when em-ploying a square root Nyquist filter. Through the use of a computer simulation, whichused the Butterworth and Nyquist filters' bandwidths as parameters, it was found that thedifference between the Butterworth and Nyquist case is approximately 5 dB. The curvelabelled as "Uncoded BER with Nyquist correction" is a result of this correction factor.Note that this is an approximation, the true Nyquist correction factor must also accountfor the added ISI caused by the Butterworth filter. The prototype's corrected performanceSection 6^ 18Chapter 2is relatively close to the theoretically expected performance with a maximum degradationof 1 dB. This deviation is attributed to the following factors.• The non-ideal signal space at the demodulator output, due to the imperfect RFcomponents.• The imperfect timing of the software controlled symbol synchronization signal.• The ISI caused by the Butterworth filters.For convenience, all subsequent performance curves of the implemented system willbe adjusted by this "Nyquist correction factor". This also holds for the coded case, sinceSection 6^ 19Chapter 2the performance is plotted against the SNR level. The SNR level that would exist withthe Nyquist case is just a simple adjustment as above.Figure 2.7 presents the measured BER performance of the modulation system in acombined AWGN and Rayleigh fading environment with BDT equal to 0.0043, 0.0022,and 0.00084. The BD T products correspond to a 7r/4 shift DQPSK system operatingwith a carrier frequency of 900MHz, a baud rate of 19.2kBaudis, and vehicle velocitiesof 100, 50, and 20km/hr respectively. Also shown in the graph, is the theoretical BERresults for a static multipath fading channel. Static refers to the channel having a constantphase modulation (i.e., the receiver or vehicle is at rest). The experimental results arefor vehicles in motion and therefore, are expected to be worse than the theoretical curvefor a vehicle at rest. It is evident that the theoretical and experimental results are inclose agreement until a residual error floor is established by the experimental curves.This error floor is a result of the random phase modulation caused by the doppler spreadobtained from the vehicle being in motion. An increase in the doppler spread resultsin an increase in the level of the error floor. The experimental results are less thanan order of magnitude higher than the computer simulated results of Feher [10] andBouras [7]. This deviation is due to the imperfections in the modulation scheme and thehardware Rayleigh simulator, as well as the Receiver DSP Card clipping the input voltagewaveforms of the I and Q channels to ±3 volts even though the amplitude periodicallyfluctuates beyond these limits.Section 6^ 20Chapter 2Section 2.7 ConclusionsThe operation of the prototype 7r/4 shift DQPSK system was verified through ex-perimental measurements. The BER performance data obtained for the AWGN channeland the combined AWGN and Rayleigh Fading Channel were in very good agreementwith the expected theoretical results illustrating the proper operation of the prototypemodulation scheme.Section 7^ 21Chapter 3Chapter 3 Application of ComplementaryPunctured Convolutional Codes toa SW Type II ARQ SchemeSection 3.1 IntroductionRecently, Kallel has introduced a new class of punctured convolutional codes whichare complementary [11]. In this Chapter we will briefly review Complementary PuncturedConvolutional (CPC) Codes and their structure. Section 3 will present the generalizedCPC SW Type II Hybrid ARQ algorithm, and Section 4 will discuss its specific imple-mentation using DSP cards housed in an IBM PC. The performance of the implementedprototype will be compared to numerical and computer simulated models in Section 5.Section 3.2 Review of Complementary PuncturedConvolutional Codes (CPC)In general, a high rate (b/N) punctured convolutional code can be constructed froma rate 1/N0 mother code by periodically and selectively deleting (bNo—N) code bitsaccording to a specific perforation pattern [12]. The function of deleting code bits isusually performed by the use of a perforation matrix which consists of b columns andNo rows for a rate of b/N punctured code. Each column is associated with one encodingcycle, and each row is associated with each coded bit stream from the No modulo-2adders of the 1/N0 encoder. The perforation matrix consists of ones and zeros whichcorresponds to transmitting and not transmitting code bits. An example, of a rate 3/4punctured convolutional code of period 3 obtained from a rate 1/2 code is given by_ [^oo^t 1 .- 1 1^_I (3.1)22Chapter 3An equivalent punctured code can be obtained by likewise cyclically shifting theNo rows. At the most, this will yield b distinct codes which have the same distanceproperties and error performance capabilities [13]. As a result, P2, which is given by[ 0 1 1P2 = 1^0^1]'(3.2)and Pi are equivalent perforation matrices.3.2.1 CPC CodesAllow Pi, i=1,2, p, to denote the perforation matrices of p equivalent CPC codes ofrate b/N obtained from a rate 1/N0 mother code, where p=r14=1• The result of perforationmatrix Pi is code CPCi. Define the matrix PTOTAL asPTOTAL^Pz •^ (3.3)i=1The p equivalent codes CPC,, i=1,2, p, are said to be Complementary if every elementof PTOTAL is greater than or equal to one. Note that for convenience the p equivalentcodes were denoted as CPC, but if they do not met the above restriction associated withPTOTAL, they should not be referred to as CPCi. The rate of PTOTAL is given by b/(pN)which results in two possible cases. If N = N0, we have p = b and the rate of PTOTAL willbe b/(bN) = 1/N0, which is the original mother code. On the other hand, if N>N0 and p<bmatrices are chosen to satisfy Equation 3.3, then some elements of PTOTAL will be greaterthan one and the combined rate is b/(pN). As an example, the two previous matrices Piand P2 of rate 3/4 are combined to form PTOTAL and yield a resulting code rate of 3/8.PTOTAL = [2 (3.4)Section 2^ 23Chapter 3Section 3.3 Generalized CPC SW Type ll Hybrid ARQ AlgorithmAllow Pi, i=1, 2, ..., p, to denote the perforation matrices of p CPC codes of rateb/N obtained from a rate 1/N0 mother code, as discussed above. The result of perforationmatrix Pi is code CPC.The scheme begins by appending ndp detection parity bits and m tail bits, corre-sponding to the encoder's memory, to each k-bit data packet. The resulting sequence isencoded by the rate 1/N0 mother code and then punctured and transmitted according tothe following algorithm [11].1. Level 1: Puncture the sequence with 131, resulting in packet A of code CPC/ whichis transmitted. The receiver decodes packet A using a rate 1/N0 Viterbi decoder andperforation matrix 13/. The error detection decoder checks the decoded sequenceconsisting of data bits and parity bits. If the sequence is declared error free,transmission of A is complete. Otherwise, the received sequence is stored for futuredecoding attempts and the algorithm moves up to the next level.2. Level i, I< i <p: Transmit packet A of code CPC, resulting from Pi. Initially, useViterbi decoding with perforation matrix Pi. If the decoded sequence is declarederror free, transmission of A is complete. Otherwise, reapply Viterbi decoding buton the combination of all i sequences, previously stored up to this level, and usingperforation matrix PTOTAL=P 1+P 2+ . • .4-P i • If the resulting sequence is declared errorfree, transmission of A is complete. Otherwise, the current sequence is stored andthe algorithm moves to the next level.3. Level p: Send packet A of code CPC,. As above, initially decode using only thereceived sequence. If unsuccessful, decode using all p sequences. If the resultingSection 3^ 24Chapter 3sequence is still in error, discard the received sequence of code CPC] and thealgorithm moves to the next level.4. Level (p+j), j=1,2,... : Send Packet A of code CPC,. Decode using the receivedsequence in conjunction with perforation matrix Pi. If unsuccessful, decode usingall p sequences. In the event that decoding is still unsuccessful, discard receivedsequence at level j+1 and the algorithm moves to the next level.It should be pointed out, that the above encoding and transmitting strategy did not discussthe implications of appending a flag and a header to packet A. In the event that a flagis not found in the implemented prototype, the receiver will time out, and the algorithmwill reinitialize at the current level. In practice it is the transmitter which times out ifit receives no response from the receiver. If a header failure is detected, the currentpacket is discarded and the algorithm also reinitializes at the current level. Since thetransmitter and receiver DSP cards are contained in the same PC they are initialized andsynchronized by the Host ARQ protocol.Section 3.4 DSP Implementation of a CPCSW Type ll ARQ SchemeThe Stop and Wait Type II Hybrid ARQ Protocol is written in Borland C++ andresident on the host PC. The protocol behaves as discussed above with p=2 CPC codesof rate 3/4 from a rate 1/2 mother code. The two perforation matrices used by the DSPtransmitter card for encoding the data packet are given by[i 0 11^n^1 11-r2 —1 1 0 1 0 1 (3.5)Figure 3.1 shows the physical block diagram of the prototype communication system. Theprotocol constructs the header and random data packet, places them in the Dual AccessSection 4^ 25Chapter 3Memory (DAM), and strobes the DSP transmitter card to send and the DSP receiver cardto listen. The DSP transmitter card retrieves the header and data packets and encodesthem according to the information placed in the header. Once the frame is constructed,it is transmitted through the channel to the DSP receiver card, which is contained inthe same PC. The DSP receiver card processes the received frame and either places anacknowledgment (ACK) or negative acknowledgment (NACK) in the DAM and strobesthe protocol. Once the protocol fetches the DSP receiver's reply, two events may occur.If an ACK was sent, the protocol will construct a new header and a new random datapacket to place in the DAM. If a NACK was sent, the protocol will keep the data packetbut construct a new header which indicates the new Pi to be used for encoding the datapacket. Note that if a frame is lost, the DSP receiver is equipped with a time-out featurewhich will result in a NACK.Figure 3.1 Block Diagram of Prototype SW Type II ARQ Scheme.It is during the construction of the header, that the protocol decides which perforationmatrix P1 or P2 to use for encoding the data packet based on the receiver's reply. Alongwith the NACK, the receiver sends the motive which may be either a Header CRC Failureor a Data CRC Failure. In the event of a header failure or lost frame (time-out), theprotocol will not switch perforation matrices. In the event of a data failure, the protocolSection 4^ 26Chapter 3alternates between P1 or P2. The result of this algorithm is to maximize throughput.This algorithm ensures that if a corrupted data sequence of code CPC1 is received, thenext data sequence received can only be encoded by P2 and be of code CPC2. If thedata sequence of code CPC2 is unsuccessfully decoded, it may be combined with thedata sequence of code CPC1 for subsequent decoding. The modulation scheme used bythe SW Type II ARQ Protocol for transmission, is the 7r/4 Shift DQPSK discussed indetail in Chapter 2.The following assumptions or simplifications are incorporated in the implementedprototype which consists of the DSP transmitter and receiver cards in the same Host PCunder the control of the SW ARQ protocol.• As a consequence of the transmitter and receiver DSP cards being in the same HostPC, they are initialized and synchronized by the ARQ Protocol running on the HostPC. In practice, there is an initialization and synchronization process to be executedby the independent transmitter and receiver.• In practice a noisy return channel is used to send the receiver's reply. In the prototype,the receiver's reply is passed internally through the PC via the DAM. This is a noisefree return channel.• As a result of the ARQ protocol controlling both the transmitter and receiver, it is thereceiver which times out if a flag is not found. Again, in practice it is the transmitterthat times out if it does not get a response from the receiver.• Symbol Synchronization is accomplished by hard wiring the transmitter and receiver.The actual symbol timing signal is software generated and is not ideal. A practicalsystem would have the receiver utilize a Phase Locked Loop or some other synchro-Section 4^ 27635 DATA BITS^32 BITS 5 BITSAAChapter 3nization circuit to obtain symbol synchronization with no link to the transmitter.These simplifications do not compromise the accuracy of the experimental results. Theprototype is used to evaluate various FEC strategies which are unaffected by the abovesimplifications.3.4.1 Frame StructureThe detailed structure of the frame used for transmission in the prototype systemis illustrated in Figure 3.2. Excluding the preamble and flag, the maximum lengththe encoded frame may attain is 1024 bits. The frame begins with an 8 bit SymbolSync Preamble. Since a Stop and Wait scheme is implemented, the channel willalways be idle before a transmission and the preamble allows the receiver to realizesymbol synchronization and stabilize before the remaining portion of the frame arrives.Immediately following the preamble is the Flag or Frame Sync, whose purpose is topresent the receiver with a unique bit pattern so that the receiver may synchronize itselfwith the data stream's frame structure. The receiver is continuously hunting for the flagpattern and the actual procedure and choice of flag is investigated in the next section.8 BITS^r4 BITS 128 ENCODED BITSI 4896 ENCODED BITS4^ • PREAMBLE FLAG HEADER CRC 16 TAIL DATA BITS^FCS32 TAIL2941B3ADDRESS•^16 BITSLENGTH Pi RESERVED^FCS16 TAIL4 P46 BITS^10 BITS• •2 BITS• • •^• •9 BITS^16 BITS 5 BITSFigure 3.2 Detailed Structure of Frame.Section 4^ 28Chapter 3Control information is contained in the 64 bit header, which includes a 16 bit FrameCheck Sequence (FCS) and a 5 bit tail for decoding. The header's address field is usedto identify the station that is to receive the frame. The next two fields, Ns and l■Ir aresequence numbers used to number the frames. The sequence numbers are not required forthe operation of the prototype but has been included for future upgrading to a SelectiveRepeat scheme. The next field contains the length of the data packet following theheader. The following field consists of two bits which indicate the perforation matrixPi used in the puncturing operation during the encoding of the data. Reserved is thenext field which consists of 9 bits and is not used by the current version of the protocol.The remaining 16 bits represent the FCS which is a result of the generator polynomialCRC—CITT defined as G16 (x) = x16 + x12 + x5 + 1.The information or data bits are contained in the data packet of the frame. Thisconsists of a maximum of 896 CPC encoded bits. As a result of using a perforationmatrix which yields a rate of 3/4, the maximum number of information bits whichthe data packet can contain is (896) — 32 — 5 = 635 bits. The length of the entireframe consisting of preamble, flag, header, and data packet is 1056 bits. The generatorpolynomial used for the FCS is the CRC32 given as G32 (X) = x32 + x26 + x23 + x22 +x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + xl + Frame SynchronizationThe 24 bit flag, denoted in hexadecimal as 2941B3, is used by the receiver tosynchronize itself with the data stream's frame structure. A good flag sequence hasthe property that the absolute value of its correlation sidelobes is small. A correlationsidelobe is the value obtained by correlating a flag sequence with a time-shifted versionSection 4^ 29Chapter 3of itself. Therefore, a correlation sidelobe value, Ck, for a k-symbol shift of a N bit flagsequence ffjj, is given byN—kCk =^FjFj+k ,^ (3.6)3=where Fi (1 i 1\1) is an individual bit taking values of ±1, and the adjacent bits (associatedwith index values i>N) are assumed to be 0 [14]. The actual flag was found throughthe use of computer simulations.Figure 3.3 shows the correlation sidelobes of the flag used in the prototype. Thesidelobes are very low when compared to the main lobe of Co, which yields a value of24. This sidelobe profile ensures a very high probability that the receiver will find theexact starting point of the flag rather than a bit shifted version of it.Correlation Sidelobes of Flag 2941B3 hex0-13025201510o 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23CkFigure 3.3 Correlation Sidelobes of Flag used in Prototype.The following procedure is followed to allow the receiver to locate the flag. Thereceiver correlates the known flag pattern to the incoming data. If the incoming data doesnot contain a flag, the correlation value will be low. On the other hand, when a flag isSection 4^ 30Chapter 3encountered the correlation value will be very high. The correlation value, C, for a 24bit flag pattern {TV and a 24 bit data sequence {Di] is given by2 4C =^F.)^, (3.7)=iwhere Fi and Di take on values of +1 or —1 representing bits 1 and 0 respectively. Themaximum value of C is 24 which indicates a flag with 0 bit errors has been located. Theprototype compares C to a user set threshold value which limits the number of bit errorswhich will be accepted in the flag and still ensure frame synchronization (i.e., a thresholdvalue of 16 indicates that 20 bits of the data sequence match the flag pattern).The optimum threshold value was found through experimentation. For each SNRtested, a 1000 uncoded frames were sent to the receiver whose correlation thresholdvalue was altered over the range of 10 to 24. Referring to Figure 3.3, it is seen thatthe highest sidelobe has a value of 5. A starting point for the threshold value is to taketwice the highest sidelobe value which is 10. Figure 3.4(a) illustrates that the probabilityof a bit error is relatively equal for threshold values of 24 to 10. However, loweringthe threshold value below 10 results in the prototype operating very slowly because itmust process a large number of false flags. The lower the threshold value, the larger theamount of false flags that the prototype must process. Figure 3.4(b) shows the percentageof flags successfully found given the different threshold values. It is seen that the lowerthe threshold value, the greater the success of finding the flags. Another observation isthat decreasing the threshold value below 12 has a marginal affect on the flag successrate. A balance must be found in which a threshold value that gives a good flag successrate does not burden the prototype with false flags. The two curves representing thresholdvalues of 10 and 12 give the best success rates and are relatively equal. It is obvious fromSection 4^ 31142^4^6^8^10^1212 14102^4^6^8^10Eb/1\10 1oll3Uncoded Frame using threshold = 10 ^•^Uncoded Frame using threshold = 12 3^^Uncoded Frame using threshold = 14 ----In---Uncoded Frame using threshold = 16^aUncoded Frame using threshold = 20 Uncoded Frame using threshold = 24 ^Lb/NeUncoded Frame using threshold = 10 ^•^Uncoded Frame using threshold = 12 Uncoded Frame using threshold = 14 ---11^Uncoded Frame using threshold = 16Uncoded Frame using threshold = 20Uncoded Frame using threshold — 24Figure 3.4 (a) and (b) Effects of Changing Threshold value used for Hag CorrelationSection 4^ 3210010-210-310-41010-610-710-8•^0.90.8r,^0.7X,^0.6§0.5±1^0.20.1Chapter 3By comparing the correlation value, C, to a threshold value, a certain number offalse flags will be located. The prototype receiver implemented is "smart" enough toeliminate the majority of false flags. When a flag is located, the header is immediatelydecoded and two events may occur.1. If the header fails the CRC check, the next subsequent flag is located and the newheader is decoded. If the CRC check fails again, the process repeats itself until theheader CRC is passed.2. If the header passes the CRC check, the length of the frame is obtained and all thefalse flag occurrences falling within the range of the frame are ignored.By using this simple procedure a very large majority of the false flags are ignored.3.4.3 Encoder/Transmitter DSP CardThe Encoder/Transmitter DSP Card contains the following C software modules:• CRC Encoder is responsible for calculating the Frame Check Sequence (FCS) bitsand is able to use generator polynomials up to 32 bits.• Rate 1/2 Convolutional Encoder outputs two data streams representing the twomodulo-2 adders of the encoder. A simple module named Combine is requiredto interleave the two outputs of the adders. The two generator polynomials areGi (x) = x4 + X3 + 1 and G2 (X) = X4 + X2 + X1 + 1 and are user configurable.• Puncture Module individually punctures the two data stream outputs of the rate 1/2convolutional encoder. The module punctures according to the perforation matrix Piwhich is chosen by the host SW ARQ protocol. Combine is required in order tointerleave the two punctured outputs of the encoder adders.Section 4^ 33Chapter 3• Block Interleaver accepts the coded symbols in 128, 256, or 512 bit blocks. Theinterleaver may be visualized as a rectangular array of I rows and n columns. Theencoded symbols are read into the array by rows and read out by columns. Thevertical dimension of the array, I, is called the interleaving degree and is userconfigurable by selecting values of 4, 8, and 16. The prototypes tested used aninterleaving degree of 16.• Queueing Module manages an 8 slot queue and is responsible for beginning andterminating the operations of the 7r/4 shift DQPSK baseband generator.It is the main program written in DSP Assembly language which utilizes the abovesoftware modules and provides the encoding and transmitting services required by thehost protocol. Figure 3.5 is a detailed description of the self explanatory procedurefollowed by the main program to encode and construct a frame. The two final operationsnot shown would be to interleave the frame and place it in the queue for transmission.The header and data are fetched from the Dual Access Memory.Section 4^ 34Chapter 3Section 4^ 35Chapter 33.4.4 Receiver/Decoder DSP CardThe Receiver/Decoder DSP card contains the following DSP Assembly softwaremodules:• Flag Correlator is used to locate the occurrence of a flag in a data stream accordingto a user set threshold value. Section 3.4.2 gives a detailed explanation of thissoftware module.• Transform is responsible for transforming the soft 7r/4 shift DQPSK data to softQPSK data and as a result eliminate the dependency between neighboring symbols.Section 2.5 discusses this transformation and its results.• Soft Data Deinterleaver is required to deinterleave the soft QPSK data. This moduleoperates on soft data as compared to its inverse module Block Interleaver whichoperates on hard data.• CRC Encoder is the same module used by the transmitter DSP card. The differenceis that the calculated Frame Check Sequence (FCS) is compared to the received FCSin the decoding mode.• Data Sequence Combiner is responsible for combining soft data sequences ofdifferent codes, such as CPC1 or CPC2, to form a more powerful code for errorcorrection purposes.• Rate 1/2 Soft Decision Viterbi Decoder is utilized to decode the header and dataaccording to the perforation matrix used in the encoding process.• In the CPC SW Type II ARQ scheme with code combining, an additional modulecalled Code Combining, which optimally combines data sequences of equal codessuch as CPC], is required.Section 4^ 36Chapter 3Figure 3.6 is a detailed flow chart of the Receiver/Decoder DSP algorithm. The algorithmis a direct result of the general scheme presented in Section 3.3 with p=2 CPC codes ofCPC1 and CPC2. As shown in Figure 3.6, the replacement of a module is necessary inorder to incorporate code combining. Rather than simply save the most current corrupteddata sequence of code CPC1 or CPC2, the module combines the current sequence withall previous corrupted sequences of the same code for further subsequent decoding.Section 4^ 37START•FIND FLAGOCCURENCE HAVEBOTHCPC I &CPC2?GET CODEDDATA NOSEND NACKCHOSE PUNCTUREMATRIXPI or P2 YESTRANSFORMDQPSK TO QPSKSOFT DATACOMBINE CPC I& CPC2DEINTERLEAVEREAL DATARATE 1/2SOFT DECISIONVITERBICRC DECODERYESFCSOK? SEND ACKSAVE COPY OFCURRENTCODED DATACPC I or CPC2YESSEND NACKNOSEND NACKTHIS MODULE IS SUBSTITUTED FOR THEONE ABOVE IT IF CODE COMBINING IS REQUESTED.COMBINE CURRENTCOPY OF CODEDDATA CPC1 or CPC2WITH EXISTINGCOPIESGET CODEDHEADERRATE 1/2SOFT DECISIONVITERBICRC DECODERChapter 3Viterbi Decoder A 16 state rate 1/2 soft decision maximum likelihood Viterbi Decoderis the heart of the receiver. It is entirely written in DSP Assembly Language for speed andefficiency. The soft decision decoding scheme makes use of past information bit historyand a metric function to decode the incoming data. It follows, that the performance of theViterbi decoder is primarily influenced by the choice of path history length and the metricfunction. It is common practice to select a path history length equivalent to four or fivetimes the constraint length of the encoder which results in negligible degradation from theoptimum decoder performance [14]. In the case of the prototype, the constraint length is5 and the path history length utilized is 32 information bits. The Viterbi decoder operateson soft QPSK data which is the product of the transformation of soft 7r/4 shift DQPSKdata. The metric chosen is the Euclidean distance based on the signal constellation ofthe QPSK signals. The Euclidean distance is defined asD = \ I(X c — X11)2 + (Yc — YR)2 ,^ (3.8)where Xc and Yc are the coordinates of the signal on the constellation for QPSK andXR and YR are the coordinates of the received data. Calculating the metric as defined inequation 3.8 is a very tedious and time consuming operation. The square root operationis not performed, and although it is not a linear function, distance values without thesquare root operation work well because the relationship between x and VT( is one-to-oneand monotonic. To further simplify 3.8, one may expand the brackets and discard thesquared terms to yieldD = XcXR d-YcYR•^ (3.9)There is a considerable amount of time saved in calculating 3.9 as opposed to 3.8.Section 4^ 39Chapter 3Once the Viterbi decoder is initialized, it will keep track of 16 surviving paths throughthe trellis. As depicted in Figure 3.7, at each new decoding instant, each survivor leadsto two new states or paths, thereby yielding a total of 32 new paths. The decodercalculates the branch metrics ,3 and y, related to the two new states, and then adds themto the accumulated metric a resulting in new accumulated metrics of cH-13 and a+-y. Thesmallest new accumulated metric will be chosen as the new surviving path.aPREVIOUS^ CURRENTSTATE STATES^4,41•10 so^a + 13BRANCHMETRICSSi^+ yPREVIOUS^ NEWACCUMULATED ACCUMULATEDMETRIC METRICSFigure 3.7 Choosing a Path Survivor.In practice, it is not possible to continue to accumulate the metric distances withoutencountering an overflow problem. Therefore, a weighted accumulation method is usedto determine the accumulated metric and is given asDnew = 13Dold + (1 — MDbranch,^ (3.10)where 0<</3<1 denotes the weighting factor, Dbranch is the branch metric, and D„,„ andDoid are the new and old accumulated distances respectively. This ensures that the newaccumulated metric is bound. The value of /3 is a performance parameter which is chosento be 0.98 in the implemented Viterbi decoder.Section 4^ 40Chapter 3Numerical Analysis Given the free distance df„, and the distance spectra ad and cd,where ad is the number of incorrect paths of Hamming weight d that diverge from thecorrect path and remerge with it sometime later, and cd denotes the total number of biterrors in all the paths having Hamming weight d, the probability of a bit error for Viterbidecoding is upper bounded [15] bycoP(B) <^CdPd •^ (3.11)d=df,„Pd is the probability that a wrong path at distance d is selected and depends only on thechannel and modulation scheme used [9].For an AWGN channel and R-14 shift DQPSK, Pd may be obtained as follows. Theprobability of a binary digit error for four-phase signalling over L statistically independentAWGN channels is given by [16] as E (\/-1)ki-k(\/—yrbL)^12./0(  V-2_,\ErobL)k=0 1LP4b(C)^C (3.12)L-171.1CnM +^(.\/^(,\TEabL)where CT, = 22L-1^( 2L — 11 )k^} •k=0Pd is the probability that a wrong path at distance d is selected and may be obtainedfrom Equation 3.12 by substituting d for L. Using 3.11 and 3.12 with the substitution, anupper bound for the performance of the rate 1/2 Viterbi decoder was calculated. FigureSection 4^ 41Chapter 33.8 depicts the resulting upper bound using a rate 1/2 code with weight spectrum givenby Table 3.RateGeneratordfiee(adfree+j 1 j=0, 1, ...4){Cdftee+j, j=0,^1, ...41Polynomials(2, 3, 4, 16, 37)1/2 23, 35 7{4, 12, 20, 72, 2251Table 3 Distance Spectrum of Code with Rate 1/2.Computer Simulation A C computer simulation was used to verify the prototypeViterbi decoder's performance. The computer model simulates the prototype which usesa 7/4 shift DQPSK modulation system with the receiver transforming the soft DQPSKdata to soft QPSK data for decoding purposes. Figure 3.8 shows the BER curve resultingfrom the computer simulation. As a result of transmitting 106 bits for each SNR leveltested, the BER curve is accurate for points above 10-5. The simulation BER curve isbelow the upper bound curve for all accurate SNR levels tested.Viterbi Decoder Performance Figure 3.8 illustrates the probability of a bit error for theViterbi decoder implemented. For each SNR level tested, the Viterbi decoder processed107 bits. As is evident, the prototype curve is slightly worse than the simulation curvebut close to the upper bound curve. This is expected since the simulation cannot take intoaccount implementation losses. The small deviation between the simulated and prototypecurves is due to the imperfect modulation system and synchronization timing. The rateSection 4^ 42Chapter 3Pi/4 QPSK Modulation Scheme•\mi1 0°1 0-21 0-310-41 0-510-610-710-8100^2^4^6^8^10^12^14Eb/No [dB]^Computer Simulation for Rate 1/2 Viterbi Decoding^•^Prototype BER for Rate 1/2 Viterbi Decoding •^Numencal Analysis for Rate 1/2 Viterbi BER ^•Uncoded theoretical BER Curve ^Figure 3.8 Rate 1/2 Soft Decision Viterbi Decoder Performance.1/2 soft decision Viterbi decoder implemented operates as expected and its performanceis verified by the computer simulation and upper bound curves.Section 3.5 Prototype PerformanceIn this section the throughput performance of the prototype CPC SW Type II ARQsystem in AWGN is compared to the ideal numerical results. The prototype's throughputperformance in a Rayleigh fading channel is also presented and discussed.Section 5^ 43Chapter 33.5.1 Throughput AnalysisThe throughput 7/ is defined as the average number of accepted information bitsper transmitted channel symbol and has a maximum possible value of 2 for DQPSKmodulation. In general, 71 may be defined as RIN, where R is the code rate and Nis the average number of packets transmitted per correctly decoded packet. If the errordetection parity bits along with the overhead of the header and flag are taken into account,the resulting throughput isR71 =^LED "JOH^ (3.13)where LEDk + ndp +(k ndp m)and Lau =^*(k ndp^h +fThe factor LED is the loss in throughput due to the addition of parity bits ndp and the tailof m known bits. The factor Loll is the loss in throughput as a result of the overheadincurred by the frame for appending a rate 1/2 header, h, and a flag, f, to each blockof k information bits. The average number of packets transmitted per correctly decodedpacket, N, for a CPC SW Type II ARQ scheme is given in [11] asp-11 + EPr{Dd(z)})1_ Pr{Dd(P)}(3.14)where Dd(j) is the event {decoded sequence obtained by combining j equivalent codes,is detected in error}. As in [11], Pr{Dd(j)}, assuming the undetected error probabilityis negligeable, is bounded asPr{Dd(j)} <1— (1— P(E))1 ,^ (3.15)Section 5^ 44Chapter 3where P(E) is the error event probability of Viterbi decoding with a code obtained bycombining j equivalent CPC codes (i.e., CPC1+CPC2+...+CPC1) and where 1 is the numberof trellis level (1,-(k+ndp)1b).P(E) is bounded as [15],00P(E) <^ (3.16)d=d3freewhere Pd is the probability that a wrong path at distance d is selected, and where c/frel andal are the free distance and weight spectra of the code obtained by combining j equivalentCPC codes. Pd is dependent on the channel and modulation scheme employed [9].Numerical Results Table 4 contains the distance spectra for the rate 3/4 puncturedconvolutional code used in the CPC SW Type II Scheme. Pd is given in Equation 3.12,Code Perforation Matrix dfree (ad+j, j=0,1..5)CPC1[1^0^1 i 3 (1, 2, 23, 124, 576, 2852)110  Jcpc2 [1^1^0-1 3 (1, 2, 23, 124, 576, 2852)011 ]CPC1 + CPC2[2^1^1 1 8 (1, 4, 3,^11, 18, 38)121 iTable 4 Distance Spectra of Rate 3/4 Punctured Convolutional Code of Memory m=4.where d is substituted for L. Using the values in Table 4 and Equations 3.13, 3.14, 3.15,Section 5^ 450.•^ UChapter 3and 3.16 a lower bound on the throughput for an AWGN channel with 7r/4 shift DQPSKmodulation can be calculated. The resulting lower bound is plotted in Figure Experimental ThroughputThe rate 3/4 CPC SW Type II ARQ scheme is tested over several SNR levelsby executing the scheme until 1000 frames are successfully delivered. The resultingthroughput is plotted in Figure 3.9 along with the previously calculated lower bound.Note that the throughput, which is the average number of information bits accepted persymbol, can be greater than one. This is a consequence of using 7r/4 shift DQPSK whichhas a maximum throughput of 2 information bits per accepted symbol. For medium toRate 3/4 CPC SW Type II ARQ Scheme in AWGN12^4^6^8^10Es/No [dB]Ideal Lower Bound ThroughputExperimental Prototype ThroughputAdjusted Throughput for Header & Frame LossFigure 3.9 Numerical and Experimental Throughputs.12^14•Section 5^ 46Chapter 3high SNR levels, the experimental curve and the lower bound are in good agreement. Thisis expected, since the Viterbi BER curve plotted against its upper bound is also in goodagreement. At low SNR levels, the prototype throughput has a maximum degradationof I dB. The calculated lower bound does not take into account header failures or lostframes. Whereas when the prototype encounters a lost frame or header failure, the entiredata packet is discarded and taken into consideration for the throughput calculation. Ifheader failures and lost frames are accounted for, the throughput of the system in questionwill suffer a decrease. To further prove this point, Figure 3.9 also plots a curve labelledas "Adjusted Throughput for Header & Frame Loss". This curve is obtained by ignoringlost and header damaged frames in the prototype system. Recall, that the receiver iscapable of transmitting a NACK which indicates whether the frame had a header failureor data failure. The transmitter keeps track of the type of NACKs, as well as the lostframes (time-outs). It is this information which is used to adjust the throughput for headerfailure and frame loss. It is clear that this adjusted curve is in good agreement with thelower bound with slight degradation at low SNR levels resulting from implementationlosses which are critical at lower SNR levels. The scheme is able to correct a certainnumber of errors. At medium to high SNR levels, the scheme easily corrects the channelerrors as well as the errors associated with the implementation losses. At low SNR levels,the number of channel errors in addition to the implementation loss errors places a loadon the scheme and results in a negligeable degradation of 0.5dB (maximum) from thelower bound curve. The implementation losses are factors such as:• imperfect symbol synchronization,• non-ideal modulator and demodulator, andSection 5^ 47Chapter 3• 1ST from the Butterworth filtering.It is clearly evident that since the prototype rate 3/4 CPC SW Type II ARQ schemeis in very good agreement with the lower bound, it is correctly operating and behavesas expected.3.5.3 Rayleigh Fading ChannelThe throughput of the prototype rate 3/4 scheme was also investigated in the combinedAWGN and Rayleigh fading channel environment. The measurements were obtained forthree BDT products of 0.0043, 0.0022, and 0.00084. These BDT products correspond toa 7r/4 shift DQPSK system operating with a carrier frequency of 900MHz, a baud rateof 19.2kHz, and vehicle velocities of 100, 50, and 20km/hr respectively. The throughputcurves are plotted in Figure 3.10.For comparison purposes, a lower bound on the throughput for a combined AWGNand a static multipath fading channel is also plotted. The lower bound is calculated in thesame fashion as before, by using Equations 3.13, 3.14, 3.15, and 3.16. The probabilityof a binary digit error for four-phase signalling over L statistically independent AWGNwith static multipath fading is given by [16] asL-1, ( 2k) (1 — /12  )k]i \^1^it k^4 — 2,u2P4blel — -- [ 1^V2 — it2 k=0'Yc where ft = 1 + and -T, is the average received SNR.Section 5^ 48(3.20)Chapter^. 0•••••5^10^15^20^25^30Es/No [dB]Experimental Throughput for BT=0.00084Experimental Throughput for BT=0.0022Experimental Throughput for BT=0.0043Static Fading Lower BoundFigure 3.10 Throughput of Prototype in a Rayleigh Fading Channel.As before, Pd is obtained from equating 3.20 by substituting d for L. The resultinglower bound is for a static multipath fading channel. The term static refers to the phasemodulation of the multipath channel being constant (i.e., the receiver or vehicle beingat rest). It is obvious that the three throughput curves obtained for the various vehiclespeeds should be worse than the lower bound since the vehicle is not at rest. Whenthe vehicle is in movement, the Doppler spread causes random phase modulations whichin turn is responsible for the existence of residual error floors in the bit error rate asdiscussed in Section 2.6. In effect, the lower bound may actually be viewed as an upperbound when it is being compared to the prototype throughput at various vehicle speeds.Rate 3/4 CPC SW Type II ARQ Scheme in Rayleigh Fading•••Section 5^ 49Chapter 3Section 3.6 CPC SW Type II ARO Scheme with Code CombiningThe upgrading of the CPC SW Type II ARQ scheme to accommodate code combiningis very simple. Only the receiver must be modified by the replacement of ten lines ofDSP Assembly Language code. The new code or module ensures that the most currentlyreceived corrupted data sequence of code CPC1 or CPC2 will be combined with allprevious corrupted copies of the same code (if the copies exist). The non—code combiningscheme simply discards the previous copy of the corrupted data sequence once a newdata sequence is received. It has been shown that code combining will increase thethroughput of the scheme at low SNR levels [3].Figure 3.11 illustrates the experimental results for the rate 3/4 CPC SW Type II ARQscheme with and without code combining. As expected, the code combining case resultedin an increase in throughput to a maximum of 1dB. If the code combining curve is adjustedfor header failure and lost frames, it is expected to perform better than the ideal Type IIlower bound curve. Recall, that the Type II lower bound curve does not take into accountlost or header damaged frames. Figure 3.11 also displays the "Adjusted Throughputfor Header & Frame Loss with Code Combining", which as expected has a substantialperformance gain in throughput in comparison to the ideal Type II lower bound. Tofurther verify the code combining scheme, measurements counting the number of framestransmitted to successfully deliver each of the 1000 frames at a certain SNR level wereaccumulated. Figures 3.12(a) and 3.12(b) are histograms representing the accumulateddata for the non—code combining and code combining cases at a SNR level of 3.32dB. Incomparing the two histograms, it is evident that the code combining case requires fewertransmitted frames to successfully deliver a frame since it is constantly combining dataSection 6^ 50Chapter 3sequences. This results in the number of transmitted frames being concentrated towardthe lower end of the histogram, as opposed to the non-code combining case where thenumber of transmitted frames are spread out. These experimental results verify the correctoperation of the code combining scheme.Kate 3/4 uru s w 1 ype 11 IkKl,2 Jcneme in HWU1NAS A • • • I/iii(5,, Ai.-1//11-.-•• •i//^2^4^6^8^10^12^1Es/No [dB]Ideal Lower Bound ThroughputExperimental Prototype ThroughputAdjusted Throughput for Header & Frame LossExperimental Prototype throughput with Code CombiningAdjusted Throughput for Header & Frame Loss with Code Combining• • TT 7.ell•••Figure 3.11 Throughput of CPC SW Type II ARQ Scheme with and without Code CombiningSection 6^ 51500 Type II ARQ scheme using CPC Codes without Combining400300(§)200100o 0^2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19A. Z. A .4! A Number of Successive Transmissions Required to Deliver a FrameSNR = 3.32dB with No Code CombiningChapter 3500400 Type II ARQ scheme using CPC Codes and Combining300200100o 0^2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19Number of Successive Transmissions Required to Deliver a FrameSNR = 3.32dB with Code CombiningFigure 3.12 Histograms for Rate 3/4 CPC SW Type II ARQ with and without Code CombiningSection 6^ 52Chapter 3Section 3.7 ConclusionsA prototype rate 3/4 CPC SW Type II ARQ scheme of memory m=4 was imple-mented utilizing a host IBM PC, two TMS320C30 DSP cards, an existing RF modula-tor/demodulator, and an existing channel simulator. The rate 1/2 soft decision ViterbiDecoder was thoroughly tested in section 1 and behaved as expected according to bothcomputer simulations and numerical results. The throughput of the prototype was exper-imentally measured for both an AWGN channel and a combined AWGN and RayleighFading channel. The experimental results for the AWGN channel were in very goodagreement with the numerical results. In the case of the combined AWGN and Rayleighchannel, the throughput curves were referenced to numerical results obtained for a staticmultipath fading channel. The experimental curves behaved as expected indicating properoperation of the prototype.When code combining was added to the prototype, the throughput at lower SNRlevels increased. There is no extra cost associated with upgrading the prototype toa code combining scheme. It only requires the replacement of ten lines of DSPAssembly Language code. The code combining prototype was also verified for properoperation by comparing the histograms at certain SNR levels which counted the numberof transmissions required to successfully deliver a frame.The comparison of the experimental data of the prototype's performance to thenumerical results clearly validate the proper and correct operation of the implementedscheme.Section 7^ 53Chapter 4Chapter 4 An Adaptive SW Type II ARQ SchemeSection 4.1 IntroductionThe previous chapter illustrated how the CPC SW Type II ARQ scheme utilizingcode combining achieved an increase in throughput at low SNR levels as compared tothe same scheme without code combing. This chapter will focus on increasing throughputat all SNR levels by employing an adaptive coding rate to the CPC SW Type II ARQscheme. The adaptive scheme uses Channel State Information (CSI) to decide whichcoding rate is the most appropriate to encode the data packet. Section 2 will present thealgorithm used to adapt the coding rate to the AWGN or combined AWGN and Rayleighchannel. Section 3 will discuss the necessary software modifications to the existing DSPAssembly code and host IBM Protocol software. Section 4 will present the performanceof the adaptive scheme for both the AWGN and combined AWGN and Rayleigh channel.Finally, all three implemented variations of the CPC SW Type II ARQ scheme will becompared and discussed.Section 4.2 The Adaptive Coding Rate AlgorithmA very simple and effective algorithm is used to select the current coding rate of theadaptive prototype. The algorithm calculates the throughput of the most recent N framestransmitted. The throughput is a measure of the channel state condition for the timeinterval required to transmit N frames. Based on this throughput, the algorithm decideswhich of the available coding rates to use from a user defined table. A user defined54Chapter 4threshold diagram which utilizes three coding rates is illustrated in Figure 4.1 It followsTHRESHOLDVALUE 2THRESHOLDVALUE 1Figure 4.1 Threshold Regions Defining Coding Rates.that the performance of the adaptive scheme is influenced by the selection of the value Nand the threshold values. The smaller the value of N, the quicker the scheme adapts tothe changing channel conditions. The threshold values are obtained from the throughputcurves of the individual rates. In essence, one would superimpose the throughput curvesand select threshold values to maximize the overall throughput of the scheme over allSNR values (i.e., select threshold values that will yield an overall maximum throughputequivalent to the maximum envelope of the individual throughputs).The generalized adaptive coding rate algorithm is best described by the followingprocedure.1. Level 0: Select the most powerful coding rate (Rate 1) and transmit using this ratefor N frames. The algorithm moves up to the next level.2. Level 1: Calculate the throughput of the last N frames transmitted. If the throughputis less than THRESHOLD VALUE 1, continue using Rate 1 to send the N framesand the algorithm remains at this level. Otherwise, if the throughput is greater thanTHRESHOLD VALUE 1, select Rate 2 to transmit the N frames and the algorithmmoves up to the next level.Section 2^ 55Chapter 43. Level i, i>1: Calculate the throughput for the most recent N frames transmitted.If the throughput is less than THRESHOLD VALUE i-1 select Rate i-/, transmit Nframes, and move down to the next level. If the throughput is between THRESHOLDVALUE i-1 and THRESHOLD VALUE i, continue using Rate i, transmit N frames,and remain at this level. If the throughput is greater than THRESHOLD VALUE i,select Rate i+1, transmit N frames, and move up to the next level.In the prototype, code rate synchronization is obtained by using two bits in the rate 1/2header to indicate the coding rate of the data packet following.Section 4.3 DSP Implementation of the Adaptive SchemeThe adaptive coding algorithm is contained in the SW ARQ protocol running on thehost PC. The transmitter and receiver DSP boards require minor software modificationsto be able to encode and decode any of the supported coding rates. The other necessarymodification is to use 2 of the 9 bits, labelled as RESERVED in the header, to indicatewhich rate is currently being used to encode the data packet.In the adaptive prototype scheme, N is chosen to be 5 and the coding rates usedare 1/2, 3/4, and 1. The adaptive SW ARQ protocol can also be forced to transmit atone of the three code rates. Figure 4.2 depicts the experimental throughputs obtainedfor the three individual coding rates. Referencing Figure 4.2, THRESHOLD VALUE 1 isselected to be 0.77 and THRESHOLD VALUE 2 is 1.2. From the above algorithm, therates of 1/2, 3/4, and 1 correspond to the code Rates of 1, 2, and 3 respectively. Noticeby selecting THRESHOLD VALUE 2 to be 1.2, there will be a region of the overallthroughput which will be less than the maximum envelope of any of the three individualthroughputs. Maximizing the throughput over all SNR levels is not always possible. TheSection 2^ 56Chapter 4CPC SW Type II ARQ Scheme in AWGN.^ • I*•,+/A— 1^41 a///jr///• • • •//,./•/i//1i2^4^6^8^10^12^14Es/No [dB]^Experimental Throughput of Rate 1/2 Scheme ^Exioerimental Throughput of Rate 3/4 Scheme— A-^Experimental Throughput of Rate 1 Scheme ^• ^Figure 4.2 Experimental Throughputs of rate 1/2, 3/4, and 1.specific SNR area is between 8dB and 10.5dB. If 1.2 is selected as a threshold valueand the current rate is 3/4, once the throughput reaches 1.2 it switches to rate 1. Thistakes place at approximately 8dB where the throughput of a rate 3/4 system is 1.2 butthe throughput of a rate 1 system is 0.85. As a result the adaptive scheme constantlyswitches between rate 1 and rate 3/4 within this region and maximum throughput is notobtained. The expected result is to obtain an average between the throughput curves ofrate 3/4 and rate 1 in this region.Section 4.4 Performance EvaluationRecall that the goal of the Adaptive CPC SW Type II ARQ protocol is to increaseen01. 4^ 57Ir-•Chapter 4or equal the throughput at all SNR levels as compared to the rate 3/4 CPC SW Type IIARQ protocol. The prototype is tested over several SNR levels by executing the schemeuntil 1000 frames are successfully delivered. Figure 4.3 displays the resulting AdaptiveCPC SW Type II ARQ throughput in an AWGN channel. As expected, the throughputhas increased at all SNR levels excluding the area between 7dB and 10dB. The slightdegradation in this area was predicted and is a factor of the selection of THRESHOLDVALUE 2. It is observed that the throughput curve has a stair case shape. This is dueto rate 1/2 being utilized at low SNR levels, rate 3/4 at medium SNR levels, and rate1 at high SNR levels. The results in Figure 4.3 clearly validates the operation of theadaptive scheme.CPC SW Type II ARQ Scheme in AWGN1. 0.9toz0 0.8E-1^ 2^4^6^8^10Es/No [dB]12^14^16Experimental Throughput of Adaptive Rate SchemeExperimental Throughput of Rate 3/4 Scheme^A-Figure 4.3 Adaptive CPC SW Type II ARQ Throughput.Section 4^ 58Chapter 4Figure 4.4 displays the adaptive scheme's throughput for various values of N. N isa performance parameter which adjusts how quickly the scheme reacts to changes inthe channel conditions. It is observed that changing the value of N between 5 and 15(i.e., approximately 5000 to 15000 bits) has marginal effect on the performance of thescheme in an AWGN channel. This can be accounted to the fact that an AWGN channel'sSNR level is constant for all practical purposes as compared to the instantaneous SNRlevel of the Rayleigh fading channel which fluctuates according to a rayleigh distribution.Changing the value of N for the combined AWGN and Rayleigh channel is expected toaffect throughput performance.CPC SW Type II ARQ Scheme in AWGN0^2^4^6^8^10Es/No [dB]Experimental Throughput of Rate Adaptive Scheme with N=5Experimental Throughput of Rate Adaptive Scheme with N=10Experimental Throughput of Rate Adaptive Scheme with N=15Figure 4.4 Affect of varying N for the Adaptive Scheme's Throughput.• 0.9(onO•^14 16• ^Section 4 59••Chapter 4Figure 4.5 illustrates the Adaptive CPC SW Type II ARQ scheme in a combinedAWGN and Rayleigh fading channel for a BDT product of 0.00084. The value for N is 5and the threshold values chosen are 0.76 and 1.19. The threshold values are slightly lowerthan those used in the AWGN channel as the fading channel is a very harsh environmentand it is more difficult to reach and maintain the threshold values. For comparisonpurposes, the experimental throughput for the rate 3/4 CPC SW Type II ARQ is alsoplotted. As in the AWGN channel, the throughput is increased at lower SNR levels,Adaptive CPC SW Type II ARQ Scheme in Rayleigh FadingtoF-•••••5^10^15^20^25^30Es/No [dB]Experimental Throughput for Adaptive N-5Rate 3/4 Experimental Throughput for BT=0.00084 •Figure 4.5 Adaptive CPC SW Type II ARQ in Rayleigh Channel.degraded at medium SNR levels, and increased at high SNR levels. Again the stair caseSection 4^ 60Chapter 4shape is evident. As in the AWGN channel, it is a result of the rate 1/2 code being usedat low SNR levels, rate 3/4 at medium SNR levels, and rate 1 at high SNR levels.Figure 4.6 depicts the remaining BDT product curves for the adaptive scheme. Itis observed that the slower the vehicle speed (i.e., the smaller the BDT product) thequicker the maximum throughput is reached at the higher SNR values. This is a veryimportant observation which implies that the set of code rates used must be optimizedto the set of BDT products representing the average vehicle speeds and transmission rateused. The three BDT products of 0.0043, 0.0022, and 0.00084 correspond to a 7r/4 shiftDQPSK system operating with a carrier frequency of 900MHz, a baud rate of 19.2kHz,and vehicle velocities of 100, 50, and 20 km/hr respectively. It is observed that the coderates of 1/2, 3/4 and 1 results in a relatively good throughput for the 20km/hr case ascompared to the non-adaptive scheme. The same cannot be said about the remainingtwo speeds of 100 and 50km/hr which will eventually reach the maximum throughputbut at a higher SNR level. This implies that a different set of code rates is required togive better performance. The random phase modulation caused by the increase in vehiclespeed cannot be overcome by the Rate 1 code (uncoded). It requires higher SNR valuesto successfully deliver the frame as opposed to the 20km/hr case. In other words, a morepowerful code than Rate 1 but weaker than 3/4 is required.Figure 4.7 shows the effect of varying the value of N which changes the amountof time it requires for the adaptive scheme to react to channel conditions. When largervalues of N are chosen, which indicates the adaptive scheme will take longer beforereacting to the channel conditions, the performance degrades. This is due to the timevarying characteristic of the Rayleigh channel. By selecting a smaller value of N, theSection 4^ 61^IR••1^•aChapter 4scheme can quickly adapt and maximize its throughput as opposed to a larger value ofN which makes the scheme more lethargic. In other words, the smaller the value of N,the more successfully the adaptive scheme can track the channel conditions.Adaptive CPC SW Type II ARQ Scheme in Rayleigh Fading10.90.8taA0.^10^15^20^25^30Es/No [dB]Experimental Throughput for Adaptive N=5Experimental Throughput for Adaptive N=5, BT= 0.0043Experimental Throughput for Adaptive N=5, BT= 0.0022Experimental Throughput for BT=0.00084Experimental Throughput for BT= 0.0022Experimental Throughput for BT= 0.0043Figure 4.6 Adaptive CPC SW Type II ARQ in a Rayleigh Channel for Various BDT Products.•••Section 4^ 620. 4Adaptive CPC SW Type II ARQ Scheme in Rayleigh Fading5^10^15^20Es/No 1cIB1Adaptive BT= 0.0043, N=15^Adaptive BT= 0.0043, N=5 0^Adaptive BT= 0.0022, N=15Adaptive BT= 0.0022, N=5^&-Adaptive BT=0.00084, N=15 ^Adaptive BT=0.00084, N=10 ^Adaptive BT=0.00084, N=5 Figure 4.7 Effect of varying N for the Adaptive Scheme in a Fading channel.Section 4.5 SW ARO Scheme ComparisonsThe three CPC SW Type II ARQ schemes implemented are listed below and rankedaccording to throughput performance.1. Adaptive CPC SW Type II ARQ Scheme2. Rate 3/4 CPC SW Type II ARQ Scheme with Code Combining3. Rate 3/4 CPC SW Type II ARQ Scheme25^30Section 5^ 63Chapter 4All three schemes are based on the CPC SW Type II ARQ protocol and utilize theidentical general DSP software library. The performance of the rate 3/4 scheme wasverified by the use of numerical results. The rate 3/4 code combining case resulted in anincrease at low SNR levels. In code combining, repeated copies of the identical codeddata sequences are optimally combined for subsequent decoding. This upgrade consistedof replacing 10 lines of DSP Assembly code. It does not require any additional memorybecause the receiver stores the combined data sequence and discards the most recentsingle copy (i.e. the most recent corrupted data sequence is combined with the previouscopies of identical coded data sequences from a certain memory slot and then stored inthat same memory slot). In order to obtain a greater increase in throughput over a largerregion of SNR levels, the adaptive scheme was implemented. In comparison to the rate3/4 scheme, the adaptive scheme's throughput increased for low and high SNR levelsand decreased for medium SNR levels. As discussed above, the slight degradation ( lessthan 1 dB) in the medium range is the result of the threshold value and the shapes ofthe individual rate throughput curves. The compromise of a slight degradation is wellworth the gain in performance at lower and higher SNR values. It was also observedthat the adaptive scheme's performance varied as a result of the system's BDT productwhich implies using a set of codes that are optimized for a set of BDT products. Theactual adaptive upgrade consisted of adding case statements in DSP Assembly code toaccount for the various code rates. The threshold values and selection of the coding ratewas added to the Host PC protocol program. The only other modification was to utilize2 of the 9 Reserved bits of the header to indicate the rate of the data packet.Section 5^ 64Chapter 4Section 4.6 ConclusionsAn Adaptive rate CPC SW Type II ARQ scheme was implemented using the existingprototype of Chapter 3 with software modifications. The goal was to utilize the existinggeneral software modules in order to minimize any cost associated with the upgrade.The Adaptive coding rate algorithm was presented and explained. The throughput ofthe adaptive prototype was experimentally measured for both an AWGN channel andcombined AWGN and Rayleigh fading channel. In both channels, the experimentalthroughput showed a general increase in performance. More specifically, the adaptivescheme's throughput increased for low and high SNR levels and decreased for mediumSNR levels in comparison to the rate 3/4 scheme. The compromise of a slight degradationis well worth the gain in performance at lower and higher SNR values. The effect ofvarying N, which controls the reaction time of the adaptive scheme, was also investigated.It was found that the value of N had marginal affect on the throughput in an AWGNchannel. In a combined AWGN and Rayleigh fading channel, as N is decreased thethroughput performance increases. The Rayleigh channel is time varying and the smallerthe value of N, the more successfully the adaptive coding rate can track the channelconditions.The experimental results indicate that the upgrade of the CPC SW Type II ARQprotocol to an adaptive scheme was successful.Section 6^ 65Chapter 5Chapter 5 Conclusions and Future ResearchSection 5.1 ConclusionsThis thesis investigated the design, implementation issues, and performance evalua-tion of various adaptive and non-adaptive FEC coding schemes of a Type II SW ARQsystem. The research contributions can be summarized as follows:1. The Software design, implementation, and test of a Digital Signal Processing (DSP)Module Library for the Spectrum TMS32C30 DSP card housed in an IBM PCplatform. The library consists of the following modules:• CRC Encoder/Decoder• Rate 1/2 Convolutional Encoder• Puncturing Module• Rate 1/2 Soft Decision Viterbi Decoder• Block Interleaver• Soft Data Deinterleaver• Queueing Module• 7r/4 shift DQPSK Baseband Transmitter/Receiver2. The Software implementation and evaluation of a Complementary Punctured Convo-lutional (CPC) coding scheme for the SW Type II ARQ system with and without codecombining utilizing the DSP library in an AWGN channel and a combined AWGNand Rayleigh Fading channel.66Chapter 53. Software upgrade and performance evaluation of an Adaptive CPC SW Type II ARQscheme utilizing the DSP library in an AWGN channel and a combined AWGN andRayleigh Fading channel.In this thesis a general algorithm for Complementary Punctured Convolutional Codingapplied to a Stop-and-Wait ARQ scheme was presented. A rate 3/4 CPC SW Type IIARQ protocol was implemented with the use of two Spectrum TM5320C30 DSP cardsand a host IBM PC. The following assumptions or simplifications are incorporated in theimplemented prototype which consists of the DSP transmitter and receiver cards in thesame Host PC under the control of the SW ARQ protocol.• As a consequence of the transmitter and receiver DSP cards being in the same HostPC, they are initialized and synchronized by the ARQ Protocol running on the HostPC. In practice, there is an initialization and synchronization process to be executedby the independent transmitter and receiver.• In practice a noisy return channel is used to send the receiver's reply. In the prototype,the receiver's reply is passed internally through the PC via the DAM. This is a noisefree return channel.• As a result of the ARQ protocol controlling both the transmitter and receiver, it is thereceiver which times out if a flag is not found. Again, in practice it is the transmitterthat times out if it does not get a response from the receiver.• Symbol Synchronization is accomplished by hard wiring the transmitter and receiver.The actual symbol timing signal is software generated and is not ideal. A practicalsystem would have the receiver utilize a Phase Locked Loop or some other synchro-nization circuit to obtain symbol synchronization with no link to the transmitter.Section 1^ 67Chapter 5These simplifications do not compromise the accuracy of the experimental results. Theprototype is used to evaluate various FEC strategies which are unaffected by the abovesimplifications.The rate 3/4 CPC SW Type II ARQ scheme was numerically analyzed for both anAWGN channel and a combined AWGN and Rayleigh fading channel. The experimentaldata obtained from the prototype was in good agreement with the numerical resultsvalidating the implementation and correct operation of the scheme.The rate 3/4 CPC SW Type II ARQ scheme was upgraded with Code Combining inan effort to gain an increase in the throughput performance. This allows the receiverto optimally combine copies of the same coded sequence for subsequent decoding.The experimental throughput performance increased at low SNR levels as comparedto the non-code combining case verifying its proper operation. The upgrade consistedof replacing 10 lines of DSP Assembly Language. The memory requirement remainsconstant since one data sequence, which consists of the combined copies, is kept ratherthan the individual copies.In an effort to further increase the throughput performance of the prototype, the CPCSW Type II ARQ protocol was upgraded with an Adaptive Coding Rate. The resultingexperimental throughput showed an increase at low and high SNR levels and a slightdegradation at medium SNR levels with respect to the throughput of the original rate 3/4prototype. The compromise of a slight degradation is well worth the gain in performanceat lower and higher SNR values. This degradation is due to the selection of thresholdvalues used in the adaptive coding rate algorithm.The three implemented schemes behaved as expected and their experimental through-Section 1^ 68Chapter 5puts verified their correct operation.Section 5.2 Future Research5.2.1 Symbol SynchronizationThe 7r/4 shift DQPSK modulation system used by the prototypes suffers fromimperfect symbol synchronization. As a result, the throughputs of the prototypes aredegraded at lower SNR levels. It would be interesting to further investigate the symbolsynchronization of the system.5.2.2 Selective Repeat UpgradeAlthough a Stop-and-Wait ARQ protocol was used for the prototypes, the softwaremodules and the design of the system were such that an upgrade to a Selective Repeat(SR) Protocol is possible. It would be interesting to have the prototypes upgraded toSR as this would only require software modifications but the majority of DSP librarymodules do not have to be modified.5.2.3 Adaptive HeaderThe implemented adaptive scheme varied the coding rate of the data packet while thecoding rate of the header remained constant (rate 1/2). If the coding rate of the header isalso made adaptive the throughput will increase. At high SNR levels, a powerful codeis not required and a larger data packet can be sent resulting in greater throughput. Atlower SNR levels, a more powerful coded header will deliver the data packet and reducethe number of retransmissions for header failures. The coding rate for the header shouldalways be more powerful than the coding rate of the data packet. In order to indicate therate of the header, a miniature header should proceed the header.Section 2^ 69Chapter 55.2.4 FEC SchemesWith the existing testbed used for the prototypes and the modular structure of theDSP library software, this leads to endless possible FEC schemes that may be investigatedand explored.Section 2^ 70Bibliography[1] S. Lin and J. D. J. Costello, Error Control Coding: Fundamentals and Applications.Prentice Hall, 1983.[2] J. Hagenauer, "Rate-compatible punctured convolutional codes (RCPC codes) andtheir applications," IEEE Trans. Commun., vol. 36, pp. 389-400, Apr. 1988.[3] S. Kallel, "Analysis of a type II hybrid ARQ scheme with code combining," IEEETrans. Commun., vol. 38, pp. 1133-1137, Aug. 1990.[4] K. J. Guth and T. T. Ha, "An adaptive stop-and-wait ARQ strategy for mobiledata communications," in the Proceedings of IEEE the 40th Vehicular TechnologyConference, pp. 656-661, Apr. 1990.[5] D. P. C. Wong and P. T. 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PrenticeHall, 1989.73Appendix A Software ListingsThe software listings appear in the following order:CSUB.0 — DSP Module Library.ADAPT.0 — Adaptive SW Type II ARQ Protocol for IBM Host PC.• XMITADAP.ASM — DSP Assembly code for Transmitter DSP card.• RCVRADAP.ASM — DSP Assembly code for Receiver DSP card.• VARSRCVR.ASM — Variables, definitions, and memory locations used by theassembly code for the transmitter and receiver DSP Cards.74Oct 6 1993 14:18:30^CSUB.0^Page 1 Oct 6 1993 14:18:30^CSUB.0^Page 21 #include <stdlib.h> 57 *^ current 32 bit word2 #include <stdio.h> 58 * index2^ -current bit position in 32 bit word3 #include <math.h> (0-31)4 main() 59 *^infobit -input bit to LFSR5676061* outputbitshift^-output bit from LFSR* -amount to shift LFSR to get outputbit8 /******************************************************************* 62 *^shreg -contents of LFSR****** 63 * feedback -feeback value for LFSR9 64 *^connections^-bits representing connections of LF10 * polydiv^v1.02^Feb 93 SR11 * 65 *^temp^ -temp storage of outputs of LFSR12 * This module implements a linear feedback shift register for 66 * remainder -remainder of polynomial division13 * polynomial division.^It is used for CRC calculation and 67 ********************************************************************14 * the decoding of convolved data chunks. *******/15 * This module requires 5 parameters: 6816 * K^- constraint length valid up to 33 decimal 6917 * MESGDATA^- pointer to message or data (dividend) 70 long unsigned polydiv(int K, long int *MESGDATA,^long unsigned int P18 * POLY - polynomial to be divisor OLY,19 * TOTAL - length of dividend in 32 bit words 71 int TOTAL,^long int *RESULT)20 * RESULT^- pointer where quotient is to be stored 72 121 * 7322 The resulting LFSR will be: 74 int index?,^index2,^infobit,^outputbit,^shift;2324** 75 long unsigned int shreg,^feedback, connections,^temp,^remainder;25 I^>x0^I^>xl^I^>x2-^>x(K^1)-^I^> 7626 * 7727 * where the connections are determined by POLY. 78 shift.0;28 * 79 temp.0;29 * NOTE:^POLY is read from right to left 80 shreg^0;30 * ie 1+x+x'4^---->^10011 . POLY 81 connections =0;31 * 82 /*The standard used is to read polynomials from right to lef32 RESULT t.33 * 83 This module needs them in left to right format so we rever34 * POLY^I^MESGDATA^REMAINDER se35 * 84 the bits of POLY^ie 0010 --> 0100.3637** 85 The following code reverse POLY and stores it in connections*/38 * The data is feed into the LFSR msb first and lab last 8639 * ie 87 for^(index?^K-1;^index? > 0;^index?--)40 * address^data 8841 * 300 25a4e845 39 if^(^((POLY)^&^(1 «^index?^-1))^:=^0)4243**301 84fe68dc 9091connections^I. 1^( K-1 - index?^);44 * "548e4a52cd86ef48"  ^LFSR 9245 * 93 )^/* end of reversal routine */46 * 9447 * Decoder Notes: 9548 * 1>^Give all 5 parameters and use quotient stored at 96 /*This section of code determines the amount to shift the49 * *RESULT.^Remainder can be discarded. 97 register by.^This is needed because if the constraint50 * 98 length is,^for example,^7 but we only use the first two51 CRC Notes: 99 registers^(ie POLY^0000011)^then we must shift the52make1>^If calculating the CRC it is your responsibility to 100 register by 5 positions to get the output of the 2nd register */53 * sure the data is premultiplied (padded with zeros) b 101y X°K 102 for^(index?^K;^indexl >. 0;^index?--)54 2>^The REMAINDER is the CRC value 10355 104 if^(^(POLY &^(1«^(index1-1)))^!=0)56 indexl -general variable used as loop count 105er & 106 shift.(K-indexl);Oct 6 1993 14:18:30^CSUB.0^Page 3 Oct 6 1993 14:18:30^CSUB.0^Page 4107108109110111index1=-1;}/* end of finding shift amount */if^(K==33)^ /*exceptional case with 32bi156157158159160/*END =return(remainder);t CRC/ 161 }112 shift=0;^ /*and we don't require a shi 162ft^*/ 163 #define K^((Int^*)0x809c00)113 164 #define POLY1^((Int^*)0x809c01)114 outputbit = 0; 165 #define POLY2^((Int^*)0x809c02)115 166 /*******************************************************************116 /*This next section implements the LFSR and feeds the entire *****117 encoded message through it.^The msb of the polynomial/mes 167 * CONV^V1.02^Feb 93sage 168118 is feed into the LFSR first. 169 This module implements a convolutional encoder of rate119 ie encoded message is "F78jNd"^dNj87F---->LFSR 170 1/2 with variable length K and generator polynomials*7 171 POLY1 and POLY2.120 172 This module requires 5 parameters:121 for^(indexl = TOTAL -1;^indexl >=0;^indexl--) 173 * *MESG^- pointer to data to be convolved122 174 * *MESGP1 - pointer to convolved data as a result of P123 for^(index2 = 31;^index2^>= 0;^index2--) OLY1124 175 * *MESGF2^- pointer to convolved data as a result of P125 /*lets get bit to input into LFSR */ OLY2126 infobit=0; 176 * SIZE - # of 32 bit words to convolve127 if^(^(*(MESGDATA + indexl^)^&^(1 « index2)) 177 *1=^0 ) 178128 infobit =1; 179 ^> P1 bits129 180 POLY 1130 /* if output=1 then feed it back */ 181131 if^(outputbit^== 1) 182 I^1^I^2 I^K^I132 feedback . Oxffffffff & connections; 183133 else 184 POLY 2134 feedback = 0; 185 ^> P2 bits135 186 *136 187 * The encoder is implemented by polynomial multiplication of t137 shreg = feedback^((infobit « K - 2)^I^shr heeg»1); 188 data and POLY1 and POLY2 polynomials respectively. This is138 outputbit=(^shreg>>^(shift)^)^& 1; 189 * achieved by shifting and exclusive ORing.139 190140 /* this shift register SHREG is implemented 191 Notes:with the */ 192 1> When using cony be sure to have a storage area with K ext141 /* lsb being the msb of the shift register ma193 bits so that none of the convovled data bits are lost.142 /*^cab^ lsb 194 ie195 16 bits of data143 /*^ie .^r4 r3 r2 rl r0 196 K =4 ^ > requires 20 hiIs144f poly/* x0 xl x2 x3 x4 c--- powers o*/197ceof storage spa145 198146 199147 if^(index2^==^0) 200 vmesg[]^- vector containing data to be convolved148 201 vmesgPl[] - vector containing convolved data from POLY149 remainder = shreg;150 202 vmesgP2[]^- vector containing convovled data from POLY151 *( RESULT + indexl )^. temp; 2152 temp = outputbit cc 31; 203 temp[] - intermediate storage vector153 204 indexl^- general loop index154 else 205 index2 - general loop index155 (temp)^I= outputbit cc^(index2^- 1); 206 index3 - general loop indexOct 6 1993 14:18:30^CSUB.0^Page 5 Oct 6 1993 14:18:30^CSUB.0^Page 6207 firstbit^- firstbit of current 32 bit word 258 firstbit = 11;208 * lastbit - 32nd bit of current 32 bit word 259 else209 * mask - used to select which term of POLYx is used 260 firstbit .^01;in 261 1210 * multiplication 262 }/*end of shifting^(polynomial multiplication)*/211 * byte^-intermediate storage variable 263212 264 /* add the terms of the polynomial multiplication to213 * RETURNS^- nothing ./214 ..................................................................../265 /* the appropriate vector according to their generator*/215 266 /* polnomials POLY1 and POLY2.216 void conv(^long unsigned int *MESG,^long unsigned int *MESGP1, */217 long unsigned int *MESGP2,^int SIZE) 267218 268 if^((*POLY1 & mask)^!. 0)219 ( 269 (220 270 for(index3.0;^index3<SIZE;^index3++)221 long unsigned int^temp[33],^vmesg1331,^vmesgP1[33],^vmesgP2 271 vmesgPl[index3]^^=temp[index3];[33]; 272 )222 int indexl,^index2,^index3,^firstbit,^lastbit,^mask; 273223 long byte; 274 if^((*POLY2^& mask)^!.^0)224 275 {225 /* get message into vector for processing */ 276 for(index3.0;^index3<SIZE;^index3++)226 for^(indexl . 0;^indexl < SIZE;^indexl++) 277 vmesgP2[index3]^^=temp[index3];227 { 278 }228 vmesg[indexl)^. *(MESG + indexl); 279229 temp[index1].0; 280 mask . mask « 1;230 vmesgPl[index1].0; 281 (7* end of adding up terms */231 vmesgP2[indexl]=0; 282232 } 283 /* now place the convolved messages P1 and P2 in the Dual */233 /* convolution using polynomial multiplication of POLY1 and 284 /* memory so that the PC host can retrieve it.^*/*/ 285 for(indexl . 0;^indexl < SIZE;^indexl++)234 /* POLY2.^Implemented by shifting and XOR vextors. 286 {*/ 287 *(MESG^+ indexl)^= vmesg[indexl];235 288 *(ME5GP1 + indexl)^= vmesgPl[indexl];236 mask . 11; 289 *(ME5GP2 + indexl)^. vmesgP2[indexl];237 for(indexl^= 0;^indexl < *K;^indexl++) 290 }238 ( 291239 firstbit^. 0; 292 return;240 lastbit .^0; 293 }241 294 /...................................................................242 /* shifting routine which shifts entire contents of ../.7 295 /*243 .7 /* vector.^Note that shifting does occur across 296297 The parameters chosen are used in interleaving by 128 bitblocks which represent 128/2 . 64 SYMBOLS244 /* element boundaries. .7.7 298245 for(index2^. 0;^index2 a SIZE;^index2++) 299 #define ROW^ 16^/* BLOCK INTERLEAVING PARAMETE246 { RS*/247 if^(indexl^==^0) 300 #define COLUMN 16248 { 301 *define BITS PER_SYMBOL^2249 302 #define SYMB3LS_PER LINE 16^/*LINE . 32 BIT WORD*/250 temp[index2]=vmesg[index2]; 303 #define FLAG1^Ox0T)000003 /* FLAG1 MUST CORRESPOND TO251 } 304 BITS PER SYMBOL252 else .7253 { 305254 byte = temp[index2]; 306 /...................................................................255 lastbit.byte & 0x80000000; 307256 temp[index2].^(byte « 1)1^(firstbit 308 interleaver^V1.00^Jan 93309257 if^(lastbit^!.^0) 310 This module will take the data given by pointer DEINT_ADDROct 6 1993 14:18:30^CSUB.0^Page, 7 Oct 6 1993 14:18:30^CSUB.0^Page 8311 and interleave it according to the parameters above and 359 {312 then place it starting at pointer INT_ADDR. 360313 361 int cur row,^cur_column,^pickbit,^addr, mod,^shift=0;314 This module is a block interleaver. 362 int symol=0;315 eg 363 int symbol_counter=0;316 364 long unsigned int TEMP . 0;317 Given: 365 for(cur_row=1; cur_row<=ROW; cur_row++)318 8 symbols/line 366 {319 4 bits/symbol 367320 [^4 X 4]^Result: 368 for(cur_column=0; cur_column<COLUMN; cur_column++)321 12345678^159D 159D26AE 369 1322 9ABCDEFO 26AE 378F4800 370 symbol = cur_row + cur column * ROW;323 37BF 371 addr =^(symbol - 1)^/^-YMBOLS PER_LINE;324 48C0 372 mod . (symbol 8 SYMBOLS_PER_LYNE);325 373 if^(mod =0)326 374 pickbit .^(SYMBOLS_PER_LINE - 1)^* B327 The module uses the current row and column of the array to c ITS_PER_SYMBOL;alculate 375 else328 the symbol to be placed in the resulting interleaved data word.376 pickbit .^( mod - 1)^*BITS_PER_SYMBOL;329 Once the symbol is known, the module calculates how much to 377increment 378 symbol_counter++;330 the data pointer DEINT_ADDR, and how much to shift the FLAG1 379. 380 shift = pickbit -^(symbol_counter - 1)^* BIT331 Next,^the module gets the symbol and stores it temporarily i S_PER_SYMBOL;n TEMP. 381 shift = shift *332333When enough symbols have been obtained to write a 32 bit word,the module places the interleaved word (TEMP) at INT_ADDR an382383/*The above line ensures the compiler compiles the shiftas a LSH rather than an ASH^DO NOT REMOVE*/d 384334 increments the pointer. 385 TEMP . TEMP I^(*(DEINT_ADDR + addr) &^(FLAG1335 « pickbit))«shift;336 Note: Regardless of the dimensions of the array the module w 386ill 387 /*if enough symbols for 32 bit word then write */337 always place the result in 32 bit lengths.^As shown above w 388 if (symbol_counter == SYMBOLS_PER_LINE)ith 389 {338 the 4X4 array giving rise to 2 32 bit lines of interleaved d 390 *(INT ADDR++ )^. TEMP;ata. 391 symboi_counter=0;339 392 TEMP = 0;340 393 )341 INT ADDR^-pointer to interleaved data 394 1342 DEIRT_ADDR -pointer to deinterleaved data 395 }343 396 1344 cur_row^-current row 397 /*******************************************************************345 cur_column^-current column ***/346 addr -amount to increment DEINT_ADDR 398347 pickbit^-bit amount to shift FLAG1 so that correct 399 int^RATES[8][6]^={348 symbol is obtained 400 {1,^1,^0,^1,^1,^01,^/*import^value^"0"349 shift -bit amount to shift symbol before placing i */t 401 {0,^1,^1,^0,^1,^11, /*import value^"1"350 in TEMP */351 mod^-intermediate calculation used for pickbit 402 {1,^0,^1,^1,^0,^11,^/*import^value^"2"352 symbol -current symbol */353 symbol_counter^-used to count symbols and write in 32 bit 403 {1,^1,^0,^1,^1,^01, /*import value^"3"354 lengths */355 404 (0,^1,^0,^1,^0,^1),^/*import^value^"4"356 ******************************************************************** */**********/ 405 (1,^0,^1,^0,^1,^0),^/*import^value^"5"357 */358 void interleaver(long int *DEINT_ADDR,^long int *INT_ADDR) 406 (1,^0,^1,^0,^1,^0),^/*import^6*/Oct 6 1993 14:18:30^CSUB.0^Page 9 Oct 6 1993 14:18:30^CSUB.0^Page 10407 {0,^1,^0,^1,^0,^1));^/*import^7*/ 465 combineheader^v1.02^Feb 93408 466 *409 void puncture(int CHOSENRATE,^long int *NEW,^long int *OLD,^int TOTAL)467 *^This module is used to combine the outputs of the adders ofthe410 { 468 *^convolutional encoder to form the header.^The header will e411 int^array[6]; ither412 unsigned long int mask=1; 469 *^be rate 1/2,^3/4 or 1/3.413 470 *414 int^index,^value,^bits,^newbits=0; 471 */415 472416 473 void combineheader(long int *P1,^long int *92,^long int *HEADER,^int417 for^(index=0;^index<6;^index++) NEWBITS)418 array[index]=RATES[CHOSENRATE][index]; 474 {419 475 int bits,^counter=0;420 for(bits=1;^bits<=TOTAL;^bits++) 476 unsigned long int templow=0;421 477 unsigned long int temphigh=0;422 value= array( bits % 6]; 478 unsigned long int mask=1;423 if^(value==1) /*keep bit*/ 479 unsigned long int maskhigh=0x10000;424 480 /* NEWBITS must be halfed and rounded up since every word yo425 if^(^(*OLD & mask)^> 0^) u give426 *NEW^I=^(^1 « newbits); 481 this module it automatically combines it into 2 words.^S427 o if428 newbits++; 482 NEWBITS=64^the module changes it to 64/2=32 since it wor429 ks on430 /*^else if^(value>1) 483 the high^(16-31)^and low (0-15) bits simultaneously givin431 g rise432 for(index=0;^index<value;^index++) 484 to 2 bits for every one that NEWBITS counts.433434 if^(^(*OLD & mask)^> 0^) 485 NEWBITS =^(NEWBITS/2)+^(NEwBITS%2);435 *NEW I=^( 1 « newbits); 486436 487 for^(bits=1;^bits<=NEWBITS;^bits++)437 488438 newbits++; 489 /*^if^(^((*P1^& mask)^I^(*P2^& mask)<<l)^>^0^)439 if^(newbits==32) 490440 491 templow 1= 1 « counter;441 newbits=0; 492442 493 if^(^((*P1 & maskhigh)^I^(*P2 & maskhigh)«1)^>0^)443 NEW++; 494 temphigh 1= 1 « counter;^*/444 495445 ) 496446 )^*/ 497447 498 templow^I=^(^(*Pl&mask)^I^(*P2&mask)«1^)«counter;448 mask«=1; 499449 if(mask==0) 500 temphigh^1-=(^(*Pl&maskhigh)»1^I^(*P2&maskhigh)^)»450 (15-counter);451452OLD++;mask=1;501502 counter +=1;453 ) 503 mask«=1;454 if^(newbits==32) 504 maskhigh<<=1;455 505456 newbits=0; 506 if^(maskhigh==0)457 507458 NEW++; 508 mask=1;459 509 maskhigh=0x10000;460 510 *HEADER++=templow;461 } 511 *HEADER++=temphigh;462 512 counter=0;463 /******************************************************************* 513 templow=0;*** 514 temphigh=0;464 515 Pl++;Oct 6 1993 14:18:30 CSUB.0^Page 11516517518P2++;519 if^(maskhigh^!=0)re not^*//* Finished in loop but if we we520 (ivisable*//* not given an amount of bits d521 *HEADER++=templow;maining *//* by 32 then we must get the re522 *HEADER++=temphigh; /* bits that are combined.523 )524 )Oct 6 1993 14:23:52^ADAPT.0^Page 1 Oct 6 1993 14:23:52^ADAPT.0^Page 21 #include^<stdlib.h> 54 .2 *include <stdio.h> 55 *^Data^I^CRC^I^Tail^I3 *include <graphics.h> 56 *^3/4^635 32^54 #include <conio.h> 57 *^1 8595 #include^ "c:\lib\tms30.h " 58 *^1/2^4116 59 .7 #define CONTROL WORD^(0X30008) 60 ...*..............**..........********...........*****..........*****8 #define VIRGIN HEADER^(0x30010) ..../9 #define VIRGIN_DATA^(0x30013) 6110 62 struct^window (11 #define ACKO^(0x3007b) 63 int left;12 #define STROBE_RCVR^(0x3007c) 64 int right;13 #define STROBE HOST (0x3007d) 65 int top;14 #define FLAGOPT^(0x30000) 66 int bottom;15 #define MENU OPTION^(0x30006) 67 };16 #define NOT _READY 01 6817 #define READY^11 69 void main(void)18 #define TROUBLE (0x30130) 70 {19 #define RUN Offffl 71 FILE *fp;20 72 int header[4],^transmit[64],^rovr[64],frame[1000],output[20]2122 /..............................*****.........*******......******.... 73 int menu,^rate,^packet,^control,^midx, midy,^locx,^boy;..*. 74 float ber2, value;23 .^ADAPT.0^SEPT 1993 75 int indexl;24 76 char beep = 7;25 Adaptive Complementary Punctured Convolutional Coding Scheme 77 unsigned long int current,^index2;for a 78 unsigned int temp,berword;26 *^Conventional Type II Stop and Wait ARQ System. 79 unsigned long int ber,symbols, oldber;27 80 int ack,^nack,^trans,^oldtrans,^oldnackr0;28 Using rate 1,^3/4,^and 1/2 codes derived from a rate 1/2 81 int CPC1,^CPC2,^CPC1CPC2;29 mother code. 82 int headfail,^crcfail,^lost,^tot;30 8331 See DSP software for actual perforation matrix and generator 84 int^noldtrans,^N;32 polynomials. 85 float^noldinfobits,^ninfo,^rat,^blockn=0;33 8634 8735 *^Frame Structure: 88 int errorcode;36 89 short errormsg;37 8 bit preamble + 24 bit flag^ 32 b 90 long int STRT,^temps,response;its 91 struct window rcv,^xmit,^stat;38 9239 .^AA^294153. 93 int^address,^Hr,^Na,^length,^PlorP2,^CSI;40 94 int successframe, headllow, headlhigh, head2low, head2high;41 * CONVOLVED RATE 1/2 HEADER^ 128 bits 95 float^infobits,^totalbits,^infoconstant,^Current_factor=1.2;42 9643 *^address^I^Na^I^Hr^I^length^I 9744 * 14 4 4 10 >32 bits 9845 99 /*graphics variables*/46 P1 or P2^I^CSI^I^Reservedl^CRC^I^Tail^I 100 int gdriver=DETECT, gmode,bkco1=DARKGRAY,maxx, maxy;47 2^2 7^16 5 >32 bits 101 char msg[120];48 10249 * CONVOLVED DATA 864 103 for^(index1=0;^indexl<1000;^indexl++)bits 104 frame[index1]=0;50 105---- 10651 1024 107bits 108 /*Initialize graphics screen*/52 109 initgraph(&gdriver,^&gmode,53 * UNCONVOLVED DATA - for use with rate 3/4 punctured from a rate 1/2 110 errorcode . graphresult();Oct 6 1993 14:23:52^ADAPT.0^Page 3 Oct 6 1993 14:23:52^ADAPT.0^Page 4111 if^(errorcode^!= grOk) 169 outtextxy(10,^135,^msg);112 f 170 sprintf(msg,^"# of NACKs arrived:");113 printf("graphics error:%s\n",^grapherrormsg(errorcod 171 outtextxy(10,^145,^meg);e)); 172 sprintf(msg,^"Current Frame #^(of 1000):");114 printf("Press any key to halt:"); 173 outtextxy(10,^155,^msg);115 getch(); 174 sprintf(msg,^"Current Rate:");116 exit(1); 175 outtextxy(10,^165,^msg);117 176118 } 177 settextjustify(CENTER_TEXT, TOP TEXT);119 cleardevice(); 178 sprintf(msg,^"Receiver DSP Board 0x290");120 setbkcolor(bkcol); 179 outtextxy(maxx*.75,^85,^msg);121 maxx=getmaxx()-2; 180 settextjustify(LEFT_TEXT,^TOP_TEXT);122 maxy=getmaxy(); 181 sprintf(msg,^"Error Free Rcvd Farmes:");123 midx = maxx/2; 182 outtextxy(midx+10,^115,^meg);124 midy . maxy/2; 183 sprintf(msg,^"8 of lost Frames:");125 setlinestyle(SOLID_LINE,^1,^THICK_WIDTH); 184 outtextxy(midx+10,^125,^meg):126 rectangle(0,^0,^maxx,^maxy*.15); 185 sprintf(msg,^"# of error Frames:");127 rectangle(0,^maxy*.15,^maxx*.5,^maxy*.5); 186 outtextxy(midx+10,^135,^meg);128 rectangle(maxx*.5,^maxy*.15,^maxx,^maxY*.5); 187 sprintf(msg,^"Throughput:");129 rectangle(0,^maxy*.5,^maxx,^maxy); 188 outtextxy(midx+10,^145,^meg);130 setlinestyle(SOLID LINE,^1, NORM_WIDTH); 189131 sprintf(msg,^"STATUS WINDOW"); 190 sprintf(msg,^"Total ACKs");132 outtextxy(10,^maxy*.5+5,^msg); 191 outtextxy(10,^maxy*.5+20,^msg);133 192 sprintf(msg,^"CPC Code 1");134 =^.24*maxy; 193 outtextxy(210,^maxy*.5+20,^msg);135 rcv.bottom =^.48*maxy; 194 sprintf(msg,^"CPC Code 2");136 rcv.left^=^.83*maxx; 195 outtextxy(360,^maxy*.5+20,^meg);137 rcv.right =^.99*maxx; 196 sprintf(msg,^"CPC 1 & CPC 2");138 =^.24*maxy; 197 outtextxy(510,^maxy*.5+20,^msg);139 xmit.bottom =^.48*maxy; 198140 xmit.left^=^.33*maxx; 199 sprintf(msg,^"Total NACKs");141 xmit.right .^.48*maxx; 200 outtextxy(10,^maxy*.5+50,^nag);142 = maxy*.56; 201 sprintf(msg,^"Header Failure");143 stat.bottom = maxy*.6; 202 outtextxy(210,^maxy*.5+50,^nag);144 stat.left^=^10; 203 sprintf(msg,^"Data CRC Failure");145 stat.right^. maxx*.98; 204 outtextxy(360,^maxy*.5+50,^nag);146 205 sprintf(msg,^"Lost Frame");147 /* Set Text and Headings for the display screen^*/ 206 outtextxy(510,^maxy*.5+50,^msg);148 settextjustify(CENTER_TEXT,^TOP_TEXT); 207149 sprintf(msg,^"Statistics Module for:"); 208 /*End of text set up */150 outtextxy(midx,^15,^meg); 209151 sprintf(msg,^"Adaptive Complementary Punctured Convolutional 210 errorcode=SelectBoard(0x290);Stop and Wait Type II ARQ scheme"); 211 if^( errorcode == 0^)152 outtextxy(midx,^25,^meg); 212 printerror(1);153 sprintf(msg,^"PI74 DQPSK Modulation Scheme"); 213154 outtextxy(midx,^35,^meg); 214 errorcode=LoadObjectFile("RCVRADAP.OUT");155 sprintf(msg,^No Code Combining"); 215 if^(errorcode^!=^0)156 setcolor(RED); 216 printerror(2);157 outtextxy(midx,^45,^meg); 217 Reset();158 setcolor(WHITE); 218 setcolor(RED);159 219 settextjustify(CENTER_TEXT,^TOP_TEXT);160 220 sprintf(msg,^"Loaded and running...");161 sprintf(msg,^"Transmitter DSP Board 0x390"); 221 outtextxy(maxx*.75,^95,^meg);162 outtextxy(maxx/4,^85,^msg); 222 for(index1=0;^indexl<3000;^indexl++);163 settextjustify(LEFT_TEXT,^TOP_TEXT); 223164 sprintf(msg,^"Total Frames sent:"); 224165 outtextxy(10,^115,^msg); 225 errorcode=SelectBoard(0x390);166 sprintf(msg,^"Baud Rate"); 226 if^(^errorcode == 0^)167 outtextxy(10,^125,^nag); 227 printerror(3);168 sprintf(msg,^"# of ACKs arrived:"); 228Oct 6 1993 14:23:52^ADAPT.0^Page 5 Oct 6 1993 14:23:52^ADAPT.0^Page 6229 errorcode=LoadObjectFile("xmitadap.out"); 286 transmit(^index2^]^. 0;230 if^(^errorcode^!.^0^) 287231 printerror(4); 288 /*rate decision must be made here*/232 Reset(); 289 N.trans-noldtrans;233 sprintf(msg,^"Loaded and running..."); 290 ninfo.infobits-noldinfobits;234 outtextxy(maxx/4,^95,^msg); 291 if^(N>=5)235 settextjustify(LEFT_TEXT, TOP_TEXT); 292 {236 setcolor(WHITE); 293 blockn.(2.0*(ninfo/(1056.0*N)));237 294 if^(CSI^..^1)238 295 i239 N=0; 296 if^(blockn<1.18)240 rat.0.0; 297 {241 noldtrans.0; 298 CSI^.^2;242 noldinfobits.0.0; 299 goto out;243 ninfo.0.0; 300 )244 blockn.0.0; 301 }245 302 else if^(CSI^.. 2)246 oldtrans.0; 303 f247 trans.0; 304 if^(blockn>1.19)248 ack =0; 305 {249 CPC1.0; 306 CSI = 1;250 CPC2.0; 307 gob o out;251 CPC1CPC2.0; 308 }252 nack=0; 309 else if^(blockn<.77)253 headfail=0; 310 1254 crcfail=0; 311 CSI^= 3;255 infobits=0.0; 312 gob o out;256 totalbits.0.0; 313 }257 infoconstant.0.0; 314 )258 tot.0; 315 else if^(CSI^.. 3)259 316 {260 successframe.0; 317 if^(blockn>.76)261 bar =^0; 318 {262 oldber=0; 319 CSI . 2;263 nack .0; 320 goto out;264 lost=0; 321 }265 locy=0; 322 )266 locx.10; 323 ninfo.0.0;267 current . 01; 324 out: noldinfobits . infobits;268 response .01; 325 N.0;269 Put32Bit(ACKO,^DUAL,^69691); 326 noldtrans . oldtrans;270 327 goto out2;271 /*******************************.**..*********************** 328 }****/ 329272 /*^Initialize Header variables*/ 330273 address = Ox1000;^ /* 14 bit address*/ 331274 Ns .^0; 332 out2: if^(CSI^..^1)275 Hr .^0; 333 {276 length . 608; /* full frame */ 334 tot.52;277 PlorP2^. 1;^ /* which code to us 335 infoconstant.859.0;e^*/ 336 }278 CSI = 3; /*channel state info 337 else if^(CSI^..^2)*/ 338 {279 339 tot . 38;280 340 infoconstant-635.0;281 341 )282 342 else if^(CSI == 3)283 for^(index1.0;^successframe<1000;^indexl++) 343 (284 1 344 tot = 24;285 for^(index2.0;^index2<64;^index2++) 345 infoconstant = 411.0;Oct 6 1993 14:23:52^ADAPT.0^Page 7 Oct 6 1993 14:23:52^ADAPT.0^Page 8346 } 398 menu = Oxl;347 399 rate . 0x4;348 400 packet = 0;349 401350 for^(index2=0;^index2<tot;^index2++) 402 control= menu^I^rate^I^packet;351 ( 403352 transmit[^index2^]^= rand(); 404 errorcode . Put32Bit(CONTROL_WORD,^DUAL,^control);353 if^(^(index2^+^1)^%^8^==^0) 405 if^(errorcode^!.^0^)354 transmit[index2]^= transmit[index2] 406 printerror(6);&^Ox07ff; 407355 408 /*frame transmitted*/356 ruvr[^index2^]^. 0; 409 setviewport(xmit.left,^,^xmit.right,^xmit.bo357 /*generate 608 random^data bits to be transmitted * ttom,^1);/ 410 clearviewport();358 } 411 sprintf(msg,^"^%d",^trans);359 /*transmit[37]=0;*/ 412 outtextxy(10,^0,^msg);360 413 sprintf(msg,^"^18.93^kHz");361 /*************************************************** 414 outtextxy(10,^10,^meg);******/ 415 sprintf(msg,^"^%d",^ack);362 /* Build Header 416 outtextxy(10,^20,^meg);*/ 417 sprintf(msg,^"^%d",nack);363 address . address +1; 418 outtextxy(10,^30,^msg);364 PlorP2=1; 419 sprintf(msg,^"^%d",^index1+1);365 420 outtextxy(10,^40,^meg);366 do( 421 if^(CSI^==^1)367 trans++; 422 rat=1.0;368 if^(response > 1000)^/*^if retransmit a 423 else if^(CSI == 2)lternate*/ 424 rat= .75;369 t 425 else if^(CSI == 3)370 if^(response^!= 9999) 426 rat=.5;371 ( 427 sprintf(msg,^"%3.3E",rat);372 if^(PlorP2^== 1^) 428 outtextxy(10,^50,^msg);373 PlorP2 . 2; 429374 else 430375 PlorP2 = 1; 431376 ) 432377 } 433 errorcode.WarmSelect(0x290);378 434 if^(^errorcode .. 0^)379 for^(index2=0;^index2<4;^index2++) 435 printerror(1);380 header[^index2]^. 0; 436381 437 menu . 3;382 438383 header[0]^. Ns «14^I^address; 439 Put32Bit(MENU_OPTION, DUAL, menu);384 header[1]^.^(Ns » 2)^I^(Nr « 2)^I^(length «6); 440385 header[2]^=^(PlorP2)^I^(CSI «2); 441386 442 for(index2=0;^index2<30000;^index2++);387 WrBlkInt(VIRGIN_HEADER,^DUAL,^2,^header); 443 for(index2=0;^index2<30000;^index2++);388 /* Header built and sent to DSP transmitter 444 for(index2=0;^index2<30000;^index2++);*/ 445 for(index2=0;^index2<30000;^index2++);389 /*************************************************** 446******/ 447 Put32Bit(STROBE_RCVR,^DUAL,^Oxffffl);390 448391 449 for(index2=0;^index2<30000;^index2++);392 errorcode . WrBlkInt(VIRGIN_DATA, DUAL, tot/2,^trans 450 for(index2=0;^index2<30000;^index2++);mit); 451 for(index2.0;^index2<30000;^index2++);393 if^(errorcode^!=^0) 452 for(index2=0;^index2<30000;^index2++);394 printerror(5); 453395 454396 455 while(Get32Bit(sTROBE_HOST,^DUAL)=.01);397 456Oct 6 1993 14:23:52^ADAPT.0^Page 9 Oct 6 1993 14:23:52^ADAPT.0^Page 10457 Put32Bit(STROBE HOST,^DUAL,^01); 515 setcolor(GREEN);458 response = Get3Bit(ACKO,^DUAL); 516 sprintf(msg,^"^%d",^ack);459 Put32Bit(ACKO,^DUAL,^88881); 517 outtextxy(15,^5,^msg);460 518 sprintf(msg,^"^%d",^CPC1);461 if^(response < 1000) 519 outtextxy(215,^5,^msg);462 ( 520 sprintf(msg,^"^%d",^CPC2);463 ack++; 521 outtextxy(365,^5,^msg);464 successframe++; 522 sprintf(msg,^"^%d",^CPC1CPC2);465 infobits +=infoconstant; 523 outtextxy(515,^5,^msg);466 totalbits +=1056.0; 524467 525468 if^(response == 100) 526 setviewport(stat.left,^maxy*.63,^stat.right,^maxy*.6469 CPC1++; 7, 1);470 else if^(response == 200) 527 clearviewport();471 CPC2++; 528 setcolor(BLUE);472 else if^(response == 300) 529 sprintf(msg,^"^%d",^flack);473 CPC1CPC2++; 530 outtextxy(15,^5,^meg);474 531 sprintf(msg,^"^%d",^headfail);475 } 532 outtextxy(215,^5,^msg);476 else 533 sprintf(msg,^"^%d",^crcfail);477 ( 534 outtextxy(365,^5,^msg);478 nack++; 535 sprintf(msg,^"^%d",^lost);479 totalbits +.1056; 536 outtextxy(515,^5,^meg);480 if^(response == 9999) 537 setcolor(WHITE);481 headfail++; 538482 else if^(response == 6666) 539 setcolor(WHITE);483 crcfail++; 540 WarmSelect(0x390);484 else if^(response == 8888) 541485 lost++; 542 }while^(response , 10001);486 } 543487 544 frame[indexl]^= trans - oldtrans;488 545 oldtrans = trans;489 RdBlkInt(FLAGOP1,^DUAL,^tot/2+5,^rcvr); 546490 547 }491 548492 ) 549 printf("%c",beep);493 550 printf("%c",beep);494 551 printf("%c",beep);495 552 printf("%c",beep);496 553497 554 for^(index1=0;^indexl<20;^indexl++)498 555 output[indexl]=0;499 556500 last: 557 for^(index1=0;^indexl<1000;^indexl++)501 setviewport(rcv.left,^,^rcv.right,^rcv.bottom 558 output[frame[indexl]]++;,^1); 559502 clearviewport(); 560 setviewport(stat.left,^maxy*.7,^stat.right,^maxy*.97,^1)•503 sprintf(msg,^"^%d",^ack); 561 sprintf(msg,^"Number of Transmissions required for Reception504 outtextxy(10,^0,^meg);505 sprintf(msg,^"^%d",^lost); 562 outtextxy(5,^5,^meg);506 outtextxy(10,^10,^meg); 563507 564 for^(index1=0;^indexl<20;^indexl++)508 sprintf(msg,^"^%d",^crcfail+headfail); 565 (509 outtextxy(10,^20,^meg); 566510 sprintf(msg,^"^%7.4E",2.0*infobits/totalbits); 567 sprintf(msg,^"^%d",^indexl);511 outtextxy(10,^30,^meg); 568 outtextxy(30*indexl,^20,^meg);512 569513 setviewport(stat.left,^,^stat.right,^ 570 setcolor(GREEN);ttom, 1); 571 sprintf(msg,^"^%d^",^output[indexl]);514 clearviewport(); 572 outtextxy(30*indexl,^30,^meg);Oct 6 1993 14:23:52^ADAPT.0^Page 11573^ setcolor(WHITE);574575576577^/*578 for (index2=0; index2<64; index2++)579 printf("%x ",transmit[ index2 1);580581^printf("\n");582 for (index2=8; index2,64; index2++)583 printf("%x ",rovr[ index2 1);584585^exit (1)586587588589590^}591592593^printerror(int number)594595 char msg[80);596^int maxy;597598 switch (number)599600^ case 1:sprintf(msg, "Select Board 290h has failed.")601 break;602^ case 2:sprintf(msg,603 break;604 case 3:sprintf(msg,"Loading RCVR.out has failed.");"Select Board 390h has failed.")605^ break;606 case 4:sprintf(msg, "Loading F.OUT has failed.");607 break;608 case 5:sprintf(msg, "Downloading transmission frameto DSP board has failed.");609^ break;610^case 6:sprintf(msg, "Writing Control Word to transmitter has failed");611 break;612^ default:sprintf(msg, "Problem with error print muttne.");613614615616617618619620621622623^}}maxy=getmaxy();setcolor(GREEN);setbkcolor(WHITE);outtextxy(10, maxy*.7+15, msg);/*getch();*/exit )l)return(S);Oct 6 1993 14:48:30^XMITADAP.ASM^Page 1 Oct 6 1993 14:48:30^XMITADAP.ASM^Page 21 451 .word 7h ;Polynomial2 .10111,1+x+x°2+23 ,•XMITADAP.asm^V1.00^Dec 92^V1.01 Jan 93 52x°4.word 9665 ;CRC-CCITT4 V1.02^Mar 93 53 .word 374732215 ;CRC-325 v1.03 Apr 93 54 .word B1492AAh ;flag for packet6 V2.00^Aug 93 55 .word ;Q_START --> 809c067 V2.01 Sept 93 56 .word ;Q_START(1)8 ; The purpose of this code is to set up the dsp board environm 57 .word ;Q_START(2)ent, 58 .word ;Q_START(3)9 , variables,^and memory.^This code is used as the main interf 59 .word ;Q_START(4)ace 60 .word ;Q_START(5)10 , between the PC and the dsp board. It places all necessary 61 .word ;Q_START(6)11 ; assembler and C routines in memory and then awaits in a simp 62 .word ;Q_START(7)le 63 .word ;Q_END --> 809c0e12 , loop, where the ARQ shell can poke the appropriate info into 64 .word ;Q_END(1)13 ; DSP memory and then run the appropriate routine. 65 .word ;Q_END(2)14 , 66 .word ;Q_END(3)15 67 .word ;Q_END(4)16 68 .word ;Q_END(5)17 69 .word ;Q_END(6)18 .include VARS.ASM 70 .word ;Q_END(7)19 .global^.bss 71 .word 09c06h ;Q_START --->809c1620 .global cinit^ ;init table^(from li 72 .word 09c0Eh ;Q_END --->809c17nker)too .global _c_in;starting address^(C standard)739C18.word 0804214 ;DIGITAL PORT ADDRESS --->8021 .global _interleaver 74 TAB_ENC .WORD ;pi/4 QPSK encoding table22 .global _puncture 75 .WORD ;---> 809c1923 .global _combineheader 76 .WORD24 .global^_conv^ ;the convolutional en 77 .WORDcoding 78 .WORD25 ;routine 79 .WORD26 .global^_polydiv^;polnomial division r 80 .WORDoutine 81 .WORD27 82 .WORD28 83 .WORD29 .sect^".init"^ ;interrupt section 84 .WORD30 RESET .word^_c_int00 ;RESET -> start addr 85 .WORDass 86 .WORD31 INTO .word^NO ;all others to dummy 87 .WORDreti 88 .WORD32 INT1 .word^INT_TRANSMISSION^;except the sync int 89 .WORD33 INT2 .word^NO 90 .WORD34 INT3 .word^NO 91 .WORD35 XINTO .word^NO 92 .WORD36 RINTO .word^NO 93 .WORD37 XINT1 .word^NO 94 .WORD38 RINT1 .word^NO 95 .WORD39 TINTO .word^NO 96 .WORD40 TINT1 .word^NO 97 .WORD41 DINT .word^NO 98 .WORD42 99 .WORD43 100 .WORD44 101 .WORD45 ; Data section to initially be loaded at $30000h but then 102 .WORD46 moved to $809c00^(on chip ram). 103 .WORD47 104 .WORD48 .data 105 .WORD49 .word^5 ;constraint length 106 ICHAN .WORD fff0000H ;IBIT CHAN^1 volt50 .word^19h^;polynomiall .11001.1+x°3+x^ 107 .WORD a780000H ;0.707Oct 6 1993 14:48:30^XMITADAP.ASM^Page 3 Oct 6 1993 14:48:30^XMITADAP.ASM^Page 4108 .WORD^0 ;0.00 157109 .WORD^-5a780000H^;-0.707 158 LOT^@PRIMCTRL, ARO^;Hardware specific i110 .WORD^-7fff0000H ;-1.00 nit111 .WORD^-5a780000H^;-0.707 159 LOT^INITIAL,^RO112 .WORD^0 160 STI RI,^*ARO113 .WORD^5a780000H 161 LOT^@EXPCTRL, ARO114 QCHAN .WORD^0 162 LOT NULL,^RO115 .WORD^5a780000H 163 STI^RI,^*ARO116 .WORD^7fff0000H 164 LOT @SERIALO, ARO^;SET DIGITAL OUTPUT117 .WORD^5a780000H TO 0118 .WORD^0 165 LDI^2H,^RO119 .WORD^-5a780000H 166 STI ED,^*ARO120 .WORD^-7fff0000H 167121 .WORD^-5a780000H 168122 .WORD^809C19H123 .WORD^809C39H 169 This portion of code is absolutely necessary when mixing C124 .WORD^809C41H 170 modules with assembly language.^It ensures that the125 171 variables defined in the C module are properly initialized.126 172127 173addressLDP^CODES^ ;get page of stored128 Variables to be ued for initialization. 174 LDI^@INIT_ADDR, ARO^;get address of mit129 tables130 STACK .usect^".stack",STACK_SIZE 175 CMPI^-1, ARO^ ;if RAM model,^skip131 mit132 .text 176 BEQ^init_done133 STACK_ADDR .word^STACK^ ;address of stack 177 LOT *ARO++, R1^;get first count134 INIT_ADDR .word^cinit ;address of mit tab 178 BZD^init_done ;if 0,^nothing to doles 179 LOT *ARO++, AR1 ;get dest address135 PRIMCTRL .word^00808064h ;primary bus control 180 LDI^*ARO++, RI^;get first wordaddress 181 SUBI^1,^121 ;count^-^1136 EXPCTRL .word^00808060h^;expansion bus contr 182ol address 183 do_init: RPTS^R1 ;block copy137 TIMECTL1 .word^808030H ;timer 1 control 184 STI NO,^*AR1++138 SERIAL() .word^808042h ;FSX/DX/CLKX port co 185 II LDI^*ARO++,^RIntrol 186 LDI RI,^R1 ;move next count int139 TIMECTL2 .word^808020h^ ;timer 2 control o R1140 RSTCTRLera.word^601h ;reset value for tim 187epeatBNZD^do_init ;if there is more,^r141 PERIOD .word^808038h ;timer 1 period 188 LDI^*ARO++, AR1^;get next dest addre142 COUNT .word^55 ;period value for ti SSmar 1 189 LDI^*ARO++,^RI ;get next first word143 SETCTRL .word^6c1h^ ;set value for timer 190 SUBI^1,^R1 ;count - 1s 191144 RAM1 .word^809c00h ;On chip ram area 192145 DUALSTART .word^30000h ;temp variables146 DUALEND .word^33300h^ ;change for 64k 193 This code block copies all of the variables placed at $30000147 DUALMEM .word^300BFh148 :******************************************************************* 194 and moves them to the on chip memory area at $809c00 - $80a0*** 00149 The following code sets up the stack pointer and then 195150 initializes the DSP hardware as outlined in the Technical 196 init_done:151 Reference Manual. 197 LDI @DUALSTART, ARO152 198 LDI @RAM1, AR1153 _c_int00: 199 LDI *ARO++,^RO ;since parallel instruction154addressLDP^CODES^ ;get page of stored 2000;coming up must initialize R155 LDI^@STACK_ADDR,^SP^;load the address in 201to SP 202 RPTS DATALENGTH156 LDI^SP,^FP ;and into FP too 203 LDI *ARO++,^RIOct 6 1993 14:48:30^XMITADAP.ASM^Page 5 Oct 6 1993 14:48:30^XMITADAP.ASM^Page 6204 IISTI^RO,^*AR1++ 259 STI R2, @MENU_OPTION205 260 BZ MENU^ ;if no choice loop back206 261207 262263 ;LSH -2,^RO208 264 ;AND RI,^121,^R3 ;get^data RATE209 LDI @DUALSTART, R6 ;clear DUAL memory 265 ;STI R3,^ORATE210 LDI @DUALEND, R7 ;$30000^-->$33300 266211 CALL CLEAR 267 LSH -2,^RI212 268 LDI PACKET_MASK, R1^;get PACKET_NUM213 LDP ONCHIP ;initialize variables 269 AND RI, R1, R4214 LDI 0, RI^ ;used in transmission interrupt 270 OTT R4, @PACKET_NUM215 LDI 0,^R1 ;routine 271216 LDI^32,^R2 272 LDP CODES217 STI RI, @SINE POINTER ;sine_pointer = $809c08 273 LDI @VIRGIN_HEADER, AR1218 STI RI,^@COSIT4E POINTER ;cosine_pointer.$809c08 274 LDI *AR1++, RI219 STI R2, @POINT EOUNT ;point_count = 32 275 LOT LENGTH MASK, R1^;get LENDATAO220 STI R1,^@DATA in-TORD ;data_word . 0 276 LSH -22,^RI221 STI R1, @CURRNT ADDRESS ;current_address = 0 277 AND RI, R1, R5222 OTT R1, @END ADDiESS ;end address . 0 278 ldi*arl,^r0223 STI R1, @Q_OTFSET ;q_oTfset . 0 279 and 3,^r0 ;get puncture matrix#224 STI R1,^@TRANSMISSION ;transmission = 0^(not busy) 280 ldi *arl,^rl225 STI R1, @Q_OFF TRANS ;q_off_trans . 0 281 and 12,^rl226 STI R1, @GET_NWFRAME_FLAG ;flag .^0 282 lsh -2,^rl ;get rate to be used227 LDI 40H,^BK ;BK . 40H 283 LDP DUAL228 284 sti rO,^@CODE229 285 sti rl,^ORATE230 286 STI R5, @LENDATAO287231 This section places the flag for the frames in the appropria 288te 289 CMPI 1,^R2232 ;^memory locations. 290 BZ OPTION1233 291 CMPI 2,^R2234 ADD_FLAG: 292 BZ OPTION2235 LDP ONCHIP 293 CMPI 3,^R2236 LDI @FLAG,^RI 294 BZ OPTION3237 LDP CODES 295 LDI 2,^R7238 LDI @FLAGOP1, AR1 296 BR ERROR239 ;LDI^15,^RC ;16 packets 297 DEAR: BR DEAR240 ;RPTB ENDLOOP1 298 ;*******************************************************************241 addi 63h,^an ;cut it out because interef ***eras 299 OPTION 1 - ADAPTIVE SCHEME242 ;with combine area must be c 300 Construct frame from given header and data. Uselean!! 301 rate 1/2 for header and appropriate CPC matrix243 302 ; chosen rate of data packet.244 OTT RO,^*AR1 303 OPTION1:245 ENDLOOP1: 304246 ;ADDI 21h, ART ;get next flag address 305 ;***********************************************************247 ****248 306 ;CRC calculation and appending to header information stored249 307 ;at VIRGIN_HEADER250 308251 ;strip information from CONTROL_WORD 309 LDP CODES252 310 LOT @VIRGIN_HEADER, AR1^;get original header and place253 START_OF_MAIN_ROUTINE: 311 LOT *AR1++, RI^ ;at HEADBUF1 padded with x°16254 312 LDI *AR1,^R1 ;zeros255 LDP DUAL 313 LDI @HEADBUF1, AR5256 MENU:^LDI @CONTROL WORD, RI 314257 LDI MENU_MASi, R1 ;get MENU_OPTION 315 LDI @HIGH MASK, R2258 AND RI,^R1,^R2 316 LSH 16, RIOct 6 1993 14:48:30^XMITADAP.ASM^Page 7 Oct 6 1993 14:48:30^XMITADAP.ASM^Page 8317 AND RO,^R2,^R3 372318 LSH -16,^R3 373319 OR R1,^R3 374 LDP CODES320 LSH 16,^RO 375 LDI OFRAMEBUFP1, AR3^;where to place result321 STI RU,^*AR5++ 376 LDI 64, RO^ ;bit length of adderl322 STI R3,^*ARS__ 377 LDI @HEADBUF1, ARO ;adder 1 output bits323 378 LDI OHEADBUF2, AR1^;adder 2 output bits324 LDI 17,^RO K constraint length 379325 LOT POND CCITT, R1^ POLY divisor 380 PUSH NO326 LDI 2, RI length of header in 32 bit 381 PUSH AR3words 382 PUSH AR1327 LDI @HEADBUF2,^R3 where to place RESULT^(not 383 PUSH AROneeded 384 CALL^combineheader328 in this CRC case) 385 SUBI^.,^SP329 386330 PUSH AR1^ save VIRGIN_HEADER+1 387 ;End of header construction331 PUSH R3 *RESULT . HEADBUF2 388332 PUSH R2 TOTAL . 2 389 ;***********************************************************333 PUSH R1 POLY . CRC_CCITT ******334 PUSH AR5^ MESGDATA = HEADBUF1 390 ;^Data CRC calculation335 PUSH RU K = 17 391336 392337 393338 CALL _polydiv^ Do CRC calculation 394 LDI @VIRGIN_DATA, ARO^;start of data339 CRC checksum returned in R 3950 396 LDI 33,^RO ;K constraint length340 397 LDI @CRC 32,^R1 ;POLY341 398 LDI ODATT,BUFP1,^R3 ;address to store RESULT342 SUBI 5,SP^ clean stack 399 LDI @VIRGIN_DATA, AR3^;*MESGDATA343 POP AR1 get back VIRGINHEADER+1 400 SUBI 1, AR3 ; same as premultiply by x^K344 LSH 5, RU shift CRC before placing 401345 LDI *AR1, R1 in VIRGIN_HEADER+1 402 LDP DUAL346 OR R1,^RU 403 LDI ORATE, R7347 STI RU,^*AR1 404 LDP CODES348 405 CMPI 1,57349 ;End of CRC calculation and appending to header info 406 LDIZ 27, R2^ ;26 DATA WORDS + BLANK CRC350 407 CMPI 2,^R7351 **;*********************************************************** 408409LDIZ 20, R2 ;19 DATA WORDS + BLANK CRCCMPI 3,^R7352 ;Convolutional encoding of header information stored at 410 LDIZ 13, R2 ;12 DATA WORDS + BLANK CRC353 ;VIRGIN HEADER.^Resulting encoded header is stored at 411 CMPI 0,^R7354 ; AdderT output encoded header bits^ > HEADBUF1 412 BZ ERROR355 ; Adder2 output encoded header bits^ > HEADBUF2 413356 414357 415358 LDI @VIRGIN HEADER, ARO^; data to be convolved 416 LDI R2,^R7359 LDI OHEADBUT.1, AR1^; address of adderl bits 417 PUSH R7360 LDI @HEADBUF2, AR2 ; address of adder2 bits 418 PUSH R3 ;*RESULT^(not used)361lyeLDI 2,^RO ;^# of 32 bit words to convo 419rds +PUSH R2^ ;TOTAL = length in 32 bit wo362 420 ;^1 for CRC32363 PUSH RU^ ;^SIZE 421 PUSH R1^ ;POLY . CRC_32364 PUSH AR2 ; MESGP2 422 PUSH AR3 ;MESGDATA = VIRGIN_DATA365 PUSH AR1 ; MESGP1 423 PUSH RU ;K = constraint length366 PUSH ARO^ ; MESG 424367 425 CALL _polydiv368 CALL _conv 426369 427 SUBI 5,^SP370 SUBI 4,^SP 428 ADDI 1, AR3 ;Point to @VIRGIN_DATA371 ;End of convolutional encoding of header 429 _...-Oct 6 1993 14:48:30^XMITADAP.ASM^Page, 9 Oct 6 1993 14:48:30^XMITADAP.ASM^Page 10430 POP R7 486 LDI @DATABUFP1, ARO^;pointer to data bits P1431 SUBI^1,^R7 487 LDI @DATABUFP2, AR1 ;pointer to data bits P2432 ADDI R7, AR3 488 LDI @FRAMEBUFP1, AR2 ;pointer to frame P1433 OTT RO,^*AR3^ ;place CRC at end of data 489 LDI @FRAMEBUFP2, AR3^;pointer to frame P2434 490435 491436 ;At this point the data exists @VIRGIN_DATA with a 32 bit CR 492 ;***********************************************************C ******437 ;appended to it right after the last data bit 493 ;Puncture and combine bits of adderl and adder2438 ;0X30013^-^0X30025 DATA^CRC^@ 30026 494439 495440 496 PUNCTURE AND COMBINE:441 ******,*********************************************************** 497 EDP ElUAL498 LOT @RATE, R7442 ;Convolutional encoding of data information @VIRGIN_DATA. 499 LDP CODES443 ;Resulting encoded data is stored at: 500 CMPI 1,R7444 ;^P1 encoded data ---> DATABUFP1 501 BZ RATE1445 ;^P2 encoded data ---> DATABUFP2 502 CMPI 2,^R7446 503 BZ RATE75447 504 CMPI 3,^R7448 ;need to get number of 32 bit words to convolve and also add 505 BZ RATESK 506 CMPI 0,^R7449 ;^(constraint length)^bits to 507 BZ ERROR450 1> rounded up word count, and 508451 2> bit count of encoded data 509 ;data bits of adder 1 are @DATABUFP1452 510 ;data bits of adder 2 are 9DATABUFP2453 LDP CODES 511454 LOT @VIRGIN DATA, ARO 512 RATE1:455 LDI @DATABUET1, AR1 513 LDP DUAL456 LOT @DATABUFP2, AR2 514 LOT @CODE, R7457 LDP DUAL 515 ldp CODES458 LOT @RATE,^R7 516 CMPI 1,^R7459 LOP CODES 517 BZ CODE1460 CMPI 1,R7 518 CMPI 2,^R7461 LDIZ 28, R4^ ;26 DATA WORDS + BLANK CRC 519 BZ CODE2462 CMPI 2,^R7 520 BZ ERROR463 LDIZ 21, R4 ;19 DATA WORDS + BLANK CRC 521464 CMPI 3,^R7 522 RATE75:465 LDIZ 15, R4 ;12 DATA WORDS + BLANK CRC 523 LDP DUAL466 524 LOT @CODE, R7467 PUSH R4^ ;SIZE 525 ldp CODES468 PUSH AR2 ;MESGP2 526 CMPI 1,^R7469 PUSH AR1 ;MESGP1 527 BZ CODE75 CPC_ONE470 PUSH ARO^ ;MESG 528 CMPI 2,^117471 529 BZ CODE75_CPC_TWO472 CALL _conv 530 BZ ERROR473 531 RATES:474 SUBI 4,^SP 532 LDP CODES475 ;End of convolutional encoding of data 533476 ;*********************************************************** 534 LOT 9DATABUFP1, ARO**** 535 LOT @DATABUFP2, AR1477 ; Construct frame 91 and P2 and place at: 536 BR RATE_HALF478 ;^frame P1 ---> FRAMEBUFP1 537479 ;^frame P2 ---> FRAMEBUFP2 538480 ; This procedure is made a bit tedious because if the header 539481 ;^length is not a multiple of 32 then we must shift and OR 540482 ; all the data bits so that they can be appended directly 541 PUSH_AND_CALL:483 ;^after the header bits!! 542 PUSH RO^ ; Routine used by all rates to push484 543 PUSH AR1 ; parameters and call puncture modul485 eOct 6 1993 14:48:30^XMITADAP.ASM Page 11 Oct 6 1993 14:48:30^XMITADAP.ASM Page 12544 PUSH AR3 601 LDI 672,^RO545 PUSH R1 602 LDI 3, R1 ;Puncture Adder2 by 3/4546 603 LDI @DATABUFP4, AR3547 CALL _puncture 604 LDI @DATABUFP2, AR1548 605 CALL PUSH AND_CALL549 SUBI 4,^SP 606 BR COMBINE550 RETS 607551 608 RATE_HALF:552 CODEl: 609 LOT 448,^RI ;14 WORDS * 32 BITS553 LDI^896,^RO 610 LDI @FRAMEBUFP2, AR3554 LOT^4,^R1 ; Puncture Adderl bits by 1/ 611 PUSH RO2 612 PUSH AR3555 LDI 8DATABUFP1, AR1 613 PUSH AR1556 LET @DATABUFP3, AR3 614 PUSH ARO557 CALL PUSH_AND_CALL 615 CALL^combineheader558 616 SUSI IT, ^SP559 LDI^896,^RO 617 BR CONSTRUCT560 LDI^5,^R1 ;Puncture Adder2 bits by 1/2 618 COMBINE1:561 LDI @DATABUFP4, AR3 619 LDI @DATABUFP3, ARO562 LDI @DATABUFP2, AR1 620 LDI @DATABUFP4, AR1563 CALL PUSH AND_CALL 621564 BR COMBINE1 622 LDP CODES565 CODE2: 623566 LDI^896,^RI 624567 LDI 6,^R1 ; Puncture Adderl bits by 1/ 625 LDI @FRAMEBUFP2, AR32 626 LDI 896,^RD ;21 WORDS * 32 BITS568 LDI @DATABUFP1, AR1 627 PUSH RI569 LDI @DATABUFP3, AR3 628 PUSH AR3570 CALL PUSH_AND_CALL 629 PUSH AR1571 630 PUSH ARO572 LDI^896,^RI 631 CALL^combineheader573 LDI 7,^R1 ;Puncture Adder2 bits by 1/2 632 SUET 7i,^SP574 LDI @DATABUFP4, AR3 633 BR CONSTRUCT575 LDI @DATABUFP2, AR1 634576 CALL PUSH AND_CALL 635577 BR COMBINE]. 636 COMBINE:578 637 LDI @DATABUFP3, ARO579 638 LDI @DATABUFP4, AR1580 CODE75_CPC ONE: 639581 LDY 672,^RO 640 LDP CODES582 LDI^0,^R1 ; Puncture Adderl bits by 3/ 6414 642583 LDI 8DATABUFP1, AR1 643 LDI @FRAMEBUFP2, AR3584 LDI @DATABUFP3, AR3 644 LDI 672,^RI ;21 WORDS . 32 BITS585 CALL PUSH_AND_CALL 645 PUSH RO586 646 PUSH AR3587 LDI^672,^RO 647 PUSH AR1588 LDI^1,^R1 ;Puncture Adder2 bits by 3/4 648 PUSH ARO589 LDI 8DATABUFP4, AR3 649 CALL^combineheader590 LDI @DATABUFP2, AR1 650 SUBI Z,^SP591 CALL PUSH AND_CALL 651592 BR COMBINE 652 ;End of header construction593 653594 CODE75_CPC TWO: 654 CONSTRUCT:595 LDT 672,^RI 655 LDP CODES596 LDI^2,^R1 ;Puncture Adderl by 3/4 656 LOT @FRAMEBUFP1, AR1597 LDI @DATABUFP1, AR1 657 ADDI 4,AR1598 LOT 8DATABUFP3, AR3 658 LDI 8FRAMEBUFP2, ARO599 CALL PUSH_AND_CALL 659 ldp DUAL611 660 LDI 27,^RI ;copy possible 27 words if rOct 6 1993 14:48:30^XMITADAP.ASM^Page 13 Oct 6 1993 14:48:30^XMITADAP.ASM Page 14ate^1/2 715661 LDI^*ARO++,^R1 716662 RPTS RO 717 LDP DUAL663 718 LDI 0,^R6664 LET^*ARO++,^R1 719 STI R6, @CONTROL_WORD665 IISTI^R1,^*AR1++ 720666 721 LDP CODES667 722 LDI @FRAMEBUFP1, R6668 723 LDI R6,^R7669 BR TRANY 724 ADDI 40H, R7670 725 CALL CLEAR671 ;End of constructing Frames P1 and P2 726 LDI @DATABUFP3, R6672 ;.***************************************************************** 727 LDI R6,^R7673674•,^Now we must save the frame P2 for future possible•, retransmission and interleave frame P1 which will728729730AUDI 200h,^R7CALL CLEAR675 also be save and then queued for transmission. 731 BR START_OF_MAIN_ROUTINE676 732677 Save frame P2^---> @PACKETxHARDP2 733678 Interleave P1 and save ---> @PACKETxHARDP1 734679 735 TRANY:680 736 LDI 31,^RO681 737 LDP CODES682 nop 738 LDI @FRAMEBUFP1, ARO683684nopnop 739 3LDI @PACKET3HARDP1, ARC ;COPY FRAME TO SLOT685 ldi BLOCKS,^r2 740 LDI *ARO++,^R1686 741 RPTS RO687 INTERLEAVE MORE: 742 LDI *ARO++,^R1688 PUSH R2 743 IISTI R1,^*AR1++689 PUSH AR2 744690 PUSH ARO 745 ;Now set up for transmission691 746692 CALL _interleaver 747 LDI @PACKET3HARDP1, ARO693 POP ARO 748 SUBI 1, ARO694 POP AR2 749 LDI ARO, AR3695 POP R2 750 ADDI 33, AR3696 751 LDI ARO,^R7697 752 LDI AR3,^R6698 ;ADDI 4, AR2^ ;not required,^subroutine au 753 CALL QUEUEtomatically 754699 ADDI DEINT_ROW, ARO^ ;increments AR2 cont 755ants 756 LDP DUAL700 SUBI^1,^R2 757 LDI^0,^R6701 BNZ INTERLEAVE_MORE 758 STI R6, @CONTROL_WORD702 759703 ;Completed interleaving of frame P1 and saving of frame P1 & 760 LDP CODESP2 761 LDI @FRAMEBUFP1, R6704 :*************************************************************** 762 LDI R6,^R7763 ADDI 40H,^R7705 764 CALL CLEAR706 ;Now set up for transmission 765 LDI @DATABUFP3, R6707 766 LDI R6, R7708 LDI @PACKET3HARDP1, ARO 767 AUDI 200h, R7709 SUBI 1,^ARO 768 CALL CLEAR710 LDI ARO, AR3 769711 AUDI 34,^AR3 770 BR START_OF_MAIN_ROUTINE712 LDI ARO, R7 771713 LDI AR3, R6 772714 CALL QUEUE 773Oct 6 1993 14:48:30^XMITADAP.ASM^Page 15 Oct 6 1993 14:48:30^XMITADAP.ASM^Page 16774 ,******************************************************************* 827****** 828 CALL _interleaver775 829 POP ARO776 ; The purpose of this option is to encode the data using a rat 830 POP AR2831 POP R2777 ; 1/2 convolutional encoder and the two polynomials defined in 832778 ; VARS.ASM. The encoded data is placed in a frame and sent thr 833ough 834 ;ADDI 4, AR2^ ;not required,^subroutine au779 ; the channel. tomatically780 ;terbiMain purpose for this option is to test perfomance of the Vi 835 AUDI DEINT_ROW, ARO^ ;increments AR2 contents781 Decoder in the RCVRCPC.ASM module. 836 SUBI 1,^R2782 837 BNZ INTERLEAVE_MORE2783 OPTION2: 838784 LDP CODES 839 ;frame is now interleaved and placed into the slot 30123785 LDI @VIRGIN_HEADER, ARO^ ;address of data to 840 ;and it also has a flag appended to itconvolve 841786 LDI @FRAMEBUFP1, AR1 ;Pl bit buffer 842 ldi @PACKET3HARDP1, ar2787 LDI @FRAMEBUFP2, AR2 ;P2 bit buffer 843 SUBI 1, AR2^ ;AR2 points to flag @ start788 LDI 16,^HO ;# of 32 bit words t of frameo encode 844 ldi ar2,^ar0789 845 ADDI 34, ARO790 PUSH HO ;SIZE 846 LDI AR2,^R7 ;start address of frame791 PUSH AR2^ ;MESGP2 847 LDI ARO,^R6 ;end address + 2792 PUSH AR1 ;MESGP1 848 CALL QUEUE ;transmit frame793 PUSH ARO ;MESG 849794 850 LOP CODES ;clear memory 8$30000 to795 CALL _conv^ ;convolve data 851 LDI @DUALSTART, R6^;$300bf and branch back for796 SUBI 4,^SP next797 852 LDI @DUALMEM, R7 ;option798 ;Now the P1 bits and P2 bits must be combined 853 CALL CLEAR799 854 BR START_OF_MAIN_ROUTINE800 LDI 512,^RO 855801 LDI @FRAMEBUFP1, ARO 856802 LDI @FRAMEBUFP2, AR1 857803 LDI @DATABUFP1, AR3 858804 859805 PUSH HO^ ;# BITS 860806 PUSH AR3 ;address of convolved data 861 OPTION 3 - Take 992 random data bits delivered @VIRGIN_HEADE807 PUSH AR1 ;Pl bits808 PUSH ARO^ ;P2 bits 862 and look at control word in order to determine809 863 which P1 frame slot to place data in.^Then trans810 CALL _combineheader mit811 SUBI 4,^SP 864 random UNCODED data with a flag.812 865813 866 The purpose of this option is to allow the user t814 ;Now set up to interleave & transmit frame through channel815 867 obtain the Bit Error Rate (with a PC host Program816 LDI @PACKET3HARDP1, AR2^;slot address of frame817 LDI @DATABUFP1, ARO^;random data start address 868 of the modulation scheme being used.^This option818 869 takes the random data, adds a flag and just819 870 transmits the 1024 bit frame through the channel.820 871821 ldi BLOCKS,^r2 872 OPTION3:822 873823 INTERLEAVE_MORE2: 874 LDP CODES824 PUSH R2 875 LDI @PACKET3HARDP1, AR2^;slot address of frame825 PUSH AR2 876 LDI @VIRGIN_HEADER, ARO ;random data start address826 PUSH ARO 877Oct 6 1993 14:48:30^XMITADAP.ASM^Page 17 Oct 6 1993 14:48:30^XMITADAP.ASM^Page 18878879 932 LDI @Q_END, AR1^ ;QUEUE880 ldi BLOCKS,^r2 933 STI R6,^*+AR1(IRO)881 934882883INTERLEAVE_MORE3:PUSH R2 935 LDI^IRO,^RO ;Adjust offset value which is used884885PUSH AR2PUSH ARO 936 ADDI 1, RO ;to make the QUEUE a circula886 937 CMPI 8,^RU ;buffer887 CALL _interleaver 938 LDIZ 0,^RO888 POP ARO 939 STI RO,^@Q_OFFSET889 POP AR2 940890891POP R2 941 LDI @TRANSMISSION, RO^;Check if busy transmittingif not892893 ;ADDI 4, AR2^ ;not required,^subroutine au942943BZ BEGIN_TRANS^ ;begin transmissionRETStomatically 944894 ADDI DEINT_ROW, ARO^ ;increments AR2 contents 945895896SUSI^1,^R2BNZ INTERLEAVE_MORE3 946 This section of code is used to begin transmission of a fram897898 ;frame is now interleaved and placed into the slot 30123 947948 and initialize various parameters for transmission interruptroutine.899900901;and it also has a flag appended to itldi @PACKET3HARDP1,^ar2949950 It is used for the first frame transmission as well as anysubsequent frame transmission when the interrupt has disable902 SUBI 1, AR2^ ;AR2 points to flag @ start 951 its^self.of frame 952903 ldi ar2,^ar0 953 BEGIN_TRANS.904905906ADDI 34, AROLDI AR2,^R7 ;start address of frameLDI ARO,^R6 ;end address + 2954955956Set up timer 1 which will be used to trigger interrupt 1every 6.6 mircoseconds.^55/.12 = 6.6mircosecondsLDP CODES907 CALL QUEUE ;transmit frame 957 LDI^@TIMECTL2, AR1908 958 LDI @TIMECTL1, ARO909 LOP CODES ;clear memory @$30000 to 959 LDI^@RSTCTRL, RO910 LDI @DUALSTART, R6^;$300bf and branch back for 960 STI RO,^*ARO911nextLDI @DUALMEM,^R7 ;option961 STI^RO,^*AR1 ;Reset timers 0,^and1912 CALL CLEAR 962913914BR START_OF_MAIN_ROUTINE 963 LDI @PERIOD, AR1 ;Set timer 1 to trigger915 964 LDI @COUNT,^RO ;every 6.6microseconds916 This section of code places the start and end address of a 965 STI RO,^*AR1917 frame to be transmitted in the queue. 966 LDI @SETCTRL, RO918 Note: before calling this routine ensure that 967 STI RO,^*ARO919 R6^end address of frame + 2 locations 968 LDP ONCHIP920 R7 = start address of frame 969 LDI OFFFFH, RE921 970 LDI @Q_START,ARO922 QUEUE: 971 STI RO,^@TRANSMISSION^;set transmission flag to bu923 sy924 LDP ONCHIP 972925 LDI @Q_START, ARO 973 LDI @Q_OFF_TRANS,^IRO926927KEEPCOING:LDI @Q_OFFSET,^IRO 974 LDI *+ARO(IRO), AR3 ;AR3 = address of frame star928 LDI *+ARO(IRO),^R1 ;QUEUE is full so keep loopi 975ng until 976 KEEP_TRANS:929 BNZ KEEPGOING ;this slot is available 977930 978931 STI R7,^*+ARO(IRO)^;Place start and end address 979Oct 6 1993 14:48:30^XMITADAP.ASM^Page 19 Oct 6 1993 14:48:30^XMITADAP.ASM^Page 20980 ;LDI @SINEO,^RO 1036 ERROR:981 LDI 0,^RO 1037 LDP DUAL982 STI RD.^@SINE_POINTER^;sine_pointer = 809c08 1038 STI R7, @ERROR_NUM983 STI RD.^@COSINE_POINTER ;cosine_pointer^809c08 1039 DEAD BR DEAD984 LDI 8,^RD 1040985 STI RO,^@POINT_COUNT^;point_count = 8 1041986 ldi^16,^r0 1042987 sti rO,^@DIBIT_COUNT 1043 , * *************** ** *************** ** *************** * ****************988 LDI *AR3++,^RD ;place first data in DATA_WO ****RD 1044 This interrupt 1 is responsible for the actual transmission989 STI RO, @DATA_WORD of990 1045 the frame.^It consists of 30 instructions^(if it does not j991 LDI AR3,^RD ump992 STI RO,^@CURRENT_ADDRESS^;save incremented pointer 1046 to get a NEWDIBIT).993 LDI @Q_END, ARO 1047 30 X 6Ons = 1800ns994 LDI^*+ARO(IRO),^RD 1048995 STI RO, @END_ADDRESS^;save end address 1049 Interrupt 1 occurs every^55^(count value)/.12 = 6.6 microse996997 ldi^0,^r0 1050 6.6microsec/60ns = 110 instructions998 sti^rO,^*+ar0(ir0) 1051999 ldi @Q_START,^ar0 1052 110 - 30 = 80 instruction between interrupts1000 sti^rO,^*+ar0(ir0) 10531001 1054 Note: NEWDIBIT is called after 32 points have been output fo10021003 LDI IRO,^RD ;Adjust offset used to make 1055 each symbol.^NEWDIBIT is very time consuming and woulQUEUE1004 AUDI 1,^RD ;a circular buffer 1056 practically take the entire 6.6 microseconds.1005 CMPI 8,^RO 10571006 LDIZ 0,^RI 10581007 STI RI, @Q_OFF_TRANS 1059 INT_TRANSMISSION:1008 10601009 LDI @GET_NEWFRAME_FLAG, RD 1061 PUSH ST1010 BZ ENABLE_RET 1062 XOR 2000H,^ST1011 LDI^0,^RD 1063 PUSH RD ;save registers before using1012 STI RI, @GET_NEWFRAME_FLAG them1013 RETS 1064 PUSH R1 ;in interrupt routine1014 1065 PUSH R21015 ENABLE_RET: 1066 PUSH ARO1016 OR 2H,^IN ;ENABLE INTERRUPT 1 1067 PUSH AR11017 OR 2000H, ST^ ;ENABLE GLOBAL INTERRUPTS 1068 PUSH AR31018 RETS 10691019 1070 push ir01020 1071 PUSH DP1021 10721073 LDP ONCHIP1022 ;This section clears memory chunks specified by ARO --› AR1 1074 LDI @IBIT_POINTER, ARO^;ar0 = sine table pointer1023 1075 LDI @QBIT_POINTER, AR1 ;arl = cosine table pointer1024 CLEAR: 10761025 SUBI R6,^R7 1077 LDI @SINE_POINTER,^IRO1026 LOIN 1,^R7 10781027 BN ERROR 10791028 LDI NULL,^RD 1080 LDI *+ARO(IRO),^R1^;output value to channel and upda1029 LDI R6,^ARO te1030 RPTS R7 1081 LDI *+AR1(IRO),^R2 ;table pointers respectively1031 STI RD.^*ARO++ 1082 STI R1, OADCHANA1032 RETS 1083 STI R2, @ADCHANB1033 ;******************************************************************* 1084**** 1085 ldi^@SERIAL°, AR31034 ;This section is used for debugging various errors 1086 LDI 2H,^R21035 1087 STI^R2,^*AR3Oct 6 1993 14:48:30^XMITADAP.ASM^Page 21 Oct 6 1993 14:48:30^XMITADAP.ASM^Page 221088 1145 ;1diz^0,^r01089 LDI @POINT_COUNT, RD ;check if 32 points per symb 1146 ;sti rO,^@COSINE_POINTERol 1147 ;ldi^16,^r01090 ;SUBI^1,^RD ;has been output to channel 1148 ;sti rO,^@DIBIT_COUNT1091 CMPI 4,^RD 11491092 1150 ;ldiz @FLAG,^r0 ;continuous flag output1093 1151 ;sti rO, @DATA_WORD1094 BNZ NOPULSE 1152 ;LDI^16,^RD1095 PULSE_RCVR: 1153 ;STI RI,^@DIBIT_COUNT1096 11541097 ;if 16th point then output 1155 BZ NEWWORD ;frame output1098 LDI^6H,^R2 ;a pulse on the serial 0 por 1156t 1157 NEXT:^LDI @SINE_POINTER, RI^ ;use DIBIT to dec1099 STI^R2,^*AR3 ide how much1100 NOPULSE: 1158 MPYI 8,^R21101 1159 ADDI R2,^RD1102 SUBI 1,^RI 1160 LDI RI,^IRO1103 STI RO,^@POINT_COUNT 1161 LDI @TABLE ENC, ARO1104 BZ NEWDIBIT ;if so get another dibit 1162 LDI *+ARO(TRO),^R11105 1163 STI R1,^@SINE_POINTER1106 FINISH: 11641107 ;STI ARO,^@SINE POINTER ;save new pointers 11651108 ;STI AR1,^@COSIRE_POINTER 11661109 11671110 FINISH2: 11681111 POP DP ;restore registers before re 1169turning 11701112 pop ir0 1171 BR FINISH21113 POP AR3 ;from interrupt routine 11721114 POP AR1 1173 NEWWORD:1115 POP ARO 1174 LDI 16,^RD1116 POP R2 1175 STI RO,^@DIBIT_COUNT1117 POP R1 11761118 POP RI 1177 LDI @CURRENT_ADDRESS, AR3^;get pointer to data to tran1119 POP ST emit1120 OR 2000h,^ST 1178 LDI *AR3++,^RD ;get data pointed to1121 RETI 1179 STI AR3, @CURRENT ADDRESS^;save incremented pointer1122 1180 STI ED, @DATA_WORE^;save data1123 1181 CMPI @END_ADDRESS, AR3 ;check if end of frame reach1124 NEWDIBIT: ad1125 LDI @GET_NEWFRAME_FLAG, RD ;if newframe flag set 1182 BZ SETFLAG1126 BN NEWFRAME ;get newframe 1183 OR NEXT^ ;if not do NEXT1127 LDI^8,^RI 11841128 LDI^3,^R1 ; R1 = 3 mask for 2 lsb's 1185 SETFLAG:1129 STI RI,^@POINT_COUNT ;initialize POINT_COUNT . 32 1186 LDI -1,^RD1130 LDI @DATA WORD, RI ; RO = DATA_WORD 1187 STI RI, @GET_NEWFRAME_FLAG1131 AND3 RI,^17d,^R2 ; R2 = DATA_WORD & 3 1188 BR NEXT1132 LSH -2,^RI ;shift DATA_WORD by 2 11891133 STI RI,^@DATA WORD 1190 NEWFRAME:1134 LDI @DIBIT_COTINT,^RI 1191 ;MIGHT WANT TO ADD TIME DELAY BETWEEN FRAMES1135 SUBI 1,^RI 1192 LDI @Q_START, ARO1136 STI RO,^@DIBIT_COUNT 1193 LDI @Q_OFF_TRANS,^IRO1137 1194 LDI *+ARO(IRO),^AR31138 hnz NEXT 1195 LDI AR3,^RI :RI will set ST flag1139 1196 BZ STOP TRANS1140 ;ldi @COSINE_POINTER,^ar0 ;random bit stream output 1197 CALL KEEPTRANS1141 ;ldi^*ar0++,^r0 1198 BR FINISH-i1142 ;sti rO,^@DATA_WORD 11991143 ;ldi^ar0,^r0 1200 STOP_TRANS:1144 ;cmpi^Offffh,^r0 1201 LDI 0,^RIOct 6 1993 14:48:30^XMITADAP.ASM^Page 23120212031204^STI RO, @TRANSMISSION1205 STI RO, @GET_NEWFRAME_FLAG12061207^POP DP^ ;restore registers before returning1208^pop ir01209 POP AR3^ ;from interrupt routine1210 POP ARO1211^POP ARO1212 POP R21213 POP R11214^POP RO1215 POP ST1216 XOR 2000H, ST1217^RETI12181219 UPDATE1:1220^LDI *ARO--(DELTA)%, RO^;output value to channel andupdate1221 LDI *AR1++(DELTA)%, R1^;table pointers respectively12221223^; SUBI DELTA, ARO1224 ; ADDI DELTA, AR11225^; BR UPDATE21226^;**********************************************************************1227 ;^All other interrupts simply return12281229 NO:^RETI1230123112321233 .endOct 6 1993 14:39:55^RCVRADAP.ASM^Page 1 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 21 51 .word 9h ;polynomiall =11001=1+x^3+x^42 RCVRADAP.asm^V1.00^Dec 92 52 .word 7h ;polynomial2 =10111.1+x+x^2+3 V1.01 Apr 93 x^44 V2.00^Sept 93 53 .word 9665 ;CRC-CCITT5 ; 54 .word 374732215 ;CRC-326 ,•^The purpose of this code is to set up the dsp board environm 55 .word B1492AAh ;flag for packetent, 56 .word ;Q_START --> 809c067 ,^variables,^and memory.^This code is used as the main interf 57 .word ;Q_START(1)ace 58 .word ;Q_START(2)8 ,^between the PC and the dsp board. It places all necessary 59 .word ;Q_START(3)9 ; assembler and C routines in memory and then awaits in a simp 60 .word ;Q_START(4)le 61 .word ;Q_START(5)1011,^loop, where the ARQ shell can poke the appropriate info into,• DSP memory and then run the appropriate routine.6263.word.word;Q_START(6);Q_START(7)12 64 .word ;Q_END --> 809c0e13 65 .word ;Q_END(1)14 66 .word ;Q_END(2)15 67 .word ;Q_END(3)16 68 .word ;Q_END(4)17 .include VARSRCVR.ASM 69 .word ;Q_END(5)18 .global^.bss 70 .word ;Q_END(6)19 .global cinit^ ;init table^(from li 71 .word ;Q_END(7)nker) 72 .word 09c06h ;Q_START --->809c1620 .global _c_int00 ;starting address^(C 73 .word 09c0Eh ;Q_END^>809c17standard) 74 .word 08042H ;DIGITAL PORT ADDRESS --->8021 .global _interleaver 9C1822 .global _puncture 75 TAB_ENC .WORD ;pi/4 QPSK encoding table23 .global _combineheader 76 .WORD ;--->^809c1924 .global^_conv^ ;the convolutional en 77 .WORDcoding 78 .WORD25 ;routine 79 .WORD26 .global^_polydiv^;polnomial division r 80 .WORDoutine 81 .WORD27 82 .WORD28 83 .WORD29 84 .WORD30 .sect^".init"^ ;interrupt section 85 .WORD31 RESET^.word^_c_int00 ;RESET -> start addr 86 .WORDess 87 .WORD32 INTO .word^NO ;all others to dummy 88 .WORDreti 89 .WORD33 INT1^.word^RCV^ ;except the sync int 90 .WORD34 INT2 .word^NO 91 .WORD35 INT3 .word^NO 92 .WORD36 XINTO^.word^NO 93 .WORD37 RINTO .word^NO 94 .WORD38 XINT1 .word^NO 95 .WORD39 RINT1^.word^NO 96 .WORD40 TINTO .word^NO 97 .WORD41 TINT1 .word^NO 98 .WORD42 DINT^.word^NO 99 .WORD43 100 .WORD44 101 .WORD45 102 .WORD46 Data section to initially be loaded at $30000h but then 103 .WORD47 moved to $809c00^(on chip ram). 104 .WORD48 105 .WORD49 .data 106 .WORD50 .word^5 ;constraint length 107 ICHAN .WORD AA50000H ;IBIT CHAN^1 voltaddressLDI^@STACK_ADDR, SP^;load the address into SPLDI^SP, FP^ ;and into FP toonit^LDI^@PRIMCTRL, ARO^;Hardware specific iLDI^INITIAL, RISTI RI, *AROLDI^@EXPCTRL, AROLDI NULL, RISTI^RI, *ARO;LDI @SERIAL°, ARO^;SET DIGITAL OUTPUTTO 0;LDI^2H, RI;STI RI, *AROThis portion of code is absolutely necessary when mixing Cmodules with assembly language. It ensures that thevariables defined in the C module are properly initialized.address^LDP^CODES^ ;get page of storedLDI^@INIT_ADDR, ARO^;get address of inittablesmit^CMPI^-1, ARO^ ;if RAM model, skipBEQ^init_doneLDI *ARO++, R1^;get first countBZD^init_done ;if 0, nothing to doLDI *ARO++, AR1 ;get dest addressLDI^*ARO++, RI^;get first wordSUBI^1, R1^ ;count - 1do_init:^RPTS^R1 ;block copySTI RI, *AR1++II^LDI^*ARO++, RILDI RI, R1^ ;move next count into R1BNZD^do_init ;if there is more, repeatLDI^*ARO++, AR1^;get next dest addressLDI^*ARO++, RI ;get next first wordSUBI^1, R1^ ;count - 1This code block copies all of the variables placed at $30000and moves them to the on chip memory area at $809c00 - $80a000init_done:LDI^@DUALSTART, AROLOT @RAM1, AR1LDI^*ARO++, RI ;since parallel instruction;coming up must initialize ROct 6 1993 14:39:55 RCVRADAP.ASM^Page 3 Oct 6 1993 14:39:55 RCVRADAP.ASM^Page 4108 .WORD^1E280000H^;0.707109 .WORD^0 ;0.00 159110 .WORD^-1E280000H^;-0.707111 .WORD^-2AA50000H ;-1.00 160112 .WORD^-1E2800001-1^;-0.707 161113 .WORD^0 162114 .WORD^1E280000H115 QCHAN .WORD^0 163116 .WORD^1E2800001-1 164117 .WORD^2AA50000H 165118 .WORD^1E2800001-1 166119 .WORD^0 167120 .WORD^-1E280000H 168121 .WORD^-2AA50000H122 .WORD^-1E280000H 169123 .WORD^809C19H^;TABENC ---> 170124 .WORD^809C39H ;IBIT CHAN 171125 .WORD^809C41H ;QBIT CHAN^---> 172126127 173128 174129 ;444********************************************44******4444.4*****4444*** 176130 ;^Variables to be used for initialization. 177131132 STACK .usect^u.stacku,STACK_SIZE 178133134 .text 179135 STACK_ADDR .word^STACK^ ;address of stack136 INIT_ADDR .word^cinit ;address of mit tab 180les 181137 PRIMCTRL .word^00808064h^ ;primary bus control 182address 183138 EXPCTRL .word^00808060h ;expansion bus contr 184ol address 185139 TIMECTL1 .word^808030H^ ;timer 1 control 186140 SERIAL° .word^808042h ;FSX/DX/CLKX port co 187ntrol 188141 TIMECTL2 .word^808020h^ ;timer 2 control 189142 RSTCTRLers.word^601h ;reset value for tim 190143 PERIOD .word^808038h^ ;timer 1 period 191144 COUNT .word^55 ;period value for timet 1 192145 SETCTRL .word^6c1h^ ;set value for timers 193146 RAM1 .word^809c0Oh ;on chip ram area 194147 DUALSTART .word^30000h^ ;temp variables 195148 DUALEND .word^33300h ;change for 64k 196149 DUALMEM .word^3008Fh150 REALSTART .word^31000H 197151 REALEND .word^32fffH152 ;.*************444444********************444444*****************444** * *153 The following code sets up the stack pointer and then 199154 initializes the DSP hardware as outlined in the Technical 200155 ;^Reference Manual. 201156 202157 _c_int00: 203158 LDP^CODES^ ;get page of stored 204Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 5 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 60 260 LDI ARO, R1 ;& increment flag pointer to205 next206 RPTS^DATALENGTH 261 ADDI 1,^R1 ;position in table.^If BOTT207 LDI *ARO++,^RI ON of208 IISTI^RI,^*AR1++ 262 CMPI @TABLE_BOTTOM, R1^;table reached reset pointer209 263 BNZ NORESET ;to TOP210 264 LDI @TABLE_TOP, R1211 265 NORESET:266 STI R1, @CURRENT FLAG212 267 ;At this point RIT) contains address of real data value of the213 LDI @DUALSTART, R6 ;clear DUAL memory 268 ;very last dibit of FLAG214 LDI @DUALEND, R7 ;$30000^-->$33300 269215 CALL CLEAR 270 SUBI 17,^RO ;point to first dibit of FL216 AG217 ldf^0,^r0 271218 ldi @RCVD_SIGNAL_ENERGY,ar0 272 cmpi @CIRC BOTTOM, r0219 stf^rO,^*ar0220 273 bge NO _ADJUST274 addi 0Iffh, ^r0221 LDI @CPC1I,^R6 275 ;This next section of code is used to check the validity of222 LDI @REALEND, R7 the223 CALL CLEARFLOAT 276 ;FLAG found.^That is,^it checks if the flag found has occur224 red225 ldi^@CPC2Q,^r6 277 ;in a frame of data thus resulting in a false flag.226 ldi^r6,^r7 278227 addi 300h,^r7 279 NO_ADJUST:228 call CLEARFLOAT 280 LDI @START_FRAME, R1^;start add of last frame dec229 oded230 281 LDI @STOP_FRAME, R2 ;stop add of last frame deco231 LDI OFFFH,^BK ;set circular length of inpu dadt 282 LDI RI,^R3 ;R3 . flag address232 ;buffers 283233 OR 2H,^IE ;enable interrupt 1 284 CMPI 121,^R2 ;STOP > START?234 OR 2000H,^ST ;enable global interrupts 285 BP NO CIRC_ADJUST^;yes, no adjustment required235 286 ldi r,^r4236 BOSS: 287 ADDI 100061,^R2 ;NO,^adjust^for circular237 288 cmpi r4,^r3238 ldp DUAL 289 bp NO CIRC_ADJUST239 ldi @STROBE_RCVR,^r0 290 ADDI 1000H, R3 ;buffer by adding circular240 bnz GOAHEAD 291 ;length241 hr BOSS 292242 293 NO_CIRC_ADJUST:243 STROBETHEHOST: 294 ;IF ( FLAG ADD > START FRAME^&^FLAG_ADD < STOP_FRAME )244 ldp DUAL 295 ,^FLAG IS INVALIB245 ldi^0,^r0 296 ;OTHERWISE PROCESS DATA246 sti rO,^@STROBE_RCVR 297247 ldi^255,^r0 298 CMPI R1, R3^ ;FLAG - START248 sti al,^@STROBE_HOST 299 BLE VALID249 hr BOSS 300 CMPI R2,^R3 ;FLAG - STOP250 301 BGE VALID251 302 BR BOSS252 GOAHEAD: 303253 LDP CODES 304254 LDI @CURRENT_FLAG, ARO ;get latest found flag point 305 •er 306 ; A this point we have a valid flag and will now select255 307 ; which mode the user has chosen for the RCVR.256 BACKUP:^LDI *ARO,^RO 308257 BZ STROBETHEHOST^;check if flag found 309 VALID:258 LDI 0,^R1 310 LDP DUAL259 STI R1,^*ARO ;if found reset pointer to z 311 LDI @MENU OPTION, R1ero 312 AND 3h, RT.Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 7 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 8313314CMPI^1,^R1BZ MODE1 369 CALL QPSK1 ;decode chunk of lengthR1315316CMPI 2,^R1BZ MODE2 370371 ;and place starting at AR2317 CMPI 3,^R1 372318 HZ MODE3 373319 BR VALID 374320 375321 376322 ;******************************************************************* 377 ;Refresh start and stop frame pointers used in flag validation323 ;^MODE 1 378 LDI @CURRENT_START, RU324 This mode makes the rcvr simply hard decode the data rcvd, 379 STI RU,^@START_FRAME325 place it at slot P1 0,^and send an ACK. 380326 No decoding is done since,^it is assumed that no coding 381 ADDI 21014,^RU327 was performed.^This mode allows the ser to check the channe 382 LDI @CIRC_TOP, R1383 CMPI R1,^RU328 conditions of the system with no coding. 384 BLT NO_SUB1329 385 SUBI^100014,^RU330 Requires: 386331 RD^real data flag start 387 NO_SUB1:STI RI, @STOP_FRAME332 Modifies: 388333334RU,^R1,^R2,^R3,^R4,^R5,^R6,^R7ARO,^AR1,^AR2 389390LOT 1, R1^;send an ACK° to HOST PROGRAMLDP DUAL335 Returns: 391 STI R1,^@ACK°336 Nothing 392 LDP CODES337 393 BR BOSS338 MODEl: 394339 LDP DUAL^ ;insure ACKO is clear 395340 LDI 0,^R7341 STI R7,^@ACK° 396342 LDP CODES 397 ; MODE VITERBI DECODE CHANNEL343344LDI @FLAGOP1,^R6 ;clear slot 0 area of P1LDI @PACKET1HARDP1,^R7 398 This mode assumes that the frame rcvd contains a flag with 496 bits345346CALL CLEAR 399 convolved with a rate 1/2 code given by polynomials in VARS.ASM347 sti rO,^@CURRENT_START 400 and constraint length K=5.348 401 The frame^32 bits --> flag349350 402403 992 bits^convolved data351 LDI 16,^R1 ;hard decode flag 404 1024 bit frame352 LDI @FLAGOP1, AR2^;slot to store decoded data 405353 CALL HARDDECODE_CHUNK^;decode chunk of length^R1 406 MODE2:354355 ;and place starting at AR2 407408LDP DUAL^ ;insure ACED is clearLDI 0,^R7356 LDI @CURRENT_START, RO 409 STI R7,^@ACK°357 ADDI 10H,^RU ;transform DQPSK data to QPS 410 LDP CODES358K datacmpi @CIRC_TOP,^r0 411412LDI @FLAGOP1,^R6 ;clear slot 0 area of P1LDI @PACKET1HARDP1, R7359 BLT NO_ADJ1 413 CALL CLEAR360 SUBI OFFFh,^RI 414361 NO_ADJ1: 415 sti rO, @CURRENT_START362 CALL DQPSK_DEINT 416363 417364 LDI @BUFP1, ARO^ ;Zk value 418365 LDI @BUFP2, AR1 ;Wk value 419 LDI 16,^R1 ;hard decode flag366 420 LDI @FLAGOP1, AR2^;slot to store decoded data367 LDI 512,^R1 ;hard decode flag 421 CALL HARDDECODE_CHUNK^;decode chunk of length = R1368 LDI @PACKETOHARDP1, AR2^;slot to store decodeddata 422423 ;and place starting at AR2Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 9 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 10424 481425 LDI @CURRENT_START, RD 482 LOT 16,^R1 ;hard decode flag426 AUDI 10H,^RD ;transform DQPSK data to QPS 483 LDI @FLAGOP1, AR2K data 484427 cmpi @CIRC TOP,^r0 485 CALL HARDDECODE_CHUNK428 BLT NO ADJ 486429 SUBI OTFFh,^RD 487 LDI @CURRENT_START, RD430 N0_ADJ2: 488 ADDI 10H, RD ;transform DQPSK data to QPS431 CALL DQPSK_DEINT K data432 489 cmpi @CIRC_TOP,^r0433 LDI @BUFP1, ARO ;Zk value 490 BLT NO ADJ434 LDI @BUFP2, AR1 ;Wk value 491 SUBI^0-FEFh,^RD435 492436 LDI^512,^R1 493437 LDI @FLAGOP1, AR2 494 ;NO_ADJ: LDI RD, ARO ;real I values438 ADDI 1, AR2 495 LOT RO, AR1439 LDI^7,^RU 496 ADDI 10008, AR1 ;real Q values440 STI RO, @ADDER_ONE_PUNC 497441 STI RO,^@ADDER_TWO_PUNC 498 LDF *ARO++(1)%,^R2442 499 STF R2,^@OLDI ;initialize OLDI & OLDQ443 CALL START_VITB 500 LDF *AR1++(1)%,^R2444 501 STF R2,^@OLDQ445 502446 503 LDI @BUFP1, AR3 ;I447 504 LDI @BUFP2, AR4 ;4448 505 LDI 496,^R4 ;length to decode449 ;Refresh start and stop frame pointers used in flag validati 506on 507 ;MORE:450 LDI @CURRENT START, RD 508 LDF @OLDI, RD451 STI RD.^@STAT2T_FRAME 509 LDF @OLDQ, R1452 510 LDF *ARO++(1)%,^R2453 ADDI 210H,^RO 511 LDF *AR1++(1)%,^R3454 LOT @CIRC TOP,^R1 512 PUSH R4455 CMPI R1,^13-0 513 CALL DIFFERENTIAL_PHASE_DECODING456 BLT NO SUB2 514 POP R4457 SUBI^1-0-00H,^RD 515 STF R6,^*AR4++(1)% ;Wk LSB458 516 STF R7,^*AR3++(1)% ;Zk MSB459 NO_SUB2:STI RU,^@STOP_FRAME 517 ;branch symbol ZkWk460 518 ;or IQ461 LDI^1,^R1 ;send an ACED to HOST PROGRAM 519 STF R2,^@OLDI462 LDP DUAL 520 STF R3, @OLDQ463 STI R1,^PACED 521 SUBI 1,^R4464 LDP CODES 522 BP MORE465 BR BOSS 523 flop466 524 LOT @BUFP1, ARO ;Zk value467 525 LOT @BUFP2, AR1 ;Wk value468 LDP DUAL ;insure ACED is clear 526 LDI 64,^R1469 LDI^0,^R7 527 LDI @FLAGOP1, AR2470 STI R7,^@ACKO 528 ADDI 1, AR2471 LOP CODES 529 CALL START_VITB472 LDI @FLAGOP1,^R6 ;clear slot 0 area of P1 530473 LDI @PACKET1HARDP1, R7 531 ;Refresh start and stop frame pointers used in flag validati474 CALL CLEAR on475 532 LDI @CURRENT START, RU476 STI RD, @CURRENT_START 533 STI RD,^@STATt.T_FRAME477 LDI 496,^R1 ;496 dibits . 992 bits 534 addi 200h,^r0478 535 cmpi 3200h,^r0479 ;CALL DATA_CHUNK_FULL ;insure all 496 dibits rcvd 536 bit NO SUB480 ;before any further processi 537 subi 1T)00h,^r0ng 538 ;NO_SUB: sti rO, @STOP_FRAMEOct 6 1993 14:39:55^RCVRADAP.ASM^Page 11 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 12539 ;SUBI^1,^AR2 597540 ;LDI AR2,^R6 598 LDP CODES541 ;STI R6,^@STOP_FRAMF 599 LDI @PACKETOHARDP1, AR1542 600 LDI *AR1++,^RO543 LDI 1, R1 ;send an ACK° to HOST PROGRAM 601 LDI *AR1,^R1544 LDP DUAL 602 LDI R1,^R4545 OTT R1,^@ACKO 603 LDI @CRC MASK, R2546 LDP CODES 604 AND R2,^1.4547 605 LSH -5,^R4 ;R4 . CRC548 606 LDI 31,^R2549 607 AND R2, Ni ;mask out TAIL & CRC from he550 BR BOSS ader551 608552 609 LDI 9HEADBUF1, AR5610 LDI @HIGH MASK, R2553 ; 611 LSH 16, RT554 ; MODE ADAPTIVE CPC DECODING 612 AND NO,^R2,^R3555 ;^This mode allows the receiver to decode a rate 1/2 header 613 LSH -16,^R3556 ; either a rate 1,^3/4 or 1/2 data packet. 614 OR R1, R3557 615 LSH 16,^RD558 616 STI RO,^*AR5++559 617 STI R3,^*ARS--560 MODE3: 618561 LDP DUAL^ ;insure ACED is clear 619562 LDI 8888,^R7 620563 STI R7,^@ACK° 621 LDP CODES564 LDP CODES 622 LDI 17,^NO565 LDI @FLAGOP1,^R6 ;clear slot 0 area of P1 623 LDI @CRC CCITT,^R1566 LDI @PACKET1HARDP1, R7 624 LDI^2,^R.567 CALL CLEAR 625 LDI @HEADBUF2, R3568 626569 STI RU, @CURRENT_START 627570 628 PUSH R3571 LDI 16, R1^ ;hard decode flag 629 PUSH 92572 LDI @FLAGOP1, AR2 630 PUSH R1573 631 PUSH AR5574 CALL HARDDECODE_CHUNK 632 PUSH RO575 633 CALL _polydiv576 634 SUBI 5,^SP577 LDI @CURRENT_START, NO 635578 ADDI 10H,^RD ;transform DQPSK data to QPS 636 CMPI RU,^R4K data 637 LDINZ 9999,^R1579 cmpi @CIRC_TOP,^r0 638 BNZ NACK ;if CRC fails send NACK580 BLT NO_ADJ 639 ;otherwise strip info from header581 SUBI OFFFh,^RD 640 ;and decode data packet582 NO_ADJ: 641583 CALL DQPSK_DEINT 642 ldi @PACKETOHARDP1, AND584 643 LDI *++ARO,^RU ;get 2nd word of header585 LOT 9BUFP1, ARO^ ;Zk value 644 ldi rO,^rl586 LDI @BUFP2, AR1 ;Wk value 645 AND 3,^RD587 LDI^64,^R1 646 and 12,^rl588 LDI @FLAGOP1,^1R2 647 LDIZ 9999,^R1589 ADDI 1, AR2 648 BZ NACK ;if rate is wrong header is NFG590 LDI 3fh,^RU 649 LDP DUAL591 STI NO, @ADDER_ONE_PUNC 650 lsh -2,^rl592 STI RO, @ADDER_TWO_PUNC 651 STI Ni,^@RATE ;get rate of data packet593 652 sti rO,^@CODE ;get CPCi code to use i=1,^2594 CALL START_VITB 653595 654 LDP CODES ;^1^- CPC1596 ;HEADER SOFT DECODED AND PLACED 9 300C1--300C2 655 ;^2^- CPC2Oct 6 1993 14:39:55 RCVRADAP.ASM^Page 13 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 14656 716657 717 DECODE:658 718 LDI @PACKETOHARDP1, AR2659 LDI @BUFP1, ARO 719 ADDI 3, AR2^;leave blank word for CRC calc660 LOT @BUFP2, AR1 720661 721662 ADDI 64, ARO 722663 ADDI 64, AR1 723 STI R1, @ADDER_ONE_PUNC664 724 STI R2, @ADDER_TWO_PUNC665 CMPI^1,^R1 ;rate 1 725 LDI R3, R1^;BIT LENGTH TO DECODE666 BZ RATE1 726 PUSH R7667 CMPI 2,^R1 ;rate 3/4 727 PUSH R4668 BZ RATE75 728 CALL START_VITB669 CMPI 3,^R1 ;rate 1/2 729670 HZ RATE50 730 ;CRC calculation for data packet671 LDI 9999,^R1 731672 BR NACK 732 LDI @PACKETOHARDP1, AR3673 733 ADDI 2, AR3674 RATE1: 734 LDI 33,^RO675 LDI 896,^R3 735 LDI @CRC 32,^131676 LDI 27,^R4 736 LDI @DATT,BUFP1, R3677 737 POP R4^ ;# OF DATA WORDS678 CMPI^1,^RO 738 LDI R4,^R2679 LDIZ 15H,^R1 739 PUSH R4680 LDIZ 2AH,^R2 740681 LDIZ 100,^R7 741 PUSH R3682 742 PUSH R2683 CMPI^2,^RO 743 PUSH R1684 LDIZ 2AH,^R1 744 PUSH AR3685 LDIZ 15H,^R2 745 PUSH RO686 LDIZ 200,^R7 746687 BR DECODE 747 CALL _polydiv688 RATE75: 748689 LDI^672,^R3 749 SUSI 5,^SP690 LDI^20,^R4 750 LDI @PACKETOHARDP1, ARO691 751 POP R4692 CMPI^1,^RO 752 ADDI R4, ARO693 LDIZ 2dh,^131 753 ADDI 2, ARO694 LDIZ lbh,^R2 754 LDI *ARO,^R1695 LDIZ^100,^R7 755 POP R7696 756 CMPI EU,^R1697 CMPI 2,^RI 757 LDIZ R7,^R1698 LDIZ 36h,^R1 758 HZ ACK699 LDIZ 2dh,^R2 759700 LDIZ 200,^R7 760 LDP DUAL701 BR DECODE 761 LDI @CODE,^RO702 RATE50: 762703 LOT^448,^R3 763 LDP CODES704 LDI 13,^R4 764 LDI @SEQUENCES, R1705 765706 CMPI^1,^RU 766707 LDIZ 3fh,^R1 767 CMPI 1,^RU ;if rate CPC1 load pointers708 LDIZ 3fh,^R2 768 LDIZ @CPC1I, ARO^ ;and update sequence count709 LDIZ 100,^R7 769 LDIZ @CPC1Q, AR1710 770 LDIZ 1,^R2711 CMPI 2,^RU 771712 LDIZ 3fh,^R1 772 CMPI 2,^RU ;if rate CPC2 load pointers713 LDIZ 3fh,^R2 773 LDIZ @CPC2I, ARO^ ;and update sequence count714 LDIZ 200,^R7 774 LDIZ @CPC2Q, AR1715 BR DECODE 775 LDIZ 2,^E2Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 15 Oct 6 1993 14:39:55^RCVRADAP.ASM Page 16776 829777 OR R2,^R1 830 LDP DUAL778 STI R1,^@SEQUENCES^;write sequence count 831 LDI BRATS, R7779 832 ldp CODES780 ;save CPCx code to appropriate slot for possible combination 833 CMPI 1,^R7781 834 BZ RATE1A782 LDI @BUFP1, AR2 835 CMPI 2,^R7783 LDI @BUFP2,^AR3 836 BZ RATE75A784 ADDI 64, AR2 ;point to real values of dat 837 CMPI 3,^R7a packet 838 BZ RATE50A785 ADDI 64, AR3 839786 LOP *AR2++,^SO ;preload registers for copyi 840 RATE1A:ng 841 STI 53, @ADDER_ONE_PUNC787 LDP *APO++, R1 842 STI 54, @ADDER_TWO PUNC788 LDI lffh, RC^ ;copy 512 WORDS 843 STI R4, @ADDER_1PRIME_PUNC789 RPTB COPY_SEQUENCE 844 STI R3, @ADDER_2PRIME_PUNC790 845 LDI 896,^RC791 ;ldf^*ar2++,^r0 846 LDI 27,^R2792 ;ldf^*ar0,^rl 847 BR CONTINUE793 ;addf^rO,^rl 848 RATE75A:794 ;stf rl,^*ar0++ 849 STI R1, @ADDER_ONE_PUNC795 850 STI RO, @ADDER_TWO PUNC796 ;ldf^*ar3++,^r0 851 STI R2, @ADDER_1PRTME_PUNC797 ;ldf^*arl,^rl 852 STI 51, OADDER_2PRIME_PUNC798 ;addf rO,^rl 853 LDI 672,^RC799 ;COPY_SEQUENCE: stf rl,^*arl++ 854 LDI 20,^R2800 855 BR CONTINUE801 ;The above commented out instructions are used in Code Combi 856 RATE50A:ning 857 STI R5, @ADDER_ONE_PUNC802 858 STI R5, @ADDER_TWO PUNC803 LDF *AR2++,^SO 859 STI R5, @ADDER_1PRYME_PUNC804 IISTF RO,^*ARO++ 860 STI R5, @ADDER_2PRIME_PUNC805 COPY_SEQUENCE: 861 LDI 448,^RC806 LDF *AR3++,^51 862 LDI 13,^R2807 IISTF R1,^*AR1++ 863 BE CONTINUE808 . 864 CONTINUE:809 865 PUSH R2810 ;currently rcvd data packet placed in CPC1 or CPC2 slot 866 LDI @CPC1I, ARO811 867 LDI @CPC1Q, AR1812 LDI @SEQUENCES,^SO 868 LDI @CPC2I,^A52813 869 LDI @CPC2Q, AR3814 CMPI^3,^RO 870 LDI 9BUFP1, AR4815 LDINZ 6666,^51 ;do we have at least two seq 871 LDI @BUFP2, ARSuences 872 ;combine 512 words for each I and Q816 BNZ NACK ;to combine 873 RPTB COMBINE817 ;NO - send NACK 874818 ;YES - combine sequences and 875 LDI @PUNC COLUMN, 51decode 876 MPYI 2, RT819 ;combine CPC1 and CPC2 877 CMPI 64,^51820 LDI 32,^RO ;initialize all necessary p 878 LDIZ 1,^R1ointers 879 sti rl, @PUNC_COLUMN821 STI SO,^@PUNC_COLUMN^;and variables for combining 880822 881 TSTB OADDER_ONE_PUNC, R1823 LDI lbh,^SO ;CPC1 and CPC2 I and Q val 882 LDFZ 0,^R2ues 883 BZ OVER1824 LDI 2dh,^R1 884 LDF *ARO++, R2 ;R2^. Ii825 LDI 36h,^R2 885826 LDI^15h,^R3 886 OVER1:^TSTB OADDER_1PRIME_PUNC, R1827 LDI 2ah,^R4 887 LDFZ 0,^R3828 ldi^3fh,^r5 888 BZ OVER2Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 17 Oct 6 1993 14:39:55^RCVRADAP.ASM Page 18889 LDF *AR2++,^R3 ;R3 - 12 949 LDI @CRC_32,^R1890 950 LDI @DATABUFP1, R3891 OVER2:^TSTB @ADDER_TWO_PUNC, R1 951 POP R2892 LDFZ 0,^R4 952 PUSH R2893 BZ OVER3 953894 LDF *AR1++,^R4 ;R4 = Ql 954 PUSH R3895 955 PUSH R2896 OVER3:^TSTB @ADDER_2PRIME_PUNC, R1 956 PUSH R1897 LDFZ 0,^R5 957 PUSH AR3898 BZ OVER4 958 PUSH RU899 LDF *AR3++,^R5 ;R5 = Q2 959900 960 CALL _polydiv901 961902 OVER4: 962 SUBI 5,^SP903 ADDF R2,^R3 963 LDI @PACKETOHARDP1, ARO904 ADDF R4,^R5 964 POP R2905 965 ADDI R2, ARO906 STF R3,^*AR4++ 966 ADDI 2, ARO907 COMBINE:STF R5,^*AR5++ 967 LDI *ARO,^R1908 968 and @MASK1,^r0909 ;clear memory at PACKETOHARDP1 969 and @MASK1,^rl910 LDI @PACKETOHARDP1, R6 970911 ADDI 3,^R6 971 CMPI RU,^R1912 LDI @PACKET1HARDP1, R7 972 BZ CLEAN_COMBINE913 CALL CLEAR 973 LDI^6666,^R1914 974 BR HACK915 ;viterbi decode rate 1/2 combined sequences 975916 976 CLEAN_COMBINE:917 ldp CODES 977 LDP CODES918 ldi @BUFP1,^ar0 978 LDI^0,^R1919 ldi @BUFP2,^AR1 979 STI R1,^@SEQUENCES920 ldi @PACKETOHARDP1,^ar2 980 LDI^300,^R1921 addi 3,^ar2 981 BR ACK922 982923 983924 LDI^3fh,^RU 984 ;Refresh start and stop frame pointers used in flag validati925 STI RU, @ADDER_ONE_PUNC on926 STI RU, @ADDER_TWO_PUNC 985 ACK:927 986 ;LDI 1,^R1928 LDP DUAL 987 LOP DUAL929 LDI @RATE, R7 988 STI R1,^@ACK°930 ldp CODES 939 LDP CODES931 CMPI 1,^R7 990 ldi 8BUFP1,^r6932 ldiz^896,^rl 991 ldi r6,^r7933 CMPI 2,^R7 992 addi Oeffh,^r7934 ldiz^672,^rl 993 call CLEARFLOAT935 CMPI 3,^R7 994936 ldiz^448,^rl 995 ldi @CPC2Q,^r6937 996 ldi r6,^r7938 997 addi 300h,^r7939 CALL START_VITB 998 call CLEARFLOAT940 999941 ;check CRC again 1000 CLEANER:942 1001 LDI @CURRENT START, RU943 1002 STI RU,^@STAFT.T_FRAME944 ;CRC calculation for data packet 1003 addi 210h,^r0945 1004 ldi @CIRC_TOP,^rl946 LDI @PACKETOHARDP1, AR3 1005 cmpi rl,^r0947 ADDI 2, AR3 1006 bit NO SUB948 LDI^33,^RU 1007 subi 100h,^r0Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 19 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 201008 NO_SUB: sti rO,^@STOP_FRAME 1064 stf r3,^*ar3++1009 10651010 10661011 BR BOSS 1067 LDF *ARO++(1)%,^R2 ;load real data I1012 1068 IILDF *AR1++(1)%,^R3 ;and Q1013 NACK: 1069 ;ldi @TROUBLE2,^ar31014 ;LDI 9999, R1^;send an NACKO to HOST PROGRAM 1070 stf r2,^*ar3++1015 LDP DUAL 1071 stf r3,^*ar3++1016 STI R1,^@ACK° 1072 ldf @OLDI,^r51017 LDP CODES 1073 stf r5,^*ar3++1018 cmpi^6666,^rl 1074 ldf OOLDQ,^r51019 bz CLEANER 1075 stf r5,^*ar31020 ;BR POLIZIA 10761021 BR BOSS 1077 PUSH R11022 1078 PUSH R41023 1079 ldf @OLDI,^r01024 ;******************************************************************* 1080 ldf @OLDQ,^rl* 1081 CALL HARDDECODE^ ;hard decode it1025 ; This section of code is responsible for hard decoding a chun 1082k 1083 POP R41026 ; of data given: 1084 POP R11027 ; Requires: 1085 STF R2,^@OLDI1028 ; RD^= start of real data I channel 1086 STF R3,^@OLDQ^ ;refresh OLDI & OLDQ1029 ; R1^. length to decode in Dibits 10871030 ; AR2 . where to place hard data 1088 LDI *AR2,^R2 ;place dibit @ current boat1031 ; Modifies: ion1032 ; R1,^R2,^R3,^R4,^R5,^R6,^R7 1089 LSH -2,^R21033 ; ARO, AR1,^AR2 1090 LSH 30,^NO1034 ; Returns: 1091 OR RU, R21035 ; Nothing 1092 STI R2,^*AR21036 10931037 HARDDECODE CHUNK: 1094 SUBI 1, R4 ;decrement dibit count1038 L]:)-^0,^R2 1095 BNZ NO_MEM INC1039 STF R2,^@OLDI^ ;initialize OLDI & OLDQ 1096 irtADDI 1, A.^ ;increment memory pointer1040 STF R2,^@OLDQ 1097 LDI 16,^R4 ;reset dibit count1041 10981042 LDI RO, AR7 ;store flag start for future 1099 NO_MEM_INC:ref 1100 SUBI 1,^R1 ;length . 0^?1043 LDI NO, ARO^ ;ARO . I channel pointer 1101 BNZ MORE_DIBITS^ ;no, branch back1044 LDI RO, AR1 ;add offset to get Q channel 1102 RETS ;yes,^returnptr 11031045 ADDI 1000H, AR1^ ;AR1 = Q channel pointer 1104 ;*******************************************************************1046 LDI 16,^R4 ;R4 . dibit count *1047 11051048 ldf^*ar0++(1)%,^r2 1106 ;^This section of code checks to insure that the necessary dat1049 stf r2,^@OLDI a1050 ldf^*arl++(1)%,^r2 1107 ;^chunk has ALL been rcvd (real data) before any further proce1051 stf r2,^@OLDQ ssing1052 1108 ;^done1053 MORE_DIBITS: 1109 ; Requires:1054 1110 ; RU . start of flag pointer1055 1111 ; R1 . # of dibits that chunk consists of1056 ldi 8TROUBLE2,^ar3 1112 ;^Modifies:1057 LOT ARO,^R2 1113 ; R1,^R21058 LDI AR1,^R3 1114 ;^Returns:1059 sti^r2,^*ar3++ 1115 ; Nothing1060 sti^r3,^*ar3++ 11161061 ldf^*ar0,^r2 11171062 ldf^*arl,^r3 1118 DATA_CHUNK FULL:1063 stf^r2,^*ar3++ 1119 LOT RO, R2_ ___^,Oct 6 1993 14:39:55^RCVRADAP.ASM^Page, 21 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 221120 ;ADDI 16,^R2 ;R2 . start of data chunk 1176 MPYF3 RO, R3,^R5 ;R5 = oldI * newQ1121 1177 SUBF R4,^R5,^R7 ;R7 . R5 - R41122 ADDI R1, R2 ;R2 now contains address poi 1178nter 1179 ;At this point R6 . Wk and R7 = Zk1123 ;for last dibit 11801124 GO: 1181 RETS1125 ;cmpi @CIRC TOP,^r2 11821126 cmpi @CIRCLESS1,^r2 1183 ;*******************************************************************1127 bit WAIT2 ***1128 subi OFFFh,^r2 1184 ;^This section of code is responsible for the actual hard deco1129 WAIT2: ding1130 ldi @REAL_IBIT_POINTER, rl 1185 ;^It references Wk and Zk and uses these real values to decide1131 cmpi r2,^rl 1186 ; which dibit was sent.1132 bnz WAIT2 11871133 1188 ;^Requires1134 1189 ; RO = oldI1135 1190 ; R1 . oldQ1136 WAIT: 1191 ; R2 . newI1137 ;LDI @REAL IBIT_POINTER, R1 1192 ;^R3 . newQ1138 ;CMPI R2,^lil ;reached last dibit^? 1193 ; R6 = Wk1139 ;BLT WAIT ;no,^then wait 1194 ; R7 . Zk1140 GETOUT: 1195 ;^Modifies:1141 ldi 9TROUBLE3, ar0^;debug code to check when 1 1196 ; RI,^R4,^R5,^R6,^R7eft loop 1197 ;^Returns:1142 sti^rl,^*ar0++ 1198 ; RI . dibit received1143 ldi rl,^arl 11991144 ldf *arl,^rl 1200 HARDDECODE:1145 sti rl,^*ar0 1201 CALL DIFFERENTIAL_PHASE_DECODING1146 RETS ;yes,^then return 12021147 1203 ;if^(Wk > 0 & Zk > 0)1148 1204 CMPF 0,^R61149 1205 BLE Li1150 ;********************************************************************** 1206 CMPF 0,^R71207 BLE Li1151 ;^This section of code is responsible for decoding the differe 1208 ; dibit is decoded as 3ntial 1209 LDI 3,^RO1152 ;^phase from the real data.^It operates on the real data from 1210 RETS1153 ; the I and Q channel and outputs real data which is no longer 12111154 ;^dependent on the previous real data.^That is it transforms 1212 Li:^;else if^(Wk > 0 & Zk < 0)1155 ; pi/4 - DQPSK real data to QPSK real data for hard decoding. 1213 CMPF 0, R61156 ;^The mapping of this transform is given by Wk and Zk. 1214 BLE L21157 ; 1215 CMPF 0, R71158 ;^Requires 1216 BGE L21159 ; RI . oldI 1217 ;dibit is decoded as a 21160 ; R1 = oldQ 1218 LDI 2,^RI1161 ; R2 . newI 1219 REIS1162 ;^R3 = newQ 12201163 ; Modifies: 1221 L2: ;else^if^((6k <^0^&^Zk > 0)1164 ; R4,^R5,^R6,^R7 1222 CMPF 0,^R61165 ;^Returns: 1223 BGE L31166 ; R6 = Wk . oldI * newI + oldQ * newQ 1224 CMPF 0,^R71167 ; R7 . Zk = oldI * newQ - oldQ * newI 1225 BLE L31168 ; 1226 ;dibit is decoded as a 11169 1227 LDI 1,^RI1170 DIFFERENTIAL PHASE DECODING: 1228 RETS1171 MPYF^RI,^1-22,^R4 ;R4 = oldI * newI 12291172 MPYF3 R1,^R3,^R5 ;R5 . oldQ * newQ 1230 L3: ;Otherwise dibit is decoded as a 01173 ADDF R4,^R5,^R6 ;R6 . R4 + R5 1231 LOT 0,^RI1174 1232 RETS1175 MPYF3 R1,^R2,^R4 ;R4 = oldQ * newI 1233 7 *******************************************************************Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 23 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 24*** 1286 TSTB 1,^R41234 ;^This section of code uses a shift register which is shifted 1287 BZ OVERand ORed 1288 ADDI 1,^R61235 ;^with the most recent decoded dibit.^This register is then 1289 OVER:1236 ; compared to the flag and if it matches the address which poi 1290 LSH -1,^R3nts 1291 LSH -1,^R41237 ;^to the occurrence of this flag (in real data)^is saved in 1292 SUBI 1,^R71238 ; the FLAG_ADDRESS_TABLE. 1293 BP TEST1239 ; 12941240 ;^Requires: 1295 SUSI R5,^R61241 ; RO = contains most recent decoded dibit 1296 CMPI @THRESHOLD, R61242 ;^Modifies: 1297 BGE FLAG_FOUND1243 ; RO,^R1,^AR2 1298 BR ENDS1244 ;^Returns: 1299 ;.******************************************************************1245 ; Nothing12461247 FLAG_CHECKER: 1300 ;^This section of code is responsible for hard decoding a chunk1248 LDI @FLAG TO_BE, R1^;load current decoded word 1301 ;^data given:1249 LSH -2, RI^ ;shift word right by 2 1302 ; Requires:1250 LSH 30,^RO ;shift dibit left by 30 1303 ; ARO^. start of MSB data Zk Q1251 OR RO, R1 ;OR dibit with current word 1304 ; AR1^= start of LOB data Wk I1252 STI R1,^@FLAG_TO_BE 1305 ;^R1^. length to decode in Dibits1253 lsh -8,^R1 1306 ; AR2 = where to place hard data1254 1307 ;^Modifies:1255 CMPI @FLAG_COMP, R1^;compare word to flag patter 1308 ; R1,^R2,^R3,^R4,^R5,^R6,^R7n 1309 ; ARO,^AR1,^AR21256 ;BNZ ENDS 1310 ;^Returns:1257 BNZ^CORRELATE ;if no match,^then return 1311 ; Nothing1258 13121259 FLAG_FOUND: 1313 QPSK1:1260 LDI @FLAG_ADDRESS_TABLE, AR2^;yes,^flag found 1314 LDI 16,^R4 ;R4 = dibit count1261 1315 MORE_DIBITS1:1262 LDI @REAL_IBIT_POINTER,^RD^;get address location of fla 1316 LDF *ARO++,^R7 ;load real data MSBg end 1317 IILDF *AR1++,^R6 ;and LSB1263 STI RO,^*AR2++^ ;store in FLAG_ADDRESS_TABLE 13181264 LDI AR2,^RO 1319 PUSH R11265 CMPI @TABLE_BOTTOM, RO^;if FLAG_ADDRESS_TABLE reach 1320 PUSH R4ed 1321 CALL QPSK2^ ;hard decode it1266 BNZ UPDATE_TABLE^ ;bottom of buffer 13221267 LDI @TABLE_TOP,^RO ;reset to top of buffer 1323 POP R41268 UPDATE_TABLE: 1324 POP R11269 STI RO, @FLAG_ADDRESS_TABLE 13251270 1326 LDI *AR2,^R2 ;place dibit @ current locat1271 ion1272 ENDS:^RETS 1327 LSH -2,^R21273 1328 LSH 30,^RO1274 CORRELATE: 1329 OR RU,^R21275 LDI @FLAG COMP, R2 1330 STI R2,^*AR21276 XOR R1,^R,^R3 ;R3^. negative l's 13311277 NOT R3,^R4 ;R4 . positive l's 1332 SUBI 1,^R4 ;decrement dibit count1278 LDI 0,^R5 ;R5 . number of negative 1 b 1333 BNZ NO_MEM INC1its 1334 ADDI 1, ARI ;increment memory pointer1279 LDI 0,^R6 ;R6 = number of positive 1 b 1335 LDI 16,^R4 ;reset dibit countits 13361280 LDI 24,^R7 ;correlate for 24 bit length 1337 NO_MEM_INC1:1281 TEST: 1338 SUBI 1,^R1 ;length . 0 ?1282 TSTB 1,^R3 1339 BNZ MORE_DIBIT51^ ;no, branch back1283 BZ LOOK_POS 1340 RETS ;yes,^return1284 ADDI 1,^R5 13411285 LOOK_POS: 1342 ; *****.*************************************************************-^... _.Oct 6 1993 14:39:55^RCVRADAP.ASM^Pee 25 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 26*** 14001343 ; This section of code is responsible for the actual hard deco 1401 ;^Deinterleaver currently set for 256 bit blocksding 1402 ; which is 8 ROWS by 16 COLUMNS of SYMBOLS1344 ; It references Wk and Zk and uses these real values to decide 1403 ;^can handle up to 256 bit block if a larger1345 ; which dibit was sent. 1404 ; size is required the DSP board requires more memory1346 ; 1405 ;^to handle the operation and FREE1 and FREE2 should be1347 ; Requires 1406 ; changed to reflect the increase in memory as well as1348 ; R6 = Wk 1407 ;^the MAP.CMD file used for compiling and linking.1349 ; R7 . Zk 14081350 ; Modifies: 1409 DQPSK_DEINT:1351 ; R6,^R7 1410 LOT RO, ARO^ ;real I values1352 ; Returns: 1411 LOT NO, AR11353 ; RI . dibit received 1412 ADDI 1000H, AR1 ;real Q values1354 ; 14131355 QPSK2: 1414 LDF *ARO++(1)%,^R21356 ;if^(Wk >^0^&^Zk > 0) 1415 STF R2,^@OLDI ;initialize OLDI & OLDQ1357 CMPF 0,^R6 1416 LDF *AR1++(1)%,^R21358 BLE L11 1417 STF R2,^@OLDQ1359 CMPF 0,^R7 14181360 BLE Lll 1419 LOT @BUFP1,^AR3 ;I1361 ;^dibit is decoded as 3 1420 LOT @BUFP2, AR4 ;41362 LDI^3,^NO 1421 ldi^512,^r41363 RETS 1422 ;LOT 496,^R4 ;length to decode1364 14231365 L11: ;else^if^(Wk >.^0^& Zk <^0) 1424 MORE:1366 CMPF 0,^R6 1425 LDF @OLDI,^RO1367 BLE L12 1426 LDF @OLDQ, R11368 CMPF 0,^R7 1427 LDF *ARO++(1)%,^R21369 BGE L12 1428 LDF *AR1++(1)%,^R31370 ;dibit is decoded as a 2 1429 PUSH R41371 LDI^2,^RO 1430 CALL DIFFERENTIAL_PHASE_DECODING1372 RETS 1431 POP R41373 1432 STF R6,^*AR4++(1)%^ ;Wk LSB1374 L12: ;else^if^(Wk <^0 & Zk a 0) 1433 STF R7,^*AR3++(1)% ;Zk MSB1375 CMPF 0,^R6 1434 ;branch symbol ZkWk1376 BCE L13 1435 ;or IQ1377 CMPF 0,^R7 1436 STF R2,^@OLDI1378 BLE L13 1437 STF R3,^@OLDQ1379 ;dibit is decoded as a 1 1438 SUBI 1,^R41380 LDI^1,^RO 1439 BP MORE1381 RETS 14401382 14411383 L13: ;Otherwise dibit is decoded as a 0 1442 ;AT THIS POINT Zk VALUES ARE AT @BUFP1 AND Wk AT @BUFP21384 LDI^0,^RO 14431385 RETS 1444 ;DEINTERLEAVE THE DATA1386 ;******************************************************************.** 14451446 LOT @FREE1,^R61387 ; 1447 LOT R6,^R71388 ; This code transforms real DQPSK data to real QPSK data and 1448 ADDI 600H,^R71389 ; then deinterleaves the data placing it 880FP1 and @BUFP2 1449 CALL CLEARFLOAT1390 ; for either hard decoding by QPSK or soft decoding. 14501391 ; 14511392 ; 1452 LDI @BUFP1, ARO1393 ; Requires: 1453 LDI @BUFP2, AR11394 ; RO . start address of real I data in receiver buffer 1454 LDI @FREE1, AR21395 ; 1455 LDI @FREE2, AR31396 ; Returns: 14561397 ; BUFP1 contains Zk real values MSB 1457 LDI 0,^RI ;RO is block count ‹. 81398 ; BUFP2 contains Wk real values LSB 1458 KEEP_DEINT:1399 ; 1459 LDI^0,^R1 ;R1^. ROW .^0,1,2,3-^--Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 27 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 281460 LDI^0,^R2 ;R2^= COLUMN =^0,1,2,3,..,15 15161461 1517 ADDI 1, NO^ ;BLOCK COUNT++1462 SYMBOL: 1518 LDI NO,^R31463 LDI R2,^R3 ;R3 . SYMBOL 1519 MPYI DEINT BLOCK, R314641465MPYI DEINT ROW, R3AUDI R1,^"irt15201521ADDI R3, A170ADDI R3, AR11466 LDI R3,^IRO 15221467 1523 CMPI BLOCKS, NO^ ;BLOCK COUNT<=7 KEEP DE1468 LDF *ARO++,^R4 ;pick the symbol from interleav INTed 1524 BNZ KEEP_DEINT1469 LDF *AR1++,^R5 ;buffer and place in deinterlea 1525ved 15261470 STF R4,^*+AR2(IRO)^ ;buffer 15271471 STF R5,^*+AR3(IRO) 1528 ;*******************************************************************1472 **1473 AUDI 1,^R2 ;COLUMN++ 1529 ;^This is the beginning of the Viterbi decoding algorithm.1474 CMPI 16,^R2 ;IF COLUMN<=15 GOT() SYMBOL 15301475 BNZ SYMBOL 15311476 15321477 ADDI^1,^R1 ;ROW++ 15331478 LDI 0,^R2 ;COLUMN . 0 1534 START_VITB:1479 CMPI DEINT_ROW, R1 1535 LDP CODES1480 BNZ SYMBOL ;IF ROW<=3 GOTO SYMBOL 1536 LDI 32,^RI1481 1537 STI RI, @PUNC_COLUMN1482 ;1 128BIT BLOCK DEINTERLEAVED AND READY TO BE COPIED BACK 15381483 ;TO THE BUFFER IT CAME FROM 1539 LDI 2,^NO1484 1540 STI NO,^@DEEP^ ;used to intial1485 ize trellis1486 LDI @BUFP1, ARO 1541 LDI 0,^RO1487 LDI @BUFP2,^AR1 1542 STI NI, @FORCE_END_ZEROS1488 LDI RO,^R1 1543 subi 4,^rl ;length-41489 MPYI DEINT BLOCK, R1 1544 PUNC:1490 ADDI R1, A50^ ;Adjust the pointers @BUFP1, 1545 LDI 0,^NO@BUFP2 1546 CMPI 5,^R11491 AUDI Ni, AR1 1547 LDILE OFFFFH, NO1492 1548 STI RO, @FORCE_END_ZEROS1493 LDF *AR2++,^R6 15491494 LDF *AR3++,^R7 ;preload registers before bl 1550ock below 1551 LDI @PUNC COLUMN, RO1495 ;is executed 1552 MPYI 2,^RT)1496 ldi DEINT BLOCK,^RC 1553 CMPI 64,^NO1497 SUBI 1,^RE 1554 LDIZ 1,^NO1498 RPTB DEINT 1555 STI RO,^@PUNC COLUMN1499 1556 TOTS @ADDER_ORE_PUNC, NO1500 LDF *AR2++,^R6 1557 LDFZ 0,^R2 ;stuff zero as I value1501 IISTF R6,^*ARO++ 1558 BZ GET_Q_VALUE1502 DEINT: 1559 LDF *ARO++,^R2 ;get I value from data1503 LDF *AR3++,^R7 15601504 IISTF R7,^*AR1++ 1561 GET_Q_VALUE:1505 1562 TSTB @ADDER_TWO_PUNC, RI1506 ;clear @FREE1 and @FREE2 1563 LDFZ 0,^R3 ;stuff zero as Q value1507 LOT @FREE1,^Ni 1564 BZ SKIP OVER1508 LOT R6,^R7 1565 LDF *ARY++, R3^ ;get real Q value from data1509 ADDI^600H,^R7 15661510 CALL CLEARFLOAT 15671511 15681512 LDI @BUFP1, ARO 15691513 LDI @BUFP2, AR1 1570 ;LDF *ARO++(IRO),^R2 ;get real I value1514 LDI @FREE1, AR2 1571 ;LDF *AR1++(IR1),^R3 ;get real Q value1515 LDI @FREE2, AR3 1572 SKIP_OVER: ,.^....Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 29 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 301573 LDI^16,^RO 1627 ldi^*-ar3(2),^r4 ;top partial metric previous1574 LOT @FORCE_END_ZEROS, R4 ;force zero for last 5 symbo stateis 1628 ldi^*+ar3,^r6 ;lower partial metric previo1575 us state1576 LDINZ 16,^RO 16291577 STI RI,^@PATH 16301578 ;LDFNZ^-7.07E-1,^R3 1631 PUSHF R31579 1632 PUSH R31580 LDI @DEEP,^RI 1633 PUSHF R21581 CMPI 16,^RI ;if trellis is not initialized 1634 PUSH R21582 BLE INIT_VITB ;4 branches deep then call mit 1635_vitb 1636 CALL FIND_CORRECT_SURV1583 16371584 ;At this point the Viterbi Decoder is initialized 4 branches 1638 ;CMPF R5,^R7 ;R7 - R51585deep.;That is there are 16 survivors and now we can go through th 1639 h;BGT UPPER_BRANCH ;R7 > R5 choose upper brance 16401586 ;repeat process of looking at all 32 paths,^calculating partSal 1641 ch;LDI *++AR3,^R4 ;R7 < R5^choose lower bran1587 ;metrics,^and decoding. 1642 ;CALL FIND_CORRECT_SURV ;R5 >= R7 choose lower bran1588 ch1589 16431590 LDI^0,^RO 1644 ONWARD: POP R21591 ;^SUBI^4,^R1 ;R1 = length - 4 1645 POPF R21592 TOP: 1646 POP R31593 LDI rO,^R4 ;calculate offset to add to 1647 POPF R3base addr 16481594 MPYI 7,^R4 1649 ADDI 1,^NO1595 LDI @STATE TABLE, AR3 1650 CMPI @PATH,^RO ;repeat for all 32 paths1596 ADDI R4, ATO ;add offset to base addr 1651 BN TOP1597 ;^Ri'Rq' 16521598 LDF *++AR3,^R4 ;R4 = Ri'^0^0 16531599 LDF *++AR3,^R5 ;R5^= Rq' / 1654 LDI @SURV_STATE TABLE, AR4 ;update survivors1600 ; / 1655 LDI @NEXT 16_SUV, AR51601 LDF *++AR3(2),^R6 ;R6 = Ri"^/^Ri"Rq" 1656 LDI^15,^li.1602 LDF *++AR3,^R7 ;R7 = Rq"^0/ 1657 RPTB BLOCKS1603 ;This is the short cut metric 16581604 ;^MPYF R2,^R4 1659 LDI *AR5++,^R21605 ; MPYF R3,^R5 1660 STI R2,^*AR4++1606 ;^ADDF R4,^R5 ;R5 = top partial metric 16611607 negf r5 1662 LDF *AR5++,^R21608 1663 STF R2,^*AR4++1609 MPYF R2,^R6 16641610 MPYF R3,^R7 1665 LDI *AR5++,^R21611 ADDF R6,^R7 ;R7 = bottom partial metric 1666 STI R2,^*AR4++1612 ;^negf r7 16671613 ;This is the distance squared 1668 BLOCKS: ADDI 1, AR41614 subf r2,^r4 16691615 subf r3,^r5 16701616 mpyf r4,^r4 16711617 mpyf r5,^r5 16721618 addf r4,^r5 1673 LOT @SURV_STATE_TABLE, AR3 ;find smallest accum metric1619 1674 LDI 15, RC1620 subf r2,^r6 1675 LDF *++AR3,^R2 ;R2 = accumulated metric1621 subf r3,^r7 1676 ldi ar3,^ar4 ;ar4 = address of min metric1622 mpyf r6,^r6 1677 RPTB BLOCKS1623 mpyf r7,^r7 1678 LDF *++AR3(4),^R31624 addf r6,^r7 1679 CMPF R3, R2 ;R2-R31625 1680 LDFGT R3, R2 ;R2 > R3 so take r3 as min1626 1681 BLOCK6: LDIGT AR3, AMOct 6 1993 14:39:55^RCVRADAP.ASM^Page 31 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 321682 1737 LDI 0,^R21683 ;At this point R2 . minimum metric & AR4 the address of this 1738 LDF 0,^R3metric 1739 RPTB BLOCK71684 17401685 LDI *--AR4,^R3 ;R3 = output bit path histor 1741 STI R2,^*AR3++Y 1742 STF R3,^*AR3++1686 AND 1,^R3 ;R3 = output bit 1743 STI R2,^*AR3++1687 LDI @BIT COUNT, R4 1744 BLOCK7: STI R2,^*AR3++1688 LOB R4,^1723 17451689 ldi^*ar2,^r5 1746 LDI^-27,^R21690 OR R3,^r5 1747 STI R2,^@BIT_COUNT1691 sti^r5,^*ar2 17481692 ADDI 1,^R4 17491693 CMPI 32,^R4 1750 RETS1694 BNZ NO_BIT_COUNT_RESET 17511695 LDIZ 0,^R4 17521696 ADDI 1,^AR2 175316971698NO_BIT_COUNT RESET:STI 17(4,^@BIT_COUNT 1754 ;This section of codeer is usedto initialize the viterbi decod1699 17551700 SUBI^1,^R1 ;length -1 1756 INIT_VITB:1701 ;could add force to zero for 1757 LDI @STATE TABLE, AR4last 1758 LDI @SURV_TATE_TABLE, AR31702 ;5 data bits???? 1759 LDI 0,^RD1703 1760 TOP2:1704 1761 ;ADDI 1,^AR217051706BNZ PUNC 1762 LDI^*+AR3(2),^R6urvivor ;get last state of current s1707 ;Input data is finished so clean up and wrap up Viterbi decoding 1763 LDI^*++AR4(3),^R7a match ;compare to state table for1708 1764 CMPI R6,^R717091710LDI *AR4,^R3 ;get path historyLSH -1,^R3 ;lose first bit which was1765 CALLZ INIT_METRICmetric ;if matches calculate branch17111712 ;output just above 17661767LDI^*++AR4(3),^R7CMPI R6,^R7 ;repeat for lower branch1713 ;NEGI R4,^R5 ;negate bit count 1768 CALLZ INIT_METRIC1714 LDI R3,^R6 17691715 ;addi^1,^r4 1770 ADDI 1,^RO1716 LSH R4,^R3 ;shift path history 1771 CMPI 16,^NO1717 ldi *ar2,^r7 ;before writing to buffer 1772 addi 1,^an1718 OR R3,^r7 1773 BNZ TOP21719 sti^r7,^*ar2++ 17741720 1775 LDI @SURV_STATE_TABLE, AR3 ;copy next state fields to1721 LDI 33,^r5 ;check if any more bits to o 1776 LDI 0,^R3 ;last state fields ofutput 1777 LDI 15,^RC ;SURV_STATE_TABLE1722 SUBI R5,^R4 1778 RPTB BLOCK21723 bp CLOSE 1779 LDI^*++AR3(3),^R21724 ldi^*ar2,^r7 1780 STI R3,^*AR31725 1781 STI R2,^*-AR31726 LSH R4,^R6 1782 BLOCK2: ADDS 1, AR31727 OR R6,^r7 178317281729sti^r7,^*ar2CLOSE: 17841785LDI @DEEP,^R2 ;make sure the proper number17301731;reset the survivor table to original values;ldi^*+ar4,^r6 1786 MPYI 2,^R2for ;of survivors is initialized1732 ;ldi @TROUBLE6,^ar4 1787 STI R2,^@DEEP ;the first 4 branches17331734*ar4;sti^r6, 17881789 ;will^be^(2,^4,^8,^16)1735 LDI @SURV STATE_TABLE, AR3 1790 CMPI 16,^R21736 LDI 15,^RE 1791 BGT PUNCOct 6 1993 14:39:55^RCVRADAP.ASM^Page 33 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 341792 MPYI 2,^R2 ;copy all 5 fields for each 1846 ;R7 lower partial metricsurvivor 18471793 LDI @SURV STATE_TABLE, AR3 1848 LDI 15,^RC1794 LDI AR3,^T:R4 1849 LDI @SURV STATE TABLE, AR41795 ADDI R2, AR4 1850 LDI^*++AR74(2),^TR.-3 ;load last state of SURV1796 LDI *AR3++,^R3 1851 RPTB BLOCK41797 SUBI 1,^R2 18521798 RPTS R2 18531799 LDI *AR3++,^R3 1854 CMPI R4, R3 ;cmp to last state of top br1800 IISTI^R3,^*AR4++ anch1801 BR PUNC ;go back for more data 1855 ldiz ar4,^ar5 ;top branch1802 1856 cmpi r6,^r3 ;cmp to last state of lower1803 branch1804 INIT_METRIC; 1857 ldiz ar4,^ar6 ;lower branch1805 LDF *-AR4(2),^R4 ;R4 . state table I 18581806 LDF *-AR4, R5 ;R5 . state table Q 1859 NOP1807 ;MPYF R2,^R4 1860 BLOCK4:^LDI *++AR4(4),^R3 ;get next last state1808 ;MPYF R3,^R5 18611809 ;ADDF R4,^R5 ;R5 . partial metri 1862c 1863 ;ARS address of last state for top branch1810 ;negf r5 1864 ;AR6 address of last state for lower branch1811 18651812 cuff r2,^r4 1866 LDF *-AR5, R41813 cuff r3,^r5 1867 mpyf BETA, r41814 mpyf r4,^r4 1868 mpyf ONE_MINUS_BETA, r51815 mpyf r5,^r5 18691816 addf r4,^r5 1870 ADDF R4, R5 ;r5=accum metric with top br1817 anch met1818 LDF ***AR3,^R4 ;get accumulated met 1871tic of 1872 LDF *-AR6,^R61819 ;current survivor 1873 mpyf BETA, r61820 mpyf BETA,^r4 1874 mpyf ONE_MINUS_BETA, r71821 mpyf ONE_MINUS_BETA, r5 18751822 1876 ADDF R6, R7 ;R7=accum metric with lower1823 ADDF R4,^R5 ;add branch metric branch met1824 STF R5,^*AR3 ;update accumulated 1877metric 1878 CMPF R5,^R7 ;^R7 - R51825 18791826 LDI^*--AR3,^R4 ;get output history 1880 BGT UPPER_BRANCH ;R7 > R5 choose top branch R1827 LSH -1,^R4 ;R4 » 1 51828 LDI 0,^R5 ;output^"0" 18811829 CMPI 8,^RO ;if RClecurrenc state 1882 ldi ar6,^ar4 ;R5 > R7 choose lower branch>=8 R71830 LDIGE @BIT_MASK, R5 ;then output^"1" 1883 CALL UPDATE_SURV1831 OR R5,^R4 1884 REIS1832 STI R4,^*AR3 ;update path history 18851833 1886 UPDATE_SURV:1834 STI RO,^*++AR3(3) ;save next state 1887 ;we have the correct survivor so now we update it1835 18881836 ADDI 1, AR3 ;move to next surviv 1889 ;R7 = accumulated metricor 1890 ;ar4= last state SURV_TABLE1837 RETS 18911838 1892 LDI @NEXT 16_SURV, AR51839 ;This next section is used to find the correct survivor 1893 LDI RO, lj1840 FIND_CORRECT_SURV: 1894 MPYI 3,^R3 ;get offset to add t1841 o base add1842 1895 ADDI R3, AR51843 ;R4 last state for top partial metric 18961844 ;R5 top partial metric 1897 STF R7,^*+AR5 ;save annum metric1845 ;R6 last state for lower partial metric 1898Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 35 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 361899 ;save bit 1958 ;*******************************************************************1900 LDI^*-AR4(2),^R5 ***1901 LSH -1^,^R5 19591902 LDI^0,^R6 1960 RCV:19031904CMPI 8,^ROLDIGE @BIT_MASK, R6 1961 PUSH ST^ ;IMPORTANT MUST USE OTHERWISE REST 0F1905 OR R6,^R5 1962 ;PROGRAM WILL NOT WORK PROPERLY1906 STI R5,^*ARS^ ;save past history 1963 XOR 2000H,^ST ;disable interrupts1907 STI RO,^*+AR5(2) ;save last state 19641908 RETS 1965 PUSH DP ;save register contents1909 19661910 1967 push ir01911 1968 push irl1912 1969 push bk1913 1970 push ie1914 1971 push if1915 1972 push iof1916 1973 push rs1917 1974 push re1918 1975 push rc1919 19761920 UPPER BRANCH: 1977 PUSH RO1921 ldf r5,^r7 ;R5 metric in R7 1978 pushf r01922 LDI AR5, AR4^ ;choose upper branch 1979 PUSH R11923 CALL UPDATE_SURV 1980 pushf rl1924 RETS 1981 PUSH R21925 1982 pushf r21926 1983 PUSH R31927 1984 pushf r31928 1985 PUSH R41929 1986 pushf r41930 - 1987 PUSH R51988 pushf r51931 Interrupt 1 is responsible for obtaining real data from the 1989 PUSH R61932 I and Q channels and then hard decoding each dibit while 1990 pushf r61933 simultaneously searching for the occurence of a flag. 1991 PUSH R71934 1992 pushf r71935 Interrupt 1 occurs once every symbol duration time period. 1993 PUSH ARO1936 Currently a symbol lasts for: 1994 PUSH AR11937 1995 PUSH AR21938 6 *^6.6micros . 39.6 micros 19961939 1997 LDP CODES1940 39.6ms/60ns^= 660^instructions 1998 LDI @ADCHANA1, ARO^;read I channel1941 1999 LDI 8ADCHANB1, AR1 ;read Q channel1942 This allows for the execution of 660 instructions between 2000 LOT *ARO, RO1943 interrupt trigger times. 2001 LLD' *AR1, R11944 20021945 Currently this interrupt consists of^xx instructions giving 20031946 rise^to^: 2004 ash -16,^r01947 660 - xx = yy instructions of main code. 2005 ash -16,^rl1948 2006 FLOAT RO, R2 ;convert A to D hex value to1949 Requires: float1950 Nothing 2007 FLOAT R1,^R31951 Modifies: 20081952 RO,^R1,^R2,^R3,^R4,^R5,^R6,^R7 2009 MPYF @SCALE, R2^ ;scale float value down1953 ARO,^AR1,^AR2 2010 MPYF @SCALE, R31954 Returns: 20111955 Nothing 201219561957 2013 At this point R2 and R3 contain a scaled down floating point ..^;,...Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 37 Oct 6 1993 14:39:55^RCVRADAP.ASM^Page 382014 ;representaion of the I and Q channel just read 2069 ;^All other interrupts simply return2015 20702016 LDI @REAL_IBIT_POINTER, ARO^;get current pointer to I an 2071 NO:^RETId Q 20722017 LDI @REAL_QBIT_POINTER, AR1^;real data 2073 ;*******************************************************************2018 *******2019 STF R2,^*ARO++(1)%^;save real value I and Q in 2074 ;^This section clears memory chunks specified by ARO --> AR12020 STF R3,^*AR1++(1)% ;circular memory 2075 CLEAR:2021 2076 SUBI R6,^R72022 STI ARO,^@REAL_IBIT_POINTER^;update pointers to real dat 2077 LDIN 1,^R7a 2078 BN ERROR2023 STI AR1, @REAL_QBIT_POINTER 2079 LDI R6,^ARO2024 2080 LDI 0,^R62025 ldf @OLDI_INT,^r0 2081 RPTS R72026 ldf @OLDQ_INT,^rl 2082 STI R6,^*ARO++2027 CALL HARDDECODE ;decode current dibit 2083 REPS2028renceSTF R2,^@OLDI_INT ;save current dibit for refe 2084 ;**************************************************************************2029 STF R3,^@OLDQ_INT^ ;by the next future dibit 2085 ERROR:2030 2086 LDP DUAL2031 CALL FLAG_CHECKER ;checks if flag has been enc 2087 STI R7, @ERROR_NUMountered 2088 DEAD:^BR DEAD2032 2080 ;*******************************************************************2033 POP AR2 ******2034 POP AR1 2090 ;^This section clears memory chunks specified by ARO --> AR12035 POP ARO 2091 CLEARFLOAT:2036 popf r7 2092 SUBI R6,^E72037 POP R7 2093 LDIN 1, R72038 popf r6 2094 BN ERROR2039 POP R6 2095 LDI R6, ARO2040 popf r5 2096 LDF 0,^R62041 POP R5 2097 RPTS R72042 popf r4 2098 STF R6,^*ARO++2043 POP R4 2099 REPS2044 popf r3 21002045 POP R3 21012046 popf r2 21022047 POP R2 2103 .end2048 popf rl2049 POP R12050 popf r02051 POP RI20522053 pop rc2054 pop re2055 pop rs2056 pop iof2057 pop if2058 pop ie2059 pop bk2060 pop in2061 pop ir020622063 POP DP2064 POP ST2065 OR 2000h,^ST2066 RETI20672060 ;***************************************************************************Oct 7199301:57:01^VARSRCVR.ASM^Page 1 Oct 7 1993 01:57:01^VARSRCVR.ASM Page 21 VARS.asm^V1.00^JAN 93 60 TRANSMISSION^.set 809d07H2345-,^This file is used to set variables which are constantly•, used throughout the assembly section of the code.•,61626364Q_OFF_TRANS .setGET NEWFRAME_FLAG .setDIBET_COUNT^.set809D08H809D09H809D0AH6 .text 657 STACK_SIZE^.set^400h^;size of system stack 66 ;RCVR VARIABLES8 FP^.set^AR3 ;frame pointer 67 ADCHANA1 .word^804000h9 DELTA .set^2^;amount to jump in SIN table 68 ADCHANB1 .word^804001h10 INITIAL^.set^800h 69 ;SCALE .float^3.052e-511 NULL .set^0 70 SCALE .float^9.155553e-512 7113 DATALENGTH^.set^100h 7214 CODES^.set^0 73 REAL_IBIT_POINTER .word 1000h15 DUAL .set^30000h 74 REAL_QBIT POINTER .word 2000h16 ONCHIP .set^809C0Oh 75 FLAG_ADDRESS_TABLE .word 3000h17 76 TABLE_TOP .word 3000h18 DEINT_ROW^.set^16 77 TABLE BOTTOM .word 3Offh19 DEINT BLOCK .set^256^;symbols per block 78 FLAG_EOMP .word B1492H20 BLOCKS .set^2 79 MASK .word FFFFFFOOH21 80 MASK1 .WORD Offffffh22 K^.set^809c0Oh 81 OLDI .float23 POLY1 .set^809c01h 82 OLDQ .float24 POLY2 .set^809c02h 83 OLDI_INT .float25 CRC_CCITT^.word^69665 84 OLDQ_INT .float26 CRC 32 .word^4374732215^;problem with length 85 FLAG TO BE .word2728FLAG-^.set ^809c05h 86 START_FEAMs.word 2000h ;init to dummy value2930MENU MASK^.set^3hPACKET_MASK^.set^7h 87 STOP_FRAMEs.word 2fffh ;init to dummy value31 LENGTH MASK .set^3ffh 88 CURRENT FLAG .word 3000h ;init to table_top32 CRC _MASK^.word^01FFFEOH 89 CIRC_BOTTOM .word 1000h33 HIGE_MASK .word^Offff0000h 90 CIRC TOP .word 2000H34 91 TROUBLE .word 0100h35 CPC_ONE_ADDER1^.set^Oh 92 TROUBLE2 .word 00F0h36 CPC ONE ADDER2_^_ .set^lh 93 TROUBLE3 .word 0110h37 CPC_TWO_ADDER1 .set^2h 94 TROUBLE4 .word 0120h38 CPC_TWO_ADDER2^.set^3h 95 TROUBLE6 .word 0130h39 96 HD LENGTH .word40 97 DIEIT .word41 ADCHANA^.set^804000H 98 THRESHOLD .word 242 ADCHANB .set^804001H 99 CIRCLESS1 .word lfffh43 TROUBLEA^.WORD^31000H 100 RCVD SIGNAL_ENERGY .word 000fh44 101 SYMBOLS .word 0010h45 Q_START^.set^809c16H^;contains add of Q table 102 but .word 1000h46 Q_END .set^809c17H ;contains add of Q end tabl 103 buf2 .word 2000he 104 CURRENT START .WORD47 SERIALO^.set^809C18H 105 ;VITERBT DECODER TABLES & VARIABLES48 TABLE_ENC .set^809C49H^;CONTAINS POINTER TO TAB_ENC 10649 IBIT_POINTER^.set^809C4AH ;contains IBIT pointer 107 BETA .set^9.9e-150 QBIT_POINTER^.set^809C4BH^;contains Qbit pointer 108 ONE_MINUS_BETA .set^1.0e-251 109 BIT_MASK .word^80000000h52 110 BIT COUNT .word^-2753 SINE POINTER^.set^809D0OH 111 DEEP .word ^254 COSINE_POINTER^.set^809D01H 112 PATH .word^1655 POINT _COUNT^.set^809D02H 113 FORCE END ZEROS .word^056 'WORDDATA^.set^809003H 114 PUNC EOLUe4-N .word^157 CURRENT ADDRESS .set^809004H 115 ADDEE_ONE_PUNC .word^758 END_ADDEESS^.set^809D05H 116 ADDER_TWO PUNC .word^759 Q_OFFSET^.set^809006H 117 ADDER_1PRTME_PUNC .word^7Oct 7 1993 01:57:01 VARSRCVR.ASM Page, 3 Oct 7 1993 101:57:01 VARSRCVR.ASM Page 4118 ADDER_2PRIME_PUNC .word 7 178 .word 7 ;state 7119 SEQUENCES .word 0 179 .float 7.07e-1 ;I(s)120 180 .float -7.07e-1 ;4(s)121 .label TABLE_STATE 181 .word 14 ;s122 .word 0 ;state 0 182 .float -7.07e-1 ;I(s+1)123 .float -7.07e-1 ;I(s) 183 .float 7.07e-1 ;Q(s+1)124 .float -7.07e-1 ;4(s) 184 .word 15 ;s+1125 .word 0 ;s 185126 .float 7.07e-I ;I(s+1) 186 .word 8 ;state 8127 .float 7.07e-1 ;4(s+1) 187 .float 7.07e-1 ;I(s)128 .word 1 ;s+1 188 .float 7.07e-1 ;Q(s)129 189 .word 0 ;s130 .word 1 ;state I 190 .float -7.07e-1 ;I(s+1)131 .float 7.07e-1 ;I(s) 191 .float -7.07e-1 ;Q(s+1)132 .float -7.07e-1 ;4(s) 192 .word 1 ;s+1133 .word 2 ;s 193134 .float -7.07e-I ;I(s+1) 194 .word 9 ;state 9135 .float 7.07e-1 ;Q(s+1) 195 .float -7.07e-1 ;I(s)136 .word 3 ;s+1 196 .float 7.07e-1 ;4(s)137 197 .word 2 ;s138 .word 2 ;state 2 198 .float 7.07e-1 ;I(s+1)139 .float -7.07e-1 ;I(s) 199 .float -7.07e-1 ;Q(s+1)140 .float 7.07e-1 ;(2(s) 200 .word 3 ;s+1141 .word 4 ;s 201142 .float 7.07e-1 ;I(s+1) 202 .word 10 ;state 10143 .float -7.07e-1 ;4(s+1) 203 .float 7.07e-1 ;I(s)144 .word 5 ;s+1 204 .float -7.07e-1 ;4(s)145 205 .word 4 ;s146 .word 3 ;state 3 206 .float -7.07e-1 ;I(s+1)147 .float 7.07e-1 ;I(s) 207 .float 7.07e-1 ;Q(s+1)148 .float 7.07e-I ;Q(s) 208 .word 5 ;s+1149 .word 6 ;s 209150 .float -7.07e-1 ;I(s+1) 210 .word 11 ;state 11151 .float -7.07e-1 ;Q(s+1) 211 .float -7.07e-1 ;I(s)152 .word 7 ;s+1 212 .float -7.07e-1 ;4(s)153 213 .word 6 ;s154 .word 4 ;state 4 214 .float 7.07e-I ;I(s+1)155 .float -7.07e-1 ;I(s) 215 .float 7.07e-1 ;Q(s+1)156 .float 7.07e-1 ;4(s) 216 .word 7 ;s+1157 .word 8 ;s 217158 .float 7.07e-1 ;I(s+1) 218 .word 12 ;state 12159 .float -7.07e-I ;0(s+1) 219 .float 7.07e-I ;I(s)160 .word 9 ;s+1 220 .float -7.07e-1 ;4(s)161 221 .word 8 ;s162 .word 5 ;state 5 222 .float -7.07e-1 ;I(s+1)163 °float 7.07e-1 ;I(s) 223 .float 7.07e-1 ;Q(s+1)164 .float 7.07e-1 ;4(s) 224 .word 9 ;s+1165 .word 10 ;s 225166 .float -7.07e-1 ;I(5+1) 226 .word 13 ;state 13167 .float -7.07e-1 ;Q(s+1) 227 .float -7.07e-1 ;I(s)168 .word 11 ;s+1 228 .float -7.07e-1 ;4(s)169 229 .word 10 ;s170 .word 6 ;state 6 230 .float 7.07e-1 ;I(s+1)171 .float -7.07e-1 ;I(s) 231 .float 7.07e-1 ;Q(s+1)172 .float -7.07e-1 ;4(s) 232 .word 11 ;s+1173 .word 12 ;s 233174 .float 7.07e-I ;I(s+1) 234 .word 14 ;state 14175 .float 7.07e-1 ;4(s+1) 235 .float 7.07e-1 ;I(s)176 .word 13 ;s+1 236 .float 7.07e-1 ;4(s)177 237 .word 12 ;sOct 7 1993101:57:01 VARSRCVR.ASM Page 5 Oct 7 1993 01:57:01 VARSRCVR.ASM Page 6238 .float -7.07e-1 ;I(s+1) 298239 .float -7.07e-1 ;Q(s+1) 299 SURV8 .word 0 ;past history240 .word 13 ;s+1 300 .float 0 ;accumulated metric241 301 .word 0 ;last state242 .word 15 ;state 15 302 .word 0 ;next state243 .float -7.07e-1 ;I(s) 303244 .float 7.07e-1 ;4(s) 304245 .word 14 ;s 305 SURV9 .word 0 ;past history246 .float 7.07e-1 ;I(s+1) 306 .float 0 ;accumulated metric247 .float -7.07e-1 ;Q(s+1) 307 .word 0 ;last state248 .word 15 ;s+1 308 .word 0 ;next state249 309250 .label TABLE_SURV 310251 SURVO .word 0 ;past history 311 SURV10 .word 0 ;past history252 .float 0 ;accumulated metric 312 .float 0 ;accumulated metric253 .word 0 ;last state 313 .word 0 ;last state254 .word 0 ;next state 314 .word 0 ;next state255 315256 316257 SURV1 .word 0 ;past history 317 SURV11 .word 0 ;past history258 .float 0 ;accumulated metric 318 .float 0 ;accumulated metric259 .word 0 ;last state 319 .word 0 ;last state260 .word 0 ;next state 320 .word 0 ;next state261 321262 322263 SURV2 .word 0 ;past history 323 SURV12 .word 0 ;past history264 .float 0 ;accumulated metric 324 .float 0 ;accumulated metric265 .word 0 ;last state 325 .word 0 ;last state266 .word 0 ;next state 326 .word 0 ;next state267 327268 328269 SURV3 .word 0 ;past history 329 SURV13 .word 0 ;past history270 .float 0 ;accumulated metric 330 .float 0 ;accumulated metric271 .word 0 ;last state 331 .word 0 ;last state272 .word 0 ;next state 332 .word 0 ;next state273 333274 334275 SURV4 .word 0 ;past history 335 SURV14 .word 0 ;past history276 .float 0 ;accumulated metric 336 .float 0 ;accumulated metric277 .word 0 ;last state 337 .word 0 ;last state278 .word 0 ;next state 338 .word 0 ;next state279 339280 340281 SURV5 .word 0 ;past history 341 SURV15 .word 0 ;past history282 .float 0 ;accumulated metric 342 .float 0 ;accumulated metric283 .word 0 ;last state 343 .word 0 ;last state284 .word 0 ;next state 344 .word 0 ;next state285 345286 346287 SURV6 .word 0 ;past history 347 .label TABLE_NEXT_16288 .float 0 ;accumulated metric 348 NEXTSURVO .word 0 ;past history289 .word 0 ;last state 349 .float 0 ;accumulated metric290 .word 0 ;next state 350 .word 0 ;last state291 351292 352293 SURV7 .word 0 ;past history 353294 .float 0 ;accumulated metric 354 NEXTSURV1 .word 0 ;past history295 .word 0 ;last state 355 .float 0 ;accumulated metric296 .word 0 ;next state 356 .word 0 ;last state297 357Oct 7 1993 01:57:01 VARSRCVR.ASM Page 7 Oct 7 1993 01:57:01 VARSRCVR.ASM^Page 8358 418359 419360 NEXTSURV2 .word 0 ;past history 420 NEXTSURV12 .word 0^;past history361 .float 0 ;accumulated metric 421 .float 0 ;accumulated metric362 .word 0 ;last state 422 .word 0 ;last state363 423364 424365 425366 NEXTSURV3 .word 0 ;past history 426 NEXTSURV13 .word 0^;past history367 .float 0 ;accumulated metric 427 .float 0 ;accumulated metric368 .word 0 ;last state 428 .word 0 ;last state369 429370 430371 431372 NEXTSURV4 .word 0 ;past history 432 NEXTSURV14 .word 0^;past history373 .float 0 ;accumulated metric 433 .float 0 ;accumulated metric374 .word 0 ;last state 434 .word 0 ;last state375 435376 436377 437378 NEXTSURV5 .word 0 ;past history 438 NEXTSURV15 .word 0^;past history379 .float 0 ;accumulated metric 439 .float 0 ;accumulated metric380 .word 0 ;last state 440 .word 0 ;last state381 441382 442383 443384 NEXTSURV6 .word 0 ;past history 444 STATE TABLE .WORD TABLE_STATE385 .float 0 ;accumulated metric 445 SURV_TATE TABLE .WORD TABLE_SURV386 .word 0 ;last state 446 NEXT_16_SUiV .WORD TABLE_NEXT_16387 447388 448389 449390 NEXTSURV7 .word 0 ;past history 450391 .float 0 ;accumulated metric 451 ;^Memory Map of On chip memory $30000 - $3ffff392 .word 0 ;last state 452393 453 ;^v1.00 Feb 93394 454395 455 LENHEADO .set 30000h ;length of unencoded header396 NEXTSURV8 .word 0 ;past history 456 LENDATAO .set 30001h ;length of unencoded data397 .float 0 ;accumulated metric 457 LENHEADENC .set 30002h ;length of encoded header398 .word 0 ;last state 458 LENDATAENC .set 30003h ;length of encoded data399 459 PACKET_NUM .set 30004h ;packet number Ns400401 460 RATEg.set 30005h ;rate to be used for encodin402 NEXTSURV9 .word 0 ;past history 461 MENU OPTION .set 30006h ;menu option 1,^2,^or 3403 .float 0 ;accumulated metric 462 ERROi_NUM .set 30007h ;error number404 .word 0 ;last state 463 CONTROL WORD .set 30008h ;control info from protocol405406 464 LENHEADT,1s.set 3000ah ;bit length of P1 header bit407 465 LENHEADP2 .set 3000bh ;bit length of P2 header bit408 NEXTSURV10 .word 0 ;past history s409 .float 0 ;accumulated metric 466 LENDATA_WORD .set 3000ch ;word length of data chunk410 .word 0 ;last state 467 LENDATA BIT .set 3000dh ;# of left over bits from da411 ta chunk412413 468 TOTAL_WORDSe.set 3000eh ;word length of current fram414 NEXTSURV11 .word 0 ;past history 469 CODE .set 3000fh415 .float 0 ;accumulated metric 470 ;unused 30009-3000f416 .word 0 ;last state 471417 472 ; Careful^!!^these are pointers to specific memory locationsOct 7 1993 01:57:01 VARSRCVR.ASM^Page 9473474 .text475 VIRGIN_HEADER^.word 30010h ;start of virgin header476 TAIL1^.set 30012h ;used for header CRC calc477 VIRGIN_DATA^.word 30013h ;start of virgin data478 TAIL2 .set 30030h ;space to store data CRC479 HEADBUF1^.word 30031h ;header buffer 1480 HEADBUF2 .word 30033h ;header buffer 2481 HEADBUF3^.word 30035h ;header buffer 3482 HEADBUF4 .word 30039h ;header buffer 4483484 DATABUFP1^•word 3003dh ;data buffer 1485 DATABUFP2 .word 3005ch ;data buffer 2486 ;7bh--->7fh Unused487 ACK()^.set 3007Bh ;ACKO488 STROBE_RCVR^.set 3007ch489 STROBE_HOST .set 3007dh490491 FRAMEBUFP1^.word 30080h ;frame buffer 1492 FRAMEBUFP2 .word 300a0h ;frame buffer 2493494 FLAGOP1^.word 300c0h ;flag for frame 0,^P1495 PACKETOHARDP1^.word 300c1h496 PACKET1HARDP1^.word 300e2h497 BUFP1^.word 30100H498 BUFP2 .word 30500H499 CPC1I .word 30900H500 CPC1Q^.word 30b0OH501 CPC2I .word 30d0OH502 CPC2Q •word 33800H503 FREE1^•WORD 33100H504 FREE2 .WORD 33400H505506507


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