Open Collections

Chanawala, Parvez Anwar

University of British Columbia

Integrated circuits are stressed at temperature and voltage levels beyond their nominal ratings for long durations (~100s of hrs) during their development stage to study their reliability under nominal conditions. This is crucial to understand their operating lifetimes (typically in years) in their actual fields of use. The conventional HTOL test (an industry-standard reliability test to determine the intrinsic failure rate of ICs) is remarkably short as compared to the ICs' operating lifetime but still requires 1,000 hrs of elapsed test time. Future ICs' development may involve less time for such reliability tests due to the recent concerns being highlighted by most semiconductor manufacturers on reducing a product’s time to market. To partially answer such concerns, I am introducing a methodology that models the results of such reliability tests. To verify the feasibility of this method, several reliability experiments were conducted on Zynq-7000 FPGAs. To successfully perform those experiments, a reliability test platform was developed that can sustainably execute a high-temperature test for 1,000 hrs and requires minimum human intervention during the experiment. This platform is built on a commercial PYNQ-Z1 board that embeds the Zynq-7000 FPGA chip. To quantify the impact of thermal stress, several copies of a ring-oscillator-based test structure were implemented on the chip. Their free-running frequency was considered as a reference parameter to measure degradation. I leverage an existing transistor-level aging model to develop a circuit-level aging model that can mathematically describe a circuit parameter’s degradation as a function of time. This circuit-level aging model is then fitted onto the degradation data collected for a relatively shorter time frame to compute its parametric constants. Finally, with the known parametric constants, the model is used to determine how it fits the actual degradation data of the entire experiment. An analysis reveals that the first ~400 hrs of degradation data has sufficient information to forecast within a 3% accuracy margin the degree of degradation accomplished until the end of a 1,000-hour-long experiment. Subsequently, the analysis is applied to other test durations to study the effectiveness of this approach to other industry-standard reliability tests which are shorter than HTOL.

Text

2022-06-27

Attribution-NonCommercial-NoDerivatives 4.0 International

http://hdl.handle.net/2429/81828

Electrical and Computer Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by-nc-nd/4.0/