Open Collections

High-efficiency and low noise planar transformers for power converters : paired layers interleaving

University of British Columbia

Nowadays, many applications, such as consumer electronics, the automotive industry, and telecoms require high power density and low height power electronics converters. To implement slim power converters, Planar Transformers (PT) have emerged, featuring low height, low leakage inductance, and low thermal resistance. Despite these benefits, PTs have large parasitic capacitance, which degrades the performance of power converters. Capacitive effects in transformers are divided into two groups: inter-winding and intra-winding capacitance. Inter-winding capacitance generates large amounts of Common-Mode (CM) noise, creating serious Electromagnetic Interference (EMI) problems. Intra-winding capacitance affects the performance of the converter and can cause loss of voltage regulation in the LLC resonant converter. The inter-winding capacitance can be reduced by separating primary and secondary windings, at the cost of increased leakage inductance and AC resistance. On the other hand, interleaved structures minimize AC resistance and leakage inductance but significantly increase the inter-winding capacitance. Therefore, there is an unfortunate trade-off in the transformer design. In order to resolve this trade-off as well as problems resulting from PTs large parasitic capacitance, this dissertation develops new design methods that target the root cause of the problem. A detailed parasitic capacitance model is developed for PTs that relate the distributed capacitance of layers to the equivalent circuit of the transformer. Based on this model, the concept of paired layers is introduced that provides criteria to achieve zero CM noise generation in PTs. Paired layers can be used to design interleaved structures that not only have low AC resistance and leakage inductance but also have almost zero CM noise generation. Multiple examples are provided for different types of windings, different turn ratios, and different topologies to show the generality of the method. The proposed method is validated using analysis, Finite Element Method (FEM), and experiments. Besides the paired layers method, this dissertation studies the detrimental effects of PTs large intrawinding capacitance on light-load voltage regulation of LLC resonant converter. It is shown that large intrawinding capacitance results in loss of voltage regulation. To resolve this, six improved winding layouts with low intra-winding capacitance are presented to maintain voltage regulation even under no-load condition.

Text

2020-04-08

Attribution-NonCommercial-NoDerivatives 4.0 International

http://hdl.handle.net/2429/73948

Electrical and Computer Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by-nc-nd/4.0/