High-Efficiency and Low Noise Planar Transformers for Power Converters:Paired Layers InterleavingbyMohammad Ali Saket TokaldaniBSc., Amirkabir University of Technology, Iran, 2009MSc., Sharif University of Technology, Iran, 2011A THESIS SUBMITTED IN PARTIAL FULFILLMENTOF THE REQUIREMENTS FOR THE DEGREE OFDoctor of PhilosophyinTHE FACULTY OF GRADUATE AND POSTDOCTORAL STUDIES(Electrical and Computer Engineering)THE UNIVERSITY OF BRITISH COLUMBIA(Vancouver)April 2020© Mohammad Ali Saket Tokaldani, 2020The following individuals certify that they have read, and recommend to the Faculty of Graduate and Post-doctoral Studies for acceptance, the dissertation entitled:High-Efficiency and Low Noise Planar Transformers for Power Converters: Paired Layers Interleavingsubmitted by Mohammad Ali Saket Tokaldani in partial fulfillment of the requirements forthe degree of Doctor of Philosophyin Electrical and Computer EngineeringExamining Committee:Dr. Martin Ordonez, Professor, Electrical and Computer Engineering, UBCSupervisorDr. Wilson Eberle, Associate Professor, Electrical Engineering, UBC OkanaganSupervisory Committee MemberDr. Shahriar Mirabbasi, Professor, Electrical and Computer Engineering, UBCUniversity ExaminerDr. Bhushan Gopaluni, Professor, Chemical and Biological Engineering, UBCUniversity ExamineriiAbstractNowadays, many applications, such as consumer electronics, the automotive industry, and telecoms requirehigh power density and low height power electronics converters. To implement slim power converters, PlanarTransformers (PT) have emerged, featuring low height, low leakage inductance, and low thermal resistance.Despite these benefits, PTs have large parasitic capacitance, which degrades the performance of power con-verters. Capacitive effects in transformers are divided into two groups: inter-winding and intra-windingcapacitance. Inter-winding capacitance generates large amounts of Common-Mode (CM) noise, creating se-rious Electromagnetic Interference (EMI) problems. Intra-winding capacitance affects the performance ofthe converter and can cause loss of voltage regulation in the LLC resonant converter.The inter-winding capacitance can be reduced by separating primary and secondary windings, at the costof increased leakage inductance and AC resistance. On the other hand, interleaved structures minimize ACresistance and leakage inductance but significantly increase the inter-winding capacitance. Therefore, thereis an unfortunate trade-off in the transformer design. In order to resolve this trade-off as well as problemsresulting from PTs large parasitic capacitance, this dissertation develops new design methods that targetthe root cause of the problem. A detailed parasitic capacitance model is developed for PTs that relate thedistributed capacitance of layers to the equivalent circuit of the transformer. Based on this model, the conceptof paired layers is introduced that provides criteria to achieve zero CM noise generation in PTs. Paired layerscan be used to design interleaved structures that not only have low AC resistance and leakage inductance butalso have almost zero CM noise generation. Multiple examples are provided for different types of windings,different turn ratios, and different topologies to show the generality of the method. The proposed method isvalidated using analysis, Finite Element Method (FEM), and experiments.Besides the paired layers method, this dissertation studies the detrimental effects of PTs large intra-winding capacitance on light-load voltage regulation of LLC resonant converter. It is shown that large intra-winding capacitance results in loss of voltage regulation. To resolve this, six improved winding layouts withlow intra-winding capacitance are presented to maintain voltage regulation even under no-load condition.iiiLay SummaryThis dissertation proposes a new design method for planar transformers-paired layers interleaving-that elim-inates a fundamental trade-off in planar transformer design. Using the proposed method, it is possible todesign highly efficient transformers that have not only low conduction loss but also minimal noise emis-sion. These two advantages cannot be attained using traditional design methods, so planar transformerswere traditionally either efficient or low noise. The proposed method resolves this trade-off and introduces anew family of planar transformers that have it all. Planar transformers are the state-of-the-art high-frequencytransformers used at the heart of power electronics converters, which in turn are fundamental to the continuedprofitable growth of the telecommunications, automotive, aerospace, medical, military, and data processingindustries. The design of the planar transformers significantly affects the converters overall performance.Now, with the proposed method, the efficiency and performance of such converters can be considerablyimproved.ivPrefaceThis work is based on research performed at the Department of Electrical and Computer Engineering of theUniversity of British Columbia by Mohammad Ali Saket Tokaldani, under the supervision of Prof. MartinOrdonez. Chapter 1 contains modified portions of text from all the below-listed publications. Portionsof Chapters 2, 3, and 4 have been published in IEEE Transactions on Power Electronics, IEEE AppliedPower Electronics Conference & Exposition (APEC), and IEEE Energy Conversion Congress and Exposition(ECCE) [1–4]. It worth mentioning that the paired layers interleaving method won a Second Place PrizePaper Award for 2018 in IEEE Transactions on Power Electronics. The paper was nominated for this awardout of 935 papers published and some 13,000 papers that were submitted to the journal in 2018.• M. A. Saket, M. Ordonez and N. Shafiei, “Planar Transformers With Near-Zero Common-Mode Noisefor Flyback and Forward Converters,” IEEE Transactions on Power Electronics, vol. 33, no. 2, pp.1554-1571, Feb. 2018. (Second Place Winner for 2018 Prize Paper Awards: IEEE Transactionson Power Electronics)• M. A. Saket, M. Ordonez, M. Craciun, and C. Botting, “Improving Planar Transformers for LLCResonant Converters: Paired Layers Interleaving,” IEEE Transactions on Power Electronics, vol. 34,no. 12, pp. 11813-11832, Dec. 2019.• M. A. Saket, M. Ordonez and N. Shafiei, “Planar transformers with no common mode noise generationfor flyback and forward converters,” 2017 IEEE Applied Power Electronics Conference and Exposition(APEC), Tampa, FL, 2017, pp. 211-217.• M. A. Saket, M. Ordonez, M. Craciun, and C. Botting, “Common-Mode Noise Elimination in PlanarTransformers for LLC Resonant Converters,” 2018 IEEE Energy Conversion Congress and Exposition(ECCE), Portland, OR, 2018, pp. 6607-6612.I was the lead investigator of the above papers, developed the proposed concepts, built simulation models,vperformed experimental verifications, and wrote the manuscripts. Prof. Martin Ordonez was the supervisoryauthor on the above papers and was involved throughout the project and provided technical advice and editedmanuscripts. Dr. Navid Shafiei helped me in building the experimental test setup. Mr. Marian Craciun andMr. Chris Botting were industry partners (Delta-Q Technologies, Vancouver, BC) in this project and providedfeedback on the outcomes of the research.Portions of Chapter 5 have been published in IEEE Transactions on Power Electronics, IEEE AppliedPower Electronics Conference & Exposition (APEC), and IEEE Energy Conversion Congress and Exposition(ECCE) [5–7].• M. A. Saket, N. Shafiei and M. Ordonez “LLC Converters With Planar Transformers: Issues andMitigation,” IEEE Transactions on Power Electronics, vol. 32, no. 6, pp. 4524-4542, June 2017.• M. A. Saket, N. Shafiei and M. Ordonez, “Planar transformer winding technique for reduced capac-itance in LLC power converters,” 2016 IEEE Energy Conversion Congress and Exposition (ECCE),Milwaukee, WI, 2016, pp. 1-6.• M. A. Saket, N. Shafiei, M. Ordonez, M. Craciun, and C. Botting, ‘Low parasitics planar transformerfor LLC resonant battery chargers,” 2016 IEEE Applied Power Electronics Conference and Exposition(APEC), Long Beach, CA, 2016, pp. 854-858.As the first author and lead investigator of the above-mentioned publications, the author of this the-sis developed the proposed concepts, built simulation models, performed experimental tests and wrote themanuscripts. Prof. Martin Ordonez was the supervisory author on the above papers and was involvedthroughout the project by providing technical advice and editing manuscripts. Dr. Navid Shafiei helpedme in building the experimental test setup. Mr. Marian Craciun and Mr. Chris Botting were industry part-ners (Delta-Q Technologies, Vancouver, BC) in this project and provided feedback on the outcomes of theresearch.viTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiLay Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiGlossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiAcknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiiDedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2.1 Transformer CM Noise Minimization . . . . . . . . . . . . . . . . . . . . . . . . . 51.2.2 Winding Optimization for Reducing AC Resistance and Leakage Inductance . . . . 71.2.3 LLC Resonant Converter Light-Load Voltage Regulation With PTs . . . . . . . . . . 91.3 Contributions of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.4 Dissertation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Parasitic Capacitance Model for PTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15vii2.1 General Method for Modeling Equivalent Parasitic Capacitance . . . . . . . . . . . . . . . . 152.2 Case 1: Parasitic Capacitance Modeling for PTs With Single-Turn Layers . . . . . . . . . . 182.3 Case 2: Parasitic Capacitance Modeling of Symmetrical Overlapping . . . . . . . . . . . . . 232.4 Equivalent Capacitance Model Extraction Using FEA . . . . . . . . . . . . . . . . . . . . . 242.5 Equivalent Capacitance Model Extraction Using Measurement . . . . . . . . . . . . . . . . 262.6 Validation of the Proposed Parasitic Capacitance Model . . . . . . . . . . . . . . . . . . . . 272.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 The Concept of Paired Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.1 Eliminating CM Noise Due to the Direct Overlapping of Primary and Secondary Layers (IP−S) 353.2 Paired Turns in Topologies With a Quiet Point at One Terminal of Each Winding . . . . . . 403.2.1 Paired Turns in Flyback Converters . . . . . . . . . . . . . . . . . . . . . . . . . . 403.2.2 Paired Turns in Forward Converters . . . . . . . . . . . . . . . . . . . . . . . . . . 453.3 Paired Turns in Topologies With a Quiet Point at One Terminal of Primary . . . . . . . . . . 473.3.1 Paired Turns in Half-Bridge LLC Resonant Converters . . . . . . . . . . . . . . . . 483.4 Paired Turns in Topologies With a Quiet Point at the Middle of Both Primary and SecondaryWinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.4.1 Paired Turns in Push-Pull Converters . . . . . . . . . . . . . . . . . . . . . . . . . 513.5 Mathematical Proof for Paired Layers Interleaving . . . . . . . . . . . . . . . . . . . . . . 533.6 Eliminating CM Noise Generation Through the Core (IP−C and IP−C−S) . . . . . . . . . . . 583.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 Paired Layers Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614.1 Methods of Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614.1.1 Implementation Using PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624.1.2 Implementation Using a Combination of PCB and Copper Foil . . . . . . . . . . . . 654.1.3 Implementation Using Copper Foil . . . . . . . . . . . . . . . . . . . . . . . . . . 664.2 The Effect of Winding Arrangement on AC Resistance and Leakage Inductance . . . . . . . 674.3 Paired Layers Interleaving for Flyback and Forward Converters . . . . . . . . . . . . . . . . 684.3.1 Implementation of the Proposed Method for PTs With Small Numbers of Turns . . . 694.3.2 Implementation of the Proposed Method for PTs With a Large Number of Turns . . 714.3.3 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74viii4.4 Paired Layers Interleaving for LLC Resonant Converters . . . . . . . . . . . . . . . . . . . 784.4.1 Implementation of the Paired-Layers in Two-Winding LLC PTs . . . . . . . . . . . 794.4.2 Implementation of the Paired-Layers Method in Center-Tapped LLC PTs . . . . . . 824.4.3 Experimental Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 Low Parasitic Planar Transformers for LLC Resonant Converters . . . . . . . . . . . . . . . 935.1 Effect of Parasitic Capacitors on Light-Load Voltage Regulation of LLC Resonant Converter 945.2 Transformer Parasitic Element Extraction Using FEA . . . . . . . . . . . . . . . . . . . . . 975.2.1 Parasitic Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975.2.2 AC Resistance and Leakage Inductance Modeling . . . . . . . . . . . . . . . . . . . 995.3 Reduction of the Parasitic Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015.3.1 No Overlapping Winding Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065.3.2 Optimized Overlapping Winding Layout . . . . . . . . . . . . . . . . . . . . . . . . 1085.3.3 Alternating Winding Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105.3.4 Alternating & No Overlapping Winding Layout . . . . . . . . . . . . . . . . . . . . 1115.3.5 Zero Voltage Gradient Winding Layout . . . . . . . . . . . . . . . . . . . . . . . . 1115.3.6 Comparison of the Proposed Winding Layouts . . . . . . . . . . . . . . . . . . . . 1145.4 Arrangement Tradeoff Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236.1 Conclusions and Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236.1.1 Detailed Parasitic Capacitance Model of PTs . . . . . . . . . . . . . . . . . . . . . 1246.1.2 Concept of Paired Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246.1.3 Paired Layers Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256.1.4 Low Parasitic Planar Transformers for LLC Resonant Converters . . . . . . . . . . . 1256.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128ixList of TablesTable 2.1 Equations for transferring the distributed capacitances to the transformer terminals . . . . 23Table 2.2 Equations describing parasitic capacitances based on field analysis . . . . . . . . . . . . 26Table 3.1 Equations for transferring the distributed capacitances to the transformer terminals . . . . 56Table 4.1 Experimental Platform Prameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Table 4.2 Experimental Platform Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Table 5.1 Equations describing parasitic capacitances based on the field analysis . . . . . . . . . . 98Table 5.2 Parameters definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Table 5.3 The ratio of AC resistance to DC resistance of Alternating & No overlapping windinglayout in different structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Table 5.4 Parameters definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118xList of FiguresFigure 1.1 Different winding types in PTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Figure 1.2 a) Distributed parasitic capacitance in PTs. b) The transformer’s equivalent circuit. . . . 2Figure 1.3 CM noise propagation path in the Flyback Converter . . . . . . . . . . . . . . . . . . . 6Figure 1.4 a) Tradeoff between low AC resistance and low inter-winding capacitance. b) The pro-posed method resolves this tradeoff and achieves low AC resistance, low leakage induc-tance and minimum CM noise at the same time. . . . . . . . . . . . . . . . . . . . . . . 8Figure 1.5 (a) The LLC resonant converter considering parasitic elements of the transformer andone capacitor model of the transformer 1© (b) Transformer distorted no-load voltagedue to the stray capacitance 2©, (c) The no-load voltage gain characteristics of the con-verter with different transformers: Unfortunate increase of voltage 3© and deviation ofexperimental characteristics from FHA prediction with high stray capacitance 4© (d) CMnoise problem due to the inter-winding capacitance 5©, (e) A portion of the transformerconsisting of one primary PCB and two secondary PCBs (each PCB is a double-layerPCB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 2.1 a) Distributed parasitic capacitance in PTs. b) Transformer’s equivalent circuit. . . . . . 16Figure 2.2 a) A typical cross-section of winding arrangement in PTs. b) Physical Representation ofone overlapping of primary and secondary layers and c), parasitic capacitance model ofthis overlapping relative to the whole winding arrangement. Three voltages are definedto find the parasitic capacitance model. . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 2.3 Transferring parasitic capacitance model of a single overlapping to the terminals of thewinding. a) Parasitic capacitance model of an arbitrary overlapping, and b) the reflectedparasitic capacitance model to the terminals of windings. . . . . . . . . . . . . . . . . . 17Figure 2.4 Electrostatic behavior model of two overlapping layers belonging to different windings . 19xiFigure 2.5 Electrostatic behavior model of two overlapping layers that belong to the same windings:a) 3D model of the system along terminals and voltage directions, b) the overlapping lay-ers are straightened while the voltage gradient between overlapping layers is preserved,c) the electrostatic model of the system and d) the electrostatic model of the system ifthe overlapping layers are the successive turns of the same winding. . . . . . . . . . . . 21Figure 2.6 The relationship between distributed parasitic capacitance of layers and the six-capacitormodel of the transformer: a) an arbitrary interleaved structure of a PT, b) the parasiticcapacitance model of two overlapping layers belong to different windings relative tothe terminals of the transformer and c) transferring the same parasitic network to theterminals of the transformer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 2.7 a) A symmetrical overlapping of primary and secondary layers. b) Equivalent parasiticcapacitance model for a symmetrical overlapping. . . . . . . . . . . . . . . . . . . . . . 24Figure 2.8 Electrostatic behavior model of the transformer: (a) Six-capacitor model with three in-dependent voltages, (b), (c), and (d) the required numerical analysis to find six-capacitormodel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 2.9 Six different measurements to establish transformer’s six capacitance model (a) M1, (b)M2, (c) M3, (d) M4, (e) M5, and (f) M6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 2.10 a) A double-layer PCB with one turn on each side. b) Definition of static capacitancebetween top and bottom layers, C1. c) E-field distribution showing fringing of E-field. . 28Figure 2.11 Finding equivalent capacitance from point a to point b. a) Voltage distribution on turns,b) prototype of the PCB and c) frequency response of the prototype. . . . . . . . . . . . 28Figure 2.12 a) FEA model of PT under study and b) the prototype of PT. The turns ratio is 4:2. EachPCB has two turns and secondary PCBs are connected in parallel. . . . . . . . . . . . . 29Figure 2.13 Analytical derivation of parasitic capacitance. a) PT arrangement which has 7 differentoverlappings, b) distributed capacitance model of PT, c) distributed parasitic capacitanceof PT transferred to the terminals and d) six-capacitor model of PT. . . . . . . . . . . . 30Figure 2.14 Extracting parasitic capacitance model using FEA: a), b) and c) Simulations required tofind the model. d) Extracted six-capacitor model. . . . . . . . . . . . . . . . . . . . . . 31Figure 2.15 Experimental tests to extract the parasitic capacitance model: a) Frequency response ofone of the tests, b) measurements configurations and measured capacitance values andc) parasitic capacitance of PT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32xiiFigure 3.1 a) Transformer’s CM noise sources and their circulation path in the converter. IP−S, IP−C,IP−C−S, and IS−C are shown with 1©, 2©, 3©, and 4©, respectively. Traditional interleavingmethods only aim to reduce AC resistance and do not consider dvdt of overlapping layerswhich leads to very large levels of CM noise that imposes the use of large CM chokes. b)In the paired layers interleaving method, primary and secondary layers are designed in away that their overlapping does not generate CM noise. The structure of the transformeralso eliminates other CM noise sources and minimizes AC resistance. . . . . . . . . . . 34Figure 3.2 CM noise generation when primary and secondary layers overlap. a) Physical presenta-tion of the overlapping and, b) equivalent parasitic capacitance model which shows howCM noise is generated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Figure 3.3 a) Symmetrical overlapping and b) equivalent parasitic capacitance model of the over-lapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Figure 3.4 a) Overlapping of single-turn layers as an example of symmetrical overlapping and b)equivalent capacitance circuit of the overlapping. . . . . . . . . . . . . . . . . . . . . . 38Figure 3.5 a) Overlapping layers should have similar number of turns, similar layout, and similar dvdtat their ports to avoid CM noise generation. a) Physical presentation of these conditions,and b) equivalent parasitic capacitance model which shows that the total CM noise isequal to zero. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Figure 3.6 a) Topology of Flyback converter along with important challenges in designing powerConverters. Leakage inductance and transformer parasitic capacitance are major causesof CM noise. b) The main drawbacks of wire-wound transformer including high levelsof noise, high leakage inductance, high height, and high thermal resistance. c) Theproblems of traditional transformers can be resolved using the proposed PTs which notonly have very low leakage inductance but also generate almost zero levels of CM noise. 41Figure 3.7 a) Flyback converter configuration with pulsating voltages that change in the same direc-tions (right configuration) and b) Flyback converter configuration with pulsating voltagesthat change in opposite directions (wrong configuration) . . . . . . . . . . . . . . . . . 42Figure 3.8 Windings’ voltage distribution in a Flyback converter with the configuration of Fig. 3.7(b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Figure 3.9 a) Paired-turns in a step-down Flyback transformer and b) paired turns in a step upFlyback transformer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44xiiiFigure 3.10 Paired turns in an 8 : 4 Flyback PT using single-turn copper foils. a) Primary and sec-ondary layouts, b) paired layers of primary and secondary, and c) a simple structure forPT that satisfies the requirements of no CM noise generation. . . . . . . . . . . . . . . . 44Figure 3.11 a) Forward converter configuration with pulsating voltages that change in opposite di-rections (wrong configuration) and b) Forward converter configuration with pulsatingvoltages that change in the same direction (right configuration). . . . . . . . . . . . . . 46Figure 3.12 Windings’ voltage distribution in a Forward converter with configuration of Fig. 3.11 (b). 46Figure 3.13 Implementation of the method for an 8 : 4 Forward PT using single-turn copper foils.a) Primary and secondary layouts, b) paired layers of primary and secondary, and c) asimple structure for PT that satisfies the requirements of no CM noise generation. . . . . 47Figure 3.14 Half-bridge LLC resonant converter considering transformer’s parasitic elements. . . . 48Figure 3.15 Finding primary and secondary truns with similar dvdt in LLC PTs. a) When 2× n1 islarger than n2, and b) when 2×n1 is less than n2. . . . . . . . . . . . . . . . . . . . . . 49Figure 3.16 Implementation of the method for an 8 : 4 LLC PT using single-turn copper foils. a)Primary and secondary layouts, b) paired layers of primary and secondary, and c) asimple structure for PT that satisfies the requirements of no CM noise generation. . . . . 51Figure 3.17 Push-Pull converter along voltage waveforms at terminals of the transformer. . . . . . . 52Figure 3.18 Finding primary and secondary turns with similar dvdt in Push-Pull PTs. a) When n1 islarger than n2, and b) when n1 is less than n2. . . . . . . . . . . . . . . . . . . . . . . . 52Figure 3.19 Implementation of the method for an 8 : 4 Push-Pull PT using single-turn copper foils.a) Primary and secondary layouts, b) paired layers of primary and secondary, and c) asimple structure for PT that satisfies the requirements of no CM noise generation. . . . . 53Figure 3.20 Transformer CM Noise cancellation requirement for Flyback and Forward converters us-ing six capacitance model of the transformer. a) Swinging points change in the oppositedirections (wrong condition) and b) swinging points change in the same direction (rightcondition). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 3.21 The relationship between distributed parasitic capacitance of layers and the six-capacitormodel of the transformer: a) an arbitrary interleaved structure of a PT, b) the parasiticcapacitance model of two overlapping layers belong to different windings relative tothe terminals of the transformer and c) transferring the same parasitic network to theterminals of the transformer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56xivFigure 3.22 Eliminating CM noise generation through the core. a) IP−C and IP−C−S are generatedwhen primary layers overlap with the core. b) IP−C and IP−C−S are eliminated when sec-ondary layers are used at the top and bottom of the structure to avoids exposing primarywinding to the core. IS−C returns to its source without going to the primary and does notshow up on the input noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Figure 4.1 Disposition of how different layers of the PCB should be used to avoid CM noise gener-ation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Figure 4.2 PCB layouts for eliminating IP−S in LLC PTs. Layout for a) 16 : 16 turns ratio, and b)16 : 8 turns ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Figure 4.3 Analysis of DC resistance increase of windings caused by use of proposed method. Theproposed layout and its DC resistance for a) 16 : 16 turns ratio, b) 16 : 8 turns ratio, c)16 : 4 turns ratio and, d) 16 : 2 turns ratio. . . . . . . . . . . . . . . . . . . . . . . . . . 64Figure 4.4 Implementing the method using PCB for one winding and copper foil for another wind-ing. Winding layouts for eliminating IP−S in a 14 : 2 Flyback PT. . . . . . . . . . . . . 65Figure 4.5 Design methodology using a combination of PCBs and copper foils. Winding layoutsfor eliminating IP−S in a 36 : 2 Flyback PT . . . . . . . . . . . . . . . . . . . . . . . . 66Figure 4.6 Implementation of the method for an 8 : 4 Flyback PT using single-turn copper foils.a) Primary and secondary layouts, b) paired layers of primary and secondary, and c) asimple structure with no CM noise generation. . . . . . . . . . . . . . . . . . . . . . . 66Figure 4.7 Effect of winding arrangement on the value of m. a) Non-interleaved structure, b) par-tially interleaved structure, and c) fully interleaved structure. . . . . . . . . . . . . . . . 68Figure 4.8 Interleaved winding arrangement with low AC resistance/leakage inductance and no CMnoise generation for a 7 : 4 PT: a) Paired layers in the primary and secondary windings.b) and c) Examples of paired layers interleaved structures. . . . . . . . . . . . . . . . . 69Figure 4.9 An example of paired layers interleaved structure for a 6 : 3 PT. a) The proposed structureand b) a three dimensional (3D) model of the structure from both sides. . . . . . . . . . 71Figure 4.10 Implementation of the proposed method for PTs with large turn ratios: Implementationof the method for a) a 24 : 4 PT and b) a 36 : 3 PT. Both of these structures satisfythe requirement of no CM noise generation (as only paired layers overlap) and low ACresistance criteria (placing parallel layers in symmetrical positions from both ends). . . . 73xvFigure 4.11 a) The prototype of the proposed PT along with an equivalent wire-wound transformer.b) The circuit that is used to signify the CM currents caused by the inter-winding capac-itance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Figure 4.12 Waveforms of the circuit of Fig. 4.11 (b) with a) the wire-wound transformer and b) theproposed PT. The DC bus voltage and the switching frequency are equal to 100V and200kHz, respectively. Output voltage of the inverter (ch1), voltage across the resistorbetween the primary and secondary (ch2). . . . . . . . . . . . . . . . . . . . . . . . . . 75Figure 4.13 Waveforms of the Flyback converter with different transformers. Switch voltage (Ch1)and primary current (Ch2). Waveforms with a) the wire-wound transformer and b) withthe proposed PT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Figure 4.14 The spectrum of conducted mode noise of the Flyback with a) wire-wound transformer,and b) the proposed PT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Figure 4.15 a) Ch1 to Ch6 show the voltage distribution over the primary winding. b) Ch1 to Ch3and Ch4 to Ch6 are the voltage distribution over the first three turns of the primary andtheir corresponding pair on the secondary, respectively. . . . . . . . . . . . . . . . . . . 77Figure 4.16 Different structures for 16 : 8 turns ratio. The layouts of primary and secondary PCBswere shown in Fig. 4.2 (b). a) A non-interleaved structure with the minimum number ofPCBs, b) a structure with two parallel PCBs for each winding, c) a structure with fourparallel PCBs for each winding and, d) a structure with three parallel PCBs for eachwinding. The thickness of PCB traces is 3oz and the AC resistance results are reportedat 200kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Figure 4.17 Different paired-layers structures with no CM noise generation for an 8 : 4 transformer.The layout of primary and secondary PCBs were shown in Fig. 4.6 (a) . Implementationof the method with a) 12 layers, b) 20 layers and, c) 24 layers. Parallel layers have thesame name and are identified using small rectangles of the same color. The thickness oflayers are 0.25mm and the AC resistance results are reported at 200kHz. . . . . . . . . . 81Figure 4.18 a) The proposed primary and secondary layouts for a 16 : 2 : 2 center-tapped PT toeliminate CM noise. b) The implementation of the transformer with minimum numberof layers. c) An interleaved structure by using three parallel windings for both primaryand secondary windings. The thickness of PCB traces and secondary layers are 3oz and0.25mm, respectively, and the AC resistance results are reported at 200kHz. . . . . . . . 83xviFigure 4.19 a) First proposed primary and secondary layouts for 16 : 1 : 1 center-tapped PT. OnlyS(01) and P(01) are allowed to overlap in this scheme. b) An interleaved structure thathas a low AC resistance and no CM noise generation. The thickness of PCB traces andsecondary layers are 3oz and 0.25mm, respectively, and the AC resistance results arereported at 200kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Figure 4.20 a) Second proposed primary and secondary layouts for 16 : 1 : 1 center-tapped PT. Anadditional open-ended turn (called P(-1)) is added to the primary that creates a pair forS(02). In this scheme, S(01) can overlap with P(01) and S(02) can overlap with P(-1).b) An interleaved structure using these layouts that has symmetrical secondary wind-ings, low winding loss, and no CM noise generation. The thickness of PCB traces andsecondary layers are 3oz and 0.25mm, respectively, and the AC resistance results are at200kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Figure 4.21 A traditional 16 : 1 : 1 PT with the same structure as Fig. 4.20. (a) The layout of theprimary PCB and secondary copper foils. (b) The structure of the PT and current distri-bution in the layers. Comparing the loss results shows the use of the proposed methodincreases the total loss from 4.4W to 5W (which is the cost of using the method to elimi-nate the transformer’s CM noise). The thickness of PCB traces and secondary layers are3oz and 0.25mm, respectively, and the AC resistance results are reported at 200kHz. . . . 87Figure 4.22 a) Test setup for measuring conducted mode noise. b) Prototypes of transformers understudy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Figure 4.23 The comparison of the proposed PT with a traditional PT for 16 : 8 turns ratio. PCBlayouts, structure, current distribution in layers, and loss results for a) the traditional PTand b) the proposed PT. The thickness of PCB traces and secondary layers are 3oz and0.25mm, respectively, and frequency is 200kHz. . . . . . . . . . . . . . . . . . . . . . . 89Figure 4.24 Comparison of conducted noise of the LLC converter with a) the regular PT and b)the proposed PT. Using the proposed method significantly reduces the CM noise whichresults in smaller filter size and enhanced power density of the converter. . . . . . . . . 90Figure 4.25 CM noise of the converter with different connections. a) incorrect connection and b)correct connection. it is necessary that quiet point is connected to the first turn of theprimary winding, so overlapping layers of primary and secondary have a similar dvdt . . . 90Figure 5.1 a) Distributed parasitic capacitance in PTs. b) Transformer’s equivalent circuit. . . . . . 94xviiFigure 5.2 (a) The LLC resonant converter considering parasitic elements of the transformer andone capacitor model of the transformer 1© (b) Transformer distorted no-load voltagedue to the stray capacitance 2©, (c) The no-load voltage gain characteristics of the con-verter with different transformers: Unfortunate increase of voltage 3© and deviation ofexperimental characteristics from FHA prediction with high stray capacitance 4© (d) CMnoise problem due to the inter-winding capacitance 5©, (e) A portion of the transformerconsisting of one primary PCB and two secondary PCBs (each PCB is a double layerPCB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Figure 5.3 Electrostatic behavior model of the transformer: (a) Six-capacitor model with three in-dependent voltages, (b), (c), and (d) the required numerical analysis to extract the six-capacitor model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Figure 5.4 a) Six-Capacitor model of the transformer, b) the three capacitance model of the trans-former, c) the equivalent model of the transformer referred to the primary, and d) the onecapacitor model of the transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Figure 5.5 a) Transformer equivalent circuit neglecting the capacitive effects and b) Modified equiv-alent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Figure 5.6 a) The 3D model of a traditional 8 : 4 planar transformer with spiral winding and b)2D cross section of the transformer, showing the arrangement of the transformer. Eachprimary PCB has eight turns (four on each side), and each secondary PCB has four turns(two on each side). The primary PCBs are connected in parallel and the secondary PCBsalso are connected in parallel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Figure 5.7 Inter-winding energy associated with one intersection of primary and secondary. All ofthe primary turns have voltage equal to 1V , and all of the secondary turns have voltageequal to 0V . The energy distribution: a) with FR4 between PCBs 101pJ and b) with airbetween PCBs 25pJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Figure 5.8 Example of the frame that is used for air separation. a) 3D model and b) physical frame . 104Figure 5.9 a) Traditional spiral winding layout: The distributed capacitance due to overlappingtraces 1©, the distributed capacitance between adjacent turns at the same side 2© and b)simplified view of the overlapping traces . . . . . . . . . . . . . . . . . . . . . . . . . 104xviiiFigure 5.10 Intra-winding energy associated with two PCBs of the same winding placed next to eachother. The PCBs are connected in parallel and 1V is distributed linearly between theterminals of each PCB. Electrostatic energy distribution: a) with FR4 between PCBs99pJ and b) with air between PCBs 73pJ. . . . . . . . . . . . . . . . . . . . . . . . . . 106Figure 5.11 The proposed improved winding layouts to reduce the parasitic capacitances in LLCconverters: a) Traditional spiral, b) and c) No overlapping, d) Optimized overlapping,e) Alternating, f) Alternating & no overlapping and, g) Zero voltage gradient windinglayouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Figure 5.12 Intra-winding energy associated with one PCB of the proposed layouts. Each layoutconsist eight turns and 1V is distributed linearly between terminals of the layout: a)Traditional spiral, b) No overlapping, c) Optimized overlapping, d) Alternating, e) Al-ternating & no overlapping, and f) Zero voltage gradient winding layouts. . . . . . . . . 108Figure 5.13 Variations of DC resistance and intra-winding capacitance of Optimized overlappingwinding layout for a) even values of n and b) odd values of n . . . . . . . . . . . . . . . 109Figure 5.14 a) Alternating winding layout with terminals at the outer edges of PCB and b) Variationsof intra-winding capacitance of Alternating winding layout for even values of n . . . . . 111Figure 5.15 Zero voltage gradient transformer with the P1S1S1P2P2S2S2P1 structure. This figureshows that all overlapping traces of the same winding have zero voltage gradient. . . . . 113Figure 5.16 Parasitic elements comparison of different winding layouts: a) Intra-winding capacitanceand b) DC resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114Figure 5.17 Current density in different arrangements: a) PPPPSSSS (NI), b) SSPPPPSS, c) PSP-SPSPS (FI), and d) PSSPPSSP. It is evident that PSSPPSSP structure leads to an evendistribution of the current between layers and provides the best AC resistance . . . . . . 115Figure 5.18 The comparison of parasitic elements of an eight layers transformer with traditionalspiral windings in different structures. a) AC resistance and inter-winding capacitanceand, b) leakage inductance and primary parallel stray capacitance . . . . . . . . . . . . 116Figure 5.19 Inter-winding energy of one intersection of primary and secondary windings with a)Traditional and b) Alternating & No overlapping layouts. . . . . . . . . . . . . . . . . . 117Figure 5.20 Experimental prototypes: a) Transformers prototypes and b) LLC resonant converterplatform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118xixFigure 5.21 Parasitic values of the prototypes: a) frequency response, b) stray capacitance, c) inter-winding capacitance and d) AC resistance . . . . . . . . . . . . . . . . . . . . . . . . . 119Figure 5.22 Waveforms in the LLC resonant converter under full-loading condition with a) Tradi-tional FI and b) zero voltage gradient transformers. Inverter voltage (Ch1), primarycurrent (Ch2), transformer secondary voltage (Ch3), and transformer secondary current(Ch4). This figure shows that reducing the inter-winding capacitances has attenuatedCM noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Figure 5.23 Waveforms in the LLC resonant converter under no-load condition with a) traditionalFI and b) zero voltage gradient transformers. Inverter voltage (Ch1), primary current(Ch2), and transformer secondary voltage (Ch3). Reducing the stray capacitances hasimproved no-load voltage waveforms and successfully mitigated the light-load voltageregulation problem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Figure 5.24 Converter voltage gain characteristic with different transformers at a) no load, b) verylight load and, c) light load. The conventional PT has serious regulation issues for allcases and the proposed Zero voltage gradient layout solves this problem by achieving anextremely low capacitance. d) Full-load efficiency of the converter at resonant frequencywith different transformers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121xxGlossary3D three dimensionalCM Common-ModeDM Differential-ModeEMI Electromagnetic InterferenceFEA Finite Element AnalysisFHA First Harmonic ApproximationFI Fully InterleavedFEM Finite Element MethodLED Light-Emitting DiodeLISN Line Impedance Stabilization NetworksMMF Magneto-Motive ForceNI Non-InterleavedPT Planar TransformerSMPS Switch Mode Power SupplyxxiAcknowledgmentsForemost, I would like to express my sincere gratitude to my advisor, Prof. Martin Ordonez, for his con-tinuous support of my Ph.D. study and research and for his patience, motivation, enthusiasm, and immenseknowledge. I could not ask for a better advisor and mentor for my Ph.D. study.Special thanks go to my committee members, Prof. William Dunford, and Prof. Wilson Eberle, for theirfeedback on my research progress.I am grateful to the University of British Columbia (UBC), the Natural Sciences and Engineering ResearchCouncil (NSERC), and Delta-Q Technologies for supporting my research project. The development of the“paired layers interleaving” method would not be possible without the constructive assistance of Mr. MarianCraciun and Mr. Chris Botting from Delta-Q Technologies.Many thanks to my colleagues, especially Dr. Navid Shafiei, Mr. Abbas Arashadi, Dr. Ion Isbasescu, andDr. Mehdi Mohammadi for all the informative discussions and technical support they have shared with me.Last but not least, I thank my beautiful wife, Shirin, for all her unconditional love, inspiration, and support.xxiiTo my parents, Zeinab and AliakbarxxiiiChapter 1Introduction11.1 MotivationToday, high-efficiency power converters are fundamental to the continued profitable growth of the telecom-munications, automotive, aerospace, and data processing industries. Power converters are high-frequencypower conversion circuits used to convert a DC or AC input voltage to a DC or AC output voltage havinga larger or smaller magnitude, possibly with opposite polarity or with the isolation of the input and outputground references. At the heart of an isolated power converter is a high-frequency transformer that aidsthe voltage gain of the converter and also provides isolation between primary and secondary windings. Inorder to reduce the size of the transformer and increase the power density of the converter, a high switchingfrequency is employed.Nowadays, many modern applications require low profile power converters, such as consumer electronics,the automotive industry, and telecoms. Due to the height of traditional magnetic cores, the form factor ofpower converters is often plump and bulky. In order to implement slim converters for the above-mentionedapplications, the Planar Transformer (PT), which has an intrinsically lower height, can be used. Unliketraditional wire-wound transformers, windings in PTs can be made using Printed Circuit Boards (PCB),copper foils, or a combination of both. Figure 1.1 shows two types of PTs made using copper foils andPCBs.Despite the promising low profile and other advantages, PTs have extremely high parasitic capacitance,resulting in severe problems for power converters. In comparison to wire-wound transformers, PTs exhibitmuch larger parasitic capacitance due to the proximity of the planar layers and their significant overlap. In1Portions of this chapter have been modified from [1–7]1(a) (b)PrimarySecondaryFigure 1.1: Different winding types in PTs: a) single-turn copper foils and b) multi-turn spiral PCBs.particular, parasitic capacitances in the transformers are divided into two groups: inter-winding and intra-winding capacitance. Intra-winding capacitance originates from the capacitive coupling between layers ofthe same winding, while inter-winding capacitance is the result of capacitive coupling between layers ofdifferent windings (i.e., one from primary and another from secondary). These capacitive effects are dis-tributed, as indicated in Fig. 1.2 (a). The total effect of distributed parasitic capacitance can be modeledby six different capacitors in the transformer equivalent circuit, as shown in Fig. 1.2 (b). The distributedintra-winding capacitance of each winding can be modeled as a lumped capacitor between terminals of thatwinding. These capacitors are shown in purple in Fig. 1.2. On the other hand, the effect of distributedinter-winding capacitance can be modeled by four capacitors between primary and secondary windings ofthe transformer, which are shown in red in Fig. 1.2.Both intra- and inter-winding parasitic capacitance have detrimental effects on the performance of DC-DC converters. Transformers’ inter-winding capacitance is one of the main sources of Common-Mode (CM)RC LmLlk1Rac1 Llk2Rac2CIntra-p CIntra-sCInterCInterCInterCInter+-vsvp+-CIntra-pCInterCInterCIntra-sCIntra-p(b)(a)PrimarySecondaryFigure 1.2: a) Distributed parasitic capacitance in PTs. b) The transformer’s equivalent circuit.2noise in the converter. CM noise in the transformer originates from an undesired electrostatic couplingbetween primary and secondary windings. In PTs, whenever a layer of primary winding overlaps a layer ofthe secondary winding, due to the proximity and large overlapping area of planar layers, a large parasiticcapacitance is formed between overlapping layers. This parasitic capacitance is exposed to a large dvdt whenthe voltage of overlapping layers changes rapidly. This leads to the generation of pulsating currents (knownas CM noise) that circulate between primary and secondary windings through the earth and create EMIproblems [8]. Since the current in the parasitic capacitor is equal to C dvdt , the value ofdvdt between overlappinglayers is a major factor in the value of CM noise. While traditional interleaving methods reduce AC resistanceby interleaving primary and secondary layers [9, 10], these methods do not consider dvdt of overlapping layersand may lead to large dvdt coupling. Unfortunately, CM noise of traditional interleaved structures imposes theuse of large CM chokes to comply with EMI standards, reducing the converter’s power density. To date, nodesign method for PTs has been proposed that can achieve both low AC resistance and very low CM noisegeneration.On the other hand, the high intra-winding capacitance gives rise to a high charging current at the trans-former input, resulting in lower efficiency and increased peak voltage stress across secondary rectifyingdevices [11]. In addition to these problems, intra-winding capacitances bring unwanted regulation issuesin some DC-DC converters, such as LLC resonant converter with wide output voltage regulation. Voltageregulation is a critical specification in power converters in order to accommodate input voltage fluctuations(e.g., line regulation) or output voltage changes (e.g., battery chargers)[12, 13]. The high intra-winding ca-pacitance of the transformer severely distorts the light-load current and voltage waveforms of the converter,leading to unpredictable behavior of output voltage at the light-load [14].This work investigates new design methods for PTs that overcome the inherently large parasitic capac-itances, allowing PTs to be used more widely in modern power converters. To do so, this work proposesa detailed model for capacitive effects in PTs that links the distributed capacitance of Fig. 1.2 (a) to thelumped capacitors of Fig. 1.2 (b). This model gives a good insight into the nature of parasitic capacitanceand shows how winding arrangement affects the equivalent capacitance circuit of the transformer. Using thismodel, the concept of “Paired Layers” is introduced, which can be used to design high-efficiency PTs withalmost zero CM noise generation. This method finally eliminates the trade-off between parasitic elementsin the transformer and results in interleaved PTs that have a low AC resistance, low leakage inductance andalmost zero generation of CM noise at the same time. Since the design method depends on the transformer’svoltage distribution, different DC-DC topologies are considered and the proposed concept is used to develop3design methods for PTs used in these converters. Besides the paired layers interleaving method, this workalso proposes six different winding layouts with very low intra-winding capacitance. These winding layoutscan be used to resolve the light-load voltage regulation of LLC resonant converters with PTs. These layoutsalso can be used to design planar inductors with high self-resonant frequency, which is very desirable inhigh-frequency power converters.1.2 Literature ReviewDesign, optimization and modeling of planar magnetic components started in the early 1990s [15–17]. Inrecent years, with the rapid development of PCB technology, research into slim power converters with low-profile cores and PCB winding technologies has attracted widespread international attention [18–29]. Planarmagnetics have a number of advantages, which can be summarized as follows:1. Low Profile: Generally, the height of a planar magnetic component is 1/4 to 1/2 the height of itswire-wound counterpart [10]. This makes them an excellent choice for slim power converters.2. Repeatability and Parasitic Element Predictability: Windings in planar magnetics are usually madeusing PCB and/or copper foils. The simple automatic assembly process increases the repeatability andresults in consistent, predictable, and controllable parasitic parameters of the manufactured devices[30].3. Ease of Manufacture and Lower Cost: Advances in the PCB industry have not only reduced thecost of PCB manufacturing but also significantly increased the speed of PCB production. Nowadays,large quantities of PCB windings can be manufactured in a short amount of time and for competitiveprices. Besides, PCB windings can be assembled using automated machines, increasing the speed ofmanufacturing and reducing labor costs.4. Excellent Thermal Characteristics: Due to a higher ratio of surface area to volume, they exhibita low thermal resistance and efficiently conduct heat, which leads to a lower temperature rise of thecomponent. The ease of heat removal greatly increases the power density of the converter [31, 32].5. Modularity: Circuit components can be mounted on the same PCB winding, eliminating the need forextra connections.6. Flexibility in Winding Arrangement: Using PCBs for windings allows for sophisticated interleavingschemes, minimizing AC resistance and leakage inductance of windings.4Despite the above-mentioned benefits, PTs suffer from large parasitic capacitance due to the large over-lapping area of planar layers and their proximity. The work in [1] compares a 100W PT that has 700pFinter-winding capacitance with its wire-wound equivalent transformer which only has 10pF inter-windingcapacitance. The large parasitic capacitance of PTs significantly deteriorates the performance of the circuitand cannot be ignored. For instance, it creates serious EMI problems, reduces efficiency, and can resultin loss of voltage regulation in some topologies. However, most of the publications for planar transformerdesign address the reduction in leakage inductances and high-frequency winding losses, while winding ca-pacitances have rarely been considered effectively [10]. This dissertation targets problems that arise fromthe parasitic capacitance of PTs and proposes design methods for PTs that resolve these problems. Parasiticcapacitance in the transformers is divided into two groups: intra-winding capacitance and inter-winding ca-pacitance. Inter-winding capacitance is the major source of CM noise in the converter, which creates EMIissues. On the other hand, intra-winding capacitance affects the performance and efficiency of the converterand can result in loss of voltage regulation in certain topologies. These problems and their related literatureare discussed here.1.2.1 Transformer CM Noise MinimizationEvery commercial power supply has to pass EMI tests before going to the market. This means that theconverter’s level of conducted noise (which consists of Differential-Mode (DM) and Common-Mode (CM)noise) should be below standard limits. It is always a challenge to ensure that the EMI of a converter meetsEMI standards [33–36]. Both CM and DM filters are used at the EMI filter stage to suppress noise. ReducingCM noise emission can greatly reduce the size of required CM chokes and enhance the converter’s powerdensity. In most cases, CM noise current is mainly caused by the displacement current within the inter-winding parasitic capacitance of transformers and the parasitic capacitance between semiconductor switchesand the ground. The CM noise paths in a Flyback converter are shown in Fig. 1.3. The CM noise currentflows into the ground through the parasitic capacitance between the high dvdt nodes, such as the drain of theMOSFET. In Fig. 1.3, the MOSFET’s drain-to-heatsink parasitic capacitance is between the ground and ahigh dvdt point. Therefore, this parasitic capacitance generates iCM−S flowing back to the converter via LineImpedance Stabilization Networks (LISN). This figure shows that the transformer’s parasitic capacitance isanother major source of CM noise. As shown in this figure, the transformer’s CM noise iCM−T flows backto the converter via LISNs at the primary side, increasing the total noise of the converter. Figure 1.3 alsoshows that secondary side diode’s anode-to-heatsink parasitic capacitance generates CM noise current of5icm-24C13C24C14C23 icm-23icm-14icm-13PEiCM-TiCM-SiCM-S i+ CM-TiCM iCMiCM-DiCM-DiCM-DLISNHigh dv/dtPointHighdv/dtPointEMIReceiver+-50Ω 50ΩConducted Noise of the ConverterdbµVf150 kHz 30 MHzFigure 1.3: CM noise propagation path in Flyback Converter.iCM−D. However, since this current does not return through LISNs, it does not affect the converter’s CMnoise. In order to comply with the standards, both iCM−S and iCM−T must be minimized. Different methodsfor attenuating iCM−S can be found in [37–40]. The focus of this work, however, is on attenuating iCM−T .Since the structure of the transformer determines CM noise levels, this topic has been considered in nu-merous works, and interesting methods have been proposed to mitigate CM noise. Regarding the transformerstructure, mitigation methods can be classified into two groups. In the first group, additional layers are addedto the transformer structure to either shunt away or inject anti-phase displacement currents to reduce noise.These methods are applicable on both wire-wound transformers and PTs and include using Faraday shields[8, 41, 42], introducing out of phase displacement currents [43–45] and integrating a Y-cap in the structureof the transformer [46]. However, since extra layers (in addition to the primary and secondary) are required,the transformer fill factor is reduced, which increases the resistance of the windings. In addition, conduc-tion loss may increase due to eddy currents in these additional, auxiliary windings. As well, the additionallayers (Faraday shields or anti-phase windings) prevent the implementation of interleaved structures thatare required to minimize AC resistance (there are multiple overlaps of primary and secondary layers in in-terleaved structures). The second group of methods targets the source of CM noise and mitigates the CMnoise without adding extra layers. Reducing the inter-winding capacitance [11] is the most straightforwardmethod of reducing the CM noise and can be done in both wire-wound transformers and PTs. This can bedone using a non-interleaved structure (in which primary and secondary are separated and only have oneoverlapping area) or avoiding the overlap between the primary and secondary windings. However, doing this6dramatically increases the AC resistance and therefore conduction losses. Recently, the winding cancellationmethod for wire-wound transformers has been presented in a number of papers [47–52]. This method mini-mizes the amount of CM noise generated not by reducing the inter-winding capacitances but by reducing thedvdt to which these capacitances are exposed. Therefore, it does not produce the side effects of other methods,such as higher winding resistance or extra eddy current loss. As the problem of parasitic capacitance ismore significant with PTs, having a similar method that can attenuate the CM noise without requiring extracomponents or leading to additional loss and increased complexity is highly beneficial. Therefore, there isa significant opportunity to develop a winding cancellation technique for PTs to achieve minimal CM noisegeneration.This dissertation resolves the large CM noise problem of PTs by proposing the concept of paired layers.According to this concept, layer layout and winding arrangement can be designed in a way that results in PTswith almost zero CM noise generation. In comparison with methods reported in the literature, the proposedconcept does not separate primary and secondary windings and can achieve zero CM noise generation evenin the highly interleaved structures.1.2.2 Winding Optimization for Reducing AC Resistance and Leakage InductanceSimilar to the conventional magnetic structures, the demand for high-frequency switching increases windinglosses due to the skin and the proximity effects, particularly at frequencies above 100 kHz [9]. AC resis-tance effects due to sinusoidal currents were treated by Bennett and Larson [53] and this work was tailoredspecifically for transformers by Dowell [54]. Dowell’s equations were later analyzed, rearranged, and im-proved for different situations [54–59]. The work in [60] presents the optimum layer thickness of conductorsto minimize winding loss. The effect of winding arrangement on AC resistance and leakage inductance isdiscussed in numerous works [9, 60–64]. In most papers about optimizing PTs, the main purpose is to re-duce leakage inductances, and they do this by proposing highly interleaved structures that minimize leakagefluxes. However, stray capacitances of these arrangements have not seriously been considered. As discussedbefore, interleaved structures have multiple overlaps of primary and secondary layers and so exhibit a verylarge inter-winding capacitance, generating a large amount of CM noise and consequently contributing toEMI problems [65].From the above discussion, it is can be concluded that the reported methods in the literature minimize ACresistance and leakage inductance at the expense of large CM noise. This trade-off is presented in Fig. 1.4(a). On the left side, an interleaved structure is shown that has a low AC resistance and leakage inductance.7(a)(b) Low AC Resistance Low Leakage InductanceVery Large Parasitic Capacitance(Causing Significant Levels of CM noise)Transformer Arrangement Trade-offProposed Solution: Paired Layers InterleavingInterleaved Structure Using The Concept of Paired LayersPaired LayersInterleaved Structures Non-Interleaved Structure Large AC Resistance Large Leakage InductanceSmall Parasitic Capacitance(Still Causing Some Levels of CM noise) Low AC Resistance Low Leakage InductanceExtremely Low levels of CM noise}}}}}}Conducted Noise of the Converter (very large)dbµVf150 kHz 30 MHz fConducted Noise of the Converter (Medium)150 kHz 30 MHzdbµVConducted Noise of the Converter (Very Low)fdbµV150 kHz 30 MHzFigure 1.4: a) The tradeoff between low AC resistance and low inter-winding capacitance. b) Theproposed method resolves this tradeoff and achieves low AC resistance, low leakage inductanceand minimal CM noise at the same time.However, since it has multiple overlapping of the primary and secondary windings, it has a large parasiticcapacitance which generates high amounts of CM noise. On the right side, a non-interleaved structure thatseparates primary and secondary windings is shown. Since there is only one overlapping between primaryand secondary windings, the value of inter-winding capacitance (and so generated CM noise) is reduced.However, this structure has the side effect of having large AC resistance and leakage inductance. No designmethod has been reported in the literature that resolves this trade-off and achieves both low AC resistanceand very low CM noise generation.This has been considered in this dissertation, and interleaving methods have been combined with theproposed concept of “paired layers” to achieve PTs that not only have minimal AC resistance and leakageinductance but also generate almost zero CM noise. According to the concept of paired layers, there arelayers in the primary and secondary that have a similar dv/dt and it will be shown that overlapping of such8layers does not generate CM noise. These layers can be used to design highly interleaved structures that notonly have a very low AC resistance and leakage inductance, but also generate almost zero CM noise, althoughthey have a very large inter-winding capacitance. The key is to use these paired layers at the intersectionsof primary and secondary in the transformer structure. As shown in Fig. 1.4 (b), paired layers interleavingfinally eliminates the trade-off between low AC resistance and low CM noise and gives the designer a toolto achieve both.1.2.3 LLC Resonant Converter Light-Load Voltage Regulation With PTsIn order to reduce switching loss and to improve EMI, soft switching techniques have emerged. Soft switch-ing also enables working at higher frequencies which reduces the size of magnetic components [66–72].Among different soft-switched converters, the LLC resonant converter offers many advantages, includinghigh part-load efficiency, no-load voltage regulation, wide gain range over narrow frequency variation, in-herent short circuit capability, and good cross regulation [73]. In a high-frequency LLC converter, magneticcomponents are often the bulkiest parts, and they determine the overall height of the converter [74]. In orderto implement slim profile LLC converters, PTs can be used since they feature low height, reproducibility,lower leakage inductance, and low thermal resistance [9, 75]. Despite the promising low profile and man-ufacturing advantages of PTs, their inherent high parasitic capacitances result in severe problems for LLCconverters. The paired layers method introduced in the previous parts minimizes CM noise by making dv/dtof inter-winding parasitic capacitors equal to zero. As mentioned before, intra-winding capacitance is an-other type of parasitic capacitance that can interrupt the dynamic behavior of the LLC resonant converter.Unfortunately, the paired layers method only targets inter-winding capacitance and does not resolve issuesdue to intra-winding capacitance. To solve this issue, a different approach from the paired layers methodwas employed which tries to minimize the value of parasitic capacitances. To do so, this part of the workproposes new winding layouts and structures to reduce both intra-winding and inter-winding capacitance.Figure 1.5 (a) shows a LLC resonant converter schematic and includes the parasitic elements of thetransformer (leakage inductances, winding resistances, and parasitic capacitances). Figures 1.5 (b), (c),(d) and (e) present the problems that arise from the transformer’s parasitic capacitances. As discussed,the high inter-winding capacitance between primary and secondary generates CM noise and contributesto EMI issues. A large intra-winding capacitance gives rise to a high charging current at the transformerinput, resulting in lower efficiency and increased peak voltage stress across secondary rectifying devices.In addition to these problems, parasitic capacitances bring unwanted regulation issues for LLC resonant9Full-LoadtiLS15(c) (e)Light-LoadtVTrans2S2S1Vfc RC LmLlk1Rac1 Llk2Rac2C12 C34C14LsCC13C23C24D8D6D5D7Cip isvovp+-vs+-(b) (d)(a)0 1 2Normalized Frequency3f r,scf r,ocVoltage Gain02314Non-Operating AreaZCS RegionCapacitanceCapacitanceFHA Exp43..................iCM iCM iCM iCMiCMiCMiCMiCMSecondaryPCBInsulationbetween primaryand secondary PCBsInsulationbetween primaryand secondary PCBsLmCstraylkL1FR4FR4FR4}PrimaryPCB}SecondaryPCB}Copper TracesTransformerFigure 1.5: (a) The LLC resonant converter considering parasitic elements of the transformer and onecapacitor model of the transformer 1© (b) Transformer distorted no-load voltage due to the straycapacitance 2©, (c) The no-load voltage gain characteristics of the converter with different trans-formers: Unfortunate increase of voltage 3© and deviation of experimental characteristics fromFHA prediction with high stray capacitance 4© (d) CM noise problem due to the inter-winding ca-pacitance 5©, (e) A portion of the transformer consisting of one primary PCB and two secondaryPCBs (each PCB is a double-layer PCB).converters with wide output regulation. Voltage regulation is a critical specification in power convertersto accommodate input voltage fluctuations (e.g., line regulation) or output voltage changes (e.g., batterychargers). The large parasitic capacitance of a transformer severely distorts the light-load current and voltagewaveforms of the converter. This leads to the erratic behavior of output voltage which cannot be seen by10First Harmonic Approximation (FHA), which is the conventional approach to model this type of converter.During the last few years, interesting research has been done to design high efficiency PT, for LLCresonant converters [9, 11, 76–86]. Most of these papers have focused on the AC resistance and leakageinductance, so the impact of transformer parasitic capacitance on the LLC performance is not covered. Inparticular, it is interesting to note that the root cause of the LLC regulation problem using PTs has not beenaddressed in detail in the past. Since the voltage regulation problem of the LLC resonant converter alsocan be caused by rectifier diode junction capacitance, [14, 87, 88] have developed methods to address thisproblem. The work in [87] developed a higher-order topology that can mitigate the effect of diode junctioncapacitances for different modes of operation. Research in [14] suggests that adding a dummy load can solvethe problem for small values of diode junction capacitance. The work in [88] presents another mitigationstrategy by adding a capacitor to the primary side. Although prior methods are successful in resolving theregulation issue due to the diode junction capacitance, their efficacy is limited to the values in the range ofdiode junction capacitance. Since the parasitic capacitance of PTs is much larger, preceding methods cannotbe used to resolve the regulation problem. For instance, the work in [9] reports stray capacitances in the orderof a few Nano Farads for conventional PTs, which results in serious regulation problems in the LLC resonantconverters. Although many papers have discussed different aspects of using PTs in LLC resonant converter,a paper that resolves the light-loading voltage regulation problem along with high full-load efficiency still ismissing in the literature.As will be discussed in chapter 5, in order to have a high efficiency LLC converter with wide outputregulation, both parasitic capacitance and AC resistance should be minimized. The strategies proposedin chapter 5 provide solutions for light-loading regulation while ensuring high efficiency under full-loadcondition. These strategies include proposing winding layouts that achieve extremely low intra-windingcapacitance (to solve light-loading voltage regulation problem) and winding arrangements that minimize ACresistance and winding loss.1.3 Contributions of the WorkIn order to eliminate the trade-off in PT design and also to address other problems associated with PTs’large parasitic capacitance, this dissertation targets the root cause of the problem and proposes new designmethods for PTs. The main contributions of this work are the following:1. Detailed parasitic capacitance model of PTs: The first step of this work involves developing a de-tailed parasitic capacitance model for PTs, which is presented in chapter 2. This parasitic capacitance11model starts from modeling the overlapping of two planar layers, which is then extended to the wholewinding. As mentioned before, parasitic capacitance has a distributed nature and the six-capacitormodel of the transformer is an equivalent model. The developed parasitic capacitance model relatesthe distributed capacitance of each overlapping to the six-capacitor model, giving a deep insight intohow the value of each capacitor in the model depends on the arrangement of the winding. The modelis extracted analytically and is verified using Finite Element Analysis (FEA)2 and experimental mea-surements. This model provides a theoretical basis for the proposed concepts in chapters 3 and 4.2. Paired-layers interleaving. In order to resolve the trade-off in PT design and minimize AC resistance,leakage inductance, and CM noise at the same time, the concept of “paired layers” is proposed inthis work. This concept resolves the trade-off between EMI problems (inter-winding capacitance) andhigh-efficiency performance (low AC resistance and leakage inductance). The concept of paired layersmatches layers with similar dvdt and shows which layers can overlap without generating CM noise.This concept enables the designer to use interleaved structures and not to worry about CM noise, asthe layers and winding arrangement are designed in such a way that the overlapping of primary andsecondary layers does not generate CM noise. The method is verified using analysis, and experimentalresults prove the strength of the method in achieving low CM noise and high-efficiency PTs. Sincethe mechanism of CM noise generation in the transformer depends on the topology, different typesof power converters are divided into three groups and the method is developed for each group. Manyexamples are provided for different topologies, turns ratios, and different types of planar windingsthroughout chapters 3 and 4 to make the method easy to understand.3. PCB winding layout with low intra-winding capacitance: The high intra-winding capacitance ofregular multi-turn PCB winding layouts causes a number of problems in DC-DC converters. If usedfor planar inductors, large intra-winding capacitance reduces the self-resonant frequency of the induc-tor, limiting its operating frequency range. If used as the planar transformer, the high intra-windingcapacitance gives rise to a high charging current at the transformer input, resulting in lower efficiencyand increased peak voltage stress across secondary rectifying devices [11]. In addition, PTs’ intra-winding capacitance brings unwanted regulation issues for LLC resonant converters with wide outputregulation. To solve these problems, this work proposes novel winding layouts that have a significantlylower intra-winding capacitance. Six new winding layouts are proposed and it is shown that the use of2MAXWELL software from ANSYS was used for the simulations.12these layouts resolves the above-mentioned problems.1.4 Dissertation OutlineIn Chapter 2, a detailed parasitic capacitance model of PTs is developed to gain insight into the factors thatinfluence the parasitic capacitance of PTs. The model starts with the analysis of overlapping between twoplanar layers and is then extended to the full transformer. This model shows how lumped parasitic capacitorsof the transformer’s equivalent circuit are related to the distributed capacitance of overlapping layers andhow the value of each lumped capacitance can be tuned by changing the winding arrangement. Besides,numerical analyses required to extract the equivalent parasitic capacitance are proposed in this chapter. Theproposed model is verified using FEA and experimental measurements. This model provides a theoreticalbasis for the methods proposed throughout the dissertation.In chapter 3, the concept of paired layers is proposed as a means to develop design methods that result inPTs with almost zero CM noise generation. First, the mechanism of CM noise generation when a layer ofprimary overlaps a layer of secondary is modeled and criteria to make the net CM noise of this overlappingequal to zero is found. The criteria set some rules on the layout of planar layers and also on which layers ofprimary and secondary are allowed to overlap (these layers are called paired layers). This concept matcheslayers with similar dvdt and shows which layers can overlap without generating CM noise. Besides, methodsare proposed to avoid CM noise generation through the core. Since the topology of the converter is animportant factor contributing to the transformer’s CM noise, different DC-DC topologies are divided intothree groups and paired layers are found for each topology. Besides, the layout requirement of overlappinglayers is discussed in this section. The proposed concept is also verified using the proposed capacitancemodel of chapter 2. It is shown that incorporating the paired layers concept in the winding arrangementresults in an equivalent circuit for PT that has net CM noise equal to zero.In Chapter 4, the concept of paired layers is combined with interleaving methods to resolve the trade-offin PT design. The resulting method is called paired layers interleaving which allows us to design PTs that notonly have a very low AC resistance and leakage inductance, but also have a near-zero CM noise generation.Different types of planar windings are considered and it is shown how the method can be used with almostany type of planar winding. The three groups of topologies are considered in this chapter and examples areprovided for each group to make the method easy to understand and implement.In Chapter 5, the problem of LLC resonant converters with conventional PTs is discussed, and it isshown that the large intra-winding capacitance of conventional PTs results in loss of voltage regulation in13LLC resonant converters under light-loading condition. The proposed paired layers method only targets theinter-winding capacitance and has no effect on intra-winding capacitance. To resolve the issue of intra-winding capacitance, novel PCB winding layouts are proposed that significantly reduce the intra-windingcapacitance of the transformer and resolve the issue of voltage regulation in LLC resonant converters. Theproposed winding layouts can also be used for planar inductors and result in inductors with a wide operatingfrequency range, as the self-resonant frequency of the resulting PTs is much higher than that of the regularplanar inductors. It should be mentioned that the approach in this chapter is different from the paired layersmethod and the proposed methods reduce the adverse effects of parasitic capacitance by directly reducingthe value of parasitic capacitance.Chapter 6 contains the relevant conclusions, contributions, and planned areas of future work. The workcontributes significantly to the field of planar magnetics by proposing the paired layers interleaving methodand also low intra-winding spiral PCB winding layouts. The contributions are highlighted in seven relevantpublications in IEEE Transactions journals and international conference papers.14Chapter 2Parasitic Capacitance Model for PTs PTs1Parasitic capacitance in transformers can be divided into two groups: inter-winding and intra-winding ca-pacitance. Intra-winding capacitance originates from the capacitive coupling between layers of the samewinding, while inter-winding capacitance is the result of capacitive coupling between layers of differentwindings (i.e., one from primary and another from secondary). These parasitic capacitances are distributed,as indicated in Fig. 2.1 (a). The total effect of distributed parasitic capacitance in the lower frequency rangecan be modeled by six lumped capacitors in the transformer equivalent circuit, as shown in Fig. 2.1 (b).Such a model proved to be reliable up till one and, even, two decades beyond ( fo), that is the lower parallelresonance frequency of the transformer which appears on the Bode plots [89]. The distributed intra-windingcapacitance of each winding can be modeled as a lumped capacitor between terminals of that winding. Thesecapacitors are shown in purple in Fig. 2.1 (b). On the other hand, the effect of distributed inter-winding ca-pacitance can be modeled by four capacitors between the primary and secondary ports of the transformer,shown in red in Fig. 2.1 (b).The objective of this chapter is to develop a general equivalent parasitic capacitance model that relates thedistributed capacitance of individual layers in Fig. 2.1 (a) to the six lumped capacitors of Fig. 2.1 (b). Thismodel will be used in the next chapter to analytically validate the concept of paired layers which achievesvirtually zero CM noise generation in PTs.2.1 General Method for Modeling Equivalent Parasitic CapacitanceFigure 2.2 (a) shows a typical cross section of a PT. As shown in this figure, there are multiple overlapsbetween layers which contribute to the equivalent parasitic capacitance model of Fig. 2.1 (b). Fig. 2.21Portions of this chapter have been published in [1–4]15RC LmLlk1Rac1 Llk2Rac2CIntra-p CIntra-sCInterCInterCInterCInter+-vsvp+-CIntra-pCInterCInterCIntra-sCIntra-p(b)(a)PrimarySecondaryFigure 2.1: a) Distributed parasitic capacitance in PTs. b) Transformer’s equivalent circuit.(b) shows one of these intersections. This figure shows a typical condition that occurs when two layers ofdifferent windings overlap (i.e. one from the primary and the other from the secondary). As shown in Fig.2.2 (b), depending on the turns ratio, overlapping layers can have a different number of turns. These layersare part of primary or secondary windings. Figure 2.2 (c) shows how these layers (turns) are related to theprimary and secondary windings. In this example, four turns of the primary are exposed to two turns of thesecondary. The electrostatic behavior of this overlapping can be modeled by six capacitors, as shown in Fig.2.2 (c).A similar condition happens for every overlapping, and six capacitors are needed to model the behavior ofeach overlapping. If the overlapping layers belong to the same winding, this model can be simplified into onecapacitor, as will be shown in the next section. While the transformer is a two-port system from the magneto-static perspective, the inter-winding capacitance between primary and secondary winding provides a pathfrom primary to secondary, making the transformer a three-port system from the electrostatic standpointa1Vc2V(b)(a) (c)b1Vd2Va1V1V2VoVb1Vc2VacCadCbcCbdCabCcdCd2V+-+-+-PrimarySecondaryFigure 2.2: a) A typical cross-section of winding arrangement in PTs. b) Physical Representation ofone overlapping of primary and secondary layers and c), parasitic capacitance model of this over-lapping relative to the whole winding arrangement. Three voltages are defined to find the parasiticcapacitance model.16[90]. For a three-port system, three independent voltages are needed to model the electrostatic behavior ofthe system. Without losing the generality, these three independent voltages are selected as in Fig. 2.2 (c) andare defined as V1, V2, and Vo. Vo is the DC offset voltage between windings. Using this voltage definition,the voltage across each capacitor of Fig. 2.2 (c) can be found. In order to find individual values of Cab, Cac,Cad , Cbc, Cbd , and Ccd , the energy method can be used. According to this method, the total energy of theoverlapping is equal to the energy that is stored in the lumped capacitors of Fig. 2.2 (c). This relationship ispresented in (2.1).Wt =12∮V(#»E ).(#»D)dV =12Cab(aV1−bV1)2+ 12Ccd(cV2−dV2)2+12Cbd(bV1−dV2−Vo)2+12Cad(aV1−dV2−Vo)2+ 12Cbc(bV1− cV2−Vo)2+12Cac(aV1− cV2−Vo)2(2.1)Where E and D are electric field and electric displacement field, respectively. Both of these quantities dependon V1, V2, and Vo. Unfortunately, finding a general analytical solution that describes the individual capacitorvalues for arbitrary winding layouts is not possible. Different number of overlapping turns lead to differentequations, and the resulting relationships are complex and not insightful. Later in this chapter, two specialcases that lead to insightful results are considered and solved analytically.The next step in developing the parasitic capacitance model of the transformer is transferring Cab, Cac,Cad , Cbc, Cbd , and Ccd to the terminals of the transformer. Figure 2.3 shows this process. The energy methodis again used to find the reflected values of these capacitors shown as C12, C13, C14, C23, C24, and C34 in Fig.a 1V1V2Vb 1Vc2VacCadCbcCbdCabC cdCd 2V(a)1V12342V13C14C(b)12C34C23C24C+-+-+-+-oV-+oV-+Figure 2.3: Transferring parasitic capacitance model of a single overlapping to the terminals of thewinding. a) Parasitic capacitance model of an arbitrary overlapping, and b) the reflected parasiticcapacitance model to the terminals of windings.172.3 (b). Equation (2.2) presents the energy relationship between Fig. 2.3 (a) and (b).Wt =12Cab(aV1−bV1)2+ 12Ccd(cV2−dV2)2+12Cbd(bV1−dV2−Vo)2+ 12Cad(aV1−dV2−Vo)2+12Cbc(bV1− cV2−Vo)2+ 12Cac(aV1− cV2−Vo)2 =12C12(V1)2+12C34(V2)2+12C24(Vo)2+12C14(V1−Vo)2+ 12C23(−V2−Vo)2+12C13(V1−V2−Vo)2(2.2)Equating terms with similar coefficients results in transfer functions from the capacitor values of Fig. 2.3(a) to capacitor values of Fig. 2.3 (b). This procedure should be done for every overlapping, and once it isdone for all of the intersections, there will be six different groups of capacitors that are connected betweenterminals of the transformer. Each group consists of several capacitors that are connected in parallel. Underthis condition, the equivalent capacitance of each group can be found by adding capacitors of that group,as all of the capacitors of each group are connected in parallel. The result is the six-capacitor model of thetransformer which was depicted in Fig. 2.1 (b).In the next section, the above-mentioned steps are done for the case of transformers with single-turnoverlapping layers. For transformers with multiple-turn overlapping layers (such as Fig. 2.2), finding ageneral analytical solution is not possible and results in complicate and non-insightful equations. Numericalmethods such as FEA should be used for these cases which are discussed later in this chapter.2.2 Case 1: Parasitic Capacitance Modeling for PTs With Single-TurnLayersAs it was shown in Fig. 2.1, the capacitive behavior of a transformer in the lower frequency range can bemodeled with six different capacitors. The proposed parasitic capacitance model of this section relates thedistributed capacitance of layers to the lumped parasitic capacitors of Fig. 2.1 (b), and shows how windingarrangements affect the value of each lumped capacitor. In other words, the model discussed here fills the gapbetween the microscopic distributed capacitance and the transformer lumped capacitor model. The analysisstarts with the capacitance model of two overlapping layers, and will then be extended to create a model fora complete winding structure.Fig. 2.4 (a) shows two overlapping layers in PTs. Since the terminations of different windings are usuallyon different sides of the PTs, Fig. 2.4 (a) represents a typical interface of two layers that belong to differentwindings (i.e one for the primary and the other for secondary). Four terminals are corresponding to theselayers, which are shown as 1, 2, 3, and 4. Like the behavior of the transformer, the capacitive behavior18V1Vo211343245C2407C2407C2405C240V21V1V21VoV22 Vo V2 VoL2V20+V22 V3++d0x directionLL2x directionWSplit line(a) (a) (c)V1 VoV21234-C60 -C60C23C24C34C12C13C14V1 Vo V21234Figure 2.4: Electrostatic behavior model of two overlapping layers that belong to different windings:a) 3D model of the system along with terminals and voltage directions. b) the overlapping layersare straightened while the voltage gradient between overlapping layers is preserved and c) theelectrostatic model of the systemof this system can be modeled with six lumped capacitances that are connected between the terminals ofthese layers. Three different voltages are needed to describe the electrostatic behavior of this system. Thesevoltages are shown in Fig. 2.4. V1 and V2 are defined as the voltage between the terminals of the top andbottom layers, respectively. Vo is the offset voltage between the two layers. Using this voltage definition,the voltage across each capacitor can be found. The energy method will be used here to find the parasiticcapacitance model of this system. According to this method, the total electrostatic energy of the system isequal to the energy that is stored in the lumped capacitances. In order to calculate the energy of Fig. 2.4 (a),the layers should be straightened, while the voltage gradient between them should be preserved. Since thedirections of the layers are different, there is a discontinuity in the voltage gradient of the two layers (whichis indicated by the split line in Fig. 2.4 (a)). Therefore, two straightened surfaces are required to modeleach layer. Figure 2.4 (b) shows these surfaces. Since in these surfaces the voltage is changing in just onedirection, the voltage distribution of these surfaces can be represented by a linear function that varies in onedimension. The voltage distribution for the yellow and blue layers are presented in (2.3).Vy(x) =V1Lx Vb(x) =Vo+ V22 − V2L x 0 < x < L2Vo+ 3V22 − V2L x L2 < x < L(2.3)Where L and W are the length and width of the layers in Fig. 2.4 (a). When the voltage distribution is known,19the total energy of the system can be found by (2.4).Wt =L∫012ε0εrWd(Vy−Vb)2dx = C024(4V21 −7V1V2−12V1V 3+4V 22 +12V2V3+12V 23 ) (2.4)In the above equation, C0 is the static capacitance between the layers, and can be found by using the parallelplate capacitor formula which is presented in (2.5).C0 = ε0εrW ×Ld(2.5)The energy of the system also can be found by using lumped capacitors. The total energy of the systembased on the lumped capacitance model is presented in (2.6).Wt =12C12V 21 +12C34V 22 +12C24V 2o +12C14(V1−Vo)2+ 12C23(V2+Vo)2+12C13(V1−Vo−V2)2 (2.6)Equations (2.4) and (2.6) both represent the total electrostatic energy of the system and therefore they areequal. Equating similar terms in these two equations, the value of the six lumped capacitors can be foundbased on the static capacitance. These capacitors are shown in Fig. 2.4 (c), and the describing terms basedon the static capacitance are presented in (2.7).C12 =C34 =−C06C13 =C24 =7C024C14 =C23 =5C024(2.7)A similar analysis can be done for a case where the direction of the layers is the same. Figure 2.5 (a)shows two overlapping layers that have the same direction. This condition usually occurs when the over-lapping layers belong to the same winding (i.e., both belong to either primary or secondary). To extract thecapacitance model of this condition, the overlapping layers should be straightened and the voltage gradientbetween the layers should be preserved. Figure 2.5 (b) shows these layers when they are straightened. Thevoltage distributions of these surfaces are presented in (2.8).Vy(x) =V1Lx Vb(x) =V3+V2Lx (2.8)When the voltage distribution is known, the electrostatic energy of the system can be found. Following the20C60V1V2Vo1 1123441223344C60C30C40C30-C60 -C60V1V2VoV30+(a) (b) (c) (d)Figure 2.5: Electrostatic behavior model of two overlapping layers that belong to the same windings:a) 3D model of the system along terminals and voltage directions, b) the overlapping layers arestraightened while the voltage gradient between overlapping layers is preserved, c) the electro-static model of the system and d) the electrostatic model of the system if the overlapping layersare the successive turns of the same winding.same procedure that was used in the previous case, the capacitive model of this condition is shown in Fig.2.5 (c), and the describing terms based on the static capacitance are presented in (2.9).C12 =C34 =−C06C13 =C24 =C03C14 =C23 =C06(2.9)If the layers of Fig. 2.5 (a) are successive layers of the same winding, points 2 and 3 are connected and thecapacitance model can be simplified. Under this condition, the equivalent capacitance between point 1 (startof the first layer) and point 4 (end of the second layer) is equal to C04 , as shown in Fig. 2.5 (d).After developing the parasitic capacitance model for two overlapping layers, the parasitic capacitancemodel of two layers should be extended to a complete transformer. Figure 2.6 (a) shows a PT with aninterleaved structure. V1 and V2 are the voltage between the beginning of the first turn and the end of the lastturn of the primary and secondary windings, respectively. The parasitic capacitance model of one intersectionof primary and secondary is shown in Fig. 2.6 (b), which is similar to the parasitic capacitance model of Fig.2.4 (c). In this figure, every layer is shown with a grey rectangle, and a series connection of these rectanglesconstitutes the winding. As shown in Figs. 2.6 (a) and (b), there are two terminals for each layer (one atthe beginning of the layer and one at the end), and each of these terminals experiences a different pulsatingvoltage. The voltage waveforms at the terminals of each layer depend on the position of that layer.In order to transfer the capacitance model of Fig. 2.6 (b) to the terminals of transformer (Fig. 2.6 (c)),one of the transformer terminals in each side is selected as a reference point. For the case that is presentedin Fig. 2.6 (b), the voltages at the terminals of primary layer are equal to bV1 and aV1, where b and a21aV1 V2VoV1 cV2bV1 dV2-C60 -C607C240C13C12 C34C24C14C237C2405C240 5C2401 3 1 32 42 4(a) (b) (c)Vo}V1V2...PrimarySecondaryFigure 2.6: The relationship between distributed parasitic capacitance of layers and the six-capacitormodel of the transformer: a) an arbitrary interleaved structure of a PT, b) the parasitic capacitancemodel of two overlapping layers belong to different windings relative to the terminals of thetransformer and c) transferring the same parasitic network to the terminals of the transformer.are defined as a ratio of the voltages at these terminals to the total voltage of primary. For instance, if thewinding has eight turns, the values of a and b for the third turn (layer) of the winding are equal to 3/8 and 2/8,respectively. These values for the last turn are equal to 8/8=1 and 7/8. A similar explanation is consideredtrue for the parameters c and d on the secondary side. These parameters represent the ratio of the voltages atthe terminals of each secondary layer to the total voltage of secondary. Given this definition, it is possible touse the energy method to transfer the parasitic capacitance network of each overlapping to the terminals ofthe transformer, as shown in Fig. 2.6 (c). This can be done by considering that the total electrostatic energiesof Fig. 2.6 (b) and (c) are equal. The total energy of Fig. 2.6 (b) is presented in (2.10).Wt =−12C06(aV1−bV1)2− 12C06(cV2−dV2)2+ 127C024(aV1− cV2−Vo)2+ 127C024(bV1−dV2−Vo)2+125C024(aV1−dV2−Vo)2+ 125C024(bV1− cV2−Vo)2(2.10)This equation is equal to (2.6), which represents the total energy in Fig. 2.6 (c). Equating similar termsin these equations provides the required equations for transferring the parasitic capacitance model of theoverlapping to the winding terminals. These equations are presented in Table 2.1 and show that the valuesof transferred capacitors depend on the parameters a, b, c, and d, which are determined by layers thatare overlapping. The transfer equations presented in Table. 2.1 should be used to transfer the parasitic22capacitance network of each overlapping to the terminals of the transformer. Once this is done for all theintersections, there will be six different groups of capacitors that are connected between the terminals of thetransformer. Each group consists of several capacitors that are connected in parallel. Under this condition,the equivalent capacitance of each group can be found by adding the capacitors of that group, as all capacitorsin each group are connected in parallel. For example, the equivalent parasitic capacitance between terminal1 and terminal 3 of the transformer in Fig. 2.6 (b) is equal to the sum of all transferred parasitic capacitancesthat are connected between these terminals. Therefore, in the end, there would be only six capacitors betweenthe terminals of the transformer, which is equal to the six-capacitor model of the transformer. In the nextchapter, equations in Table. 2.1 will be used to validate the concept of “paired layers”.Table 2.1: Equations for transferring the distributed capacitances to the transformer terminalsCapacitor Trans f er EquationC13 C024[5ad+7bd+7ac+5bc]C14 C024[12a+12b−5ad−7bd−7ac−5bc]C23 C024[12c+12d−5ad−7bd−7ac−5bc]C24 C024[24+5ad+7bd+7ac+5bc−12a−12b−12c−12d]C12 C024[8a2+8b2+8ab−12a−12b]C34 C024[8c2+8d2+8cdb−12c−12d]2.3 Case 2: Parasitic Capacitance Modeling of Symmetrical OverlappingOne special case that will be used in the next chapter to develop the concept of “paired layers” is whenthe intersection is symmetrical. Figure 2.7 shows this condition. When the intersection is symmetrical, theoverlapping layers have the same number of turns, the same PCB layout and are only rotated by 180 degreesaround the core center leg. Due to symmetry, one can say that the following equations are valid.Cad =Cbc , Cab =Ccd (2.11)This relationship is also true for the case of single-turn layers that were presented in section 2.2, asoverlapping of single-turn layers also is symmetrical. Although (2.11) does not give the exact equation forindividual capacitor values, this relationship can be used to find a solution to cancel the adverse effect ofparasitic capacitances. This is discussed in detail in the next chapter.23dcbaCbdCacCbc C= adCcd C= abCababcd(b)(a)Figure 2.7: a) A symmetrical overlapping of primary and secondary layers. b) Equivalent parasiticcapacitance model for a symmetrical overlapping.2.4 Equivalent Capacitance Model Extraction Using FEAAs discussed earlier, for transformers with multiple-turn overlapping layers such as Fig. 2.2, finding ageneral analytical solution is not possible and results in complicate and non-insightful equations. Numericalmethods such as FEA can be used to extract the equivalent parasitic capacitance for these cases. This isdiscussed in this section.While the transformer is a two-port system from the magnetostatic perspective, the inter-winding capac-itance between primary and secondary winding provides a path between primary and secondary, making thetransformer a three-port system from the electrostatic standpoint [90]. For a three-port system, three inde-pendent voltages and six capacitors are needed to model the electrostatic behavior of the system. Figure 2.8(a) shows one way of selecting the independent voltages and the six-capacitor model of the transformer.The total energy of the system can be found by summing energies of lumped capacitors. Under this(a) (b) (c) (d)n:1C13C24CC14C12 C3423V1V2VoVoV2V1Figure 2.8: Electrostatic behavior model of the transformer: (a) Six-capacitor model with three inde-pendent voltages, (b), (c), and (d) the required numerical analysis to find six-capacitor model.24condition, the total energy of the system is equal to (2.12).Wt =12C12V 21 +12C34V 22 +12C24V 2o +12C14(V1−Vo)2+ 12C23(V2+Vo)2+12C13(V1−Vo−V2)2 (2.12)By rearranging (2.12) based on voltages, (2.13) can be obtained.Wt =12(C12+C14+C13)V 21 +12(C34+C23+C13)V 22 +12(C24+C14+C23+C13)V 2o+(−C14−C13)V1Vo+(C23+C13)V2Vo+(−C13)V1V2(2.13)The total energy of the system also can be computed using electric fields. Since Maxwell’s equations arelinear, they satisfy the superposition principle. In a system with three independent voltages, like the one inFig. 2.8 (a), the total electric field is equal to the sum of# »E1,# »E2, and# »Eo, corresponding to the voltages#»V1,#»V2, and#»Vo. Therefore, the total electric field and electric displacement field in the system can be written asfollows:#»Et =# »E1+# »E2+# »Eo# »Dt =# »D1+# »D2+# »Do (2.14)The total electrostatic potential energy may be expressed in terms of these fields in the form of followingequation:Wt =12∮V(# »E1+# »E2+# »Eo).(# »D1+# »D2+# »Do)dV =12∮V# »E1.# »D1+12∮V# »E2.# »D2 dV +12∮V# »Eo.# »Do dV+12∮V(# »E1.# »D2+# »E2.# »D1)dV +12∮V(# »E1.# »Do+# »Eo.# »D1)dV +12∮V(# »E2.# »Do+# »Eo.# »D2)dV(2.15)Numerical methods like FEA can be employed to calculate the energy using (2.15). Three differentanalyses are required to find the six-capacitor model and they are presented in Figs. 2.8 (b), (c) and, (d). Thecases presented in Fig. 2.8 (b) and (c) require a linear voltage distribution on the turns of one winding, andzero voltage on all the turns of the other winding. The linear distribution of the voltage on the turns of oneside is signified by a triangle next to that winding. The analysis performed in Fig. 2.8 (d) requires a constantvoltage on all turns of the secondary side and zero voltage on all turns of the primary side. The constantvoltage on all turns of the secondary side also is signified by a rectangle next to that winding, which showsthat there is no voltage difference between the terminals of the secondary side. Obtaining the values of thefirst three terms in (2.15) are straightforward. The total electrostatic energy in Figs. 2.8 (b), (c) and (d) areequal to the first, second, and, third terms, respectively. The remaining three components are found using thesuperposition theorem.25Similar to (2.13), equation (2.15) indicates that the total energy is composed of six components. Equatingcorresponding terms in (2.15) and (2.13), expressions for finding six capacitors are presented in Table 2.2.Among six capacitors, C13, C14, C23, and C24 are inter-winding capacitances and C12 and C24 model theintra-winding capacitances of windings. As mentioned before, reducing the inter-winding capacitances cansignificantly attenuate CM noise and enhance the performance of the converter.Table 2.2: Equations describing parasitic capacitances based on field analysisCapacitor EquationC13 −12V1V2∮V (# »E1.# »D2+# »E2.# »D1)dVC14 −12V1Vo∮V (# »E1.# »Do+# »Eo.# »D1)dV −C13C23 12V2Vo∮V (# »E2.# »Do+# »Eo.# »D2)dV −C13C12 1V 21∮V (# »E1.# »D1)dV −C14−C13C34 1V 22∮V (# »E2.# »D2)dV −C13−C23C24 1V 2o∮V (# »Eo.# »Do)dV −C13−C23−C142.5 Equivalent Capacitance Model Extraction Using MeasurementThe value of lumped capacitors of equivalent circuit can be measured using six different impedance measure-ments. There are four ports and different measurement configurations are possible to extract the six-capacitormodel. The measurement can be done between any two ports, and also ports can be connected together. Animportant criterion in selecting measurement configuration is that the resulting circuit should not have anytwo capacitors in series. In other words, in a right configuration, all capacitors are in parallel. Otherwise,it produces wrong results. Six different measurements of Fig. 2.9 satisfy this requirement and can give sixequations to find the value of six capacitors. For example, the equivalent capacitance measured in Fig. 2.9(a) is equal to C13+C14+C23+C24 and there is no series connection of capacitors. Equivalent capacitanceof each measurement is presented in (2.16).CM1 = (C13+C14+C23+C24) CM2 = (C34+C13+C23)CM3 = (C12+C13+C14) CM4 = (C12+C24+C23)CM5 = (C34+C14+C24) CM6 = (C12+C23+C14+C34)(2.16)Having the equivalent capacitance of each measurement, the value of each capacitor is found based on26(a) (b) (c)(d) (e) (f)123412341234123412341234Figure 2.9: Six different measurements to establish transformer’s six capacitance model (a) M1, (b) M2,(c) M3, (d) M4, (e) M5, and (f) M6the measurements and is presented in (2.17).C12 =12(CM3−CM1+CM4) C34 = 12(CM2−CM1+CM5)C13 =12(CM2+CM3−CM6) C24 = 12(CM4+CM5−CM6)C14 =12(CM1−CM2−CM4+CM6) C23 = 12(CM1−CM3−CM5+CM6)(2.17)2.6 Validation of the Proposed Parasitic Capacitance ModelIn this section, FEA simulations and experimental measurements are used to validate the proposed parasiticcapacitance model. The verification starts with a model of double layer PCB and then extends to the case ofa simple PT with four double-layer PCBs.Fig. 2.10 (a) shows a double-layer PCB with one turn on each side. As shown in Fig. 2.10 (b), thecapacitance between the top and bottom layers are called static capacitance, C1. The value of this capacitorcan be found by using the formula of the parallel plate capacitor, as shown in (2.18).C0 = ε0εrAd= (8.85×10−12)× (4)× (11.5×10−4)0.66×10−3 = 62pF (2.18)The area is found using the PCB design software and d is the thickness of PCB used. Due to the fringingof E-field, the actual value of this capacitance is slightly higher than the calculated value. To consider thefringing effect, the static capacitance between the top and bottom layers is also found using FEA. Figure 2.10(c) shows E-field between the top and bottom layers and the simulation result for the static capacitance is27(a) (c)(b) C1760E (V/m )15200Cross SectionFigure 2.10: a) A double-layer PCB with one turn on each side. b) Definition of static capacitancebetween top and bottom layers, C1. c) E-field distribution showing fringing of E-field.equal to 66pF. This capacitance is called C1 in this section. This was expected as the fringing of the electricfield slightly increases the overlapping area.As analytically proven in section 2.2 and shown in Fig. 2.5, if the overlapping turns are successive turns ofthe same winding, their equivalent parasitic capacitance from the start of the top turn to the end of the bottomturn is equal to one-fourth of the static capacitance. To verify this, the equivalent capacitance from point a inFig. 2.11 to point b in Fig. 2.11 was found using FEA. One volt was applied between the start of the top turnand the end of the bottom turn. The total energy was equated to the energy stored in the self-capacitance andso the value of equivalent capacitance was found. Using this method, the value of equivalent capacitancebetween points a and b is equal to 16pF, which is almost one-fourth of static capacitance between the top andbottom layers (66pF/4=16.5pF) found using FEA. This PCB layout also has been measured experimentallyto validate the model. Figure 2.11 (b) shows the prototype of this PCB and the impedance of this layout ispresented in 2.11 (c). The measured capacitance value is equal to 15.8pF which is in a good agreement withthe simulated value (16pF) and calculated value (15.5pF).Volt10.50(a) (b) (c)fr=70MHzEnergy=7.9pFL=375nHC=15.8pFabFigure 2.11: Finding equivalent capacitance from point a to point b. a) Voltage distribution on turns, b)prototype of the PCB and c) frequency response of the prototype.28a(b)(a)fghbcdePrimary 4 turnsSecondary 2 turns (two in parallel)Figure 2.12: a) FEA model of PT under study and b) the prototype of PT. The turns ratio is 4:2. EachPCB has two turns and secondary PCBs are connected in parallel.After verifying the model for the single PCB, now a simple PT structure is used to validate the proposedparasitic capacitance model. Figures 2.12 (a) and (b) show the FEA model and physical prototype of this PT,respectively. The turns ratio is 4 : 2 and each PCB has two turns (one on the top layer and another one on thebottom layer). Secondary PCBs are in parallel and are placed between primary layers. The distance betweenPCBs is 0.83mm and the material between them is air.Fig. 2.13 (a) shows the structure of the transformer. As shown in Fig. 2.13 (a), there are seven over-lappings between layers in this structure (indicated by OV1 to OV7). OV1, OV3, OV5, and OV7 are theoverlapping between the top and bottom layers of the same PCB. Therefore, the parasitic model from thestart of the top turn to the end of the bottom turn is equal to one-fourth of static capacitance (as discussed in2.10). For OV2, OV4, and OV6, the material between overlapping layers is air and the distance is 0.83mm.This results in a static capacitance value of 17.86pF. This capacitance is called C0 in the following parts.OV4 is the overlapping between successive turns of the same winding, so its parasitic capacitance modelis equal to one-fourth of static capacitance. However, for this case, the static capacitance is C0. OV2 andOv6 are the overlappings between layers of different windings. Therefore, they need six capacitors to modeltheir capacitive behavior. Fig. 2.13 (b) shows the parasitic capacitance model of this PT. Color coding isused in this figure and the parasitic capacitance model of each overlapping is shown with the same coloras it was indicated in Fig. 2.13 (a). The capacitance model of OV2 is shown with a purple color. Thiscapacitance model is similar to the capacitance model developed in section 2.2 and shown in Fig. 2.4 (c).Similarly, modeling OV6 requires six capacitors, and it is shown with brown capacitors in this figure. To2991C1920110C1920=10.2pF82C192019C192029C192053C192053C192029C192091C192019C1920 C41 C41 C40(c) (d) C161 C161 C81 - C21 C-120-11C480-11C480-C6-C60 0aefhaefh 11C2400.14pF7.6pF==5C2407C240 C41 C41 C40 C41 1 C4-C60-C607C2407C2405C240-C60-C60abcdefgh7C2405C24031.2 pF=82C19207.6pF=110C1920=10.2pFP1(a) (b)S1OV1S2S1S2P20.83mmairP3P40.66mmPCB{OV3{OV5{OV7{OV2{OV4{OV6{abccdePrimarySecondaryFigure 2.13: Analytical derivation of parasitic capacitance. a) PT arrangement which has 7 differentoverlappings, b) distributed capacitance model of PT, c) distributed parasitic capacitance of PTtransferred to the terminals and d) six-capacitor model of PT.find the six-capacitor model of the transformer, distributed capacitors of Fig. 2.13 (b) should be transferredto the terminals of the transformer. Equations provided in Table. 2.1 are used for this purpose. Figure 2.13(c) shows the parasitic capacitance model with all capacitors transferred to the terminals of the transformer.This can be further simplified, as there are many capacitors in parallel. Finally, Fig. 2.13 (d) shows the sixcapacitance model of the transformer.To validate the parasitic capacitance model of Fig. 2.13 (d), FEA was used to extract the value of eachlumped capacitor. As explained in section 2.4, three different analyses are needed to do so. The results30V1Volt210Volt10.50V2(a)(c)(b)(d)VoVolt1010aefh31.1pF8.22pF0.59pF8.19pF9.95pF9.94pFFigure 2.14: Extracting parasitic capacitance model using FEA: a), b) and c) Simulations required tofind the model. d) Extracted six-capacitor model.of these three analyses should be used according to the formulas provided in Table. 2.2 to extract the six-capacitor model. Figures. 2.14 (a), (b) and (c) show these three analysis. Figure 2.14 (d) shows the extractedparasitic capacitance model of PT using FEA, which is in great agreement with the analytical model.Finally, measurements were done to characterize the PT under study, and extract the six-capacitor modelof PT. Configurations presented in Fig. 2.9 was used to find the capacitance model. Figure 2.15 (a) showsthe frequency response of the first configuration. Figure 2.15 (b) shows the value of measured capacitancein all configurations. These measurements are used in equations provided in (2.17) to find the six-capacitormodel of the transformer, which is presented in Fig. 2.15 (c).Comparing the proposed equivalent parasitic capacitance model of Fig. 2.13 (d) with models found usingFEA and experimental tests (Fig. 2.14 (d) and Fig. 2.15 (c)) shows that the proposed parasitic capacitancemodel accurately predicts the lumped capacitance model of the transformer. This was expected, as theproposed equivalent capacitance circuit is developed using mathematical analysis and no assumptions orsimplifications were made.31aefh32pF9.8pF0.2pF9.5pF11.6pF11.8pF42.8pF(a) (b) (c)M1:53.3pFM2:51.5pFM3:53.4pFM1:21.3pFM1:55.6pFM1:Figure 2.15: Experimental tests to extract the parasitic capacitance model: a) Frequency response ofone of the tests, b) measurements configurations and measured capacitance values and c) para-sitic capacitance of PT2.7 SummaryParasitic capacitance in PTs has a distributed nature and exists whenever two layers overlap. The net effectof parasitic capacitance can be expressed using the equivalent six-capacitor model. In this chapter, a method-ology for extracting the six-capacitor model of PTs was presented based on the energy method. Using thismethodology, general equations relating the distributed capacitance of layers to the six-capacitor model ofthe transformer were derived. These equations show how the winding arrangement affects the six-capacitormodel and provide a deep insight into how changing the winding arrangement can manipulate the value ofeach lumped capacitor. Two special cases of PTs were considered, and analytical equations were derivedfor each case. In addition to the proposed analytical model, methodologies for extracting the six-capacitormodel using FEA and experimental measurements were proposed. Finally, the proposed capacitance modelhas been verified using FEA and experimental characterization. This model is used in the next chapters toaddress the root cause of CM noise problems in power converters.32Chapter 3The Concept of Paired Layers1With the overgrowing demand in applications that require slim-profile power supplies, such as LED drivers,consumer electronics (laptops, flat-panel TVs) [91], and servers [92], the use of PTs has attracted attention[6, 31, 77–79, 81, 83, 86]. Despite many desirable features of PTs, their large inter-winding capacitancegenerates large amounts of CM noise which creates serious EMI problems. Attenuating large amounts ofnoise requires large CM chokes which increases the cost and reduces the power density of the converter. Thelarge CM noise of PTs is a severe technical challenge that remains unresolved. The objective of this sectionis to find a solution that allows us to design PTs that have almost zero CM noise generation.In the previous chapter, a detailed parasitic capacitance model of PTs was proposed which describeshow the winding arrangement affects the six-capacitor model of the transformer. This model is used in thissection to find a solution for the large CM noise of PTs. CM noise in the transformer originates from anundesired electrostatic coupling between primary and secondary windings and also between windings andthe core. In PTs, whenever a layer of the primary winding overlaps with a layer of the secondary winding,due to the proximity and large overlapping area of planar layers, a large parasitic capacitance is formedbetween overlapping layers. A parasitic capacitance also is formed between the core and layers of windingsthat are exposed to the core. When the voltage of overlapping layers changes rapidly due to high-frequencyswitching, parasitic capacitance is exposed to a large dvdt . This leads to the generation of pulsating currents(known as CM noise) that circulate in the circuit through the earth and create EMI problems [8]. Figure 3.1(a) shows different sources of CM noise in a transformer. IP−S is the CM noise current that is generated whenprimary and secondary layers overlap and is the largest part of the transformer’s CM noise. As shown in Fig.3.1 (a), this current circulates between primary and secondary sides through the earth and shows up in the1Portions of this chapter have been published in [1–4]33Common-Mode Noise Generation in Planar TransformersThe Proposed Solution to Eliminate All Common-Mode Noise SourcesTo Secondary=0=0PELISNPrimaryCircuitSecondaryCircuitTo SecondaryV0V1VV0VV2/2VV2/2VV2/2(a)(b)IP-SIS-CCC-GCC-GIP-S IP-CIP-CIP-CIS-CIP-C-SIP-C-SIP-SIP-C-SCP-CCP-SCP-SCS-CPELISNPrimaryCircuitSecondaryCircuitV1VVV2/2VV2/2V0V0VV2/2112 43IS-CIS-CIS-CIS-CIP-SIP-SI=0IS-CIS-CIP-CIS-CIP-C-S34232114444111114IP-SIP-SFigure 3.1: a) Transformer’s CM noise sources and their circulation path in the converter. IP−S, IP−C,IP−C−S, and IS−C are shown with 1©, 2©, 3©, and 4©, respectively. Traditional interleaving methodsonly aim to reduce AC resistance and do not consider dvdt of overlapping layers which leads tovery large levels of CM noise that imposes the use of large CM chokes. b) In the paired layersinterleaving method, primary and secondary layers are designed in a way that their overlappingdoes not generate CM noise. The structure of the transformer also eliminates other CM noisesources and minimizes AC resistance.standard EMI tests that are done at the input of the converter. The amount of IP−S depends on the structureof the transformer which determines the number of overlapping between primary and secondary layers. Thestructure of the transformer is also a determining factor in windings’ AC resistance. AC resistance is a factorof skin effect and proximity effect. More interleaved structures that are used to reduce the proximity effectand so minimize winding’s AC resistance significantly increase IP−S, as they have multiple overlapping of34primary and secondary which results in a large inter-winding capacitance. The second noise source is IP−C,which generates when a primary layer overlaps with the core. Figure 3.1 (a) shows that this current returnsto the primary through the parasitic capacitance between the core and earth and appears in the standard EMItests done at the input of the converter. The third noise source is IP−C−S, which is the result of the indirectcoupling of primary and secondary layers through the core. As shown in Fig. 3.1 (a), this current goes fromprimary to secondary (or vice-versa) through the core and returns to its source through the earth. This noisealso shows up in the input EMI tests. Finally, the fourth source of noise in a transformer is IS−C, whichgenerates when a secondary layer overlaps with the core. This noise then returns to the secondary throughthe earth and does not appear in the input of the converter. Therefore, it does not affect the results of standardEMI tests of the converter. In order to effectively minimize the CM noise of the converter, IP−S, IP−C, andIP−C−S should be minimized. While traditional methods reduce AC resistance by interleaving primary andsecondary layers, these methods do not consider CM noise sources in the transformer structure, resulting inlarge amounts of CM noise. To date, no method of interleaving has been proposed for PTs that can achieveboth low AC resistance and very low CM noise generation.This section aims to eliminate the CM noise by introducing the concept of paired layers. Figure 3.1 (b)shows the concept of the proposed method to eliminate different sources of CM noise in PTs. Accordingto this figure, four-layer PCBs are used to make windings (it is also possible to use single-turn copper foillayers, and this is discussed later in the next chapter). IP−S, which is the most significant part of the CMnoise, is eliminated by a novel PCB winding layout which avoids CM noise generation when primary andsecondary layers overlap. IP−C and IP−C−S can be eliminated by using simple criteria in the transformerstructure that blocks the CM noise path from the primary to the core. These concepts are discussed in thissection.3.1 Eliminating CM Noise Due to the Direct Overlapping of Primary andSecondary Layers (IP−S)IP−S is the most significant part of the transformer’s CM noise and is generated when the primary andsecondary layers overlap. Figure 3.2 (a) shows a typical condition that occurs when two layers of differentwindings overlap (i.e. one from the primary and the other from the secondary). As shown in Fig. 3.2 (a),depending on the turns ratio, overlapping layers can have a different number of turns. The electrostaticbehavior of this overlapping can be modeled by six capacitors, as shown in Fig. 3.2 (b) (there are fourterminals and one capacitor is needed between each pair of terminals). The total generated CM noise between35these layers can be found by adding the currents in capacitors Cac, Cad , Cbc, and Cbd (capacitors Cab and Ccddo not contribute to CM noise, as they are between layers of the same winding). CM noise currents in thesecapacitors are presented in (3.1).iac =Cac(dvadt− dvcdt)iad =Cad(dvadt− dvddt)ibc =Cbc(dvbdt− dvcdt)ibd =Cbd(dvbdt− dvddt) (3.1)Considering these equations, the total generated CM noise can be calculated using (3.2).iCM = iac+ iad + ibc+ ibd =Cac(dvadt− dvcdt)+Cad(dvadt− dvddt)+Cbc(dvbdt− dvcdt)+Cbd(dvbdt− dvddt) (3.2)In order to achieve zero CM noise generation between overlapping layers, a condition must be found thatmakes (3.2) equal to zero. Equation (3.2) shows that the amount of CM noise depends on both the values ofdvdt and capacitors. Both of these factors should be considered to find a condition for making total CM noiseequal to zero. The first required condition affects dvdt of overlapping layers and is presented in (3.3).dvadt=dvcdt,dvbdt=dvddt(3.3)CcdCabCacCbc CadCbdaabdccbdIad Ibc IbdIac(a) (b)Figure 3.2: CM noise generation when primary and secondary layers overlap. a) Physical presentationof the overlapping and, b) equivalent parasitic capacitance model which shows how CM noise isgenerated.36In order to achieve these equalities, two conditions should be met. First, the overlapping layers should havethe same number of turns and, second, the dvdt at the ports of overlapping layers should be similar, which canonly happen if specific turns of primary and secondary overlap. By considering (3.3), two terms in (3.2) areeliminated and (3.2) is reduced to (3.4).iCM = iad + ibc =Cad(dvadt− dvddt)+Cbc(dvbdt− dvcdt)=(Cad−Cbc)(dvadt− dvbdt)(3.4)dva/dt and dvb/dt both belong to the same winding and so cannot be equal, as it is not possible that twopoints of the same winding have similar dvdt . Therefore, the only option for making (3.4) equal to zero is tohave Cad and Cbc equal. As discussed in the previous chapter, parasitic capacitance is distributed in its nature,and the six lumped capacitors equivalent circuit of Fig. 3.2 (b) only models the total effect of distributedcapacitance. The value of lumped capacitors can be found by equating the total energy of the overlappingwith the energy of the six-capacitor model. This method was used in section 2.2 for overlapping of single-turn layers, and the results provided simple and insightful equations for each lumped capacitor. However, inthe case of overlapping layers with multiple turns, it is not possible to find a simple and insightful equationfor lumped capacitors. Since the value of Cad and Cbc is not important and it is only required that they to beequal, symmetry can be used to make this happen. When the overlapping layers are symmetrical, they havethe same number of turns, the same PCB layout and are only rotated by 180 degree around the core centerleg. Figure 3.3 (a) shows a symmetrical overlapping of primary and secondary layers. Due to symmetry, onecan say that the following equation is valid.Cad =Cbc (3.5)The general equivalent parasitic capacitance of this overlapping is shown in Fig. 3.3 (b).It should be remembered that the overlapping layers could be multi-turn or single-turn and as long as theyhave symmetrical layouts, (3.5) would be valid. This relationship was proven mathematically for the caseof single turn overlapping in the previous section. Based on the analysis provided in the previous chapter,the overlapping of single-turn layers and its equivalent parasitic capacitance model are shown in Fig. 3.4.According to this figure, the relationship between inter-winding capacitors are presented in (3.6).Cad =Cbc =5C024, Cac =Cbd =7C024(3.6)37dcbaCcdCab C= cdCbc C= adCac Cbdacbd(a) (b)Figure 3.3: a) Symmetrical overlapping and b) equivalent parasitic capacitance model of the overlap-ping.Where C0 is presented in (3.7).C0 = ε0εrW ×Ld(3.7)Satisfying (3.3) and (3.5) is the required condition to make CM noise equal to zero in (3.4). Figure 3.5shows an overlapping of two layers of similar design that have similar dvdt on their ports and so generate zeroCM noise.From the above discussion, the overlapping layers must have the same number of turns and the samePCB layout. They can be single-turn or multiple-turn and be made using PCB or copper foil. Besides, theoverlapping layers should have a similar dvdt on their ports to satisfy (3.3). It means that only certain turnsbadc7C240dW(a) (b)Cbc=Cac7C240=5C240=Cad5C240=CbdacbdFigure 3.4: a) Overlapping of single-turn layers as an example of symmetrical overlapping and b)equivalent capacitance circuit of the overlapping.38dcbaCcdCab C= cdCbc C= adCac CbdacbdIad Icb=0Iac =0Ibd(a) (b)Figure 3.5: a) Overlapping layers should have similar number of turns, similar layout, and similar dvdtat their ports to avoid CM noise generation. a) Physical presentation of these conditions, and b)equivalent parasitic capacitance model which shows that the total CM noise is equal to zero.of primary and secondary are allowed to overlap and other turns should never meet any part of the otherwinding. Turns that are allowed to overlap are called paired turns in this document. The first step in buildingsuch a winding structure is finding paired turns in primary and secondary. Finding paired turns depends onthe transformer’s voltage distribution and paired turns of one topology are not necessarily paired in anothertopology. It is important to note that paired layers interleaving is only applicable if there is a quiet point inthe primary side. On this basis, three different groups of topologies are considered as follows:1. Topologies with a quiet point at one terminal of each winding. Examples of this are Flyback andForward converters.2. Topologies with a quiet point at one terminal of primary and a quiet point on the middle turn of thesecondary. Converters with half-bridge inverter fall in this category.3. Topologies with a quiet point in the middle of both primary and secondary winding. The push-pullconverter is an example of this type of converters.In the next section, these three groups of topologies along their various configurations are considered andpaired turns are found for them. These paired turns (layers) are used in the next chapter to implement thepaired-layers interleaving method.393.2 Paired Turns in Topologies With a Quiet Point at One Terminal of EachWindingThe first category of converters encompasses topologies that have a quiet point on one terminal of eachwinding. Flyback and Forward converters are two well-known examples of these topologies. In both ofthese topologies, one terminal of the primary winding is directly connected to the DC bus and has a quietvoltage. One terminal of the secondary also is connected to secondary ground and has a quiet potential.These topologies can be realized using two different configurations on the secondary side and it will beshown that only one of these configurations allows us to find paired turns. These topologies, their differentconfigurations, and a methodology to find paired turns in them are topics of this subsection.3.2.1 Paired Turns in Flyback ConvertersFlyback is a commonly used low-cost topology for low power isolated applications [98–100]. The efficiency,performance, power-density, and form factor of this topology highly depends on the characteristics of thetransformer, which is a key part of this converter. Fig. 3.6 (a) shows the topology of a Flyback converter andprovides a list of important challenges in designing high-efficiency, high power-density Flyback converters.The transformer leakage inductance significantly affects the performance of the Flyback converter. Largeleakage inductances that are present in the traditional wire-wound transformers cause large voltage spikeson the switch, leading to the selection of switches with higher rated voltage. Besides, a large voltage spikecreates large dvdt which creates CM noise in the switch parasitic capacitance [101] and transformer’s inter-winding capacitance. The transformer form factor also significantly affects the overall height and size of theconverter as usually, it is the tallest and bulkiest part of the circuit along with the output capacitor. Due totheir high height, traditional cores cannot be used in certain low profile applications like Flat TVs or portabledevices. Higher height also is a disadvantage from the heat transfer point of view, as it leads to high thermalresistance. Figure 3.6 (b) summarizes the aforementioned drawbacks of wire-wound transformers. Some ofthese problems can be resolved using planar transformers (PT), which are well suited to slim-profile powerconverters. They provide extremely low leakage inductances that cannot be attained using traditional wire-wound transformers and elaborated interleaved structures can be implemented easily in PTs in such a way asto minimize leakage inductance[9, 85].Despite these advantages, PTs have extremely high inter-winding parasitic capacitance, due to the prox-imity of the layers and their significant overlap, and this generates large levels of Common-Mode noise lead-ing to serious EMI problems [6–8, 46–48, 94–96]. As discussed in previous chapters, CM noise is created402413Wire-Wound Transformer Proposed PTtVSwLlkLarge (dv/dt) asa result of High profileSmall area forheat extractionLarge LevelsCM noise12234Extremely lowlevels of CM noisetVSwLowprofile(50-60% less)LlkSmall (dv/dt) asa result of low Excellent Heatextraction capability(b) (c)icm-24C13C24LlkInter-winding CapacitanceRacC14CS-GC23icm-23icm-14icm-13PE2iCMiCM iCMCswLISN EMI Efficiency Form Factor Heat ExtractionChallenges:(a)11234Transformer Effects: EMI (CM noise) 1Leakage Inductance EMI (Large dv/dt over switch)1 Efficiency (Snubber Loss)22 11Figure 3.6: a) Topology of Flyback converter along with important challenges in designing power Con-verters. Leakage inductance and transformer parasitic capacitance are major causes of CM noise.b) The main drawbacks of wire-wound transformer including high levels of noise, high leakageinductance, high height, and high thermal resistance. c) The problems of traditional transformerscan be resolved using the proposed PTs which not only have very low leakage inductance but alsogenerate almost zero levels of CM noise.by displacement currents that flow from the voltage pulsating nodes in the circuit to the protective earth (PE)though parasitic capacitors [8]. Figure 3.6 (a) shows how CM noise currents are generated in the parasiticcapacitors and circulate in the circuit. According to this figure, transformer inter-winding capacitors play amajor role in CM noise generation. These parasitic capacitors not only generate CM noise but also providea path for secondary side parasitic capacitors and lead to the generation of CM noise currents in these par-asitic capacitors. While interleaved structures that have many intersections between primary and secondarywindings can significantly reduce leakage inductance and enhance the efficiency of the transformer, theyalso lead to very large parasitic capacitance, which increases the level of CM noise generated. Higher levels41of CM noise require more attenuation to comply with standards and regulations, and this requires the use oflarger CM choke filters at the input of the converter. The goal of paired layers interleaving is to eliminate thistrade-off and attain interleaved PTs that not only have a low leakage inductance but also have no generationof CM noise.To find paired turns in the transformer of a Flyback converter and achieve no generation of CM noise,the converter should be realized using the right configuration. The transformer of a Flyback converter hasa static terminal in each winding, which is not affected by the switching of the converter. The remainingtwo terminals have pulsating voltages that change relative to each other. In order to find turns that havesimilar dvdt (which are called paired turns in this document), thedvdt of pulsating terminals must have the samepolarity. The polarity of dvdt of pulsating terminals depends on the configuration of the converter. In orderto show how the configuration of the converter affects the polarity of dvdt , Figs. 3.7 (a) and (b) show twopossible configurations of a Flyback converter. As shown in this figure, the configuration of Fig. 3.7 (a)results in a condition in which the voltage of pulsating terminals move in the same direction. In other words,the polarity of dvdt in pulsating terminals of the primary and secondary is similar. Under this condition, it ispossible to find turns in primary and secondary that have similar dvdt (paired turns). Another configuration ofthe Flyback converter can be realized by placing the diode in the return path, as shown in Fig. 3.7 (b). In thisconfiguration, the voltages of pulsating terminals move in opposite directions (the polarity of dvdt in pulsatingterminals of the primary and secondary is different). Therefore, it is impossible to find turns with a similardvdt . Therefore, it is essential to use the configuration of Fig. 3.7 (a) to implement paired-layers interleaving.Fig. 3.8 shows the voltage distribution of windings in a Flyback converter with the configuration of Fig.2143i24C13C24C14C23 i23i14i13Vdvvvvdv12341dtnaVaddv2dtdv3dtdv4dtδ(t)naδ(t)2143i24C13C24C14C23 i23i14i13Vdvvvdv1341 dtVanadVodv2 dtdv3 dtdv4 dtδ(t)aδ(t)naδ(t)naδ(t)(b)(a)v2 aaFigure 3.7: a) Flyback converter configuration with pulsating voltages that change in the same direc-tions (right configuration) and b) Flyback converter configuration with pulsating voltages thatchange in opposite directions (wrong configuration)423.7 (a). Both primary and secondary have a static terminal and a pulsating terminal. The static terminal ofthe primary is connected to the DC bus and the pulsating terminal is connected to the switch. The terminal ofthe secondary that is directly connected to the output has static potential and the terminal that is connected tothe diode has the pulsating voltage. Starting from the terminal with static voltage, the amplitude of voltagefluctuation increases after each turn and reaches its maximum at the other terminal. Based on this figure,one can say that the first turn after the static terminal of the primary has a similar dvdt as the first turn afterthe static terminal of the secondary. The same is true for the second turns of both windings and so on. Thenumber of paired turns is similar to the number of turns of the winding with fewer turns. In order to avoidCM noise generation, the structure of the transformer should be designed in a way that only paired turnsoverlap. According to Fig. 3.8 (which shows the case for a step-down transformer), there are turns on theprimary side that have no pair on the secondary and should not overlap with any of secondary turns.By knowing the voltage distribution along windings, it is possible to identify turns with a similar dvdt .Figure 3.9 shows paired turns for both step-up and step-down cases. The following guideline can be used tofind paired turns:1. The dot convention should be used to name primary and secondary turns. For the primary winding,the dot point is connected to the first turn P(1) and the non-dot point is connected to the last turn ofthe primary, which is called P(n1). Similarly, the secondary’s first turn S(1) is connected to the dotpoint and the last turn S(n2) is connected to the non-dot point.2. Using the above convention, P(1) is paired with S(1), P(2) is paired with S(2), P(3) is paired S(3)P(1) P(2) P(3) P(n2). . . P(n1-1) P(n1)2Vp2Vs2Vs. . .S(1) S(2) S(3) S(n2). . .Paired Layers Layers with no PairPrimary WindingSecondary Windinga=3/n1b=2/n1c=3/n2d=2/n2Figure 3.8: Windings’ voltage distribution in a Flyback converter with the configuration of Fig. 3.7 (b).4311n1n2n2(a) (b)V1VV2V(1)(n )V(1)V2No CM noise RegionV(n )2V1V(1)V(n )11V(n )2 n >1 n 2iCM =0 11n1n2n1V2VV1V(1)(n )No CM noise RegionV(n )12 n <1 n 2iCM=0Figure 3.9: a) Paired-turns in a step-down Flyback transformer and b) paired turns in a step up Flybacktransformer.Layers with no pair on the secondaryS(1)P(5)P(6)P(7)P(8)P(1)S(2)P(2)S(3)P(3)S(4)P(1)S(1)S(2)P(2)P(4)S(4)P(4)P(6)P(5)P(8)P(7)P(3)S(3)}Paired LayersP(8) P(7) P(6) P(5)P(4) P(3) P(2) P(1)S(4) S(3) S(2) S(1)(b) (c)(a)Figure 3.10: Paired turns in an 8 : 4 Flyback PT using single-turn copper foils. a) Primary and sec-ondary layouts, b) paired layers of primary and secondary, and c) a simple structure for PT thatsatisfies the requirements of no CM noise generation.and so on. The number of paired layers is equal to n1 or n2, whichever is less.3. By using the above convention, the dot point of both windings should be connected to the static point.Fig. 3.10 shows paired turns in an 8 : 4 PT using single-turn copper foils. Under this condition, the firstfour turns of the primary are paired with the four turns of the secondary and so can overlap with them. Theother four turns of the primary do not have a pair and so should be hidden from the secondary winding.Any structure that satisfies this requirement does not generate CM noise. A simple structure that only hasoverlapping between paired layers is shown in Fig. 3.10 (c). More complicated structures that utilize thisconcept are presented in the next chapter.443.2.2 Paired Turns in Forward ConvertersThe forward converter is another popular Switch Mode Power Supply (SMPS) that is used for producingisolated and controlled DC voltage from the unregulated DC input supply. As in the case of Flyback converterthe input DC supply is often derived after rectifying (and little filtering) of the utility AC voltage. Theforward converter, when compared with the Flyback circuit, is generally more energy-efficient and is used forapplications requiring little higher power output (in the range of 100 watts to 200 watts) [102–104]. However,the circuit topology, especially the output filtering circuit is not as simple as in the Flyback converter. Thetransformer used in the forward converter is desired to be an ideal transformer with no leakage fluxes, zeromagnetizing current, and no losses. Interleaved PTs are a perfect solution to achieve low leakage inductanceand AC resistance and at the same time enhance the form factor of the converter. However, as discussedearlier, interleaved PTs result in a large inter-winding capacitance that generates CM noise. To resolve thistrade-off, the concept of paired turns (layers) has been proposed in this chapter that can be used to designinterleaved structures that generate no CM noise. In other words, paired layers interleaving results in PTs thathave the best of both worlds: low leakage inductance and AC resistance and also no CM noise generation.In order to find paired turns in a Forward converter, the voltage distribution on the transformer’s windingsshould be investigated. Similar to the transformer of a Flyback converter, the transformer of a Forwardconverter has a static terminal in each winding which is not affected by the switching of the converter. Theremaining two terminals have pulsating voltages that change relative to each other. In order to find turns thathave similar dvdt (which are called paired-turns), it is required that thedvdt of pulsating terminals of primaryand secondary windings have the same polarity. The polarity of dvdt of pulsating terminals depends on theconfiguration of the converter. Two possible configurations of the Forward converter are shown in Figs. 3.11(a) and (b). For the Forward converter, the traditional configuration that is shown in Fig. 3.11 (a) cannotprovide the required condition, as the pulsating voltages change in opposite directions. To resolve this issue,the diode D1 and output filter inductance L f are moved to the return path, which is shown in Fig. 3.11 (b). Inthis configuration, the pulsating voltages change in the same direction and, therefore, the condition requiredfor no CM noise generation is obtained.Fig. 3.12 shows the voltage distribution of windings in a Forward converter with the configuration ofFig. 3.11 (b). The situation is very similar to Flyback Converter. Both primary and secondary have astatic terminal and a pulsating terminal. The static terminal of the primary is connected to the DC bus andthe pulsating terminal is connected to the switch. The ground of the secondary side is often connected toprotective earth for safety and so has the static potential. The terminal of the secondary that is directly45δ(t)naδ(t) aδ(t) aδ(t) cδ(t) bδ(t) ncδ(t) nbδ(t)nai14=0vvvvdv12341 dtV dVodv2 dtdv3 dtdv4 dt21 34i24C13C24C14D1LfC23i23i14Vdδ(t)b δ(t)cδ(t)nb ncδ(t)ncna nbi14=0 vvvvdv12341 dtV ddv2 dtdv3 dtdv4 dt21 34i24i23C13C24C14D1LfC23i13Vdncnanbca bca b(a) (b)Figure 3.11: a) Forward converter configuration with pulsating voltages that change in opposite direc-tions (wrong configuration) and b) Forward converter configuration with pulsating voltages thatchange in the same direction (right configuration).connected to the output has static potential and the terminal that is connected to the diode has the pulsatingvoltage. Starting from the terminal with static voltage, the amplitude of voltage fluctuation increases aftereach turn and reaches its maximum at the other terminal. By knowing the voltage distribution along thewindings, it is possible to identify turns with a similar dvdt . Figure 3.12 shows paired regions of windings forboth step-up and step-down cases. Based on Fig. 3.12, the following guideline can be used to find pairedturns:1. The dot convention should be used to name primary and secondary turns. For the primary winding,the dot point is connected to the first turn P(1) and the non-dot point is connected to the last turn ofthe primary, which is called P(n1). Similarly, the secondary’s first turn S(1) is connected to the dot1 1n1n2n2(a) (b)V1VV2V(1)(n )V(1)V2No CM noise RegionV(n )21V(n )2 n >1 n 2iCM=011n2n1V2VV1V(1)(n )V(1)V1No CM noise RegionV(n )12V(n )1 n <1 n 2iCM=0Figure 3.12: Windings’ voltage distribution in a Forward converter with configuration of Fig. 3.11 (b).46Layers with no pair on the secondaryS(1)P(5)P(6)P(7)P(8)P(1)S(2)P(2)S(3)P(3)S(4)P(1)S(1)S(2)P(2)P(4)S(4)P(4)P(6)P(5)P(8)P(7)P(3)S(3)}Paired LayersP(8) P(7) P(6) P(5)P(4) P(3) P(2) P(1)S(4) S(3) S(2) S(1)(b) (c)(a)Figure 3.13: Implementation of the method for an 8 : 4 Forward PT using single-turn copper foils.a) Primary and secondary layouts, b) paired layers of primary and secondary, and c) a simplestructure for PT that satisfies the requirements of no CM noise generation.point and the last turn S(n2) is connected to the non-dot point.2. Using the above convention, P(1) is paired with S(1), P(2) is paired with S(2), P(3) is paired S(3)and so on. The number of paired layers is equal to n1 or n2, whichever is less.3. By using the above convention, the dot point of both windings should be connected to the static point.Fig. 3.13 shows paired turns in an 8 : 4 PT using single-turn copper foils. Under this condition, the firstfour turns of the primary are paired with the first four turns of the secondary and so can overlap with them.The other four turns of the primary do not have a pair and so should be hidden from the secondary winding.Any structure that satisfies this requirement does not generate CM noise. A simple structure that only hasoverlapping between paired layers is shown in Fig. 3.13 (c). More complicated structures that utilize thisconcept are presented in the next chapter.3.3 Paired Turns in Topologies With a Quiet Point at One Terminal ofPrimaryIn the second category of converters, one terminal of the primary winding has a quiet point but none of theterminals of the secondary winding are quiet. Converters with half-bridge inverter and full-bridge/center-tapped rectifier fall under this category. For this type of converters, the configuration of the converter isnot important and paired turns always can be found in primary and secondary. One famous example of thistype of converters is half-bridge LLC resonant converter which will be considered in the next subsection andpaired turns would be found for that.473.3.1 Paired Turns in Half-Bridge LLC Resonant ConvertersThe LLC resonant converter is an excellent option for achieving high efficiency and power density [105–108]. This topology has several advantages including soft switching operation, high part-load efficiency,no-load voltage regulation, high gain range over narrow frequency variation, and its soft-switching operation[109–111]. Soft switching operation minimizes switching loss and reduces Electromagnetic Interference(EMI). Due to these benefits, this topology has been widely adopted in applications that have strict require-ments regarding efficiency and power density [91, 92, 112]. With the overgrowing demand in applicationsthat require slim-profile power supplies, such as Light-Emitting Diodes (LEDS) drivers, consumer electron-ics (laptops, flat panel TVs) [91] and, servers [92], the use of Planar Transformers (PT) in LLC resonantconverters has attracted attention [6, 77–79, 81, 83, 86], as they are the solution for designing low-profilepower converters. PTs also have several other advantages including low leakage inductance, repeatabilityand, low thermal resistance [5, 9, 10, 93]. However, in spite of all these benefits, traditional PTs present highlevels of Common-Mode (CM) noise, a severe technical challenge that remains unresolved. In comparisonto wire-wound transformers, PTs generate significantly larger Common-Mode (CM) noise which createsserious EMI problems [7, 8, 46–48, 94–96].Fig. 3.14 shows the topology of a half-bridge LLC resonant converter along with the detailed model ofthe transformer. As discussed earlier, the requirement of minimizing AC resistance and leakage inductanceis in contradiction with the requirement of minimizing inter-winding capacitance (shown with red color inthe figure). Interleaved structures that reduce AC resistance and leakage inductance lead to large capacitivecoupling between primary and secondary windings and result in large inter-winding capacitance. To resolvethis trade-off, the idea of paired-layers interleaving is proposed in this document. In order to find paired turnsin the half-bridge LLC resonant converter, it is essential to have a detailed look at the voltage waveformsS2S1Vfc RC LmLlk1Rac1 Llk2Rac2C12 C34C14LsCC13C23C24D8D6D5D7CvoTransformerFigure 3.14: Half-bridge LLC resonant converter considering transformer’s parasitic elements.48present at different parts of the transformer.Fig. 3.15 shows voltage waveforms at different parts of the transformer in the LLC resonant converter.In the half-bridge LLC resonant converter, one terminal of the primary winding is connected to the negativeterminal of the DC bus, so it has static potential that is not affected by the switching of the converter. Theother terminal of the primary fluctuates between V1/2 and −V1/2 in each switching period, where V1 is theprimary voltage. By going from the static terminal to the other end of the primary winding, the amplitudeof fluctuation increases after each turn, reaching its maximum at the other terminal of the winding (whichis equal to V1). Considering that the increment of voltage fluctuation after each turn is equal to V1/n1, thevoltage waveform on different parts of the primary winding is shown in Fig. 3.15. This figure also shows thatall parts of the winding have a similar polarity of dvdt , which means that they all go up and down together. Onthe other hand, none of the secondary terminals have static potential, as both terminals have a square-shapedvoltage waveform with a peak-to-peak amplitude of V2, where V2 is the voltage at secondary. However, thepolarities of dvdt at the secondary terminals are the opposite. This means that when the upper terminal is V 2/2,the lower terminal is −V 2/2 and they both change polarity at the switching moment. Under this condition,the middle point of the secondary winding has a static potential, which is not affected by the switching ofthe converter. These conditions are presented in Fig. 3.15, which shows the voltage waveform along thesecondary winding.By knowing voltage distribution along windings, it is possible to identify turns with a similar dvdt . Accord-ing to Fig. 3.15, the secondary winding can be divided into two equal sections. The polarity of dvdt in half of11n1n /22n /22n2(a) (b)V1VV2V(1)(n )V(n )/2VV2(1 V2V2No CM noise Region01n1n2V1V(1)V1V V2(1)No CM noise Region2V(n )/22V(n /2-n )2 1(n /2-n )2 n /221V(n )/221V(n )2V(n )2V(n )1)2n >1 n 2 2n <1 n 2iCM=0iCM=0Figure 3.15: Finding primary and secondary truns with similar dvdt in LLC PTs. a) When 2×n1 is largerthan n2, and b) when 2×n1 is less than n2.49the turns of the secondary is opposite to the polarity of dvdt in the primary turns. Therefore, it is impossibleto find corresponding turns for these turns on the primary side. On the other hand, the polarity of dvdt on theturns of the other section is similar to the polarity of dvdt on the turns of the primary. So, it is possible to findpaired layers for them in the primary. According to this figure, turns with a similar dvdt have equal distancefrom the static point of their windings. The above explanation can be formulated in the following steps tofind turns with a similar dvdt on the primary and secondary windings.1. The dot convention should be used to name primary and secondary turns. For the primary winding,the non-dot point is connected to the first turn P(1) and the dot point is connected to the last turn of theprimary, which is called P(n1). For the secondary winding, the sequence is the opposite. This meansthat the secondary’s first turn S(1) is connected to the dot point and the last turn S(n2) is connected tothe non-dot point.2. Using the above convention, P(1) is paired with S(n2/2), P(2) is paired with S(n2/2− 1), P(3) ispaired S(n2/2−2) and so on. The number of paired layers is equal to n2/2 or n1, whichever is less.3. The above convention is only valid if the non-dot terminal of the primary is connected to the quietpoint (i.e. −VDC).The above explanations are also shown in Fig. 3.15. Figure 3.15 (a) shows the condition when 2n1 islarger than n2. Under this condition, some of the primary turns cannot be matched with any of the secondaryturns. Therefore, these turns also should not overlap with any part of the secondary winding. Figure 3.15(b) shows the condition when 2n1 is less than n2. Under this condition, all of the primary turns have acorresponding turn on the secondary that has a similar dvdt . In order to achieve zero CM noise generation, theoverlapping layers of primary and secondary should have the same number of turns and only consist of turnsthat have similar dvdt . This should be considered when PCB layouts are designed and will be discussed in thenext chapter.Fig. 3.16 shows an 8 : 4 PT using single-turn copper foils. Under this condition, the first two turns of theprimary are paired with two turns of the secondary and so can overlap with them. The other six turns of theprimary and the other two turns of the secondary do not have a pair and so should be hidden from the otherwinding. A simple structure that only has overlapping between paired layers is shown in Fig. 3.16 (c). Morecomplicated structures that utilize this concept are presented in the next chapter.50Layers with no pair on the secondaryS(1)P(5)P(6)P(7)P(8)P(2)S(2)P(1)S(3)P(3)S(4)S(1)S(3)S(4)S(2)P(4)P(5)P(4)P(3)P(2)P(1)P(8)P(7)P(6)}Paired LayersP(8) P(7) P(6) P(5)P(4) P(3) P(2) P(1)S(4) S(3) S(2) S(1)(b) (c)(a)Figure 3.16: Implementation of the method for an 8 : 4 LLC PT using single-turn copper foils. a)Primary and secondary layouts, b) paired layers of primary and secondary, and c) a simplestructure for PT that satisfies the requirements of no CM noise generation.3.4 Paired Turns in Topologies With a Quiet Point at the Middle of BothPrimary and Secondary WindingThe third category of converters consists of topologies that have a quiet point in the middle of primary andsecondary windings. In these converters, both terminals of primary and secondary windings have pulsatingvoltages that move in opposite directions. One example of these topologies is the Push-Pull converter whichwill be studied in the next subsection and paired turns will be found for that.3.4.1 Paired Turns in Push-Pull ConvertersThe Push-Pull isolated converter is illustrated in Fig. 3.17. This converter is used always with the low inputvoltage, high input current. It tends to exhibit low primary side conduction losses since at any given instantonly one transistor is connected in series with the dc source Vg [115]. The ability to operate with transistorduty cycles approaching unity also allows the turns ratio to be minimized, reducing the transistor currents.The push-pull converter is one of the few available galvanic isolated topologies in which both transistors arereferred to primary ground, which makes it easier to drive them. Both primary and secondary windings arecenter-tapped and their center-tap is connected to the quiet points of primary and secondary. Both terminalsin primary and secondary have pulsating voltages that move in opposite directions.To find paired turns in the Push-Pull converter, it is essential to have a detailed look at the voltage wave-forms present at different parts of the transformer. Figure 3.18 shows voltage waveforms at different parts ofthe transformer in the push-pull converter. Based on this figure, the following guideline can be used to findpaired turns of primary and secondary.1. The dot convention should be used to name primary and secondary turns. For the primary winding,51 a a a a a a a a b b b b b b b bvvvvdv12341 dtdv2 dtdv3 dtdv4 dti24i23C13C24C14C23i13i14a2aabb2a1 32 4Figure 3.17: Push-Pull converter along voltage waveforms at terminals of the transformer.the dot point is connected to the first turn P(01) and the non-dot point is connected to the last turn ofthe primary, which is called P(n1). For the secondary winding, the sequence is the same. This meansthat secondary’s first turn S(01) is connected to the dot point and last turn S(n2) is connected to thenon-dot point.2. Using the above convention, P(n1/2) is paired with S(n2/2+1), P(n1/2−1) is paired with S(n2/2+11n1n2n 1(a) (b)V1VV(n ) (1)V(1)V1V2V2No CM noise Region n >1 n 2 n <1 n 2iCM=0No CM noise Region/2n 1/2-n 2/2n 1/2+n 2/2/2 1V(n ) V1V1/2 1V(n ) /2 2V(n ) 1V(n ) 1V2VV(n ) (1)V1V1V1/2 2V(n ) 2n 2/211n2n1n 2/2n 2/2-n 1/2n 2/2+n 1/2n 1/2V(1) V2V(n ) 2V2Figure 3.18: Finding primary and secondary turns with similar dvdt in Push-Pull PTs. a) When n1 islarger than n2, and b) when n1 is less than n2.52Layers with no pair on the secondaryS(4)P(5)P(6)P(7)P(8)P(1)S(3)P(2)S(2)P(3)S(1)S(3)S(2)S(1)S(4)P(4)P(5)P(7)P(8)P(6)P(3)P(2)P(1)P(4)}Layers with no pair on the secondary}Paired LayersP(8) P(7) P(6) P(5)P(4) P(3) P(2) P(1)S(4) S(3) S(2) S(1)(b) (c)(a)Figure 3.19: Implementation of the method for an 8 : 4 Push-Pull PT using single-turn copper foils.a) Primary and secondary layouts, b) paired layers of primary and secondary, and c) a simplestructure for PT that satisfies the requirements of no CM noise generation.2), P(n1/2− 2) is paired S(n2/2+ 2) and so on. In addition, P(n1/2+ 1) is paired with S(n2/2),P(n1/2+ 2) is paired S(n2/2− 1) and so on. The number of paired layers is equal to n2 or n1,whichever is less.Fig. 3.19 shows an 8 : 4 Push-Pull PT using single-turn copper foils. Figure 3.19 (b) shows paired turnsof primary and secondary which are found using the above guidelines. A simple structure that only hasoverlapping between paired layers is shown in Fig. 3.19 (c).3.5 Mathematical Proof for Paired Layers InterleavingIn this section, the parasitic capacitance model of PTs with single-turn layers (developed in section 2.2) isused to analytically validate the concept of paired layers. It will be shown that designing the structure basedon the concept of paired layers results in an equivalent lumped capacitance circuit for the transformer thathas a net amount of CM noise equal to zero. The first group of converters is considered for this analyticalvalidation. The same method can be used to analytically validate the concept for second and third groups ofconverters.In order to achieve no generation of CM noise in the transformer of Flyback and Forward converters,these topologies should be realized using the right configuration. In addition, transformer lumped parasiticcapacitances should also satisfy a certain condition. The level of CM noise that is generated due to thetransformer inter-winding capacitance depends on the voltages at the transformer terminals. Both Flybackand Forward converters have a static terminal on each side, which is not affected by the switching of theconverter. The remaining two terminals have pulsating voltages that change relative to each other. To show53C122143C34C13C24C14C23C12C34C13C24C14C23i =024i =024iCMiCMi =23i14i14i13i14i23i13i +13v1v2Vdv1 dtdv2 dtv1v2dv1 dtdv2 dtv3v4nVdv3 dtdv4 dtv3v4dv3 dtdv4 dtnVδ(t)nVnVδ(t) Vδ(t)VVδ(t)2143iCMiCM(a) (b)Figure 3.20: Transformer CM Noise cancellation requirement for Flyback and Forward converters us-ing six capacitance model of the transformer. a) Swinging points change in the opposite direc-tions (wrong condition) and b) swinging points change in the same direction (right condition).what condition is required to achieve CM noise cancellation for the transformer, Figs. 3.20 (a) and (b)show two different conditions that can occur in the aforementioned power converters. The whole effect oftransformer inter-winding capacitance on CM noise can be modeled using four lumped capacitors betweenterminals of the primary and secondary. These two figures are only different in the way that voltages in theswinging terminals change relative to each other. From the continuity of the current in the green cut-set ofFig. 3.20 (a), (3.8) can be derived.2iCM = i13+ i14+ i23+ i24 (3.8)The expressions for the displacement currents are presented in (3.9).i13 =C13(dv1dt− dv3dt)i14 =C14(dv1dt− dv4dt)=C14dv1dti23 =C23(dv2dt− dv3dt)=−C23 dv3dti24 =Cac(dv2dt− dv4dt)= 0(3.9)No CM noise generation means that the iCM should be equal to zero. In order to achieve this, i13, i14, i23, andi24 should cancel one another out and make the total CM noise equal to zero. Equating iCM to zero in (3.8)and using (3.9), the required conditions for achieving full CM noise cancellation for Flyback and Forwardconverters can be obtained, and are presented in (3.10).dv1dt(C13+C14)=dv3dt(C13+C23)(3.10)Equation (3.10) can be achieved only if dv1/dt and dv3/dt have the same sign. When this condition ismet, it means that the voltages in the swinging terminals change in the same direction. Otherwise, all of54the displacement currents will have the same direction and will be unable to cancel each other out. Thisexplanation is conceptually depicted in Figs. 3.20 (a) and (b). Figure 3.20 (a) shows the condition in whichthe voltages are changing in opposite directions. In this case, the displacement currents all have the samedirection and, therefore, they cannot cancel each other out. In contrast, the pulsating voltages in Fig. 3.20 (b)change in the same direction. Under this condition, one of the displacement currents flows in the oppositedirection of the other two currents and, therefore, it cancels them out. Therefore, no CM noise generation forthe Flyback and Forward converters requires that the pulsating voltages change in the same direction. FullCM noise cancellation also requires that the transformer’s lumped capacitors satisfy a certain condition. Ifthe coupling between the primary and secondary windings is strong, dv1/dt and dv3/dt can be related toeach other according to (3.11).dv3dt= kdv1dt(3.11)Where k is the transformer turn ratio (n2/n1). Using this relationship, (3.10) can be simplified and thefollowing condition for achieving no CM noise generation can be found.(1− k)C13+C14 = kC23 (3.12)Therefore, if the transformer’s parasitic capacitances follow (3.12), displacement currents cancel each otherout, and the net CM current is equal to zero. Equation (3.12) states the conditions necessary in a PT toachieve no CM noise generation in the transformer of Flyback and Forward converters.Now it is shown that employing paired layers concept achieves the condition of (3.12). As explained inchapter 2, distributed capacitance of every overlapping can be transferred to the terminals of the transformer.Figure 3.21 (a) shows a PT with an interleaved structure. The parasitic capacitance model of one intersectionof primary and secondary is shown in Fig. 3.21 (b). In this figure, every layer is shown with a grey rectangle,and a series connection of these rectangles constitutes the winding. As shown in Figs. 3.21 (a) and (b),there are two terminals for each layer (one at the beginning of the layer and one at the end), and each ofthese terminals experiences a different pulsating voltage. The voltage waveforms at the terminals of eachlayer depend on the position of that layer. In order to relate the distributed parasitic capacitances of Fig.3.21 (b) to the six capacitance model of the transformer, one of the transformer terminals on each side isselected as a reference point. For the case that is presented in Fig. 3.21 (b), the voltages at the terminals55aV1 V2VoV1 cV2bV1 dV2-C60 -C607C240C13C12 C34C24C14C237C2405C240 5C2401 3 1 32 42 4(a) (b) (c)Vo}V1V2...PrimarySecondaryFigure 3.21: The relationship between distributed parasitic capacitance of layers and the six-capacitormodel of the transformer: a) an arbitrary interleaved structure of a PT, b) the parasitic capacitancemodel of two overlapping layers belong to different windings relative to the terminals of thetransformer and c) transferring the same parasitic network to the terminals of the transformer.of the primary layer are equal to b×V1 and a×V1, where b and a are defined as a ratio of the voltages atthese terminals to the total voltage of primary. For instance, if the winding has eight turns, the values of aand b for the third turn (layer) of the winding are equal to 3/8 and 2/8, respectively. These values for thelast turn are equal to 8/8=1 and 7/8. A similar explanation is considered true for the parameters c and d onthe secondary side. These parameters represent the ratio of the voltages at the terminals of each secondarylayer to the total voltage of secondary. Given this definition, it is possible to use energy method to transferTable 3.1: Equations for transferring the distributed capacitances to the transformer terminalsCapacitor Trans f er EquationC13 C024[5ad+7bd+7ac+5bc]C14 C024[12a+12b−5ad−7bd−7ac−5bc]C23 C024[12c+12d−5ad−7bd−7ac−5bc]C24 C024[24+5ad+7bd+7ac+5bc−12a−12b−12c−12d]C12 C024[8a2+8b2+8ab−12a−12b]C34 C024[8c2+8d2+8cdb−12c−12d]56the parasitic capacitance network of each overlapping to the terminals of the transformer, as shown in Fig.3.21 (c). Equations presented in Table. 3.1 provide transfer equations from distributed capacitance of 3.21(b) to lumped capacitance of 3.21 (c). These equations show that the value of transferred capacitors dependson the parameters a, b, c, and d, which depend on the layers that are overlapping.The concept of paired layers requires that dvdt at terminals of overlapping layers to be equal, which waspresented in (3.3). This requirement is equivalent to 3.13.a = kc , b = kd (3.13)Where k is the transformer turns ratio (n2/n1).The requirements for achieving zero CM noise in the transformers have been proposed in (3.12). Substi-tuting C13, C14, and C23 in (3.12) with their equivalent expressions in table 3.1, the condition for achievingzero CM noise can be found which is shown in (3.14).(1− k)C13+C14 = kC23→(1− k)C024[5ad+7bd+7ac+5bc]+C024[12a+12b−5ad−7bd−7ac−5bc]= kC024[12c+12d−5ad−7bd−7ac−5bc](3.14)The solution for (3.14) is presented in (3.15).a+b = k[c+d] (3.15)This is the general condition that results in zero CM noise and paired layers concept is a special case ofthis requirement, as (3.13) satisfies this requirement. Any other method that satisfies this requirement alsoachieves zero CM noise generation.Considering the above explanations, the concept of paired layers to achieve zero CM noise can be ex-plained in two different ways:1. Through lumped Capacitance Circuit: By using the concept of paired layers, the equivalent lumpedcapacitance circuit of the transformer is in a way that displacement currents in the four inter-windingparasitic capacitances cancel each other out which leads to net CM noise equal to zero.572. Through Distributed Capacitance Model: When paired layers overlap, the overlapping layers havethe same dvdt . Therefore, no displacement current will be induced in the distributed parasitic capaci-tances. As a result, there would be no CM current in the transformer.The analytical proof presented in this condition showed that the paired layers concept is a special case ofa general condition that results in zero CM noise. Other schemes that satisfy 3.15 also can be designed toachieve zero CM noise generation.3.6 Eliminating CM Noise Generation Through the Core (IP−C and IP−C−S)As mentioned at the beginning of this chapter, CM noise also can propagate through the core. While theamount of CM noise that is generated through the core is much smaller than the amount of CM noise thatgenerates when layers of primary and secondary overlap, efforts should be made to avoid the generation ofCM noise through the core to achieve very low CM noise generation. As shown in Fig. 3.22 (a), IP−C is theCM noise that is generated when a layer of primary overlaps with the core and injects CM noise current intoit. Part of this CM noise goes to the earth through parasitic capacitance between core and ground (CC−G)and returns through the Line Impedance Stabilization Networks (LISN). Since most of the time EMC testsare done at the input of the power converter, this CM noise will be part of the measured noise, and thus itshould be eliminated. On the other hand, IP−C−S is the part of CM noise that is generated from capacitiveIS-CIS-CIP-CIP-CIS-CIS-CIP-C-SIP-C-S(a) (b)PrimarySecondaryFigure 3.22: Eliminating CM noise generation through the core. a) IP−C and IP−C−S are generatedwhen primary layers overlap with the core. b) IP−C and IP−C−S are eliminated when secondarylayers are used at the top and bottom of the structure to avoids exposing primary winding to thecore. IS−C returns to its source without going to the primary and does not show up on the inputnoise.58coupling between primary and secondary through the core. Both IP−C and IP−C−S can be eliminated by notoverlapping the primary layers and the core. This means that the primary layers should be placed betweensecondary layers and the top layer and bottom layer of the PT structure should belong to the secondary. Thiscondition is shown in Fig. 3.22 (b). Since no layer of the primary overlaps with the core, no CM noise willbe injected from primary to the core and both IP−C and IP−C−S will be eliminated.It should be noted that this technique is only possible if the structure of the transformer starts and endswith the secondary winding. For instance, in applications that have a strict isolation requirement, a non-interleaved structure should be used to satisfy the isolation requirement. Under this condition, the primarywinding is exposed to the core and causes some CM noise through the core. In this case, the distance betweenthe primary winding and the core should be increased to minimize the effect of this overlapping. As a result,the core window is not utilized efficiently.It is also worthwhile to mention that the above-mentioned rules only target CM noise and depending onthe situation, the designer might decide to expose the primary winding to the core. Usually, this happens instep-up transformers, where dvdt of secondary layers is much higher than primary turns. Since a conductorwith high dvdt acts like an E-field antenna, exposing secondary turns to the core and circuit creates a radiationproblem. Similar to conducted noise tests, power converters should pass radiated tests too and passing thistest would be hard with exposed secondary turns. As a result, the designer might compromise common-modenoise for getting lower radiated noise.3.7 SummaryIn this section, the concept of paired layers was introduced as a method of avoiding CM noise generationin PTs. According to this concept, if the overlapping layers have the same layout and similar dvdt , such anoverlapping does not generate CM noise. These layers are called paired layers and any winding arrangementthat only has overlapping of paired layers at primary and secondary intersections theoretically has zero CMnoise generation. In order to implement this idea, turns with similar dvdt (called paired turns) should be foundin primary and secondary windings. Finding paired turns depends on the voltage distribution of windingswhich depends on the topology. From transformer’s voltage distribution point of view, power converters weredivided into three groups and paired turns were found for each group. Besides, different configurations oftopologies were studied and right configuration that allows for finding paired turns in primary and secondarywere presented. A simple example of an 8 : 4 PT that incorporate the concept of paired layers was presentedfor each group to make the procedure easy to understand. Also, a mathematical proof for the concept of59paired layers were presented. It was shown that employing the concept of paired layers in the transformerstructure leads to a lumped capacitance network for PT that has net amount of CM noise equal to zero.Beside, methods for eliminating CM noise generation through the core was presented. In the next chapter,paired turns will be combined with interleaving methods to achieve PTs with low AC resistance, low leakageinductance, and no CM noise generation.60Chapter 4Paired Layers Interleaving1The main purpose of introducing the concept of “paired layers” is to develop a design method that resultsin PTs with no CM noise generation. In this section, this concept is combined with interleaving methods toachieve PTs that not only have low AC resistance and leakage inductance but also benefit the converter by notgenerating CM noise. The combination is a design method called “paired layers interleaving” which elimi-nates the long-standing trade-off in transformer design and allows the designer to use interleaved structuresto minimize AC resistance and leakage inductance, and not to worry about CM noise.In the first part of this chapter, different methods of designing planar layers are discussed. Then, theeffect of winding arrangement on AC resistance and leakage inductance is briefly discussed, and conventionalinterleaving methods for PTs are presented. These winding arrangements are then combined with the conceptof “paired layers” to develop paired layers interleaving method. Three different groups of converters areconsidered and several designs using the paired layers interleaving method are provided for each group tomake the method easy to understand. These examples are further experimentally tested to verify the proposedmethods and concepts.4.1 Methods of ImplementationAs explained in the previous section, eliminating IP−S (which is the result of direct overlapping of primaryand secondary) requires the overlapping layers of primary and secondary to have the same number of turns,the same layout, and the same dvdt at their ports. Depending on the number of turns in primary and secondarywindings, different methods can be used to make this happen. In this section, different winding methods toimplement the concept of “paired layers is discussed.1Portions of this chapter have been published in [1–4]614.1.1 Implementation Using PCBIf both windings consist of a large number of turns, four-layer PCBs that are commonly used in circuit designcan be used to construct both windings. Figure 4.1 shows a diagram of primary and secondary windings madeusing four-layer PCBs; The design should be done in such a way that top layer of the primary and the bottomlayer of the secondary have turns with similar dvdt ; therefore, their overlapping does not create CM noise. Thesame criterion should be applied in the design of the bottom layer of the primary and the top layer of thesecondary. Turns that do not share the dvdt with any turn of the other winding should be placed on the middlelayers, so they are shielded by the top and bottom layers and do not create CM noise.Considering the above-mentioned rules for designing PCBs, Fig. 4.2 shows PCB layouts for differentturns ratios in LLC PTs. The criteria for finding paired-turns in LLC PTs was discussed in section 3.3.1.Figure 4.2 (a) shows how primary and secondary PCBs should be designed for a 16 : 16 turns ratio speci-fication. As shown in Fig. 4.2 (a), the top layer of the primary PCB has the first four turns of the primary(P(01) to P(04)). On the other hand, the bottom layer of the secondary, which faces the top layer of theprimary, contains the turns S(05) to S(08) of the secondary (these turns have similar dvdt as turns P(01) toP(04)). Therefore, the overlapping of the top layer of the primary and bottom layer of the secondary doesnot create CM noise. The same condition is true for the bottom layer of the primary (which contains turnsP(05) to P(08)) and the top layer of the secondary (which contains turns S(01) to S(04)). Since these turnshave similar dvdt , their overlapping does not generate CM noise. Figure 4.2 (a) also shows the turns that haveno pair on the other winding (P(9) to P(16) on the primary winding and S(09) to S(16) on the secondarywinding) are placed within the middle layers of PCBs. Therefore, they are not exposed to the other windingand so do not contribute to CM noise generation. Figs. 4.2 (b) shows the PCB layout design specified forPrimary PCB Secondary PCBPrimary Bottom Layer Similarto Secondary Top LayerPrimary Top Layer Similar to Secondary Bottom LayerPrimary Turns that shouldn’tOverlap with Secondaryare Placed in Mid-Layers.Secondary Bottom Layer Similarto Primary Top LayerSecondary Top Layer Similar to Primary Bottom LayerSecondary Turns that shouldn’tOverlap with Primaryare Placed in Mid-Layers.Figure 4.1: Disposition of how different layers of the PCB should be used to avoid CM noise genera-tion.62(a)iCM =0Eligible Turns to OverlapP(01)P(02)P(08)P(16)S(08)S(1)S(16)No CM noise RegionP(01)-P(04)S(05)-S(08)S(01)-S(04)S(13)-S(16)S(09)-S(12)S(05)-S(08)P(01)-P(04)BCP yradnoceSBCP yramirPP(09)-P(12)P(13)-P(16)P(05)-P(08) S(01)-P(04)P(05)-P(08)No CM NoisePriSecSeciCM=0iCM=0No CM Noise(b)iCM =0Eligible Turns to OverlapP(01)P(04)P(16)S(04)S(01)S(08)No CM noise RegionS(01)-S(02)S(05)-S(06)S(07)-S(08)S(03)-S(04)P(01)-P(02)Primary PCB Secondary PCBP(05)-P(10)P(11)-P(16)P(03)-P(04)P(01)-P(02)S(03)-S(04)S(01)-P(02)P(03)-P(04)No CM NoisePriSecSeciCM=0iCM=0No CM NoiseSSESES: StartE: EndS: StartE: EndS: StartE: EndS: StartE: EndESELayouts for 16:16 LLC PT Layouts for 16:8 LLC PT Figure 4.2: PCB layouts for eliminating IP−S in LLC PTs. Layout for a) 16 : 16 turns ratio, and b) 16 : 8turns ratio.a 16 : 8 LLC PT based on the same principle. Following the explanation for Fig. 4.2 (a) shows that theselayouts are compliant with the rules, and so their overlapping does not create CM noise.The disadvantage of using the proposed layouts of Fig. 4.2 is the extra DC resistance of the layout. Inthe traditional PCB layouts for planar windings, the turns are distributed equally between the PCB layers.Since all turns have the same width, the current distribution is even and so the DC resistance of the windingis minimized. In the proposed layouts of Fig. 4.2, the turns of primary PCB do not necessarily have thesame width. According to Fig. 4.2, when the turns ratio is unity, the number of turns on each layer of theprimary PCB is the same. However, as the turns ratio deviates from unity, more turns should be placed onmid-layers and fewer turns are allowed to be on top and bottom layers. This increases the DC resistance ofthe primary winding as a side effect of using the method to minimize CM noise. To find out by how muchprimary winding resistance is increased as the result of using the proposed method, FEA has been used tofind the DC resistance of the layouts; and the results are shown in Fig. 4.3. These layouts are designedfor an ER/41/10/28 core and the copper thickness is 3oz. Figure 4.3 (a) shows the primary and secondary63Primary Primary Primary PrimaryR = 165 mΩ16:816:16 16:4 16:2DC-Primary(%0 increase)R = 201 mΩDC-Primary(%21.8 increase)R = 270 mΩDC-Primary(%63 increase)R = 298 mΩDC-Primary(%80.6 increase)R = 165 mΩDC-SecondaryR +R =330 mΩp s/(%0 increase)(%0 increase)R +R =348 mΩp s/(%11.5 increase)R +R =426 mΩp s/ /(%32 increase)R +R =423 mΩp s(%45 increase)R = 36.8 mΩDC-Secondary(%0 increase)R = 9.8 mΩDC-Secondary(%0 increase)R = 1.96 mΩDC-Secondary(%0 increase)Secondary Secondary Secondary(a) (b) (c) (d)SecondaryFigure 4.3: Analysis of DC resistance increase of windings caused by use of proposed method. Theproposed layout and its DC resistance for a) 16 : 16 turns ratio, b) 16 : 8 turns ratio, c) 16 : 4 turnsratio and, d) 16 : 2 turns ratio.layouts for the 16:16 turns ratio. In this layout, turns are distributed equally between layers of the primaryPCB and there is no increment of the primary winding’s resistance. In other words, there is no extra DCresistance penalty when the proposed layout is used for 16 : 16 turns ratio. Figure 4.3 (b) shows the primaryand secondary layouts for the 16 : 8 turns ratio. In this case, the primary turns are not equally shared betweenPCB layers (top and bottom layers each have two turns and middle layers have 6 turns each). This causesthe primary winding resistance to increase by 21% and the total windings’ resistance reflected to the primary(R1 +R2× (n1n2 )2) to increase by 11.5% (in comparison to a traditional layout for 16 : 8 turns ratio). Notethat the secondary PCB always has an equal number of turns in each layer and so there is no increase in thesecondary winding resistance. Figure 4.3 (c) and (d) show the primary and secondary layouts for the 16 : 4and 16 : 2 turns ratios. Compared to traditional layouts, these layouts have 32% and 45% more DC resistancethan traditional layouts for these turns ratios. However, it does not mean that the conduction losses for theselayouts are 32% and 45% more: for transformers with large step-down ratios, most of the high-frequency64conduction losses are on the secondary winding, which does not have extra resistance due to the use of theproposed method. Therefore, the secondary losses are similar in the proposed and the traditional methods,and the extra conduction loss is much less than 32% and 45%. This aspect will be explained in the nextsection when a proposed 16 : 1 : 1 PT is compared to a traditional 16 : 1 : 1 PT.4.1.2 Implementation Using a Combination of PCB and Copper FoilIf one winding has a large number of turns and the other has fewer turns (as the case for high step-up orstep-down PTs), the winding with a large number of turns can be constructed using four-layer PCB and theother winding can be realized using single-turn copper foils. Figure 4.4 shows this condition for a 14 : 2Flyback PT. In this case, the first two turns of the primary are paired with secondary turns. Secondary turnsare realized using copper foils (as they are high-current). The first two turns of the primary (that are pairedwith the secondary turns) are placed on the top and bottom layers of PCB and the rest of primary turns areplaced within the middle layers of the PCB. As a result of this layout, secondary turns only overlap withpaired turns and their overlapping does not generate CM noise.If the use of four-layer PCBs is prohibitive due to the cost issue, a combination of two-layer PCBs andcopper foils can be used for PTs with large or small turns ratio. Figure 4.5 shows this type of implementationfor a 36 : 2 Flyback PT. Using this layout, only the first two turns of the primary have a pair on the secondaryside. The remaining 34 turns do not have a pair on the secondary and, therefore, should not overlap withthe secondary winding. To implement the proposed idea, the first two turns of the primary are realized usingsingle-turn layers. These two layers can overlap with their pair on the secondary side. The remaining 34turns are realized using a double layer PCB. This PCB is placed between the first two turns of the primary tohide them from the secondary winding.Eligible Turns to OverlapS(02)S(01)P(01)Primary PCB Secondary Copper FoilP(02)-P(07)P(08)-P(13)P(14)P(01)S(01)S(02)S(02)S(01)P(02)No CM NoisePriSecSeciCM=0iCM=0No CM NoiseSS: StartE: EndS: StartE: End=0P(14)P(02)P(01)S(01)S(02)No CM noise RegioniCMLayouts for 14:2 Flyback PT Figure 4.4: Implementing the method using PCB for one winding and copper foil for another winding.Winding layouts for eliminating IP−S in a 14 : 2 Flyback PT.6536:2 =0Eligible Turns to OverlapP(36)P(02)P(01)S(01)S(02)No CM noise RegionS(02)S(01)P(01)Primary PCB Secondary PCBP(03)-P(36)P(02)2P(01)S(01)S(02)S(02)S(01)P(02)P(03-36)No CM NoisePriSecSeciCM=0iCM=0No CM NoiseiCMFigure 4.5: Design methodology using a combination of PCBs and copper foils. Winding layouts foreliminating IP−S in a 36 : 2 Flyback PT4.1.3 Implementation Using Copper FoilIf the number of turns is small in both windings, it is possible to use single-turn copper foils for bothwindings. Figure 4.6 shows an 8 : 4 Flyback PT using single-turn copper foils. Under this condition, thefirst four turns of the primary are paired with four turns of the secondary and so can overlap with them. Theother four turns of the primary do not have a pair and so should be hidden from the other winding. A simplestructure that only has overlapping between paired layers is shown in Fig. 4.6 (c). Unlike the PCB-basedwindings, this method does not have the penalty of having more conduction loss in the primary winding.In this section, the implementation of the paired-layers method has been explained through several ex-amples. The proposed PCB layouts can overlap with each other without generating CM noise. The methodwas implemented for different turns ratios to show the method’s flexibility and also to make it easy to under-stand. Implementing the method using single-turn copper foils also has been discussed through an example.Layers with no pair on the secondaryS(1)P(5)P(6)P(7)P(8)P(1)S(2)P(2)S(3)P(3)S(4)P(1)S(1)S(2)S(2)P(4)S(4)P(4)P(6)P(5)P(8)P(7)P(3)S(3)}Paired LayersP(8) P(7) P(6) P(5)P(4) P(3) P(2) P(1)S(4) S(3) S(2) S(1)(b) (c)(a)Figure 4.6: Implementation of the method for an 8 : 4 Flyback PT using single-turn copper foils. a) Pri-mary and secondary layouts, b) paired layers of primary and secondary, and c) a simple structurewith no CM noise generation.66Later in this chapter, these layouts are used to design interleaved structures that not only have very low ACresistance but also have very low CM noise generation.4.2 The Effect of Winding Arrangement on AC Resistance and LeakageInductanceThe effect of winding arrangements on AC resistance can be explained by Dowel’s formula to calculate theAC resistance that is presented in (4.1).Rac = Rdc× ξ2[sinh(ξ )+ sin(ξ )cosh(ξ )− cos(ξ ) +(2m−1)2× ( sinh(ξ )− sin(ξ )cosh(ξ )+ cos(ξ ))](4.1)Where ξ and m are defined as follows:ξ =hδm =F(h)F(h)−F(0) (4.2)In (4.2), h is the thickness of traces, δ is the skin depth at the operating frequency, and F(h) and F(0) arethe Magneto-Motive Force (MMF) at the limits of the conductor, which depend on the arrangement of thetransformer. The first term in (4.1) describes the skin effect and only depends on the ratio of copper thicknessto skin depth (ξ ). The second term in (4.1) represents the proximity effect and relates the AC resistance to thewinding arrangement of the transformer. The proximity effect depends on two factors; ξ and m. The value ofm for each layer is determined by the leakage fluxes that surround the layer and is calculated based on (4.2).In the interleaved structures (where primary and secondary layers are interleaved and have several overlaps),the leakage fluxes of primary and secondary windings cancel each other out and, therefore, a low value form is obtained. However, for the non-interleaved structure (where primary and secondary are separated),the values of m are very large and the proximity effect dominates (4.1) and significantly increases the ACresistance. In order to show how the structure of PT affects the value of m, Fig. 4.7 shows three differentstructures for an 8 : 4 PT. According to Fig. 4.7 (a), the non-interleaved structure leads to large values of m,which considerably increases the AC resistance. On the other hand, using the interleaved structures of Fig.4.7 (b) and (c), the values of m are reduced significantly, which minimizes proximity effect and leads to lowAC resistance and leakage inductance.67NI2NI3NI4NI5NI6NI7NI8NI0P1P2P3P4P5P6S4S3S2S1P7P8m=1m=2m=3m=4m=5m=6m=7m=8m=4m=3m=2m=1(a) (c)(b)NI-NI0P1S4P2P3S3P4P6P7S1P8P5S2m=1m=0.5m=1m=1m=0.5m=1m=1m=0.5m=1m=1m=0.5m=1NI2NI-2NI-NI0S1P1P2P3P4S2P6P7P8S4S3P5m=1m=2m=1m=1m=2m=1m=1m=2m=1m=1m=2m=1Figure 4.7: Effect of winding arrangement on the value of m. a) Non-interleaved structure, b) partiallyinterleaved structure, and c) fully interleaved structure.4.3 Paired Layers Interleaving for Flyback and Forward ConvertersIn this section, the concept of paired layers is combined with interleaving methods to develop paired layersinterleaving method for Flyback converter, which belongs to the first category of power converters discussedin section 3.2. The same winding structures are also applicable on Forward converter, as paired turns are sim-ilar in Flyback and Forward converters. This method results in Flyback/Forward PTs that not only generatealmost zero CM noise, but also have very low AC resistance and leakage inductance.The implementation of the proposed principle depends on the number of turns in the primary and sec-ondary. For low voltage applications, the number of required turns is not too high. Therefore, single-turncopper foils can be connected in series to make a complete winding. Under this condition, the proposedmethod can be implemented easily, as all layers consist of one turn. However, if the input (or output) voltageis high, such as for adapters with universal input voltages (85-265 VAC), then a large number of turns isrequired. Under this condition, it is not possible to use a single-turn copper foil for every layer, as the spacein the core is very limited and cannot accommodate many copper layers. In this case, a combination of PCBand single-turn copper foils is used to implement the proposed idea. In this section, both conditions areconsidered and a procedure for implementing the proposed idea for both scenarios is proposed. By follow-ing the procedure that is presented for these transformers, high-efficiency PTs with no CM noise generationproperty can be designed.684.3.1 Implementation of the Proposed Method for PTs With Small Numbers of TurnsThe number of turns is directly proportional to the applied voltage. For low voltage applications, few turnsare needed and windings can be made using single-turn copper foils that are connected in series. In thissituation, the number of layers for each winding is at least equal to the number of turns, as each layerconsists of only one turn. If some layers are connected in parallel (to reduce resistance), the number oflayers will be more than the number of turns. The focus of this subsection is on showing the applicabilityof the paired layers interleaving method to PTs with a small number of turns. In order to explain how theproposed idea can be applied to these PTs, the method is implemented for different turn ratios.Fig. 4.8 explains how paired layers interleaving can be applied on a 7 : 4 PT. Figure 4.8 (a) shows thepaired layers on the primary and secondary sides and shows that four turns on the primary side have a pairon the secondary side. The remaining three turns of the primary side do not have a pair on the secondaryside and, therefore, should be avoided in the intersections. Any structure that satisfies this condition will leadto CM noise elimination. Figure 4.8 (b) shows one simple structure that satisfies this condition. As shownin this figure, only paired layers overlap with each other in this structure. In this structure, seven layers ofthe primary are connected in series to make a seven-turn winding. The four layers of the secondary are alsoconnected in series to make a four-turn secondary winding. Therefore, there are no parallel layers in thisP7P4S4S3P3P6P2S2S1P1P5(b)(a) (c)S1P1S1P5P1P2P7S2S3P3P6P4S4S4P4P6P3S3S2P2S1S2S3S4P7P5P6P3P4P1P2Layers with no pair on the secondary}Paired LayersPrimarySecondaryFigure 4.8: Interleaved winding arrangement with low AC resistance/leakage inductance and no CMnoise generation for a 7 : 4 PT: a) Paired layers in the primary and secondary windings. b) and c)Examples of paired layers interleaved structures.69structure. However, if the core window can accommodate more layers, it is desirable to add more layersin parallel and reduce the resistance. Adding more layers also makes it possible to allow more interleavingand, consequently, to achieve lower leakage inductance. Figure 4.8 (c) shows the same transformer withmore layers. In this arrangement, the secondary has eight layers (two layers per turn, connected in parallel).Since each layer of the secondary winding requires a pair in the primary side (to achieve noise cancellation),there should be eight paired layers in the primary. In other words, each of the first four turns of the primary(which have a pair in the secondary) are made using two layers in parallel, while the unpaired turns arerealized using only one layer. The above explanation can be seen in Fig. 4.8 (c), as the layers with the samename are connected in parallel. In this figure, parallel layers are also identified using small rectangles of thesame color. Both structures in Fig. 4.8 also start and end with a secondary layer, which blocks CM noisegeneration injection from primary to the core and so avoids CM noise propagation through the core. As aresult, both of these arrangements meet the requirements to achieve zero CM noise generation.The key requirements in implementing paired layers interleaving are as follows:1. Only paired layers of primary and secondary should overlap each other. The layers that do not have apair in the other winding should not be placed in the intersections. This ensures that no CM noise willbe generated.2. Legal intersections (overlapping between paired layers) should be used to design an interleaved struc-ture that minimizes leakage flux. This results in low leakage inductance and AC resistance.3. If parallel layers are used in the winding, they should have similar positions in terms of proximityeffect. Otherwise, one of the conductors will carry most of the current.4. It is desirable to start and end the winding arrangement with secondary layers to avoid CM noisegeneration through the core.Following the above criteria for PTs will lead to the creation of high-efficiency PTs that do not produceCM noise, in spite of their very large inter-winding capacitance. The above rules can be applied to transform-ers with different turn ratios, and without restrictions in turns ratio values. Figure 4.9 (a) shows an optimizedwinding arrangement that satisfies the no-noise generation requirement and low leakage inductance for a 6:3Flyback PT. In this figure, parallel layers are also identified using small rectangles of the same color. Toillustrate the structure better, a three dimensional model of this structure is shown in Fig. 4.9 (b). Figures4.9 (a) and (b) show that the above rules are applied to this structure. Therefore, it is expected that this trans-former generates no CM noise and at the same time achieves low AC resistance and leakage inductance. To70P4P1P1P2S2S1S1S3P3P6P3S3S2P2P5P5P6P3P4P1P2S3S1S2Layers with no pair on the secondary(a) (b)}Paired LayersPrimary ViewSecondary ViewPrimarySecondaryFigure 4.9: An example of paired layers interleaved structure for a 6 : 3 PT. a) The proposed structureand b) a 3D model of the structure from both sides.confirm this claim, this transformer has been simulated using FEA. According to the FEA results, the totalleakage inductance from the primary side is equal to 130 nH which is much lower than leakage inductanceof an equivalent wire-would Flyback transformer (typically in the range of few uH).In this subsection, the paired layers interleaving method has been implemented for PTs with a few turns oneach side. The typical application of these PTs is in low voltage Flyback and Forward converters. Windingsin such PTs can be realized using single-turn copper foils that are connected in series. It has been shown thatthe proposed idea can be implemented easily for different turn ratios. In addition to the proposed CM noisecancellation method, the criteria for achieving low leakage inductance have been provided. Therefore, theresulting PTs not only generate no CM noise but also have very low leakage inductance which improves theperformance and efficiency of Flyback converters.4.3.2 Implementation of the Proposed Method for PTs With a Large Number of TurnsFor higher voltage levels, the number of turns should increase to limit the flux density within the core. Forinstance, given the relatively small size of the cores that are used in low power transformers, the transformersthat are used in Flyback adapters with universal voltage range (85-260 Vac) should have a large number ofturns in the primary side. If the number of turns in a winding is high, it is not practically possible to makethat winding using single-turn copper foils. This is mainly due to the limited space in the core, which cannotaccommodate many layers. Besides, a large number of turns require many terminations, which makes it71difficult in small width core design. In this situation, spiral PCB designs can facilitate the creation of manyturns in one layer. As explained in section 4.1, this means that four-layer PCBs or a combination of PCB andcopper foil can be used to make the PCB with a large number of turns.Fig. 4.10 (a) shows an interleaved paired layers structure for a 24 : 4 Flyback PT. Under this condition,only the first four turns of the primary have a pair on the secondary side. The remaining 20 turns do not havea pair on the secondary and, therefore, should not overlap with the secondary winding. In this case, the firstfour turns of the primary are realized using single-turn layers. These four layers can overlap with their pairon the secondary side. The remaining 20 turns are realized using two double-layer PCBs. Each PCB has 10turns (five on each side), and PCBs are placed between single-turn layers of the primary side to hide themfrom the secondary winding. On the other hand, the secondary winding consists of four single-turn copperfoils that are connected in series. As shown in Fig. 4.10 (a), only paired layers overlap in the structurewhich avoids CM noise coupling from primary to secondary. For example, P3 only overlaps with its pairwhich is S3. Beside satisfying paired layers requirement, the top and bottom layer of the structure belongs tothe secondary winding which blocks CM noise injection from primary to the core. Therefore, this structurevirtually does not generate any CM noise.Fig. 4.10 (b) shows the implementation of the proposed method for a PT with 36 : 3 turn ratio. The firstthree turns of the primary side have a pair on the secondary. These turns are realized using single-turn copperfoils, and the remaining 33 turns are made using PCBs. Each PCB has 11 turns and the PCBs have beenplaced between the layers of the primary to avoid overlapping with the secondary winding. Examining thestructure that is proposed in Fig. 4.10 (b) confirms that only paired layers meet each other in this structure.Besides, the parallel layers in the secondary side are placed symmetrically from both ends, which ensureseven current sharing and low AC resistance. Therefore, this structure also does not create CM noise andprovides very low AC resistance and leakage inductance.In this section, the concept of paired layers has been employed along with interleaving methods to achievewinding structures with very low leakage inductance and close to zero CM noise generation for Flyback PTs.It has been shown that the proposed solution does not have any limitation regarding the turns ratio values,and can be applied to transformers with both large and small numbers of turns. If the number of turnsis small, the solution can be implemented using single-turn copper foil layers. If the number of turns islarge, a combination of single-turn copper foils and PCBs can be used to implement the idea. Therefore, theproposed method can be implemented for any turns ratio. While implementing the proposed method adds abit of complexity to the design of the PT structure, the benefits of employing the method are significant and72S1S1S2S3S4P1P2P3P4S2S3S3S2S1P1P2P3P3P2P1P26-P36P15-P25P4-P14P5-P14P15-P24(a) (b)S1S2S3S4P23P24P3P4P5P1P2Layers with no pair on the secondary}Paired Layers..S1S2S3P35P36P3P4P5P6P1P2Layers with no pair on the secondary}Paired Layers..Figure 4.10: Implementation of the proposed method for PTs with large turn ratios: Implementation ofthe method for a) a 24 : 4 PT and b) a 36 : 3 PT. Both of these structures satisfy the requirement ofno CM noise generation (as only paired layers overlap) and low AC resistance criteria (placingparallel layers in symmetrical positions from both ends).73make using the method worthwhile.4.3.3 Experimental VerificationIn order to confirm the validity of the proposed techniques, extensive experimental tests have been done.Fig. 4.11 (a) shows the prototype of a PT that is realized using the proposed method. The structure of thistransformer is similar to Fig. 4.9. The specifications of this transformer are also presented in table 4.1. Sincethis transformer has a highly interleaved structure, the value of leakage inductance is extremely low. On theother hand, since primary and secondary overlap each other several times (as a result of interleaving) andthe overlapping layers are tightly placed next to each other, the value of parasitic capacitance is a very largevalue of 700 pF which is large enough to make serious EMI problems. However, since this transformer hasbeen manufactured using paired layers interleaving method, it will be shown that this transformer generatesextremely low levels of CM noise. In order to validate the method, the result of the proposed planar trans-former with 700 pF inter-winding capacitance is compared with a wire-wound transformer which only has aTable 4.1: Experimental Platform PrametersFlyback Converter Planar Transformer Wire-WoundVin 72V Np/Ns 6/3 Np/Ns 6/3Vo 24V Copper 0.125 mm Wire LitzP 100W Core ER 32/6/25 Core RM 12f 150 kHz Cinter 700 pF Cinter 10 pFLm 42µH Llk−p 130 nH Lleak 1µHRAC−p 23 mΩS2S1V(a) (b)d410 kΩ321C13C24VRCpCswCpC14C23-+i14iCM-tri≈0i≈0High Impedance Path-Most of Trans CM noiseReturnsThrough ResistoriCM-swi13i24i23C =700 pFps C =10 pFps`Low Impedance Path-Voltage over R visualizestransformer CM noiseFigure 4.11: a) The prototype of the proposed PT along with an equivalent wire-wound transformer. b)The circuit that is used to signify the CM currents caused by the inter-winding capacitance.74(a) (b)CM currents Very low CM currentsWire-wound with 10pF inter-winding Cap The proposed Planar Transformer with 700pF inter-winding CapSwitching Moment Switching MomentV/div100V/div10V/div100V/div10V =R ICMR*V =R ICMR*Figure 4.12: Waveforms of the circuit of Fig. 4.11 (b) with a) the wire-wound transformer and b) theproposed PT. The DC bus voltage and the switching frequency are equal to 100V and 200kHz,respectively. Output voltage of the inverter (ch1), voltage across the resistor between the primaryand secondary (ch2).parasitic capacitance of 10 pF (70 times less). This transformer is shown in Fig. 4.11 (a) and its specifica-tions are presented in table 4.1. In this part, we will show that the proposed PT generates significantly lessCM noise than this transformer, although its parasitic capacitance is 70 times more.The first test intends to separate and visualize the common mode current caused by the transformer’sinter-winding capacitance and proves that the proposed PT generates very little CM noise. Since the standardmethod of measuring conducted noise at the input side cannot separate the noise of different elements, thecircuit that is shown in Fig. 4.11 (b) is used as a test circuit for observing only the CM noise that is generateddue to the inter-winding capacitance of the transformer [47]. As there is one terminal with static voltageand another terminal with swinging voltage, the transformer’s voltage is similar for Flyback and Forwardconverters. Therefore, the transformer’s behavior in terms of CM noise generation is similar to the behaviorwhen used in Flyback and Forward converters There are two sources of CM noise in Fig. 4.12 (b): Thefirst one is the parasitic capacitance between the drain and heatsink of the switch. Another source of CMnoise is the parasitic capacitance of the transformer. Since the secondary side is open, no current is inducedin the secondary winding through magnetic coupling and the current at the secondary side consists of onlyCM noise currents of the transformer. As is shown in Fig. 4.11 (b), the CM noise currents of the switchand transformer propagate in the circuit and return to their source through the earth. In order to separatethe transformer CM noise, a resistor has been added between the quiet point of the secondary and the earth.Since the impedance of this resistor is much less than the impedance of parasitic capacitances betweenthe secondary nodes and the earth, most of the transformer CM noise currents complete the path throughthis resistor. Under this condition, the resistor voltage is a representation of the transformer’s CM noise.75Figs. 4.12 (a) and (b) show the voltage across the resistor with the wire-wound transformer and the PTemployed in the circuit, respectively. Since the wire-wound transformer has significantly less inter-windingcapacitance (70 times less), the general expectation is that it will generate considerably lower CM noisecurrent. However, the experimental results are presented in Fig. 4.12 (a) and (b) show that the proposed PTwith a very large inter-winding capacitance of 700 pF generates extremely low levels of CM noise (closeto zero). In other words, the proposed method enables the use of highly interleaved structures for PTs thatminimize AC resistance and leakage inductance, while simultaneously generating almost zero CM noise,despite having large inter-winding capacitances.For the second test, the proposed PT has been employed in a Flyback power converter to confirm thesuperiority of the proposed method in terms of noise reduction. The specification of the converter is presentedin table 4.1. Line Impedance Stabilization Networks (LISN) have been placed at the input of the converterand the total conducted noise has been observed with a spectrum analyzer. The conditions of both testsare the same and the same Flyback converter with RCD snubber is used. Figures 4.13 (a) and (b) show(b)(a)akael wol fo tluser a sa sserts egatloV woL)Hu 1( ecnatcudnI egakael yb desuac sserts egatloV rehgiH ge Inductance of PT (130 nH)A/div5V/div10V/div100A/div5V/div100VswIPrimaryVswIPrimaryFigure 4.13: Waveforms of the Flyback converter with different transformers. Switch voltage (Ch1)and primary current (Ch2). Waveforms with a) the wire-wound transformer and b) with theproposed PT.(a) (b)Although having just 10 pF inter-winding cap,the generated noise of wire-wound transformeris more than the proposed PT with 700 pF cap.8-10 dB less noise in despite of 700 pF inter-windingCap using the proposed winding method. db/μV110 db/μV90 db/μV90 db/μV110 db/μV10 db/μV10 Red: Noise peak amplitude with wire-wound transformer Green: Noise peak amplitude with Proposed PTStart Frequency: 150kHz Stop Frequency: 30 MHz Start Frequency: 150kHz Stop Frequency: 30 MHzFigure 4.14: The spectrum of conducted mode noise of the Flyback with a) wire-wound transformer,and b) the proposed PT.76Static PointCh1Ch1 Ch1Ch4Ch2Ch3Ch6Ch5Ch2 Ch3Ch2Ch3Ch4Ch5Ch6Paired Layers(a)(b)Ch4Ch5Ch6Layers with no pair on the secondary}SELayers with no pairLayers that have pair on the secondary sideand can overlap withtheir pairs.The proof that shows Paired layers have similar voltage distribution. Overlapping ofsuch layers does not make CM noise.Layers with no pairwhich do not overlap with secondary layers.V/div100V/div100Figure 4.15: a) Ch1 to Ch6 show the voltage distribution over the primary winding. b) Ch1 to Ch3and Ch4 to Ch6 are the voltage distribution over the first three turns of the primary and theircorresponding pair on the secondary, respectively.the waveforms of the converter with PT and the wire-wound transformer, respectively. Due to the largeleakage inductance of the wire-wound transformer, the switch voltage has a considerably larger spike atturn-off. On the other hand, the proposed PT has a very small leakage inductance which is the result of ahighly interleaved structure and leads to less voltage spike on the switch. Figures 4.14 (a) and (b) show thespectrum of conducted noise with wire-wound transformer and the proposed PT, respectively. These figuresshow that while the proposed PT has a very high parasitic capacitance of 700pF , it produces less noisethan does a traditional transformer whose parasitic capacitance is 70 times less. These results show thatthe proposed method has resolved the trade-off between low leakage inductance and the noise due to inter-winding capacitance, leading to a new generation of PTs that have low leakage inductance and extremelylow noise generation at the same time.Finally, as it was explained in chapter 3, the winding method relies on the proposed concept of paired77layers which tries to overlap layers that have similar voltage waveforms (and so similar dvdt ) to avoid thegeneration of CM noise. Therefore, it is also interesting to compare the voltage of paired layers to confirmthe concept of paired layers and show why the proposed method leads to no generation of CM noise. Figure4.15 (a) shows the voltage distribution along the primary winding. As shown in this figure, the first pin of theprimary has a static voltage waveform which is not affected by the switching of the converter. The amplitudeof voltage swinging increases after each turn and reaches its maximum after the last turn. Since this is a6:3 transformer, the first three turns of the primary can be paired with the secondary layers. The remainingthree layers of the primary do not have a pair on the secondary side and, therefore, should not overlap withsecondary layers (the structure was shown in Fig. 4.9). To confirm this hypothesis, another measurement isdone which is shown in Fig. 4.15 (b). Figure 4.15 (b) shows the voltage of paired layers on the primary andsecondary sides. As it was expected, these layers have a similar voltage waveform (the same dvdt ). As it wasexplained and analytically proved in chapter 3, the overlapping of such layers does not produce CM noise.The experimental results verify that the proposed method successfully eliminates the trade-off betweeninter-winding capacitance and leakage inductance for Flyback PTs. Using this method, designers can use ahighly interleaved structure for Flyback PTs to achieve very low leakage inductance without the concern ofCM noise generation due to a large inter-winding capacitance of these structures.4.4 Paired Layers Interleaving for LLC Resonant ConvertersIn traditional PTs, the amount of the transformer’s CM noise depends on the number of overlapping betweenprimary and secondary layers. Interleaved structures that are used to reduce AC resistance generate signif-icant amounts of CM noise, as they have many overlapping between primary and secondary layers. Thismeans that traditional interleaved PTs reduce AC resistance at the expense of generating large amounts ofCM noise and so suffer from a trade-off between AC resistance and CM noise. In this section, the concept ofpaired layers is employed along with interleaving methods to develop paired layers interleaving method forhalf-bridge LLC resonant converter, which belongs to the second category of DC-DC converters discussedin section 3.3. It will be shown that the trade-off between low AC resistance and low leakage inductance willbe eliminated for LLC PTs by using paired layers interleaving method. This means that no matter how manytimes these PCBs overlap, no CM noise will be generated, and so the designer is free to use any structurewithout the concern of CM noise generation.784.4.1 Implementation of the Paired-Layers in Two-Winding LLC PTsAs discussed before, if the number of turns is large in a winding, four-layer or two-layer PCBs are usedto make the winding. Each of the proposed PCBs in section 4.1 makes a complete winding, and so onlytwo PCBs−one for the primary and one for the secondary winding−are required to make the transformerstructure. So, in its simplest form, the structure of the transformer only has one primary PCB and onesecondary PCB. However, depending on the requirements and specifications, the designer may choose touse several PCBs in parallel or series for each winding to reduce the resistance of the winding. Selectingthe transformer’s structure depends on a number of factors. For instance, if the design is cost-driven, thedesigner might be limited to use only one primary PCB and one secondary PCB (to reduce the cost), thuschoose a non-interleaved structure. Depending on the isolation requirements, the designer might not be ableto use an interleaved structure. For low voltage and high current applications, the designer might use severallayers in parallel for each winding (to reduce DC resistance of the windings) and also use a very interleavedstructure to minimize AC resistance. In all different scenarios, the use of the proposed methods guaranteesthat almost no CM noise will be generated in the PT.In order to show how the structure of PT affects the AC resistance and loss, Fig. 4.16 shows four differentstructures for a 16 : 8 PT. The layout of primary and secondary PCBs is similar to the layouts of Fig. 4.2(b) and so the CM noise generation of all these structures is minimal (because no matter how many timesprimary and secondary overlap, their overlapping does not generate CM noise). Figure 4.16 (a) shows thesimplest structure that only has one PCB for primary and one PCB for secondary. This is a non-interleavedstructure with a minimum cost that can be used in applications that have strict requirements regarding costor isolation. However, the winding resistance is high and so it cannot be used in high current applications.It also does not block the CM noise generation path through the core, as the primary winding is exposedto the core. For higher current levels, it is possible to have multiple PCBs in parallel for each winding toreduce the resistance and conduction loss. Adding PCBs in parallel is only effective if the current is sharedevenly between the PCBs. This requires that parallel PCBs have symmetrical positions in the transformer’sstructure, such as the structure of Fig. 4.16 (b). Otherwise, due to the skin and proximity effects, the currentis not equally shared between the PCBs and only one PCB effectively conducts the current, which means thatthe added PCB is not helping to reduce resistance and conduction loss. Fig. 4.16 (b) shows an interleavedstructure with two PCBs for each winding that are connected in parallel. Using two PCBs for each windinghalves the DC resistance and placing the primary PCBs between secondary PCBs helps to reduce leakageflux and AC resistance. This structure also blocks the CM noise path through the core, as primary turns79(a) (b)(c) (d)RFEA Results201 mΩ67 mΩ50.5 mΩ72 mΩ 13.8 mΩ9.2 mΩ 12.3 mΩ100 mΩ 18.4 mΩ362 mΩ 174 mΩdc-pRac-pRdc-sRac-s36.8 mΩ64.5 mΩ 23.5 mΩRFEA Resultsdc-pRac-pRdc-sRac-sRFEA Results82.9 mΩdc-pRac-pRdc-sRac-s 18 mΩRFEA Resultsdc-pRac-pRdc-sRac-sJ(A/m )26.9e+073.2e+074.7e+06J(A/m )21.9e+071.0e+071.6e+06J(A/m )21.7e+070.8e+071.3e+06J(A/m )23.7e+071.8e+073.8e+06CuLoss@ 800W & 25V out9.9 WCore 1.2 WCuLoss@ 800W & 25V out2.0 WCore 1.2 WCuLoss@ 800W & 25V out2.5 WCore 1.2 WCuLoss@ 800W & 25V out4.3 WCore 1.2 WPrimarySecondaryFigure 4.16: Different structures for 16 : 8 turns ratio. The layouts of primary and secondary PCBswere shown in Fig. 4.2 (b). a) A non-interleaved structure with the minimum number of PCBs,b) a structure with two parallel PCBs for each winding, c) a structure with four parallel PCBsfor each winding and, d) a structure with three parallel PCBs for each winding. The thickness ofPCB traces is 3oz and the AC resistance results are reported at 200kHz.are not exposed to the core. Figure 4.16 (c) shows another structure with four PCBs in parallel for eachwinding. Comparing to Fig. 4.16 (a), the DC resistance is reduced four times. It also achieves a good currentsharing between PCBs, as parallel PCBs are positioned such that they experience similar leakage flux andproximity effect. This structure also blocks the CM noise generation through the core, as the primary PCBsare not exposed to the core. Figure 4.16 (d) shows a very interleaved structure that intends to minimizeproximity effect and so AC resistance. In this structure, the top and bottom PCBs should only have half ofthe secondary turns. According to this figure, this structure achieves a low AC/DC resistance ratio and equal80(b)P(1)S(2)S(4)S(4)S(3)P(3)P(2)P(4)S(1)S(1)P(2)S(2)P(1)P(6)P(5)P(7)P(1)S(3)S(4)S(2)P(8)P(2)S(1)S(3)P(2)S(1)S(3)S(4)S(4)S(2)P(8)P(6)P(7)P(1)P(5)P(4)S(3)S(2)P(3)P(1)P(2)S(1)S(3)S(4)(c)9.87e+66.58+63.90e+61.37e+6J (A/m )3RPrimary6.34 mΩ18.4 mΩ0.3 µHdcLlkRacSecondaryR 1.45 mΩ2.45 mΩ0.06 µHdcLlkRac8.08e+65.40e+63.25e+61.10e+6J (A/m )3RPrimary5.99 mΩ12.4 mΩ0.24 µHdcLlkRacSecondaryR 1.17 mΩ2.17 mΩ0.05 µHdcLlkRac(a)−160 8 12-12-8 16Flux Density (mT)−10−150 5-5 10 15Flux Density (mT)Current DensityCurrent Density2.02e+71.00e+71.42e+6J (A/m )3RPrimary7.24 mΩ29.7 mΩ0.37 µHdcLlkRacSecondaryR 3.55 mΩ6.25 mΩ0.05 µHdcLlkRacS(3)P(8)P(7)S(1)P(3)P(2)P(5)S(4)P(6)P(4)S(2)P(1)-3 10 2-2 -1 3Flux Density (mT)Current DensityPrimarySecondaryFigure 4.17: Different paired-layers structures with no CM noise generation for an 8 : 4 transformer.The layout of primary and secondary PCBs were shown in Fig. 4.6 (a) . Implementation of themethod with a) 12 layers, b) 20 layers and, c) 24 layers. Parallel layers have the same name andare identified using small rectangles of the same color. The thickness of layers are 0.25mm andthe AC resistance results are reported at 200kHz.current sharing between parallel layers. It also blocks the path from primary to the core and so minimizesCM noise generation through the core. This structure has been used in the experimental section to confirmthe validity of the proposed methods and techniques.As mentioned in the first section of this chapter (section 4.1.3), if the number of turns is small, single-turn copper foil layers can be used to make both windings. Figure 4.17 shows three different paired-layersinterleaved structures with a different number of layers for 8 : 4 turns ratio. Layers layout and paired layershave been shown in Fig. 4.6 (a). These layers are designed for ER/51/10/38 core and the copper thickness is0.25 mm. As shown in Fig. 4.17, all of these structures satisfy the requirement of no CM noise generation,as only paired layers overlap in these structures. Besides, all of these structures start and end with secondarylayers, and so they block the CM noise path from the primary winding to the core. Figure 4.17 (a) shows astructure with 12 layers for an 8 : 4 PT (8 layers for the primary and 4 layers for the secondary). Since thereare only two sets of paired layers, only two intersections are possible for this condition. Figure 4.17 (b) shows81another structure for the same turn ratio. This structure has 20 layers (10 layers for primary and 10 layersfor secondary). In this figure, parallel layers are identified using small rectangles that have the same color.Investigating this structure also reveals that only paired layers overlap, and therefore, this structure doesnot generate CM noise. Based on FEA results, the total AC resistance of winding reflected to the primaryside is reduced from 58.66mΩ to 28mΩ, which is the result of using more layers and a more interleavedstructure. Finally, Fig. 4.17 (c) shows another structure for the same turns ratio, but with 24 layers (12layers for both primary and secondary). This figure shows that only paired layers of primary and secondaryoverlap in this structure; therefore, it generates no CM noise. FEA results also confirm that this structure ismore successful in minimizing AC resistance and leakage inductance than the previous structures, as it hasa highly interleaved structure. These examples confirm that paired-layers interleaving method is general andcan be applied for different turns ratios, different numbers of layers, and different types of layers.4.4.2 Implementation of the Paired-Layers Method in Center-Tapped LLC PTsThe transformer’s voltage distribution is similar in two-winding and center-tapped transformers. Therefore,the presented PT structures of previous sections also can be used for center-tapped PTs to avoid CM noisegeneration. For instance, the same structures of Fig. 4.16 that were used for 16 : 8 turns ratio can also be usedfor 16 : 4 : 4 turns ratio and no CM noise would be generated. However, unlike two-winding transformers,the secondary winding in center-tapped transformers is divided into two windings and only one of thesewindings conducts at a time. Therefore, for the same turns ratio, the distribution of leakage flux in a center-tapped transformer is different from a two-winding transformer. Center-tapped transformers are used whenlow voltage and high current are needed at the output. Secondary windings have few turns (one or two turnsare common) and they conduct large amounts of current. As the current is high, secondary turns can berealized using copper foil layers (instead of PCB) to increase current handling capability. The objective ofthis part is to show different approaches in implementing the paired-layers method in center-tapped PTs andto study the performance of these transformers.Similar to two-winding transformers, depending on the design specifications, different structures can beused to make a center-tapped transformer. The only requirement is that the overlapping layers of the primaryand secondary have the same number of turns and the same dvdt . Figure 4.18 (a) shows primary PCB layoutand secondary copper-foil layers that satisfy this condition for 16 : 2 : 2 turns ratio. For this turns ratio, P(01)and P(02) are paired with S(02) and S(01), respectively, and only these turns are allowed to overlap. Asshown in Fig. 4.18 (a), the top layer of the primary (P(01)) overlaps with S(02) and the bottom layer of the82S2PS3S4S1S2PS3S4S1S2PS3S4S1S2PS3S4S1S2PS3S4S1S2PS3S4S1S2PS3S4S1S2PS3S4S1P and S1-S2 are conducting P and S3-S4 are conductingP and S1-S2 are conducting P and S3-S4 are conductingR 270 mΩ389 mΩdc-pRac-pR 1.96 mΩdc-s1R 2.63 mΩac-s1Rdc-s2Rac-s21.96 mΩ2.55 mΩJ(A/m )26.3e+073.0e+074.3e+06R 91.6 mΩ120 mΩdc-pRac-pR 0.676 mΩdc-s1R 1.15 mΩ0.676 mΩ0.94 mΩac-s1Rdc-s2Rac-s2(c)J(A/m )22.2e+071.1e+071.4e+06(a)(b)iCM =0Eligible Turns to OverlapP(01)P(04)P(16)S(04)S(03)S(02)S(01)No CM noise RegionS(01)S(03)S(04)S(02)P(01)Primary PCBP(03)-P(09)P(10)-P(16)P(02)P(01)S(02)S(01)P(02)No CM NoisePriSecSeciCM=0iCM=0No CM NoiseSecondary PCBS: StartE: EndS: StartE: EndESESTotal Cu Loss@ 800W & 25V out8.8 WCore Loss 1.2 WTotal Cu Loss@ 800W & 25V out3 WCore Loss 1.2 WS1-S2 S3-S4 P S1-S2 S3-S4 PS1-S2 S3-S4 P S1-S2 S3-S4 PLayouts for 16:4 or 16:2:2 LLC PT Figure 4.18: a) The proposed primary and secondary layouts for a 16 : 2 : 2 center-tapped PT to elim-inate CM noise. b) The implementation of the transformer with minimum number of layers. c)An interleaved structure by using three parallel windings for both primary and secondary wind-ings. The thickness of PCB traces and secondary layers are 3oz and 0.25mm, respectively, andthe AC resistance results are reported at 200kHz.83primary (P(02)) overlaps with S(01). Therefore, these layouts satisfy the requirement of the method. In themost basic form, a non-interleaved structure with the minimum number of layers (one PCB for primary andone copper foil layer for each secondary turn) can be used to make a 16 : 2 : 2 PT. If using more layers andinterleaved structures is possible, parallel layers can be used to reduce DC and AC resistance. Fig. 4.18(b) and (c) show two different structures for 16 : 2 : 2 turns ratio. In this figure, layers of one secondarywinding (S(01) and S(02)) are shown with purple color and layers of the other secondary winding (S(03) andS(04)) are shown with blue color. As mentioned earlier, each of the secondary windings conducts for half ofthe switching period. So each structure has been simulated twice and each time only one of the secondarywindings is conducting. Fig. 4.18 (b) shows an interleaved structure with the minimum number of layers forthis turns ratio. In this structure, only paired layers are overlapping and the core is only exposed to secondarylayers. Therefore, this structure does not generate CM noise. If the use of more layers is possible, a numberof Fig. 4.18 (b) structure can be connected in parallel to reduce windings’ resistance. Figure 4.18 (c) showsanother structure that is made by connecting three structures of Fig. 4.18 (b) in parallel. In this case, the DCresistance is reduced by a factor of three and the use of a more interleaved structure has helped to reduce ACresistance.Fig. 4.19 shows one implementation of the method for 16 : 1 : 1 turns ratio. In this case, the only pairedturns are P(1) and S(1) and no other turns of primary and secondary can overlap. Figure 4.19 (a) showsthe primary PCB layout and secondary copper foils to satisfy this condition. According to Fig. 4.19 (a),the primary PCB is designed in such a way that both top and bottom layers only have P(01) (which meansthat the top and bottom layers have the same turn and are connected in parallel) and P(02)−P(16) areplaced on the middle layers of PCB. Figure 4.19 (b) shows an interleaved structure using these layouts. Thestructure is such that the primary PCB always overlaps with S(01) and so it does not generate CM noise. Onedownside of this structure is the non-symmetrical placement of secondary windings. This causes the leakageinductance of secondary windings to be different, which is not desirable from the circuit operation point ofview. In addition, the layers of the non-conducting secondary in each half-cycle are exposed to large valuesof leakage flux, which induces extra eddy current loss in those layers.These issues can be solved by using the winding layout and structure of Fig. 4.20. As shown in thisfigure, it is possible to make a pair for S(2) on the primary side by adding an extra turn to the primarywinding. According to Fig. 4.20, the primary winding has 17 turns. However, the first turn is open and thewinding starts after the first turn. This turn is only connected to the primary winding from one end and isopen at the other end. By doing this, the dvdt of this extra turn will be similar to S(2). Figure 4.20 (a) shows84Eligible Turns to OverlapP(01)P(16)S(01)S(02)No CM noise RegioniCM =0P(01)S(01)S(01)P(01)No CM NoisePriSecSeciCM=0iCM=0No CM NoiseP(01)Primary PCB(Open)P(02)-P(08)P(09)-P(16)P(01)TerminalsS(01)S(02)(a)S1 S2 P S1 S2 PP and S1 are conducting P and S2 are conductingR134 mΩ99 mΩ 0.163 mΩ0.163 mΩdc-pRac-pRdc-s1R 0.479 mΩac-s1Rdc-s2Rac-s2 0.475 mΩ(b)J(A/m )23e+071.4e+071.9e+06Total Cu Loss@ 800W & 25V out4.1 WCore Loss 1.2 WS1PS2S2S1S1PS2S2S1S1PS2S2S1S1PS2S2S1S1PS2S2S1S1PS2S2S1SSEEFirst Layout for 16:1:1 LLC PTFigure 4.19: a) First proposed primary and secondary layouts for 16 : 1 : 1 center-tapped PT. Only S(01)and P(01) are allowed to overlap in this scheme. b) An interleaved structure that has a low ACresistance and no CM noise generation. The thickness of PCB traces and secondary layers are3oz and 0.25mm, respectively, and the AC resistance results are reported at 200kHz.the PCB layout that implements this idea. By using this PCB layout, both S(1) and S(2) can overlap with theprimary, and so it is possible to use the symmetrical structure of Fig. 4.20 (b). This structure achieves similarleakage inductance for secondary windings and also is designed in such a way that the non-conducting layersare always next to locations that have minimum leakage flux. As a result, this structure significantly reducesthe loss associated with eddy current in the layers of non-conducting secondary.As explained before, in traditional PCB layouts, turns are equally shared between layers of PCB. How-ever, using the paired-layers method causes the primary turns not to be shared equally between PCB layers.85S1 S2 PS1 is conductingS2 is offS1 S2 PP and S1 are conducting P and S2 are conducting(b)R99 mΩΩm 442.0Ωm 5.47 0.244 mΩdc-pRac-pRdc-s1R 0.545 mΩac-s1Rdc-s2Rac-s2 0.573 mΩTotal Cu Loss@ 800W & 25V out3.8 WCore Loss 1.2 WJ(A/m )21.9e+071.0e+071.3e+06Eligible Turns to OverlapP(-1) S(1)S(2)Primary PCB Secondary Copper Foil(Open)P(02)-P(08)P(09)-P(16)P(1)TerminalsP(01)P(-1)P(16)S(01)S(02)No CM noise RegioniCM =0Additional Turn that has similar dv/dt as S(02).It is open and do not transfer power.P(-1)S(02)S(01)P(01)No CM NoisePriSecSeciCM=0iCM=0No CM Noise(a)PS2S2S1PS2S1PS2S1PS1PS2S2S1PS2S1PS2S1PS1SESESecond Layout for 16:1:1 LLC PT Figure 4.20: a) Second proposed primary and secondary layouts for 16 : 1 : 1 center-tapped PT. Anadditional open-ended turn (called P(-1)) is added to the primary that creates a pair for S(02). Inthis scheme, S(01) can overlap with P(01) and S(02) can overlap with P(-1). b) An interleavedstructure using these layouts that has symmetrical secondary windings, low winding loss, and noCM noise generation. The thickness of PCB traces and secondary layers are 3oz and 0.25mm,respectively, and the AC resistance results are at 200kHz.As shown in Figs. 4.19 and 4.20, for large turns ratios, most of the primary turns are placed on mid-layersand the top and bottom layer is not used effectively which increases the primary winding resistance. How-ever, since the dominant source of loss for this turns ratio is the secondary windings, which is not affectedby the use of the proposed method, this increment in primary resistance does not have a significant effect onthe total loss of the PT. In order to quantify the extra loss that is caused by using the proposed PCB layouts,the loss of an equivalent traditional PT has been analyzed using FEA. Fig. 4.21 shows a PT with a traditionalPCB layout for primary and the same structure as Fig. 4.20 (b). According to this figure, using the proposedwinding layout increases the transformer’s loss from 4.4W to 5W . Although the conduction loss is increased86S1 S2 P S1 S2 PP and S1 are conducting P and S2 are conductingR56 mΩΩm 442.0Ωm 1.14 0.244 mΩdc-pRac-pRdc-s1R 0.545 mΩac-s1Rdc-s2Rac-s2 0.57 mΩJ(A/m )21.9e+071.0e+071.3e+06P(01)-P(04)Primary PCB Secondary Copper FoilP(09)-P(12)P(13)-P(16)P(05)-P(08)SES: StartE: EndS(01)S(02)(a)(b)SETotal Cu Loss@ 800W & 25V out3.2 WCore Loss 1.2 WS1PS4S2PS4S2PS4S2PS2S1PS4S2PS4S2PS4S2PS2Traditional Layout for 16:1:1 LLC PT Figure 4.21: A traditional 16 : 1 : 1 PT with the same structure as Fig. 4.20. (a) The layout of theprimary PCB and secondary copper foils. (b) The structure of the PT and current distribution inthe layers. Comparing the loss results shows the use of the proposed method increases the totalloss from 4.4W to 5W (which is the cost of using the method to eliminate the transformer’s CMnoise). The thickness of PCB traces and secondary layers are 3oz and 0.25mm, respectively, andthe AC resistance results are reported at 200kHz.a bit in the proposed PT, this extra loss is justified by considering the benefits of minimizing the transformer’sCM noise. These benefits include the use of smaller and cheaper CM chokes in the converter’s EMI filter.Smaller CM chokes also have a lower loss which compensates for the extra loss in the transformer.In this section, the proposed winding layouts of section 4.1 have been used to design several LLC PTsfor different turns ratios. It was shown that the proposed winding layouts can be used to design interleavedstructures with low AC resistance and no CM noise generation: two features that do not come together usingthe traditional transformer designs. The proposed method is general and can be applied to different turns87ratios.4.4.3 Experimental VerificationIn order to confirm the validity of the proposed methods, extensive experimental tests were done. An 800WLLC resonant converter was used to evaluate the performance of paired layers interleaving in terms of CMnoise reduction. The experimental platform is shown in Fig. 4.22 (a). Tests were performed using thesuggested setup for measuring conducted noise, and Line Impedance Stabilization Networks (LISN) andspectrum analyzer have been used at the input of the converter to measure the noise. As the proposedmethod only targets CM noise, Differential-Mode (DM) noise was eliminated from the measured noise andthe comparison has been made on CM noise only. The parameters of this experimental platform are shownin Table 4.2.Three transformers have been manufactured and tested to show the advantages of the proposed method.Figure 4.22 (b) shows these three transformers. The first transformer is a regular 16 : 8 PT. The layoutTable 4.2: Experimental Platform SpecificationsLLC Converter Test Equipments Transformers’ SpecificationsVin 400v LISN lI-125A Np/Ns 16:8 and 16:1:1Vo 100V Spectrum Analyzer RSA360B PCB Trace Thickness 3 OzP 800 W Copper Foil Thickness 0.25 mmfr 200 kHz PCB Thickness 1mmfsw 200 kHz Core E43/10/28 3F3MOSFET IXFH60N65X2Diode B40250TGLISNEUT(a) (b)Regular PT(16:8)(C =1.21 nF)SecondarypsProposed PT(16:8)(C =1.28 nF)psProposed PT(16:1:1)(C =1.08 nF)psPrimaryLISN: LI-125ASpectrum Analyzer:RSA360BFigure 4.22: a) Test setup for measuring conducted mode noise. b) Prototypes of transformers understudy.88and structure of this transformer are shown in Fig. 4.23 (a). The second transformer is a 16 : 8 PT that ismade using the paired layers interleaving method. The layout and structure of this transformer are shownin Fig. 4.23 (b). According to Fig. 4.23 (b), the top layer of the primary PCB and the bottom layer ofthe secondary PCB in the proposed PT have similar dvdt and so their overlapping is expected not to generatenoise. The same is true for the bottom layer of the primary PCB and top layer of the secondary PCB in theproposed PT. As shown in Fig. 4.23, both transformers have the same structure and so the same numberof overlapping between primary and secondary layers. This means that the static inter-winding capacitance(measured between primary and secondary windings) is approximately equal. It will be shown that whileboth transformers have a similar inter-winding capacitance, the proposed PT generates significantly lessCM noise, which is the result of overlapping layers with similar dvdt . To confirm this claim, these PTs were(b)(a)67 mΩ 12.4 mΩRFEA Results82.9 mΩdc-pRac-pRdc-sRac-s 18 mΩ2.5 WLossWindingLossCore 1.2 WJ(A/m )21.9e+071.0e+071.6e+0655 mΩ 12.4 mΩRFEA Results73.1 mΩdc-pRac-pRdc-sRac-s 18 mΩ2.3 WLossWindingLossCore 1.2 WJ(A/m )21.7e+071.0e+071.6e+06S(01)-S(02)S(05)-S(06)S(07)-S(08)S(03)-S(04)P(01)-P(02)Primary PCBProposed PTTraditional PTSecondary PCBP(05)-P(10)P(11)-P(16)P(03)-P(04)SS: StartE: EndS: StartE: EndESES(01)-S(02)S(05)-S(06)S(07)-S(08)S(03)-S(04)Secondary PCBS: StartE: EndEP(01)-P(04)Primary PCBP(09)-P(12)P(13)-P(16)P(05)-P(08)ES: StartE: EndSSPSPSPSSFigure 4.23: The comparison of the proposed PT with a traditional PT for 16 : 8 turns ratio. PCBlayouts, structure, current distribution in layers, and loss results for a) the traditional PT andb) the proposed PT. The thickness of PCB traces and secondary layers are 3oz and 0.25mm,respectively, and frequency is 200kHz.89dBμV150 dBμV0 Start Frequency: 150kHzdBμV15 Stop Frequency: 30 MHz11.25dbuV200kHz9.11dbuV20.29dbuVdBμV150 dBμV0 Start Frequency: 150kHzdbμV15 Stop Frequency: 30 MHz(b)(a)200kHzRed: Traditional PT Green: Proposed PTFigure 4.24: Comparison of conducted noise of the LLC converter with a) the regular PT and b) theproposed PT. Using the proposed method significantly reduces the CM noise which results insmaller filter size and enhanced power density of the converter.employed in the LLC resonant converter and the CM noise of the converter in each case was measured.Figures 4.24 (a) and (b) show the measured CM noise of the converter with the regular PT and the proposedPT, respectively. As shown in this figure, the proposed PT generates significantly less CM noise in mostfrequencies and the difference reaches 20.29 dBµV . This means that much smaller CM chokes are requiredto filter CM noise, considerably increasing the power density of the converter.The proposed concept and method have also been verified by another experiment. For this experiment,a 16 : 1 : 1 PT was manufactured and tested under different conditions. This transformer, along with itsprimary PCB and secondary copper foil, is presented in Fig. 4.22 (b). The PCB layout of the primary, thelayout of secondary copper foils, and the transformer’s structure are similar to those in Fig. 4.20. If the quietpoint of the primary (the terminal that goes to the DC bus) is connected to the first turn of primary (the onethat overlaps with secondary), the dvdt of overlapping primary and secondary layers would be similar, and soit is expected no CM noise will be generated as a result of this overlapping. However, if the quiet terminalof the primary is connected to the sixteenth turn of primary, it causes very large dvdt on the turns that overlapwith secondary layers. In this case, dvdt of overlapping primary and secondary layers are very different whichdb/μV150 db/μV0 Start Frequency: 150kHzdb/μV15 Stop Frequency: 30 MHz(a) (b)12.7dbuV8.7dbuVdbμV dbμV : dbμV t r cy: zdb/μVdb/μV0 Start Frequency: 150kHzdbμV15 Stop Frequency: 30 MHzdbμV150 dbμVRed: Correct Connection Green: Incorrect ConectionFigure 4.25: CM noise of the converter with different connections. a) incorrect connection and b)correct connection. it is necessary that quiet point is connected to the first turn of the primarywinding, so overlapping layers of primary and secondary have a similar dvdt .90causes a significant amount of CM noise. Figure 4.25 shows the CM noise of the converter with the sametransformer under different conditions. As shown in this figure, the same transformer generates significantlylower CM noise if the quiet point of the converter is connected to the correct terminal of the primary winding.This result shows the significant effect of dvdt of overlapping layers which makes for another proof of conceptof the method.In this section, experimental tests have been presented to validate the paired layers interleaving method.Using the proposed method, the converter’s CM noise has been reduced significantly in most frequenciesand the attenuation reaches 20.29 dBµV . This CM noise reduction results in smaller CM choke filters andimproves the power density of the converter.4.5 SummaryIn this chapter, the concept of paired layers have been combined with interleaving methods to design PTs thathave it all: low leakage inductance, low AC resistance, and almost zero CM noise generation. Dependingon the number of turns, different winding layouts for implementing paired layers concept using multi-layerPCBs, copper foils or a combination of both have been investigated and proposed. The effect of windingarrangement on AC resistance has been briefly discussed and interleaving methods to reduce AC resistancehave been presented. Once the concept of paired layers is combined with interleaving methods, the resultingmethod is called paired layers interleaving.Paired layers interleaving was used to design a number of Forward/Flyback PTs for different turns ratios.These designs have been validated using FEA and it was shown that they all have low leakage inductanceand AC resistance which is the result of their highly interleaved structures. Experimental tests were usedto confirm the superiority of the proposed PTs regarding CM noise reduction. In one case, it was shownthat a Flyback PT designed with paired layers interleaving generates even less CM noise than a wire-woundtransformer that only has 7pF parasitic capacitance. This example shows that paired layers interleavingdoes not address the CM noise problem by reducing the parasitic capacitance. Instead, it avoids CM noisegeneration by making the dvdt of overlapping layers similar. In other words, PTs designed with paired layersinterleaving have large parasitic capacitance, but they do not generate CM noise.Paired layers interleaving was also used to design a number of LLC PTs for different turns ratios, anddifferent types of windings (two-winding, center-tapped). Since only half of the secondary turns have a pairon the primary, an extension of the paired layers concept was also introduced which creates pairs for theseturns by adding auxiliary open-ended turns to the primary. The proposed LLC PTs were analyzed using FEA91and it was shown that they all have low AC resistance and leakage inductance. Experimental tests have beendone for two cases and it was shown that a LLC PT designed with paired layers interleaving generates up to20.29 less CM noise than does an equivalent regular PT.92Chapter 5Low Parasitic Planar Transformers for LLCResonant Converters1As explained in chapter 1, capacitive effects in the transformers are divided into inter-winding and intra-winding capacitors. While intra-winding capacitance originates from the capacitive coupling between layersof the same winding, inter-winding capacitance is the result of capacitive coupling between layers of differentwindings (i.e. one from primary and another form secondary). These parasitic capacitors are distributed andare visualized in Fig. 5.1 (a). The total effect of distributed parasitic capacitance can be modeled by sixdifferent capacitors in the transformer equivalent circuit, which is shown in Fig. 5.1 (b). The distributedintra-winding capacitance of each winding can be modeled as a lumped capacitor between terminals of thatwinding. These capacitors are shown with the purple color in Fig. 5.1. On the other hand, the effect ofdistributed inter-winding capacitance can be modeled by four capacitors between primary and secondaryports of the transformer which are shown in red color in Fig. 5.1.Both intra- and inter-winding parasitic capacitors have detrimental effects on the performance of DC−DCconverters. The high intra-winding capacitance gives rise to a high charging current at the transformerinput, resulting in lower efficiency and increased peak voltage stress across secondary rectifying devices. Inaddition to those problems, parasitic capacitances also bring unwanted regulation issues for LLC resonantconverters with wide output regulation. The effect of inter-winding capacitance is even worse, as it is oneof the main sources of CM noise in the power converter. In previous chapters, paired-layers interleavingwas introduced as a method that avoids CM noise generation when primary and secondary layers overlap.The basis of this method is to avoid CM noise generation by only overlapping layers that have a similar1Portions of this chapter have been published in [5–7]93RC LmLlk1Rac1 Llk2Rac2CIntra-p CIntra-sCInterCInterCInterCInter+-vsvp+-CIntra-pCInterCInterCIntra-sCIntra-p(b)(a)PrimarySecondaryFigure 5.1: a) Distributed parasitic capacitance in PTs. b) Transformer’s equivalent circuit.dvdt . Without going to details of the transformer’s parasitic capacitance model (which was presented in theprevious chapters), this can be explained by 5.1 which presents the general relationship between voltage andcurrent of a capacitor.i =C(dvdt)(5.1)Paired-layers interleaving makes CM noise equal to zero by making dvdt term equal to zero. Anothermethod of reducing CM noise is to reduce the value of parasitic capacitance. In this chapter, methods ofreducing both intra-winding and inter-winding capacitors are presented for PTs that are made using multiple-turn PCB windings. In particular, the detrimental effect of intra-winding capacitance on voltage regulationof LLC resonant converter under light-loading condition is considered, and layouts that have a significantlylower intra-winding and inter-winding capacitors are proposed to resolve this problem.5.1 Effect of Parasitic Capacitors on Light-Load Voltage Regulation ofLLC Resonant ConverterIn a high-frequency LLC converter, magnetic components often are the bulkiest parts, and they determine theoverall height of the converter [74]. Due to the height of traditional magnetic cores, the form factor of LLCchargers is often plump and bulky. In order to implement slim profile converters, PTs can be used featuringlow height, reproducibility, lower leakage inductance, and low thermal resistance.Despite the promising low profile and manufacturing advantages of PTs, their inherent high parasiticcapacitances result in severe problems for LLC converters. Figure 5.2 (a) presents a LLC resonant converterschematic and includes parasitic elements of the transformer (leakage inductances, winding resistances, andparasitic capacitors). Figures 5.2 (b), (c), (d) and (e) present the problems that arise from transformer’sparasitic capacitances. As discussed, the high inter-winding capacitance between primary and secondary94Full-LoadtiLS15(c) (e)Light-LoadtVTrans2S2S1Vfc RC LmLlk1Rac1 Llk2Rac2C12 C34C14LsCC13C23C24D8D6D5D7Cip isvovp+-vs+-(b) (d)(a)0 1 2Normalized Frequency3f r,scf r,ocVoltage Gain02314Non-Operating AreaZCS RegionCapacitanceCapacitanceFHA Exp43..................iCM iCM iCM iCMiCMiCMiCMiCMSecondaryPCBInsulationbetween primaryand secondary PCBsInsulationbetween primaryand secondary PCBsLmCstraylkL1FR4FR4FR4}PrimaryPCB}SecondaryPCB}Copper TracesTransformerFigure 5.2: (a) The LLC resonant converter considering parasitic elements of the transformer and onecapacitor model of the transformer 1© (b) Transformer distorted no-load voltage due to the straycapacitance 2©, (c) The no-load voltage gain characteristics of the converter with different trans-formers: Unfortunate increase of voltage 3© and deviation of experimental characteristics fromFHA prediction with high stray capacitance 4© (d) CM noise problem due to the inter-winding ca-pacitance 5©, (e) A portion of the transformer consisting of one primary PCB and two secondaryPCBs (each PCB is a double layer PCB).generates CM noise and contributes to EMI issues. Complying with EMI standards requires significant ef-fort to reduce CM noise, especially if the noise level is high. Usually, high EMI noise requires a bulkier filterthat consequently increases the volume and cost of the system. In isolated power supplies, reducing inter-winding capacitance decreases CM noise amplitude significantly, simplifies the filter design and shrinks the95total filter size. On the other hand, the high intra-winding capacitance brings unwanted regulation issues forLLC resonant converters with wide output regulation. Voltage regulation is a critical specification in powerconverters to accommodate input voltage fluctuations (e.g., line regulation) or output voltage changes (e.g.,battery chargers). The large parasitic capacitance of the transformer severely distorts the light-load currentand voltage waveforms of the converter, leading to unpredictable behavior of output voltage which cannotbe seen by First Harmonic Approximation (FHA). A typical waveform of the transformer voltage in this con-dition is presented in Fig. 5.2 (b). Since the requirement of applying FHA in resonant converters is havingsquare shape voltage and sinusoidal current of the same frequency, applying FHA under this condition leadsto inaccurate results. Solid and dashed curves in Fig. 5.2 (c) present the light-loading voltage gain character-istics of the LLC resonant converter with experimental measurements and FHA for different values of straycapacitance, respectively. The solid curves show that large parasitic capacitance leads to unpredictable be-havior of output voltage and therefore, loss of the regulation. This figure also shows that although FHA canpredict an unfortunate increase in the voltage gain due to the parasitic capacitances which limit the abilityof the converter to handle low conversion ratios (e.g., low output voltages or high input voltage), it fails toaccurately predict the output voltage. As it was mentioned before, this discrepancy in the results is due tothe parasitic capacitance that distorts the voltage and current waveforms and leads to regulation problems forLLC resonant converters. It is worth mentioning that the FHA curves are found by combining the effect of allparasitic capacitors into one parallel stray capacitance that is shown in Fig. 5.2 (a). The required equationsfor getting the value of this stray capacitance based on the six-capacitor model of the transformer will bepresented in the next sections. Reducing the value of this capacitor can significantly improve the situationand resolve the regulation problem.This chapter characterizes the PT capacitance issue in detail and proposes mitigation strategies to im-prove the performance of LLC converters with PTs. A systematic analysis is performed, and six improvedPT winding layouts are introduced and benchmarked with a traditional design. As a result of the investi-gation, an optimized transformer is obtained to minimize PT parasitic capacitance while maintaining lowAC resistance. For each proposed winding layout, the analytical equations describing the parasitic capac-itance are found, and the advantages and disadvantages of each layout are presented. In addition to theproposed winding layouts and arrangement, a comprehensive procedure to extract all parasitic elements ofPTs are provided, which can be used to run FEA simulations of the electro- and magneto-static behavior ofPTs. Experimental results show that the proposed transformers have up to 21.2 and 16.6 times less intra-and inter-winding capacitance, without compromising the resistance. This significant parasitic capacitance96reduction considerably improves the performance of the converter. Experimental results of employing theproposed transformers in a 1.2 kW LLC resonant converter show that the proposed transformers can success-fully resolve both CM noise and voltage regulation problems in the LLC resonant converter and can regulatethe output voltage even under no-load condition. In addition to these benefits, the converter efficiency in-creases due to the elimination of the parasitic capacitance.5.2 Transformer Parasitic Element Extraction Using FEAAs mentioned before, high parasitic capacitances of the transformer have severe detrimental effect on thevoltage regulation and CM noise of the LLC resonant converter. In order to attain high conversion efficiencyand wider output regulation in LLC resonant converters, PT stray capacitance should be minimized as muchas possible while keeping AC resistance low. In this section, a comprehensive study of transformer parasiticelements is presented and a full procedure of getting the equivalent circuit using FEA is proposed with theobjective of designing low parasitic PTs to address regulation problems in LLC converters.5.2.1 Parasitic CapacitanceThe procedure for extracting the six-capacitor equivalent circuit of the transformer was presented in 2.4. Asdiscussed, three different analyses are required to find six-capacitor model which are presented in Figs. 5.3(b), (c) and, (d). Based on these analyses, Table. 5.1 presents relationships that can be used to find the valueof each lumped capacitor.In order to evaluate the overall impact of parasitic capacitance on the voltage regulation, the six-capacitorshould be converted to the one capacitor model of Fig. 5.2 (a). The expression for calculating this capacitancedepends on the connection between primary and secondary windings. Fig. 5.4 (a) shows the six-capacitormodel of the transformer with three independent voltages. If there is no connection between the primary and(a) (b) (c) (d)n:1C13C24CC14C12 C3423V1V2VoVoV2V1Figure 5.3: Electrostatic behavior model of the transformer: (a) Six-capacitor model with three inde-pendent voltages, (b), (c), and (d) the required numerical analysis to extract the six-capacitormodel.97Table 5.1: Equations describing parasitic capacitances based on the field analysisCapacitor EquationC13 −12V1V2∮V (# »E1.# »D2+# »E2.# »D1)dVC14 −12V1Vo∮V (# »E1.# »Do+# »Eo.# »D1)dV −C13C23 12V2Vo∮V (# »E2.# »Do+# »Eo.# »D2)dV −C13C12 1V 21∮V (# »E1.# »D1)dV −C14−C13C34 1V 22∮V (# »E2.# »D2)dV −C13−C23C24 1V 2o∮V (# »Eo.# »Do)dV −C13−C23−C14secondary windings, the offset voltage between two windings can be found using the following relationship[5].Vo f s =(C13+C14)V1− (C13+C23)V2C13+C14+C23+C24(5.2)Having the offset voltage as a function of primary and secondary voltages, the six-capacitor model can bereduced to the three capacitors of Fig. 5.4 (b). The expressions for these capacitors can be found by equatingC13C14C23C24C12 C34Vp+-VsVofs+-Llk1LmLlk2(b)(c)(b)Llk11:kV1+-V2+-2LmCpsCsCpLlk2(a)VofsLmCstraylkLi13i14i24i23CpsCp CsVp+-Vs+-Lslk1LmLlk2///Figure 5.4: a) Six-Capacitor model of the transformer, b) the three capacitance model of the trans-former, c) the equivalent model of the transformer referred to the primary, and d) the one capacitormodel of the transformer98the electrostatic energy of this circuit to the energy of the six-capacitor model and replacing Vo f s with 5.2.These three capacitors then can be referred to the primary side which is shown in the Fig. 5.4 (c). Using theequations that are provided in [90], expressions for these capacitors are presented in 5.3.C′p = (C12+C14+C13)−(C14+C13)2C13+C14+C23+C24+ k(−C13+ (C14+C13)(C23+C13)C13+C14+C23+C24 )C′s = k2(C34+C23+C13− (C23+C13)2C13+C14+C23+C24)+ k(−C13+ (C14+C13)(C23+C13)C13+C14+C23+C24 )C′ps =−k(−C13+(C14+C13)(C23+C13)C13+C14+C23+C24)(5.3)The circuit shown in Fig. 5.4 (c) can be simplified further if the leakage inductances are negligible incomparison to the magnetizing inductance (which is the case for planar transformers). Under this condition,the capacitance Cps is short circuited and Cp and Cs are in parallel. Figure 5.4 (d) shows the one capacitormodel of the transformer. The expression for the stray capacitance in this circuit is presented in 5.4.Cstray =C′p+C′s=C12+ k2C34+((C14+C13)(C23+C24)+ k2(C13+C23)(C14+C24)C13+C14+C23+C24)+2k((C14C23−C13C24)C13+C14+C23+C24)(5.4)Where k is the transformer turns ratio. Equation (5.4) shows that both intra- and inter-winding capacitorscontribute to the parallel stray capacitance which leads to regulation problems. Therefore, both types ofcapacitors should be minimized to reduce the value of this capacitance and solve the voltage regulationproblem in the LLC resonant converter.Equation (5.4) and table 5.1 are useful tools in designing low parasitic capacitance PTs for LLC resonantconverter. These equations can be used along FEA to investigate the parasitic capacitance of any design. Re-garding CM noise, these equations split the inter-winding capacitance to the four capacitors of C13, C14, C23and, C24 which is a great advantage in CM noise modeling. Regarding the voltage regulation problem, (5.4)can be used to evaluate the value of parallel stray capacitance and avoid the problem of voltage regulation inLLC resonant converters.5.2.2 AC Resistance and Leakage Inductance ModelingIn order to design an optimized PT for the LLC resonant converter, not only parasitic capacitances should beminimized, but also AC resistance and leakage inductance of the transformer should be kept low. Therefore,it is also important to define a procedure for finding AC resistance and leakage inductance of the transformer.99RcsLmsLlk1Rac1Llk2Rac2V1+-V2+-I1I2n:1Llk1Rac1 Llk2Rac2V1+-V2+-I1 I2n:1Rc Lm(a) (b)Figure 5.5: a) Transformer equivalent circuit neglecting the capacitive effects and b) Modified equiva-lent circuit.Neglecting capacitive effects, the transformer is a two-port system whose equivalent circuit is shown in Fig.5.5 (a). For a two-port system, the relationship between primary and secondary voltages and currents can berepresented by a 2×2 matrix. However, finding the matrix impedance of Fig. 5.5 (a) is not straightforward.Thus, a minor circuit transform is required to get the impedance matrix. The parallel core resistance andmagnetizing inductance can be converted to the series from using (5.5). Fig 5.5 (b) shows the modifiedequivalent circuit.Lms =Q2Q2+1×Lm , Rcs = 1Q2+1 ×Rc , Q =ωLmRc(5.5)The matrix representation of this circuit is expressed in 5.6.Z =(Rac1+Rcs)+S(Llk1+Lms) 1n(Rcs+SLms)1n(Rcs+SLms) (Rac2+1n2 Rcs)+S(Llk2+1n2 Lms) (5.6)Arrays of matrix impedance can be found using field analysis which can be done with the aid of FEA. (5.7)and (5.8) present elements of each array based on the fields.Ri j =12× Ii(pk)× I j(pk)∮V(#»Ji .#»J∗j +#»J∗i .#»Ji )dV (5.7)Li j =12× Ii(pk)× I j(pk)∮V(#»Hi.# »H∗j +# »H∗i .#»Hi)dV (5.8)In the above equations, Ji and Hi are the current density and magnetic field due to the input current at theport i. Besides, Ri j and Li j are resistance and inductance associated with the array i j in the impedancematrix. In the case of two windings transformer, there are two ports and two different analysis are requiredto get corresponding current densities and magnetic fields. In finding field solution, eddy currents shouldbe considered to investigate the impact of arrangement on the AC resistance and leakage inductance. Afterfinding field solution for each case, superposition theorem will be used to calculate (5.7) and (5.8). Equating100the matrix produced with these equations with the transformer impedance matrix, the values of equivalentcircuit can be found by (5.9).Rac1 = R11− 1k R12 Llk1 = L11−1kL12Rac2 = R22− kR21 Llk2 = L22− kL21Lms =1kL12 Rcs =1kR12(5.9)Where k is equal to 1/n. Having the required analysis to extract PTs’ parasitic elements, it is possible todesign optimized PTs with low parasitic elements for the LLC resonant converter. These analysis tools areused through this paper to investigate different PT structures and designing low parasitic capacitance PTs forthe LLC resonant converter with wide output voltage regulation.5.3 Reduction of the Parasitic CapacitancesAs discussed in section 5.1, the inter-winding capacitance makes the CM noise problem and the primary straycapacitance leads to a voltage regulation problem under light-loading condition. Therefore, efforts should bemade to minimize parasitic capacitances of PT in the design stage. However, reducing the parasitic capaci-tance often leads to increment in resistance. Therefore, both of these parasitic elements should be consideredat the same time to achieve high-efficiency and low-parasitic PT. In this section, a systematic analysis isperformed, and six improved PT winding layouts are introduced and benchmarked with a traditional design.The analysis starts with the static capacitance between two layers of the traditional spiral winding layout andthen the low parasitic capacitance layouts are introduced.The value of the static capacitance between two conductive layers with an overlapping area of At and aseparation distance of d is presented in (5.10).Cstatic = ε0εrAtd(5.10)Where εr is the permittivity of the material between layers. For a transformer with m intersections of primaryand secondary, the total value of static inter-winding capacitance is presented in (5.11).Cstatic = m× ε0εr Atd (5.11)The total value of inter-winding capacitance is equal to the sum of C13, C14, C23 and, C24 capacitors. There-101fore, reducing the total value of inter-winding capacitance means that the overall impact of inter-windingcapacitance is reduced. Equation (5.11) shows that the total value of static inter-winding capacitance canbe reduced by increasing the separation distance, reducing the overlapping area, reducing the number ofintersections, and using low permittivity materials between layers. Increasing the separation distance re-duces the value of capacitance. However, more distance means more space for insulation and less spacefor copper which leads to higher conduction losses. As a result, this method often sacrifices resistance toreduce parasitic capacitance. Reducing the overlapping area also reduces PCB utilization and increases theDC resistance. Also, this method suffers from high proximity effect that results in very high AC resistance.Therefore, among different factors, only the number of intersections and the permittivity of the material canbe manipulated to reduce the static inter-winding capacitance. Reducing the number of intersections shouldbe done by considering the proximity effect. While the Non-Interleaved (NI) structure has only one intersec-tion, it cannot be used due to the high ratio of AC to DC resistance. The proposed methods and proceduresin section 5.2 can be used to find an optimized transformer arrangement that minimizes both AC resistanceand inter-winding capacitance. Using low permittivity material is a very effective method of reducing thestatic capacitance with no penalty on the other parasitic elements.It should be mentioned that FR4 is the most widely used material for PCBs due to its electrical andmechanical properties. This material is flame resistant and provides up to 20 kV/mm electrical insulation.Despite these advantages, FR4 has a relatively high permittivity of 4.7. This high permittivity leads to aconsiderable parasitic capacitance between the top and bottom traces. Since commercial PCBs are usuallymanufactured using FR4, the parasitic capacitance between the top and bottom traces cannot be reduced byusing another material. However, we are still able to use low permittivity materials between separate PCBsto reduce the parasitic capacitance between them. This option is only available in the windings realized bymodularly stacked double-layers PCBs, as the material between PCBs are not necessarily FR4. As a result,windings made with double-layer PCBs are more customizable and capable of reducing parasitic capacitancethan windings that are manufactured by multi-layer PCBs.In order to explain how the material between PCBs affects the distributed parasitic capacitances, a cross-section of an 8 : 4 transformer is shown in Figs. 5.6 (a) and (b). The primary has four PCBs in parallel andeach PCB has eight turns (four on the top and four on the bottom). The secondary also has four PCBs inparallel and each PCB has four turns. Figure 5.6 (b) shows a 2D cross-section of the transformer and explainshow the PCBs are arranged. There are four intersections of primary and secondary PCBs. The material thatis used in these intersections significantly affects the inter-winding capacitance. In multi-layer PCBs, this102PrimaryPrimaryPrimarySecondaryInsulationFR4}}Secondary}Secondary}Secondary}}Primary}}(b)(a) Figure 5.6: a) The 3D model of a traditional 8 : 4 planar transformer with spiral winding and b) 2Dcross section of the transformer, showing the arrangement of the transformer. Each primary PCBhas eight turns (four on each side), and each secondary PCB has four turns (two on each side). Theprimary PCBs are connected in parallel and the secondary PCBs also are connected in parallel.material is FR4. However, in windings that are made with double-layer PCBs, low permittivity materials likeair can be used. Figures 5.7 (a) and (b) show one of these intersections with FR4 and air used, respectively.These figures show that replacing FR4 with air reduces the static capacitance between successive PCBsroughly 4.7 times for the same structure. The separation distance can be realized using hollow frames.Figure 5.8 shows an example of a frame that can be used to provide air separation between layers. Sinceframes only are required in the soldering process (the transformer will maintain its physical structure aftersoldering), they may be designed in a way that allows them to be removed after the soldering. Although aireffectively reduces the static capacitance between successive layers, it cannot provide the required insulationclearance between overlapping traces. Therefore, the required insulation clearance between layers can be1.4e-0041.2e-0041.0e-0048.6e-0056.7e-0054.8e-0052.8e-005 9.3e-006Energy (J/m )3(b) (a) Primary Double LayerPCB {Primary Double LayerPCB {Primary Double LayerPCB {Primary Double LayerPCB {FR4 as material between primary and secondary PCBsair as material between primary and secondary PCBsFigure 5.7: Inter-winding energy associated with one intersection of primary and secondary. All of theprimary turns have voltage equal to 1V , and all of the secondary turns have voltage equal to 0V .The energy distribution: a) with FR4 between PCBs 101pJ and b) with air between PCBs 25pJ.103(a) (b)Figure 5.8: Example of the frame that is used for air separation. a) 3D model and b) physical framerealized by using one or two layers of Kapton tape.Unlike inter-winding capacitance, finding the self-capacitance of two overlapping layers of the samewinding requires calculating the total electrostatic energy in that layer. Figure 5.9 shows a double-sidedPCB used as a winding in PTs. The analytical expressions for calculating the intra-winding energy betweenoverlapping traces and adjacent turns are presented in (5.12) and (5.13).Eoverlap =∫ L012ε0εrW ×dxd(VwLx)2 =16ε0εrW ×Ld(Vw)2 (5.12)Ead jacent = 2∗∫ (1− 2n )L012ε0t×dxc(Vwn)2 = ε0(n−2)n3t×Lc(Vw)2 (5.13)The parameters of (5.12) and (5.13) are presented in the table 5.2. The sum of these energies is equal tothe energy stored in the lumped intra-winding capacitance. Equating the energy expressions, the value oftdlc+-Vnw( )............WdldlWdld+-VxL wVw( )x=L ,V=0x=0x=LV=Vwx=X21X=0 X=L/2VwVw/20(a) (b)Figure 5.9: a) Traditional spiral winding layout: The distributed capacitance due to overlapping traces1©, the distributed capacitance between adjacent turns at the same side 2© and b) simplified viewof the overlapping traces104Table 5.2: Parameters definitionParameter DefinitionL Total lenght of turns in one sideW Width of tracesd Distance between two layersc Clearance between adjacent tracest Thickness of Coppern Total number of turns in PCBεr FR4 permitivityAt Total area of turnslumped capacitor can be found using (5.14).Cintra =13ε0εrAtd+2(n−2)n3ε0tWAtc(5.14)In the equation above, the first term is associated with the overlapping turns and the second term shows theintra-winding capacitance due to the adjacent turns of the same side of PCB. In developing the second part,the fringing of electric field is ignored. In reality, due to the fringing of electric field, part of electric fieldreaches to the adjacent trace through the PCB. Therefore, the value of the second term is higher than what(5.14) predicts. However, since the thickness of the traces is much smaller than their width and the value ofthe second term is roughly proportional to 1n2 , the value of the second term is negligible in comparison to thefirst term. For the studied prototypes, the second term is less than three percent of the first term. Ignoringthe second term, the intra-winding capacitance of Fig. 5.9 is presented in (5.15).Cintra ≈ 13ε0εrAtd=13Cstatic (5.15)Equation (5.15) indicates that for the same area, the value of intra-winding capacitance of two overlappinglayers of Fig. 5.9 is equal to one-third of the static capacitance between two layers. Since replacing FR4with air only is applicable between different PCBs, this method cannot be used to reduce the capacitancebetween traces of the same PCB. However, if PCBs of the same windings are placed next to each other, aircan reduce the value of static capacitance between layers of different PCBs. Figures 5.10 (a) and (b) showthe intra-winding energy of two successive PCBs of the same winding with FR4 and air between PCBs,respectively. These figures confirm that air only can mitigate the intra-winding capacitance between layersof different PCBs. In other words, the overall impact of this method on the intra-winding capacitance is105(a)(b)7.1e-0056.1e-0055.1e-0054.2e-0053.3e-0052.3e-0051.4e-005 9.4e-008Energy (J/m )3Primary Double LayerPCB {Primary Double LayerPCB {Primary Double LayerPCB {Primary Double LayerPCB {FR4 as material between successive primary PCBsAir as material between successive primary PCBsFigure 5.10: Intra-winding energy associated with two PCBs of the same winding placed next to eachother. The PCBs are connected in parallel and 1V is distributed linearly between the terminalsof each PCB. Electrostatic energy distribution: a) with FR4 between PCBs 99pJ and b) with airbetween PCBs 73pJ.much lower. Therefore, other methods should be used to reduce the intra-winding capacitance betweentraces of the same PCB. In the following subsections, six improved winding layouts with very low parasiticcapacitances are proposed and compared regarding the parasitic capacitance and resistance. These windinglayouts are shown in the figures 5.11 (b), (c), (d), (e), (f), and (g). For each winding layout, the analyticalexpressions describing DC resistance and intra-winding capacitance are proposed and verified with the aidof FEA. In comparison to the traditional spiral winding layout, the proposed layouts have up to 21.2 and 16.6less intra- and inter-winding capacitances which significantly reduce the CM noise and solve the regulationproblem in the LLC resonant converter, which is the objective of this section.5.3.1 No Overlapping Winding LayoutsMinimizing the overlapping area is the first approach to reducing the intra-winding capacitance. Figure 5.11(b) and (c) show minimized overlapping winding layouts. These winding layouts are called no overlap-ping winding layouts through this chapter. The energy stored in these winding layouts is proportional tothe distributed capacitance between adjacent turns on the same side of PCB. The analytical expression forcalculating the parasitic capacitance between adjacent turns is equal to the second term in (5.14). Figure5.12 (b) shows the intra-winding energy associated with the layout of Fig. 5.11 (b). This figure shows thatthese layouts strongly reduce the intra-winding energy as the value of intra-winding energy is reduced from33 pJ in the traditional design to 1.7 pJ. Regarding the inter-winding capacitance, these layouts offer doublespace between windings and reduce the value of static inter-winding capacitance. Although these layoutseffectively mitigate the problem of intra-winding capacitances, they have higher DC resistance comparingto the traditional winding layout. In these layouts, only 50% of PCBs are used and consequently, the values106(a) (b) (c)(d) (e)(g)(f)Primary part 1(first four turns)PCB1 top and bottomare parallelPCB2top and bottomare parallelPCB3top and bottomare parallelPCB4top and bottomare parallelPrimary part 2(Last four turns)Secondary part 1(first two turns)Secondary part 2(last two turns)Middle connection for series connection of two parts of the secondaryMiddle connection for series connection of two parts of the PrimaryPrimary(2 Layer PCB)Secondary(2 Layer PCB)Insulation between PCBsInsulation between PCBsInsulation between PCBsInsulator (FR4)Primary(2 Layer PCB)Secondary(2 Layer PCB)Insulator (FR4)Figure 5.11: The proposed improved winding layouts to reduce the parasitic capacitances in LLC con-verters: a) Traditional spiral, b) and c) No overlapping, d) Optimized overlapping, e) Alternating,f) Alternating & no overlapping and, g) Zero voltage gradient winding layouts.107(a) 33 pJ (b) 1.7 pJ(c) 10.5 pJ (d) 3.4 pJ(e) 2.15 pJ (f) 1.1 pJEnergy (J/m )3Energy (J/m )33.8e-0061.9e-0062.5e-0073.7e-005Energy (J/m )37.1e-0054.6e-0069.5e-0064.8e-0062.5e-007Energy (J/m )3Energy (J/m )31.4e-0057.0e-0062.5e-0078.6e-0064.3e-0069.1e-0072.8e-005Energy (J/m )35.5e-0054.6e-006Figure 5.12: Intra-winding energy associated with one PCB of the proposed layouts. Each layout con-sist eight turns and 1V is distributed linearly between terminals of the layout: a) Traditionalspiral, b) No overlapping, c) Optimized overlapping, d) Alternating, e) Alternating & no over-lapping, and f) Zero voltage gradient winding layouts.of DC resistances are roughly twice the traditional winding layout. Due to higher conduction loss, thesedesigns are not suitable for high-efficiency LLC applications.5.3.2 Optimized Overlapping Winding LayoutThe second winding layout which attempts to reduce the parasitic capacitance with less resistance incrementis shown in Fig 5.11 (d). The stored energy between overlapping traces depends on the voltage gradientof those traces. Therefore, the energy is not evenly distributed in the area between two layers, and moreenergy is stored between outer turns that have larger capacitance and voltage gradient. This feature is used inthis layout to remove the overlapping area between the outer turns and effectively reduce the intra-windingcapacitance. Removing the overlapping between these turns means that putting (n2 + 1) turns on one sideand (n2 −1) on the other side. For PCBs with the odd number of turns, it means having (n+12 ) turns on oneside and (n−12 ) turns on the other side. This winding layout is called Optimized overlapping winding layoutin this chapter. For even values of n the intra-winding energy and corresponding capacitance can be foundusing (5.16).Eintra =∫ ( n2−1n2+1)L012ε0εrW ×dxd× (Vw(n−2n )(n2−1n2+1)Lx)2=[16ε0εrW ×LdV 2w]×[(n2 −1n2 +1)(n−2n)2]Cintra =[13ε0εrW ×Ld]×[(n2 −1n2 +1)(n−2n)2] (5.16)108Following the same procedure for odd values of n, the intra-winding capacitance associated with this condi-tion is presented in (5.17).Eintra =∫ ( n−1n+1 )L012ε0εrW ×dxd×[Vw(n−1n )(n−1n+1)Lx]2dx =[16ε0εrW ×LdV 2w]×[(n−1n+1)(n−1n)2]Cintra =[13ε0εrW ×Ld]×[((n−1)3n2(n+1))] (5.17)Assuming the total length of winding is equal to the traditional winding layout, DC resistance for each caseis presented in (5.18).n = Even RDC−Opt = (n+2n)RDC−tradn = Odd RDC−Opt = (n(n+1)n2+1)RDC−trad(5.18)In the above equations, RDC−trad is the DC resistance of traditional spiral design. Figures 5.13 (a) and(b) show the normalized DC resistance and intra-winding capacitance of Optimized overlapping windinglayout for different values of n. The base values for normalization are the DC resistance and intra-windingcapacitance of traditional winding layout. These figures show that the value of intra-winding capacitance canbe reduced effectively, without doubling the DC resistance. An eight-turn winding layout with this strategyis shown in Fig. 5.11 (d). The intra-winding energy distribution of this layout is shown in Fig. 5.12 (c).This figure shows that in the case of eight turns PCBs, removing the overlapping area between first and lastturns reduces the intra-winding capacitance by 69%. This result is in a very good agreement with (5.16).The percentage of increase in the DC resistance can be calculated using (5.18) which is equal to 25%. Incomparison to the no overlapping winding layouts that have 100% more DC resistance, the DC resistanceincrement in this layout is just 25%. Although this layout proposes a significant capacitance reduction by asmall increment of resistance, the parasitic capacitance still is considerable and can lead to voltage regulation2 4 6 8 10 12 14 1611.251.51.752Number of TurnsNormalized DC Resistance 00.51Normalized Intra−winding CapacitanceDC ResistanceIntra−Winding Cap3 5 7 9 11 13 15 1711.11.21.31.4Number of TurnsNormalized DC Resistance 00.51Normalized Intra−winding CapacitanceDC ResistanceIntra−Winding CapFigure 5.13: Variations of DC resistance and intra-winding capacitance of Optimized overlappingwinding layout for a) even values of n and b) odd values of n109problems. Therefore, more optimized winding layouts should be investigated to strongly reduce the parasiticcapacitance while not letting the resistance increase.5.3.3 Alternating Winding LayoutNo overlapping and optimized overlapping winding layouts are based on the overlapping minimization prin-ciple. Although effective in mitigating the intra-winding capacitance, these winding layouts sacrifice DCresistance to achieve this goal. The intra-winding capacitance also can be minimized by reducing the voltagegradient between overlapping traces. Minimizing voltage gradients between large overlapping traces reducesthe intra-winding energy and consequently the intra-winding capacitor. One way to reduce the voltage gra-dient between overlapping traces is illustrated in Fig. 5.14 (a). This winding layout is called Alternatingwinding layout in this chapter. In this layout, the overlapping traces are two successive turns. In other words,after each turn, the next turn is on the other side. These turns are connected through VIA. For this layout,the intra-winding energy can be calculated by (5.19).Eintra =∫ L012ε0εrW ×dxd× (Vwn2)2 =[12ε0εrW ×LdV 2w × (4n2)]Cintra =[13ε0εrW ×Ld]×[6n2] (5.19)The above equation shows that this winding layout reduces the value of intra-winding capacitance by afactor of 6n2 . Figure 5.14 (b) presents the intra-winding capacitance of this layout for different values of nand shows that the value of intra-winding capacitance rapidly decreases by increasing the number of turns.Regarding the DC resistance, this winding layout has no increment as all of the available PCB is used forcopper traces. Figure 5.11 (e) shows an eight turns Alternating winding layout. For the ease of connectingto other PCBs, the winding is started from the middle, and the terminals are at the edges of the PCB. Theintra-winding energy distribution of this layout also is shown in Fig. 5.12 (d). This figure shows that an eightturns Alternating winding layout has 10 times less intra-winding energy than the traditional winding layoutwhich is in a good agreement with (5.19). In comparison to the previous designs, this layout reduces theintra-winding capacitance without sacrificing the DC resistance. Although this layout is a suitable candidatefor wide-range and efficient LLC converters, it does not have any superiority in terms of the inter-windingcapacitance. Besides, a large number of VIAs can increase the eddy current loss. Therefore, other windinglayouts should be investigated to find an optimum layout that minimizes both types of parasitic capacitances.110....2 4 6 8 10 12 14 1600.20.40.60.81Number of TurnsNormalized Intra−winding Capacitance(a) (b)Figure 5.14: a) Alternating winding layout with terminals at the outer edges of PCB and b) Variationsof intra-winding capacitance of Alternating winding layout for even values of n5.3.4 Alternating & No Overlapping Winding LayoutThe minimized overlapping strategy also can be used to reduce the value of inter-winding capacitance. Onthis basis, Alternating & no overlapping winding layout with minimized overlapping of primary and sec-ondary is shown in Fig. 5.11 (f). This layout uses the alternating layout to reduce the intra-winding capaci-tance and avoids any overlapping between primary and secondary to minimize the inter-winding capacitance.Therefore, this transformer minimizes both intra and inter-winding capacitances. Due to the alternating lay-out and lower overlapping area between the traces of the same winding, the intra-winding capacitance of thislayout is very low. Figure 5.12 (e) shows the intra-winding energy of this layout which is roughly 15 timesless than the traditional layout. Since the overlapping of primary and secondary is avoided in this structure,this layout also has lower inter-winding capacitance. On the downside, this layout only uses 50% of PCBand therefore has twice DC resistance. More importantly, this layout has a very high AC resistance due tothe proximity effect. Therefore, it makes a lot of conduction loss and is not suitable for high efficiency LLCconverters. This layout will be discussed more in the next section.5.3.5 Zero Voltage Gradient Winding LayoutThe final proposed winding layout for solving the parasitic capacitance problem is called Zero voltage gra-dient layout. In order to explain this winding method, an 8 : 4 transformer that is realized using double-layerPCBs is shown in Fig. 5.11 (g). There are four different PCBs (two double-sided PCBs for the primary side,and two double-sided PCBs for the secondary side). This figure shows that the eight turns of the primary aresplit into two parts. The first four turns of the primary are duplicated on both sides of the first PCB of the111primary. The top and bottom layers of this PCB are connected in parallel, which means that this PCB hasfour turns out of the eight turns of the primary. Since the top and bottom layers of this PCB are identical andconnected in parallel, they have the same voltage and there is no voltage gradient between the overlappingturns. This condition also can be seen from the direction of the turns in this PCB. The four remaining turnsof the primary are duplicated on both sides of the second PCB of the primary. Similar to the first PCB, thetop and bottom layers of this PCB are connected in parallel. The first four turns that are on the first PCB arethen connected in series to the four turns of the second PCB via a middle connection, making an eight-turnprimary winding. The same is true for the secondary winding. The key idea here is that the top and bot-tom layers of each PCB should be identical and connected in parallel to achieve zero voltage gradient andminimize the parasitic capacitance.The proposal is implemented in Fig. 5.11 (g) by dividing each winding into two portions, duplicatingeach portion on the top and bottom sides of a separate PCB, and then connecting the two PCBs with a middleconnection. In general, the proposal can be extended to dividing winding into any even number of groups.Different steps that are required to implement this proposal are provided as follows:1. Each winding should be split into two (or any even number of) groups, and each group should beduplicated on both sides of a separate PCB. The minimum number of required PCBs for each windingis equal to the number of groups.2. The top and bottom layers of each PCB should be connected in parallel.3. Different PCBs should be placed separately to avoid the voltage gradient between them. All differentPCBs should then be connected in series to make a complete winding. Middle connections are requiredto connect two successive PCBs. The number of required middle connections is equal to half thenumber of PCBs.It can be seen that the above rules are applied to the transformer shown in Fig. 5.11 (g). In this case, eachwinding is divided into two groups, and two PCBs are required for each winding (one PCB for each group).Besides, one middle connection is required to connect these PCBs in series.The intra-winding energy distribution of a PCB, the top and bottom layers of which are connected inparallel, and which has four turns on each side, is shown in Fig. 5.12 (f). Compared to the traditionalwinding method, the proposed method reduces the value of intra-winding energy from 33pJ to just 1.1pJ,while maintaining the same overlapping area and without compromising DC resistance. This reduction in112parasitic capacitance is even greater than that provided by the minimized overlapping winding layouts thathave double conduction loss.As mentioned before, the minimum number of PCBs that are required for each winding in this method isequal to the number of portions into which the winding is divided. If the core windows can accommodatemore layers, it is desirable to add extra layers in parallel to reduce the resistance. For example, in Fig.5.15, the windings of the same transformer are realized by using four PCBs (two PCBs in parallel for eachportion of windings). The PCBs that are connected in parallel are identical and both have the same portion ofwinding. Therefore, they also have the same voltage distribution. This characteristic can be used to reducethe inter-winding capacitance. Due to the zero voltage gradient between these PCBs, they can be placedvery close together without raising concerns about increasing the intra-winding capacitance or violatingthe electrical clearance, which saves space in the limited height of the core windows. This space can beused to increase the number of layers or to increase the separation distance in the primary and secondaryintersections to reduce the inter-winding capacitance. This advantage is shown in Fig 5.15. This figureshows that identical PCBs are separated just by one Kapton layer, providing more separation distance forintersections of the primary and secondary. Therefore, this winding layout not only results in minimumintra-winding capacitance but also provides the opportunity to reduce the inter-winding capacitance. Thebenefits of this winding layout can be summarized as follows:1. Extremely low intra-winding capacitance due to the zero voltage gradient between overlapping traces.2. No increment in the value of DC resistance. The same DC resistance as in the traditional windinglayout.Connection betweentwo parts of the primaryConnection betweentwo parts of the secondaryAir &KaptonAir &KaptonKaptonKaptonAir &KaptonKaptonAir &KaptonPrimary part 1(first four turns)Secondary part 1(first two turns)Secondary part 1(first two turns)Secondary part 2(last two turns)Secondary part 2(last two turns)Primary part 2(last four turns)Primary part 2(last four turns)Primary part 1(first four turns)PCB1P1 S2 S2 P2 P2 S1 S1 P1PCB2 PCB3 PCB4 PCB5 PCB6 PCB7 PCB8Figure 5.15: Zero voltage gradient transformer with the P1S1S1P2P2S2S2P1 structure. This figureshows that all overlapping traces of the same winding have zero voltage gradient.1133. Identical PCBs can be placed very close together without increasing the intra-winding capacitance.Therefore, there is more space to be used in the intersections of the primary and secondary, resultingin less inter-winding capacitance.Since it results in very low parasitic capacitance, this layout can resolve both CM noise and light-loadvoltage regulation problems in the LLC converter; at the same time, it produces a low level of resistance,which ensures high full-load efficiency. Therefore, this layout is suitable for use with LLC resonant convert-ers.5.3.6 Comparison of the Proposed Winding LayoutsIn the previous section, six improved winding layouts were proposed to minimize the parasitic capacitance ofPT and consequently, solve problems due to the parasitic capacitance in the LLC resonant converter. Amongthe proposed winding layouts, those that reduce the parasitic capacitance by decreasing the overlappinghave higher DC resistance. On the other hand, designs that minimize the parasitic capacitance by reducingthe voltage gradient have the benefit of using all the available space and therefore do not compromise DCresistance. The DC resistance and intra-winding capacitance of different winding layouts are compared inFigs. 5.16 (a) and (b). Figure 5.16 (a) shows that all of the proposed winding layouts have considerablylower intra-winding capacitance than the traditional spiral layout.No overlapping layouts can strongly mitigate the parasitic capacitance and solve the regulation problem.However, they also double the DC resistance which leads to higher conduction loss. Optimized overlappinglayout is the optimized version of No overlapping layouts that reduces a big portion of parasitic capacitanceby a small increase in the resistance. However, it is not as effective as No overlapping layout and since6819.86.23.8 3.3 2.201020304050607080Traditional OptimizedOverlapAlternating Alternating &No OverlapNo Overlap Zero VoltagegradientStatic Inter-Winding Cap (pF)Intra-Winding Cap31 Times less Intra-winding Capacitancewith the same DC Resistance37.647.242.48185370102030405060708090Traditional OptimizedOverlapAlternating Alternating &No OverlapNo Overlap Zero VoltagegradientDCResistance (mOhm)DC ResistanceNo sacrifice onthe DC Resistance(a) (b)Figure 5.16: Parasitic elements comparison of different winding layouts: a) Intra-winding capacitanceand b) DC resistance114wide output regulation requires very low parasitic capacitance, it may not solve the regulation problem. Al-ternating layout also strongly reduces the intra-winding capacitance without increasing the DC resistance.Therefore, this layout can be used to resolve the regulation problem without compromising efficiency. How-ever, it does not have an advantage over the traditional layout in terms of CM noise. In order to reduce bothintra- and inter-winding capacitances, Alternating & no overlapping layout is proposed. Although this lay-out effectively reduces both parasitic capacitances, it has significantly higher AC resistance in comparisonto other layouts which will be discussed more in the next section. Among different layouts, Zero voltagegradient layout offers the minimum intra-winding capacitance without any increment in the DC resistance.Reducing the intra-winding capacitance significantly enhances the converter performance and mitigates theregulation problem. In terms of inter-winding capacitance, this layout also provides the lowest inter-windingcapacitance. Minimizing the inter-winding capacitance not only reduces the CM noise but also enhances theregulation.5.4 Arrangement Tradeoff AnalysisIn the previous section, improved winding layouts have been proposed to significantly reduce the parasitic ca-pacitance and attenuate the CM noise and solve the voltage regulation problem in the LLC resonant converter.In addition to the winding layout, the structure of the transformer strongly affects the parasitic elements. Itis interesting to note that there is a trade-off between intra-winding capacitance, AC resistance and leakage3.7723e+0073.2694e+0072.7666e+0072.2638e+0071.7609e+0071.2581e+0077.5523e+006 9.6864e+003J (A/m )21.7947e+0071.5580e+0071.3186e+0071.0792e+0078.3984e+0066.0044e+0063.6104e+006 1.9442e+0041.0721e+0079.5847e+0078.4484e+0077.3122e+0066.1760e+0065.0398e+0063.9036e+006 2.1992e+006J (A/m )29.0282e+0068.0566e+0067.0850e+0066.1134e+0065.1418e+0064.1702e+0063.1985e+006 1.7411e+006J (A/m )2J (A/m )2(a) (b)(c) (d)P1P2P3P4S1S2S3S4S1S2P1P2P3P4S3S4P1S1P2S2P3S3P4S4P1S1S2P2P3S3S4P4Figure 5.17: Current density in different arrangements: a) PPPPSSSS (NI), b) SSPPPPSS, c) PSPSP-SPS (FI), and d) PSSPPSSP. It is evident that PSSPPSSP structure leads to an even distributionof the current between layers and provides the best AC resistance1151414808606202301172 1324302040608010012002004006008001000120014001600AC Resistance (mΩ)Inter-Winding Cap (pF)Inter-Winding Capacitance AC ResistanceThe same AC resistance ofFI structure but with much less inter-winding Capacitance680618649 628397 385 388 383.300.10.20.30.40.50.60.70.80.910100200300400500600700800Leakage Inductance (µH)Parallel Stray Cap(pF)Stray Capacitance of one Cap model Leakage Inductance(a) (b)Figure 5.18: The comparison of parasitic elements of an eight layers transformer with traditional spiralwindings in different structures. a) AC resistance and inter-winding capacitance and, b) leakageinductance and primary parallel stray capacitanceinductance against the inter-winding capacitance. The values of intra-winding capacitances, AC resistances,and leakage inductances decrease by using interleaved structures. On the other hand, the inter-winding ca-pacitance is proportional to the number of intersections between primary and secondary which increases inthe interleaved structure. Most of the proposed winding layouts in the previous section can effectively solvethe intra-winding problem. Besides, the leakage inductances are inherently small in PTs comparing to thewire wound transformers and also the primary leakage inductance is capable of being absorbed by the seriesinductor. For these reasons, the trade-off analysis in finding the optimum arrangement is only made based onAC resistance and inter-winding capacitance. On this basis, the optimum structure is the one that minimizesthe AC resistance with the minimum number of intersections between primary and secondary. Figure 5.17shows the current density in the transformer with four layers of primary and secondary in different structures.This figure shows that the best current distribution between layers happens in the PSSPPSSP structure. Incomparison to the Fully Interleaved (FI) structure, the number of intersections has reduced from seven tofour, meaning the value of inter-winding capacitance is reduced roughly by 43%. This reduction in the par-asitic capacitance can significantly attenuate the CM noise in LLC converters. The comparison of differentstructures regarding parasitic elements is presented in Figs. 5.18 (a) and (b). The stray capacitance in Fig.5.18 (b) is calculated by using (5.4).The proposed winding layouts also are investigated with different structures and in all cases, the proposedarrangement gives the best results. The only exception is the Alternating & No overlapping winding layoutwhich has significantly larger AC resistance in all arrangements. Table 5.3 shows the ratio of AC to DCresistance of this layout in different structures.116Table 5.3: The ratio of AC resistance to DC resistance of Alternating & No overlapping winding layoutin different structuresParameter PPPPSSSS PPSSPPSS PSPSPSPS PSSPPSSPRacRdc168.648.1184.2848.121248.1201.548.1This table shows that the interleaving does not solve the proximity effect for this winding layout. Sincethe primary and secondary turns do not meet each other, primary and secondary MMF do not cancel eachother and the proximity effect leads to a high ratio of AC to DC resistance. Figure 5.19 compares the inter-winding energy of the traditional winding layout with the Alternating & No overlapping winding layout.This figure shows that even with no overlapping between primary and secondary, still there are some capac-itive coupling between windings due to the fringing of the electric field. Indeed, even with no overlappingbetween primary and secondary, the value of inter-winding capacitance is half of the traditional windinglayout. Considering the problem of AC resistance and the fact that inter-winding capacitance still has a largevalue, the minimization of overlapping between primary and secondary is not a practical way to mitigate theinter-winding capacitance problem. Instead, the inter-winding capacitance should be minimized through op-timizing the structure, increasing the separation distance between windings and, using the low permeabilitymaterials in the intersections.Having improved winding layouts and the optimized structure with low AC resistance and inter-windingcapacitance, now we can fabricate very low parasitic capacitance PTs for high efficiency LLC resonantconverter with wide output voltage regulation. These transformers can be used to resolve both CM noise andvoltage regulation problems in the LLC resonant converter.5.5 Experimental ResultsTo verify the theoretical hypothesis, the winding layouts under investigation were manufactured (total of 6)and employed in a 1.2kW LLC resonant converter. The experimental results show that the proposed PTs haveextremely lower parasitic elements in comparison to the conventional PTs which mitigates the light-loading1.1e-005Energy (J/m )32.4e-0051.5e-0066.6e-006Energy (J/m )31.5e-0055.7e-007(a) 25 pJ (b) 11.9 pJFigure 5.19: Inter-winding energy of one intersection of primary and secondary windings with a) Tra-ditional and b) Alternating & No overlapping layouts.117voltage regulation problem and also ensures high full-load efficiency by minimizing AC resistance and inter-winding capacitance. The specification of the converter and PTs are provided in Table. 5.4. Figures 5.20(a) and (b) show the prototypes of the special PTs under study and the LLC resonant converter platform,respectively.Table 5.4: Parameters definitionConverter Parameters Transformer PrametersParameters Value Parameters ValueVin 200 V Np/Ns 2:1 (8:4)Vout 96 V Core ELP 58/11/38Output Power 1200 W PCB Thickness 0.6mmf 200 kHz Copper Thickness 4 OzFigure 5.21 (a) shows the frequency response of different transformers with the secondary open. Aslong as the leakage inductances are negligible in comparison to the magnetizing inductance, the equivalentcapacitor in this condition is equal to Cstray. Considering the fact that open circuit inductance is the same inall conditions, Fig. 5.21 confirms that the proposed transformers have significantly lower stray capacitance.Figure 5.21 (b) shows the stray capacitance of different layouts. Among different layouts, zero voltagegradient winding layout has the lowest primary parallel stray capacitance. In comparison to the traditionalFI transformer, this transformer has 21.2 times less stray capacitance. Figure 5.21 (c) shows the inter-winding capacitance of the proposed transformers and shows that using an optimized structure and replacingFR4 with air significantly reduces the inter-winding capacitance. Among different layouts, zero voltagegradient winding layout again has the best result as its inter-winding capacitance is 16.6 times less than the(a) (b)TransformerResonant TankRectifierDSP Full-BridgeTrad-FR4PSPSPSPSTrad-AirPSSPPSSPNo-OverlapPSSPPSSPNo-OverlapPSSPPSSPOpt-OverlapPSSPPSSPAlternatingPSSPPSSPAlternate & NoPSSPPSSPZero GradientPSSPPSSPTrad-FR4PSSPPSSPFigure 5.20: Experimental prototypes: a) Transformers prototypes and b) LLC resonant converter plat-form1186806183851518756.9 49 320100200300400500600700800Primary Parallel Stray Cap (pF)201.557.634.6 31.1 29 28.2 27.5 27.5050100150200250AC Resistance (mOhm)1414808172 170 154 124 95 8502004006008001000120014001600Inter-Winding Capacitance (pF)(a)(c)(b)(d)21.2 times less intra-winding capacitance,solving the light-loading regulation problem. 16.6 times less inter-winding capacitance,Significantly Reducing the CM noise. Parasitic Capacitances are reducedwith no compromise on the resistance.Trad-FI950 kHzOpt Overlap2.05 MHzAlternating2.6 MHzZero Grad4.2 MHzRDC=24Figure 5.21: Parasitic values of the prototypes: a) frequency response, b) stray capacitance, c) inter-winding capacitance and d) AC resistancetraditional FI structure. Figure 5.21 (d) shows the AC resistance of the proposed transformers. This figureshows that while some of the proposed layouts increase the resistance to reduce the parasitic capacitance,zero voltage gradient winding layout reduces the parasitic capacitance without increasing the resistance.Therefore, this transformer is the best one among the proposed transformers in terms of parasitic capacitanceand AC resistance.Figures 5.22 (a) and (b) show full-load waveforms of the LLC resonant converter with the traditional PTand the proposed zero voltage gradient transformer. Here, the inverter voltage is the output voltage of thefull-bridge inverter. Comparing the waveforms shows that reducing the inter-winding capacitance reducesthe high-frequency currents and considerably improves the current waveforms. Figure 5.23 (a) shows thetransformer voltage under the no-load condition with the traditional PT. This figure shows that high straycapacitance distorts the transformer’s no-load voltage in such a way that it cannot be considered square-shaped. This distorted waveform makes serious problems in controlling output voltage under no-load and119(a) (b)Effect of large parasiticCapacitanceThe effect of minimizing the parasitic capacitanceipisvinvvsipisvinvvsFigure 5.22: Waveforms in the LLC resonant converter under full-loading condition with a) TraditionalFI and b) zero voltage gradient transformers. Inverter voltage (Ch1), primary current (Ch2),transformer secondary voltage (Ch3), and transformer secondary current (Ch4). This figureshows that reducing the inter-winding capacitances has attenuated CM noise.light-load conditions which cannot be predicted with FHA. On the other hand, Fig. 5.23 (b) shows the no-load voltage of converter with the proposed zero voltage gradient transformer. This figure shows that evenunder no-load condition, the transformer voltage still is square-shaped.Since large parasitic capacitances distort the transformer’s no-load voltage, FHA fails to consider allissues introduced by these parasitic capacitances and accurately predict the output voltage behavior. Fig.5.24 (a), (b), and (c) compare the voltage characteristics of the converter with different transformers inthree light-load conditions. This figure shows large stray capacitance leads to an unpredictable voltagebehavior under no-load condition. Figures 5.24 (b) and (c) show increasing the load can somehow improve(a) (b)High frequency ocilation on transformer voltage due to the high value of stray CapVery small voltage ocilation due to reducing the parasitic capacitanceipvinvvsipvinvvsFigure 5.23: Waveforms in the LLC resonant converter under no-load condition with a) traditional FIand b) zero voltage gradient transformers. Inverter voltage (Ch1), primary current (Ch2), andtransformer secondary voltage (Ch3). Reducing the stray capacitances has improved no-loadvoltage waveforms and successfully mitigated the light-load voltage regulation problem.120the situation. However, the voltage behavior still is unpredictable. In addition to the unpredictable behavior,the converter cannot regulate for low output voltages as shown in Fig. 5.24 (c). Minimizing the parasiticcapacitance can avoid these problems and enables the converter to regulate the output voltage. This figureshows that for the same sweep of frequency, the converter with zero voltage gradient transformer can providewider ranges of output and regulate the output voltage.PTs also are compared regarding the converter efficiency. Figure 5.24 (d) shows the full-load efficiencyof the converter at the resonant frequency with different transformers. This figure shows that zero voltagegradient transformer has the highest efficiency between different transformers. It is mainly due to lowresistance and low CM noise. The efficiency of other transformers that have higher resistance is slightlylower. In the case of Alternating & No overlapping winding layout, as explained in the previous sections,the interleaving does not improve the AC resistance, and this transformer has much higher AC resistance.00.20.40.60.811.21.41.61.80.75 0.9 1.05 1.2 1.35 1.5 1.65 1.8 1.95Vo/VinNormalized FrequencyLight-LoadingTrad-FI-FR4 (680 pF) Trad-Air (389 pF) Zero Gradient (32 pF)(a) (b)(c) (d)00.20.40.60.811.21.41.61.820.75 0.9 1.05 1.2 1.35 1.5 1.65 1.8 1.95Vo/VinNormalized FrequencyVery Light-LoadingTrad-FI-FR4 (680 pF) Trad-Air (385 pF) Zero Gradient (32 pF)00.511.522.533.50.75 0.9 1.05 1.2 1.35 1.5 1.65 1.8 1.95Vo/VinNrmalized FrequencyNo LoadTrad-FI-FR4 (680 pF) Trad-Air (389 pF) Zero Gradient (32 pF)95.195.996.1 96.196.2 96.296.394.494.895.295.69696.4Efficiency (Percent)Regulated voltage even in no-load!Effect of high stray capacitanceUnpredictable behaviordue to the parasiticcapacitances Figure 5.24: Converter voltage gain characteristic with different transformers at a) no load, b) verylight load and, c) light load. The conventional PT has serious regulation issues for all casesand the proposed Zero voltage gradient layout solves this problem by achieving an extremelylow capacitance. d) Full-load efficiency of the converter at resonant frequency with differenttransformers.121Therefore, the efficiency of this transformer is considerably lower than other transformers. As a result, thenon-overlapping strategy is not a suitable layout for high-efficiency applications.5.6 SummaryThis chapter presented the problems associated with the parasitic capacitance of PTs in LLC resonant con-verters and proposed mitigation strategies to reduce the parasitic capacitance and improve the converter’sperformance. It was shown that the high inter-winding capacitance makes the CM noise problems while theparallel stray capacitance leads to voltage regulation problems under the light-loading condition. In orderto overcome these problems, a systematic analysis was performed, and six improved PT winding layoutswere introduced and benchmarked with a traditional design. The proposed winding layouts were comparedregarding parasitic capacitance and resistance with the aid of analytical equations. As a result of the inves-tigation, an optimized structure with minimum AC resistance and inter-winding capacitance was found andverified by FEA and experimental tests. The proposed winding layouts and structure were used to manufac-ture PTs with very low parasitic capacitance. While all of the proposed transformers significantly reduce theparasitic capacitances, the proposed Zero voltage gradient layout has the best results as it has 21.2 times lessprimary stray capacitance and 16.6 times less inter-winding capacitance. This structure reduces the stray andinter-winding capacitances from 618pF and 1414pF to 32pF and 85pF , respectively. Another advantageof this transformer is that it reduces the parasitic capacitance without increasing the resistance and has thelowest parasitic capacitances and resistance at the same time. The experimental results of employing the pro-posed transformers in a 1.2 kW LLC resonant converter shows that not only the proposed transformers haveenhanced the performance and efficiency of the converter by minimizing AC resistance and inter-windingcapacitance, but also have mitigated the voltage regulation problem and enabled the converter to regulate theoutput voltage even under no-load condition.Besides the application in LLC resonant converters, the proposed winding layouts also can be used to de-sign inductors that have a wide-range operating frequency. Since they exhibit much smaller self-capacitance,such inductors have a large self-resonant frequency which is very desirable in high-frequency applications.122Chapter 6Conclusion6.1 Conclusions and ContributionsAlthough PTs feature many advantages such as low height, excellent thermal characteristics, modularity,flexibility, repeatability, and ease of manufacturability, they exhibit large parasitic capacitances which resultsin severe problems for DC-DC converters. Large parasitic capacitance in PTs is due to the proximity ofthe planar layers and their significant overlap. In particular, parasitic capacitances in the transformers aredivided into two groups: inter-winding and intra-winding capacitance. Intra-winding capacitance originatesfrom the capacitive coupling between layers of the same winding, while inter-winding capacitance is theresult of capacitive coupling between layers of different windings (i.e., one from primary and another fromsecondary). Inter-winding capacitance is the major source of CM noise in the converter which creates EMIissues. On the other hand, intra-winding capacitance affects the performance and efficiency of the converterand can result in loss of voltage regulation in LLC resonant converter.Comparing to wire-wound components, parasitic capacitances of PTs can be two orders of magnitudelarger. Such large values significantly deteriorate the performance of the circuit and cannot be ignored.Most of the publications for planar transformer design concern the reduction in leakage inductances andhigh-frequency winding losses, but winding capacitances have rarely been considered effectively. To fillthis void, this dissertation focuses on parasitic capacitances of PTs and sheds light on the complex nature ofcapacitive effects in PTs. By targeting the root cause of problems, this work proposes new design methodsthat resolve problems that arise from the large parasitic capacitance of PTs. The following subsectionssummarize contributions of this work.1236.1.1 Detailed Parasitic Capacitance Model of PTsParasitic capacitances in PTs are distributed, as each overlapping in the PT structure contributes to parasiticcapacitance. The total effect of distributed parasitic capacitance can be modeled by six lumped capacitorsin the transformer equivalent circuit. In chapter 2, the energy method has been used to develop a generalparasitic capacitance model for PTs. This model relates the distributed capacitance of individual layers tothe six-capacitor model of the transformer and provides a deep insight into how changing the winding ar-rangement can manipulate the value of each lumped capacitor. Two special cases of PTs were considered,and analytical equations were derived for each case. In addition to the proposed analytical model, method-ologies for extracting the six-capacitor model using FEA and experimental measurements were proposed.The proposed capacitance model has been verified using FEA and experimental characterization. This modelprovides the mathematical basis of the proposed ideas and is used in chapter 3 to analytically validate theconcept of paired layers.6.1.2 Concept of Paired LayersCM noise in the transformer originates from an undesired electrostatic coupling between primary and sec-ondary windings and also between windings and the core. In PTs, whenever a layer of the primary windingoverlaps with a layer of the secondary winding, due to the proximity and large overlapping area of planarlayers, a large parasitic capacitance is formed between overlapping layers. A parasitic capacitance also isformed between the core and layers of windings that are exposed to the core. When the voltage of over-lapping layers changes rapidly due to high-frequency switching, parasitic capacitance is exposed to a largedv/dt. This leads to the generation of pulsating currents (known as CM noise) that circulate in the circuitthrough the earth and create EMI problems. To minimize the CM noise of PTs, the concept of “paired layers”has been proposed in chapter 3. According to this concept, if overlapping layers have a similar layout andequal dv/dt at their ports, such overlapping does not generate CM noise. This means that if the structureof the PT is designed in a way that only paired layers overlap, the PT does not generate CM noise. Findingpaired turns depends on the voltage distribution on the transformer’s windings, which is topology-dependent.From the transformer’s voltage point of view, topologies were divided into three groups and a methodologyfor finding paired turns in each group has been presented. Examples also were provided for each group tomake the methodology easy to understand. The concept of paired layers also has been verified using anal-ysis. It was mathematically proven that any winding structure based on the concept of paired layers has anequivalent capacitor network that results in zero CM noise.1246.1.3 Paired Layers InterleavingInter-winding capacitance depends on the number of overlapping between primary and secondary layers,and more interleaved structures exhibit larger inter-winding capacitance. This creates a trade-off in thetransformer design, as the requirement of low AC resistance and low leakage inductance is in contradictionwith the requirement of low inter-winding capacitance. Interleaved structures that minimize AC resistanceand leakage inductance have many overlapping between primary and secondary layers, which results in largeinter-winding capacitance. On the other hand, separating primary and secondary windings (non-interleavedstructure) achieves low inter-winding capacitance at the expense of large AC resistance and leakage induc-tance. In most papers about optimizing PT, the main purpose is to reduce leakage inductances, and they dothis by proposing highly interleaved structures that minimize leakage fluxes. However, since these methodsdo not consider capacitive effects, they result in PTs with large inter-winding capacitance and large CM noisegeneration. No design method had been reported in the literature that resolves this trade-off to achieve bothlow AC resistance and very low CM noise generation. This has been considered in chapter 4 and interleavingmethods have been combined with the proposed “paired layers” concept to achieve PTs that not only haveminimum AC resistance and leakage inductance but also have almost zero generation of CM noise. In otherwords, “paired layers interleaving” finally eliminates the trade-off between low AC resistance and low CMnoise and gives the designer a tool to achieve both. Different methods of implementing this method usingPCBs and copper foils were proposed and the method has been developed for three groups of topologies.Examples for different turns ratios and topologies have been presented to show the generality of the methodand also to make it easy to understand.6.1.4 Low Parasitic Planar Transformers for LLC Resonant ConvertersThe high intra-winding capacitance of regular multi-turn PCB winding layouts causes a number of problemsin DC-DC converters. If used for planar inductors, large intra-winding capacitance reduces the self-resonantfrequency of the inductor, limiting its operating frequency range. If used as the planar transformer, thehigh intra-winding capacitance gives rise to a high charging current at the transformer input, resulting inlower efficiency and increased peak voltage stress across secondary rectifying devices. In addition to thoseproblems, intra-winding capacitance brings unwanted regulation issues for LLC resonant converters withwide output regulation. In order to overcome these problems, a systematic analysis was performed, and siximproved PT winding layouts were introduced and benchmarked with a traditional design. The proposedwinding layouts were compared regarding parasitic capacitances and resistance with the aid of analytical125equations. As a result of the investigation, an optimized structure with minimum AC resistance and inter-winding capacitance was found and verified by FEA and experimental results. The proposed winding layoutsand structure were used to manufacture PTs with very low parasitic capacitance. It was shown the proposedwinding layouts can reduce self-capacitance up to 21.2 times, without compromising winding resistance. Theexperimental results of employing the proposed transformers in a 1.2 kW LLC resonant converter showedthat the use of proposed winding layouts mitigated the voltage regulation problem and enabled the converterto regulate the output voltage even under no-load condition. Besides application in LLC resonant converter,the proposed winding layouts can be used to design inductors with a wide range of operating frequencies.Since they exhibit much smaller self-capacitance, such inductors have a large self-resonant frequency, whichis very desirable in high-frequency applications.6.2 Future WorkThis work opens up many full areas of research that can build upon its findings. Some of the main areas inwhich multiple Masters and Ph.D. students could be supervised include:• Paired layers interleaving for converters with full-bridge inverter: The paired layers concept requiresa quiet point on the primary winding. For converters with the full-bridge inverter, it was expected thata quiet point would exist in the middle of the primary winding. If that was the case, paired layersinterleaving in its current form could be applied to this type of converters. However, in the tests doneby the author, it was observed that the voltage at the middle point of the primary was affected by theswitching and voltage spike were present at switching moments. As a result, paired layers interleavingis not applicable to this type of converters. Investigating the root cause of this, finding mitigationstrategies to achieve a quiet point on primary and consequently applying paired layers concept on thistype of converters remains to be studied.• PT capacitance tuning to cancel switch’s CM noise: Besides the transformer, MOSFET’s drain toheatsink parasitic capacitance is another major source of CM noise in the circuit. Paired layers inter-leaving minimizes PT’s CM noise. However, it does not do anything about the CM noise of the switch.The proposed parasitic capacitance model shows how winding arrangement affects the equivalent par-asitic capacitance network of the transformer. Instead of using paired layers interleaving to achievezero CM noise, the parasitic capacitance model can be used to design PT in a way that its CM noisecancels out CM noise of the switch, making net CM noise of the converter equal to zero. This is a126major opportunity to fully eliminate the total CM noise of the converter which remains as the futurework.• Application of paired layers interleaving in matrix transformers: The matrix transformer is defined asan array of elements inter-wired so that the whole functions as a single transformer. The benefits ofthe matrix transformer are that it can split current between secondary windings connected in paral-lel, reduce leakage inductance, reduce winding AC resistance, and improve thermal performance bydistributing the power loss throughout the elements. All those features make the matrix transformervery attractive for high current and high-frequency applications. Developing paired layers interleavingfor matrix transformers gives them the benefit of no CM noise generation which makes this type oftransformers even more desirable. This remains a topic of future research.127Bibliography[1] M. A. Saket, M. Ordonez and N. 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High-efficiency and low noise planar transformers for power converters : paired layers interleaving Saket Tokaldani, Mohammad Ali 2020
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Title | High-efficiency and low noise planar transformers for power converters : paired layers interleaving |
Creator |
Saket Tokaldani, Mohammad Ali |
Publisher | University of British Columbia |
Date Issued | 2020 |
Description | Nowadays, many applications, such as consumer electronics, the automotive industry, and telecoms require high power density and low height power electronics converters. To implement slim power converters, Planar Transformers (PT) have emerged, featuring low height, low leakage inductance, and low thermal resistance. Despite these benefits, PTs have large parasitic capacitance, which degrades the performance of power converters. Capacitive effects in transformers are divided into two groups: inter-winding and intra-winding capacitance. Inter-winding capacitance generates large amounts of Common-Mode (CM) noise, creating serious Electromagnetic Interference (EMI) problems. Intra-winding capacitance affects the performance of the converter and can cause loss of voltage regulation in the LLC resonant converter. The inter-winding capacitance can be reduced by separating primary and secondary windings, at the cost of increased leakage inductance and AC resistance. On the other hand, interleaved structures minimize AC resistance and leakage inductance but significantly increase the inter-winding capacitance. Therefore, there is an unfortunate trade-off in the transformer design. In order to resolve this trade-off as well as problems resulting from PTs large parasitic capacitance, this dissertation develops new design methods that target the root cause of the problem. A detailed parasitic capacitance model is developed for PTs that relate the distributed capacitance of layers to the equivalent circuit of the transformer. Based on this model, the concept of paired layers is introduced that provides criteria to achieve zero CM noise generation in PTs. Paired layers can be used to design interleaved structures that not only have low AC resistance and leakage inductance but also have almost zero CM noise generation. Multiple examples are provided for different types of windings, different turn ratios, and different topologies to show the generality of the method. The proposed method is validated using analysis, Finite Element Method (FEM), and experiments. Besides the paired layers method, this dissertation studies the detrimental effects of PTs large intrawinding capacitance on light-load voltage regulation of LLC resonant converter. It is shown that large intrawinding capacitance results in loss of voltage regulation. To resolve this, six improved winding layouts with low intra-winding capacitance are presented to maintain voltage regulation even under no-load condition. |
Genre |
Thesis/Dissertation |
Type |
Text |
Language | eng |
Date Available | 2020-04-08 |
Provider | Vancouver : University of British Columbia Library |
Rights | Attribution-NonCommercial-NoDerivatives 4.0 International |
DOI | 10.14288/1.0389775 |
URI | http://hdl.handle.net/2429/73948 |
Degree |
Doctor of Philosophy - PhD |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
GraduationDate | 2020-05 |
Campus |
UBCV |
Scholarly Level | Graduate |
Rights URI | http://creativecommons.org/licenses/by-nc-nd/4.0/ |
AggregatedSourceRepository | DSpace |
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