Advanced Monitoring andControl of Distributed DCSystemsAn Embedded Impedance Detection ApproachbyFrancisco PazIng., Universidad Nacional del Comahue, 2012M.A.Sc., The University Of British Columbia, 2014A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFDOCTOR OF PHILOSOPHYinThe Faculty of Graduate and Postdoctoral Studies(Electrical & Computer Engineering)THE UNIVERSITY OF BRITISH COLUMBIA(Vancouver)February 2020c© Francisco Paz, 2020The following individuals certify that they have read, and recommend to the Faculty ofGraduate and Postdoctoral Studies for acceptance, the thesis entitled:Advanced Monitoring and Control of Distributed DC SystemsAn Embedded Impedance Detection Approachsubmitted by Francisco Paz in partial fulfillment of the requirements forthe degree of Doctor of Philosophyin Electrical and Computer EngineeringExamining Committee:Dr. Martin OrdonezSupervisorDr. William DunfordSupervisory Committee MemberDr. John MaddenSupervisory Committee MemberDr. Andre IvanovUniversity ExaminerDr. Elod GyengeUniversity ExamineriiAbstractDirect Current (DC) systems, made possible by power electronics technology, are becomingmore prevalent due to their advantages when integrating renewable energy sources, energystorage, and DC loads. Microgrids and local area energy systems are instrumental to DCsystems, and much progress has been made around them. However, DC microgrids face nu-merous challenges due to their decentralized nature, such as resource optimization, control,and protection. This thesis focuses on developing a core technology, an embedded impedancedetection (EZD) method for DC systems, and its application to five critical challenges in DCsystems. The proposed method uses a reference signal of minimal amplitude and high fre-quency, injected in the control loop of the power electronic converter, and a digital Lock-InAmplifier to extract the incremental behavior of the voltage and current around the DCoperating point. These are used to calculate the incremental impedance, which is repre-sentative of the reactive part of the system as well as the nonlinear characteristics of thesystem. The proposed EZD method is applied to address five critical problems in today’sDC systems: 1) adaptive control in the presence of active loads - to expand stability andimprove transient response; 2) islanding detection - to detect the connection and disconnec-tion of the utility grid and change controllers for autonomous operation; 3) fault location -to detect the distance to a fault and simplify the system restoration; 4) high-impedance faultdetection - to accurately distinguish a fault condition from a load increase; and 5) maximumpower point tracking of photovoltaic panels - to ensure efficient energy harvesting. For allthese applications, the proposed EZD-based solution offers critical benefits and advantages,iiisuch as high sensitivity and accuracy at a low system disturbance and fast detection. Thework presents a detailed analysis of the proposed EZD technique as well as considerationsfor its implementation in commercial microcontrollers, followed by simulations to illustrateits capabilities. The thesis also presents a detailed analysis of each DC system applicationand its particular considerations. The outlined benefits are supported by simulations andvalidated through experimental results using a real power electronics platform.ivLay SummaryThe accelerated adoption of renewable energy sources (such as solar and wind) and equipmentthat uses Direct Current (DC) natively (such as electric vehicles, information technology, andconsumer electronics) presents challenges compare to traditional power systems based onAlternating Current (AC). Smart power electronics converters and local area electric powersystems based on DC can enable the efficient integration of these renewable energy sources,but they are not without problems. This work proposes solutions to some of the mainchallenges faced by DC systems integrating renewable energy sources. A core technique,embedded impedance detection, which allows extraction of information from the system,is presented. This tool is used to optimize the operation of renewable energy sources, todynamically adjust the control of the system to changing demands, and to allow the systemto detect problems and operate on its own. This work contributes to the development of DCtechnologies which are fundamental to a more renewable power system.vPrefaceThis work is based on research performed at the Electrical and Computer Engineering de-partment of The University of British Columbia by Francisco Paz, under the supervision ofDr. Martin Ordonez.Chapter 2 contains modified versions of all the publications below.Portions of Chapter 3 have been published at the IEEE International Symposium onPower Electronics for Distributed Generation Systems (PEDG) and IEEE Transactions onIndustrial Electronics [1, 2]:• F. Paz and M. Ordonez, “An Embedded Impedance Measurement for DC MicrogridsBased on a Lock-In Amplifier,” in Proc. 7th IEEE Int. Symp. Power Electronics forDistributed Generation Systems (PEDG), Jun. 2016, pp. 1–6.• F. Paz and M. Ordonez, “High-Accuracy Impedance Detection to Improve TransientStability in Microgrids,” IEEE Transactions on Industrial Electronics, vol. 64, no. 10,pp. 8167–8176, Oct. 2017.Portions of Chapter 4 have been published at the IEEE International Symposium onPower Electronics for Distributed Generation Systems (PEDG) [3] and an extended versionis in preparation to be submitted for review to a journal:• F. Paz and M. Ordonez, “An Impedance-Based Islanding Detection Method for DCGrids,” in Proc. 9th IEEE Int. Symp. Power Electronics for Distributed GenerationSystems (PEDG), Jun. 2018, pp. 1–7.viPortions of Chapter 5 have been published at the IEEE International Symposium onPower Electronics for Distributed Generation Systems (PEDG) [4] and an extended versionis in preparation to be submitted for review to a journal:• F. Paz and M. Ordonez, “Embedded Fault Location in DC Microgrid Systems Based ona Lock-In Amplifier,” in Proc. 8th IEEE Int. Symp. Power Electronics for DistributedGeneration Systems (PEDG), Apr. 2017, pp. 1–6.Portions of Chapter 6 have been accepted to the IEEE International Symposium on PowerElectronics for Distributed Generation Systems (PEDG) [5]:• F. Paz and M. Ordonez, “High-Impedance Fault Detection Method for DC Microgrids,”in Proc. 10th IEEE Int. Symp. Power Electronics for Distributed Generation Systems(PEDG), Jun. 2019, pp. 1–6.Portions of Chapter 7 have been published at the IEEE International Symposium onPower Electronics for Distributed Generation Systems (PEDG) and IEEE Transactions onIndustrial Electronics [6, 7]:• F. Paz and M. Ordonez, “Fast and Efficient Solar Incremental Conductance MPPTUsing Lock-In Amplifier,” in Proc. 6th IEEE Int. Symp. Power Electronics for Dis-tributed Generation Systems (PEDG), Jun. 2015, pp. 1–6.• F. Paz and M. Ordonez, “High-Performance Solar MPPT Using Switching Ripple Iden-tification Based on a Lock-In Amplifier,” IEEE Transactions on Industrial Electronics,vol. 63, no. 6, pp. 3595–3604, Jun. 2016.As the first author of these publications, the author of this thesis developed the theoreticalcontribution, the simulation models, and performed the experimental work. The authorreceived advice and technical support from Dr. Ordonez and members of his research team.viiTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiLay Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiiList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiiList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiiiList of Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviiList of Symbols and Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiAcknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxivDedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvi1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.2.1 Impedance Detection . . . . . . . . . . . . . . . . . . . . . . . . . . 61.2.2 Control of Power Converters in DC Systems with Active Loads . . . 8viii1.2.3 Islanding Detection and Autonomous Operation of DC Microgrids . 101.2.4 Fault Location in DC Systems . . . . . . . . . . . . . . . . . . . . . 121.2.5 High-Impedance Fault Detection in DC Systems . . . . . . . . . . . 141.2.6 Maximum Power Point Tracking for Photovoltaic Panels . . . . . . . 151.3 Contributions of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171.4 Dissertation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Incremental Impedance Measurement in Power Electronics Converters 222.1 Reference Generation and Injection . . . . . . . . . . . . . . . . . . . . . . . 252.2 Signal Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292.2.1 Moving Average Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 312.2.2 Digital Lock-In Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 352.3 Impedance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452.4 Embedded Impedance Detection Simulations . . . . . . . . . . . . . . . . . 482.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 Transient Performance and Stability Improvement in DC Systems . . . 513.1 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533.1.1 Load Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.1.2 Dynamic Model of the System . . . . . . . . . . . . . . . . . . . . . 583.2 Proposed Incremental Load Detection Scheme . . . . . . . . . . . . . . . . . 613.2.1 Equivalent Incremental Load Detection . . . . . . . . . . . . . . . . 623.2.2 Control Adjustment Technique . . . . . . . . . . . . . . . . . . . . . 643.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703.5 Comparison Against Other Equivalent Load Detection Techniques . . . . . 743.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77ix4 Islanding Detection and Autonomous Operation for DC Systems . . . . 794.1 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814.1.1 DC System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824.1.2 Composite Load Model . . . . . . . . . . . . . . . . . . . . . . . . . 834.1.3 Bumpless Controller Mode Change . . . . . . . . . . . . . . . . . . . 874.1.4 Traditional Islanding Detection Method . . . . . . . . . . . . . . . . 894.2 Proposed Islanding Detection Method . . . . . . . . . . . . . . . . . . . . . 914.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994.5 Comparison Against Other Islanding Detection Techniques . . . . . . . . . . 1024.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035 Low-Impedance Fault Location . . . . . . . . . . . . . . . . . . . . . . . . . 1055.1 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075.2 Proposed LIF Location Method . . . . . . . . . . . . . . . . . . . . . . . . . 1115.2.1 LIF Before Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125.2.2 Load Before LIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256 High-Impedance Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . 1276.1 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296.2 Proposed HIF Detection Method . . . . . . . . . . . . . . . . . . . . . . . . 1326.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142x7 Maximum Power Point Tracking for PV Systems . . . . . . . . . . . . . . 1447.1 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1467.1.1 Photovoltaic Panel Background . . . . . . . . . . . . . . . . . . . . . 1477.1.2 Standard InCond MPPT Algorithm . . . . . . . . . . . . . . . . . . 1507.2 Proposed LIA-Based MPPT . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527.2.1 DC Conductance Measurement . . . . . . . . . . . . . . . . . . . . 1547.2.2 Incremental Conductance Measurement . . . . . . . . . . . . . . . . 1557.2.3 MPP Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567.2.4 Stability of the Proposed MPPT . . . . . . . . . . . . . . . . . . . . 1577.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667.5 Comparison Against Other MPPT Methods . . . . . . . . . . . . . . . . . . 1697.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1758.1 Conclusions and Contributions . . . . . . . . . . . . . . . . . . . . . . . . . 1758.1.1 Improve Transient and Stability . . . . . . . . . . . . . . . . . . . . 1768.1.2 Islanding Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778.1.3 Low-Impedance Fault Location . . . . . . . . . . . . . . . . . . . . . 1778.1.4 High-Impedance Fault Detection . . . . . . . . . . . . . . . . . . . . 1788.1.5 Photovoltaic Maximum Power Point Tracking . . . . . . . . . . . . . 1798.1.6 Specific Academic Contributions . . . . . . . . . . . . . . . . . . . . 1808.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185xiList of Tables2.1 Sample LIA Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.1 Normalized Simulation Parameters for Equivalent Incremental Load Detection 673.2 Equivalent Load Detection Simulation . . . . . . . . . . . . . . . . . . . . . 673.3 Experimental Set-Up Parameters . . . . . . . . . . . . . . . . . . . . . . . . 733.4 Experimental Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 743.5 Comparison of the Proposed Technique with Existing Methods . . . . . . . . 764.1 Normalized Simulation Parameters for Islanding Detection . . . . . . . . . . 944.2 Simulation Load Cases Considering R1,n = R2,n = 0.01 . . . . . . . . . . . . 944.3 Experimental Set-Up Parameters . . . . . . . . . . . . . . . . . . . . . . . . 1004.4 Comparison of the Proposed Technique with Existing Methods . . . . . . . . 1025.1 Simulation Circuit Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 1185.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215.3 Experimental Set-Up Configuration . . . . . . . . . . . . . . . . . . . . . . . 1245.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246.1 Experimental Set-up Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 1397.1 Simulation Profile Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617.2 MPPT Experimental Set-up Parameters . . . . . . . . . . . . . . . . . . . . 1677.3 MPPT Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 172xiiList of Figures1.1 Diagram of a DC Microgrid with the proposed EZD tool built-In . . . . . . . 32.1 Incremental Behavior of DC Loads and Sources Around the Operating Point 232.2 Block Diagram of the DSP Implementation . . . . . . . . . . . . . . . . . . 242.3 Nested Loop Power Electronics Converter Controller with Reference Injection 262.4 Reference Generation from a Circular Buffer . . . . . . . . . . . . . . . . . . 292.5 Lock-In Amplifier Signal-Processing Chain . . . . . . . . . . . . . . . . . . . 302.6 Moving Average Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . 322.7 Moving Average Filter Frequency and Step Response . . . . . . . . . . . . . 342.8 Digital Lock-In Amplifier Block Diagram and Operation . . . . . . . . . . . 362.9 Generation of the Sine, Cosine, and Reference . . . . . . . . . . . . . . . . . 402.10 Example Circuit and Bode Plot for LIA . . . . . . . . . . . . . . . . . . . . 422.11 Example Simulation Output for the LIA . . . . . . . . . . . . . . . . . . . . 442.12 Expanded Diagram of the Impedance Calculation . . . . . . . . . . . . . . . 452.13 Impedance Detection Simulation Circuit . . . . . . . . . . . . . . . . . . . . 492.14 Embedded Impedance Detection Simulation Outputs . . . . . . . . . . . . . 503.1 Block Diagram and Key Benefits of the Impedance Based Controller . . . . . 523.2 Power Electronics Converter and Load Schematic . . . . . . . . . . . . . . . 543.3 VI Curves of a Resistive and Constant Power Load . . . . . . . . . . . . . . 563.4 VI Curves of a Combined Load . . . . . . . . . . . . . . . . . . . . . . . . . 58xiii3.5 Power Electronics Converter and Load Control Model . . . . . . . . . . . . . 593.6 VI and Time Domain Curves of a Combined Load with Net-Resistive Nature 633.7 VI and Time Domain Curves of a Combined Load with Net-CPL Nature . . 643.8 VI and Time Domain Curves of a Combined Load with Net-Zero . . . . . . . 653.9 Simulations of the Proposed Incremental Load Detection . . . . . . . . . . . 693.10 Load Profile for the Simulations . . . . . . . . . . . . . . . . . . . . . . . . . 693.11 Simulations of the Adaptive Technique . . . . . . . . . . . . . . . . . . . . . 703.12 Simulations of the Standard Controller for 25% CPL . . . . . . . . . . . . . 713.13 Simulations of the Standard Controller for 100% CPL . . . . . . . . . . . . . 713.14 Picture of the Experimental Set-Up for the Equivalent Load Test . . . . . . 723.15 Experimental Capture of the Impedance Detection Injected Reference . . . . 733.16 Experimental Captures of the Equivalent Load Detection . . . . . . . . . . . 754.1 Block Diagram of the DC Microgrid and Outline of the Proposed ID Algorithm 804.2 Incremental Model of the Power Electronics Converter in GTM and IM . . . 824.3 V-I Curves of Different Loads . . . . . . . . . . . . . . . . . . . . . . . . . . 844.4 Incremental Resistance for CPL+CRL and CCL+CRL . . . . . . . . . . . . 874.5 Proposed Islanded Mode Controller . . . . . . . . . . . . . . . . . . . . . . . 884.6 Block Diagram and Time Diagram of a Standard Islanding Detection Method 904.7 Block and Time Diagram of the Proposed Islanding Detection Method . . . 914.8 Simulations of the Proposed Islanding Detection in Open Loop . . . . . . . . 964.9 Detail of the Simulations of the Proposed Islanding Detection in Open Loop 974.10 Impedance Plane Simulation Results for Different Loads . . . . . . . . . . . 984.11 Simulations of the Closed Loop System with Droop Control . . . . . . . . . 994.12 Diagram Experimental Set-Up . . . . . . . . . . . . . . . . . . . . . . . . . 1004.13 Experimental Captures of Islanding Detection in Open Loop . . . . . . . . . 101xiv5.1 General Outline of the Proposed LIF Location Method . . . . . . . . . . . . 1065.2 Diagram of the System with a LIF Before the Load . . . . . . . . . . . . . . 1085.3 Diagram of a Reconfigurable Ring DC Microgrid . . . . . . . . . . . . . . . . 1105.4 Diagram of the System with a LIF After the Load . . . . . . . . . . . . . . . 1105.5 Reconfigurale System to Improve the Low Impedance Fault Location . . . . 1115.6 Proposed LIF Location Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 1115.7 Simulation Schematic for the Proposed LIF Location Method . . . . . . . . . 1185.8 Simulation Results for Case 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 1195.9 Simulation Results for Case 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 1205.10 Simulation Results for Case 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 1215.11 Picture of the Experimental Set-Up for the LIF Test . . . . . . . . . . . . . 1235.12 Experimental Capture for Case 1 . . . . . . . . . . . . . . . . . . . . . . . . 1255.13 Experimental Capture for Case 2 . . . . . . . . . . . . . . . . . . . . . . . . 1255.14 Experimental Capture for Case 3 . . . . . . . . . . . . . . . . . . . . . . . . 1266.1 Block Diagram and Time Diagram of the HIF Detection Method . . . . . . 1286.2 DC and Incremental Schematic of the System . . . . . . . . . . . . . . . . . 1306.3 Current and Resistance as a Function of the Load State . . . . . . . . . . . . 1316.4 Effect of a Higher Impedance in the Detection . . . . . . . . . . . . . . . . . 1326.5 Block and Time Diagram of the Proposed HIF Detection Method . . . . . . 1336.6 Simulations of the Load Step-Up . . . . . . . . . . . . . . . . . . . . . . . . 1366.7 Simulations of the HIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1376.8 Picture of the Experimental Set-Up for the HIF Test . . . . . . . . . . . . . 1386.9 Experimental Capture of the Set-Up After a Load Increase . . . . . . . . . . 1406.10 Experimental Capture of the Set-Up After a HIF . . . . . . . . . . . . . . . 1416.11 Comparison of the Experimental Outputs . . . . . . . . . . . . . . . . . . . . 142xv7.1 Block Diagram and General Comparison of the Proposed MPPT vs. the Clas-sical Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457.2 Structure of a PV Cell and Behavioral Model . . . . . . . . . . . . . . . . . 1477.3 Voltage-Current-Power Curves of a PV panel . . . . . . . . . . . . . . . . . 1497.4 MPP Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507.5 Flowchart and Time Diagram of the InCond MPPT . . . . . . . . . . . . . 1517.6 Block and Time Diagram of the LIA-Based InCond MPPT . . . . . . . . . 1537.7 Stability block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1587.8 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607.9 Simulations of the Traditional InCond . . . . . . . . . . . . . . . . . . . . . 1627.10 Simulations of the LIA-Based MPPT . . . . . . . . . . . . . . . . . . . . . . 1637.11 Details of the Simulated Transitions . . . . . . . . . . . . . . . . . . . . . . 1647.12 V-I View of the Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657.13 Start-Up Profile as a Function of KI . . . . . . . . . . . . . . . . . . . . . . 1657.14 MPPT Tracking Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667.15 Picture of the Experimental Set-Up for the MPPT Test . . . . . . . . . . . . 1687.16 Experimental Capture of the LIA-Based InCond . . . . . . . . . . . . . . . . 1707.17 Experimental Capture of the Standard InCond . . . . . . . . . . . . . . . . 171xviList of AcronymsAC Alternating CurrentADC Analog to Digital ConverterBIBO Bounded Input Bounded OutputBW BandwidthCB Current BreakerCL Current LoopCCL Constant Current LoadCPL Constant Power LoadCRL Constant Resistance LoadCV Constant Voltage (MPPT method)DAC Digital to Analog ConverterDC Direct CurrentDSP Digital Signal ProcessorDTFT Discrete Time Fourier TransformDZ Detection ZonexviiEMS Energy Management SystemEZD Embedded Impedance DetectionFFT Fast Fourier TransformFIR Finite Impulse ResponseFOCV Fractional Open Circuit Voltage (MPPT method)FSCI Fractional Short Circuit Current (MPPT method)GTM Grid-Tie ModeHIF High Impedance FaultHVDC High Voltage DCID Islanding DetectionIDM Islanding Detection MethodIM Islanded ModeInCond Incremental Conductance (MPPT method)IEEE Institute of Electrical and Electronics EngineersKF Kalman FilterLIA Lock-In AmplifierLIF Low Impedance FaultLPF Low Pass FilterMAF Moving Average FilterxviiiMAP Magnitude and PhaseMPP Maximum Power PointMPPT Maximum Power Point TrackingNDZ Non-Detection ZoneOCP Over-Current ProtectionOM Operating ModePEC Power Electronics ConverterPEDG International Symposium on Power Electronics for Distributed Generation SystemsPI Proportional Integral (Controller)PID Proportional Integral Derivative (Controller)P&O Perturb and Observe (MPPT method)PPU Power Probe UnitPSO Particle Swarm Optimization (MPPT method)PV PhotovoltaicPWM Pulse Width ModulationRLS Recursive Least SquaresROCOF Rate of Change of FrequencyRT Rate TransitionTAB Triple Active BridgexixTHD Total Harmonic DistortionTZ Trip-ZoneUBC The University of British ColumbiaUV/OV Under Voltage/Over VoltageVL Voltage LoopxxList of Symbols and NotationBelow there is a list of the most commonly used symbols in the document. Some symbolstake special meanings as auxiliary variables in a limited scope in the document (such as xbeing a generic input signal when explaining a digital filter, instead of the imaginary part ofthe incremental impedance); when this is the case, it is indicated in the text.θn phase of the n-th harmonicAn Amplitude of the n-th harmonicAr Amplitude of the reference signalb Incremental susceptance b = Im (y)ex Error of the variable x (such as tracking error, measurement error, estimationerror)fr Frequency of the reference signalfs Sampling frequencyfsw Switching frequencyg Incremental conductance g = Re (y)iin Input currentio Output currentxxiM Number of samples in the buffer of the MAFN Number of samples in a period of the reference signalNp Number of periods of the reference signal averaged by the LIAr Incremental resistance r = Re (z)TMPPT Sampling Period of the MPPT algorithmTr period of the reference signal (1/fr)Ts Sampling Period (1/fs)Tsw Switching Period (1/fsw)ipv Current output of the photovoltaic panelvin Input voltagevo Output voltagevpv Voltage output of the photovoltaic panelr Incremental reactance x = Im (z)y Incremental admittance: y = 1/z = g + j bz Incremental impedance: z = r + j xxxiiNotation• Some variables have a subscript ending in ..., n (such as vo,n); this indicates the ”nor-malized value of vo”.• Some variables have a hat accent (such as vˆo); this indicates the ”estimated value ofvo”, usually the output of a computation through an algorithm.• Some variables have a tilde accent (such as v˜o); this indicates the ”the incrementalvalue around the DC operating point”.• Some variables have an asterisk super-index (such as v∗o); this indicates a set-point toa control loop.• Capitalized versions of variables (Vo to vo) signify the average value of vo, in generalthe quiescent point of the variable.• Variables followed by (t) (such as vo(t)) are assumed to analog (continuous in time).• Variables followed by [k] (such as vo[k]) are assumed to be discrete (either as a sampledversion of an analog signal) or generated discretely. k can be replaced as the indexvariable by other symbol (such as i, K, n), when this is the case, it is indicated in thetext.xxiiiAcknowledgmentsFirstly, I would like to thank my supervisor, Dr. Martin Ordonez, for the opportunity tojoin his team. It has been an experience beyond my dreams. His technical support, patience,drive, and leadership are an inspiration to me.This work greatly benefited from the various people who reviewed it and provided com-ments and suggestions. I am grateful to the members of my Ph.D. committee, Dr. Dunfordand Dr. Madden, for the feedback and comments at various stages of my program. I alsowant to thank Dr. Jaeger for chairing my exams and providing valuable insights that im-proved the work. Finally, I am grateful for the input I received from reviewers, editors, andpeers at conferences and symposiums.My gratitude goes to all those who work at Dr. Ordonez’s Lab at the University of BritishColumbia, for making my Ph.D. experience unforgettable. I want to thank in particular Dr.Ion (Isbi) Isbasescu for the support building prototypes; not to mention for the candy thatfueled the late-night work. Dr. Rafael Pen˜a-Alzola, for the values and principles, for thehonest feedback and discussion, and the fun we had in the lab. I am eternally in debt toIgnacio (Nacho) Galiano Zurbriggen, for the years of friendship and support. His insight hasbeen invaluable, and his leadership showed me the way to be better. I am grateful to AndresBianchi, Dr. Emanuel Serban, and Dr. Ali Arefifar for the contributions to our shared work.My gratitude goes to the University of British Columbia, and the Department of Electricaland Computer Engineering for supporting my research. Their generous financial supportmade this journey possible; their outstanding human support made it enjoyable.xxivI want to thank Alpha Technologies and the people who work there for the opportunityto collaborate with them. Special thanks go to Victor Goncalves, Dr. Rahul Khandekar, andPeter Ksiazek; their input is invaluable.I leave for the last those who are closest to my heart. I am grateful to my parents, Rosa andCesar, and my sisters Carmen, Lola, and Carola, for being always supportive of my passions,and for sharing theirs with me. Their continuous support got me this far. A special thanksgo to my nephews, Santiago, Valentino, and Emilio, and my cousin Juanchi; they bring joyto my life. Other special thanks go to Bruno, who arrived just in time to be included in thisacknowledgment.Finally, I would like to thank my partner, Celeste, for all the love and support; for herpatience and companionship; for her continuous encouragement and kindness; for the hun-dreds, if not thousands, of kilometers walked together in Vancouver. Nothing would be worthdoing without her.xxvTo Abu N˜ata, our grandmotherxxviChapter 1Introduction1.1 MotivationIntending to reduce greenhouse gas emissions due to human activities, small local powerand energy systems based on renewable energy are becoming more attractive. Traditionalenergy production (coal and gas plants, big hydroelectric dams, and nuclear power plants)are controllable. Therefore, they can rely on the centralized generation and the AlternatingCurrent (AC) transmission and distribution grid to efficiently integrate them. On the otherhand, energy harvesting from renewable energy resources (such as wind, ocean, tidal, andsolar) is at the whim of the sun, wind, or ocean and produces variable voltages and currentsPortions of this chapter have been published in• F. Paz and M. Ordonez, “An Impedance-Based Islanding Detection Method for DC Grids,” in Proc. 9th IEEE Int.Symp. Power Electronics for Distributed Generation Systems (PEDG), Jun. 2018, pp. 1–7.• F. Paz and M. Ordonez, “Fast and Efficient Solar Incremental Conductance MPPT Using Lock-In Amplifier,” in Proc.6th IEEE Int. Symp. Power Electronics for Distributed Generation Systems (PEDG), Jun. 2015, pp. 1–6.• F. Paz and M. Ordonez, “High-Performance Solar MPPT Using Switching Ripple Identification Based on a Lock-InAmplifier,” IEEE Transactions on Industrial Electronics, vol. 63, no. 6, pp. 3595–3604, Jun. 2016.• F. Paz and M. Ordonez, “An Embedded Impedance Measurement for DC Microgrids Based on a Lock-In Amplifier,” inProc. 7th IEEE Int. Symp. Power Electronics for Distributed Generation Systems (PEDG), Jun. 2016, pp. 1–6.• F. Paz and M. Ordonez, “High-Accuracy Impedance Detection to Improve Transient Stability in Microgrids,” IEEETransactions on Industrial Electronics, vol. 64, no. 10, pp. 8167–8176, Oct. 2017.• F. Paz and M. Ordonez, “An Impedance-Based Islanding Detection Method for DC Grids,” in Proc. 9th IEEE Int.Symp. Power Electronics for Distributed Generation Systems (PEDG), Jun. 2018, pp. 1–7.• F. Paz and M. Ordonez, “Embedded Fault Location in DC Microgrid Systems Based on a Lock-In Amplifier,” in Proc.8th IEEE Int. Symp. Power Electronics for Distributed Generation Systems (PEDG), Apr. 2017, pp. 1–6.• F. Paz and M. Ordonez, “High-Impedance Fault Detection Method for DC Microgrids,” accepted to 10th IEEE Int.Symp. Power Electronics for Distributed Generation Systems (PEDG).1that are not directly compatible with the AC system. Power Electronics Converters (PECs)are developed to interface these variable inputs to grid-compatible AC levels; however, thiscan be achieved more efficiently by using Direct Current (DC) directly.DC systems often use different architectures than AC systems. Many are connected tothe utility grid but are also able to operate on their own (islanded mode), receiving the namemicrogrids. This name is given to a wide range of configurations, from megawatt systemsintegrating large areas and resources, to small scale grids that feed a single house, a singleship, or a telecommunications hub rated at a couple of kilowatts. Figure 1.1 presents onemicrogrid and the different elements in it.Power electronics is one of the key enabling technologies of the microgrid, allowing forcontrol of power flow and quality. The PECs in Fig. 1.1 convert variable voltage, current,and frequency, coming from renewable energy sources, into a regulated voltage and currentthat meet the requirements of the loads, at extreme levels of efficiency and density. Digitalcontrol allows the benefits of power electronics to be extended by adding novel features, suchas automatic resource optimization, which are fundamental for an efficient power system.Moving from a centralized generation architecture (such as the traditional power system)to a distributed generation architecture introduces the challenge of distributing the controland operations. While the traditional grid has only a few power plants to control, thedistributed architecture can lead to multiple generators without a direct way to be controlledby the utility. Moreover, centralized control would depend on a communications lifeline,which then becomes a critical point of failure in the system.Examples of areas of intense research in DC systems technology are:• resource optimization,• islanding detection,• fault detection, analysis, isolation, and system restoration,2av bvbiaiAC MPPTID HIFLIFEZDvivAiAxvxiDCIDCVrArfDC microgridxˆj+r= ˆzˆLIALIAFigure 1.1: DC microgrids offer advantages when integrating renewable energy sources (suchas PV and wind), energy storage (such as batteries), and loads (such as variable speeddrives and IT equipment), but they have some critical problems; this thesis focuses on thedevelopment of a core technology, an embedded impedance detection (EZD) algorithm builtinto each power electronics converter, which allows each converter to inject a reference signalof minimal amplitude and high frequency, and extract the incremental behavior of the systemaround the current operating point using a Lock-In Amplifier (LIA); this information is usedto address five key problems depending on which converter is considered: (A) adaptive control(AC) for extended stability and improved dynamic performance, (B) islanding detection (ID)for autonomous operation, (C) low impedance fault (LIF) location to find the distance to afault in the system, (D) high-impedance fault (HIF) detection to differentiate a fault from aload change, and (E) maximum power point tracking (MPPT) for PV panels.3• protection coordination,• and stability.Moreover, the magnitudes in DC systems (voltage and currents) present a constant value ata given operating point. The operation of the DC system around constant voltage masksmany characteristics of the system, and finding ways to extract them without adding cost inthe form of hardware or significant disturbances is challenging. This leads to slow adoptionof DC distribution technology and its benefits. For example, the output voltage and currentof a DC converter do not convey information about the reactive part of the load; the phasedifference between voltage and current in an AC system can be used to detect the reactivepart of the impedance.This work introduces a solution to some of the main challenges faced by DC systemsthrough an embedded impedance detection (EZD) algorithm built into each power converterin the microgrid. The EZD uses a reference signal of small amplitude and known frequencyto measure the incremental impedance (i.e., the derivative of voltage with respect to currentaround one operating point) from the PEC. The incremental impedance has the advantageof being sensitive to the characteristics of the system (constant resistance, constant power,constant voltage, constant current), as well as reflecting the reactive part of the set-up (lineinductance, capacitive input). The applications of the EZD to different elements of themicrogird tackled in this thesis are presented in Fig. 1.1, they are(A) detect the type of load and adjust the controller to improve stability and transientbehavior in real time,(B) islanding detection to switch the controller between modes and achieve smooth contin-uous operation,4(C) measure the distance to a low impedance fault between conductors, to aid in findingthe fault in the system,(D) detect high impedance faults and differentiate them from load increases in point-to-point architectures, and(E) control the PECs to perform MPPT from a photovoltaic (PV) panel, even under un-certain parameters and changing conditions.1.2 Literature ReviewResearch in DC systems, especially those interfacing with renewable energy sources, haveseen a surge of interest in the power electronics community in the past years [8–11]. Manycritical pieces of technology were adapted from AC systems, but many of these solutions arenot suitable for DC systems [12]. Areas of intense work include optimization of resourceintegration, control systems, increased autonomy, and fault detection problems [10, 13]. Inall these problems, work is put towards the integration of the solution into the PEC wheneverpossible, but the possibilities and needs are dependent on the type of DC system.Essential applications of DC systems exist in the form of DCmicrogrids, or, more generally,local area power and energy systems [14]. On the bigger scale, applications can take the formof a regional microgrid integrating photovoltaic plants, wind turbines, battery storage, andloads with or without a connection to the utility AC grid [9]. Stand-alone DC systems existin the form of the power system of a ship [15]. DC systems are also critical in providing highreliability power to telecommunication sites [16–19]. The electrification of transportation willlikely rely on local storage, integrated into a DC system, to provide the peak power to theEV charging station and avoid over-sizing the grid connection [19]. On the smaller end, DCbuildings and homes have been proposed to reduce greenhouse gas emissions [20–22].5This thesis contributes to the implementation of distributed DC systems by proposingan EZD method, built into the PEC, and outlining five critical applications of the proposedtechnology. The following cited work has been performed in the field of power electronics fordistributed generation concerning impedance detection and the target applications for theinsights developed in this work.1.2.1 Impedance DetectionThe incremental impedance of a system is defined as the derivative of voltage with respect tocurrent at one particular operating point (also called the small-signal impedance) [23]; it canyield very crucial information about the behavior of the system. The incremental impedanceof the load, for example, defines the input impedance seen by the source converter at a givenoperating point and affects its stability [23–26]. This parameter is challenging to measurein real-time, using only the hardware already employed in a PEC, but can provide usefulinformation if continuously monitored. Detecting the incremental impedance is especiallychallenging for DC systems, which operate around a stationary operating point, as opposedto AC systems.Incremental impedance detection is, at its core, a system identification problem; as such,many techniques have been introduced that rely on the fundamentals of this field [27]. Therecursive least square method (RLSM) and Kalman filter were used in [28] to determine theincremental impedance of DC systems. Methods based on discrete sequences [29] and thediscrete Fourier transform [30] were also presented. However, most methods either requirelarge amounts of computational power to determine the equivalent impedance or sacrificeprecision. A precise method that is computationally efficient, such that can be implementedin the microcontrollers used to control PECs, would add valuable insight in real time to thesystem.6The Lock-In Amplifier (LIA), sometimes referred to as the phase-sensitive method, is aversatile algorithm or instrument that can accurately detect a signal of a selected frequencyin an environment with high noise [31]. This is achieved by using a combination of modu-lation and demodulation techniques, along with low pass filtering, to extract the magnitudeand phase of the signal of interest. Most commercial applications of the LIA are laboratoryequipment [32]. They rely on dedicated hardware to provide adjustable frequency and am-plitude control, but do so at an extremely high cost ($10,000 USD or more), and are notsuitable to be implemented in every PEC in the system.The LIA has been used in the past to characterize the impedance of transformers [33] andfuel cells [34, 35]. It was used to determine the junction impedance of a diode [36], and thehysteresis loop of magnetic materials [37]. Detection of optical signals was implemented usinga LIA and a 20-bit Analog to Digital Converter (ADC), achieving 103 dB dynamic range [38].An extended analysis of the frequency response was presented in [39] for the analog case,and a broadband version of the algorithm was presented in [40]. A simplified digital versionwas presented in [41], and an oversampled one was presented in [42]. The convergence ofthe method was explored in [43] where an entropy-based method was proposed for opticaltests. These applications can extract some specific characteristics of the system using a LIAbut use laboratory equipment and desktop computers, as opposed to real time processingin microcontrollers for embedded applications. Little work has been presented in real-timeimplementation of LIAs in field-equipment.Although there are algorithms that extract the incremental impedance using powerfulhardware (laboratory equipment and desktop/laptop processors), there is room to use ad-vanced algorithms such as the LIA to detect the impedance in real time using embeddedmicrocontrollers and sensors present in PECs.71.2.2 Control of Power Converters in DC Systems with ActiveLoadsControl of PECs in DC microgrids faces some particular challenges such as maintainingreliable dynamic performance under changing load conditions, ensuring stability of the system[44, 45]. This can be especially challenging in the presence of active loads, which are PECsthemselves, regulating their output voltage. This causes a Constant Power Load (CPL)behavior, leading to stability problems. CPLs present a negative incremental resistance:if the input voltage drops, in order to keep the power delivered to the load constant, theinput current has to increase [46]. The negative incremental resistance plays a crucial rolein determining the stability of the system [47–50], and the stability analysis has seen manycontributions in the past years [14, 51]. Although in real-world applications no CPL hasinfinite bandwidth, this scenario is relevant in order to account for the worst-case scenario.Developing modern control strategies that allow the DC microgrid to deal with active loads,especially under uncertain load conditions, requires continuous measurement of the system.Passive solutions rely on changing the passive components (resistors, capacitors, and in-ductors) strategically to improve the stability of the grid. Rather than proposing novelcontrol strategies, these methods add components to the system. Some solutions proposethe use of RC and RL filters to mitigate the CPL problems [52]. Alternatively, increasingthe bus capacitance can increase the stability margin of the system at the expense of moreexpensive capacitors [46]. These methods, although very simple, have the obvious drawbackof adding cost in the form of additional components.Modifications to the control strategy can be done to the source-end PEC or the load-endPEC. Examples of modifications to the load-end controller focus on changing the bandwidthof the controller such that the load does not present such an aggressive CPL behavior. Thismodification can take the form of an emulated impedance in the DC bus (where the control8loop is designed to behave as a particular impedance to provide the desired benefits), whichcan be implemented for a single PEC [44, 53, 54] or many [55]. Limiting the current rate ofchange in the load-end PEC also has the effect of limiting the response and therefore, theCPL behavior [56]. More complex stabilization strategies can be added to the controller tomake the system stable [57].Alternatively, controllers for the source-end PEC have been presented in the form of tradi-tional and nonlinear solutions. Linear approaches include [47, 50, 58, 59], where the methodis called active damping for its emulation of a damping circuit. Nonlinear approaches includemany techniques [60–64] that allow for robust control by doing away with the small-signalanalysis. Geometric control allows improvement of the regulation speed by not requiringsmall-signal tuning [65]. It has been shown that geometric controllers can contribute to thestability of the microgrid, even if only a small fraction of the PECs are controlled usinggeometric control [66].When tuning the controller of the system, considerations are made of the different loadstates of the PEC, and performance is not uniform for all conditions. Adaptive controllers,based on gain scheduling schemes, have been utilized for many years and provide an advancedsolution that still relies on simple controller architectures (such as the Proportional IntegralDerivative, PID) [67]. These controllers offer the advantage of linear control, its very well-known operation, with the ability to improve the performance for different changes in thesystem. Instead of tuning the system to a single state, gain scheduling has a set of controllergains that depends on the state of the system (e.g. the type and size of the load). The useof the EZD method leaves room to perform a smart tuning of the controller as a function ofthe incremental load.91.2.3 Islanding Detection and Autonomous Operation of DCMicrogridsMicrogrid voltage regulation can be structured in two main ways: either the voltage is regu-lated cooperatively by all the PECs in the system, or only some PECs (known as grid-formingconverters) regulate the voltage while the others follow them. Islanding detection (ID), thatis the process of detecting when the grid-forming PEC has been disconnected, is a fundamen-tal feature of any PEC built to work in a DC microgrid and remains an open challenge [68].A functioning ID method (IDM) allows the system to disconnect as soon as the islandingevent happens or switch over to a controller designed for this operating mode. By using theappropriate controller for islanded and grid-tie mode, the DC system can be made to operatesafely (by ensuring the bus voltage is regulated at all times) and efficiently (ensuring thedistributed sources operate following the local optimization rules).When the microgrid is connected to a grid-forming PEC, connected PECs follow localrules to optimize their performance (such as maximum power point tracking or battery charg-ing) [69–71]. In the event that a grid forming PEC is not available, the PECs in the DCsystem follow alternative rules designed to maintain service to the loads. In a master-slaveapproach, if the grid forming PEC is not available, the duty to regulate the voltage is usu-ally delegated to the energy storage device or a diesel generator. This allows the rest ofthe devices to continue to operate in MPPT mode, increasing the efficiency of the energyharvesting. Alternatively, PECs might implement a collaborative regulation of the voltagethrough the use of a droop controller [72–77]. For some applications, such as [75], the droopcontrol can be integrated into the Energy Management System (EMS) to regulate the storagein supercapacitors and other fast storage.Research in IDMs has seen many contributions in the past years, especially for AC sys-tems [78–81]; however, the same techniques cannot be extended to DC systems. In DC10systems, the only variable magnitude that can be affected during the islanding event is thevoltage; therefore, methods that rely on the frequency, such as the Rate of Change of Fre-quency (ROCOF) [82–85], and those based on phase variation [86] cannot be applied to DCsystems.The passive IDMs rely on measuring signals such as the voltage and current, withoutinjecting any disturbance, and inferring the islanding state from there. The parameters ofthe microgrid are monitored and if a parameter goes outside some prescribed magnitude(such as the grid voltage going outside of the under/over voltage area) the IDM signals thedetection of the islanding event. The passive techniques can be swift and accurate whenthere is a significant power mismatch in the system between what is being generated and theload [87, 88]. However, they have limitations when the mismatch between generation andload is zero or close to zero. The range of operating points where the IDM is not triggered iscalled its Non-Detection Zone (NDZ). Examples of passive methods include the under/overvoltage (UV/OV) [89], and the autocorrelation function of model current envelope [90]. Acomprehensive review of these methods was recently presented in [68].Active islanding methods, on the other hand, rely on injecting some form of disturbancein the system and inferring, from the transient, the state of the grid. An active method thatcombines a perturbation with the MPPT algorithm is presented in [91]. This method intro-duces a perturbation that starts on the order of 10% of the load current and increases in size,generating a significant disturbance that pushes a passive OV/UV scheme to trip. The NDZof this method can be tuned by selecting different perturbation sizes and frequencies. Thepositive feedback method relies on injecting a disturbance and increasing it proportionallyto the size of the voltage deviation; this method has a very small NDZ, but influences thestability of the system [92, 93].11Some methods rely on a communication to be established between the distributed gener-ators and grid forming device [94–96]. These methods offer almost zero NDZ but are costlyand sensitive to damage or attacks in the communications system.Once the islanding is observed, several actions can be taken. In many applications, itis required that the PECs disconnect from the grid once the islanding event is detected,usually within a small time frame (100-300 ms) [97]. Other applications require the systemto continue providing service even during the islanding event, in order to ensure service isprovided to the load [72, 73, 98]. It is essential that the controllers are designed to smoothlyswitch over to different controller modes, which can be achieved using advanced techniquesor simple PI techniques [67]. Although many techniques can detect the islanding event, notmany IDMs are able to also detect when the system has been reconnected to the grid. Theproposed ID can be combined with different controllers for island and non-islanded mode toensure the system continues to provide regulated power to the loads in a decentralized way(without communications).1.2.4 Fault Location in DC SystemsA Low Impedance Fault (LIF) between two conductors is the unintended circulation of ahigh amount of current between the conductors, usually a short circuit. Besides detectingthe fault, it is essential to locate where in the system the fault happens in order to isolatethat part and repair faster [13].LIFs in AC systems can be cleared relatively easily due to the natural zero-crossing eventsproduced by the alternating voltage/current; this is not the case in DC systems [13]. Thelack of zero-crossing in DC systems has led to much interest in DC protective devices andstrategies, capable of breaking a non-zero current [99–102]. Topologies that are connected tothe AC grid can rely on fast Circuit Breakers (CBs) on the AC side to extinguish the currentand slow switches in the DC side to segment the system [103]. An alternative method to seg-12ment a grid relying on a topology that can limit current on its own is proposed in [104] usingthe power router, a form of the triple active bridge (TAB) [105]. These novel approaches tobreak the current and change the path of the current have led to the possibility of imple-menting architectures with multiple paths that offer higher reliability through redundancy[106, 107]. These have controllable switches that allow for a reconfiguration of the systemin the event of a fault to maintain power to the loads in the unaffected part of the system.This reconfigurability increases the availability of the system [107, 108]. Radial architecturesprovide the least redundancy to the system: a fault in any of the lines cuts power to that partof the system. Ring architectures provide an alternative path to the current, allowing for onefault point before power needs to be cut to the load [109, 110]. Interconnected architecturesprovide an additional level of redundancy [111]. Adding the different paths for the currentalso adds challenges to identify the faulted line [103] and the location of the fault in thatsegment in order to repair the fault promptly.Several methods to locate a fault in a DC system have been proposed in the past. Themethod proposed in [112] uses an external Power Probe Unit (PPU) to inject a signal inthe system and locates the fault by means of the oscillation frequency and damping. Otherexamples of methods that rely on external hardware include [113] for marine vehicles and[109] for renewable energy systems. Using external hardware such as PPUs is expensive andrequires the repair crew to move the external equipment around. Measuring the transientand using its parameters to estimate the distance to the fault has been proposed in [114, 115];this has the disadvantage of requiring a very high sampling rate and accuracy to detect thelocation. A handshake method that can be applied to multiterminal DC systems is presentedin [103], which makes use of slow DC switches to interrupt segments of the system to performthe detection, but relies on communications between the converters to be established. Oncethe LIF is located, the system should be reconfigured, when possible, to restore power to13the loads. Building the fault location features into the PEC facilitates a cost reduction andautomate repairs in the system.1.2.5 High-Impedance Fault Detection in DC SystemsHigh Impedance Faults (HIFs) can be produced for several reasons [116–119]: aging anddamage in the isolation of the wires can create current leakage between the conductors; lowconductivity materials (such as tree branches) can come in contact with the conductors;arcs can be established and maintained for long periods of time; or even people or animalstouching the conductors can create a high impedance path for the current. These faults aredangerous, as they can accelerate the damage on the isolation leading to short circuit faults,can cause the fault path to heat leading to a fire, or can cause the person or animal to sufferelectric shock or burn [120]. Due to the dangers posed by HIFs, it is crucial to detect themand activate the protections swiftly.The Detection of a HIF is challenging, as the fault current is not likely to trip the OverCurrent Protection (OCP), being more likely to be confused with a load step-up [10, 116].However, extensive analysis of the transients and spectrum has yielded methods that enablethe detection of a fault.The Detection of HIFs in AC power systems has seen many contributions over the pastyears. An extensive characterization of different types of HIFs and their effect on the ACgrid was carried out in [121]. An algorithm that integrates time and harmonic analysis withprobabilities was discussed in [117]. The method in [122] incorporates information from thecurrent magnitude, the third and fifth harmonic, and the phase of the current harmonicswith respect to the voltage to detect HIFs. A method based on the wavelet transform is usedin [123] to detect a fault. A decision tree method, based on Fast Fourier Transform (FFT)training on the substation feeder current was introduced in [124]. All these methods useinformation about the frequency and phase, which are not readily available in DC systems.14The detection of HIF in DC systems remains one of the main challenges today [10]. Thestudy in [125] mentioned the implementation of HIF protection for pole-to-ground faults,based on commercial devices, but does not mention pole-to-pole faults; even then, the de-tection of pole-to-ground HIFs is challenging [126]. Contributions have been made in HighVoltage DC (HVDC) systems that rely on the harmonics injected by the AC side and rec-tification circuit [127]; but these methods are not suitable for systems with DC inputs orsignificant storage elements. The traveling wave methods are highly effective, but they re-quire dedicated hardware and have high signal processing requirements that can make themprohibitive to some applications, in particular small systems [128]. A Fourier-based analysisis presented in [129] for a point-to-point architecture, typical in many applications; this aswell relies heavily on processing power to detect the fault. The use of a DC reactor to detectthe fault in HVDC is proposed in [130, 131]; this can be effective in HVDC but also requiresdedicated external equipment. Building the HIF detection into each power converter allowssafer operation (by allowing the system to detect the fault and disconnect the power) andsimpler system implementation (by removing the need for external, dedicated hardware).1.2.6 Maximum Power Point Tracking for Photovoltaic PanelsPeak energy harvesting for PV panels has become a fundamental requirement to achievehigh overall conversion efficiency (converting as much irradiance into electricity injected inthe system), given the non-linear voltage/current characteristics of the panel [132, 133]. TheMPPT algorithm is entrusted with ensuring the PV panel operates at the Maximum PowerPoint (MPP). Many contributions have been implemented in the past years to maximizethe energy harvested from PV panels [134], but some issues remain open. A wide variety ofMPPT algorithms are available [135, 136] ranging from simple and inaccurate algorithms suchas the Constant Voltage (CV), Fractional Open Circuit Voltage (FOCV), or Fractional ShortCircuit Current (FSCI); the popular hill-climbing algorithms such as Perturb and Observe15(P&O) and Incremental Conductance (InCond) [137]; and the sophisticated algorithms basedon heuristics such as Particle Swarm Optimization (PSO) [138–140] and Fuzzy Logic [141–143].The popularity of the Hill-Climbing techniques (InCond and P& O) derives from theirsimplicity, needing a few sensors and tuning parameters. They work by injecting a change inthe operating point of the converter (perturbation) and checking for a condition to determinea better operating point. However, several issues remain unsolved. Both the InCond and theP&O algorithm suffer from a characteristic oscillation in steady-state that results in a reduc-tion in efficiency [144, 145]. The step-size of the algorithm and the sampling-time are mixedto produce a trade-off between accuracy and speed [146–148] that leaves the fast algorithmswith large oscillations and the accurate algorithms with slow tracking speed; this has lead tooptimization criteria [149–151] and adaptive versions of the algorithm [152–154]. Among theadaptive versions of the algorithm, new approaches have been presented using Dual KalmanFilters on FPGA devices [155, 156], this technique is used to identify parameters from thesystem and adapt the MPPT algorithm for optimization. Another common problem of theInCond and P&O is the tracking of changing environmental conditions, namely the Irradiance(Irr) and the Temperature (T ). The nature of the algorithm leads to confusion during chang-ing conditions and inefficient tracking even when going in the correct direction [157, 158].Moreover, if the environmental conditions (in particular the irradiance) are not uniform,the PV presents local maxima, which leads to confusions in the MPPT process. Solutionshave been presented for some of the issues such as environmental changes [159] and localmaxima problems [160–169], the advance of distributed inverters (string, micro, and moduleintegrated) have helped mitigate this problem. Classical approaches, such as the InCond andP& O, exhibit a significant limitation in that the algorithm can make the incorrect decisionunder specific environmental changes. This error arises when the switching ripple and lowfrequency perturbation interact. Solutions have been proposed to minimize this interaction16while keeping the standard algorithms [170]. Opportunities to introduce further improve-ments in steady-state operation and transient dynamic tracking remain open. It has beenshown in [171, 172] that the switching ripple can be used as a non-intrusive method to per-form optimization. The elimination of perturbation and the use of the switching ripple havethe potential to increase MPPT performance, but switching ripple is hard to detect due toits amplitude and the noise.Different control architectures can influence the speed and accuracy of the MPPT algo-rithm. Multi-loop controllers use the output of the MPPT as a reference voltage/current forthe controller, sacrificing speed for tighter control of the voltage [173]. Single-loop architec-tures achieve faster transients [174–176] but the control objective is directly aimed at theMPP, ignoring other restrictions (such as current limits). Some methods, based on slidingmode control, allow fast MPPT convergence, while keeping controllers in place [146, 177–180].Although much progress has been made in uniformly irradiated PV panels, opportunities forsmooth, fast, and simple algorithms remain open.1.3 Contributions of the WorkThe objective of this work is to investigate novel control and monitoring techniques thatallow for a more efficient and more autonomous DC power system, based on distributedresources. This is achieved through the development of an impedance analysis instrumentand its modification and tuning for specific applications. The main contributions of this workare:1. An Embedded Impedance Detection (EZD) method is introduced. The proposed EZDmethod can detect the incremental behavior of a system around an operating pointat a given frequency. It allows the measurement of the resistive and reactive parts ofthe impedance both in magnitude and phase, using reference signal (of lower magni-17tude than other methods) injected in the system. The proposed EZD method can beimplemented in an industry-standard microcontroller (TI C2000), with no additionalsensors.2. A gain scheduling technique to improve the stability and transient behavior of DCmicrogrids with active loads is proposed. The EZD is used to determine the incrementalbehavior of the load and update the controller’s gain, which extends the stability ofthe system. The performance of the proposed system is compared with a controllertuned for a specific case, which fails under extended active load transients, and againsta controller tuned for the worst-case active load, which exhibits undesired performanceunder other loading conditions. The proposed controller extends the stability to afull active load scenario and reduces overshoots from 15% to 2.5%, without sacrificingspeed.3. A new active IDM for DC microgrids based on the EZD, is presented. The method usesthe EZD to detect the incremental load, which is a clear indication of the islanding/non-islanding scenario, even in the most challenging conditions. The proposed method hasa minimal non-detection zone, uses a minimal reference signal and converges faster(compared with other active methods), and can detect islanding and non-islandingconditions. This allows the PEC to switch to a grid forming controller and then switchback to a grid follower controller, increasing the autonomy of the system.4. A Low Impedance Fault (LIF) location technique for DC systems is presented. Usingthe EZD method, it is possible to detect how far away from the PEC the LIF is located.This measurement is affected by the fault resistance, which introduces error. The EZDallows the LIF location method to use not only the resistive part but also the reactivepart of the impedance, to increase the accuracy. The proposed method allows thePEC to be used as a detection unit reducing the time needed to perform the repairs.18Moreover, it allows to restore energy to the healthy part of the system after the incident,without the use of dedicated pieces of equipment (such as PPUs).5. A High Impedance Fault (HIF) detection method based on the EZD is introduced,which exhibits the ability to distinguish a fault condition from a load increase in pointof load-end PECs. The HIFs are challenging to detect, as they might not trip the over-current protection and be confused with load increases. The proposed method benefitsfrom the negative incremental resistance of constant power loads to distinguish a HIFfrom a load increase. The nature of the difference is such that the HIF and load increasepush the incremental resistance in different directions, making it a clear distinctionbetween the two cases.6. A novel Maximum Power Point Tracking (MPPT) algorithm that can follow irradiancechanges, operate with no oscillations, adapt the step size to track the irradiance changes,and does so with a single control loop is presented. The control loop is based onimpedance sensing using the proposed EZD method, aiming to match the DC andincremental behavior. The proposed method achieves 40 times speed improvementover the traditional incremental conductance method, as well as no oscillation andtracking of transients within 98% of the true MPP.In the area of DC systems, this work makes significant contributions to building newcapabilities and autonomy without adding additional hardware or special microcontrollers.The proposed technique allows for increased energy extraction efficiency and its distribution.It replaces external components, such as power probe units used to locate faults, by internalalgorithms. It gives the DC system new capabilities, such as the possibility to self-tune andthe ability to switch between grid-follower and grid-forming modes with no extra cost. It im-proves safety by detecting problems and preventing fires. Ultimately, the contributions of this19work push the development of autonomous DC systems forward, allowing more autonomousand dependable systems to be built.1.4 Dissertation OutlineThe rest of the work is organized as follows:Chapter 2 introduces the core EZD method, outlining its analysis and implementation.The work builds on the LIA algorithm and explores the details, modifications, and trade-offsneeded to implement it in a real-time system of constrained resources, such as the microcon-troller in a PEC.Chapter 3 presents the use of the proposed EZD method to improve the transient stabilityof a DC microgrid through an adaptive controller. The dynamic response of the system as afunction of the load is analyzed. The controller uses a PI structure and updates it followingthe detected incremental load, achieving improved performance and stability.Chapter 4 introduces an EZD based IDM and islanding operation. The behavior of thesystem when the grid is connected and when it is not is analyzed. It is shown that theincremental behavior of the load, measured from the source converter, is a clear ID signal.The proposed EZD-based IDM is compared with a standard Under-Voltage/Over-Voltage inthe most challenging scenarios.Chapter 5 outlines the location of Low-Impedance Faults (LIFs) between conductors in aDC system using the proposed EZD method. The location error is analyzed as a function ofthe control variables and the unknowns. The use of the EZD method allows for fault locationand repair cost reduction.Chapter 6 outlines the use of the EZD method to detect High-Impedance Faults (HIF)and differentiate them from load increases. The HIFs can be caused by arcs and conductorstouching low conductivity materials; if they are not interrupted, they can lead to fires and20equipment damage. The behavior of the PEC under the HIF and under a load increase isanalyzed for challenging scenarios.Chapter 7 presents the implementation of a modified EZD algorithm to perform MaximumPower Point Tracking (MPPT) in a uniformly irradiated PV panel. The proposed methodbuilds on the incremental conductance (InCond) algorithm and pushes the EZD method tothe extreme: using only the switching ripple as the reference signal.For all the applications, simulations and experimental results are presented to validate theproposed technique. A comparison with other methods is presented to validate the benefitsof the technique.Chapter 8 contains the relevant conclusions, contributions, and planned areas of futurework derived from this thesis. The findings of this work contributed significantly to theimplementation of DC systems; the value of this work is demonstrated by the seven relevantpublications in international conferences and Transactions journals from the Institute ofElectrical and Electronics Engineers (IEEE).21Chapter 2Incremental Impedance Measurementin Power Electronics ConvertersReactive components connected to the Power Electronics Converter (PEC) and non-linearities in the sources and loads affect the dynamic behavior of the system. Their variationcan be an indicator of problems and changes in the condition of the system. The extent ofthese characteristics cannot be inferred from simple measurements of the quiescent point ofthe PECs in a DC system, as it depends on changes around it. Figure 2.1(a) shows the V-Icurve of a load that includes reactive components (L and C) operating in DC. The straightline represents the resistive component of the impedance, while the ellipse shows the reactivebehavior [181]: the amplitude is related to the magnitude, the phase shift of the major axisPortions of this chapter have been published in• F. Paz and M. Ordonez, “Fast and Efficient Solar Incremental Conductance MPPT Using Lock-In Amplifier,” in Proc.6th IEEE Int. Symp. Power Electronics for Distributed Generation Systems (PEDG), Jun. 2015, pp. 1–6.• F. Paz and M. Ordonez, “High-Performance Solar MPPT Using Switching Ripple Identification Based on a Lock-InAmplifier,” IEEE Transactions on Industrial Electronics, vol. 63, no. 6, pp. 3595–3604, Jun. 2016.• F. Paz and M. Ordonez, “An Embedded Impedance Measurement for DC Microgrids Based on a Lock-In Amplifier,” inProc. 7th IEEE Int. Symp. Power Electronics for Distributed Generation Systems (PEDG), Jun. 2016, pp. 1–6.• F. Paz and M. Ordonez, “High-Accuracy Impedance Detection to Improve Transient Stability in Microgrids,” IEEETransactions on Industrial Electronics, vol. 64, no. 10, pp. 8167–8176, Oct. 2017.• F. Paz and M. Ordonez, “An Impedance-Based Islanding Detection Method for DC Grids,” in Proc. 9th IEEE Int.Symp. Power Electronics for Distributed Generation Systems (PEDG), Jun. 2018, pp. 1–7.• F. Paz and M. Ordonez, “Embedded Fault Location in DC Microgrid Systems Based on a Lock-In Amplifier,” in Proc.8th IEEE Int. Symp. Power Electronics for Distributed Generation Systems (PEDG), Apr. 2017, pp. 1–6.• F. Paz and M. Ordonez, “High-Impedance Fault Detection Method for DC Microgrids,” accepted to 10th IEEE Int.Symp. Power Electronics for Distributed Generation Systems (PEDG).22(a) (b)vi0<)1,i1v(∣∣∣∣idvd=1r0<)2,i2v(∣∣∣∣idvd=2r1I2I2V1Vvi1I2I2V1V1I1V=1R2I2V=2RFigure 2.1: Voltage vs. current (V − I) curves of devices around a DC operation point andtheir incremental behavior: in (a) a resistive load with reactive component is shown, the DCresistance (Ri = Vi/Ii) do not reflect the reactive part, but the incremental behavior shows it;in (b) the characteristics of a non-linear load where Ri is not distinguishable from a resistor,but the incremental resistance (dv/di) is negative.to the phase shift, and the direction of rotation to capacitive (clockwise rotation) or induc-tive (counter clockwise) behavior. From the quiescent point (the DC voltage and current),only the resistive part can be calculated. Figure 2.1(b) shows the behavior of a non-linearload: from the DC operating point, it cannot be differentiated from a resistive load, but theincremental behavior shows its negative resistance.An advanced algorithm to extract the incremental behavior of the voltage and current,named Embedded Impedance Detection (EZD), is introduced in this chapter. This methodallows the extraction of reactive and non-linear behavior around the DC operating point. Theproposed EZD method uses sensors typically found in a PEC (current and voltage) and theembedded microcontroller, along with digital algorithms, such as the Moving Average Filter(MAF) and the Lock-In Amplifier (LIA), to extract the incremental impedance seen fromthe terminals of the PECs. The high sensitivity and selectivity of the proposed techniqueallow for a minimal reference signal (r[k]) to be used to extract the incremental impedance.Even with the outlined benefits, the implementation of the EZD can be carried out in anindustry-standard microcontroller; this adds all the benefits of the EZD without adding cost.23gSmicrocontrollerLIA IC APPsupervisor system]k[, i]k[v ]k[rzdprotectionsTZADC averaging control PWMEZD)t(v)t(iFigure 2.2: Block diagram of the DSP based control and supervision system for power elec-tronics converter (PEC); the diagram includes the trip-zone (TZ) hardware protections andthe sampling process (ADC+averaging) and control and modulation blocks; it includes theproposed Embedded Impedance Detection (EZD) method and the particular applicationblock (APP) for the detected impedance; this chapter focuses on the blue highlighted blocksthat generate the reference (r[k]) to be injected through the controller, the Lock-In Amplifier(LIA) to extract the effect of r[k] on v[k] and i[k], and the Impedance Calculation (IC) tocombine these effects and compute the incremental impedance (z), the following chaptersfocus on the application blocks and modifications.A general block diagram of the embedded system implemented for this work is presentedin Fig. 2.2, outlining the different tasks and execution priorities, as well as signals needed forthis analysis. This microcontroller is tasked with generating the gate signals to the PEC (Sg)based on the control decision derived from the measurements of the voltage and current (v,i) from the PEC. The uppermost layer includes the highest priority (most time-critical) tasksof the PECs controller: sampling using the Analog to Digital Converter (ADC) to convertthe analog signals v(t) and i(t) to the sampled domain (v[k] and i[k]), averaging, controlto regulate the converter through the duty cycle (d), Pulse Width Modulation (PWM) toconvert d to the gate signals Sg, and the protection blocks (trip-zone, TZ); these need to beexecuted in real-time otherwise risk damaging the PEC. The middle layer includes the bulkof the proposed technique: the LIA, the impedance calculation, and each application. The24individual application informs the supervisor system and communications. The rest of thischapter focuses on the analysis of the blocks highlighted in blue: the LIA and the ImpedanceCalculation (IC); the ensuing chapters are devoted to the block highlighted in orange, theparticular applications and the modifications to the general scheme to fit them. This chapterfirst focuses on the generation and injection of r[k] through the controller, then on extractingthe effect of the reference in the voltage and current (v[k] and i[k]), and then on using thisinformation to calculate the measured impedance (z). A simulation example including aPEC, a resistive load with inductance, and a Constant Power Load (CPL) is presented tointegrate the concepts discussed.2.1 Reference Generation and InjectionIn order to measure the impedance seen by the PEC at one of its ports, a reference signal(r[k]) of an arbitrary frequency (fr) is internally generated and injected into the controlsystem as shown in Fig. 2.2. For this work, r[k] is given byr[k] = Ar sin (2pi fr Ts k) , (2.1)where Ar is the amplitude of the reference, Ts is the sampling period, and k is the sampleindex. Ultimately, the reference is digitally generated by the same microcontroller thatcomputes the control loops and generates a sinusoidal variation of the PWM duty-cycle;however, depending on fr, it must be injected at different stages of the control computation toensure the reference passes through the regulation stages. The EZD extracts the incrementalimpedance at the selected fr.The control system of most PECs is tasked with regulating some voltages and currentsof the PEC. It usually has more than one nested control loop to improve the performance,25rv ri rd++ ++ +- -PWM∗i∗vv igS)z(vC )z(iCve ie D d+swf0 dBcurrentloopvoltagelooprvf rif rdff|H|10swf≈BWCL10BWCL≈BWV L swK f=s′f(a)(b)Figure 2.3: Most power electronics converters (PECs) have nested control loops; in (a) theblock diagram of a control system with a current loop (CL) nested inside a voltage loop (V L)with the possibility to add references at each stage; in (b) simple bode diagram showing therelative bandwidths of the control loops and the frequency of the different reference injected.add protection (current limiting), or add special features (maximum power point tracking,current sharing through droop control, etc.). Figure 2.3(a) shows a typical control systemwith two nested loops: the voltage loop (V L) takes the voltage set-point (v∗) and comparesit to the measured voltage (v), and the difference (ev) is fed to the voltage controller (Cv)that produces the set-point for the current loop (CL); the CL takes this set-point (i∗) andcalculates the difference with the measured current (i) and feeds this error (ei) to the currentcontroller (Ci) that produces the duty-cycle (D) for the Pulse Width Modulation (PWM)generator. More control loops can be added on top of these to provide additional features(such as maximum power point tracking or current sharing using droop control).Each nested controller (such as current or voltage) is designed to be compatible with theothers in the loops, as it is represented in Fig. 2.3(b). As a general rule, the innermost loop26(CL in this case) is designed to have a bandwidth (BW ) ten times smaller than the switchingfrequency (fsw):CLBW ≈ fsw10. (2.2)In this way, the converter follow the description provided by the small signal approximationaround the operating point. The BW of the V L (V LBW ) is selected ten times smaller thatCLBW :V LBW ≈ CLBW10. (2.3)This ensures the CL follows the reference as if it were an ideal source. Depending on whichband fr resides in, r[k] needs to be generated differently.Figure 2.3 shows the different types of r[k] (vr, ir, dr). For r[k] that fall inside thebandwidth of the voltage control loop, r[k] is generated as a voltage reference (vr) with afrequency fvr and injected along with v∗. For medium speed (those faster than the bandwidthof the voltage loop and slower than the bandwidth of the current loop), r[k] is generated as acurrent reference (ir) with a frequency fir and injected along with i∗. Finally, a very fast r[k](faster than the current control loop) is generated as a direct perturbation of the duty-cycledr and added to the output of the CL (D) with a frequency fdr . It is not possible to use frhigher than fsw, as the PWM only generates one control action per cycle.Computing trigonometric functions, such as r[k] in real time is resource-intensive, espe-cially if the microcontroller does not have a dedicated accelerator (such as the TrigonometricMath Unit, TMU, in some Texas Instruments microcontrollers), but the specific applicationin this work offers characteristics that can be exploited to make an efficient implementation.Since r[k] is synchronized with the PWM and the control loop, there are a fixed number ofsamples (N) in the sequence r, given byN = (fr Ts)−1 . (2.4)27Then, the finite sequencer[i] ={Ar sin(2piNi)}, 0 ≤ i < N (2.5)is related to the running sequence r[k] byr[k] = r[kmodN ]. (2.6)where the notation ”kmodN” means the remainder of the integer division of k by N (e.g.7mod 6 = 1). For example, with Ts = 100µs and fr = 2.5 kHz, N is given by (2.4):N = ((2.5 kHz) (100µs))−1 = 4, (2.7)and the finite sequence isr[i] ={Ar sin (0) , Ar sin(pi2), Ar sin (pi) , Ar sin(3pi2)}. (2.8)A representation of this reference generation method for an r[k] that is injected into dis shown in Fig. 2.4. The values of r[i] are precalculated and stored in a register that isscanned using an index (i) that wraps back to 0 after N steps. This is known as a “circularbuffer”. After picking the correct value from r[i], it is added to D which is updated in thenext switching period.This proposed method to obtain r[k] from a finite list reduces the reference generationto a simple read from a circular buffer of size N . If memory is constrained, the symmetryproperty of the r[k] can reduce the memory footprint to N/4 with some additional operations.Another advantage of this method is its independence of time.28[0]r[1]r]i[rrttswTD D D]i[r+D0>]i[rD+ 1] = 0i[r0<+ 2]i[r...i1]−N[r)iNpi2sinrA] =i[rswN T=r/f= 1rTgSFigure 2.4: Diagram of the generation of the reference signal (r[k]) from a circular buffer(r[i]); r[k] is generated as an N -point look-up table and the output is updated every samplingperiod (Tsw) resulting in a period Tr = NTsw; the sequence is then added to the duty cycle(D) the controls the PWM modulator, which is updated every Tsw.2.2 Signal ExtractionAfter r[k] is injected in the system and it propagates to the voltage and current, its effectmust be extracted using digital signal processing. The input to the signal extraction stage(x(t)) can be divided inx(t) = xs(t) + xr(t), (2.9)where xs is the part of x that comes from the behavior of the system without r[k] (such asclosed loop response and switching ripple), and xr is the effect of the reference in the system,reflected in the signal x (voltage or current response). That is, xr is the part of the signalthat needs to be analyzed with the signal extraction process and xr represents interference.The interference can be in the form of noise, switching event, or DC behavior of the signal.29MAFADC RTLPFS LIAcontrol loop]k[x]′k[x)t(x )t(blx ]′k[adcx 1, θ1Aanalog signalhybrid sTsampled at/KsT=s′Tsampled atFigure 2.5: Signal-processing chain from a sensor (S), through an amplifier/low pass filter(LPF), an over-sampled Analog to Digital Converter (ADC), a Moving Average Filter (MAF)to remove the switching effects, a rate transition (RT) to adjust to the control loop samplingperiod, and finally feeding the Lock-In Amplifier (LIA) for signal extraction and the controlloop for regulation; the different colors indicate the time domain of the signals.The signal xr is then given byxr(t) =∞∑n=1An sin (2pi n fr t+ θn) . (2.10)Where An and thetan are the amplitude and phase of the Fourier decomposition of xr. Theharmonics are considered from n = 1 to infinity for generality.To calculate the incremental impedance at fr, only the amplitude of the first component(A1) and its phase-shift (θ1) need to be extracted. The proposed digital LIA offers highdynamic range to extract this small oscillation from the large DC value (up to references of0.1% of the DC value) using the same sensors included for the control loop.The signal-processing chain for each of the signals in the system is shown in Fig. 2.5 fromthe magnitude transducer to separating A1 and θ1. The blocks up until x[k] are mandatory inorder to implement the control loop, so they do not add computation overhead. The blocksindicated with a dashed trace are rate transitions (RT), either from the continuous domain(t) to a sampled one (using the ADC), or between two different sampling rates (T ′s to Ts).The oversampling of signals is implemented when it is necessary to average the switchingripple from the voltage and current and make the control decision based on the average.30The magnitude to be measured (v, i) is transformed by a sensor (S in the diagram) thatproduces a voltage output proportional to the magnitude. This sensor could be a simpleshunt resistor, a hall effect sensor, or voltage divider. The signal x is then amplified tofit the requirements of the ADC and filtered using a Low Pass Filter (LPF) to remove thehigh-frequency components of x that would cause aliasing. After the LPF, the band-limitedversion of x, xbl, isxbl(t) = xs,bl(t) +Nmax∑n=1An sin (2pi n fr t+ θn) , (2.11)where Nmax is the maximum harmonic of fr that is let through by the LPF.In the following sections, the main building blocks of the signal chain are discussed indetail. The Moving Average Filter (MAF) serves as a building block of the digital Lock-InAmplifier (LIA) and to remove the effects of the switching ripple. The digital LIA allows theextraction of A1 and θ1 from signals with large offset and noise.2.2.1 Moving Average FilterThe MAF is a simple digital filter that has low pass characteristics, plus the ability tocompletely remove some specific frequencies. For a given input signal (x[k]), the output ofthe MAF (x¯[k]) is given byx¯[k] =1MM−1∑i=0x[k − i], (2.12)where M is the order of the filter (number of samples in the average). Since the output canbe expressed as a finite sum of the input delayed, the MAF is a Finite Impulse Response(FIR) filter, which offers advantages such as guaranteed Bounded-Input Bounded-Output(BIBO) stability and linear phase.31(a)(b)]k[x]k[x¯1]−k[x 2]−k[x 1)]−M(−k[x1−z 1−z 1−z/M1Moving Average Filter]k[x/M1++-1−zM−z]k[x¯]M−k[x1]−k[x¯Moving Average Filter (Recursive)Figure 2.6: Block diagram of the Moving Average Filter (MAF) using (a) a non-recursiveimplementation vs. (b) a recursive implementation.Computation of the MAFA block diagram of the MAF is presented in Fig. 2.6(a), where it can be seen that for a MAFof order M , this implementation needs a buffer of size M , and needs to compute M sumsand one product. This is an expansion of the block labeled MAF in Fig. 2.5. This is feasiblefor small Ms, but would be too slow to implement in real time for larger Ms.A more computationally efficient way to implement the MAF would be looking at thechange in x¯ between two steps. From (2.12) the previous iteration of the filter (x¯[k − 1]) isx¯[k − 1] = 1MM−1∑i=0x[k − 1− i]. (2.13)Then the change between the steps isx¯[k]− x¯[k − 1] = 1MM−1∑i=0x[k − i]− 1MM−1∑i=0x[k − 1− i]. (2.14)32Removing all the terms that cancel out from the right hand side of (2.14), the increment isx¯[k]− x¯[k − 1] = x[k]− x[k −M ]M, (2.15)and the running output of the filter isx¯[k] = x¯[k − 1] + x[k]− x[k −M ]M. (2.16)This is known as recursive implementation, and offers the advantage of requiring two sumsand one product for any size M . The block diagram of this implementation is shown inFig. 2.6(b). It is important to note that neither the memory footprint of the filter nor itsFIR nature change.Inspection of (2.16) shows that, although the number of operations to calculate x¯[k] isindependent of M , it is still necessary to shift the data through the entire delay chain, whichhas O(M) operations; this might be too much for a real-time implementation. The shiftingis solved using the same kind of circular register used to generate r[k]. This implementationcomputation time is independent of M .MAF Output and Frequency ResponseM needs to be selected such that it removes some specific frequencies. This is reflected in itsDiscrete Time Fourier Transform (DTFT ) given byH(ej2pi Ts f)=1M1− e−j2pi Ts fM1− e−j2pi Ts f . (2.17)where f is the frequency parameter and Ts is the sampling time. The filter has a magnitudeof ∣∣H (ej2pi Ts f)∣∣ = 1M√1− cos(2piTs fM)1− cos(2piTs f) , 0 ≤ f ≤12Ts(2.18)33]k[y]k[u= 8M= 16M= 4M1= 8M= 16M= 4M(a) (b)skTfrf∣∣)fspiT2jeH∣∣sT2/1sT4sT8sT16Figure 2.7: Characteristics of the Moving Average Filter (MAF); in (a) the magnitude ofthe frequency response shows the unitary gain at 0, the notches at f = n/TsM , and thegenerally lower gain of the filter for higher M ; in (b) the step response of the same MAFshows the added delay of the filter when M increases.which is shown in Fig. 2.7(a) for different values ofM . The following features can be observedfrom the plot:• |H(ej2pi Ts f )| = 1, for f = 0,• |H(ej2pi Ts f )| = 0, for f = n/TsM , with n = 1, 2, ..,M/2,• a peak in between each notch, that is attenuated for larger M .Therefore, to remove a signal with frequency fr, M should be chosen such thatM =nTsfr. (2.19)There are many values of M that completely remove the signal at fr. Picking a differentn places fr at the n-th notch of H(ej2pi Ts f ). The minimum M that can notch fr (for a givenTs) is found when n is one:Mmin =1Tsfr. (2.20)34Placing fr in the n-th notch requires to average n periods of the signal at fr. By selecting thenumber of periods (Np), it is possible to increase the frequency resolution and the attenuationof the filer, but the response becomes more delayed and the memory footprint expands (thetime window expands). The final size of the filter is given byM = Np ×Mmin. (2.21)The step response of the MAF with different sizes is shown in Fig. 2.7(b). The outputdelay is directly proportional to M . Therefore, a trade-off needs to be found between theattenuation required, the number of notches, the delay, and the memory footprint. Thisbalance is application-specific.2.2.2 Digital Lock-In AmplifierThe Lock-In Amplifier (LIA) is an algorithm that uses the injected r[k] and extracts theresponse of the system at the selected fr. Many instruments can extract the response of thesystem, but they are generally expensive dedicated pieces of equipment (such as a networkanalyzer or frequency response analyzer). In this work, an embedded digital version of theLIA is proposed, which allows accurate extraction of the effect of r[k] on v and i, whichcan be used for impedance measurement. This implementation uses the sensors commonlypresent in the PEC.LIA AnalysisA block diagram of the digital LIA is shown in Fig. 2.8(a), this is an expansion of the blocklabeled LIA in Fig. 2.5. The input signal x, given by (2.11) is multiplied by a sine and cosine35)ksTrpi fsin (2)ksTrpi fcos (2MAF 2MAF 21A1θ]k[x]k[dx]k[qx ]k[qx¯]k[dx¯MAPdXqX)ksTrpi fsin (2×MAFrf rf2 rf3 rf4sxXdXdX¯1A 2A 3A 4Affff(a) (b)extracted componentLock-In AmplifierFigure 2.8: In (a) the block diagram of the proposed implementation of the digital Lock-In Amplifier (LIA), the Magnitude and Phase (MAP) block combines the quadrature anddirect components to obtain the desired phase and magnitude; in (b) a simplified outline ofthe operation of the LIA for the xd signal.pair to produce direct and quadrature componentsxd[k] = x[k] sin (2pi fr Ts k) (2.22)=(xs[k] +Nmax∑n=1An sin (2pi n fr Ts k + θn))sin (2pi fr Ts k) ,andxq[k] = x[k] cos (2pi fr Ts k) (2.23)=(xs[k] +Nmax∑n=1An sin (2pi n fr Ts k + θn))cos (2pi fr Ts k) .36Considering the detailed expansion of (2.22)xd[k] = xs[k] sin (2pi fr Ts k) +(Nmax∑n=1An sin (2pi n fr Ts k + θn))sin (2pi fr Ts k) , (2.24)which shows that xs is modulated up in frequency to fr. The second term shows the productof all the harmonics with the sine wave. Expanding the second term of (2.24) using thetrigonometric identitysinα× sin β = cos (α− β)− cos (α + β)2, (2.25)yieldsxd[k] =xs[k] sin (2pi fr Ts k) + (2.26)+Nmax∑n=1An2(cos (2pi (n− 1) fr Ts k + θn)− cos (2pi (n + 1) fr Ts k + θn)) .This operation splits the amplitude of An between one harmonic up (n+1) and one harmonicdown (n− 1). This operation is illustrated in Fig. 2.8(b) (in a simplified case with no phaseshift).The signal xd is then fed through a MAF tuned for fr and its harmonics. Given (2.18)and (2.26), the following is observed:• In steady-state xs[k] does not include high-frequency components; its DC value is elim-inated by the notch at fr.• For n = 2, 3, ...., Nmax, n + 1 and n − 1 fall in a notch of the MAF and they arecompletely eliminated• For n = 1, n + 1 falls in the second notch, while n− 1 = 0 falls in the DC gain of theMAF, which is one.37Considering these observations, it can be seen that in steady-state, the output of the MAFassigned to xd[k] isx¯d[k] ≈ A12cos(θ1). (2.27)An analogous study can be done for (2.23) using the trigonometric identitysinα× cos β = sin (α− β) + sin (α + β)2, (2.28)which yieldsx¯q[k] ≈ A12sin(θ1). (2.29)Combining (2.27) and (2.29), the magnitude and phase (MAP) block in Fig. 2.8 asA1 =√x¯2d + x¯2q , (2.30)θ1 = tan−14Q(x¯qx¯d), (2.31)where tan−14Q (·) is the four-quadrant inverse tangent1.For some applications, it is neither useful nor efficient to compute (2.30) and (2.31), as itrequires the computation of square roots and inverse tangents. The outputs of the algorithmcan beXd = A1 cos θ1, (2.32)Xq = A1 sin θ1, (2.33)as shown in Fig. 2.8(a). These outputs allow the computation of the impedance componentsfrom products and divisions, which are easier to compute.1In (2.27) and (2.29) the equation use the approximate instead of the quality to account for the case of spectral leakage dueto the time-limited window. This effect is reduced for longer windows due to the increase attenuation of the MAF. Moreover,this effect is much smaller in steady-state, when the DC component of xs is dominant.38Equations (2.30) and (2.31) or (2.32)and (2.33) yield the ultimate output of the LIA, yetsome implementation details need to be noted before moving on to the impedance calculation,namely the generation of the sine and cosine and the MAF size selection.Sine and Cosine GenerationIn order to compute the LIA, it is necessary to have available a sine and cosine pair, and thiscan be computationally intensive. As it was mentioned in Section 2.1, when the filter andPWM are completely synchronized, it is possible to precalculate the finite sequence (2.5),and the same can be done for the sine signal:s[i] = sin(2piNi), 0 ≤ i < N, (2.34)with N given by (2.4). The sine signal is then computed assin (2pi fr Tsk) = s[kmodN ], (2.35)updated every Ts. It is evident from (2.6) and (2.35) that the reference can be generated bysimply havingr[k] = Ar s[kmodN ]. (2.36)Given the symmetric properties of the sine and cosinesin(θ) = cos(θ +pi2), (2.37)or, in terms of s[i],cos (2pi fr Tsk) = s[(k +N4)modN], (2.38)39iswN T=r/f= 1rT4N/+i)iNpi2] = sini[s)iNpi2= cos]4N+i[s]i[srA] =i[r2pi=4NNpi2=θ[0]s[1]s]i[s]4N+i[s1]−N[ststrrA×2]−N[sFigure 2.9: Illustration of the generation of the sine and cosine pairs from a single circu-lar buffer with two phase shifted indexes; the same signal can be recycled to generate thereference.if N is an integer multiple of four. This method to generate r[k] along with the sine andcosine pair is illustrated in Fig. 2.9. As it is observed, the method uses a single circular bufferof size N and two indexes to compute the reference and all the sine and cosine pairs.LIA’s MAF Size SelectionSelecting the size of the MAF (M) is important to guarantee that the filter eliminates thedesired frequency fr and that it attenuates all the bands around the different frequenciesenough. A trade-off between the memory footprint, delay, frequency resolution, and noiserejection need to be developed for each application.For a given reference signal r[k], of frequency fr sampled at Ts, the number of samples inthe signal is given by (2.4),N = (fr Ts)−1 , (2.39)40which is the same as (2.19) for n = 1M =1Tsfr. (2.40)This yields that the minimum size of the MAF to eliminate fr is the same number of samplesas the reference has:Mmin = N. (2.41)This is reasonable since a moving average of a sine wave that has a window of exactly oneperiod is zero. To increase the noise immunity, n in (2.19) can be increased. Under thisconsideration, n = Np becomes the number of periods of r[k] to average.By selecting Np, the size of the MAF is thenM = Np ×N. (2.42)Increasing Np increases the noise rejection, the attenuation of the side bands, the conver-gence time, and the memory footprint. It also reduces the frequency interference during theanalysis.LIA SimulationsA simulation example of the LIA is presented in Fig. 2.10(a). A simple RC circuit is shown,there is an input voltage source (vin) that has a constant value of 1V. The signal detected(x) is the capacitor voltage. During the simulation, the value of R suddenly changes from0.5Ω to 2.0Ω.The frequency response of the system is given byX(jω) =1jω RC + 1. (2.43)4101.0 1.0 1 10 1000.05.0−0.1−5.1−rf/f=nf010−20−30−[dB]|)jω(X|)[rad]jω(X(b)(a)xC2Ω→5Ω.= 0Rinv= 1V∗vLIA]k[rv1θ1Aη5Ω.=0R|)jω(X|0Ω.=2R|)jω(X|0Ω.=2R)jω(X5Ω.=0R)jω(X5.0−=5Ω.=0R)rpif2j(X1.1−=0Ω.=2R)rpif2j(X45.= 00Ω.=2R|)rpif2j(X|89.= 05Ω.=0R|)rpif2j(X|Figure 2.10: In (a) a sample circuit to illustrate the behavior of the proposed Lock-InAmplifier (LIA) where the reference is injected as a voltage and the resistance (R) changes;in (b) the Bode plot of the circuit before and after the change of resistance indicating thegain and phase at the reference frequency (fr).Since R changes during the simulation, X(jω) changes as well. Bode plot of the two sce-narios is shown in Fig. 2.10(b) indicating the magnitude and phase at fr (|X(j2pifr)|Ri and6 X(j2pifr)Ri).The r[k] is injected at the voltage control stage (vr[k]) with the parameters outlined inTable 2.1, given byvr[k] = r[k] = Ar sin (2pifrTsk) . (2.44)The simulations are shown for a deterministic case (no noise injected) for different Np, anda fixed Np adding noise. The objective of the LIA is to extract the effect of the reference onthe system (A1 and θ1). Based on this and X , the expected values for the outputs of the42Table 2.1: Sample LIA ParametersParameter Symbol ValueReference Frequency fr 1HzReference Amplitude Ar 0.01Number of Reference Samples N 16Number of Averaged Periods Np 1, 2, 4Sampling Period Ts = 1/Nfr 1/16 sLIA areA1 = Ar × |X(j2pifr)|, (2.45)θ1 = 6 X(j2pifr). (2.46)This shows how the LIA is able to extract the response of the system to the selected r[k]around the DC operating point. The main limitation in the extraction depends on the reso-lution of the ADC, which limits how small a signal can be and still be detected (oversamplingcan be implemented to extend the resolution [182]).The simulation results for the deterministic case (without noise) are shown in Fig. 2.11(a)neglecting the start-up of the system. Both before and after the change in R, A1 andθ1 accurately measure the expected values. The outputs are shown for several number ofaveraged periods (Np); as it can be observed, increasing Np slows the response of the system.From the knowledge of Ar it is possible to reconstruct the value of X at fr.The outputs of the simulated system for the case with significant measurement noise (η)are shown in Fig. 2.11(b) compared with the deterministic case (both with Np = 4). Thenoise is generated using Simulink’s Band-Limited White Noise block with a Noise Power of1 × 10−6. The resulting amplitude of the injected noise is the same as Ar. With this noise,4315 20 25 30)t(x]k[1A]k[1θ02.100.198.0010.0008.0006.0004.015 20 25 30)t(x]k[1A]k[1θ02.100.198.0010.0008.0006.0004.0tchangeR changeRη+x4.0−6.0−8.0−0.1−2.1−4.0−6.0−8.0−0.1−2.1−= 1pN= 2pN= 4pN= 1pN= 2pN= 4pN(b)(a)t0089.= 05Ω.=0,R1A0045.= 00Ω.=2,R1A0089.= 05Ω.=0,R1A0045.= 00Ω.=2,R1A1.1−=0Ω.=2,R1θ5.0−=5Ω.=0,R1θ1.1−=0Ω.=2,R1θ5.0−=5Ω.=0,R1θFigure 2.11: In (a) the signal (x) and the outputs of the LIA (A1 and θ1) for differentnumber of averaged periods (Mp); in (b) significant noise is added to x and the A1 and θ1are shown for Mp = 4 with and without noise (η).the standard deviation (normalized) in steady state over a period of the MAF, given bysA1 = 100×√∑N×Npn=1 (A1[k − n]− A1,Rx)2A1,Rx(2.47)is below 5%.These simulations illustrate the principle of operation of the proposed LIA and the effectof the design parameters. Using the LIA, it is possible to build an instrument to extract theeffect of selected signals on one of the variables of the system. The selection of the parametersdepends on the particular application.44+-LIALIA]k[v]k[i,v1A,i1A,i1θ,v1θ|z|zθcossinrxImpedance Calculation(a) (b)+-LIALIA]k[v]k[iImpedance Calculationdvqvqidi2urxEmbedded Impedance Detection Embedded Impedance DetectionFigure 2.12: Block diagram of the Embedded Impedance Detection (EZD) calculation usingthe LIAs: in (a) the implementation most suitable for magnitude and phase calculation (|z|and θz); in (b) the implementation to calculate the resistive and reactive parts (r and x).2.3 Impedance CalculationOnce the injected r[k] propagates through the system and the LIA extracts its effect on avariable, these results can be combined to detect the incremental impedance (z). The outputsof the EZD can be calculated in terms of magnitude and phase (|z|, and θz) or as the realand imaginary part (z = r + jx), which might be adequate for some specific applications.A block diagram of this implementation is shown in Fig. 2.12; this diagram expands onthe block diagram of Fig. 2.2. Two LIA blocks, one for a voltage (v) and one for the current(i), are implemented; since the two LIAs are synchronized only one r[k], and one sine andcosine pair are needed. To calculate |z| and θz each LIA produces two outputs: a magnitude(A1,x) and a phase (θ1,x), where x stands for v or i.From A1,x and θ1,x, the magnitude of z at fr is calculated using the block diagram inFig. 2.12(a):|z| = A1,vA1,i, (2.48)45and the phase measurement is given byθz = θ1,v − θ1,i. (2.49)From these, r and x can be calculated asr = |z| cos θz, (2.50)x = |z| sin θz. (2.51)Unfortunately, (2.50) and (2.51) require the computation of the sine and cosine of θz in realtime (and they use the results from (2.30) and (2.31), that require the computation of inversetangents.For applications where r and x are necessary, a better implementation can be obtainedby computing the complex division of the pairv1 = vd + j vq, (2.52)i1 = id + j iq, (2.53)as shown in Fig. 2.12(b). Then, z is given byz =vd + j vqid + j iq=vd id + vq iqi2d + i2q+ jvq id − vd iqi2d + i2q. (2.54)46Using (2.54) r and x are given byr =vd id + vq iqi2d + i2q, (2.55)x =vq id − vd iqi2d + i2q, (2.56)which avoid the calculation of tan−1(·) (and the multiplication by 2, for that matter) in theLIA, and the sine and cosine calculations in (2.50) and (2.51). Moreover, the denominatorof (2.55) and (2.56) is the same, so it only needs to be calculated once.Admittance CalculationThrough this section, the calculations are referred to as “impedance calculation”, but thesame information can be used to calculate the admittance. For some applications, the rela-tionships are more directly evident or apparent by using the conductance. In general, theadmittance is given byy = g + jb, (2.57)where g is the conductance and b is the susceptance.From the outputs of the two LIAs, y is given by|y| = A1,iA1,v, (2.58)and the phase is given byθy = θ1,i − θ1,v. (2.59)47From these, g and b can be calculated asg = |y| cos θy, (2.60)b = |y| sin θy. (2.61)Moreover, the complex division version is given byg =vd id + vq iqv2d + v2q, (2.62)b =iq vd − id vqv2d + v2q. (2.63)Through this document, the method is referred to as “impedance detection”, even whenusing y, to maintain clarity. If the application calls for the use of y, it is indicated in theequations, figures, and text.2.4 Embedded Impedance Detection SimulationsThis section presents simulation results for the proposed EZD method illustrating the be-havior of the system for resistive loads and CPL. Figure 2.13 shows the simulated PEC,including the PWM, with the schematic of the two loads. The outputs of the EZD algorithmextraction of the incremental impedance value for the two sample loads.The outputs of the simulation for a resitive load (Rn) with line inductance (Ll) are shownin Fig. 2.14(a). The load goes from Rn = 2.0 (half the nominal load) to Rn = 1.0 (nominalload). Since the load is resistive, the real part of z (r) is Rn. The reactive part (x) reflectsthe value of the reactance at fr. Although r could be calculated in this example from the DCvalues (Vo and Io), they give no information to calculate x. For a passive load, the proposedEZD allows extraction of x.48cpl,nvcpl,n∗icpl,n∗PlLnRin,nVnLnC o,nvo,niL,niloadgSFigure 2.13: Simulation circuit for the proposed Embedded Impedance Detection (EZD)method; a standard dual loop controller is used (iL and vo) driving the duty-cycle of thePWM, and the EZD measures io and vo; the simulations include resitive load with lineinductance (Rn and Ll) and constant power load (CPL).The outputs of the simulation for a CPL are shown in Fig. 2.14(b). The CPL goes from0.5 (half of the nominal load) to 0.75. The real part of the outputs of the EZD (r) for theCPL is negative as expected: the incremental impedance of a CPL is negative. Since theCPL is ideal in the simulation, its bandwidth is infinite, and x is zero. For the CPL case,x can represent a) the effect of the line inductance, b) the effect of the input capacitor, orc) the behavior of a band-limited CPL. As opposed to the resistive load before, r cannot beinferred from the DC operating point directly: the ratio of Vo and Io is always positive.2.5 SummaryThis chapter presented the general idea and analysis of the proposed Embedded ImpedanceDetection (EZD) method, based on the digital Lock-In Amplifier (LIA). It outlined the abilityof the proposed technique to extract the incremental impedance from the DC system, as seenby the Power Electronics Converter (PEC). The main building blocks of the proposed EZDmethod, the reference (r[k]) generation, the Moving Average Filter (MAF), the LIA, and theImpedance Calculation, were studied analytically. Simulations of various individual stages,49rfrf5.4 0.5 5.5 0.6 5.6 0.71.10.19.00.00.10.00.15.05.10.20.300.005.010.015.0transientov transientovo,nvo,ni1.10.19.00.00.15.05.1o,nvo,ninr nrnxnxnt5.4 0.5 5.5 0.6 5.6 0.7nt0.= 2nR0.= 1nR0625.= 0lLrpi f= 2nx0.= 1o,n∗V(b)(a)0.00.1−0.2−0.3−20.0−20.000.075.= 0CPLP50.= 0CPLP0.2−33.1−Figure 2.14: Normalized simulation results for the voltage and current (vo,n and io,n) andthe outputs of the Embedded Impedance Detection (EZD) method for buck converter with(a) an inductance with a resistive load (Rn) that changes from 2 to 1, and (b) a ConstantPower Load (CPL) that goes from 0.5 to 0.75.as well as a simple integrated system, were presented. Special considerations were mentionedthat outline its implementation in real-time with commercial microcontrollers.The following chapters explore the use of this proposed technique to different applications.Each application looks at the particular requirements and modifications performed to thefundamental EZD algorithm introduced in this chapter. The system looks at the input port,as well as the output port of the PEC to provide useful, actionable information for a DCsystem.50Chapter 3Transient Performance and StabilityImprovement in DC SystemsPower Electronic Converters (PECs) connected to a grid, as shown in Fig. 3.1(a), interfaceloads that can have various different behaviors, such as resistive or constant power, or combi-nations of them. In the outlined grid, the PEC regulates the voltage of the bus, maintainingit within the requirements of the system. Since the output regulation provided by the PECand its stability are dependent on the behavior of the load, it is important to either design acontroller that is robust enough to handle any combination of load (i.e. 0 to 100% of ratedload, 0 to 100% constant power), or to dynamically adjust the controller to the differentloads. Robust controllers are usually tuned to guarantee stability in the most challengingscenario but sacrifice dynamic performance in many other conditions. The proposed Em-bedded Impedance Detection (EZD) method can be used to extract the equivalent load andadjust the controller to achieve reliable dynamic performance (in terms of maintaining theperformance indicators such as overshoot and rise time) without sacrificing stability.Portions of this chapter have been published in• F. Paz and M. Ordonez, “An Embedded Impedance Measurement for DC Microgrids Based on a Lock-In Amplifier,” inProc. 7th IEEE Int. Symp. Power Electronics for Distributed Generation Systems (PEDG), Jun. 2016, pp. 1–6.• F. Paz and M. Ordonez, “High-Accuracy Impedance Detection to Improve Transient Stability in Microgrids,” IEEETransactions on Industrial Electronics, vol. 64, no. 10, pp. 8167–8176, Oct. 2017.51reliable dynamic performanceovttti, KpK∗VovershootfailiKandpKconstantincyadjusted foriKandpKextended stability regionMcomposite loadDGsPIEZDPWMi, KpKDSP∗Vov bL∗ibLirdd∗d)z(CgSoiovcurrent loopincy(a) (b)eyeyFigure 3.1: General diagram of the system under study and the proposed controller, in(a) a block diagram of the proposed system, where sources feed a composite load, and onePEC is in charge of supporting the voltage of the bus (vo), this PEC implements the EZD todetect the incremental load and tune the controller accordingly; in (b) a comparison betweenthe proposed adaptive controller and a standard PI controller for this system showing vo forthe controller with constant Ki and Kp and output of the proposed Embedded ImpedanceDetection (EZD) method which is used to extract the incremental load (ye) seen from thePower Electronics Converter (PEC).In this chapter, the proposed EZD method is deployed to estimate the incremental be-havior of the load of a PEC connected to a DC microgrid. This incremental load is used todynamically tune the PEC’s controller to improve the performance of the system. An outlineof the features of the proposed method is presented in Fig. 3.1(b). It uses only sensors alreadypresent in the system, output current and voltage, and is computed in real time by the mi-croncontroller. This proposed EZD method is in turn used to implement the adaptive controltechnique that monitors the load and updates the controller coefficients ➊ to maintain reli-able transient performance ➋ and extend the stability beyond normally tuned controllers ➌.Controllers are traditionally tuned using constant gains, and show overshoots that exceedthe expected values for some loads and can fail for others. The ability of the proposed EZD52method to extract the incremental load behavior from the different combinations of loads,as well as the benefits of implementing the adaptive control, are validated through computersimulations. An experimental test set-up is deployed using a PEC controlled by a standardmicrocontroller, as well as resistances and electronic loads, to validate the ability of the EZDmethod to detect the equivalent impedance in a real setting. Finally, the implementation iscompared against other load identification techniques to validate its advantages and outlinethe limitations.3.1 System ModelIn this section, a general outline of the system under study is presented. The block diagramof the proposed system is presented in Fig. 3.1(a); it consists of a PEC connected to a DC busthat feeds several types of loads, and that may include other Distributed Generators (DGs).The average and incremental behavior of the different composite loads as seen by the PECare presented. The converter is controlled using a DSP that senses the variables of the PECand implements an inner current control loop and an outer voltage control loop. The EZDmethod is used to extract the incremental load and update the PI controller for the outerloop. A model of the system and the controller is presented around the operating point, andthe impact of the load in the selection of the controller is studied.A schematic of the system under study is presented in Fig. 3.2. A buck converter isconnected to the DC bus that interfaces some loads that are resistive (passive) and somethat behave as Constant Power Loads (CPLs). The source is assumed to be ideal, able toprovide the needed power for the system at this operating point. The PEC is controlledusing a dual loop controller that can linearize the inner part (inductor current) and provideadditional regulation and protections. The outer control loop is assumed to be slower than53bCbLbLiovoiLvDQ loadCPLLRLi LRi CPLigSiVFigure 3.2: Schematic diagram of the analyzed source-end Power Electronics Converterconnected to a network feeding several loads; the loads are grouped in resistive loads (RL)and Constant Power Loads (CPLs).the inner control loop, as it usually is the case, in order to provide the benefits of the dualloop controller.3.1.1 Load ModelIn a DC system, many loads with different behaviors are connected to the bus; altogether,they present a resistive behavior partially, and partially a CPL behavior. Although theseloads present the same DC behavior (i.e., their average output voltage and current are thesame), they influence the dynamic performance of the PEC differently.In general, the load presents a relationship between its voltage (vL) and current (iL):iL = f (vL) . (3.1)In a DC system, vL is mostly constant. The operating point of the DC load is then given bya point (VL, IL) in the characteristic curve of the load. The equivalent DC conductance ofthe load is then defined asG =ILVL. (3.2)This represents the equivalent resistance seen by the source in this particular operating point.54The incremental behavior of the load gives the response of the current around the operatingpoint, as a linearization:iL ≈ IL + g × (vL − VL) , (3.3)where g is the incremental conductance presented by the PEC.Resistive loads (and those active loads designed to behave as resistances) present a verywell known characteristic, given by Ohm’s law. The current taken by the passive load (iRL)is given byiRL =vL(t)RL, (3.4)where RL is the equivalent resistance of all the passive loads in the network.The DC characteristic of the resistive load is simple enough: for a DC load voltage (VL),the current is given byIRL =VLRL. (3.5)Therefore, the DC conductance of the resistive load is given byGRL =1RL, (3.6)The incremental conductance of the resistive load (i.e. the change in iRL , for a change in vL)is clearly given bygRL =diRLdvL=1RL. (3.7)This behavior is illustrated in Fig. 3.3(a). The load behaves as a straight line with positiveslope, as expected. A higher resistive load (lower RL) draws higher IRL and has a steeperslope.551CPL,I2CPL,I3CPL,I4CPL,I5CPL,I5,LRI4,LRI3,LRI2,LRI1,LRI(a) (b)Li LiLv LvLV LVLRg=LRGCPLG0<CPLgFigure 3.3: Voltage and Current (V-I) curves of two types of load operating in DC operatingpoints given by VL, in (a) the curves of a resistive load for different resistance (RL) values;in (b) the curves for a Constant Power Load (CPL) of different values.The current in the CPL part of the load (iCPL), on the other hand, is given byiCPL =PCPLvLif vL > Vmin,0 if vL ≤ Vmin,(3.8)where PCPL is the combined power of all CPLs. While the CPL does not work for low vL (inorder to prevent over current events, from (3.8)), in this chapter it is considered that vL issuch that it does not go into shutdown mode.The DC behavior of the CPL for different PCPL is shown in Fig. 3.3(b), showing its DCvalue and non-linear incremental behavior. The DC operating point is given byICPL =PCPLVL. (3.9)56This DC conductance is indistinguishable from a resistive load with a conductance such thatGCPL =ICPLVL=PCPLV 2L, (3.10)as represented by the dashed lines in Fig. 3.3(b). However, the real incremental behavior ofthe CPL around VL is given bygCPL =diCPLdvL= −PCPLV 2L, (3.11)which is negative (increasing vo causes the CPL to draw less iCPL). This negative gCPL ishighly challenging for controllers, as it pushes the poles of the characteristic equation to theright-half-plane, making the system unstable.Since both types loads are connected in parallel to the bus, the total current that the loaddraws is given byiL = iRL + iCPL =vLRo+PCPLvL. (3.12)When the operating point VL and IL are considered, the equivalent load (Ge) is given byGe =1RL+PCPLV 2L, (3.13)which is seen as an equivalent resistive load, if the incremental behavior is ignored.For the same VL and IL, the incremental behavior is a combination of a fraction of CPLand a fraction of resistive load. The equivalent incremental behavior of the mixed load isgiven byge =1RL− PCPLV 2L. (3.14)This behavior is shown in Fig. 3.4. Loads that are mostly resistive at the given operatingpoint show a positive ge. Loads that are mostly CPL present a negative ge. For a load that is57LR100%LR75%25% CPLLR50%50% CPLLR25%75% CPL100% CPLLvLVLiLIFigure 3.4: Voltage and Current (V-I) curves of several loads that consume the same amountof power at VL; each load has a combination of CPL and RL that total 100% at the operatingpoint; since they all consume the same current (IL), the nature of the load cannot be inferredfrom the DC values, but the incremental behavior is very different.precisely 50% CPL, ge = 0: the extra current taken by the CPL is the same as the reductionon the resistive part.Although the DC operating point of the mixed loads is the same as the resistive andthe CPL, the stability of the system depends on ge. The ge cannot be inferred from theDC operating point alone. Other components of the system can present reactive behavior(inductive and capacitive). The proposed EZD method detects both the magnitude andphase of the dynamic load in order to obtain the complete behavior.3.1.2 Dynamic Model of the SystemIn this section, the system introduced in Fig. 3.2 is modeled around an operating point inorder to determine: a) its stability and b) its dynamic response. The dynamic response andits dependency on the equivalent dynamic load are presented. The loads are connected to58+-vePIo∗VbL∗i bCbLiovoiLvloadLRLi LRi CPLiCPLbCloadLR+-vePICPLg(a)(b)0 bL∗i˜bLi˜ oi˜ Li˜ LRi˜CPLi˜ov˜ Lv˜Figure 3.5: In (a) the schematic of the system, including the simplified inner loop for thecurrent; in (b), the small-signal model showing the incremental behavior modeled around theset-point.the output of the PEC, therefore,vL = vo, (3.15)iL = io. (3.16)The proposed controller uses two nested loops, a current loop for the inductor current iLband another voltage loop for vo. In this work, the current loop is modeled as ideal, and theanalysis focuses on the voltage loop, as indicated in Fig. 3.5(a).The differential equation for the outer loop is given byCbdvodt= iLb − io = iLb −voRL− PCPLvL, (3.17)where Cb is the output capacitor. The schematic of the system model is presented inFig. 3.5(b). After linearizing around the operating point (Vo, Io), the incremental equation59is given byCbsv˜o(s) = i˜L(s)−(1RL− PCPLV 2o)v˜o(s). (3.18)where the tilde indicates the incremental variable. The incremental model of the PEC ispresented in Fig. 3.5(b). In open loop (˜iLb = 0), the system is stable if the pole in (3.18)remains negative. This is obtained if1RL>PCPLV 2o. (3.19)When the control loop is closed, the control objective is considered to be v˜o = 0. Using a PIcontroller, iL(s) is given byi˜L(s) =(Kp +Kis)(−v˜o(s)), (3.20)where Kp and Ki are the proportional and integral gains respectively. The loop equation isthen given byCsv˜o(s) = −(Kp +Kis)v˜o(s)−(1RL− PCPLV 2o)v˜o(s)= −(geq +Kis)v˜o(s), (3.21)wheregeq = Kp +1RL− PCPLV 2o= Kp + ge, (3.22)is the total equivalent resistive term and ge is given by (3.14).The dynamic response to disturbances to the system is then given byP (s) = s2 +geqCbs+KiCb. (3.23)60With the following characteristicsωn =√KiCb, (3.24)ς =geq2√KiCb. (3.25)Two observations can be derived from (3.23), (3.24) and (3.25): a) the stability of the systemis determined bygeq > 0, (3.26)orKp > −ge; (3.27)and b) the dynamic response of the system is dramatically impacted by ge, even more sothan by the total load, and this value can change in real-time. The use of the EZD methodfor determining ge and an adaptive control scheme based on this real-time measurement isdetailed are introduced in the following section, .3.2 Proposed Incremental Load Detection SchemeThe performance and stability of the controller under different load conditions are affectedby the selection of Kp and Ki. This section proposes a method to tune the controller,dynamically changing Kp and Ki, based on the equivalent load. The proposed adaptivecontrol is based on using the EZD method, built into the PEC, to measure ge and adjustingthe controller for the desired response; these key objectives are outlined in Fig. 3.1. Thetwo critical steps of this approach are outlined in this section: measuring ge, and using thisinformation to improve the controller.613.2.1 Equivalent Incremental Load DetectionTo measure ge, the proposed EZD method is used. The reference signal, a small perturbationin the duty cycle (d), is added to the control loop of the PEC. The minimum size of theperturbation is limited by the sensitivity of the instrument, ADC, and sensors. The outputof the algorithm, implemented using the conductance mode, are|yˆe| = Aˆ1,iAˆ1,v, (3.28)θˆye = θˆ1,i − θˆ1,v, (3.29)where Aˆ1,i and Aˆ1,v are given by (2.30), and θˆ1,i and θˆ1,v are given by (2.31). Then,gˆe = Re (yˆe) = |yˆe| cos(θˆye). (3.30)Figure 3.6(a) shows the V-I of the load connect to the PEC; the load combines a resistivepart and a CPL part. In this case, the resistive part is larger than the CPL, denoted by thepositive slope of the combined VI curve around the operating point. In Fig. 3.6(b), vo andio for the PEC in this condition are shown; as it can be observed, the injected oscillationmagnitude is related to the slope of the V-I curve. Since the load is mostly resisitive, theoscillations in vo and io is in phase, which leads to θˆye = 0.Figure 3.7(a) shows the V-I of the load connected to the PEC; the load combines a resistivepart and a CPL part. In this case, the resistive part is smaller than the CPL, denoted by thenegative slope of the combined VI curve around the operating point. The vo and io for thePEC with this load are shown in the right of Fig. 3.7(b); as it can be observed, the injectedoscillation magnitude is related to the slope of the V-I curve. The opposite phase of vo andio clearly shows the θˆye = pi, characteristic of the CPL net result.62ovoiovtoioIoVoIoV1L,R11L,RI1L,RI1CPLI1CPLIo2V1CPLP+1L,R1o2V1CPLP−1L,R1o2V1CPLP−o2V1CPLP,v1A,i1A(a) (b)Figure 3.6: In (a) Voltage and Current (V-I) curves of a resistive load (RL) with a parallelCPL; the RL presents a positive incremental behavior, while the CPL presents a negativeincremental behavior; the black curve shows the VI curve of the combined load, since theresistance draws more power at this operating point, the incremental behavior is resistive(ge > 0); in (b) the time domain curves show the variation in vo and the effect on each loadseparately (iCPL and iRL) and the combination, since the load is mostly resistive, the resultis vo and io are in phase.An exceptional condition is presented when gˆe, given by (3.14), approaches zero: anysmall error triggers the change of θˆye between 0 and pi; this, however, is not reflected in alarger than typical error in the estimation. This condition is shown in Fig. 3.8(a), when theCPL exactly matches the resistive part. Since the estimation depends on the decompositionin real and imaginary parts (by multiplying by sine/cosine), the oscillation maps to a signchange in the real part. Since |yˆe| in itself is close to zero, the resulting amplitude is onlyaround ±∆Re/2 (the measurement error). When |yˆe| is more substantial, this change doesnot show as a large oscillation, although the magnitude of the actual error is the same.The selection of the EZD parameters (especially M and Ar) is dependent on the rippletolerance of the system and the computational power available. Since the EZD method canbe implemented very efficiently in the microcontroller (using very few computation resourcesin real time), the buffer sizeM can be incremented to increase the sensitivity of the technique.63,v1A,i1AovoiovtoioIoVoIoV1L,RI1CPLIo2V2CPLPo2V2CPLP−o2V2CPLP−2L,R1o2V2CPLP+2L,R12L,R12L,RI2CPLI(a) (b)Figure 3.7: In (a), the Voltage and Current (V-I) curves of a resistive load (RL) with aparallel CPL; the RL presents a positive incremental behavior, while the CPL presents anegative incremental behavior; the black curve shows the VI curve of the combined load,since the CPL draws more power at this operating point, the incremental behavior is CPL(ge < 0); in (b) the time domain shows the variation in vo and the effects on each load andthe net result, the net change is a 180◦ shifted in io.Critical information from the system can be extracted in real-time and used to improve theperformance of the system using this technique.3.2.2 Control Adjustment TechniqueThe equivalent load can be used to tune a controller to exhibit a set of desired response char-acteristics and be adjusted in real-time to keep the response constant using the informationobtained from the EZD method. For this, a gain-scheduling technique is presented.To ensure the stability of the small-signal model, the resistive contribution of the controllerhas to be kept atKp + ge > 0. (3.31)This presents a lower boundary for Kp, especially when the load is mostly CPL (ge < 0).64,v1AovoiovtoioIoVoIoV3CPLI3L,RIo2V3CPLP=3L,R1o2V3CPLP+3L,R1o2V3CPLP−= 0o2V3CPLP−3L,R1= 0,i1A(a) (b)Figure 3.8: In (a) the Voltage and Current (V-I) curves of a resistive load (RL) with a parallelCPL; the RL presents a positive incremental behavior, while the CPL presents a negativeincremental behavior; the black curve shows the VI curve of the combined load, since theCPL and RL draw precisely the same power at this operating point, the incremental behavioris null (yˆe = 0); in (b) the time domain shows how a displacement in vo causes no change inio, caused by the exact match between the variation of iRL and iCPL.The dynamic performance of the PEC is given by (3.24) and (3.25). Once again, it canbe seen from (3.25) that ς is influenced by ge which works by adding gain to the loop (if theresulting load is CPL), or by subtracting it (if the resulting load is resistive). The selectionof Kp has to be tuned to ensure stability and consistent dynamic response when the loadchanges.The selection of the possible coefficients depends on ge: if ge < 0, Kpv should be increasedenough to meet (3.31) and then the final selection is made asKi = Cbω2n, (3.32)andKp = 2Cbωnς − ge. (3.33)65This yields the desired response independently of the load. If ge > 0, there is the possibilitythat (3.33) yields Kp < 0; in this case, it was preferred to keep Kpv > 0 and sacrifice someperformance in order to avoid a nonminimal phase zero in the system.The update of the controller coefficients is performed in steady-state, to avoid errorsproduced by transients in yˆe. During the transient, the PEC goes through a series of dynamicstates; as shown in Fig. 3.4, ge is only defined at each operating point, not during thetransients. Moreover, in a real implementation, the CPLs have limited bandwidth, whichleads to a slower response and a transient behavior that is not entirely representative of theexpected dynamic load. The proposed application allows the controller to add a margin ofstability by adding some extra gain around the current operating point, instead of designingfor the absolute worst transient.3.3 Simulation ResultsThe previous section introduced the use of the proposed EZD method to measure the incre-mental behavior of the equivalent load and adapt the controller to it. Simulation results arepresented in this section to validate the detection method and the proposed adaptive controlapproach. The simulations are performed over the circuit in Fig. 3.2. All the magnitudes inthe simulation system are introduced in the normalized domain, according to the values inTable 3.1. This allows the simulation to be performed independently of the size of the PEC.In order to validate the ability of the proposed algorithm to extract the incremental behav-ior of the total load, several transitions are tested that take the system from a pure resistivestate to a mostly CPL state. Table 3.2 shows the different scenarios in the simulation, alongwith the increment in each kind of load, the total load, and the equivalent DC and incre-mental conductances calculated from (3.14) and (3.13). The loads are presented normalized66Table 3.1: Normalized Simulation Parameters for Equivalent Incremental Load DetectionParameter Normalized ValueVo,n 1Lb,n 1/2piCb,n 1/2piZo,n√Lb/Cb = 1Io,n Vo,n/Zo,n = 1fo,n 1/2pi√LbCbtn t× fo,nvo,n vo/V∗oio,n io/I∗oRo,n Ro/ZoTable 3.2: Simulation Conditions for Testing the Equivalent Load Detection AlgorithmLoad Equivalent LoadLabel Resistive CPL Total Load Gn ge,nA 0.25 0 25 0.25 0.25B 0.25 0 50 0.50 0.50C 0 0.50 100 1.00 0.00D 0 0.25 125 1.25 -0.25with respect to Zo,n; they are described asPn =V 2o,nZo,n= 1. (3.34)Under these conditions, the start-up condition of a 0.25 resistive load meansRL,1,n =V 2o,nPRL,1=10.25= 4. (3.35)The steps in the load in CPL mode are given as a fraction of the unitary load.67The simulation results of the proposed technique are presented in Fig. 3.9. The upperplot shows vo,n, while the lower plots show the outputs of the EZD method (|yˆe,n| and θˆye).The transients A and B present a resulting resistive behavior that is correctly captured bythe algorithm. Transient C adds enough CPL to cause |yˆe,n| = 0 (which causes oscillationsin θˆy), as expected from measuring zero. If the load were to present a dynamic reactivecomponent (considering input capacitance, connection inductance), the oscillation would notbe noticeable, since the oscillation would be a minimal variation around pi/2 (0.25 in thenormalized domain). Finally, 0.25 CPL is added which causes the resulting |yˆe,n| to be equalto the initial step, but with θˆye = pi. Even though the total load is 1.25, the incremental loadis very different. The results in Fig. 3.9 show how the proposed algorithm can accuratelymeasure the incremental behavior of the load from the injected perturbation.It can be seen from Fig. 3.9 that the transient response of the EZD method goes throughseveral values before settling in the correct value. This transient is mainly influenced bythe transient in vo and io. During this transition, the information provided by the EZDalgorithm (in the form of |yˆe,n| and θˆye) does not reflect the true nature of the equivalentdynamic impedance, since this is defined around a given operating point, in steady-state.During this transition, the controller cannot be adjusted using the output of the sensor; thisadjustment should be made only in steady-state.Next, transient simulations comparing the proposed controller against fixed controllerstuned for different nominal loading conditions are presented. Figure 3.10 shows the loadprofile used for the simulations. The load starts at zero and it periodically increases in stepsof 25% of the nominal load until the full load condition is reached.The simulation results for the sample application of the adaptive controller are shown inFig. 3.11, and the same transients are presented for two fixed controllers tuned for 25% CPL inFig. 3.12 and for 100% CPL in Fig. 3.13. During the simulation, more CPL is added in stepsof 0.25 periodically; the performance of the PEC is evaluated accordingly. After the second6800.01.01.0)ntnormalized time (5 10 15 207.08.09.01.12.04.06.08.0)o,nvvoltage(normalizedoutput0piRes<CPL Res>CPLCPL = ResA B C Dnormalizedincremental)|e,ny|load(incrementalload)eyθphase(0>e,ny = 0e,ny 0<e,ny= 0eyθpi=eyθoscillateseyθFigure 3.9: Simulation results of the proposed EZD method under load change conditionsin the normalized domain; the load changes from 0.25 (resistive), adding 0.25 resistive, thenadding 0.75 units of CPL in two steps; the output of the instrument shows the detection ofthe magnitude and phase of yˆe,n as expected.0 5 10 15 20)ntnormalized time (25.+0 25.+0 25.+0 25.+0CPL:NormalizedLoadPower25.050.075.000.100.0Figure 3.10: Load profile for the simulated transient; the CPL starts at 0% of the nominalload and periodically increases by 25% until nominal load is reached.690 5 10 15 20)ntnormalized time ()o,nvvoltage(normalizedoutput7.09.08.00.11.12.125.+0 25.+0 25.+0 25.+0CPL:Figure 3.11: Simulation capture of the adaptive technique under load change conditions; theproposed equivalent incremental load detection technique allows the controller to be adjustedin each step ➊, maintaining an acceptable overshoot ➋, and maintaining stability for the fullCPL condition ➌.step, the controller tuned for 25% CPL becomes unstable. The controller tuned for 100% CPLis stable all the time since it was tuned for the worst condition. However, it presents variableperformance, including oscillations, compared with the adaptive controller. The oscillationsare observed during the transients for the 100% CPL controller, given by the interactionwith the current loop. In order to compensate for the expected CPL, the bandwidth of thevoltage loop is pushed too close to that of the current loop. New coefficients can be selectedto improve the dynamic performance and stability of the controller in real-time following(3.32) and (3.33).3.4 Experimental ResultsThe simulations in the previous section showed that the proposed EZD method could capturethe incremental behavior of the load for both resistive, CPL, and mixed loads; however, itremains to be tested that the this can be performed in a real PEC with standard sensorsand real CPLs. To further validate the use of the proposed algorithm, an experimental set-700 5 10 15 20)ntnormalized time ()o,nvvoltage(normalizedoutput7.09.08.00.11.12.125.+0 25.+0 25.+0 25.+0CPL:controllerfailslargeovershootlargeundershootcoincide withadaptiveFigure 3.12: Simulation capture of the standard controller tuned for 25% CPL condition; thetransient coincides with the proposed adaptive technique for the first step, but changes afterthe second, and becomes unstable at the third.0 5 10 15 20)ntnormalized time ()o,nvvoltage(normalizedoutput7.09.08.00.11.12.125.+0 25.+0 25.+0 25.+0CPL:coincide withadaptiveoscillationsFigure 3.13: Simulation capture of the standard controller tuned for 100% CPL condition;the transient coincides with the proposed adaptive technique for the last step, but in theintermediate steps shows poor performance and oscillations.up was built with components that maintain the relationships outlined in the normalizationprocedure in Table 3.1, and the outputs of the proposed instruments were logged.The tests are implemented in a power platform, as shown in Fig. 3.14. The power sup-ply a feeds the PEC b , controlled by an industry standard microcontroller c . Theresistive part of the load (RL) is implemented using power resistors d , while the CPL part71abc debCbLovoiCPLLRiVa b d ebLicmicrontroller board(TMS320F28335)Figure 3.14: Picture and diagram of the experimental set-up implemented to test the pro-posed EZD method to measure the incremental behavior of the load. The power supply afeeds the PEC b , controlled by an industry standard microcontroller c . The resistive partof the load (RL) is implemented using power resistors d , while the CPL part is implementedusing an electronic load e .is implemented using an electronic load e . The parameters of the implemented PEC areshown in Table 3.3.The platform’s vo and io are presented in Fig. 3.15, the upper plots indicate the timedomain signal including the reference. The injected perturbation is so small that it cannotbe plainly seen in the signals given the switching ripple. The panel to the right shows a zoomof the measured signals. The lower plots show the FFT of vo until the first components ofthe switching ripple (removing the DC component). The injected perturbation is shown in72Table 3.3: Experimental Set-Up ParametersParameter ValueLb 2.108 mHCb 4.75 µFfo 1.5 kHzZo 21 Ωfsw 10 kHzfs 40 kHzVin 24 VVo 12 Vfr 250 HzM 40Ar 0.1% )ovDTFT(ovoiinjectedreferenceswfFigure 3.15: Experimental noise immunity test in steady-state; the upper traces (vo and io)show that the advantageous small perturbation signal cannot be seen in the time domain(switching ripple dominates in the zoomed signals); the lower FFT plots depicts how smallthe perturbation signal is compared to the switching ripple.the FFT as the small peak at 250 Hz, much smaller than the ripple, the implemented digitaltechnique is able to extract gˆe from this small reference.The experimental capture of the EZD and the outputs are presented in Fig. 3.16 for threedifferent loading conditions. The results of the proposed EZD method are outputted via aDigital to Analog Converter (DAC) and scaled correspondingly with the Oscilloscope. In73Table 3.4: Experimental MeasurementsFigureLoad Configuration Calculated Value EZD OutputRL [Ω] CPL [W ] gCPL [Ω−1] ge [Ω−1] |yˆe| cos θˆye [Ω−1]3.16(a) 24 0 ∞ 0.042 0.0433.16(b) 24 5 −0.0347 0.007 0.0073.16(c) 24 10 −0.069 −0.028 0.029Fig. 3.16(a) the load is purely resistive and therefore, ge matches the load resistance. InFig. 3.16(b) a CPL of 5 W is added; geq,L becomes larger. However, ge remains positive,since the contribution of the CPL is not enough to change the sign; this is appropriatelyreflected in the output of the algorithm. Finally, in Fig. 3.16(c) another 5 W of CPL areadded, making the influence of the CPL larger than that of RL. The output of the instrumentreflects this by changing the phase to pi.A summary of the experimental cases, as well as the measured result, can be found inTable 3.4. The maximum error found in the measurement is below 5%. Table 3.4 comparesthe results obtained from measuring ge from (3.14) with the output of the proposed EZDmethod. The accuracy of the proposed technique for a given size of the perturbation presentsevidence of the excellent characteristic features of the technique, allowing accurate estimationwith low distortion injected. Increasing the size of the perturbation can increase the accuracyor relax the requirements on the buffer size.3.5 Comparison Against Other Equivalent LoadDetection TechniquesIn the previous sections, the proposed EZD based load detection method was introduced, andsimulation and experimental results showing the behavior of the algorithm were presented. Inthis section, a comparison of the proposed technique with existing load impedance detection74ovoi2Ω.23resistive→0ovoi136Ωresistive→0ovoi4Ω.33CPL behavior→pi(a)(b)(c)|eyˆ|/= 1|ezˆ|eyθˆ−=ezθˆ|eyˆ|/= 1|ezˆ|eyθˆ−=ezθˆ|eyˆ|/= 1|ezˆ|eyθˆ−=ezθˆFigure 3.16: Experimental captures of the outputs of the impedance measurement algorithmfor different load conditions; in (a) with a 24 Ω resistive load, in (b) a parallel connection of5W CPL is added, and in (c) the CPL part is increased to 10W.75Table 3.5: Comparison of the Proposed Technique with Existing Methods Reported in theLiteraturePerturbation ComputationAlgorithm Type Amplitude Frequency (fr) Convergencetime [step]OperationsEZD-Based* sin−d(t) 0.1% High‡ Np/fr +,×, /, tableKalman Filter(KF)†square-i(t) 25% Low‡ 1/2fr +, AB,A−1Recursive LeastSquare (RLS)†square-i(t) 25% Low‡ 1/2fr +, AB,A−1* Implementation is performed in a microcontroller, trigonometric functions are imple-mented with tables† Implementation was performed in a Core-i5 computer, with a real time simulator; eachiteration of the KF or RLS takes about 50µs‡ In this case, the low or high frequency is compared to the bandwidth of the controller, inthe LIA, the perturbation is faster than the loop, in the KF and RLS it is much slowertechniques is presented. These are compared using some of the critical indicators of thealgorithm’s performance: the type and amplitude of the perturbation, the computationalcost (as indicated by the type of operations required), and the convergence time. Twoalgorithms are presented for comparison, both of which are based on the Kalman Filter. Otherimpedance estimation algorithms exist, but they are not implemented for DC systems andhave to operate within the utility frequency (60− 50 Hz), which makes them fundamentallydifferent.The comparison of the main parameters is presented in Table 3.5 for the RLS and theKF. Several main differences can be outlined: the injected perturbation (reported in theexperimental results) indicates that the technique uses a large slow perturbation to estimatethe impedance; this perturbation is later removed, which is an advantage. The quick andsmall perturbation introduced by the LIA provides the benefit of continuous estimation withminimal interference in the system. Moreover, the computations required to use the LIA76are simple recursive additions (using a circular buffer) and some trigonometric calculations,which can all be implemented efficiently using tables. Both the Kalman Filter and the RLSimplementations require the inversion of a matrix, as well as several more computations;for this reason, the computations take much longer even when implemented in a desktop-grade microprocessor (about 50 µs). The computations for the LIA-based method take lessthan 12 µs. The KF and RLS methods do offer one advantage compared to the LIA-Basedmethod: they converge faster, relative to the frequency of the perturbation (1/2fr). Thisis compensated by the faster perturbation and reduced computational cost offered by theLIA-Based algorithm.3.6 SummaryIn this chapter, the use of the Embedded Impedance Detection (EZD) method, built into aPower Electronics Converter (PEC), operating in a DC network was proposed as a way toimprove the transient performance and the stability of the system. The PEC feeds severalloads of different types and magnitudes, and its stability and dynamic behavior depend onthe incremental load, rather than the total load. Constant Power Loads (CPLs) presentan especially challenging problem since their dynamic behavior has an inherent negativeincremental resistance that leads to instability. The proposed EZD method was used toproduce an adaptive control scheme that keeps the transient behavior of the PEC predictableunder load change conditions.The proposed technique offers several key benefits: a) real-time detection of the equivalentincremental load, seen from the PEC, with minimal signal injection; b) transient performanceimprovement for different types of load; and c) extension of the stable operation regionwithout compromising performance in other conditions. The information extracted through77the EZD method allows the real-time adjustment of the controller coefficients in order toobtain a reliable response under load change conditions.Simulations have been carried out to show the ability of the proposed technique to extractthe incremental behavior of the load, not only when it is either purely resistive or purelyCPL, but also when it is of mixed nature. Moreover, the integration of this instrument toadapt the controller was presented, and compared against a standard PI controller tuned forspecific cases.Experimental results using a power platform as well as a standard microcontroller werepresented, showing the accuracy of the proposed technique. The experimental validationsshow the power of the technique to detect a perturbation much smaller than the switchingripple.Finally, a comparison of the proposed technique with other impedance estimation methodsfor stability was introduced, comparing the advantages and disadvantages of the proposedtechnique. The proposed technique, although narrower in its application, can be implementedin real-time in a standard microcontroller, as opposed to other techniques that are powerfulbut too demanding to implement in real time using small microcontrollers.78Chapter 4Islanding Detection and AutonomousOperation for DC SystemsFigure 4.1(a) presents a block diagram of a DC microgrid with an AC interface. In thismicrogrid, the grid interface Power Electronics Converter (PEC) is in charge of the regulationof the bus voltage; if it disconnects, the other PECs need to detect this islanding eventand either disconnect or change controllers to support the grid voltage. Fast and accurateislanding detection (ID) is critical to ensure the system disconnects or transitions to theislanding operation mode. This is especially challenging in DC systems since some of thevariables typically used to differentiate the islanding event (such as phase and frequency) arenot present in DC. Impedance-based methods exist for AC systems and provide minimal Non-Detection Zones (NDZ), so the proposed Embedded Impedance Detection (EZD) method canbe suitable for this application.In this chapter, a novel active ID Method (IDM) for DC systems, based on the EZD, ispresented. Figure 4.1(b) presents a general diagram of the proposed technique, comparinga traditional Over-Voltage/Under-Voltage (OV/UV) IDM to the proposed impedance-basedIDM. The proposed IDM provides three key benefits: virtually zero NDZ for all types ofPortions of this chapter have been published in• F. Paz and M. Ordonez, “An Impedance-Based Islanding Detection Method for DC Grids,” in Proc. 9th IEEE Int.Symp. Power Electronics for Distributed Generation Systems (PEDG), Jun. 2018, pp. 1–7.79tttGTMGTM GTMIMIMoi ovoiV∆±slowdetectionreconnectionnot detectedloadchangeno non-detection zonesmall perturbationfaste detectionislanding and reconnection detectionLIA-ZIDOV/UV IDovo, iovMcomposite loadDGsIDGTMIMDSPbSGF PEC(a) (b)incrˆFigure 4.1: In (a) a block diagram of the DC system feeding a composite load from agrid interface PEC and other source PECs, when the grid interface disconnects, the source-end PEC has to detect this condition and take over regulation of the bus; in (b) behaviorof the proposed EZD-based islanding detection method (IDM) against a traditional Over-Voltage/Under-Voltage (OV/UV) detection method for an islanding event with a closelymatched source and load, a load change, and a grid re-connection; the OV/UV method isnot able to detect the event under very closely matched conditions and does not detect are-connection; the proposed method is based on incremental impedance, and therefore offers:no NDZ ➊, small perturbation ➋, fast detection ➌, and the ability to detect both islandingand non-islanding conditions; paired with a simple controller, it provides smooth transitionbetween autonomous and following behavior.loads ➊; the injected signal is 1% of the duty-cycle, given the sensitivity of the Lock-InAmplifier (LIA), produces a Total Harmonic Distortion (THD) of 1.4% ➋; converges in lessthan 20ms ➌; and the ability to detect both islanding events (grid disconnection) and gridre-connection events ➍. This allows the system to transition between Grid Tie Mode (GTM)and Islanded Mode (IM) without powering down, communications links, or leaving the busunregulated, contributing to increase the reliability and the quality of service.The proposed method is studied for a challenging scenario, where the DGs are producingthe same power that the load is consuming (causing voltage and current not to change duringthe islanding event), both including and not including line impedances. Moreover, different80types of loads are included in the analysis to validate the accuracy of both active and passiveloads. A simple bumpless controller to regulate the operation in GTM and IM is included.Simulations of the proposed algorithm, as well as a standard passive method, are includedto illustrate the proposed algorithm. Experimental results further validate the proposedmethod. A general comparison against other algorithms is included to measure the virtuesand limitations of the proposed method.4.1 System ModelThis section presents a general outline of the system when the gird is connected and inislanding mode. Figure 4.1(a) shows the block diagram of the DC microgrid. The gridforming PEC, connected to the utility AC distribution grid regulates the bus voltage, whilethe distributed generators (DGs) inject power to the system following their guidelines (suchas maximum power point tracking, battery charging profile). The total load is a compositionof several types of load. The constant resistance loads (CRLs, such as heating) show a passivebehavior; active loads, on the other hand, can show different behaviors such as constant powerloads (CPLs) or constant current loads (CCL).During an islanding event, the switch Sb disconnects and the bus is not regulated anymore.The control algorithm in the DGs can be switched over to one that can regulate the busvoltage, instead of other rules.The following subsections cover the building blocks for the proposed method, along witha traditional IDM. It presents the operation of the PEC in its DC equilibrium state and theDC and incremental behavior of the loads and its composition. The section outlines a simplecontroller that can operate in both IM and GTM, with the ability to move in between themsmoothly, and switch between modes following the ID signal.81si bS dcvsCoiov1Z 2Z(a) (b)ersi bS dcvsCoiov1Z 2ZerFigure 4.2: Incremental model of the microgrid, as seen by the source-end power electronicsconverter in (a) Grid Tied Mode (GTM) and (b) islanded mode.4.1.1 DC System ModelFigure 4.2(a) shows a model of the system when the grid is connected (Sb is closed). Thesource-end PEC is modeled as a current source with a parallel capacitor, modeling the innercurrent loop of the PEC. The Z1 and Z2 model the losses of the wires connecting the loadand the grid-forming PEC. The grid forming PEC is considered an ideal voltage source. TheRe represents the fraction of the composite load that is fed by the PEC under analysis.When the PEC is not islanded, the average output voltage (Vo,ni) is given byVo,ni =(R1 +ReR2Re +R2)Is +(ReRe +R2)Vdc, (4.1)where Is = Io (the ripples are absorbed by the capacitor). In this condition, the resistance(Rni) seen from the terminals of the source-end PEC isRni =Vo,niIo=(R1 +ReR2Re +R2)+(ReRe +R2)VdcIs, (4.2)a superposition of the load components, the line, and the influence of the grid forming PEC.Since R1 and R2 are relatively small, Vo,ni is approximatelyVo,ni ≈ Vdc, (4.3)which does not depend on the load condition.82Figure 4.2(b) shows the same system under the islanded condition. In this case,Vo,i = (R1 +Re) Is ≈ IsRe, (4.4)and the resistance seen from the source-end PEC in islanded mode (Ri) isRi =Vo,iIo,i= R1 +Re ≈ Re. (4.5)The Ri clearly depends on the load condition.This difference in DC resistance could be enough to differentiate between the islanded andthe non-islanded condition in many cases, but lacks the ability to the detect when the loadclosely matches the source. In this case, since the source-end PEC was initially supplyingthe load, the difference is minimal. The difference is affected by unknowns, such as R1 andR2.4.1.2 Composite Load ModelLoads can come in different forms and combinations. The simplest is a Constant ResistanceLoad (CRL), in which Ohm’s Law gives the V −I relationship. Active loads come in the formof CCL, where the current is independent of the voltage applied, and Constant Power Loads,where i = P/v. Ideal CCLs have infinite parallel resistance, while ideal CPLs have infinitebandwidth. A diagram of these kinds of loads, along with their V − I curves, is presentedin Fig. 4.3. Although the DC resistance (Re = Vload/Iload) is the same for all the cases, theincremental resistance (re = dv/di) is different. The CCLs have an infinite re, while CPLspresent an inherent negative resistance (dv/di < 0).83LvLiLVLI →∞pRCCLiCCLCPLvLPFCPLPCPLLRCRLLRCPL+LRCCL+Figure 4.3: Voltage and Current curves of different loads: Constant Resistance (CRL), Con-stant Current (CCL), Constant Power (CPL), and composite loads; ideal CCLs have aninfinite parallel resistance (Rp), while real ones have a very high one; ideal CPLs have infi-nite bandwidth, while real CPLs show a limited bandwidth.The resistive load that draws PCRL is given byRL =V 2LPCRL, (4.6)where VL is the voltage in the load. The incremental behavior is given byrCRL =dvCRLdiCRL= RL. (4.7)For a CCL, that draws PCCL, the incremental behavior is given byrCCL =dvCCLdiCCL=∞. (4.8)Finally, for a CPL, the incremental behavior for a load of PCPL is given byrCPL =dvCPLdiCPL= − V2LPCRL. (4.9)84For a composite load (i.e. a load that is part CRL, part CPL, part CCL), and that drawsPL given byPL = PCRL + PCPL + PCCL, (4.10)the incremental behavior depends on the combination of loads. The state of load (pL) of thePEC is defined by the ratio between PL and the rated load (PN)pL =PLPN=1PN(PCRL + PCPL + PCCL) . (4.11)Moreover, it is possible to analyze the load combination by analyzing the fraction of the loadthat is of each kind. The normalized load (pL) represents the total load in relationship tothe nominal load of the converter and is given bypL =PLPN=PLPN(PCRLPL+PCPLPL+PCCLPL). (4.12)The re is given by the parallel connection of all the types of load, thenre =(1rCRL+1rCCL+1rCPL)−1. (4.13)Plugging in (4.6), (4.7), (4.8), and (4.9), the re is given byre =(PCRLV 2L+1∞ −PCPLV 2L)−1, (4.14)=(PCRLV 2L− PCPLV 2L)−1, (4.15)= V 2L (PCRL − PCPL)−1 . (4.16)85Using (4.10) in (4.16)re = V2L (PL − PCCL − 2PCPL)−1 , (4.17)=V 2LPL(1− PCCLPL− 2PCPLPL)−1(4.18)By multiplying and dividing by PN , the re can be expressed asre = RN1pL(1− PCCLPL− 2PCPLPL)−1(4.19)where RN is the nominal load resistanceRN =V 2LPN. (4.20)From (4.19) it can be observed that re can be lower than zero, but its absolute value is alwaysgreater than RN .Figure 4.4(a) shows the normalized re (i.e. re,n = re/RN) for a mix of CPL and CRL(PCCL = 0). The plot shows all the combinations of loads, including different pL and differentPCPL/PL. For a fraction of CPL lower than 50%, the re is positive, while for higher than50%, re is negative. However, this transition passes through an asymptote, without crossing1 or 0.Figure 4.4(b) shows the same plot for a CCL with CRL. The plot shows all the combina-tions of loads, including different pL and different PCCL/PL. As the portion of CCL increases,the re increases, and for very light load condition, the re also increases.860.0 0.00.5 0.51.0 1.0LPCPLPNPLP02486100<i,nrfori,nr−|e,nr|= 1|e,nr|LPCCLP0.0 0.00.5 0.51.0 1.0 NPLP0248610|e,nr|= 1|e,nr|(a) (b)Figure 4.4: Normalized incremental resistance (re,n) for a composite load that is part resis-tance and in (a) part CPL and in (b) part CCL, as a function of the load state (PL/PN) andthe fraction of active load; |re| > 1 for all conditions.4.1.3 Bumpless Controller Mode ChangeThe control of the distributed generators can follow two alternative modes: grid-tie or island;switching over between them depends on the IDM. Figure 4.5 shows a block diagram of theproposed controller. In GTM, the current reference (I∗s ) of the inner loop can come fromdifferent strategies, such as the maximum power point tracking (MPPT) algorithm or thebattery management system. Since vo is being regulated by the grid forming PEC, there thevoltage variation is only due to small line resistance.In IM, the PEC should regulate vo. This regulation can take several forms: in a master-slave setting, the energy storage could take the lead to regulate vo after the grid connectionis lost, while other DGs keep working in GTM; in a current share setting, a droop law isimplemented to share regulation among the PECs.The controller in Fig. 4.5 is a simple PI controller, given byuc = Kp(ev +∫ (Kiev +Kweu +Ktei∗s)dt), (4.21)87iK+---++ +++pKwKtKo∗Vov/s1vecu suues∗is∗ies∗Iislanded mode (IM) controllermodeselectorrigrid tie mode (GTM)controllerFigure 4.5: Proposed controller for the source Power Electronics Converter (PEC); in GTM,the PEC operates in current source mode, and its reference comes from the local controller;in islanded mode the controller follows a voltage reference (V ∗o ) using a PI controller (Kpand Ki), the controller includes an anti-windup method (Kw) and an output tracker (Kt) toallow for a bumpless transition between modes; the IDM allows switching between modes.where Kp and Ki are the PI constants. The controller includes a two amendments to ac-count for non-ideal conditions: control signal saturation with anti-windup, and control signaltracking. The saturation is given byus =uc if Imin ≤ uc ≤ Imax,Imax if uc > Imax,Imin if uc < Imin,(4.22)where Imax and Imin are the limits of the PEC output. Then, eu is drawn to zero by theintegral controller with a gain of Kw, ensuring the integrator does not extend beyond thesaturation limit.To allow for a smooth transition between the GTM and IM, the IM controller needs tohave the same output as the GTM controller when in GTM mode. This tracking is achievedby incorporating a feedback of the actual control signal and the decision of the IM controller(ei∗s), adjusted by the tracking gain (Kt). Using these adjustments, the controller can switchbetween modes smoothly. A similar tracking mechanism is implemented for the GTM.88In the master-slave case, the voltage set-point of the IM output voltage set-point (V ∗o ) isV ∗o = Vset, (4.23)where Vset is the rated bus voltage. In the current sharing mode, V∗o is given by the drooplawV ∗o = Vset − Rdio, (4.24)where Rd is the droop gain. In this chapter, the controller implemented uses a droop law,but the results are the same for a master-slave setting. Although the controller might bethe same, the criteria used to switch between modes can make a difference in the systembehavior, and traditional modes do not always do a good job.4.1.4 Traditional Islanding Detection MethodThis section presents a traditional IDM as a reference. The method is based on the under-voltage/over-voltage (UV/OV) method. Figure 4.6(a) shows a block diagram of the proposedmethod. The algorithm compares vo with the reference set-point and creates a detection zone(DZ, usually ±5%) where vo is allowed to vary and still be considered as non-islanded. Themain advantage of the UV/OV voltage is its simplicity and passive nature, which allows itnot to distort the operation of the system at all.A time diagram of the traditional method is presented in Fig. 4.6(b). When the grid isconnected, as per (4.3) Vo is close to the grid voltage, independently from the load. During anislanding event, the Vo is given by (4.4). If the load and source are different (e.g., if the sourceis supplying 10A and the load takes 15A) Vo,ni is very different from Vo,i and the traditionalmethod can detect the change. However, if the load is closely matched with the source (e.g.,if the source is supplying 10A and the load takes 9.9A) Vo,ni is very similar from Vo,i and the89(a) (b)OV/UV islanding detectionOMOMtttoiovovOMIMGTMDZIMGTMislandinggridreconnectsov∆setV05.0setV05.0−setV05.0−setV05.0+-setVDZov∆Figure 4.6: In (a) a block diagram of a simple under-voltage/over-voltage (UV/OV) IDM; in(b) a timing diagram of the outputs of the UV/OV method, the output voltage (vo) changesafter the islanding event, as the load takes less power, however, depending on how closelymatched the load and source are, this can go unnoticed; if the islanding event is triggered,the method is not good to detect the reconnection.traditional method is unable to detect the islanding event. This limitation defines the NDZas the range of loads that do not cause a sufficient change in Vo to be detected.The UV/OV method is aimed to disconnect the PEC from the grid under the islandingevent; therefore, the reconnection criteria is given by Vo returning to the safe zone. If thesystem is configured to change the mode to a grid forming mode, then the voltage is alwaysin the range; therefore the UV/OV method is not able to detect the grid reconnection in thisscenario.90(a) (b)LIALIAimpedance-based methodOMOMtttDZoioiovovincrOMincrNRNR−IMGTMDZIMGTMri)ksTrpifsin (2rAislandinggridreconnectsrfT∆oi˜+oIov+ ˜oVEZDICˆFigure 4.7: In (a) a block diagram of the proposed impedance-based IDM, it is based on usingthe proposed Embedded Impedance Detection (EZD) and a Detection Zone (DZ) defined bythe characteristics of the load; in (b) a time diagram of the proposed method showing thechange in the output voltage (vo) and current (io) caused by the injected reference (ir) for bothislanding and non-islanding events; the algorithm can identify and switch between controlmodes after a small delay due to the frequency of ir.4.2 Proposed Islanding Detection MethodThe proposed Incremental-Impedance Based IDM is based on two key elements: using theproposed EZD method to measure re, and defining a band of values for each operation mode.The simple block diagram of the proposed method is shown in Fig. 4.7.91When the proposed EZD method is used to inject a reference in the current set-point (i∗s),it causes a small variation to appear in all the variablesis = Is + i˜s, (4.25)io = Io + i˜o, (4.26)vo = Vo + v˜o, (4.27)vdc = Vdc + v˜dc. (4.28)In non-islanded mode, v˜o is then given byv˜o,ni =(R1 +reR2re +R2)i˜o +(rere +R2)v˜dc. (4.29)Therefore the incremental resistance seen by the PEC in non-islanded mode is given byrni =v˜o,nii˜o=(R1 +reR2re +R2)+(rere +R2)v˜dci˜o. (4.30)In islanded mode, v˜o is then given byv˜o,i = (R1 + re) i˜o. (4.31)Then, the incremental resistance seen by the PEC in islanded mode is given byri =v˜o,ii˜o= (R1 + re) . (4.32)It remains to be seen whether the use of these expressions creates a more sensitive ID criteria.The behavior observed in Fig. 4.4, that illustrates the results in (4.19) shows an incremen-tal behavior that is never lower than RN (in absolute value). This can be used in combination92with (4.30) and (4.32), and with the consideration that v˜dc is very small, to obtainrni = R1 +R2 ≈ 0, (4.33)ri = R1 + re ≈ re, (4.34)with |re| > RN . This creates a significant gap between the system operation with andwithout the grid connection, even when considering the losses in the line, making it aneffective method to detect the islanding conditions.These two scenarios are identified using the EZD method presented in Chapter 2. Theincremental resistance (rˆinc) is calculated using (2.55):rˆinc =vd id + vq iqi2d + i2q. (4.35)This calculation allows accurate extraction of the rˆinc with minimal reference injection.Using the difference between ri and rni, the operating mode (OM) is given byOM =GTM if |rˆinc| < RN ,IM if |rˆinc| ≥ RN .(4.36)This simple criteria allows for accurate detection of the islanding condition for any load (evenexactly matched), regardless of the line resistances, and can detect the grid reconnection.The reactive part of the measured incremental impedance (xˆinc) does not play a role inthe IDM. However, it could interfere with the detection. The proposed algorithm allowsdetecting xˆinc by using (2.56), and the results are shown in the simulations, showing that itdoes not interfere with the detection.93Table 4.1: Normalized Simulation Parameters for Islanding DetectionParameter Normalized ValueVo,n 1Lb,n 1/2piCb,n 1/2piZn√Lb/Cb = 1Io,n Vo,n/Zo,n = 1fo,n 1/2pi√LbCbtn t× fo,nvo,n vo/V∗oio,n io/I∗oRo,n Ro/ZoTable 4.2: Simulation Load Cases Considering R1,n = R2,n = 0.01Type Lline,n Ro,n CPL CPL BW CCL Trace[%Zo,n] %Pn ×fr ColorCRL0 0.99 0 - 01 0.99 0 - 0CPL0 1.38 25 200 01 1.38 25 200 00 1.38 25 20 01 1.38 25 20 0CCL 0 0 0 - 1 ∗4.3 Simulation ResultsThis section presents the computer simulations of the proposed IDM for different typesof loading conditions. The results are normalized with the parameters given in Table 4.1.Several loads are considered to evaluate the effect of different conditions on the efficacy of thedetection. Table 4.2 presents the different scenarios and their trace color. For the simulations,the parameters of the LIA are Ar,n = 0.01, fr,n = 8, Np = 1.94Figure 4.8 shows the simulation results for an islanding event. During the islanding event,given the close match between the source and load, there is a slight change in vo,n. TheTHDi before the islanding event is lower than 1.4% and after the event is much lower thanthat. The lower two axes show the outputs of the EZD algorithm. During non-islandedoperation, the EZD reports rˆinc equal to the sum of both line resistances (R1 and R2) whilethe values of xˆinc are equal to the line’s inductive part (xline = 2pifrLline). After the islandingevent, two things can be observed: 1) for all cases, the detected impedance is much largerthan the non-islanded case and is distinguishable from the non-islanded mode; 2) limitingthe bandwidth of the CPL results in a capacitive-like effect manifesting. In all cases, the gapbetween non-islanded and islanded is significant, allowing for a clear differentiation betweenboth operating modes.A magnification during the islanding transient is shown in Fig. 4.9. The type of loadimplemented affects the length of the transient in the LIA. Adding Lline slows down theconvergence by a small amount while adding the CPL increases the convergence time sig-nificantly. Moreover, if the CPL has a bandwidth that is close to the LIA’s frequency, thetransient is significantly larger. In all cases, the proposed EZD method converges to a valuethat can be flagged as an islanding condition and allows the controller to implement theappropriate decision.A different comparison of the simulation results can be seen in Fig. 4.10 for the steady-state outputs of the proposed EZD method before and after the islanding event. The resultsin Fig. 4.10 are presented in the impedance plane, showing how the simulation results nevercome inside the area defined by ri,n < 1. An ri,n < 1 would imply the PEC is overloaded,and this would trip the protections. Although some tolerance is allowed in io, it never bringsri,n close to rni,n. On the other hand, confusion could come from the losses in the line (Z1),but there are not many applications in which losses are comparable to the load itself. Thisgives the EZD method a wide application range.952 4 6 8 105.00.10.05.0−0.1−0.00.10.20.30.496.098.000.102.104.196.098.000.102.104.1s,n∗Iinc,nxinc,nro,nio,nv)ntnormalized time (rated loadislandingeventi,nrni,nrCPL bandwidthˆˆˆˆFigure 4.8: Simulation results of the proposed incremental impedance-based IDM in openloop (no control action) for different types of loads listed in Table 4.2 with a small lineimpedance; before the islanding event, the output voltage (vo) is stiff and current (io) showsa larger oscillation (a low rˆinc), while after the islanding event, this is reverted; the proposedalgorithm is able to separate the effect of the line inductance (L1) and the bandwidth of theCPL and reliably detect the islanding event in all cases.A final comment on the simulation scenarios: Table 4.2 lists a case with a CCL (∗), butas expected an ideal CCL can not be implemented, so it was limited by the parallel resistor(Rp). Under these conditions, the output of the islanding detector yields rˆinc = Rp (a verylarge number). This case is easy to detect due to the very large value of Rp (tens of times96islandingevent5.00.10.05.0−0.1−0.00.10.20.30.496.098.000.102.104.196.098.000.102.104.1inc,nxinc,nro,nio,nv)ntnormalized time (i,nrni,nr0.5 5.5 0.6 5.6rated loads,n∗Ieffect of CPL bandwidthˆˆˆˆFigure 4.9: Detail of the simulation in Fig. 4.8 showing the transient behavior of the proposeddetection method for the different loads; the type of load can extend the transient, but theworst-case puts the reliable detection well inside one time constant of the power electronicsconverter.the nominal load), but would have distorted the simulations figures due to scale and it wasomitted.A simulation of the proposed system in closed-loop, using either the proposed impedance-based IDM or a traditional OV/UV method is presented in Fig. 4.11. The capture shows voand io, as well as the operating mode the system is in. The controller is the same for bothmethods, only changing the criteria to switch between them. As can be seen, during the first973.02.01.00.00.01.0−2.0−3.0−5.0 0.1 5.1 0.2 5.2)inc,nrnormalized incremental resistance ()inc,nxnormalizedincrementalreactance(= 1incr= 0incr = 0CPLP99.= 0CRLP1Lrpif21Lrpif21Lrpif225.= 0CPLP74.= 0CRLPBW reductionˆˆˆ ˆFigure 4.10: Simulation results of the proposed IDM for different loads in the impedanceplane, normalized to the nominal load; for all loads, the detected impedance in non-islandedmode is 100 times or more smaller than the impedance in islanded mode, even includingthe line impedance; for the islanded mode, the impedance is higher than 1, even for limitedbandwidth CPLs.interval A , the PEC operates in GTM , reflected by the low oscillation in vo (stiff voltage),the load is closely matched to the source. In B , the grid forming PEC is disconnected,while the OV/UV method does not detect the change due to the load falling in the NDZ,the proposed method quickly identifies the event and switches to IM ➌. In C , the loadchanges causing the OV/UV to detect the condition and change mode; it is also noted thatthis transient does not cause a false detection with the proposed method. Finally, in D thegrid forming PEC reconnects and the proposed method promptly identifies this conditionand switches to GTM. The OV/UV method does not detect this. This is all achieved with areference amplitude of 1% duty cycle ➋.98A B C D)ntnormalized time ()o,nvvoltage(normalizedoutput0 1 2 3 4 5 6 7 8 9 100.60.81.0IMGTM1.051.000.95normalizedoutput)o,nicurrent(operatingmodeoi×dR−o∗Vslowdetectionreconnectionnot detectedno droopLIA-ZIDOV/UV IDFigure 4.11: Simulations of the proposed closed-loop system using the traditional OV/UVIDM and the proposed impedance-based method; the traditional method fails to detect theislanding event at first, and only does so after the load transient, while the proposed methodsmoothly transitions between modes quickly and accurately.4.4 Experimental ResultsThe simulations in the previous section showed that the proposed EZD method can detectthe connection and disconnection of the grid, i.e., the islanding events, clearly for a varietyof loads and that this can be used to switch between a GTM regulator and an IM regulator.To further validate the use of the proposed algorithm, an experimental set-up was built withparameters that follow the proportions outlined in the normalization stage stage in Table 4.1,and the outputs of the proposed instruments were logged.Figure 4.12 shows a diagram of the platform used to test the proposed method. The powersupply a feeds the PEC controlled by an industry-standard microcontroller a . The loadis implemented using a power resistor and an electronic load c , while the grid forming PEC99bCbLovoiCPLa b d ebLimicrontroller board(TMS320F28335)cPECinVFigure 4.12: Diagram of the experimental set-up used for validating the proposed method.The power supply a feeds the PEC controlled by an industry-standard microcontroller a .The load is implemented using a power resistor and an electronic load c , while the gridforming PEC is implemented using a PEC d and source e .Table 4.3: Experimental Set-Up ParametersParameter ValueLb 2.108 mHCb 4.75 µFfo 1.5 kHzZo 21 Ωfsw 10 kHzfs 40 kHzVin 30 VVo 24 Vfr 5 kHzNp 4Ar 1%is implemented using a PEC d and source e . The parameters of the implemented PECare shown in Table 4.3.The platform’s vo and io are presented in Fig. 4.13, the upper plots indicate the timedomain signal, including the reference. The injected perturbation cannot be seen in the100Short Transient (Mp=4) T = 16msovoi)incz= im (incx)incz= re (incr r∆Short Transient (Mp=4) T = 16msovoi)incz= im (incx)incz= re (incr r∆islandingislanding(a)(b)ˆ ˆˆ ˆ ˆˆ ˆˆ ˆ ˆFigure 4.13: Experimental captures of the proposed incremental impedance-based IDM inopen loop (no control action) for different types of loads listed: in (a) a resistive load and in(b) a mixed load part CPL and part resistance.signals given the switching ripple. The lower plots show the outputs of the EZD algorithmthrough a DAC (and properly re-scaled). It can be seen that for different kinds of loads, theoutput of the sensor differentiates the GTM from the IM.101Table 4.4: Comparison of the Proposed Technique with Existing MethodsPerturbation DetectionAlgorithm Type Amplitude Frequency(fr)Convergencetime [step]NDZ ID/N-IDProposedmethodsin−is 0.1% High Np/fr none yesOV/UV none – – fast large noCurrent In-jection∆Is large† low slow f(∆Is) noPositiveFeedbackis or vo large* – medium none no‡† Perturbation is 0.1 to 0.9 of Is, and is periodically increased‡ Can be used to detect the reconnection if the action when the islanding event is detectedis to disconnect* there are several combinations that are grouped under this name4.5 Comparison Against Other Islanding DetectionTechniquesThe previous sections introduced the proposed incremental impedance-based IDM and pre-sented simulation and experimental results. The results were compared against a traditionalIDM: the UV/OV method. However, many algorithms offer specific advantages and disad-vantages. This section presents a comparison of the proposed technique against several otherIDMs. These are compared using some of the critical indicators of the algorithm’s perfor-mance: the type and size of the perturbation, the convergence time, the NDZ, and the abilityto detect a reconnection as well as an islanding event. Two other algorithms, the currentinjection and positive feedback, are presented for comparison.Table 4.4 shows a comparison of several IDMs in the literature. Most methods are notdesigned to detect the reconnection of the grid if the system is switched to an islandingcontroller. The current injection method is a combination of the UV/OV method with a102forced change in the set-point. If a change of 10% in the current set-point leads to a changein vo, a new step is injected that can trip the UV/OV scheme. This method can produce largeperturbations in the regular operation of the system (±10% of the rated current during normaloperation), leading to lower MPPT performance and large THD. The NDZ is proportionalto the size of the perturbation.The positive feedback method is another IDM that can be used in DC systems. Theperturbation can be injected in several parts of the loop, and it is proportional to the observeddeviation. In the event of islanding, this perturbation leads the system to unstable operationthat trips the detection method. Since this method relies on forcing the system to operatein an unstable region, it requires careful design to ensure the instability is controlled.Most of these methods are designed to disconnect the system in the event of an islandingcondition. Therefore, they do not target reconnection in their specifications. If the system isdisconnected, the OV/UV can be used to reconnect when vo returns to the normal operatingrange; but it does not work to achieve smooth operation.4.6 SummaryThis chapter proposed the use of the Embedded Impedance Detection (EZD) method, builtin a Power Electronics Converter (PEC), operating in a DC microgrid as an active islandingdetection method (IDM). The PEC feeds a composite load, showing a mix of resistive (CRL),Constant Power (CPL), and Constant Current (CCL) parts. The proposed incrementalimpedance-based IDM can differentiate the GTM, where the incremental resistance is almostzero, from the IM where the incremental resistance is higher than the nominal load.The proposed technique offers several key benefits: a) no NDZ due to the significantdifference in the impedance, b) small perturbation, compared with other active methods,c) fast convergence, and d) the ability to detect both islanded and non-islanded scenarios.103The proposed technique is combined with a simple droop controller to allow for bumplesstransition between modes, maintaining the DC system voltage during the whole process.The proposed technique is limited to a case with a single, designated, converter to regulatethe voltage in the event of an islanding condition. If more than one converter has such role, theinterference of the other source converters in the same grid can present a challenge. If morethan on converter injects the reference at the same frequency, these can interfere with eachother; this can be addressed by selecting different frequencies for each converter, but requirecoordination in the installation. On the other hand, this problem can also be addressed byimplementing complementary IDMs: while a leader converter injects the reference signal, afollower will work to cancel its own injection (presenting a high impedance at the reference’sfrequency). This allows the leader to apply the proposed IDM and the follower to detect theislanding by the change in the cancellation signal, more research is needed to address thischallenge.Simulations were carried out to show the ability of the proposed technique to detect theislanding event. Many different mixed loads were analyzed; for all, the proposed method candetect the islanding event.Experimental results using a power platform as well as a standard microcontroller werepresented, showing the accuracy of the proposed technique. The experimental validationsshow the power of the EZD method to detect the islanding condition for different types ofload.Finally, it presented a comparison of the proposed technique with other IDMs (both activeand passive), comparing the advantages and disadvantages of the proposed technique. Theproposed technique is able to detect the islaning event with an injected signal of 1% of thenominal current, using an industry standard microcontroller and sensors.104Chapter 5Low-Impedance Fault LocationModern DC systems are pushed to increase their autonomy as generation is becomingmore distributed. One feature that has the potential to be distributed in the system is afault location mechanism for Low Impedance Faults (LIFs) after the Over-Current Protection(OCP) is activated. This mechanism would allow the power electronics converters (PECs)in the system to report the faulted connection and the distance to the fault to speed uprepairs. Accurate knowledge of the faulted line can significantly reduce repair time and cost,by avoiding the use of dedicated hardware that needs to be move around to scan the gridlooking for the fault.New architectures for DC systems that allow for reconfiguration have been presented.Figure 5.1(a) presents a block diagram of a sample DC system with two sources feeding aresistive load. The system shows a LIF in the line connecting source 1 and 2. A ring-typemicrogrid can restore power to the healthy parts of the system (i.e., the parts to the left ofsource 1 and right of source 2) that are using DC switches. Moreover, this reconfigurationfeature can be used to implement the LIF location method in the system, even for challengingconfigurations.This chapter presents a method to measure the distance from a source-end PEC to a LIF.The proposed method uses the Embedded Impedance Detection (EZD) method introduced inPortions of this chapter have been published in• F. Paz and M. Ordonez, “Embedded Fault Location in DC Microgrid Systems Based on a Lock-In Amplifier,” in Proc.8th IEEE Int. Symp. Power Electronics for Distributed Generation Systems (PEDG), Apr. 2017, pp. 1–6.105tttovoibuilt in PPU modeusing reactive part lowers errorfast convergenceldˆrdˆldˆrdˆdˆfaultPPUPSsfdsfdlarge error for both methodsLR fRLRfRreconfiguration improves detection(a)(b)L, iLvfLdLRswitch 1 switch 2source 1 source 2f1sdf2sdL1sdL2sd1o,, i1o,v 2o,, i2o,v1o,v2o,vFigure 5.1: In (a) schematic of a DC system with two source converters, a line connectingthem is a resistive load (RL), and a fault closer to source 2; using the proposed LIF locationalgorithm, the distance to the fault can be estimated from either direction (ds1,f or ds2,f)which yields different error; in (b) a comparison of the outputs of the proposed LIF locationmethod using resistive and reactive parts (dˆr or dˆl) for both sources the one closer to the load(orange trace) and the one farther (blue trace); the proposed method turns the source-endpower electronics converter from power supply (PS) mode to power probe unit (PPU) modein the event of a LIF; in this mode, it injects a small reference signal and extracts dˆr and dˆl.this work to turn the source-end PEC into a Power Probe Unit (PPU) which in turn gathersthe location of the fault. The system is analyzed showing the different possible locations ofthe fault relative to the load and the source-end PEC, and its impact on the accuracy of themethod. The key benefits of the proposed technique are outlined in Fig. 5.1(b). The proposed106method benefits from the embedded nature of the algorithm, avoiding the need for externalhardware ➊, the ability to use the reactive part of the impedance reduces the error due to theload ➋, the fast convergence of the method can quickly locate the LIF, returning the source-end PEC to feed the system ➌, and, in a reconfigurable system, the configurations that yieldmore error can be avoided by changing the configuration of the system ➍. Increasing thereference frequency allows the influence of the error to be reduced when the reactive partis included. The limitations of the technique are explored, and a solution for reconfigurablesystems is proposed. The proposed method does not require high-speed communications.Simulations of the proposed method in different configurations are included. The sim-ulations show accurate measurements for beneficial configurations, as well as highlight theproblematic situations. Further validation of the proposed technique is included with anexperimental platform implemented with an industry-standard microcontroller and sensors.5.1 System ModelThis section presents a description of the system and the different possible locations of theLIF in relationship with the line and load. These configurations impact the effectiveness ofthe proposed technique and its modifications. The objective of the LIF location technique isto determine the distance to the LIF.The characteristics of the system, the load, and the LIF affect the effectiveness of theLIF location estimation technique. In many applications, the load (RL) is connected at theend of the wire coming from the load source, as shown in Fig. 5.2. The source-end PECproduces the output voltage and current (vo and io) for the load. In the event of a LIF, thevo drops significantly; for active loads (such as constant power loads, constant current loads,and those loads with some start-up procedure), this causes the load to disconnect.107source-end PECo, iov L, iLv+LIF)s(CfRrdsLdsfd fLdLRloadFigure 5.2: Diagram of the DC system for a LIF between the source and load.During normal operation, the value of RL can beRN ≤ RL ≤ ∞, (5.1)where RN is the nominal load of the PEC (lower RL trips the OCP). Any load with an RLlower than RN forces the source-end PEC to provide more than the maximum current.The Rf can also take different values. In the ideal LIF,Rf = 0. (5.2)In order for the fault to be a LIF, it needs to trip the OCP and therefore Rf is0 ≤ Rf ≤ RN . (5.3)In practice, it is not expected that Rf takes a value close to RN .In the case outlined in Fig. 5.2, the LIF can only happen between the load and source.The line impedance between the source and load (ZsL) isZsL = dsL (ρ+ jωλ) , (5.4)108where dsL is the distance between source and load, ρ is the resistance per unit of distance, andλ is the inductance per unit of distance in the wire. When the LIF happens, the impedanceof the wire between the source and the fault (Zsf) isZsf = dsf (ρ+ jωλ) , (5.5)where dsf is the distance from the source to the fault. Also, the impedance of the wirebetween the fault and load (ZfL) is given byZfL = dfL (ρ+ jωλ) , (5.6)where dfL is the distance from the fault to the load. As expecteddsL = dsf + dfL. (5.7)In many DC systems, such as a ring DC microgrid there are multiple source-end PECswith lines feeding the loads. This allows reconfiguring the microgrid in the event of a LIFto re-energize the part that is not damaged. This is illustrated in Fig. 5.3, where severalsource-end PECs connected in a ring configuration through switches allow feeding either sideof the ring or both. In the event of a LIF, the system identifies which line is faulted andreconfigures the system to stop powering only this segment. This configuration where theline extends between two source-end PECs leads to a situation where the LIF can be locatedfurther away from the source-end PEC performing the location algorithm, introducing newchallenges.This configuration presents different characteristics for the LIF location problem, as out-lined in Fig. 5.4. This is especially challenging if the load is not smart enough to disconnect109ring DCmicrogridrestored systemfaulted segmentFigure 5.3: Diagram of a reconfigurable ring DC microgrid; in the event of a Low ImpedanceFault (LIF), the faulted segment can be isolated and power is restored to the remainingsegments; this reconfiguration can be used to locate the LIF more reliably.o, iovL, iLv+LIF)s(CfRrdsource convertersfdsLd fLdLRloadFigure 5.4: Diagram of the DC system when the distance to the LIF is more than the distanceto the load.in the event of a LIF. In the event of a LIF, part of the line and the load are in parallel,distorting the measurement of the distance.Finally, if the system is reconfigurable, as indicated in Fig. 5.3, the location estimation canbe made using the other end of the line. This is illustrated in Fig. 5.5; by closing switch 2 andopening switch 1, a LIF condition of the type shown in Fig. 5.4 can be modified to look like110L, iLvfLdLRswitch 1 switch 2source 1 source 2f1sdf2sdL1sdL2sd1o,, i1o,v 2o,, i2o,vFigure 5.5: In the event of a Low Impedance Fault (LIF) in a reconfigurable system, theswitches can be used to take the system to a configuration that can be used to more accuratelylocate the LIF; by connecting switch 2 instead of switch 1, the system can be taken to aconfiguration where the LIF is between source and load.LIF location methodLIALIAoiovri)ksTrpifsin (2rArx/ρ1/λ1rpif2/1rdˆldˆEZDICFigure 5.6: Diagram of the proposed LIF location algorithm using the Embedded ImpedanceDetection (EZD) method; two estimations can be extracted: one from the resistance (r) andanother from the reactive part (x).the configuration in Fig. 5.2. The proposed method and the error in different configurationsare presented in the next section.5.2 Proposed LIF Location MethodA schematic of the proposed LIF location method is presented in the Fig. 5.6. The methoduses the proposed EZD method to turn each of the PECs in the system into a PPU that canmake an estimation estimation of the distance to the LIF. The EZD outputs two measure-111ments: the resistance (r) and the reactive part (x), given by (2.55) and (2.55)r =vd id + vq iqi2d + i2q, , (5.8)x =vq id − vd iqi2d + i2q, . (5.9)Two estimations of the distance from the PEC to the LIF (dsf) can be made from outputsof the EZD methoddˆr =rρ, (5.10)dˆl =x2pifrλ, (5.11)where fr is the frequency of the injected reference signal from the LIA. The relative error ofeach of the estimations is given byedr =∣∣∣∣∣ dˆr − dsfdsf∣∣∣∣∣ , (5.12)edl =∣∣∣∣∣ dˆr − dsfdsf∣∣∣∣∣ . (5.13)This error depends on the relative location of the source, load, and LIF, as well as the valuesof these magnitudes.5.2.1 LIF Before LoadThis condition corresponds to that shown in Fig. 5.2, where dsf is lower than dsL. In thiscase, the impedance measured by the source-end PEC using (5.8) and (5.8)z = r + jx = dsf (ρ+ j2pi fr λ) +11Rf+ 1RL+dfL(ρ+j2pi fr λ). (5.14)112Considering that dsL = dsf + dfL, (5.14) can be written asz = r + jx = dsf (ρ+ j2pi fr λ) +11Rf+ 1RL+(dsL−dsf )(ρ+j2pi fr λ). (5.15)The estimation based on resistance is then given bydˆr =re(z)ρ= dsf +re(11Rf+ 1RL+(dsL−dsf )(ρ+j2pi fr λ))ρ, (5.16)and the estimation based on the reactive part is given bydˆl =im(z)2pifrλ= dsf +im(11Rf+ 1RL+(dsL−dsf )(ρ+j2pi fr λ))2pifrλ. (5.17)The second terms of (5.16) and (5.17) define the absolute error in the estimation of the valuesintroduced by each method. Using (5.12) and (5.13), the relative errors for this configurationare are given byedr |Rf=0 =∣∣∣∣∣∣∣∣re(11Rf+ 1RL+(dsL−dsf )(ρ+j2pi fr λ))ρdsf∣∣∣∣∣∣∣∣, (5.18)edl |Rf=0 =∣∣∣∣∣∣∣∣im(11Rf+ 1RL+(dsL−dsf )(ρ+j2pi fr λ))2pifrλdsf∣∣∣∣∣∣∣∣. (5.19)Some particular cases are of interest for the error evaluation:• If Rf = 0 or very close, then both (5.18) and (5.19) yield zero error, as the term 1/Rfbecomes infinity and nullifies the error. This makes intuitive sense, as a perfect shortcircuit would eliminate the effect of anything after the LIF in Fig. 5.2.113• If the load is smart enough to disconnect after the LIF (RL →∞), then errors becomeedr |RL→∞ =∣∣∣∣re (Rf)ρdsf∣∣∣∣ , (5.20)edl |RL→∞ =∣∣∣∣ im (Rf )2pifrλdsf∣∣∣∣ = 0. (5.21)In this case, edr depends only on Rf and dsf (worse for LIFs that are closer to thesource-end PEC), but edl is always zero.• If the estimation is performed using fr = 0, that is, using the DC values instead of theLIA, there is no opportunity to measure dˆl and edr is given byedr |fr=0 =∣∣∣∣∣∣∣∣re(11Rf+ 1RL+(dsL−dsf )ρ)ρdsf∣∣∣∣∣∣∣∣, (5.22)which still depends on Rf , RL, and dsf .• If the estimation is performed using a very high fr (fr →∞), the errors areedr |fr→∞ =∣∣∣∣re (Rf )ρdsf∣∣∣∣ , (5.23)edl|fr→∞ =∣∣∣∣ im (Rf)2pifrλdsf∣∣∣∣ = 0. (5.24)After considering the particular cases, a more general expression of the error can be analyzed.With no particular condition, edr is given byedr =Rfρdsf(RL + (dsL − dsf)ρ)(Rf +RL + (dsL − dsf)ρ) + ((dsL − dsf)2pifrλ)2(Rf +RL + (dsL − dsf)ρ)2 + ((dsL − dsf)2pifrλ)2 . (5.25)Since (5.25) has the term that depends on fr in the numerator and denominator in thesame power, the expression levels off for higher frequencies. This means the error does not114significantly improve by increasing fr. On the other hand, edl is given byedl =R2f (dsL − dsf)dsf((Rf +RL + (dsL − dsf)ρ)2 + ((dsL − dsf)2pifrλ)2) , (5.26)which shows two main benefits: the error reduces with the square of Rf (which is expected tobe small), and it has f 2r only in the denominator. By increasing fr, it is possible to improvethe estimation of the measurement significantly.5.2.2 Load Before LIFThis condition corresponds to that shown in Fig. 5.4, where dsf is greater than dsL. In thiscase, the impedance measured by the source-end PEC using (5.8) and (5.8)z = r + jx = dsL (ρ+ j2pi fr λ) +11RL+ 1Rf+dfL(ρ+j2pi fr λ). (5.27)The estimation based on the resistance yieldsdˆr =re(z)ρ= dsL +re(11RL+ 1Rf+dfL(ρ+j2pi fr λ))ρ, (5.28)and the estimation based on the reactive part is given bydˆl =im(z)2pifrλ= dsL +im(11RL+ 1Rf+dfL(ρ+j2pi fr λ))2pifrλ. (5.29)Equations (5.28) and (5.29) show that, unlike the case where the LIF is located before theload, the first term of each equation is not the correct distance (dsf). If the load is smartenough to disconnect, then (5.28) and (5.29) return to (5.16) and (5.17) and the error is only115present in the dˆr, and is proportional to Rf . In other cases, the error is given byedr =∣∣∣∣∣∣∣∣∣∣∣dsL − dsf +re 11RL+ 1Rf+dfL(ρ+j2pi fr λ)ρdsf∣∣∣∣∣∣∣∣∣∣∣, (5.30)edl =∣∣∣∣∣∣∣∣∣∣∣dsL − dsf +im 11RL+ 1Rf+dfL(ρ+j2pi fr λ)2pifrλdsf∣∣∣∣∣∣∣∣∣∣∣. (5.31)Considering that dsf = dsL + dLf , then the error is given byedr =∣∣∣∣∣∣∣∣∣∣∣−dLf +re 11RL+ 1Rf+dfL(ρ+j2pi fr λ)ρdsf∣∣∣∣∣∣∣∣∣∣∣, (5.32)edl =∣∣∣∣∣∣∣∣∣∣∣−dLf +im 11RL+ 1Rf+dfL(ρ+j2pi fr λ)2pifrλdsf∣∣∣∣∣∣∣∣∣∣∣. (5.33)These equations show that, when the LIF happens after the load, the error is not compensatedby fr, even when Rf = 0. This is true for both the resistive and reactive estimations andpresents a limitation to the method. However if the system has the ability to reconfigure anduse the other PECs to probe, both directions can be tested and the LIF can be located byreducing the circuit in Fig. 5.4 to that of Fig. 5.2. The masking of the resistance is a commonissue in many applications of LIF location, by making the LIF location algorithm a firmwareupdate to the PECs in the system, moving the location equipment is avoided thereby reducing116the repair times and cost. Even when the error is increased for the condition where the loadis located before the fault and the system is not reconfigurable, the proposed method stillprovides a better solution than looking through the whole line.5.3 Simulation ResultsIn this section, computer simulations of the proposed LIF location method are presented todemonstrate the behavior of the proposed LIF location technique. The simulated circuit ispresented in Fig. 5.7 in which the source-end PEC is modeled as a buck converter, normalizedfor generality, and the load is presented as a resistive load. The PEC is controlled usingstandard PI control methods with a current limit for the injection in LIF-location mode (lowvoltage). The simulations neglect the switching behavior for clarity. Three different LIFcases are simulated, related to the different scenarios discussed in the previous section, inorder to validate the errors introduced and the capability of the system: 1) a short circuitLIF before the load, 2) a short circuit LIF after the load, and 3) a LIF with a larger Rf afterthe load. In all these cases, it is assumed the load is not smart enough to disconnect fromthe system during the LIF because this is the worst case scenario.The parameters of the circuit are presented in Table 5.1, in the normalized domain. Theρ and λ of the line are listed normalized and per meter. The reference signal is injected inthe current control loop, as the converter is working current injection mode.Figure 5.8 presents the simulation results for Case 1 (a short circuit at a short distancefrom the source). After the LIF, the location method injects current with the referencesignal. The proposed EZD method outputs the resistive (rn) and reactive (xn) part, that,when combined with the configured parameters (ρ and λ), allow estimating the distanceaccurately to the LIF (dLIF ). The two estimations are shown: the one calculated using theresistance (dr), and the one calculated using the inductance (dl). As can be seen, the results117bCbLbLiovoiDQgSiVcase 1 case 2 case 3ov10 km20 km30 km40 kmfRDC/DCLRFigure 5.7: Schematic of the simulated circuit; the load is connected in the middle of the lineand is not disconnected after the Low Impedance Fault (LIF); three cases are presented atdifferent distances and with a different LIF resistance (Rf).Table 5.1: Simulation Circuit ParametersParameter ValueCb,n 1/2piLb,n 1/2pifo = 1/√LC 1Zo =√L/C 1V ∗o,n 1D∗ 0.5fsw 15RL,n 1I∗max,n 2ρ 1e− 5λ 1e− 6fs 4fswfr fo/5show the accuracy of the method for this scenario. The accuracy of the measurement isrelated to zero Rf and the fact that the LIF happens before the load.118)ntnormalized time (0 1 2 3 4 5normalizedvoltage )n,inv¤t(normalizedmeasured)nlinductance(normalizedmeasured)nrresistance(00.005.010.000.000.000.100.100.200.200.3oiov0 km.= 10rd→100.= 0nr0 km.= 10ld→01.= 0nlfaulto,n∗Vmax,n∗IFigure 5.8: Simulation results of the proposed LIF location method for a short circuit close tothe source-end power electronics converter; the top plot shows the output voltage and current(vo and io), while the bottom two plots show the outputs of the Embedded ImpedanceDetection (EZD) method; after the Low Impedance Fault (LIF), both the resistive andreactive part provide accurate estimations of the distance.The simulation results for Case 2 (a short circuit after the load) are presented in Fig. 5.9;in this case, the accuracy of the method is affected by the presence of the load in the path.Since the load is configured to remain connected, it introduces a parallel path (although arelatively high impedance one) for the scanning signal. Even including this, the low Rf allowsaccurate measurement.Finally, simulations for the Case 3 (a higher Rf after the load) are presented in Fig. 5.10.The results of the estimation show that the error of the measurement is significant, as ex-pected. This reflects the limitations of the method when the loads do not disconnect in the119)ntnormalized time (0 1 2 3 4 5normalizedvoltage )n,inv¤t(normalizedmeasured)nlinductance(normalizedmeasured)nrresistance(00.005.010.000.000.000.100.100.200.200.3oiov2 km.= 28ld→0282.= 0nl2 km.= 30rd→302.= 0nrfaulto,n∗Vmax,n∗IFigure 5.9: Simulation results of the proposed LIF location method for a short circuit fartherfrom to the source-end power electronics converter (after the load); the top plot shows theoutput voltage and current (vo and io), while the bottom two plots show the outputs of theEmbedded Impedance Detection (EZD) method; after the Low Impedance Fault (LIF), asRf is very small, the estimation is suitable for both methods.event of a LIF. In practice, most loads in DC systems are active and disconnect in the eventof a LIF, making the location more accurate.Table 5.2 shows a summary of the results of the simulations. As can be observed, thelocation of the LIF with respect to the load has a significant impact on the accuracy of dsf .The measured values coincide with the expected results from the error equations. The mostsignificant error is present when the load is located closer to the source than the LIF, as it wasexpected. This corresponds to the architecture limitations considered in the error analysisthat can be overcome when the system is operated in a reconfigurable architecture.120)ntnormalized time (0 1 2 3 4 5normalizedvoltage )n,inv¤t(normalizedmeasured)nlinductance(normalizedmeasured)nrresistance(00.005.010.000.000.000.100.100.200.200.3oiov8 km.= 50rd→508.= 0nr= 30 kmld→03.= 0nlfaulto,n∗Vmax,n∗IFigure 5.10: Simulation results of the proposed LIF location method for a short circuitfarther from to the source-end power electronics converter (after the load) and with a higherresistance; the top plot shows the output voltage and current (vo and io), while the bottomtwo plots show the outputs of the Embedded Impedance Detection (EZD) method; after theLow Impedance Fault (LIF), the higher Rf (20% of the nominal load) in combination withthe load produce very inaccurate results.Table 5.2: Simulation ResultsCase 1 Case 2 Case 3dsf [km] 10.0 30.0 40.0rn 0.100 0.302 0.508dˆr[km] 10.0 30.2 50.8edr [%] 0 0.66 27.00ln 0.0100 0.0282 0.0300dˆl[km] 10 28.2 30.0edl [%] 0 6.00 25.001215.4 Experimental ResultsThe simulation results in the previous section showed how the proposed LIF location methodcould measure the distance to a LIF in different conditions. To further validate the proposedmethod, an experimental set-up was built with similar characteristics to the simulated system,and it was used to measure different impedances. These experimental results confirm theability of the proposed EZD method to measure the low values are expected during the LIF,allowing the system to locate the LIF, using only the microcontroller and sensors built intothe PEC and no additional hardware.A picture and diagram of the experimental set-up is shown in Fig. 5.11. The powerplatform a is controlled by a standard C2000 microcontroller b . The three LIF cases areimplemented using the electronic load with three different channels c , d , and e in fault-test mode. The load of the system is f . The Rf is implemented using a lumped resistorsg . The inductances of the line are represented using lumped inductors of given values i .The parameters of the implemented platform are given in Table 5.3.The transient response of the different LIFs are presented in Figs. 5.12, 5.13, and 5.14 foreach of the LIFs presented. Since the lumped elements in the network are not proportionalto each other, it is not possible to determine an equivalent distance for the LIF. Instead,the results are analyzed based on the accuracy of the impedance measured, which wouldtranslate into the accuracy of the predicted distance. A summary of the experimental resultsand their error is presented in Table 5.4 when compared with the expected results. As canbe seen, the error remains below 5% for all the cases.As expected, the proposed method can use standard sensors to measure the impedanceaccurately. In a scenario where the wires were present, the outputs of the proposed systemcould be used to measure the distance to the LIF. The proposed method is still subject tothe errors that come from the location of the LIF in relationship with the load and Rf . The122a bc d e fgibCbLovoiabd ebLimicrontroller board(TMS320F28335)cinVfgi12 34Case 1 Case 2 Case 3Figure 5.11: Picture ad diagram of the experimental set-up implemented to test the proposedLIF location method. The power platform a is controlled by a standard C2000 microcon-troller b . The three LIF cases are implemented using the electronic load with three differentchannels c , d , and e in fault-test mode. The load of the system is f . The Rf is im-plemented using a lumped resistors g . The inductances of the line are represented usinglumped inductors of given values i .proposed method helps locate the LIF using a standard controller for the PEC but can besubject to error in certain situations. If the system is can be reconfigured to the simpleline topology, the LIF location accuracy is significantly improved compared with the ringarchitecture.123Table 5.3: Experimental Set-Up Configuration(a) Converter ParametersParameter ValueCb 4.75µfLb 2.108mHfo = 1/√LC 1.59 kHzZo =√L/C 21.3V ∗o 25D∗ 0.5fsw 20 kHzRL 24fs 80 kHzfr 250HzNp 4Ar 0.1%(b) Line Segment Parameters iSegment Resistance [Ω] Inductance [mH]1 1.089 4.262 0.260 2.573 0.111 2.04 0.080 1.36(c) Fault CasesCase Resistance [Ω] Switch Resistance [mΩ]1 − 17 c2 − 17 d3 5 g 80 eTable 5.4: Experimental ResultsCase 1 Case 2 Case 3rcalc 1.106 1.86 6.30xcalc 6.69 13.79 14.22rˆ 1.12 1.75 6.40xˆ 6.98 14.15 14.5er[%] 1.3 3.31 1.58ex[%] 4.3 2.61 1.97124fault= 25Vovovoir= 2Aoi98Ω.= 6x12Ω.= 1rˆxˆ ˆˆFigure 5.12: Experimental capture for the transient during a Low Impedance Fault (LIF) inthe location of Case 1. The estimated resistance is 1.1Ω, and the reactance is 6.98Ω.fault= 25Vovovoirx= 2Aoi75Ω.= 1r15Ω.= 14xˆˆˆˆFigure 5.13: Experimental capture for the transient during a Low Impedance Fault (LIF) inthe location of Case 2. The estimated resistance is 1.75Ω, and the reactance is 14.15Ω.5.5 SummaryIn this chapter, a new implementation of the impedance-based Low Impedance Fault (LIF)location technique, using the proposed Embedded Impedance Detection (EZD) method forDC systems, was proposed. The analysis of the systems, as well as the possible locations ofthe different elements (source, load, and LIF), were presented. The impact of the differentconfigurations in the error, as well as the parameters of the proposed method, were analyzed.125fault= 25Vovovoirx= 2Aoi5Ω.= 14x40Ω.= 6rˆˆˆˆˆFigure 5.14: Experimental capture for the transient during a Low Impedance Fault (LIF) inthe location of Case 3. The estimated resistance is 6.40Ω, and the reactance is 14.5Ω.By using the proposed EZD method, it is possible to turn each source-end PECs into a powerprobe unit (PPU), instead of using external hardware.The proposed LIF location method benefits from the high accuracy of the proposed EZDmethod and its ability to measure both the resistive and reactive part of the impedance, toaccurately locate the LIF. From the error analysis, it is observed that using the reactive partof the line to estimate the distance is less sensitive to error when the LIF is located betweensource and load. When the LIF is located after the load, the error in the method can bereduced by using a reconfigurable architecture to allow the system to measure from the otherdirection.The proposed method was validated through simulations, where the accuracy of themethod in both resistive and reactive parts was presented. The simulation results reflectthe predicted biases due to the load’s characteristics. The limitations of the method, namelyrelated to the LIF resistance and the presence of passive loads that do not disconnect fromthe system were shown. The proposed method was further validated by experimental cap-tures of several scenarios, showing the ability of the proposed algorithm to measure the faultimpedance when implemented with a microcontroller and standard sensors.126Chapter 6High-Impedance Fault DetectionHigh-Impedance Faults (HIFs) can be caused by many reasons and are hard to detectsince they draw a small amount of current that does not trip the Over Current Protection(OCP). However, detecting them in time is crucial to avoid fires, damage to equipment, andpossible harm to people. This task is challenging, and cannot always be achieved by a singlealgorithm, but for some particular cases, special techniques can be developed.One such case is the Point-to-point architecture, like the one illustrated in Fig. 6.1(a),where a Power Electronics Converter (PEC) feeds a a load that also has a PEC. A HIF inbetween the conductors (indicated by the red cross in the diagram) establishes a resistiveconnection between the conductors. This increases the output current without tripping theOCP.This chapter presents an algorithm to detect HIFs between conductors in a point-to-pointconnection. The algorithm relies on the use of the proposed Embedded Impedance Detection(EZD) to measure the incremental resistance (rinc) seen by the PEC. Based on the CPLnature of the load, its rinc decreases after a current increase, while a HIF is reflected in anincrease in rinc.A diagram of the two different transients, a load step-up and a HIF, and the proposedtechnique is presented in Fig. 6.1(b). The proposed method uses the measurement of thePortions of this chapter have been published in• F. Paz and M. Ordonez, “High-Impedance Fault Detection Method for DC Microgrids,” in Proc. 10th IEEE Int. Symp.Power Electronics for Distributed Generation Systems (PEDG), Jun. 2019, pp. 1–6.127load-end PECsource-end PECo, iov)s(LCL, iLv+HIF)s(CfRFrdrtttovoiovoihigh sensitivitysmall perturbationfast convergenceload change/HIFRsame ∆oisame ∆load changeHIFincrR(a) (b)Figure 6.1: In (a) a block diagram of a DC system feeding an electronic load through aline with a HIF; in (b) a comparison of the transient for a HIF (blue) as opposed to a loadincrease (orange); although the voltage and current (vo and io) show no difference in steady-state (leading to no difference in R), the incremental resistance (rinc) shows a clear differenceby moving in the opposite direction.output voltage and current (vo and io) to determine rinc as seen by the PEC. As opposedto the DC resistance (Vo/Io), which is the same for both events, detection based on rincusing the proposed EZD offers three key benefits: high sensitivity, due to the qualitativedifference between the fault and load r ➊, small reference injected ➋, fast detection whilekeeping the sampling frequency low ➌. Moreover, the proposed method is embedded in thePEC which adds the detection without additional hardware. The benefits and performanceof the proposed HIF detection method are validated using simulations showing the compar-ison for closely matched cases. Experimental results, implemented in an industry-standardmicrocontroller, are provided to assess the performance of the proposed strategy and itsfeasibility.1286.1 System ModelFigure 6.1(a) presents the system under study. The system uses a point-to-point connectionwhere the source-end PEC regulates the output voltage (vo) that is sent through a wire to theload-end PEC. The load-end PEC regulates its output voltage to supply the load, causing aConstant Power Load (CPL) behavior. During a HIF, the fault resistance (Rf ) is significant(higher than the nominal load), which causes the OCP not to trip in most conditions. Theline connecting the source-end PEC with the load-end PEC can be considered to have losses,modeled with a resistance distributed through the line (Rline). In the event of a HIF in somepart of the line, the Rline can be divided asRline = Rsf +RfL, (6.1)where Rsf is the resistance from source-end PEC to a fault and RfL is the resistance fromfault to load-end PEC.Fig. 6.2(a) shows a circuit schematic of the system for the DC operating point. For aCPL, the load current (IL) is given byIL =PLVL, (6.2)where PL is the CPL power and VL is the voltage at the terminals of the CPL. The incrementalbehavior of the CPL is given byrL = −V2LPL. (6.3)This is the inherent negative resistance of a CPL. This incremental model is presented inFig. 6.2(b).129oIfRoIoV=RoV LVLVLP=LICPL(a)(b)oi˜fRov˜ Lv˜CPLoi˜dovd˜=incrsfR fLRsfR fLRLPL2V−=LrFigure 6.2: In (a) the functional diagram of the system in its DC operating point, the DCresistance (RDC) is the ratio of Vo and Io; in (b) the incremental behavior of the systemunder a small perturbation, the incremental resistance rac is dvo/dio.The equivalent load (R), seen from the terminals of the source-end PEC, isR =VoIo, (6.4)where Vo and Io are the average vo and io. Both an increase in PL and a HIF cause Io toincrease; the difference cannot be distinguished from R. In other words: there is an increasein PL that yields the same ∆Io as a HIF of a given Rf ; therefore, R cannot be used as anindicator of the HIF.The incremental model shown in Fig. 6.2(b), the equivalent incremental resistance (rinc)seen from the source-end PEC is given byrinc =dvodio= Rsf +11Rf+ 1RfL+rL. (6.5)130LPLPoIoIoV=Roidovd=incrAL,P BL,Pmaxo,IARCinc,rAinc,rBinc,rLP∆LP∆=CR BRAo,IBo,I=Co,IOCPHIFABCoI∆load increase→0>incr∆HIF→0<incr∆Figure 6.3: Output current (Io) as a function of the load power (PL) under regular operationand during a fault; the DC resistance (RDC) seen from the source is the same for both casesbut the incremental resistance (rac) is different.The measurement of rinc shows different behavior for the transitions: for a HIF, Rf changesfrom infinity to a finite value (although a large one); for the load step-up, Rf remains atinfinity, but the rL becomes less negative.Figure 6.3 shows Io under normal operations as a function of PL in orange, and depicts thecurve, in a cyan trace, under a HIF of a given Rf . The lower axis shows R in a solid line andrinc in a dashed line for both cases. Two possible transitions are shown from A to B (loadincreases by ∆P ) and from A to C (HIF event). It can be seen that from measuring Io, Vo,and R it is not possible to differentiate the two events. However, rinc presents a completelydifferent behavior: while rinc,B > rinc,A, rinc,A < rinc,C.The observed difference is sensitive to the value of the fault resistance (Rf): as Rf in-creases, it becomes harder to distinguish a HIF from the regular operation. This is expectedsince a HIF with very high impedance is indistinguishable from no change at all. The varia-tion of the curves as a function of Rf is shown in Fig. 6.4.131oIoV=R↑fR↑fRmaxo,ILPLPoIoidovd=incr↑fROCPFigure 6.4: Effect of a higher fault resistance (Rf ) in the detected change; as Rf increases, itbecomes harder to distinguish the HIF from a load increment; for very high Rf the differenceis too small.6.2 Proposed HIF Detection MethodThe proposed HIF detection method is based on two key elements: using the proposed EZDmethod to measure the incremental behavior of the load, and defining a correlation betweenthe increment in io with a change in rinc. The simple block diagram of the proposed methodis shown in Fig. 6.5. As discussed in the previous section, it is possible to differentiate a loadincrement from a HIF by looking at rinc. Given the constant nature of the DC system, thisinformation is not readily available from vo and io and needs to be inferred somehow.The proposed method injects a reference signal to the duty cycle reference given bydr = Ar sin (2pifrTsk) , (6.6)132(a) (b)LIALIAHIF detection methodFFttttoioiovovincrincrri)ksTrpifsin (2rAov+ ˜oVMAF--incr∆1−z+ 0>1−z+ 0>oI oI∆0<incr∆0>incr∆0>oI∆0>oI∆oi˜+oIEZDICFigure 6.5: In (a) a block diagram of the proposed impedance-based HIF detection method.It is based on using the proposed Embedded Impedance Detection (EZD) method and cor-relating the change in rinc (∆rinc) with a change in Io (∆Io); in (b) a timing diagram of theproposed method showing the output voltage (vo) and current (io) and the changes during aload increase and a HIF, the rinc changes in both cases, but the proposed method only flagsthe HIF.where Ts is the sampling rate of the LIA and EZD, and fr is the reference frequency, Ar isthe amplitude of the reference. The incremental variables are given byio = Io + i˜o, (6.7)vo = Vo + v˜o, (6.8)iL = IL + i˜L, (6.9)vL = VL + v˜L. (6.10)Using the LIA as discussed in Chapter 2 the incremental behavior of the system can beextracted.133Using EZD and the expression in (2.55), the rinc measured from the terminals of thesource-end PEC is given byrinc =vd id + vq iqi2d + i2q, (6.11)where vdq and iiq are the direct and quadrature components of the LIA implemented toperform EZD. The algorithm then computes the difference between rinc between two stepsof the algorithm given by∆rinc[K] = rinc[K]− rinc[K − 1]. (6.12)It is important to note that K denotes the time-steps of the HIF detection algorithm, asub-rate of Ts. The time-step of the HIF detection algorithm has to be selected, consideringthat the system has reached a stable output, given that the transient can go through severalvalues.As some io circulates through Rf , an increase in io is a requirement for a HIF to havehappened. The change in io is calculated as∆Io[K] = Io[K]− Io[K − 1], (6.13)where Io is calculated using a MAF tuned to fr, which removes the reference signal. Thecalculated ∆Io is reflected in the second condition in the diagram of Fig. 6.5: ∆Io > 0.Using the extracted information, the HIF is determined to have occurred asF =1 if (∆rinc > 0) and (∆io > 0),0 otherwise.(6.14)134This simple criteria allows for accurate detection of the HIF, as long as the changes can beobserved by the available sensors.6.3 Simulation ResultsThe previous section presented the use of the EZD method to detect HIFs. The algorithmbenefits from the efficient and accurate calculation of rinc implemented using the proposedEZD, as well as the nature of the load connected, to differentiate a HIF from a load step-up. This section introduces the validation of the proposed technique through computersimulations. The simulations are presented in the normalized domain, for generality, andcorrespond to two transients that yield the same DC operating point. In other words, theproposed simulations represent similar transitions to those outlined in Fig. 6.3, where Io andVo are the same for both transients. Using the EZD, the difference between the two transientsis clear. The simulations neglect the switching ripple for clarity.Figure 6.6 presents the transient when there is a load increase. The simulations show theoutput voltage (vo) and load voltage (vL) in the top plot. The second plot shows the outputcurrent (io) and the load current (iL). Finally, the output of the EZD (rinc) is presentedalong with the DC resistance R, calculated as the ratio of the average values of vo and io.During the load step-up, io and iL remain the same, as there is no current that goes througha different loop (the parallel Rf is very large). As expected from the calculations, the ∆rincis positive (the rinc becomes less negative) due to the increase in power from (6.3). Thissimulates a transition from point A to B in Fig. 6.3, where the system does not have a HIF.For the simulations, the transient in rinc takes only one period of fr, as there is no need toaverage for noise.Figure 6.7 shows the transient when there is a HIF. During the HIF, io and iL are different:some of the current circulates through the HIF. As expected from the calculations, the ∆rinc135oisame ∆)ntnormalized time (0 1 2 3 4 5A B1.00.00.50.00.55.0-5.00.0normalizedvoltage)nv()ni(normalizedcurrentnormalizedmeasured)nrresistance(load increase→0>incr∆Rsame ∆load increase→Li=oiovLvLioiincrRFigure 6.6: Simulations during a load step up; the current in the output and the load (io andiL) are the same, as no current circulates through the HIF; the rinc reflects an increase (lessnegative).is negative (the rinc becomes more negative) due to the effect of Rf . This reflects a transitionfrom point A to C in Fig. 6.3 that the EZD HIF detection method should identify as a HIF.As can be observed, these transients, although they match precisely the DC behavior(having the same R) show a clear difference in rinc. The simulation results show clearlythe features of the proposed method: the difference in behavior between HIF and ∆PLis qualitative ➊; the injected signal is small ➋; the convergence of the method is fast ➌.Moreover, the proposed method is built into the converter, allowing the detection of the faultwithout any additional hardware.136ARsame ∆)ntnormalized time (0 1 2 3 4 51.00.00.50.00.55.0-5.00.0normalizedvoltage)nv()ni(normalizedcurrentnormalizedmeasured)nrresistance(ovLvoiLiincrRoisame ∆ fault→Li=6oiHIF→0<incr∆CFigure 6.7: Simulations during a load step up; the current in the output and the load (ioand iL) are different, as some current circulates through the HIF; the rinc reflects a decrease(more negative).6.4 Experimental ResultsThe simulation results in the previous section show the ability of the proposed method todifferentiate between a load increase and a HIF. This section presents further validationimplemented using a real microcontroller. The experiments show the ability of the proposedEZD method to distinguish the qualitative difference between a HIF and the load step-upand to do so with a small reference injection and fast convergence time. The experiment isimplemented using an industry-standard microcontroller, and practical sensors for the currentand voltage. The results in this section validate the implementation of the HIF detectionmethod in a real system.137a bc defbCbLovoiabdebLimicrontroller board(TMS320F28335)cinV f1 2CPLFigure 6.8: Picture and Diagram of the experimental set-up implemented to test the proposedHIF detection method; the proposed method can identify the load change (implemented withan electronic load) from a HIF (implemented with a resistance).The PEC a is controlledby the standard microcontroller board b , where the EZD-based HIF detection algorithmis implemented. The CPL is implemented using an electronic load d in CPL mode thatcan be externally controlled to step-up. Another channel of the electronic load is used togenerate the HIF c using the fault test mode. The line connection is implemented usingdiscrete components e and Rf can be changed using a discrete resistor f .A picture of the experimental set-up used for the validation is shown in Fig. 6.8. ThePEC a is controlled by the standard microcontroller board b , where the EZD-based HIFdetection algorithm is implemented. The CPL is implemented using an electronic load d inCPL mode that can be externally controlled to step-up. Another channel of the electronic load138Table 6.1: Experimental Set-up ParametersParameter ValueCb 470 nFLb 2.2 mHfsw 10 kHzVo 24VPL,1 24 W∆P 6 WRf 100Ωfs 40 kHzfr 1 kHzNp 2Ar 2.5%is used to generate the HIF c using the fault test mode. The line connection is implementedusing discrete components e and Rf can be changed using a discrete resistor f . The set-point of the CPL, the increment, and the value of Rf are selected to match the expectedtransitions such that they are indistinguishable from the DC operating point. The parametersof the implemented PEC are given in Table 6.1, they are selected to match the normalizedvalues in the simulations section. The load increment (∆P ) is 6W, while the Rf of 100Ωtakes 5.76W. The similarity between both the ∆P and the extra power drawn from Rfcauses two conditions to look very similar for the detection algorithm, presenting the samechallenge as in the simulations.Figure 6.9 shows an oscilloscope capture of the voltage and current (vo and io) from theprototype during a load step-up (corresponding to the simulated transient in Fig. 6.6). Theoutput of the proposed EZD method is captured using a DAC from the microcontrollerand then scaled correspondingly in the oscilloscope. The system starts from the normaloperating point A , where the load is 24W and transitions to a state B where the load is30W. During the transition, io increases and the output of the EZD algorithm, calculated139ovoioisame ∆A Bload increase→0>incr∆incr2.9 msFigure 6.9: Oscilloscope captures of the experimental set-up before and after the load change;the rinc, measured by the proposed algorithm and extracted using a DAC, reflects an increase(less negative).in the microcontroller, reflects an increase in rinc (less negative) from −24Ω to −19Ω, asit was expected from (6.3) ➊. The signal injected in the system is relatively small ➋ andcan be further reduced. The transient in rinc shows two peaks, corresponding to the twoperiods averaged by the EZD, which stem from the need to average in the presence of noise.Convergence is achieved after 5ms ➌. The proposed method is able to detect the change inthe load accurately using the sensors present in the PEC without adding cost.The transient during the HIF event is shown in Fig. 6.10 (matching the transient simulatedin Fig. 6.7). The system starts from the normal operating point A , where the load is 24Wand transitions to a HIF state C where an Rf of 100Ω is added in parallel. While thetransient in vo and io are very similar, and the steady-state values are precisely the same,the output of the EZD algorithm reflects a decrease in rinc (more negative), from −24Ω to−29Ω, as expected from the calculations outlined before ➊. The signal injected in the system140HIF→0<incr∆incrovoioisame ∆A C2.9 msFigure 6.10: Oscilloscope captures of the experimental set-up before and after the HIF; therinc, measured by the proposed algorithm and extracted using a DAC, reflects a decrease(more negative).is relatively small ➋ and can be further reduced. The transient in rinc shows the same twopeaks, corresponding to the two periods averaged by the EZD, which are the same as for thetransient load experiment. Convergence is also achieved after 5ms ➌.Further comparisons of the transient can be drawn from using the memory feature of theoscilloscope. The comparison is shown in Fig. 6.11. As can be seen, after the transition, thetwo transients diverge, even when the system has not reached steady state. This apparentdifference between the rinc during a load step-up and a HIF in the output of the proposed EZDbased method allows the differentiation of both events. The experimental captures shownin Figs. 6.9, 6.10, and compared in 6.11 clearly show the features of the proposed method:the difference in behavior between HIF and ∆PL is qualitative ➊; the injected signal is small(less than 2% of the DC voltage) ➋; the detection converges in less than 3ms ➌.141incrovoioisame ∆HIFLP∆2.9 msFigure 6.11: Comparison of the oscilloscope captures using the memory features of the scope;the voltage and current (vo and io) are very similar for both transients, but the rinc shows aclear departure.6.5 SummaryThis chapter presented an active High Impedance Fault (HIF) detection method, based onthe proposed Embedded Impedance Detection (EZD) method, for DC systems with ConstantPower Loads (CPL). The algorithm uses a small signal injected by the Power ElectronicsConverter (PEC) (through the control loop) to scan the incremental behavior of the systemand monitor the transitions. After an output current increase, which could be due to aload increase or a HIF, the HIF detection algorithm monitors the change in the incrementalresistance to determine the nature of the transient. The algorithm benefits from the negativeresistance of the CPL to differentiate it from the HIF condition.The combination of the EZD and the nature of the load produce four key advantages: 1)high sensitivity, due to the difference in sign of the change, 2) small reference injected to thesystem, due to the EZD features, 3) high convergence speed, and 4) embedded implementation142using the existing hardware. These features allow the proposed method to help preventequipment damage, as well as fires, and human harm at no additional cost.Simulation results showed the difference in readings from the method for HIFs and loadincrements that look equal in terms of DC operating point. The proposed algorithm isfurther validated with captures of the output of a microcontroller implementation. Theimplementation of the EZD method is computationally efficient without sacrificing accuracy,allowing it to be implemented in an industry-standard microcontroller without increasingcost. The experimental captures match the simulation results.143Chapter 7Maximum Power Point Tracking forPV SystemsOne essential function of a Power Electronics Converter (PEC) interfacing a renewableenergy source as in Fig. 7.1(a), such as a photovoltaic (PV) panel, is to ensure that itmaximizes the power transferred to its load. This Maximum Power Point Tracking (MPPT)task is usually challenging, as it is often the case that the actual operating conditions of therenewable energy source are not known. Since maximum power transfer is achieved when thesource and load impedances are matched, it stands that the proposed Embedded ImpedanceDetection (EZD) method can offer unique advantages in this field.A first approach would be to use a reference injected in the system and extract theimpedance as outlined before. This approach was explored in a preliminary version of thiswork, and it provided some benefits [6], such as accurate tracking and reduced perturbationsize; however, the power of the proposed EZD method allows this technique to be pushed tothe extreme: no reference injection at all.Portions of this chapter have been published in• F. Paz and M. Ordonez, “Fast and Efficient Solar Incremental Conductance MPPT Using Lock-In Amplifier,” in Proc.6th IEEE Int. Symp. Power Electronics for Distributed Generation Systems (PEDG), Jun. 2015, pp. 1–6.• F. Paz and M. Ordonez, “High-Performance Solar MPPT Using Switching Ripple Identification Based on a Lock-InAmplifier,” IEEE Transactions on Industrial Electronics, vol. 63, no. 6, pp. 3595–3604, Jun. 2016.144LIA-InCondInCondMPPno oscillation in steady-statefast start-upaccurate trackingtttdpvipvpslow start-upovershootconfusion during changessteady-state oscillationaccuracy vs. speed trade-offswitchingripplepvvpvi∗spvvpvi bCbLbCvbLibusCbusVmicrocontrollerControl+MPPTgS(a)(b)Figure 7.1: In (a) a block diagram of the proposed PV system using a boost converter tointerface a PV panel with a DC bus; the MPPT algorithm uses the information from thePV voltage and current (vpv and ipv) to determine an operating point that maximizes powertransfer, and (b) comparison between the proposed MPPT algorithm (orange trace) and thestandard InCond algorithm (blue trace); the Issues of the InCond show oscillations in steady-state slow start-up, confusion during irradiance changes, and a trade-off between speed andaccuracy. The proposed LIA-Based MPPT algorithm uses the switching ripple in the powerelectronics converter to accurately track the MPP with no perturbation, fast start-up andtracking due to the identification and the integral controller.This chapter presents an MPPT algorithm for uniformly irradiated PV cells to provideswitching ripple detection and tracking abilities in the presence of noise to allow high MPPTperformance. The core implementation of the EZD method is modified to use the switchingripple as the reference signal, executing the EZD algorithm every switching cycle.145The novel MPPT technique, based on the Lock-In Amplifier, takes advantage of theexisting switching ripple and provide adaptive-steps resulting in enhanced performance. Dueto its core resemblance to the Incremental Conductance (InCond) algorithm, the proposedtechnique is dubbed LIA-Based InCond. The three key desirable features of this algorithmare outlined in Fig. 7.1(b) in comparison with the standard InCond algorithm: Using theswitching ripple to measure the conductance allows for smooth operation in steady-state ➊,fast and accurate start-up ➋, and accurate tracking during the transients with no errors ➌.The benefits and performance of the LIA-Based InCond are validated using simulations tocarefully compare it with the traditional InCond, a benchmark algorithm widespread in theindustry and literature. Experimental results, implemented in an industry-standard micro-controller and real PV panels, are provided to assess the performance of the proposed strategyand its feasibility. A comparison is performed with other competing high-performance algo-rithms to show how this technique fares with resent advancements.7.1 System ModelThe behavior of the PV panel with the PEC can be analyzed from the block diagram inFig. 7.1(a). The DC bus is assumed to be able to take all the energy available from the PVpanel, therefore making it useful to have MPPT, and the selected PEC is a boost converter.The ipv and vpv are regulated by the PEC to maximize the power transferred. Two MPPTalgorithms are implemented in this chapter: the proposed LIA-Based MPPT and the standardInCond, as a comparison reference. The standard InCond algorithm is selected as a baselinecomparison since most modern MPPT algorithms are at some point compared with theInCond; by comparing with this algorithm, it is possible to extend the comparison to otherexisting algorithms and future improvements. In this work, the algorithms directly drive146(a) (b)pvvpvicathodeanodep-typen-typepnjunctionfrontcontactrearcontactglasslightpvIsRD shR pvipvvrrIFigure 7.2: Block diagram of the proposed PV system using a boost converter to interfacea PV panel with a DC bus; the MPPT algorithm uses the information from the PV voltageand current (vpv and ipv) to determine an operating point that maximizes power transfer.the duty-cycle (d) of the PEC, producing MPPT-oriented control algorithms that maximizespeed while reducing complexity by removing the need for voltage and current loops.7.1.1 Photovoltaic Panel BackgroundA PV cell is a semiconductor device that transforms photons arriving at its surface intoelectrical current. Figure 7.2(a) shows a simple diagram of a PV panel; the PV cell is, inessence, a diode exposed to light and, as expected, its behavior responds to the characteristicsof a diode. Figure 7.2(b) presents an equivalent behavioral model of a PV cell : the PV cellbehaves like a current source (Ipv), given by the amount of irradiance arriving at the cell(Irr); with a parallel diode (D), a parallel resistor (Rsh), and a series resistor (Rs).The voltage and current (vpv and ipv) of a PV cell are given byipv = Iph −(evpv+ipvRsnVT − 1)− vpv + ipvRsRsh, (7.1)147where n is the diode ideality factor (1 for an ideal diode), and VT is the thermal voltage givenbyVT =κTq, (7.2)where κ is Boltzmann’s constant, T is the absolute temperature, and q is the elementarycharge.A PV cell on its own produces a small amount of power; its voltage is approximately 0.6Vand its current is around 2A; for this reason, PV cells are built into panels of series/parallelconnections. A connection of Ms cells in series is called a string and it increases the voltageby Ms. Mp strings can be connected in parallel to increase the current. For Mp equal stringsof Ms series-connected cells, the characteristic V-I curve is given byipv = MpIph −MpI0(evpv+ipvRsMs/MpMsVT − 1)− vpv + ipvRsMs/MpMsRsh. (7.3)The power produced by the PV panel ppv is given byppv = ipv × vpv. (7.4)Fig. 7.3 presents the V-I and V-P curves of a PV panel . The output of the PV panels isaffected by Irr (which increases the current and the overall power) and by the temperature.The effects of Irr are shown in Fig. 7.3(a), while the effects of the temperature are shown inFig. 7.3(b).The maxima of (7.4) has to be found to operate the PV panel at the MPP. When thesystem operates at the MPP, the power characteristic has a zero derivativedppvdvpv∣∣∣∣MPP= 0, (7.5)148pvvpvppvvpvi↑rrI↑rrIpvvpvppvvpvi↑cellT↑cellT(a) (b)MPPSTCVMPPSTCVMPPSTCPMPPSTCISCSTCIOCSTCVOCSTCVMPPSTCVMPPSTCVMPPSTCPMPPSTCISCSTCIOCSTCVOCSTCVSTCMPPSTCMPPSTCMPPSTCMPPFigure 7.3: V-I and V-P curves of a PV panel under (a) different irradiance (Irr) levels at aconstant temperature (T ), and (b) different levels of T at a constant Irr.Expanding (7.5) for the V-I expressions, the condition can be stated asipvvpv∣∣∣∣MPP= − dipvdvpv∣∣∣∣MPP. (7.6)The left term of (7.6) is the equivalent load that the PEC presents to the PV panel, that is theDC conductance (G). The right term of (7.6) is the negative of the incremental conductance(−g) of the PV panel. As expected, g is negative for a PV panel (increasing vpv yields alower ipv). Therefore, the MPP condition can isG = −g. (7.7)This condition is represented in Fig. 7.4. The load line (whose slope is given by G) has to beperpendicular to the tangent line (whit a slope of −g) at that MPP. Keeping the PV panel149= 0pvvdpvpdMPPIMPPPpvvpvppvvpvvpviGg−pvvdpvid=g pvvpvv=Gg−=GGg−MPPMPPMPPVFigure 7.4: Characteristic behavior of the PV cell around the MPP: the MPP is characterizedby the equivalent load (G) being equal to the negative of the incremental conductance (g),which gives a flat V-P curve.working in this condition under changing environmental conditions is the task of the MPPTalgorithm.7.1.2 Standard InCond MPPT AlgorithmFigure 7.5(a) shows a flowchart of the standard InCond MPPT algorithm. The algorithmscans the I-V curve looking for the condition of (7.7). The estimated G isGˆ[K] =ipv[K]vpv[K], (7.8)150(a) (b)ENDInCondpvitpvvttgSMPPTTswf1]−K[pvv]K[pvv]K[pvv∆]K[pvi∆]K[pvi1]−K[pvi]K[d + 1]K[d]K[pv, v]K[pvi1]−K[pvi−]K[pvi] =K[pvi∆1]−K[pvv−]K[pvv] =K[pvv∆]K[pvv]K[pvi] =K[Gˆ]K[pvv∆]K[pvi∆] =K[gˆGˆg >ˆ−d] + ∆K[d+ 1] =K[d d∆−]K[d+ 1] =K[d]K[pvi1] =−K[pvi]K[pvv1] =−K[pvvyesFigure 7.5: In (a) a flowchart of the Incremental Conductance (InCond) algorithm; in (b) atime diagram of the InCond close to steady-state showing the PV panel voltage and current(ipv and vvp), and the switching signal (Sg) that drives the PEC; in order to determine thenext step, the algorithm needs to wait for ipv and vvp to reach steady-state, and when theMPP is found it toggles in a characteristic three-level operation all the time, in order to beable to detect a change in environmental conditions.where ipv[K] and vpv[K] are the current and voltage of the PV panel measured at a givenoperating point in step K. The estimated g is given bygˆ =ipv[K]− ipv[K − 1]vpv[K]− vpv[K − 1] . (7.9)With (7.8) and (7.9), the new operating point isd[K + 1] =d[K]−∆d if Gˆ[K] < −gˆ[K]d[K] + ∆d otherwise, (7.10)151where d[K] is the PEC’s duty-cycle and ∆d is the step-size of the algorithm. The selection of∆d and the time between MPP decisions (TMPPT ) has to be selected based on the applicationand is one of the disadvantages of the InCond algorithm.Figure 7.5(b) shows the timing diagram of the InCond algorithm. The algorithm waits forthe PEC to stabilize in the new operating point before making a new decision since this timedepends on the operating point, it has to be calibrated for the worst case (slowest response).This algorithm has several disadvantages that are inherent to its core nature: a) thecontinuous injection of a perturbation causes an oscillation in between three states thatreduces the overall efficiency of the PEC, b) the fixed ∆d and TMPPT create a trade-offbetween accuracy (given by a smaller ∆d) and speed (given by a larger ∆d) and a balance hasto be selected, c) since the PEC has to reach steady-state to obtain a valid measurement, theTMPPT is limited by the PEC’s speed further compromising the tracking, d) since changesin irradiance can happen in between samples, errors can happen in the calculation of gˆcausing deviations in the operating conditions, and e) the tracking of gradual changes in theirradiance is not accurate except when ∆d coincides with the optimal changing rate. Theproposed LIA-Based MPPT algorithm tackles those limitations.7.2 Proposed LIA-Based MPPTThe InCond algorithm is based on the estimation of G and g by the difference betweenadjacent operating points. However, a more accurate estimation can be obtained using theEZD method proposed in this work. The block diagram of the proposed LIA-Based MPPTalgorithm is shown in Fig. 7.6(a); it uses a MAF to extract the average values of vpv andipv to calculate G and uses two LIAs and the switching ripple injected by the PEC as thereference signal to measure g. A digital Integral controller (I(z)) is used to drive the difference152(a) (b)MAFLIApvi GMAFLIAgpvv)z(ILIA-InCondd,v1A,i1Apvi¯pvv¯pvitpvvttgSsw/f= 1MPPTT,v1A,i1A]K[pvi¯]K[pvv¯+ 1]K[d= 0k= 1k1−M=kFigure 7.6: In (a) a block diagram of the proposed LIA-Based InCond algorithms, it is basedon using the switching ripple along with a fast LIA and MAF to measure the G and g andmatch them using an integral controller (I(z)); in (b) a time diagram of the proposed MPPTalgorithm in steady-state showing the PV panel voltage and current (ipv and vvp), and theswitching signal (Sg), the amplitude of the fundamental components (A1,i and A1,v) are usedto extract g, while the averages are used to calculate G.between G and g to zero. A timing diagram of the operation of the proposed LIA-BasedMPPT algorithm is shown in Fig. 7.6(b).The use of a PEC to adapt the voltage/current characteristics of the PV panel to theload and do the MPPT process introduces an inherent ripple to the PV panel controlledby the switching frequency (fsw), the duty cycle (d), and the reactive components of theconverter (Cb and Lb). This ripple is usually lower than 1% of the DC voltage. Using thisripple to measure g is particularly convenient since: a) it is already in the system, so noadditional perturbation is injected, b) it is small compared with the standard step-size ofthe InCond algorithm (usual values for the InCond stepsize are around 10% of Voc), c) itis very fast, which allows for accurate tracking of changing environmental conditions (the153steps of the InCond are injected at intervals of 500 − 100ms, while the ripple has a periodof 0.01− 0.1ms), and d) it calculates the tangent line around the operating point, instead ofthe secant line between two operating point.Two characteristics need to be identified from vpv and ipv: the average value (¯ipv and v¯pv,to calculate G), and the amplitude of the fundamental components from ripple (A1,i and A1,vto calculate g). This is achieved by sampling the ripple and applying the MAFs to extract i¯pvand v¯pv in the switching cycle, and the LIAs to extract A1,i and A1,v. It is important to notethat, as opposed to the general formulation of the EZD method outlined in Chapter 2, theLIA, and impedance calculation are computed every switching cycle and without injectingthe reference signal. This makes the computation efficiency more critical than the case wherethe reference is injected at a lower frequency and the computations are performed only onceper switching cycle (and at a lower priority).Once G and g have been measured, the MPPT’s task is to keeping the difference betweenthem zero. While traditional InCond implementations check the difference and move theoperating point one step in that direction, a more straightforward implementation can bemade using an integral controller.7.2.1 DC Conductance MeasurementMeasuring the DC conductance (G) presented by the PEC to the PV panels is relativelysimple: measuring ipv and vpv, the mean value in a cycle is related to the DC load asG[K] =i¯pv[K]v¯pv[K], (7.11)where i¯pv[K] and v¯pv[K] are the outputs of the MAF used for oversampling after the ratetransfer block, as shown in Fig. 2.5 and discussed in Section 2.2.1. For an oversample of M154points per switching cycle, the MAF for each signal is given by (2.12)i¯pv[k] =1MM−1∑i=0ipv[k − i], (7.12)v¯pv[k] =1MM−1∑i=0vpv[k − i]. (7.13)Note the difference in the sample index between the MPPT step (K) and the oversamplestep (k). The averages are taken inside a single switching period subdivided in M samples,only one decision is made per switching cycle, as illustrated in Fig. 7.6(b).7.2.2 Incremental Conductance MeasurementThe calculation of the incremental conductance (g) is performed using the proposed EZDmethod. For this application, the reference signal that the LIA locks-into is the switchingripple introduced by the PECs. For this, two crucial modifications are introduced in thesystem: 1) the EZD block (in particular the LIAs) is moved to before the rate transition inthe signal chain in Fig. 2.5, and 2) no reference signal (r[k]) is generated.The switching ripple has a fundamental frequency of fsw. Therefore the reference frequencyis given byfr = fsw. (7.14)The number of samples in the reference is selected as the same as the oversample rateNs = M, (7.15)which makes the sampling timeTs =1Mfsw. (7.16)155This introduces the challenge to compute the LIA M-times per switching cycle, whichrequires much more computation than the injected reference approach. The efficient compu-tations introduced in Chapter 2 allow it to be performed. Moreover, the fact that the valueof g is only used once per switching cycle allows the equivalent impedance calculation to becomputed only once per cycle, avoiding additional products and divisions for discarded re-sults. Finally, for most applications that concern such a fast MPPT, the reactive componentsin the connections are minimal, and the phase shift can be neglected.Considering this, g is given byg[K] =A1,i[K]A1,v[K]. (7.17)If a significant phase shift is expected (due to long wires or high capacitance in the particularPV panels), (7.17) can be expanded using (2.60).The use of the embedded LIA allows the fundamental amplitude of the ripples to beextracted and combined to calculate g.7.2.3 MPP RegulatorOnce G and g have been measured, the objective of the MPPT algorithm is to make themmatch, such thatG− g = 0. (7.18)While the traditional InCond would compare the two values and step in one direction basedon the sign of the difference, a simpler solution can be implemented. By selecting the step-sizeto be proportional to the difference between the two resistances, the duty cycle isd[K + 1] = d[K] +KI(G− g), (7.19)156where d[K] is the duty-cycle in step K, and KI is the proportionality constant; this corre-sponds to a digital Integral Controller (I(z)) that regulates the difference between the twoconductances to be zero. The MPPT happens at switching speedTMPPT =1fsw=MTs. (7.20)In summary, the proposed LIA-Based MPPT algorithm uses a MAF and LIA to measureG and g accurately, and a simple I(z) achieving zero steady-state error and adaptive-stepcharacteristics. The implementation of the filters is computationally efficient, and the tuningof KI is simple, given its well-known behavior.7.2.4 Stability of the Proposed MPPTIn order to evaluate the stability of the proposed LIA-Based MPPT strategy a small signalmodel of the plant and controller around the MPP is developed. A block diagram of thesystem is presented in Fig. 7.7, where G is obtained by the MAF and g is obtained with theEZD method. The digital controller is evaluated once every MPPT sample period (TMPPT )indicated by the index K. The new duty cycle d[K] is determined by the integral controllerI(z) to produce the adaptive-step and passed through the Zero-Order-Hold to the continuoustime domain. The DC/DC PEC and PV panel are modeled by Hdv. It is important to notethat the sample time of the MAF and LIA Ts is M-times smaller and indicated by the indexk; the output of the filters is evaluated only once per MPPT cycle resulting in a cycle averageand avoiding the interaction between the filters and the control loop.The small signal averaged transfer function of the PEC around the MPP is given byHdv(s) =−VlinkLbCbs2 + LbGMPPs+ 1, (7.21)157MAFMAFLIALIAsTMPPTT+)z(I ZOHdpvvpvi]K[e]K[G]K[g]K[dPEC−Figure 7.7: Block diagram of the LIA-based MPPT algorithm with the control loop toevaluate stability.where GMPP is the DC conductance at the MPP and Vlink is the voltage of the DC bus. Theerror signal (e) is given by the MPP criteria given in (7.7) and it can be re written ase =ipvvpv+dipvdvpv. (7.22)A linearization of e around the MPP is given bye(vpv, ipv) ≈e(VMPP , IMPP )++∂e(vpv, ipv)∂vpv∣∣∣∣∣VMPP ,IMPP(vpv − VMPP )++∂e(vpv, ipv)∂ipv∣∣∣∣∣VMPP ,IMPP(ipv − IMPP ), (7.23)And considering the approximation of ipv around the MPP isipv ≈ 2IMPP −GMPPvpv, (7.24)158the e signal can be estimated ase(vpv, ipv) ≈ 2GMPP − 2GMPPVMPPvpv. (7.25)The small-signal, averaged e is given byeˆ(vpv, ipv) ≈ −2GMPPVMPPvˆpv. (7.26)The change in the duty cycle is given bydˆ(z) = −2(GMPPVMPPvˆpv)(KITMPPTz − 1), (7.27)and after the ZOH, the continuous time duty-cycle is given bydˆ(s)vˆpv(s)= −2(GMPPVMPP)(KITMPPTesTMPPT − 1)(1− e−sTMPPTsTMPPT). (7.28)The time delay esTMPPT can be approximated by Taylor’s expansion as (1 − sTMPPT ). Thismodel yields the following expression for the voltage-to-duty-cycle transfer functiondˆ(s)vˆpv(s)= −2(GMPPVMPP)(KI(1− sTMPPT )s). (7.29)The characteristic equation is given byH(s) = 1 + 2(KIGMPPVlinkVMPP)(1− sTMPPTLbCbs3 + LbGMPPs2 + s). (7.30)The range of stable values for KI depends on the system parameters as well as TMPPT asexpected. Figure 7.8 presents the bode plot for the simulated system parameters; it shows1591 10 100 1000 10000 100000s]/[radω90−180−270−[dB]|)jω(H|50050−100−150−)[deg]jω(H◦= 45P.M.s/= 30 rad0 dBωs/= 550 rad◦180−ω5 dB.= 47G.M.Figure 7.8: Frequency response of the system with the proposed LIA-based MPPT indicatinggain margin (GM) and phase margin (PM) for stability.the Gain and Phase Margins available for the system. The range of stable values for KI ineach application can be determined using this model.7.3 Simulation ResultsThe previous section introduced the proposed LIA-Based InCond algorithm. This algorithmbenefits from the fast and efficient computation of the DC and incremental conductances (G,and g) using the proposed EZD method, and the impedance matching characteristic of theMPPT process to produce a novel MPPT algorithm with desirable characteristics. Computersimulations are performed incorporating the proposed algorithm and comparing against theInCond to validate the outlined claims.The simulated model of the system consists of a PV panel connected to a constant DCbus through a boost converter and the MPPT controller to determine the duty cycle of160Table 7.1: Simulation Transients Implemented to Test MPPT AlgorithmsLabel Initial Irrr [kWm−2] Final Irr [kWm−2] Speed [kWm−2s−1]A 0.6 1.0 40B 1.0 0.3 −70C 0.3 1.0 7D 1.0 0.3 −7the converter, as shown in Fig. 7.1(a). The MPPT and control block implement eitherthe proposed or the standard method. The analog stages and quantization of ADC areimplemented in the model to better reflect the behavior of the platform and its possibleshortcomings.The results of the simulations are presented in the normalized domain, where the normal-ization factors are the MPP current, voltage, and power in standard test conditions (IoMPP ,V oMPP and PoMPP ). The fsw is set to 10 kHz and fs to 80 kHz which makes the order of theMAFM =fsfsw= 8. (7.31)Different slopes are considered during the simulation to validate the ability of the pro-posed algorithm to track different transients. The details of the transients implemented arepresented in Table 7.1, each transient is assigned a label ( A , B , C and D ) to track themthrough the different simulation captures and domains.Figure 7.9 presents the simulation results for the standard InCond algorithm. The stan-dard InCond presents a slower start-up time and oscillations in steady-state; the step-sizeselection balances the tracking speed and accuracy and constitutes a trade-off between theseaspects. During the transients ( A , B , C , and D ), the algorithm can make the wrongdecision (increase d instead of decreasing it) based on the direction of the irradiance changeand the previous step-direction. Even when tracking in the correct direction, the InCondalgorithm is prone to overshoot if the tracking speed does not precisely match the irradiance161) [ms]ttransient time (0 200 400 600 8000.00.51.00.00.51.00.00.51.0PVpanelpower)pv,np()d()pv,ni(PVpanelcurrentconverterduty-cycleA B C D2m/MPP at 1000W2m/MPP at 600W2m/MPP at 300Wslowstart-up tracking mismatchovershootoscillation in steady-statetrade-off:accuracy vs. speedlarge error forlong transientsconfusion duringirradiance changeFigure 7.9: Simulations of the standard InCond for a start-up transient followed by the fourtransients A , B , C and D ; details of these transients are presented in the following figures.change speed. These oscillations, delays, errors, and overshoots contribute to reducing thetracking efficiency of the algorithm and are well-known limitations of the InCond algorithm.Figure 7.10 presents the simulation results for the proposed LIA-Based MPPT. The pro-posed LIA-Based MPPT algorithm solves all those issues effectively. Using the LIA and theinherent switching ripple of the PEC it is possible to produce smooth operation in steady-statemaximizing the extracted power ➊, the adaptive-step feature allows the quick and accuratestart-up of the system ➋, and the combination of both can clearly identify the changes inIrr and track them ➌. From Fig. 7.10, the benefits of the proposed LIA-Based MPPT areevident.A comparison of the transient tracking capabilities of both algorithms is presented inFig. 7.11 for the transients A , B , C and D in Figs. 7.9 and 7.10. The proposed LIA-162) [ms]ttransient time (0 200 400 600 8000.00.51.00.00.51.00.00.51.0PVpanelpower)pv,np()d()pv,ni(PVpanelcurrentconverterduty-cycle2m/MPP at 1000W2m/MPP at 600W2m/MPP at 300WA B DCFigure 7.10: Simulations of the LIA-Based MPPT for a start-up followed by the four tran-sients A , B , C and D ; the key benefits: the smooth operation in steady-state➊, the faststart-up ➋, and the accurate tracking of changing environmental conditions ➌ are indicated.Based MPPT keeps the tracking within 98% of the MPP during all the transients, while thestandard InCond deviates notably during the transient. While the transient in A shows ahigh tracking accuracy, this is due to the excellent match between the slope of the transientand the step-size. For transients where the slope is descending, such as B and D , themismatch is exacerbated by the confusion caused by the descent. During transient C , evenwhen the InCond chooses the correct direction, it overshoots by 10%. The proposed LIA-Based algorithm prevents all these shortcomings: tracking during all the transients is smoothand remains with 98% of the simulated MPP.The same transients can be observed in Fig. 7.12 in the V − I plane. The proposedMPPT has a superior performance operating over the optimal line while the standard InCondalgorithm deviates visibly from that optimal trajectory. The labels A , B , C , and D163C D) [ms]ttransient time () [ms]ttransient time ()pv,npPVpanelpower()pv,npPVpanelpower()pv,npPVpanelpower()pv,npPVpanelpower(400 450 500 600 650 700B210205200110105100) [ms]ttransient time ( ) [ms]ttransient time (0.00.51.00.00.51.00.00.51.00.00.51.0MPP MPPMPPA MPP2m/600 to 1000 W 2m/1000 to 300 W2m/300 to 1000 W 2m/1000 to 300 WFigure 7.11: Detail of the transients A , B , C and D simulated compared with the idealMPP and the 98% mark.indicate the trajectory of the InCond algorithm since the LIA-Based MPPT stays very closeto the optimal line. Transient D shows a drop of 23% in power output for the InCondcaused by the typical confusion (wrong decision during irradiance changes) of the standardInCond algorithm due to the overall power decreasing for a long period of time; the proposedLIA-Based algorithm does not present this problem, producing accurate tracking all the time.The selection of KI influences the transient effects in the same way as any control loop.The effects of this parameter for a range of 0.3 to 3 are shown in Fig. 7.13. Even when thewhole range of parameters produces stable behavior, the selection can lead to faster trackingor have overshoot when it is not correctly selected. The value of 2 was selected for KI forthese simulations.164ABCD2m/1000W2m/600W2m/300W5.10.15.00.0)pv,niPVpanelcurrent()pv,nvPV panel voltage (0.02.04.06.08.00.12.1LIA-MPPTInCond1MPP2MPP3MPPFigure 7.12: V −I plane representation of the transients A , B , C and D for the proposedLIA-Based MPPT and the Standard InCond algorithms.0 10 20 30 40204060803.= 0IK5.= 0IK0.= 1IK0.= 2IK0.= 3IK5.3 3.5 1.14 4.272% steady state±)[%]ddutycycle() [ms]ttransient time (0.0Figure 7.13: Influence of the selection of the integral gain KI on the tracking capabilities ofthe LIA-Based MPPT.Finally, a summary of the tracking efficiency (defined as the distance to the true MPP, inpercentage) of both algorithms during the complete simulation can be observed in Fig. 7.14.The curves show how the proposed MPPT keeps the tracking efficiency within 98% all thetime and within 99% in steady-state. The variations in the tracking efficiency have onecomponent for the proposed LIA-Based MPPT (the switching ripple) and an additionalcomponent for the InCond MPPT (the oscillation in steady-state). The tracking efficiency islower at lower irradiance since the step-size is constant and vMPP is not linearly dependent on1651009590trackingefficiency[%]) [ms]ttransient time (0 200 400 600 800LIA-MPPTInCond99%98%Figure 7.14: Tracking efficiency of the LIA-Based MPPT and the standard InCond duringthe simulation.the irradiance, leading to a proportionally more significant loss due to the variation at lowerirradiance. This is expected given the logarithmic dependence of vMPP with the irradiance.The using the standard InCond result in lower tracking efficiency, especially during thetransients where it goes below the top 10%.7.4 Experimental ResultsThe simulation results in the previous section showed how the standard InCond algorithmhas a limited start-up speed (given by the fixed step-size and sample time), has oscillations insteady-state, and can make the incorrect decision when tracking transient irradiance profilesif those do not match the tuned speed. To further validate the proposed LIA-Based InCondalgorithm, an experimental set-up was built with similar characteristics to the simulatedsystem, and it was tested using fast transitions in Irr. These experimental results not onlyconfirm the benefits shown in the simulations but also show evidence that the proposedEZD method is able to measure g from the switching ripple using standard sensors andmicrocontrollers used in PECs.166Table 7.2: MPPT Experimental Set-up ParametersParameter ValueCb 470 nFLb 2.2 mHfsw 10 kHzfs 80 kHzfc 40 kHzM 8TMPPT,InC 2 ms∆dfast 2%∆dslow 1%Voltage Range 0 to 30 VCurrent Range 0 to 6 AFigure 7.15 shows a picture and a diagram of the experimental platform. Figure 7.15(a)shows the picture of the experimental set-up. Real PV panels are used to test such a high-speed algorithm since PV array emulators have limited bandwidth. As such, the custom-builtsolar chamber indicated by a contains two PV panels and lamps to generate controllableirradiance profiles. The DC source b driven in external mode by a signal generator c witha custom profile powers the lamps. The power platform d is connected in its input port tothe PV panels and its output port to the DC Load e , working in constant-voltage (CV)mode.Figure 7.15(b) shows a detailed picture of the power platform. The power stage f iscontrolled by a TI C2000 microcontroller g , typically employed to control PECs, to performthe MPPT process. A summary of the system parameters is presented in Table 7.2.Figure 7.16(a) shows an oscilloscope capture of the experimental set-up operating insteady-state to show the signals that are used to measure the impedance. The vpv andipv are measured using voltage and current probes, while ppv is calculated using a math oper-ation. The standard resolution, shown in the left, presents no oscillation in steady-state and167(a)(b)abcdefgbdcae(c)Controlled DC SourceElectronic DC LoadFunction GeneratorPower Converter PlatformControlBoardf Power BoardgFigure 7.15: Experimental set-up implemented to test the proposed LIA-Based MPPT algo-rithm against the classic InCond method; in (a) the overall picture of the set-up shows thechamber with the PV panels, illuminated by lamps controlled with a DC source to producethe desired profile, the PEC is connected to a DC load set in constant voltage mode; in (b)a picture of the PEC in the experimental platform, the controller is implemented in a TImicrocontroller; in (c), a block diagram of the experimental platform.168a smooth behavior, a desirable operating mode to maximize the energy extracted, withoutthe oscillation in steady-state that reduces the efficiency. The zoom-in section, shown to theright, shows the switching oscillation that is isolated by the LIA to extract the incrementalconductance. This small ripple is characteristic of the system, as opposed to the perturba-tion injected by the InCond algorithm to locate the MPP. The vpv and ipv are 180◦ separated(the maximum vpv happens at the ipv minimum), this is expected, given the nature of theV-I curve of the PV panel. The LIA can extract this small value rejecting the noise, whilethe computation time for this configuration was measured to be less than 0.6 µs per sample,which would allow further increasing fsw to hundreds of kilohertz.Fig. 7.16(b) shows an experimental capture of the proposed LIA-Based MPPT for irradi-ance transients. The irradiation of the PV panel changes during the transient; the dynamicsof the lamps limit the transient speed. The proposed LIA-Based MPPT stabilizes at theMPP showing no oscillations ➊, and can track the MPP in a smooth way ➌, this coincideswith the simulated results.Figures . 7.17(a) and (b) present experimental captures of the standard InCond with twodifferent steps-sizes (fast and slow). The InCond with a small tracking step produces smalleroscillations in steady-state but is not able to track the MPP during changing environmentalconditions, producing a lagging result. The InCond with a large step-size can track fasterbut has occasional overshoots and a much larger oscillation in steady-state which leads toreduced efficiency. Proper tuning leads to a balance for a given slope, panel, and oscillationbut the benefits are lost if the slope of the change in Irr is changed.7.5 Comparison Against Other MPPT MethodsThe comparison of the proposed LIA-Based MPPT algorithm was performed against thestandard InCond. This provides a reference point to compare with advanced MPPT algo-169switching ripple (identification signal)vertical x10horizontal x100MPPIMPPVMPPPpvipvvpvppvipvp(a)(b)Figure 7.16: In (a), the steady-state experimental capture of the proposed LIA-based MPPT,the zoom shows the small switching ripple used to identify g; in (b), the transient experimentalcapture of the proposed LIA-based MPPT, it benefits from the ➊ eliminated oscillation, thesmall-signal identification, and ➌ adaptive-step.rithms. Table 7.3 shows a comparison of the proposed LIA-Based MPPT with the resultsreported for other advanced MPPT algorithms. The selected algorithms are presented fortheir advanced features that allow for fast tracking and account for environmental changes.Since the tracking speed is highly dependent on the size of the PEC [183], the trackingtime is normalized to the resonance frequency of the PEC (for those documents that providesaid values). The selected algorithms use InCond versions with adaptive-step (such as theβ algorithm) or very high-speed controllers such as the sliding mode controller to increasethe speed. The proposed algorithm benefits from the single loop MPPT-oriented control170(a)(b)oscillation in steady-stateconfusion duringirradiance changetracking mismatchpvipvposcillation in steady-stateconfusion duringirradiance changeovershootFigure 7.17: Transient experimental capture of the traditional InCond algorithm with (a) asmall tracking-step, and (b) a large tracking-step.to increase the speed and the LIA and MAF to reduce the perturbation size allowing fast,accurate, and smooth behavior.Although the proposed technique presents higher computational demand for the samplingand filters compared with standard MPPT algorithms, the removal of the perturbation thatleads to higher steady-state tracking efficiency, the ability to identify the changes and theadaptive step-size obtained are a significant advantage over more simple algorithms. Typicaldigitally-controlled PECs sample several times per switching cycle to average the behavior ofthe current/voltage, and the processing power of industry-standard microcontroller (C2000)is capable of handling this load. The benefits of the proposed implementation, with smooth171Table 7.3: Comparison of the proposed LIA-Based MPPT algorithm, the InCond, and theresults reported in the literature for four advanced MPPT algorithmsAlgorithm Loops Perturbation τ ∗o NotesInCond (∆dfast) MPPT Fixed 742 Baseline comparison algorithmLIA-Based MPPT None 20 Tracking of transient slopes andsteps are optimized; higher com-putational costSliding Mode V + MPPT Fixed 405 Control is based on Sliding mode,while MPPT is based on InCond;Tracking of slope changes showsproblems as InCondLocus Based I + MPPT Fixed† 187 Requires off-site characterizationEmulated Resis-tanceV + MPPT Voc measured 74 Requires off-site characterizationand temperature characterization;requires periodic measurement ofVocβ MPPT Variable‡ 52 Requires off-site characterizationand temperature characterizationand irradiance tuning for β* Tracking time normalized to the converter resonance frequency τo = To/(2pi√LC)† Fixed step is used in steady-state, the large tracking is done with the Locus Based Method‡ Reduced until a minimum valueoperation and adaptive tracking speed become evident when compared with the standardMPPT algorithms.The additional computation required can present a limitation for very fast switching powerconverters (above 250 kHz, for the selected microcontroller) given that they will overflow thecomputation capabilities of the microcontrolle. However, for this scenarios, the g measuredat such frequency is not representative of the power transfer and will not yield the MPP2.2This high frequency is interesting however for other applications of the EZD for high frequency devices such as [184]1727.6 SummaryA new Maximum Power Point Tracking (MPPT) algorithm for uniformly irradiated photo-voltaic (PV) panels, based on the proposed Embedded Impedance Detection (EZD) method,was presented in this chapter. This algorithm, dubbed Lock-In Amplifier (LIA) based incre-mental conductance (LIA-InCond), used the inherent ripple in Power Electronics Converters(PEC) combined with the Moving Average Filter and the LIA to produce accurate trackingof the MPP, even in the presence of changes in the environmental conditions, without theneed of injecting any kind of disturbance to the system or including any additional sensors.An Integral controller was used to produce an adaptive-step feature for variable trackingspeed that allows for fast tracking, and its stability was studied based on the small-signalmodel.The combination of these characteristics produced: 1) smooth operation in the steady-steady state, maximizing the transferred power and removing the characteristic oscillationsof standard MPPT algorithms to achieve 99% tracking efficiency in steady-state, 2) fast andaccurate tracking during the start-up (40 times faster than the reference InCond method) and3) irradiance change identification and tracking for variable change rates (with 98% trackingefficiency during transients).The proposed algorithm was validated using computer simulations comparing against thestandard InCond algorithm as a benchmark. Further validation was performed with an ex-perimental platform, showing good agreement with the simulations and the feasibility ofimplementing the EZD method based on the switching ripple. A comparison of the results ofthe proposed MPPT algorithm was performed against several modern MPPT algorithms tohighlight the benefits and drawbacks. It was shown that the proposed LIA-InCond achieves40 times speed improvement over the traditional InCond, and between 2 and 20 times im-173provement over other fast methods, without the need of device specific tuning, removing theperturbation, and using a single control loop oriented to MPPT.The performance improvements provided by this simple method, based on the proposedEZD method, both in steady-state and during transients show the benefits of using theinherent ripple as the reference signal. The power of the proposed detection technique toisolate a minimal signal in the voltage and current and compute the impedance in real-timeallows this to be achieved.174Chapter 8Conclusion8.1 Conclusions and ContributionsThis dissertation introduced the Embedded Impedance Detection (EZD) method and ex-plored five critical applications for it: Maximum Power Point Tracking (MPPT) for Pho-tovoltaic (PV) systems, Adaptive Control for systems with Constant Power Loads (CPLs),Islanding Detection (ID), Low-Impedance Fault (LIF) Location, and High-Impedance Fault(HIF) Detection. The general analysis and design considerations of the proposed methodwere discussed in Chapter 2. That chapter introduced the fundamental building blocks: thesignal-processing chain, the reference generation, the signal extraction, and the computationof the impedance; and their design considerations.The core contribution of this work is the possibility of implementing online, real-time,impedance detection on every power converter in the system, using only the sensors alreadypresent in the converter. For this reason, Chapter 2 placed particular emphasis on theimplementation considerations to make the system as accurate and fast as possible, whilemaintaining a computationally efficient implementation. In the past, impedance detectionwas limited to dedicated, expensive, hardware in the laboratory environment, the proposedEZD allows it to be carried out inside all converters.The ensuing chapters discussed the characteristics of each application. Each chaptershowed the analysis of the problem, the use of the EZD as a solution, and its validation.The validation section included time-domain simulation, experimental results implemented175in real Power Electronics Converters (PECs), Hardware-In-The-Loop (HIL) co-simulations,and comparison with competing technologies, as appropriate.Overall, this work showed that real-time impedance detection can be implemented indistributed PECs with little to no cost and adds new capabilities to the system. It showsthat the EZD provides critical insights into the behavior of the DC system, such as real-timedetection of the incremental behavior of the load, otherwise masked by the constant voltageand current in the system. These new features increase the autonomy and modularity of thesystem by providing insights into more than just the DC operating point. This techniquecan be implemented in new designs, as well as in existing hardware, as it does not requirespecialized hardware.As the power and energy industry continues moving towards DC systems in pursuit ofhigher efficiency, reliability, and autonomy, the proposed EZD method offers an inside lookinto the state of the system. It provides solutions to some of the main gaps in DC systemsresearch.8.1.1 Improve Transient and StabilityChapter 3 introduced the use of the EZD method to characterize the equivalent load seenby a PEC and its incremental behavior to adapt the controller. The presence of non-linearconstant power loads (CPLs) introduces a negative incremental resistance that is highlydetrimental to the performance of power electronics systems. The traditional approach oftuning the PEC for the worst-case load is not always optimal, as the performance for mixedloads is unpredictable. The proposed algorithm uses the measured impedance to adapt thecontroller and obtain reliable performance for an extended variation of the load condition.The adaptive control technique introduced in this chapter allowed the real-time adjustmentof the controller coefficients to obtain a reliable response under changing load conditions.The simulations showed a comparison against the fixed controller schemes tuned for different176operating points showing better performance and matching the fixed cases for each condition.The proposed controller reduced overshoot from 15% to 2.5%, while maintaining convergencetime and extending the range of CPL that can be tolerated when compared with fixed tunedcontrollers.8.1.2 Islanding DetectionChapter 4 introduced the incremental impedance-based IDM in DC systems. Without thephase and frequency information present in AC grids, ID is challenging in DC systems.The proposed method used the small signal injected and detected the change between thegrid-connected scenario (very low incremental impedance) and the islanded scenario (largeincremental impedance). The method was studied for different types of loads, includingpassive loads, constant power loads, and constant current loads, showing very high sensitivityto the change. The proposed IDM allowed a smooth transition between islanded and grid-tiedmode, allowing flexible operation of the microgrid.The proposed method offers significant advantages when compared with the current meth-ods: Over-Voltage/Under-Voltage (UV/OV) and perturbation injection. Voltage based meth-ods fail in closely matched source-load conditions (which is a desirable operating mode, asit minimizes energy transactions). Perturbation injection methods inject increasingly largerdeviations to the set-point which deviates the system from equilibrium. The proposed IDMuses a reference signal of 1% the amplitude of the DC current and is able to detect theislanding event in less than the time constant of the output filter.8.1.3 Low-Impedance Fault LocationChapter 5 introduced the use of the EZD method for locating Low Impedance Faults (LIFs)in a DC microgrid using the distributed generators as Power Probe Units (PPUs). Once177a LIF is detected, and the faulted section of the system is isolated, finding the distance toa LIF in the system is essential to speed up repairs. The proposed method builds on theEZD to measure the resistance and inductance seen by the source-end PEC and estimatethe distance based on this. The use of the proposed method allows the use of the reactance,which is less sensitive to errors due to fault resistance, and the load resistance.In the event of a fault further away than the load, the proposed method benefits frombeing able to be embedded in all the source-end PECs in the system. The system can betaken to a configuration that reduces the error and use any of the distributed PECs.The adoption of the proposed EZD-based fault location technique removes the need forexpensive additional equipment, such as external PPUs or smart relays to locate the faultin the system. The use of external PPUs needs human intervention (and is therefore ex-pensive and time-consuming); smart relays are costly and require a communication lifelineto work. The proposed algorithm uses the same sensors present in the PEC and needs nohigh-speed communications link, making it more convenient to distribute the control of themicrogrid. Simulations show the algorithm at work for different fault scenarios, and thelocation capabilities are validated through experimental results.8.1.4 High-Impedance Fault DetectionChapter 6 introduced the use of the EZD method to detect High Impedance Faults (HIF) inpoint-to-point DC systems. As opposed to LIFs, HIFs do not trip the OCP and are oftenconfused with load changes. This can lead to HIF being maintained for a long time. Bydetecting the incremental impedance and comparing its change through time, it is possibleto differentiate a load change from a fault condition.The proposed method benefits from the nature of the active loads (having non-linear V-Icharacteristics) and the faults being mainly resistive. This difference yields a qualitativedifference between a change in the load (positive change) and a fault condition (negative178change). Simulations and experimental results showed the performance of the algorithm andits sensitivity.8.1.5 Photovoltaic Maximum Power Point TrackingChapter 7 presented a solution to the problem of tracking the Maximum Power Point of aPhotovoltaic panel, dubbed LIA-InCond, using the proposed EZD method. The proposedalgorithm goes beyond the standard implementation of the EZD method and the state of theart MPPT algorithms by avoiding injecting a reference signal at all. Instead, the LIA-InConduses the inherent ripple introduced by switching PECs as its reference signal and extractsthe incremental conductance every switching cycle. This reference signal requires computinga reduced version of the proposed EZD method several times per switching cycle.This proposed solution solves some of the main issues in MPPT algorithms and elimi-nates the need for voltage or current controllers in the PEC. The MPPT algorithm makesimpedance matching the primary goal through an integral controller, allowing for variablespeed tracking and accurate direction detection - a solution to two of the major drawbacksof most MPPT algorithms. The combination of these characteristics produced: 1) no oscil-lation in steady-state maximizing the transferred power , 2) start-up tracking 40 times fasterthan the standard InCond, and 3) irradiance change identification and tracking within 98%accuracy for variable change rates.The proposed algorithm was validated by performing computer simulations to show thebenefits and compare it with the standard InCond as a benchmark. Further validation wasperformed using an experimental platform showing not only the same advantages but alsothe feasibility of using the ripple as the scanning signal with standard microcontrollers andsensors. Finally, the performance and features of the PEC were compared against severalmodern algorithms proposed in literature showing the ability of the proposed method to179achieve above 98% tracking efficiency using only a single control loop, no additional sensors,no injected reference, and needing to device-specific tuning.8.1.6 Specific Academic ContributionsThe following publications introduced the Embedded Impedance Detection in a DC microgridscenario to characterize the equivalent load and improve the stability of the system:• F. Paz and M. Ordonez, “High-Accuracy Impedance Detection to Improve TransientStability in Microgrids,” IEEE Transactions on Industrial Electronics, vol. 64, no. 10,pp. 8167–8176, 2017.• F. Paz and M. Ordonez, “An Embedded Impedance Measurement for DC MicrogridsBased on a Lock-In Amplifier,” in Proc. IEEE 7th Int. Symp. Power Electronics forDistributed Generation Systems (PEDG), 2016, pp. 1–6.The work on using the embedded impedance detection to identify the islanding conditionin a DC microgrid for diverse sets of loads was published in:• F. Paz and M. Ordonez, “An Impedance-Based Islanding Detection Method for DCGrids,” in Proc. 9th IEEE Int. Symp. Power Electronics for Distributed GenerationSystems (PEDG), 2018, pp. 1–7.The work on low-impedance fault location was published in:• F. Paz and M. Ordonez, “Embedded Fault Location in DC Microgrid Systems Based ona Lock-In Amplifier,” in Proc. 8th IEEE Int. Symp. Power Electronics for DistributedGeneration Systems (PEDG), 2017, pp. 1–6.The work to use the embedded impedance detection to differentiate a high-impedancefault from a load step-up in a point-to-point DC system is accepted in:180• F. Paz and M. Ordonez, “High-Impedance Fault Detection Method for DC Microgrids,”in Proc. 10th IEEE Int. Symp. Power Electronics for Distributed Generation Systems(PEDG), Jun. 2019, pp. 1–6.The work on Maximum Power Point Tracking (MPPT) for Photovoltaic systems culmi-nated with the following publications:• F. Paz and M. Ordonez, “High-Performance Solar MPPT Using Switching Ripple Iden-tification Based on a Lock-In Amplifier,” IEEE Transactions on Industrial Electronics,vol. 63, no. 6, pp. 3595–3604, 2016.• F. Paz and M. Ordonez, “Fast and Efficient Solar Incremental Conductance MPPTUsing Lock-In Amplifier,” in Proc. 6th IEEE Int. Symp. Power Electronics for Dis-tributed Generation Systems (PEDG), 2015, pp. 1–6.These publications cover a preliminary implementation of the LIA-InCond using the standardEmbedded Impedance Detection Method, as well as the perturbationless version.Some publications resulted from collaborative research around photovoltaic systems, DCmicrogrid systems, and MPPT for other applications:• M. A. Bianchi, I. G. Zurbriggen, F. Paz, and M. Ordonez, “Improving DC MicrogridsDynamic Performance Using a Fast State-Plane-Based Source-End Controller,” in IEEETransactions on Power Electronics, vol. 34, no. 8, pp. 8062-8078, Aug. 2019.• M. Aliaslkhiabani, F. Paz, M. Ordonez, and L. Wang “Partial Shading Mitigation inPhotovoltaic Arrays using Shade Dispenser Technique,” in Proc. 10th IEEE Int. Symp.Power Electronics for Distributed Generation Systems (PEDG), 2019, pp. 1-5.• G. Bogado, F. Paz, I. Galiano Zurbriggen, and M. Ordonez, “Optimal Sizing of aPV and Battery Storage System Using a Detailed Model of the Microgrid for Stand-181Alone Applications,” in Proc. IEEE Applied Power Electronics Conf. and Exposition(APEC), 2019, pp. 1-5.• S. A. Arefifar, F. Paz, and M. Ordonez, “Improving Solar Power PV Plants UsingMultivariate Design Optimization,” IEEE Journal of Emerging and Selected Topics inPower Electronics, vol. 5, no. 2, pp. 638–650, 2017.• E. Serban, F. Paz, and M. Ordonez, “Improved PV Inverter Operating Range Using aMiniboost,” IEEE Transactions on Power Electronics, vol. 32, no. 11, pp. 8470–8485,2017.• E. Serban, F. Paz, and M. Ordonez, “PV Array Voltage Range Extension for Photo-voltaic Inverters Using a Mini-Boost,” in Proc. IEEE Energy Conversion Congress andExposition (ECCE), 2016, pp. 1–8.• R. Pen˜a-Alzola, D. Campos-Gaona, F. Paz, J. M. Morales, and M. Ordonez, “MPPTand Control Design of a Vienna Rectifier-Based Low Power Wind Turbine with ReducedNumber of Sensors,” in Proc. IEEE 7th Int. Symp. Power Electronics for DistributedGeneration Systems (PEDG), 2016, pp. 1–5.• I. G. Zurbriggen, F. Paz, and M. Ordonez, “Direct MPPT Control of PWM Convertersfor Extreme Transient PV Applications,” in Proc. IEEE Applied Power ElectronicsConf. and Exposition (APEC), 2016, pp. 386–391.• P. F. Ksiazek, I. G. Zurbriggen, F. Paz, J. M. Galvez, and M. Ordonez, “Reverse controlof solar power converters for modular telecommunications UPS,” in Proc. IEEE 36thInt. Telecommunications Energy Conf. (INTELEC), 2014, pp. 1–5.182• F. Paz, R. Pen˜a-Alzola, and M. Ordonez, “Time-Optimal Switching Surface for Pho-tovoltaic MPPT,” in Proc. 5th IEEE Int. Symp. Power Electronics for DistributedGeneration Systems (PEDG), 2014, pp. 1–5.8.2 Future WorkThis body of work opens many new lines of research. Some open problems that could beaddressed using the proposed EZD method include:• Investigating the use of the EZD for battery energy storage: Impedance is an indicatorof the State of Charge (SoC) and State of Health (SoH) of batteries. Online char-acterization is challenging, as it is highly sensitive to the chemistry of the battery,temperature, and aging; however, it can yield promising results.• Arc Fault detection and characterization: During an Arc Fault event, impedance in-creases rapidly and has a wide frequency spectrum. An extension of the EZD thatmonitors multiple frequencies would be needed to allow this application.• Extending Fault Detection and Location to other architectures: Extending the algorithmto work with different architectures (radial and interconnected) would allow it to workin different systems such as data centers and electric ships. This is challenging as theexistence of multiple paths can mask some of the effects.• Maximum Power Point Tracking for other renewable energy sources: the EZD-basedMPPT developed for photovoltaic systems can be extended to other systems such aswind and ocean turbines. Research needs to be carried out to implement impedanceanalogies for electromechanical systems.• Implementing the impedance detection in non-energy producing nodes: with the ad-vances in PECs, microgrid architectures that use PECs at different stages, such as183power routers and smart nodes, are becoming a possibility. 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Advanced monitoring and control of distributed DC systems : an embedded impedance detection approach Paz, Francisco 2020
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Title | Advanced monitoring and control of distributed DC systems : an embedded impedance detection approach |
Creator |
Paz, Francisco |
Publisher | University of British Columbia |
Date Issued | 2020 |
Description | Direct Current (DC) systems, made possible by power electronics technology, are becoming more prevalent due to their advantages when integrating renewable energy sources, energy storage, and DC loads. Microgrids and local area energy systems are instrumental to DC systems, and much progress has been made around them. However, DC microgrids face numerous challenges due to their decentralized nature, such as resource optimization, control, and protection. This thesis focuses on developing a core technology, an embedded impedance detection (EZD) method for DC systems, and its application to five critical challenges in DC systems. The proposed method uses a reference signal of minimal amplitude and high frequency, injected in the control loop of the power electronic converter, and a digital Lock-In Amplifier to extract the incremental behavior of the voltage and current around the DC operating point. These are used to calculate the incremental impedance, which is representative of the reactive part of the system as well as the nonlinear characteristics of the system. The proposed EZD method is applied to address five critical problems in today's DC systems: 1) adaptive control in the presence of active loads - to expand stability and improve transient response; 2) islanding detection - to detect the connection and disconnection of the utility grid and change controllers for autonomous operation; 3) fault location - to detect the distance to a fault and simplify the system restoration; 4) high-impedance fault detection - to accurately distinguish a fault condition from a load increase; and 5) maximum power point tracking of photovoltaic panels - to ensure efficient energy harvesting. For all these applications, the proposed EZD-based solution offers critical benefits and advantages, such as high sensitivity and accuracy at a low system disturbance and fast detection. The work presents a detailed analysis of the proposed EZD technique as well as considerations for its implementation in commercial microcontrollers, followed by simulations to illustrate its capabilities. The thesis also presents a detailed analysis of each DC system application and its particular considerations. The outlined benefits are supported by simulations and validated through experimental results using a real power electronics platform. |
Genre |
Thesis/Dissertation |
Type |
Text |
Language | eng |
Date Available | 2020-02-06 |
Provider | Vancouver : University of British Columbia Library |
Rights | Attribution-NonCommercial-NoDerivatives 4.0 International |
DOI | 10.14288/1.0388579 |
URI | http://hdl.handle.net/2429/73491 |
Degree |
Doctor of Philosophy - PhD |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
GraduationDate | 2020-05 |
Campus |
UBCV |
Scholarly Level | Graduate |
Rights URI | http://creativecommons.org/licenses/by-nc-nd/4.0/ |
AggregatedSourceRepository | DSpace |
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