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Efficient power and data converter circuits for RFID applications Kamalinejad, Pouya 2014

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Efficient Power and Data Converter Circuits for RFIDApplicationsbyPouya KamalinejadB.Sc., Electrical Engineering, University of Tehran, 2006M.Sc., Electrical Engineering, University of Tehran, 2008A THESIS SUBMITTED IN PARTIAL FULFILLMENTOF THE REQUIREMENTS FOR THE DEGREE OFDOCTOR OF PHILOSOPHYinThe Faculty of Graduate and Postdoctoral Studies(Electrical and Computer Engineering)THE UNIVERSITY OF BRITISH COLUMBIA(Vancouver)August 2014© Pouya Kamalinejad, 2014AbstractThe basic concept of radio-frequency identification (RFID) as a means of wirelessidentification of physical objects has existed for over half a century. However, thetechnology became economically feasible during the mid-90s mainly due toproliferation of low-cost integrated circuits. Since its emergence, RFIDtechnology has gained extensive attraction and has been used in numerousindustrial applications. To facilitate widespread deployment, RFID tags as thebackbone of such identification systems have to fulfil two general requirements,namely, low power consumption and small form factor. In this thesis, with anemphasis on power and area efficient architectures, efficient data and powerconverters as the two major building blocks of sensor-enabled RFID tags areinvestigated.In the context of data conversion, by using two low-power analog buffersinstead of the conventional binary weighted capacitive array, a low-power 8-bitsuccessive-approximation register (SAR) analog-to-digital converter (ADC) withan area efficient digital-to-analog converter (DAC) architecture is proposed.Furthermore, time-mode ADC as an alternative area and power-efficient structureis discussed and a highly linear, wide-input-range voltage-to-time converter(VTC) is presented and experimentally evaluated.In the context of efficient power converters, through optimizing the biasvoltage of the gate of switching transistors in a conventional differential rectifier,three high-efficiency RF rectifier architectures, namely, gate-boosted,auxiliary-cell biased, and quasi-floating-gate (QFG)-biased rectifiers areproposed. Furthermore, through dynamically adjusting the input capacitance, adual-band matching approach for RF rectifiers is presented. In a practicaliiapplication scenario, the incorporation of the proposed high-efficiency rectifiers incomplete wireless monitoring systems is briefly discussed.The proposed QFG-biased rectifier is incorporated and analyzed in a wake-upradio front-end. Also, backscattering method as a power efficient scheme duringthe transmit mode is studied in the context of biomedical implants. Furthermore,based on the techniques developed for enhancing the efficiency of the rectifiers,an ultra-low-power complementary metal-oxide-semiconductor (CMOS) voltage-controlled ring oscillator architecture is proposed.The proposed building blocks and systems, namely, ADC, rectifiers, wake-upradio structure, and voltage-controlled ring-oscillator architecture are designed ina 0.13-µm CMOS technology and their performances are verified through post-layout simulation and/or measurement results.iiiPrefaceI, Pouya Kamalinejad, am the principle contributor to all six chapters, except forChapter 4 (Section 4.2) where Kamyar Keikhosravy is the main contributor and forthis section, I have assisted him with the design of the test setup, measurement ofbackscattering scheme and preparing the manuscript for the dissemination of theresults.Kamyar Keikhosravy has assisted me with the design of the voltage-to-timeconverter of Chapter 2 (Section 2.4), the auxiliary-boosted rectifier of Chapter 3(Section 3.3), the QFG-boosted rectifier of Chapter 3 (Section 3.4), the dual-bandmatching technique of Chapter 3 (Section 3.6), the wake-up radio architecture ofChapter 4 (Section 4.1) and the ring-oscillator of Chapter 5 (Section 5.1).Reza Molavi has assisted me in the design of the voltage-to-time converter ofChapter 2 (Section 2.4), the dual-band matching technique of Chapter 3(Section 3.6) and the ring-oscillator of Chapter 5 (Section 5.1).Dr. Kenichi Takahata has provided technical assistance to the antenna stent forthe backscattering study of Chapter 4 (Section 4.2). He has also provided designinsight for the monitoring system of Chapter 3 (Section 3.7).Arash Zargaran-Yazd has assisted with the design of the measurement setupfor the backscattering study of Chapter 4 (Section 4.2).Dr. Michele Magno (a post-doctoral fellow at University of Bologna and ETHZurich) and Professor Luca Bennini (University of Bologna and ETH Zurich) haveassisted with the system-level design of the wake-up radio architecture of Chapter 4(Section 4.1).Professor Shahriar Mirabbasi and Professor Victor Leung, who co-supervisedthe research, have provided technical consultation and editorial assistance on theivmanuscripts.Below is the list of accepted and submitted journal and conference papers thatare resulted from this work:Refereed Conference Contributions1. K. Keikhosravy, P. Kamalinejad, A. Zargaran-Yazd, Kenichi Takahata andS. Mirabbasi “A Fully Integrated Telemonitoring System for Diagnosing In-Stent Restenosis,” to be presented at IEEE Biomedical Circuits and SystemsConference (BIOCAS), Laussane, Switzerland, October 2014.2. P. Kamalinejad, K. Keikhosravy, R. Molavi, S. Mirabbasi and V. C.M.Leung “An Ultra-Low-Power CMOS Voltage-Controlled Ring Oscillatorfor Passive RFID Tags,” IEEE International New Circuits and SystemsConference (NEWCAS), Trois-Rivie`res, Canada, June 2014.(Chapter 5. Section 5.1)3. P. Kamalinejad, K. Keikhosravy, R. Molavi, S. Mirabbasi and V. C.M.Leung “Efficiency Enhancement Techniques and a Dual-Band Approach inRF Rectifiers for Wireless Power Harvesting,” IEEE InternationalSymposium on Circuits and Systems (ISCAS), special session on CircuitalAspects of Emergent Application-Driven Wireless Power Transfer Systems,Melbourne, Australia. June 2014. (Chapter 3. Section 3.6,[1])4. P. Kamalinejad, K. Keikhosravy, M. Magno, S. Mirabbasi, V. C.M. Leungand L. Benini “A High-Sensitivity Fully Passive Wake-Up Radio Front-Endfor Wireless Sensor Nodes,” IEEE International Conference on ConsumerElectronics (ICCE), pp. 209-210, Las Vegas, USA, Jan. 2014.(Chapter 4. Section 4.1,[2])5. K. Keikhosravy, P. Kamalinejad, S. Mirabbasi, V. C.M. Leung “AWideband Unity-Gain Buffer in 0.13 µm CMOS,” IEEE InternationalConference on Electronics, Circuits and Systems (ICECS), Abu Dhabi,UAE, December 2013.v6. P. Kamalinejad, K. Keikhosravy, S. Mirabbasi and V. C.M Leung “ACMOS Rectifier with Extended High-Efficiency Region of Operation,”IEEE International Conference on RFID Technologies and Applications(RFID-TA), pp. 1-6, Johor Bahru, Malaysia, September 2013.(Chapter 3. Section 3.4[3])7. P. Kamalinejad, K. Keikhosravy, S. Mirabbasi and V. C.M Leung “AnEfficiency Enhancement Technique for CMOS Rectifiers with LowStart-Up Voltage for UHF RFID Tags,” International Green ComputingConference (IGCC), pp. 1-6 Arlington, USA, June 2013.(Chapter 3. Section 3.3,[4])8. K. Keikhosravy, P. Kamalinejad, S. Mirabbasi, K. Takahata and V. C.M.Leung “An Ultra-Low-Power Monitoring System for Inductively CoupledBiomedical Implants,” IEEE International Symposium on Circuits andSystems (ISCAS), pp. 2283-2286, Beijing, China, 19-23 May 2013.(Chapter 3. Section 3.7, [5])9. P. Kamalinejad, S. Mirabbasi and V. C.M. Leung, “An Ultra-Low-PowerSAR ADC with an Area-Efficient DAC Architecture,” IEEE InternationalSymposium on Circuits and Systems (ISCAS), pp. 15-18, Rio de Janeiro,Brazil, May 2011. (Chapter 2. Section 2.2, [6])10. P. Kamalinejad, S. Mirabbasi and V. C.M. Leung, “An Efficient CMOSRectifier with Low-Voltage Operation for RFID Tags,” International GreenComputing Conference (IGCC), pp. 25-28, Orlando, USA, July 2011.(Chapter 3. Section 3.2, [7])Refereed Journal Submissions1. P. Kamalinejad, C. Mahapatra, Z. Sheng, Y. L. Guan, S. Mirabbasi, and V.C.M. Leung “Wireless Energy Harvesting for Internet of Things,” Submitted.2. K. Keikhosravy, D. S. Brox, P. Kamalinejad, S. Mirabbasi and K. Takahata“An Ultra-Low-Power 35-nW Wireless Monitoring System for BiomedicalApplications,” Submitted.viTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiiGlossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviiiAcknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 RFID Technology Overview . . . . . . . . . . . . . . . . . . . . 11.2 RFID Classification . . . . . . . . . . . . . . . . . . . . . . . . . 41.2.1 RFID Frequency Bands . . . . . . . . . . . . . . . . . . . 41.2.2 RFID Power Delivery Methods . . . . . . . . . . . . . . 81.2.3 RFID Protocols . . . . . . . . . . . . . . . . . . . . . . . 101.3 Challenges and Motivation . . . . . . . . . . . . . . . . . . . . . 111.4 Summary of Contributions . . . . . . . . . . . . . . . . . . . . . 181.4.1 Proposed Ultra-Low-Power SAR ADC with anArea-Efficient DAC Architecture . . . . . . . . . . . . . . 181.4.2 Proposed Highly Linear Wide Input RangeVoltage-to-Time Converter . . . . . . . . . . . . . . . . . 19vii1.4.3 Efficiency Enhancement Techniques for Rectifiers . . . . 191.4.4 Proposed Dual-Band Approach for Wireless PowerHarvesting . . . . . . . . . . . . . . . . . . . . . . . . . 211.4.5 Proposed High-Sensitivity Fully Passive Wake-Up Radio 211.4.6 Feasibility Study of Backscattering For Telemonitoring . 221.4.7 Proposed Ultra-Low-Power Voltage-Controlled RingOscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 221.5 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Efficient Data Converter Circuits for RFID Applications . . . . . . . 252.1 Overview of Successive Approximation RegisterAnalog-to-Digital Converters . . . . . . . . . . . . . . . . . . . . 262.2 Ultra-Low-Power SAR ADC with an Area-Efcient DAC Architecture 292.2.1 Comparator Architecture . . . . . . . . . . . . . . . . . . 322.2.2 Sample and Hold Architecture . . . . . . . . . . . . . . . 342.2.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . 352.3 Overview of Time-Mode Analog-to-Digital Converters . . . . . . 372.4 Highly-Linear Wide Input Range Voltage-to-Time Converter forTime-Mode Signal Processing . . . . . . . . . . . . . . . . . . . 392.4.1 Conventional Current-Starved VTC . . . . . . . . . . . . 392.4.2 Proposed Linearization Technique . . . . . . . . . . . . . 432.4.3 Implementation of Voltage Level shifters and SourceDegeneration Resistors . . . . . . . . . . . . . . . . . . . 472.4.4 Implementation of the Inverter-Based Comparator . . . . 492.4.5 Design Considerations . . . . . . . . . . . . . . . . . . . 502.4.6 Measurement Results . . . . . . . . . . . . . . . . . . . . 572.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 Efficient Power Converter Circuits for RFID Applications . . . . . . 633.1 Efficiency Analysis of UHF CMOS Rectifiers . . . . . . . . . . . 643.2 Proposed Switched Rectifier Scheme . . . . . . . . . . . . . . . . 723.2.1 Switched-Capacitor Gate-Boosting Scheme . . . . . . . . 753.2.2 Design Considerations . . . . . . . . . . . . . . . . . . . 78viii3.3 Proposed Auxiliary-Cell Boosting Scheme . . . . . . . . . . . . . 803.3.1 Design Considerations . . . . . . . . . . . . . . . . . . . 863.4 Proposed Quasi-Floating-Gate Boosting Scheme . . . . . . . . . 883.4.1 Design Considerations . . . . . . . . . . . . . . . . . . . 963.5 Post-Layout Simulation Results for the Proposed EfficiencyEnhancement Techniques . . . . . . . . . . . . . . . . . . . . . 1023.5.1 Switched Rectifier and switched-capacitor BoostedRectifier . . . . . . . . . . . . . . . . . . . . . . . . . . 1023.5.2 Auxiliary-cell Boosted Rectifier . . . . . . . . . . . . . 1063.5.3 Quasi-Floating-Gate Boosted Rectifier . . . . . . . . . . 1083.6 Proposed Dual-Band Matching Scheme . . . . . . . . . . . . . . 1163.6.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . 1183.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204 Power Efficient Receive and Transmit Schemes . . . . . . . . . . . . 1234.1 Proposed High-Sensitivity Fully Passive Wake-Up Radio . . . . . 1244.1.1 Overview of Wake-up Radio Scheme . . . . . . . . . . . 1244.1.2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . 1264.1.3 Wake-Up Radio Concept . . . . . . . . . . . . . . . . . . 1284.1.4 The Proposed Wake-Up Radio Architecture . . . . . . . . 1314.1.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . 1334.1.6 Experimental Results . . . . . . . . . . . . . . . . . . . . 1344.2 Feasibility Study of Backscattering For Telemonitoring . . . . . . 1374.2.1 Overviwew of backscattering scheme for telemonitoring . 1394.2.2 Telemonitoring of In-Stent Restenosis . . . . . . . . . . . 1394.2.3 Experimental Results . . . . . . . . . . . . . . . . . . . . 1414.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1435 Power Efficient Clock Generator Circuit . . . . . . . . . . . . . . . 1445.1 Proposed Ultra-Low-Power Voltage-Controlled Ring Oscillator . 1445.1.1 Overview of Low-Power Oscillators for Passive RFID tags 1455.1.2 Low-Power Ring Oscillator architecture . . . . . . . . . 1465.1.3 Design Considerations . . . . . . . . . . . . . . . . . . . 148ix5.1.4 Post-Layout Simulation Results . . . . . . . . . . . . . . 1525.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . 1546.1 Low-Power and Area-Efficient SAR ADC . . . . . . . . . . . . . 1546.2 Wide Input Range voltage-to-Time Converter . . . . . . . . . . . 1566.3 Efficiency Enhancement Techniques for Rectifiers . . . . . . . . . 1586.4 Dual-Band Matching Scheme . . . . . . . . . . . . . . . . . . . . 1606.5 Fully Passive Wake-Up Radio . . . . . . . . . . . . . . . . . . . 1616.6 Study of Backscattering for Telemonitoring . . . . . . . . . . . . 1626.7 Low-Power Ring Oscillator . . . . . . . . . . . . . . . . . . . . . 1626.8 Future Target: Self-Sufficient RFID Tag . . . . . . . . . . . . . . 163Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165xList of TablesTable 1.1 Summary of RFID frequency bands and characteristics. . . . . 7Table 1.2 Comparison of ADC types characteristics. . . . . . . . . . . . 15Table 2.1 Comparison of the proposed SAR ADC with the state-of-the-artresults [6]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Table 2.2 Comparison of the proposed VTC with similar works. . . . . . 61Table 3.1 Performance summary of the proposed efficiency enhancementtechniques and comparison with state-of-the-art [3, 4, 7]. . . . . . . . 115Table 4.1 Performance summary of the proposed fully-passive WUR. . . 137Table 5.1 Performance summary of the proposed low-powervoltage-controlled ring-oscillator. . . . . . . . . . . . . . . . . . . . . 151xiList of FiguresFigure 1.1 Block diagram of a generic RFID system. . . . . . . . . . . . 3Figure 1.2 RFID frequency bands. . . . . . . . . . . . . . . . . . . . . . 4Figure 1.3 Schematic diagram of the operation principles of inductive andradiative coupling in RFID systems. . . . . . . . . . . . . . . . . . . 6Figure 1.4 Schematic diagram of the operation principles of passive,semi-passive and active RFID tags. . . . . . . . . . . . . . . . . . . . 9Figure 1.5 Schematic diagram of a sensor-enabled passive RFID tag. . . 13Figure 1.6 Schematic diagram of the power levels along the path from thereader to the output of the rectifier. . . . . . . . . . . . . . . . . . . . 14Figure 1.7 Comparison of different ADC architectures in terms ofsampling rate and resolution. . . . . . . . . . . . . . . . . . . . . . . 16Figure 1.8 Schematic diagram of a time-mode analog-to-digital converter. 17Figure 1.9 Schematic diagram different blocks of a passive RFID tagaddressed in this thesis. . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 2.1 Schematic diagram of a conventional SAR ADC [6]. . . . . . 26Figure 2.2 Schematic of the proposed DAC architecture and its timingdiagram [6]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Figure 2.3 Schematic of the proposed comparator and its timing diagram[6]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 2.4 Schematic of the low-power latch architecture [6]. . . . . . . 33Figure 2.5 Schematic of the low-power amplifier [6]. . . . . . . . . . . . 34Figure 2.6 Schematic of the Proposed sample-and-hold architecture andtiming diagram [6]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35xiiFigure 2.7 Simulated DNL and INL at 25ks/s [6]. . . . . . . . . . . . . . 36Figure 2.8 Output spectra for input sine wave @ 2.24kHz and 12.4kHz[6]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Figure 2.9 Schematic diagram of a generic TMSP system. . . . . . . . . 38Figure 2.10 Conventional current-starved VTC. . . . . . . . . . . . . . . 40Figure 2.11 Schematic diagram of transient discharge current and voltagelevels of the current-starved VTC. . . . . . . . . . . . . . . . . . . . 42Figure 2.12 Simulated delay-time and discharge current versus inputvoltage for the conventional current-starved VTC. . . . . . . . . . . . 43Figure 2.13 Proposed charge and discharge scheme. . . . . . . . . . . . . 44Figure 2.14 NMOS input device with diode-connected load . . . . . . . . 45Figure 2.15 shifted drain currents of an NMOS device and summation ofthe shifted curves versus input voltage. . . . . . . . . . . . . . . . . . 46Figure 2.16 Schematic diagram of the circuit level implementation of theproposed constant-Gm voltage-to-current converter. . . . . . . . . . . 46Figure 2.17 CMOS implementation of level shifters and sourcedegeneration resistors . . . . . . . . . . . . . . . . . . . . . . . . . . 48Figure 2.18 Comparator implementation . . . . . . . . . . . . . . . . . . 49Figure 2.19 Circuit level schematic of the proposed VTC. . . . . . . . . . 51Figure 2.20 Simulated delay for the entire input range for different clockfrequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 2.21 Simulated transient voltage of storage capacitor during thecharge cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 2.22 Storage capacitor modification scheme along with thesimulated delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 2.23 Delay offset cancellation scheme . . . . . . . . . . . . . . . . 56Figure 2.24 Spectrum of the output delay for different input frequencieswithout sample-and-hold. . . . . . . . . . . . . . . . . . . . . . . . . 57Figure 2.25 Spectrum of the output delay for a 15.1 MHz sinusoidal inputwith and without sample-and-hold. . . . . . . . . . . . . . . . . . . . 57Figure 2.26 Micrograph of the fabricated VTC. . . . . . . . . . . . . . . . 58Figure 2.27 Schematic diagram of the measurement setup. . . . . . . . . . 58Figure 2.28 Measured and simulated delays for the entire input range. . . . 59xiiiFigure 2.29 Measured and simulated linearity error for the entire input range. 59Figure 2.30 Measured and simulated analog current consumption of theVTC for the entire input range. . . . . . . . . . . . . . . . . . . . . . 60Figure 3.1 Schematic diagram of a generic RF power harvesting unit. . . 64Figure 3.2 Schematic diagram of the PCE curve of a generic rectifier. . . 66Figure 3.3 Conventional differential rectifier . . . . . . . . . . . . . . . 67Figure 3.4 PCE curve and forward-to-reverse current ratios of MP2 versusinput voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Figure 3.5 PCE curve and average gate-drive voltage during forward andreverse conduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Figure 3.6 Proposed biasing scheme. . . . . . . . . . . . . . . . . . . . 71Figure 3.7 Proposed Switched rectifier. . . . . . . . . . . . . . . . . . . 73Figure 3.8 Clock generation circuitry [7]. . . . . . . . . . . . . . . . . . 75Figure 3.9 Proposed Gate-boosted rectifier. . . . . . . . . . . . . . . . . 76Figure 3.10 Switched-capacitor implementation of the floating voltagesource [7]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Figure 3.11 Schematic diagram of the proposed gate-boosted rectifier [7]. 78Figure 3.12 Output voltage and current of a rectifier stage versus loadvalues [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Figure 3.13 Schematic diagram of a reverse-rectifier cell and the associatedvoltage levels [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Figure 3.14 Diagram of the intermediate and boosted gate-drive voltagesalong the rectifier chain [4]. . . . . . . . . . . . . . . . . . . . . . . . 82Figure 3.15 Schematic diagram of the proposed auxiliary-cell boostingscheme [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Figure 3.16 Generated voltage waveforms at the second stage of theproposed rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Figure 3.17 Schematic diagram of the proposed auxiliary-cell boostedrectifier [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Figure 3.18 Parasitics seen by the coupling capacitors in the floatingrectifier [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Figure 3.19 The proposed QFG-biased gate-boosting scheme. . . . . . . . 90xivFigure 3.20 Quasi-floating gate biased NMOS transistor [3]. . . . . . . . . 91Figure 3.21 Proposed QFG-biased differential rectifier [3]. . . . . . . . . 92Figure 3.22 Schematic diagram of the intermediate DC voltage, BiasP,BiasN and the boosting levels of the proposed biasing scheme [3]. . . 93Figure 3.23 The proposed bandgap Bias generator circuitry [3]. . . . . . . 94Figure 3.24 Simulated voltage waveforms of the bias generator [3]. . . . . 94Figure 3.25 Transient output waveform of the proposed gate boosting scheme 95Figure 3.26 Schematic diagram of the proposed QFG boosted rectifier [3]. 96Figure 3.27 Parasitics associated with the gate of a QFG-biased switch. . . 97Figure 3.28 Low-pass filtering characteristic of QFG architecture. . . . . . 99Figure 3.29 Transient response time of QFG architecture. . . . . . . . . . 100Figure 3.30 PCE performance of SW and SC rectifiers . . . . . . . . . . . 103Figure 3.31 Output voltage versus load value of SW and SC rectifiers . . . 104Figure 3.32 Output power versus load value of SW and SC rectifiers . . . 105Figure 3.33 Frequency performance of SW and SC rectifiers . . . . . . . . 106Figure 3.34 PCE of the proposed auxiliary-cell boosted rectifier [4]. . . . . 107Figure 3.35 Output voltage of the proposed auxiliary-cell boosted rectifier[4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Figure 3.36 Performance of the proposed auxiliary-cell boosted rectifier asa function of load value . . . . . . . . . . . . . . . . . . . . . . . . . 109Figure 3.37 Frequency dependency of the proposed auxiliary-cell boostedrectifier [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Figure 3.38 PCE of the proposed QFG-boosted rectifier [3]. . . . . . . . . 111Figure 3.39 Performance of the proposed QFG-boosted boosted rectifier asa function of load value. . . . . . . . . . . . . . . . . . . . . . . . . 112Figure 3.40 Frequency dependence of the proposed QFG-boosted rectifier[3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Figure 3.41 Current consumption of the bandgap bias generator [3]. . . . . 113Figure 3.42 Layout view of the proposed rectifiers. . . . . . . . . . . . . . 114Figure 3.44 Proposed matching scheme. . . . . . . . . . . . . . . . . . . 116Figure 3.45 Schematic of the first stage of the rectifier and its inputcapacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Figure 3.46 Block diagram of the proposed dual-band matching scheme. . 118xvFigure 3.47 Transient response of the proposed matching scheme. . . . . . 119Figure 3.48 Frequency response of the proposed matching scheme. . . . . 119Figure 3.49 Schematic diagram of monitoring system. . . . . . . . . . . . 121Figure 4.1 Generic block diagram of a wireless node with a separate wakeup radio receiver [2]. . . . . . . . . . . . . . . . . . . . . . . . . . . 129Figure 4.2 Asynchronous communication scheme using a wake up radio. 129Figure 4.3 Block diagram of the proposed WUR front-end [2]. . . . . . . 131Figure 4.4 Schematic diagram of the three-stage differential rectifier. . . 133Figure 4.5 Transient simulation of wake-up radio front-end [2]. . . . . . 133Figure 4.6 Micrograph of the three-stage rectifier. . . . . . . . . . . . . . 134Figure 4.7 Block diagram of the measurement setup. . . . . . . . . . . . 134Figure 4.8 The rectifier output at 10kb/s data rate for a − 21 dBm inputpower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Figure 4.9 The rectifier output at 10, 50 and 100 kb/s . . . . . . . . . . . 136Figure 4.10 Comparator output at 10, 50 and 100 kb/s . . . . . . . . . . . 138Figure 4.11 Rectifier output for an input power of − 26 dBm at 100 kb/sinput data rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139Figure 4.12 Schematic diagram of the test setup for backscatteringfeasibility study. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140Figure 4.13 Backscattering-based measurement setup [8]. . . . . . . . . . 141Figure 4.14 Measured backscattered power level versus different loadvalues and input powers [8]. . . . . . . . . . . . . . . . . . . . . . . 142Figure 5.1 Block diagram of a generic passive RFID tag. . . . . . . . . . 145Figure 5.2 Schematic diagram of the proposed two-stage ring oscillator. . 147Figure 5.3 Implementation of the floating voltage sources through QFGarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148Figure 5.4 Transient settling behavior of the proposed QFG-biased VCRO. 149Figure 5.5 Schematic diagram of the proposed VCRO and voltage levelconverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Figure 5.7 Oscillation frequency of the proposed VCRO. . . . . . . . . . 151Figure 5.8 Layout view of the proposed VCRO. . . . . . . . . . . . . . . 152xviFigure 6.1 Schematic diagram of a time-mode ADC. . . . . . . . . . . . 156Figure 6.2 Schematic diagram of the current-based SAR ADC. . . . . . . 157Figure 6.3 Schematic diagram of the wireless power harvesting unit. . . . 159Figure 6.4 Schematic diagram of the multi-band matching scheme. . . . 161Figure 6.5 Schematic diagram of the self-sufficient RFID tag/senor node. 163xviiGlossaryADC analog-to-digital converterCMOS complementary metal-oxide-semiconductorCPU central processing unitCS current-starvedDLL delay locked loopsDNL differential nonlinearityDTC digital-to-time converterENOB effective number of bitsFCC federal communications commissionFDM frequency-division multiplexingFOM figure of meritFSK frequency shift keyingHF high-frequencyIC integrated circuitsINL integral nonlinearityISM industrial scientific and medicalxviiiKBPS kilo-bit per secondLF low-frequencyLNA low noise amplifierLSB least significant bitMAC medium access controlMCU microcontroller unitMF medium-frequencyMIM metal-insulator-metalMOS metal-oxide-semiconductorMSB most significant bitMSPS Mega-samples per secondOCR optical character recognitionOOK on-off keyingPCE power conversion efficiencyPD pseudo-differentialPLL phase locked loopPMU power management unitPSK phase shift keyingQAM quadrature amplitude modulationRF radio frequencyRFID Radio frequency identificationRO ring oscillatorxixSAR successive approximation registerSC switched-capacitorSMA sub-miniature version ASNDR signal-to-noise and distortion ratioSRO single-ended ring-oscillatorTDC time-to-digital converterTMSP time mode signal processingTVC time-to-voltage converterUHF ultra-high-frequencyVCDU voltage-controlled delay unitVCRO voltage-controlled ring oscillatorVHF very-high-frequencyWUR wake-up radioxxAcknowledgmentsFirst and foremost, I would like to express my sincere appreciation to my academicsupervisor, Professor Shahriar Mirabbasi, for his full support, expert guidance,understanding and encouragement. He has been more than an academic supervisor.I have been lucky to have him as my mentor throughout my study and research.This thesis would not have been possible without his kindness and persistent help.My deep gratitude also goes to my co-supervisor, Professor Victor C.M. Leung,for his humbleness, incisive guidance, comments, suggestions, and encouragementduring my research.Furthermore, I would like to thank my colleagues and friends at the System-on-a-Chip (SoC) Research Laboratory for the technical discussions, the friendlyenvironment they created for me and all the fun memories we had together.I would also like to acknowledge the Natural Sciences and EngineeringResearch Council of Canada (NSERC) for funding this project and CanadianMicroelectronics Corporation (CMC Microsystems) for providing CAD toolsupport and facilitating chip fabrication.Last but not least, my heartfelt thanks and sincere gratitude go to my mother,my father and my sister for their love, support and encouragement over the years;it is to them that I dedicate this thesis.xxiChapter 1Introduction1.1 RFID Technology OverviewRadio frequency identification (RFID) is a communication technology that useselectromagnetic waves to transfer data between a reader and a tag for the purposeof contactless identification, tracking and data collection. The concept of usingradio communication to identify physical objects has existed for over half acentury [9]. However, the widespread use of this technology became a possibilityonly after the emergence of inexpensive integrated circuits (IC). RFID technologycan be considered as the predecessor to the two widely used optical identificationsystems namely bar code and optical character recognition (OCR). Bar code andOCR use an optical transducer to extract data from the identifying mark(one-dimensional in the case of bar code and two-dimensional in the case ofOCR) [9]. Although optical identification methods are being prevalently used invirtue of their simplicity and low cost, they come with many drawbacks. Mostimportantly, such systems require a line of sight between the reader device and theidentification mark which severely limits their usefulness in applications where alarge number of objects are spread over a wide area. Some other shortcomings ofoptical identification systems include readability degradation as the result ofmechanical damage to the marks, short interrogation distance and limited storagecapacity.RFID technology on the other hand uses electromagnetic waves to establish a1communication link between the reader and the physical object and thereforealleviates the need for line of sight. The non-line-of-sight operation of RFIDsystems allows simultaneous identification of multiple objects in a wide area.Moreover, RFID systems offer many more advantages over optical identificationsystems which could be summarized as RFID advantages1 [10]:• Robustness and reliability: Objects can be identified in tough environmentsand difficult scenarios.• Speed: The transponders (objects) respond to the interrogation command ata very short time (on the order of miliseconds).• Bidirectional communication: The transponders are writable (i.e., theidentity code can be edited in real time). Also, depending on theapplication, some transponders can initiate a communication with thereader.• High storage capacity: The transponders can accommodate semiconductormemory (flash) and are therefore, capable of offering a higher storagecapacity compared to optical identification systems.• Data process capability: The transponders can be equipped with a processingunit which allows them to detect more elaborate interrogation commands andtransmit more detailed environmental/sensory data.The aforementioned advantages combined with the emergence of low-costintegrated circuits have made RFID technology a very attractive candidate fornumerous real world applications. According to IDTechEx2 report, the totalmarket for RFID technology was worth $6.98 billion and $7.88 billion in 2012and 2013 respectively and will grow to $9.2 billion in 2014. The report forecaststhe market value to rise $30.24 billion in 2024 [11]. Major applications of RFIDtechnology include [12]:• Logistics: Facilitates supply chain management and product delivery.1http://www.brooks.com/applications-by-industry/rfid/rfid-basics/rfid-advantages2http://www.idtechex.com/2TransceiverProcessing Unit (FPGA, DSP) TransceiverProcessing Unit Sensorcommand (Reader)response (Tag)Reader (interrogator) Tag (transponder)host  (network) MemoryFigure 1.1: Block diagram of a generic RFID system.• Toll systems: Provides a fast, contactless, secure and convenient checkin/out.• Ticket: Enables contactless automatic identification. Also allows furtherdata collection (allocation, flow of ticket holders, etc.).• Health care: Facilitates the automation of admittance, screening and treating.Enables wireless personal health monitoring.• Security and Identification: Provides a reliable storage of identificationinformation (ID cards, passports, etc.).A generic RFID system consists of three main components, namely reader(interrogator), tag (transponder) and the host computer (network) as schematicallyshown in Figure 1.1. The reader and the antenna tags establish the wirelesscommunication between the reader and the tag. The reader antenna can beintegrated with the reader or connected with a cable, while the tag antenna isgenerally integrated in the tag. Most tags incorporate an IC which contains the tagID (in a silicon memory) and performs the processing required for communicationwith the reader and sensory data interfacing. Note that the sensor (and theassociated interface) is not an integral part of all RFID tags and may or may notbe incorporated in the tag depending on the application. The reader and tagtransceivers are responsible for receiving/transmitting (modulation/demodulation)the interrogation commands and tag responses respectively. There are some tagsin the technology that do not use an IC and only transmit an identification code inresponse to an interrogation command. Also, depending on the application, thereader may support a user interface or may be connected to a host for furtherprocessing and storage of the received responses [9].3LF MF HF VHF UHF3000 300 30 3 0.3 0.03100K 1M 10M 100M 1G 10GInductive (magnetic) Radiative (electromagnetic)125/134KHz 13.56MHz 860-960MHz 2.4GHzcommon RFID bandsWavelength (m)frequency (Hz)Figure 1.2: RFID frequency bands.1.2 RFID ClassificationRFID systems are generally categorized based on three characteristics, theirfrequency of operation, the method they use to deliver power to the tags and theprotocol they use to for the communication between the tag and the reader. Thefrequency band, power delivery method and communication protocol are dictatedby the application and directly influence the important aspects of the entire systemsuch as cost, communication range and functionality [9].1.2.1 RFID Frequency BandsRFID operates in the unlicensed spectrum space also known as the industrialscientific and medical (ISM) band. ISM bands are reserved for the use of radiofrequency (RF) energy for industrial, scientific and medical purposes only (ratherthan telecommunication)3 and their use are governed by part 18 of federalcommunications commission (FCC) rules4 [13].Figure 1.2 shows the operating frequencies used by RFID systems [9]. Asshown in the figure, the most common frequency bands used by RFID systems are125/134 kHz5, 13.56 MHz and 2.4-2.45 GHz. The systems operating in the firstfrequency band (125/134 kHz) are referred to as low-frequency (LF) RFID3http://en.wikipedia.org/w/index.php?title=Special:Cite&page=ISM band&id=6034922964http://www.ecfr.gov/cgi-bin/text-idx?SID=758038852bf8e27b362820cc4a3ae5da&node=47: two distinct frequencies are used for frequency-shift-keying scheme.4systems, those operating at 13.56 MHz are known as high-frequency (HF) systemsand finally readers and tags operating at 900 MHz and 2.4-2.45 GHz range arecharacterized as ultra-high-frequency (UHF) systems. To distinguish between the900 MHz and 2.4-2.45 GHz bands, the former category of tags and readers arereferred to as UHF devices while the latter category are known as microwaveRFID system [9]. As shown in Figure 1.2, medium-frequency (MF) andvery-high-frequency (VHF) bands are not used for RFID application.Note that in Figure 1.2, the frequency band is partitioned into inductive andradiative regions. Generally, the systems in which the wavelength is much largerthan typical antenna sizes are inductively coupled. The systems in the inductiverange have a wavelength of 3000 to 3 meters. Therefore, for a typical antenna size(on the order of 1 meter or less), such systems fall into the category of inductively(magnetically) coupled devices. The inductively coupled reader-tag systempractically forms a magnetic transformer which provides a coupling between thecurrent flowing in the reader antenna (primary) and the voltage induced in the tagantenna (secondary). For a fixed transmitted energy from the reader, the receivedenergy at the tag antenna drops with the cube of the communication distance (orfaster in practical scenarios). Such a coupling can be used to transfer data betweenthe reader and the tag and also power from the reader to the tag.Radiative (electromagnetic) coupling is referred to systems in which theantenna size is comparable to the wavelength. Generally, in electromagneticallycoupled systems, the reader-tag distance is much longer than a single wavelengthand a weak version of the transmitted signal (by the reader) is received at the tagantenna. Note that in many practical scenarios, multipath fading furtherexacerbates the detection of the received signal, making it a heavily dependentfunction of the tag’s location [14]. For a fixed transmitted energy from the reader,the received energy at the tags antenna falls off with the square of thecommunication distance (or faster in practical scenarios).Apart from the distinction in the frequency of operation, the adoption of thecoupling method (inductive versus radiative) directly affects the behavior of theentire RFID system. Generally, inductive coupling is a reliable method when thedistance between the reader and the tag antenna is short (on the order of the readerantenna size). However, inductive coupling is very sensitive to both the5currentReader TagTag pow er α 1 / d 3  C ommu n i c a t i on  d i s t a n c e TagReader antenna Tag antenna TagR ea d erR ea d erC ommu n i c a t i on  d i s t a n c eTag pow er α 1 / d 2  ob s t a c l eob s t a c l ed ≈ λ d »  λ inductive coupling radiative couplingvoltageFigure 1.3: Schematic diagram of the operation principles of inductive andradiative coupling in RFID systems.communication distance and the relative displacement (orientation) of theantennas. Therefore, such systems are essentially suitable for applications wherethe communication distance is short and the orientation of the antennas (coils) canbe easily defined by the user. Examples of such applications include health-caremonitoring devices (animal and human ID) and access control (ID card readers).On the other hand, electromagnetically coupled RFID systems provide a longercommunication distance at the cost of more complex propagation channel whichtypically requires a more sophisticated receiver for the RFID tag. The operationprinciples of inductive coupling and radiative coupling methods are schematicallyshown in Figure 1.3 [9].The choice of frequency band has many implications on other performancemetrics of the RFID system. Inductively coupled systems use coil antennas. For afixed primary coil (reader antenna) current, the voltage induced on the secondarycoil (tag antenna) is proportional to the frequency of operation, the size and thenumber of the turns of the coil. Therefore, systems operating at LF (125 kHz)require larger coils with more number of turns (on the order of 10 to 100 turns).Systems operating at HF (13 MHz) also use coil antennas with less number ofturns (3 to 6 turns) compared to LF systems. At UHF/microwave frequencies, tagsgenerally used dipole antennas. The size of a dipole antenna (typically about halfthe wavelength) is inversely proportional to the frequency of operation.The frequency of operation also affects how the waves interact with materials6Table 1.1: Summary of RFID frequency bands and characteristics.Band LF HF UHF MicrowaveFrequency 30 - 300 kHz 3 - 30 MHz 0.3-3 GHz 2-30 GHzTypical RFIDFrequency125 - 134 kHz 13.56 MHz433 MHzUHF1860 - 960 MHzUHF22.45 GHz∼CommunicationRange< 0.5 m ≤ 1.5 mUHF1: ≤100 mUHF2: 0.5 m∼5 m≤ 10 mData Transfer Rate < 1 kbps ≈ 25 kbps ≈ 30 kbps ≤ 100 kbpsCharacteristicsShort range.Low data rate.Penetrates waterbut not metal.Mid range.Mid data rate.Penetrates waterbut not metal.Long range.High data rate.No water/metalpenetration.long range.High data rate.No water/metalpenetration.ApplicationAnimal ID.Access control.Car immobiliser.Smart labels.Contactless travelcards, AccessSecurity, Apparel.Logistics, Baggage,Handling, Electronictoll collection.Electronictoll collection.present in the communication medium. The two most common materials RFIDwaves encounter with are water and metallic objects. Generally, the wavespenetration distance (also known as skin depth) both for water and metallicobjects drops as the frequency increases. This follows that LF and HF systems aremore suitable for human and animal identification where the waves need topenetrate through water containing materials (body tissue).The data rate of an RFID system is also a function of the frequency ofoperation. More specifically for a frequency modulation scheme, the signaldetection accuracy is directly proportional to the number of the cycles that thereader/tag receives for each binary bit (0 or 1), in order to be able to differentiatebetween the two frequencies the represent each bit. Therefore, for higherfrequencies, less time is required to accurately detect a transmitted bit, which inturn corresponds to a higher data rate. The data rate of LF systems is on the orderof a few kilo-bit per second (KBPS) while UHF tags operate and a few tens ofkbps data rate [9]. Table 1.1 summarizes RFID frequency bands, theircharacteristics and common applications [15].71.2.2 RFID Power Delivery MethodsAs mentioned earlier, RFID systems are also categorized based on the power(energy) delivery methods to the tags. From the perspective of manufacturing costand form factor, it is particularly desirable to remove the dedicated energy source(battery) of the tags. Battery-less tags also provide a long and maintenance-freelife time. Depending on the presence or absence of the dedicated power sourceand the extent to which the power source is used, RFID tags are classified intothree groups of passive, semi-passive and active tags.Passive tags do not have an independent power source and do not use aconventional transmitter. These class of tags harvest their required energy byrectifying the transmitted power from the reader. In order to send informationback to the reader, passive tags practically reflect the transmitted waves in ascheme known as backscattering [16] .Semi-passive tags (also referred to as battery-assisted passive tags) incorporatea battery. However, the battery is only used to power the tag’s internal circuitry.In order to transmit information back to the reader, semi-passive tags also use thebackscattering communication method and therefore do not employ a conventionaltransmitter.Active tags on the other hand, use a battery both to power the tag circuitry andsignal transmission. They incorporate a conventional transmitter and establish abidirectional communication with the reader.As mentioned above, passive tags extract power from the received waves bymeans of a block called rectifier (also known as RF-to-DC converter). Therectified voltage is regulated to produce a rather stable supply for the succeedingcircuitries. These category of tags generally perform envelope detection method todemodulate and detect the received signal. In order to transmit information backto the reader, passive tags change the electrical characteristics of their antenna bymodulating the impedance of the antenna with respect to the data bits. A commonmethod for realizing antenna impedance modulation is through switching theantenna terminal between two states (short an open in the extreme case). Suchvariations in the impedance of the antenna can be detected by the sophisticatedreceiver at the reader side. The absence of battery and dedicated transmitter (and8ReaderrectifierDC powermemoryProcessing unitPower (tag and radio) Backscattered signal dataimpedance modulationPassive TagReaderPower (radio) Backscattered signal RF powerReaderbattery memoryProcessing unitcommandresponsedatatransceiverreceiver 010101batteryDC powermemoryProcessing unitdataimpedance modulationreceiver 010101Semi-passive TagActive TagFigure 1.4: Schematic diagram of the operation principles of passive, semi-passive and active RFID tags.associated analog blocks such as frequency synthesizers, power amplifiers, lownoise amplifiers, etc.), facilitates low cost implementation of passive tags which isof paramount importance in many RFID applications. However, such simplicityand low cost offered by passive tags come at the expense of short read range (onthe order of 2 to 20 meters). Also, since passive tags rely on the transmitted power(from the reader) as the sole source of energy, they are unable to support9complicated communication protocols and are typically designed to perform basiccomputational tasks.Semi-passive tags use a battery to power the internal circuitry and aretherefore capable of accommodating a more elaborate IC. Although they usebackscattering for re-transmitting information to the reader, availability of adedicated power source allows inclusion of some RF blocks (such as RFamplifiers) at the receiver front-end. A more elaborate receiver provides a longerread range (on the order of 10 to 100 meters) for semi-passive tags. Semi-passivetags have a rather long life time as they sink their battery at a very low duty cycleand spend most of their time in idle/sleep mode. Nevertheless, incorporation of abattery imposes a higher manufacturing cost, larger aspect ratio and maintenancerequirements.Active tags are practically complete radios with all the required circuitryincluding power source, receiver, transmitter and processing unit [9]. Theytypically incorporate the complete transceiver chain and are capable of realizingmore complex modulation schemes, such as frequency-divisionmultiplexing (FDM) which is beneficial in scenarios where multiple tags want tocommunicate with the reader simultaneously. In virtue of their powerful receiver,active tags can support sophisticated modulation schemes such as phase shiftkeying (PSK), frequency shift keying (FSK) and quadrature amplitudemodulation (QAM) and therefore achieve a much longer read range (on the orderof hundreds of meter and higher) compared to their passive and semi-passivecounterparts. Evidently, this advantage comes with a high cost, large size andmaintenance requirements for the tags.Figure 1.4 schematically shows the operation principles of passive,semi-passive and active tags [9].1.2.3 RFID ProtocolsProtocols generally define a set of rules on how information is exchanged betweentwo nodes. They address the type of signals and symbols and also determine howthe channel is allocated among different transmitters. In the context of RFID10systems, EPCglobal®6 is in charge of establishing standards for supply chain andrelated applications. There are different protocols for different systems andclasses. These protocols were developed independently and the systems adoptingthem, are not necessarily mutually compatible. In terms of RFID frequencybands, different classes inevitably require different coding and modulationschemes, and therefore adopt distinct protocols. As discussed earlier, LF systemsuse FSK while HF and UHF tags use amplitude modulation. Also, different powerdelivery methods entail specific standards. For example, as discussed earlier,passive tags employ a simple receiver and are therefore incapable of realizingspectrally efficient modulation schemes such as PSK and QAM. Note that apartfrom modulation scheme, medium access control (MAC) layer architecture, packetstructure and coding schemes are also defined as elements of RFID protocols [17].RFID communication protocols are beyond the scope of this thesis and were onlydiscussed briefly in this section.1.3 Challenges and MotivationRFID technology covers a wide range of applications, each with its specific set ofrequirements. Some applications require sophisticated tag/reader with complexcircuitries and high processing capabilities. Such applications allocate sufficientpower budget for the system and usually cost is not a matter of concern for them.Such applications span a relatively narrow range of RFID potentials. In mostapplications, an RFID system is expected to involve a very large quantity of tagswith unique IDs in an architecture known as Internet of things [18]. Internet ofthings is a term referred to the network of a large number of uniquely identifiableobjects in an Internet-like structure. Each identifiable object is equipped with asort of embedded intelligence which allows an interaction with internal or externalenvironment. Internet of things relies on RFID technology as its infrastructure.Due to several reasons, active tags do not simply lend themselves to largescale deployment. Unfortunately, battery technology has progressed slowly and islagging behind the requirements expected for low maintenance systems. Printedbatteries and power packs exist in the technology, however, the amount of energy6http://www.gs1.org/gsmp/kc/epcglobal11they store and deliver to the tag is far less than what is required to run an activetag for a reasonable amount of time. Apart from manufacturing cost, maintenancerequirements and power considerations, battery-powered tags are problematic inmany RFID applications which are size-sensitive. Passive tags on the other hand,are very attractive candidates for large scale deployment in virtue of theirsimplicity, low manufacturing cost and zero maintenance requirements. They canoperate at any RFID frequency band, however they could be designed in smallerform factor at higher frequencies. In virtue of the essential advantages mentionedabove, passive IC-based RFID tags are considered to be the dominant RFIDtechnology in near future manufactured and deployed in very large quantities.As mentioned in Section 1.2, passive tags extract their required energy fromthe incident power transmitted by the reader (or from environmental sources in theform of heat, light or vibrations) and the absence of a dedicated energy source inpassive tags poses stringent design challenges. The most important problem ariseswhen the tag is located at a far distance from the reader (in electromagneticallycoupled systems) or is misaligned with respect to the reader (in inductivelycoupled systems). As discussed in Section 1.2, the power received by the tag(from the reader) drops with the cube and the square of the communicationdistance in inductively coupled and electromagnetically coupled systemsrespectively. The received power by the tag is even less in the presence ofenvironmental obstacles and multipath fading. Therefore, if the reader and the tagare located far enough from one another such that a minimum power is notreceived by the tag, the entire operation of the system would be compromised.Such scenarios occur frequently in practice, when the reader, the tag and/or theenvironmental objects are in motion. Since a long read range is of paramountimportance in many RFID applications, meticulous architectures (both at systemand circuit levels) need to be devised in order to guarantee that the tag receivessufficient amount of energy at any circumstance and to avoid potentialmalfunctions.From a circuit level perspective, two major paths has to be followed in orderto guarantee that sufficient power is delivered to the passive tag. Primarily, a highperformance power harvesting unit is required to receive the incoming energy andto convert it to a stable form to supply the tag’s circuitry. Furthermore, intelligent12R ectif ier regu l atorSensorADCTransceiverB a c k s c a t erri n gor (ASK  mod / d emod )memoryB aseb and  p rocessing u nitC l ock G en.V D D  (D C )Power (RF)M atchingcircu itA ntenna Passive RFID TagFigure 1.5: Schematic diagram of a sensor-enabled passive RFID tag.design techniques have to be devised and applied to the tag’s circuitry in order tominimize the minimum required power proper operation.Figure 1.5 shows the block diagram of a generic sensor-enabled passive RFIDtag. As shown in the figure, a passive tag comprises an antenna, an impedancematching circuit (typically embedded in the antenna structure), a transceiver(backscattering or ASK modulator/demodulator), a baseband processing unit andmemory, a clock generator, an analog-to-digital converter (ADC) and a sensor(s).Note that excluding some specific applications where the tag transmits simple IDinformation (code), a sensor (and the associated interface including the ADC) isan integral part of a passive RFID tag. The sensor and the ADC are required if thetag is to interact with its internal environment and collect data (e.g., in wirelesssensor networks and Internet of things). The baseband processor controls theoperation of the tag. Its main task is to process the received data (from thereceiver) and to generate an appropriate response (for the transmitter) using theinformation stored in the memory or from the data collected by the sensor. Theclock generator (typically in the form of a simple local oscillator) synchronizesthe operation of the ADC, processor and the transmitter.An important block in the passive RFID tag is the rectifier (also known as RF-to-DC converter). Rectifier as the core of the power harvesting unit is responsiblefor receiving RF energy from the tag antenna and to convert it to an stable DCvoltage to supply the building block of tag. The most crucial performance metricof a rectifier is its power conversion efficiency (PCE) which directly affects theoverall operation of the entire tag. PCE is defined as:13R ectif ierreaderc h a n n el  l os sP TX P RXref l ec t ed  p ow er ref l ec t ed  p ow erP in, RF P ou t, D CPRX/PTX  α 1/d2 PRX/PTX  α 1/d3 radiative:inductive: P ou t, D C =  P C E rec ×  P in, RFdM atchingnetworkFigure 1.6: Schematic diagram of the power levels along the path from thereader to the output of the rectifier.PCErec =Pout,DCPin, RF(1.1)where, Pin,RF is the RF power available at the input of the rectifier and Pout,DC is therectified DC output power of the rectifier. In order for the tag to operate properly,Pout has to be larger than the summation of the required power for all the buildingblocks including transceiver, processor, clock generator, ADC and the sensor.Figure 1.6 schematically shows how the power level drops from thetransmitter (reader) on its way to the output of the rectifier. As shown in thefigure, the highest degradation occurs across the communication channel(PTX-to-OPRX) due to channel loss. As mentioned in Section 1.2.1, the channelloss is proportional to the square of distance and to the cube of distance inradiative and inductive coupling respectively. Note that these dependencies areoptimistic estimations and do not include the adverse effects of the obstacles andmultipath fading (for radiative coupling) and misalignment (inductive coupling).The received power at the tag antenna (PRX) further drops due to the potentialimpedance mismatch between the output of the antenna and the input of the tag(rectifier and transceiver). Note that a perfect impedance matching, even in thepresence of the matching network is not practically feasible due to geometriclimitations of the antenna and the variable input impedance of the tag. The finalpower level degradation occurs in the process of rectification the implication ofwhich is represented by an imperfect PCE (i.e., PCE% 6= 100). For an idealchannel (no environmental obstacle) and for a perfect impedance matching (noreflection from the input of the tag), Friis equation shows how the tag’s power is14Table 1.2: Comparison of ADC types characteristics.Architecture Latency Speed Resolution AreaFlash Low High Low HighSAR Low Low-medium Medium-high LowFolding/interpolation Low Medium-high Medium HighDelta-sigma High Low High MediumPipeline High Medium-high Medium-high Mediumrelated to the transmitted power [19]:Pout,DC = Ptag = PTX ·Gtag ·PCErec ·(λ4pid)2(1.2)where, Ptag is the minimum required power for the tag circuitry, PTX is thetransmitted power by the reader (as in Equation 1.1), Gtag the the gain of tagantenna, PCErec is the efficiency of the rectifier (as in Equation 1.1), λ is thewavelength of the transmitted waves and d is the communication distance. Notethat in Equation 1.2, the maximum PTX is governed by FCC to 4 W ([13]), Gtag isdictated by antenna geometry and tag’s size limitations and λ (and accordinglythe frequency of operation) and the read range. d are set by the application. Also,Ptag is dictated by the application, sensitivity of the tag receiver and basebandprocessing requirements of the tag (typically on the order of a few micro-Watts tohundreds of micro-Watts). Therefore for a fixed Ptag, the efficiency of the rectifier,PCErec turns out to be the only design parameter in order to guarantee a reliabletag operation and to increase the read range, d. Extensive studies have beencarried out in the literature in an attempt to improve the performance of the powerharvesting unit and to propose high efficiency rectifiers for passive RFID tags.Enhancing the power conversion efficiency of the rectifier at a circuit levelperspective will be discussed in details in Chapter 3.Another important building block of a sensor enabled passive RFID tag is theanalog to digital converter. Environmental data collected by the sensors (e.g.,temperature, humidity, gas, blood pressure, etc.) are analog in nature and have tobe converted to the digital domain to be processed by the processing unit of thetag and consequently transmitted to the reader. The ADC can consume a large15D el ta- sigm aSA RPip el ineF ol d ingI nterp ol atingF l ash2 - b it4 - b it6 - b it8 - b it1 0 - b it1 2 - b it1 4 - b it1 6 - b it1 0 0 k 1 M 1 0 M 1 0 0 M 1 G 1 0 Gsamp l ing  r ate ( samp l es/ second)resolutionFigure 1.7: Comparison of different ADC architectures in terms of samplingrate and resolution.percentage of both the power and the silicon area available for the passive RFIDtag. Therefore, the selection of the right topology and specification of the ADCrequires a keen attention. ADC topologies are classified into five major categoriesof delta-sigma, successive approximation, pipeline, folding/interpolating andflash. Figure 1.7 and Table 1.2 compare different ADC types in terms of samplingrate, resolution and basic characteristics [20]. It should be noted that most RFIDapplications (depending on the sensory data that they capture) require a mediumsampling rate on the order of a few kilo-samples per second to a fewMega-samples per second (MSPS) with medium resolution on the order of 8 to 10bits. Such requirement along with its inherent simplicity, make successiveapproximation register (SAR) ADCs the most attractive candidates for most RFIDapplications. Among different categories, SAR ADC uses minimal analogcircuitry and could be implemented with small silicon area and low powerconsumption [6]. Many research have been carried out on SAR ADCs at systemand circuit levels, to improve their performance in terms of power consumptionand area requirements. Improving the performance of SAR ADCs will bediscussed in details in Chapter 2.Another design technique that has proven promising for implementation of the16C ou nterTim e- m od e com p aratorT ime- to- dig ital  conver terSensor V ol tage-to- tim e converter(V TC )Processing unitA nal og variab l e Tim e- m od e variab l e D igital  variab l eT ime- mode anal og - to dig ital  conver terC ontrol l erFigure 1.8: Schematic diagram of a time-mode analog-to-digital converter.ADC block in passive RFID tags, is time mode signal processing (TMSP). In TMSP,voltage and current variables are converted to a time domain variable (i.e., the delaybetween two edges of a clock signal) [21]. The time domain variable can then beprocessed through an all-digital circuitry. Processing the information in digitaldomain facilitates a low power and compact implementation of the processing unitwhich is specifically beneficial in the context of passive RFID tags.As shown in Figure 1.8, a crucial building block of a TMSP system (includingthe time-mode analog-to-digital converter) is the voltage-to-time converter. VTCas the interface between analog and time domain, is responsible to receive theanalog signal and to convert it into an accurate time domain representation. Theperformance of the VTC in terms of linearity, input range, power consumption andlayout area directly affects the TMSP system and the overall operation of the RFIDtag. Circuit level design techniques to improve the performance of the VTC blockare discussed in details in Chapter 2.171.4 Summary of ContributionsAs mentioned in Section 1.3, the building blocks of a passive RFID tag arerequired to fulfill stringent requirements in order to guarantee a reliable tagoperation. Such strict requirements mainly stem from the absence of a dedicatedpower source for the tags and necessitate sophisticated design technique to copewith the very tight power budget of the passive tag. Apart from low powerconsumption, the tag circuitries are required to be area efficient. Small form factorfor the integrated circuits is of paramount importance in the context of passiveRFID tags as it leads to lower manufacturing cost. Also, there are strict limitationson the size of the tags in passive RFID applications (e.g, human health-caremonitoring, inventory and supply chain management, etc.).In this thesis, data and power converter as two crucial building blocks of apassive RFID tag are studied at a circuit level perspective. With an emphasis onlow power consumption and small silicon area, design techniques are proposed toimprove the performance of these blocks. The circuits using the proposedtechniques are designed and their performance are verified through simulationand/or measurement. A summary of the contributions of this work are presentedin the following sections.1.4.1 Proposed Ultra-Low-Power SAR ADC with an Area-EfficientDAC ArchitectureTo reduce the power consumption and layout area of the SAR ADC, adigital-to-analog converter architecture is proposed that employs two rail-to-raillow-power unity-gain buffers and only 4 minimum-size capacitors instead of theconventional binary-weighted capacitor array. Thereby, power consumption andarea are drastically reduced by virtue of lower switching activity and smaller sizecapacitor array. The proposed 8-bit SAR ADC is designed and simulated in a0.13µm CMOS process. Simulation results show that for a 2.4 kHz (12.4 kHz)input signal while sampling at 25 kHz, the ADC achieves an effective number ofbits (ENOB) of 7.9 (7.8), consumes 290 nW (350 nW) form a 0.8 V analog supplyand a 0.6 V digital supply, and achieves a figure of merit (FOM) of48 fJ/conversion-step (62 fJ/conversion-step). Details of the proposed SAR ADC18design are discussed in Chapter Proposed Highly Linear Wide Input Range Voltage-to-TimeConverterTo achieve good performance for the VTC new design techniques areinvestigated. High linearity is achieved by re-ordering the charge and dischargecycles, i.e., initially charging the storage capacitor by a current proportional to theinput voltage and subsequently discharging it at a constant rate. Through use ofdegenerated input devices driven by level shifted versions of the input voltage, alinear voltage-to-current converter is proposed to produce a linear voltagedependent current for almost the entire input range. The proposed VTC isdesigned and fabricated in a standard 0.13 µm CMOS technology. For a supplyvoltage of 1 V at 80 MHz sampling frequency, the measurement results confirm asmall linearity error of below ± 1.4 % for the entire input range (0∼1 V) whilethis value is below ± 0.5 % for the input range between 0 and 0.95 Vcorresponding to a resolution of 7.38 ENOB. The entire VTC occupies an area of60µm×60µm. The analog portion of the VTC consumes 16.8 ∼22.8 µW for0 V ∼ 1V input range and the digital part consumes 1.8 µA at 80 MHz samplingrate. Details of the proposed VTC design are discussed in Chapter Efficiency Enhancement Techniques for RectifiersThree different techniques to enhance the efficiency of rectifiers for RFID tags arepresented. These techniques extend the low-voltage (low-power) operation rangeof rectifiers.1. Proposed Efficient Rectifier with Low-Voltage Operation: A new switchingscheme is proposed to enhance the power efficiency of the conventional 4transistor (4T)-cell rectifier. By switching the gate of charge-transfer transistors tothe intermediate nodes of preceding and succeeding stages, low on-resistance andsmall leakage current are obtained simultaneously. To further improve thelow-voltage operation capability, an external gate-boosting technique is alsoapplied to the proposed design which enables an efficient operation for inputvoltage levels well below the nominal standard threshold voltage of MOS19transistors. The two proposed rectifier architectures are designed and laid out in astandard 0.13-µm CMOS technology. For a 950 MHz RF input and 10 kΩ outputload, post-layout simulation results confirm a PCE of 74% at −10 dBm and 57%at −26 dBm for switched 4T-cell and gate-boosted switched 4T-cell, respectively.While the PCE of the proposed switched 4T-cell rectifier compares favorably withthat of the state-of-the-art rectifier designs, the gate-boosted version achieves arelatively high PCE while operating with a very low input power. Details of theproposed rectifier design are discussed in Chapter 3.2. Proposed Rectifier with Low Start-Up Voltage: To enhance the powerconversion efficiency of the conventional rectifier when the input voltage (power)is low, appropriate gate-drive voltages for each stage of the rectifier are generatedusing a chain of auxiliary floating rectifier cells. Floating rectifier cells areoptimized to generate shifted versions of the intermediate voltage of each stage toboost the drive voltage of NMOS and PMOS switching transistors andaccordingly improve the PCE. The proposed rectifier architecture is designed in astandard 0.13 µm CMOS technology. For a 950 MHz RF input and 50 kΩ outputload, simulation results show that the rectifier achieves a PCE of 54 % for a smallinput signal with an amplitude of 200 mV (−19 dBm) which is well below thenominal standard threshold voltage of MOS transistors in the technology used.Details of the proposed rectifier design are discussed in Chapter 3.3. Proposed Rectifier with an Extended High-Efficiency Region of Operation:Using quasi-floating gate technique, a gate-biasing scheme is proposed to providea relatively flat power conversion efficiency curve for a wide input voltage (power)range. The proposed technique also enables an efficient operation for input voltagelevels well below the standard threshold voltage of the MOS switching transistors.Appropriate bias voltages for different stages of the rectifier are generated througha chain of low-power bandgap reference generators which impose minimal powerand area overhead. The proposed rectifier architecture is designed and laid out in astandard 0.13 µm CMOS technology. For a 2.4 GHz RF input frequency and 30 kΩoutput load, post-layout simulation results of the circuit show that a maximum PCEof 66.7 % is achieved for an input signal with an amplitude (power) of 0.45 V(−8 dBm). While a high PCE of 60 % is achieved for input voltage (power) levels20as low as 0.25 V (−15 dBm), PCE maintains above 60 % for a wide input voltage(power) range from 0.25 V to 0.7 V (−15 dBm to−3 dBm). Details of the proposedrectifier design are discussed in Chapter Proposed Dual-Band Approach for Wireless Power HarvestingA wide band matching network is greatly desired for wireless power harvesting inthe context of passive RFID tags. Typically, RFID tags are optimized for a singlefrequency band. Such an approach makes the tags inoperable at other frequencybands as the power harvesting unit fails to provide sufficient energy for properoperation of the tag due to excessive power reflections at the tags input. Due togeometrical limitations and size issues, it is practically impossible to incorporatean antenna that operate at a wide frequency range, or to allocate separate antennasfor different bands. A viable approach is then to modulate the input impedance ofthe tag (rectifier) in response to the variations of the transmitted frequency ratherthan adjusting the antenna impedance. Built upon efficiency enhancementtechniques developed in this thesis, a dual-band approach in RF rectifiers isproposed. Through dynamically adjusting the input capacitance of the rectifier, adual-band input matching scheme is developed which enables efficient powerdelivery at two distinct frequencies. Details of the proposed dual-band approachare discussed in Chapter Proposed High-Sensitivity Fully Passive Wake-Up RadioAs mentioned in Section 1.3, in power-limited consumer wireless devices such asRFID systems, biomedical implants, wireless sensor networks, wearablecomponents, and Internet of Things, energy saving is a critical design task. Thesedevices are usually battery operated and have a radio transceiver that is typicallytheir most power hungry block. Wake-up radio schemes can be used to achieve areasonable balance among energy consumption, range, data receiving capabilitiesand response time. The wake-up radio (WUR) is comprised of a high-efficiencyrectifier that rectifies the incident RF signal and drives subsequent circuit blocksincluding a low-power comparator and potentially a reference generators; and atthe same time detects the envelope of the on-off keying (OOK) wake-up signal.21The WUR does not need an external power source as it extracts the entire energyfrom the RF incident signal received at the antenna. A proof-of-concept systembased on a custom 0.13m CMOS rectifier is designed that supports addressing andshort commands communication. Experimental results demonstrate the sensitivityof −21 dBm (without matching circuit) at 868 MHz. Using matching circuit asensitivity of −33 dBm can be achieved. Details of the proposed passive WURare discussed in Chapter Feasibility Study of Backscattering For TelemonitoringAs mentioned in Section 1.2, backscattering is a power efficient transmissionscheme and is commonly used for passive RFID tags at short communicationdistances. The feasibility of backscattering for health-care telemonitoring using astent as a the tag’s antenna is investigated. Theoretical analysis suggest thatbackscattering scheme outperforms telemonitoring schemes based on activetransmitters in terms of power consumption and reliability. A proof-of-conceptprototype is designed and implemented and a set of experiments are carried out tostudy the feasibility of backscattering using an antenna stent (inductive stent).Details of this feasibility study are discussed in Chapter 4 and [8].1.4.7 Proposed Ultra-Low-Power Voltage-Controlled Ring OscillatorAs discussed in Section 1.3, the clock generator is an integral part most passiveRFID tags. Simple oscillators typically constitute the core of such clock generatorcircuits. In the context of RFID tags, the oscillator need to consume low powerand should be capable to operate with low supply voltage. As a proof-of-conceptto fulfill the aforementioned requirements, an ultra-low-power CMOSvoltage-controlled ring oscillator (VCRO) is proposed. The design techniquesemployed in the high efficiency rectifiers are adopted to achieve the ultra lowpower consumption. The proposed two-stage VCRO is designed and laid-out in astandard 0.13 µm CMOS technology. A voltage level converter is also presentedto interface the output of the proposed VCRO with the succeeding circuitry. Theentire VCRO core occupies an area of 25µm×20µm. For a supply voltage of aslow as 140 mV, an output frequency of 4 MHz is achieved at 3.6 nW power22R ectif ierSensorADCTransceiverB a c k s c a t erri n gor (ASK  mod / d emod ) memoryB aseb and  p rocessing u nitC l ock G en.M atchingcircu itA ntenna Passive R F I D  TagThree efficiency enhancement techniques (Chapter 3)Dual-band approach (Chapter 3)Passive WUR (Chapter 4)`Ultra-low-power VCRO (Chapter 5)Ultra-low-power SAR ADC (Chapter 2)Backscattering feasibility study (Chapter 4) Highly-linear VTC (Chapter 2)Figure 1.9: Schematic diagram different blocks of a passive RFID tagaddressed in this thesis.consumption. Although the intended application for the proposed VCRO ispassive RFID tags, the architecture can be used in other ultra-low-powerapplications. Details of the proposed Ultra-Low-Power VCRO are discussed inChapter 5.1.5 Thesis OutlineIn this thesis, design techniques to improve the performance of the main buildingblocks of a passive RFID tag are presented. The proposed designs involve circuittechniques to improve the performance of the associated blocks with an emphasison low power consumption and layout area. Figure 1.9 shows how the contributionof this thesis address the different blocks of a passive RFID tag.The organization of this thesis is as follows: Chapter 2 provides an overviewof analog-to-digital converters for RFID tags. An ultra-low-power SAR ADC isproposed. TMSP concept is reviewed and a highly linear wide input range VTC as23the front-end for such systems is introduced and studied in details.Chapter 3 reviews wireless power harvesting schemes in the context of RFIDsystems and wireless sensor networks. Three different efficiency enhancementtechniques are applied to differential rectifiers and their performances are studied.Based upon the techniques developed, a dual-band approach is introduced whichenables efficient power delivery to the tag at two distinct frequencies.In Chapter 4 wake-up radio as an attractive approach to enable a power efficientreceive mode for the passive tags and wireless sensor nodes, is reviewed and afully-passive high-sensitivity wake-up radio is presented. Also, as a power efficientapproach during the transmit mode, feasibility of backscattering in the context ofwireless telemonitoring using an antenna stent is studied.Chapter 5 proposes an ultra-low-power VCRO which serves as the core of theclock generator unit. The proposed VCRO employs the techniques developed forthe high efficiency rectifiers to achieve low voltage operation and consequently,low power consumption.Chapter 6 provides the concluding remarks, summary of achievements andfuture works.24Chapter 2Efficient Data Converter Circuitsfor RFID ApplicationsAs mentioned in Chapter 1, the operation of a sensor-enabled RFID tag isdependant on an on-chip ADC. ADCs are among critical components that areused in most of nature interface systems and usually consume a fair share of theoverall power and chip area budget. Therefore, reducing the power consumptionand silicon area requirements of the ADC can significantly benefit an efficient androbust tag design.Among different categories of analog-to-digital converters, successiveapproximation register ADC is the most attractive candidate in virtue of itsminimal use of analog circuity. With the comparator and a capacitive DAC arraybeing the only analog blocks, SAR ADCs perform the conversion in a powerefficient manner. SAR ADCs are capable of providing high speeds with mediumresolution which suffices the requirements of most RFID applications. Power andarea efficient implementation of SAR ADCs will be discussed in this chapter.Another promising technique to efficiently implement the analog-to-digitalconversion is the time-mode converters which will be discussed in this chapter.25V inV D A CV SH SARresetsampleS/HVSSS0 S2S1 SnVREFOUT D1...D8S0...SnC0 C0 2C0 2(n-1)C0DAC01 10 1 1 tV D A CV SHVREF/2VinFigure 2.1: Schematic diagram of a conventional SAR ADC [6].2.1 Overview of Successive Approximation RegisterAnalog-to-Digital ConvertersThe binary capacitor array SAR ADC architecture was first introduced in 1975 byGary L. Baldwin in [22] and [23]. SAR ADC performs the binary search algorithmin a feedback fashion in order to resolve the analog input. More specifically, asshown in Figure 2.1, the input is sampled during the first step. The sampled inputis initially compared with half the reference voltage (Vref/2). Depending on thethe output of the comparator, SAR unit provides the appropriate switching signalfor the capacitive DAC during the charge recycling step. The sampled input iscompared with the updated DAC voltage (VDAC) until all the bits are resolved.Generally, in a SAR ADC there are two major contributors to powerconsumption: comparator and charging/discharging of the DAC array. TypicalSAR structures use bulky DAC capacitive arrays which are usually the area andpower bottleneck of the design. From the power dissipation perspective, in orderto sample a full-scale sine wave at the Nyquist frequency, a traditional capacitivearray on average consumes [24]:Ptot = Pin +Pref =CT ·V2RTs+CT ·V2R2Ts(2.1)26where Pin is the power drawn from the input, Pref is the average power drawn formthe reference generator for charge redistribution, CT is the total capacitance of thearray, VR is the reference voltage and Ts is the conversion period. Accordingly,layout area and power consumption grow exponentially (CT = 2n ·C0 where C0 isthe unit capacitor) with the number of bits (n) which compromises the advantageof SAR ADCs, especially as the number of bits increases.Extensive studies have been carried out on energy-efficient DAC architectures.Ginsburg and Chandrakasan [25] propose the capacitor splitting scheme whichreduces the average switching energy of the array by splitting the most significantbit (MSB) capacitor into n−1 binary scaled sub-capacitors (where n is the numberof bits). Consequently, for down transitions [25], the charge on the MSB capacitorwill be restored for further conversions. Although the proposed techniquesignificantly saves the switching energy for small output codes, it fails to performequally well for higher output codes where less down transitions occur. Moreover,this approach is still dependent on a bulky DAC array and requires twice as manyswitches as the conventional scheme.In another structure, Choi and Tsui [26] reduce the average switching energyof the capacitive array by separating the decoding of MSB and least significantbit (LSB) through using two different capacitor arrays with unequal size.However, the low-power consumption is achieved at the cost of two additionalclock cycles which poses energy overhead due to additional comparison stepsrequired. Moreover, the layout occupies a higher area than that of the traditionalarchitecture due to MSB DAC, memory storage with logic and the extracomparator.Sauerbrey et al. [27] use an extra shunt capacitor in the capacitive array toadjust the signal levels in order to facilitate low voltage operation. The DACvoltage converges to the input voltage with each conversion and therefore, theleakage of the switches are avoided for small supply voltages. This architecturerequires a dedicated sample-an-hold unit as the input voltage is not directlysampled on the capacitive DAC.Agnes et al. [24] use an attenuation capacitor to reduce the total size of thecapacitive array and consequently the energy drawn from the reference. Kianpouret al. [28] divide the conversion steps into coarse and fine phases while a resistive27DAC is used for coarse conversion and a capacitive DAC is used for fineconversion. Only two capacitors are used for fine binary search and therefore,layout area and power consumption are reduced.[29] drives the bottom plate of DAC capacitors through inverters and use anattenuation capacitor to keep the peak-to-peak differential output voltage of theDAC within the rail to rail range. Geng et al. [30] use a dummy capacitor whichis switched between GND and the common-mode voltage therefore reducing thetotal capacitance of the array to half of the value required for a convectional DAC.Hu et al. [31] samples the input on one DAC use a secondary auxiliary DAC tocompensate the voltage error caused by the parasitic capacitors at the main DAC.MSB is resolved by the auxiliary DAC and the rest of the bits are decided by themain DAC. Therefore, the total capacitance of both DACs is the same as that of aconventional DAC. The proposed scheme allows using half the reference voltageto resolve the entire range and therefore brings a significant power reduction.In general, there are several common techniques to reduce the powerconsumption and area requirements of the capacitive DAC [31, 32] namely:1. Use of attenuation capacitor to reduce the size of the DAC [33]. Thistechnique adversely affects the accuracy of the capacitive DAC.2. Charging the DAC through several intermediate voltages [34]. This methodposes extra complexity overhead for intermediate voltage generation.3. Recycling the charge stored in the capacitors [25, 35]. This scheme requirestwice as many switches compared to the conventional approach.4. Performing monotonic switching scheme [36]. This method in notapplicable to single-ended architecture.5. Using merged capacitor switching method [37]. This method is sensitive tothe reference voltage accuracy.6. Employing VCM-based switching method [38]. This method is sensitive tothe reference voltage accuracy.This report proposes an area-efficient DAC architecture that both reduces thepower consumption and the layout area. The proposed DAC architecture consists28of four minimum-sized capacitors and two low-power buffers for which the binarysearch algorithm is carried out at no extra cost in terms of clock cycles andcomparison steps. Also, the use of four minimum-sized capacitor DAC relaxescapacitor mismatch and parasitic requirements. To further save area and powerconsumption, the two low-power buffers are dually used as the comparatorpreamplifier blocks in an open-loop fashion [6].2.2 Ultra-Low-Power SAR ADC with an Area-EfcientDAC Architecture1The operating principles of a SAR converter are well known [22–38]. Simplyput, the capacitive DAC main task is to provide the appropriate voltage levels toimplement the binary search algorithm as shown in Figure 2.1. The algorithmstarts by setting the MSB to 1 and all other bits to 0. Thereby, Vin is compared withVref/2. Charge recycling is then carried out based on the output of the comparator,i.e., if D1 (comparator output) is high, the second largest capacitor is charged toVref setting VDAC =3Vref4 . This is called an up transition. Conversely, if D1 islow, the largest capacitor is discharged and the second largest one is charged toVref which is called a down transition. The sequence continues until all the bitsare decided. The binary search algorithm described above can be interpreted asfollows: two voltage levels are dened as Vtop and Vbot which are the upper andlower voltage bounds at each clock cycle and they converge toward Vin with eachbit decision. Vmid is then produced from Vtop and Vbot as:Vmid =Vtop +Vbot2(2.2)For the mth bit, this voltage, i.e., the output of the DAC, is compared with Vinand the comparison result Dm updates the value of Vtop or Vbot in the next clockcycle such that if Dm = 1 (’up’ transition), Vtop maintains its old value while Vbot isshifted up to Vmid. Conversely, if Dm = 0 (’down’ transition), Vbot retains the oldvalue and Vtop is shifted down to Vmid. The procedure continues until all bits areconcluded.1The material presented in this section is based on [6].29C top 1C b ot1 C b ot2C top 2V RE F V RE FB2St1 St2Sb1 Sb2S1S2S3S4S5S6S7S8V T O P 1 V T O P 2V B O T 2V B O T 1V M ID1 V M ID 2d own transitionu p  transitionVTOP1VBOT1VMID1VMID2VTOP2VTOP1VBOT2 VBOT1VINVMID1B it1 = 0 B it2 = 0 B it3 = 1d own transitionVTOP2VBOT2VREFVGNDB1Figure 2.2: Schematic of the proposed DAC architecture and its timingdiagram [6].As shown in Figure 2.2 the algorithm can be implemented using four capacitorsand two unity gain buffers. For a given output of ’001...’ (where the first three bitsare evaluated) the operation of the proposed DAC architecture can be described asfollows:Each bit decision cycle is divided into two time slots, comparison cycle andcharge recycling cycle. During each comparison cycle one capacitor set(Ctopi,Cboti)performs as a capacitive divider producing Vmid =Vtop+Vbot2 and theother set holds the same two voltage levels(Vtop,Vbot)that are being processed(the two capacitor sets interchangeably switch these two tasks in subsequentcomparison cycles). Voltage levels are then updated at charge recycling cycle30based on the previous decision. At the beginning of conversion (sampling phase),(S1,S7) and (S2,S8) are on, charging (Ctop1,Ctop2) and (Cbot1,Cbot2) to VREF andVGND, respectively. Then in the first comparison cycle, (S1,S2) and (S7,S8) turnoff and (St1,Sb1) turn on to form a capacitive divider (from Ctop1,Cbot1) whichgives VMID1 =VREf2 . Note that as stated earlier when each capacitor set is active,i.e., providing VMID for comparison(Ctop1,Cbot1), it is essential that the othercapacitor set(Ctop2,Cbot2)holds the same voltage levels being searched at thetime, which in this case is VTOP2 = VREF and VBOT2 = 0.Then VMID1 is compared with VIN which yields D1 = 0 based on theassumption made for the first three bits. Voltage levels are updated in thesucceeding charge recycling cycle. As mentioned earlier for each ’down’transition Vbot maintains its value and Vtop is shifted down to VMID. For thispurpose, (St1, Sb2) and (S4, S5) are switched on while all other switches are off.Buffer B1 provides a copy of VMID1 for Ctop2 thus shifting Vtop2 down to VMID1.At the same time, buffer B2 returns Cbot1 voltage back to VBOT1 = VGND in orderfor(Ctop1,Cbot1)to have a copy of new voltage levels that are to be processed inthe next comparison cycle. At this point, Vtop1 = Vtop2 =VREF2 andVbot1 = Vbot2 = 0 and the capacitors are all set for the next comparison cyclewhere (St2, Sb2) turn on and all other switches are off. The capacitive dividerproduces VMID2 =VTOP2+VBOT22 =VREF4 . This voltage is compared with Vin andresults in D2 = 0 which corresponds to a ’down’ transition. In the next chargerecycling cycle, (St2, Sb1) and (S3, S6) are switched on. Buffer B2 shifts VTOP1down to VMID2 =VREF4 and buffer B1 returns VBOT2 back to VGND such thatVtop1 = Vtop2 =VREF4 and Vbot1 = Vbot2 = 0. Therefore, in the next comparison(Ctop1,Cbot1) produce VMID1 =VREF8 which yields D3 = 1. In the next chargerecycling cycle (St2, Sb1) and (S3, S6) are switched on. Buffer B1 pulls VBOT2 upto VMID1 =VREF4 and buffer B2 returns VTOP1 back toVREF2 . All the next bits aredecided in the same manner.In terms of power, the proposed architecture outperforms the conventional SARarchitectures. As the algorithm suggests, during a conversion cycle, each of the twobuffers contributes in the charge recycling process for at most n times. So, the total31charge drawn from VREF during the conversion cycle is:Qtot = 4 ·n · Ib ·TCR (2.3)where n is the number of bits, Ib is the bias current for each buffer stage, TCRis the charge recycling period and the factor ’4’ accounts for the two, two-stageamplifiers. The two factors governing Ib are the required voltage gain and speed.To achieve the desired resolution, the buffer output has to settle within 12 LSB of theinput, which for an 8-bit resolution requires an open loop gain on the order of 50to 60 dB. The two-stage low-power amplifier (described in Section 2.2.1) providessuch a gain by drawing only 124 nW from VREF. Regarding speed, since the loadcapacitance is minimum-sized, slew-rate is not that critical and charge-recyclingperiod (VCR) can be very short.The aforementioned algorithm is implemented in the proposed ADC with someminor amendments. To further save power, the buffers turn off whenever theirservice is not required. This is achieved by shutting off the supply current (thebuffer architecture is described in Section 2.2.1). An example for such a powersaving mode is when the destination voltage, VTOP or VBOT is supposed to beupdated to VREF or VGND, respectively. In this situation the respective buffer willnot perform the task, instead one of (S1,S7) or (S2,S8) turns on to update VTOPor VBOT to VREF or VGND, respectively. This power saving scheme proves usefulparticularly for very large or very small inputs. For instance, for a very small outputcode starting with several consecutive ’0’s (0000...), at each charge recycling cycle,one buffer remains inactive until the first ’1’ is detected. The same goes for verylarge output codes.2.2.1 Comparator ArchitectureAs mentioned in Section 2.2, to further save area and power, the two buffersemployed in DAC are used as the preamplifier stages for the comparator byopening the loop through CLKcomp, as shown in Figure 2.3.At each comparison phase, one capacitor set provides VMID to be comparedwith VIN for which the appropriate clock (CLKcomp1 or CLKcomp2) goes high. Tobetter utilize the available hardware, the two amplifiers operate simultaneously to32CLKcompCLKcomp1,2CLK-latchCLK- preCLK- offOUT-OUT+OUTB1VINCLKcompVMID1VMID2CLKcomp1CLKcomp2B2 VINCLKcompCLKcompVMID1VMID2CLKcomp1CLKcomp2OUT+OUT-CLKcompFigure 2.3: Schematic of the proposed comparator and its timing diagram [6].V RE FV RE FCL K -l a t c hCL K -l a t c hO U TOUT+OUT-CL K -p r eCL K -p r eS LM n1 M n2M p 1 M p 2CL K -l a t c hFigure 2.4: Schematic of the low-power latch architecture [6].amplify the voltage difference between the input voltages. For this purpose VIN andVMIDi are applied to opposite terminals of B1 and B2. Thus, as one of OUT+/OUT-charges up to VREF, the other one is pulled down to VGND. This scheme brings atwofold benefit: on one hand, the pre-amplification phase would be twice as fast.On the other hand the overall comparator resolution is improved.Almost at the end of comparison cycle where OUT+ and OUT- are about their33V RE FVI N +VI N -I BCCOUTCL K - o f fCL K - o f fS b 1S b 2Figure 2.5: Schematic of the low-power amplifier [6].extreme voltage levels (note that clock periods are not drawn to scale inFigure 2.3), a very short pulse CLKpre, connects OUT+ and OUT- to the inputterminals of the regenerative latch as shown in Figure 2.4. CLKpre turns off after ashort period so that B1 and B2 do not drive the latch for the rest of the latch cycle.The buffer/amplifier architecture is shown in Figure 2.5. After the pre-amplifiedvoltages are properly delivered to the latch at the end of CLKpre, CLKoff goes highwhich turns the amplifiers off by shutting off the bias currents through Sb1,2.Latch phase starts simultaneously with CLKpre and the regenerative latchproduces a digital level output in a very short interval. At the end of process, SLresets the latch by connecting the input and output of the back-to-back inverters toset them close to VREF2 which speeds up the next latch operation. To further savepower, Mn1,2 and Mp1,2 perform the power-gating task by blocking the latch inputcurrent in inactive mode when CLKlatch is off.2.2.2 Sample and Hold ArchitectureA switched-capacitor clock-boosted architecture is used for the sample-and-holdcircuit due to its rail-to-rail capability and low-power operation. As shown inFigure 2.6, after a few clock periods, Cboost is charged to VREF and subsequentlyacts as a floating voltage source. At each sampling phase (CLKSAMPLE), Cboostconnects the gate-source terminals of Msample in such a way that: VGS = VREF.Therefore in sampling phase, the gate voltage of Msample will always be as much34V RE FC b o o s tC r e f r e s hCL K HCL K HCL K SAM P L EVI NM s a m p l eM d u m m y C s a m p l eSampling PeriodCL K SAM P L EM S1M S2M H2 M H1V G SV RE F- V RE FV G SCL K HCL K HCL K SAM P L ECL K SAM P L EFigure 2.6: Schematic of the Proposed sample-and-hold architecture andtiming diagram [6].as VREF higher than its source voltage, regardless of the value of VIN. Thispresents a rail-to-rail operation. On the other hand, in the hold phase, MH1,MH2turn on and MS1,MS2 turn off, providing a negative voltage between thegate-source terminals of Msample such that for the entire hold phase:VGS = −VREF. This negative bias alleviates the leakage current and fully isolatesthe sampled voltage from input fluctuations.CLKH can be picked from any of the clock signals already generated in thecircuit, however, for a better performance, it has to be a high frequency clock suchas CLKcomp. As shown in Figure 2.6, Crefresh updates the voltage on Cboost at everyCLKH. Mdummy is employed to cancel the charge-injection effect. However, specialcare has to be given to the size of Mdummy which is not the conventionalSizeMSample2due to the fact that the gate-source voltages that the two transistors experience arenot the same. Note that this architecture almost imposes no power consumptionpenalty as the current drawn from VREF is limited to the leakage current of Cboostand switching transistors and thus is on the order of few nano-Watts.2.2.3 Simulation ResultsThe proposed DAC/comparator architecture is designed and laid out in an 8-bit25kS/s SAR ADC in a 0.13µm CMOS technology. DAC capacitors are35Figure 2.7: Simulated DNL and INL at 25ks/s [6].Figure 2.8: Output spectra for input sine wave @ 2.24kHz and 12.4kHz [6].implemented by a metal-insulator-metal (MIM) structure with the unit capacitor of50 fF and the sampling capacitor is 500 fF.As shown in Figure 2.7, at 25kS/s the simulated differential nonlinearity (DNL)and integral nonlinearity (INL) are within 0.25 LSB and 0.5 LSB, respectively. Thespectra for an input full-scale sine wave at 2.24 kHz and 12.4 kHz are shown inFigure 2.8, for which the signal-to-noise and distortion ratio (SNDR)s of 49.4 dB(ENOB=7.91) and 48.8 dB (ENOB=7.81) are obtained, respectively.The entire digital circuitry is custom designed and dissipates 24 nW from a0.6 V supply. The total power consumption for 2.24 kHz and 12.4 kHz inputsine-wave are simulated to be 290 nW and 350 nW which exhibits a FoM of48 fJ/conversion-step and 62 fJ/conversion-step, respectively. A comparison ofthe proposed architecture with the state-of-the-art SAR ADCs is provided inTable 2.1.36Table 2.1: Comparison of the proposed SAR ADC with the state-of-the-artresults [6].[39]? [40]? [41]? [42]?? This work??Technology (µm) 0.18 0.18 0.13 0.13 0.13Supply Voltage (V) 1 (1) 0.9 1.2 1 A: 0.8, D: 0.6Sampling Rate fs (kS/s) 200 (100) 200 1000 100 25Input Frequency fin (kHz) 100 (50) 100 101 48.5 12.4ENOB (@ fin) 7.96 (10.55) 7.44 8.39 9.17 7.81Power Dissipation (µW) 19 (25) 2.47 150 1 0.35FoM† (fJ/conversion-step)381 (166) 65 437‡ 17 62?Measurement results. ?? Simulation results. † FoM = Pdiss/(2 · fin ·2ENOB) ‡ FoM = Pdiss/(fs ·2ENOB)2.3 Overview of Time-Mode Analog-to-DigitalConvertersEmerging deep sub-micron CMOS technologies are basically optimized to benefita digital implementation. As transistor dimensions constantly decrease with eachprocess node to facilitate higher integration, the reduction of applicable voltagelevels poses severe challenges to the performance of analog and mixed-signalblocks.To address the ever-increasing challenges of analog design in deep sub-micronCMOS technologies, TMSP has gained an extensive attention in recent years. ATMSP system converts the voltage/current signal to a modulated pulse width or aproportional time delay (in the form of the time difference between the risingand/or falling edges of a reference clock and delayed clock). The time modesignal (i.e., the proportional delay) could then be processed by a digital processingunit, therefore eliminating the need for the challenging analog blocks such asoperational amplifiers and comparators. Furthermore, an all-digital processfacilitates the implementation with smaller supply voltages, lower cost and higherintegration level. Owing to its numerous advantages over the conventional analogdomain processing, TMSP systems are recently being used in a wide range ofapplications including digital oscilloscopes and digital phase locked loop (PLL)s,implantable biomedical devices, sensor interface units, RADAR applications and37V ol tage(d igital )-to- Tim e converter(V TC / D TC )Tim e- m od e signal  p rocessing(TM SP)Tim e- to-vol tage(d igital ) converter(TV C / TD C )VinDinTin Tout VoutDoutt i m e  d o m a i nv o l t a g e  d o m a i n v o l t a g e  d o m a i n10 1. . . 110 . . . . . . 110 . . . 0 10Figure 2.9: Schematic diagram of a generic TMSP system.many more [21, 43–45].As schematically shown in Figure 2.9, a TMSP system generally consists ofthree main building blocks, namely the VTC, the time-mode-signal processing unitand the time-to-voltage converter (TVC). Similarly as shown in the figure, the inputto the system and its corresponding output can be digital signals, suggesting adigital-to-time converter (DTC) as the input block and a time-to-digital converter(TDC) as the output block.As the name suggests, the VTC (DTC) block is mainly responsible forconverting the input voltage signal to the proportional time difference (delay).Other useful functions such as voltage-to-time addition and voltage-to-timeintegration could also be performed at the interface between the voltage and timedomain [21, 46].The time-mode signal processor is the core of the TMSP systemand allocates the time-mode counterparts of the main building blocks of aconventional analog/mixed-signal system such as comparators, amplifiers,counters, ring oscillators, delay locked loops (DLL)s, etc. [47, 48]. Finally, theTVC (TDC) converts the processed time-mode signal back to an analog (digital)signal by quantizing the time difference (delay) between the appropriate edges ofclock signals and producing a proportional analog voltage (digital code). Toperform the conversion between time and voltage (digital) domain, the TVC(TDC) unit mainly relies on Vernier delay lines and DLLs to produce accuratereference clock signals [49].382.4 Highly-Linear Wide Input Range Voltage-to-TimeConverter for Time-Mode Signal ProcessingAs discussed in Section 1.3, TMSP is desirable alternative for voltage domainconventional analog-to-digital converters. Transferring the processing load todigital (time) domain is particularly beneficial in the context of RFID tags as itfacilitates low-power and small-area implementation of the analog-to-digitalconverter. As the interface between the voltage and time domains, the VTC unitplays a key role in TMSP systems and its performance directly affects that of theentire system. Among various criteria, high linearity and wide input range are twocrucial performance metrics a VTC has to offer in most of applications (speciallyin time-mode data converters). In this work, through re-ordering thecharge/discharge cycles in conventional current-starved VTC and by usingdegenerated input devices driven by shifted versions of the input voltage, a VTCis proposed to address both high linearity and wide input range simultaneously.2.4.1 Conventional Current-Starved VTCAs mentioned in Section 2.3, in order to obtain an accurate time domainrepresentation of the input voltage signal, the VTC block has to provide a linearrelationship between the input voltage and the corresponding output delay.Typically, the so-called current-starved (CS) inverter is the most attractivecandidate to perform the voltage-to-time conversion in many applications due toits simplicity.A generic current-starved VTC is shown in Figure 2.10a. As seen in thefigure, a basic CS-VTC incorporates two inverters in cascade, with a fixedcapacitor placed at the output of the first inverter. During the low signal at clkref(charge cycle), the storage capacitor Cstore is charged through MP to VDD settingclkdel = 0 at the output of the second inverter. Note that MP and Cstore aredesigned so as to guarantee Vcs = VDD within the charge cycle. Upon arrival ofthe rising edge of clkref, Cstore starts to discharge through Mn and Min. The secondinverter performs as a comparator, mountainously comparing its input voltage Vcswith its internal threshold voltage Vth. Once the constantly dropping Vcsintersects Vth, the second inverter triggers to set clkdel = 1 as schematically shown39clkrefVinclkdelC s t o r eVt hVCSVinI chg VCSI dischgVCSC S  V T C ch arge cy cle d is ch arge cy cleM pM nM i nVDD(a)clkrefVCSV t hclkdeldela yVintdel 0 del1d i s c h a r g e  c y c l edel it 0VDDΔV(b)Figure 2.10: Conventional current-starved VTC. (a) Circuit level schematicfor charge and discharge cycles, (b) Timing diagram.in Figure 2.10b. Note that, as opposed to the charge cycle, the discharge current(i.e., the dropping rate of Vcs) is controlled by the input voltage Vin, modulatingthe drain-source resistance of Min or equivalently, the discharge current Idischg. theresulted delay is measured between the rising edge of clkref (t0 in Figure 2.10b)and the rising edge of clkdel which is (inversely) proportional to the input voltageVin. More specifically, (disregarding the minor effect of Vcs variations on Idischg)the delay is given by:delay =Cstore ·∆VIdischg(2.4)where, ∆V = VDD−Vth (as shown in Figure 2.10b) and Idischg is related to the40input voltage Vin by Idischg = GM,in × Vin (where GM,in is the large signaltransconductance of the input transistor Min). According to Equation 2.4, thereare two issues which severely prevent a linear relation between the resulting delayand the input voltage Vin. Firstly, even for a perfectly linear relationship betweenIdischg and Vin (i.e., a constant GM,in for the entire input range), Equation 2.4suggests that delay is inversely proportional to Vin. More specifically, assuming aconstant GM,in, delay is given by:delay =kVin(k =Cstore ·∆VGM,in)(2.5)Furthermore, the transconductance of Min (GM,in) is not constant during thedischarge cycle. In other words, Idischg is a non-linear function of both Vin and time.As schematically shown in Figure 2.11, for small enough input voltages (Vin <VX +Vth,Min), both Mn and Min start conducting in saturation at the beginning ofthe discharge cycle since Vcs = VDD. As long as both Mn and Min are in saturation,Min draws a rather constant current proportional to (Vin−Vth M,in)2. The cascodetransistor Mn assists in establishing a constant current by shielding the drain of Minform the voltage variations of Vcs (i.e., ∆VX  ∆Vcs). However, the constantlydropping Vcs will eventually push the transistors into triode region compromisingthe constant discharge current. As the gate of Mn is connected to VDD, it will entertriode before Min does, coupling Vcs variations on VX. With further decrease inVcs, Min enters triode which completely eliminates the established constant current.As schematically shown in Figure 2.11 for a given Vin, the transition instants areinput dependent and if occur before the trigger point (Vcs = Vth,inv) will exacerbatethe non-linearity. Note that typically a weak NMOS with a small aspect ratio (Mauxas shown in Figure 2.11) with its gate tied to VDD (or its drain) is placed in parallelwith the input transistor to assist discharging the storage capacitor for small inputvoltages.Based on the above discussion, discharge current is a non-linear, time-variantfunction of the input voltage which severely complicates obtaining a closed formexpression for Idischg versus Vin. For a clock frequency of 80 MHz, Cstore = 100 fFand VDD=1V, the simulated delay time versus input voltage is shown inFigure 2.12. The average discharge current produced by Min (excluding the41VinC s t o r eVCSM nM i nVDDM a u xI dischgV t h , inv  ≈ V D D / 2XVt h , i nvV XVCSI d i s c h gVDDtts a ts a tt r is a tVi nt r it r iVt h , M i nVt h , M nM nM i nt delt 0Figure 2.11: Schematic diagram of transient discharge current and voltagelevels of the current-starved VTC.current drawn by Maux) versus the input voltage is also shown in the figure. Asshown in the figure, the linear relation between the delay and input voltage occursfor a very narrow range of input voltages typically located in the middle of theinput range. The non-linear drain current of the input device (Min) averagedduring the discharge cycle is also shown in the figure. As can be seen from thefigure, this current complies with the Id-Vgs curve of an NMOS and therefore, theinput device fails to contribute in the discharge of the storage capacitors for inputvalues smaller than its threshold voltage, produces a non-linear current in thesaturation and is pushed to triode region for large input values.It is worth mentioning that due to its simplicity, current-starved VTC is still themost attractive candidate in applications where a small input range is required. Anexample of such applications in which the current-starved VTC is widely used isthe voltage-controlled delay unit (VCDU) in DLLs.Numerous studies exist in the literature targeted to improving the performanceof CS-based VTCs. Pekau et al. [50] employ several parallel current starvingdevices along with source degeneration in order to simultaneously improve thelinearity and voltage sensitivity. The proposed VTC achieves a linear input rangeof 200 mV (0 ∼ 200mV for a supply voltage of 1.2V) at a sensitivity of 2.5 ps/mV(2% error). Keskin [51] enhances the linear range through incorporating two delaylines in parallel such that the input voltage is applied to the positive supply of oneand to the negative supply of the other. The desired output delay is extracted fromthe output of either delay lines according the input voltage through use of two420 0.2 0.4 0.6 0.8 11234input voltage (V)delay time (nS)2468discharge current ( µ A )Id,MinlinearregionFigure 2.12: Simulated delay-time and discharge current versus input voltagefor the conventional current-starved VTC.decision comparators. Although the design presented in [51] achieves a rail-to-railinput range, the resulted delay is still dependent on the resistance of PMOS/NMOSdevices in triode region and is therefore not perfectly linear. Macpherson et al. [52]use a voltage controlled tunable MOSCAP in parallel with the starving NMOS tocontrol the gain (sensitivity) of the CS VTC and achieves a 100 mV linear rangewith a tunable gain.2.4.2 Proposed Linearization TechniqueBased on the discussion provided earlier, in order to achieve a wide linear inputrange for a dual-slope integrating VTC (which operates based on charging anddischarging a capacitor), two requirements have to be satisfied:1. A linear relation between the delay and the charge (or discharge) current hasto be established (as opposed to Equation 2.4).2. A linear relation between the charge (or discharge) current and the inputvoltage (i.e., a constant Gm voltage-to-current converter) has to beestablished.In view of Equation 2.4, the first requirement (i.e., a linear relation betweenVin and Idischg) could be met by reversing the order of input proportional chargeand discharge, i.e., initially charging the storage capacitor at a rate proportionalto the input and subsequently discharging it at a constant rate. Such a scheme43C s toreV C Sc l k r e fc l k r e fc l k d e lcompIchgId i s chgVin G mVr e f(a)clkref d i s c h a r g e  c y c l eVrefV csVcs0Vcs ic h a r g e  c y c l eclkdel Vindel0 del it 0dela y tǻV 0ǻV 52Tc l k(b)Figure 2.13: Proposed charge and discharge scheme. (a) Circuit levelschematic, (b) Timing diagram.is schematically shown in Figure 2.13a where Cstore is initially charged throughthe variable current source at a rate proportional to the input voltage ( i.e., Ichg =Gm×Vin). Cstore is subsequently discharged at a constant rate and the comparatortriggers clkdel once Vcs = Vref. Without lose of generality, one can assume Vref = 0,therefore the capacitor voltage at the end of charge cycle is:Vcs|t0 =Gm ·Vin ·∆TCstore(∆T =Tclk2)(2.6)Therefore, as shown in Figure 2.13b, the delay is given by:44MpMi nIdVin(a)0 0.2 0.4 0.6 0.8 1246810input voltage (V)drain current ( µ A ) triodesatlinearrangeNPcut−off(b)Figure 2.14: NMOS input device with diode-connected load. (a) Circuit levelschematic, (b) Drain current versus input voltage.delay =Cstore ·Vcs,t0Idischg= k′ ·Vin(k′ =Gm ·Tclk2 · Idischg)(2.7)According to Equation 2.7, for a constant Tclk and Idischg, a linear delay profilecould be obtained provided that Gm remains constant regardless of Vin variations.Extensive studies on constant-Gm input stages exist in the literature [53–56].The well-known complementary input architecture suffers from strict n-channeland p-channel matching requirements and typically needs sophisticated gm controlcircuitry. The dual n-channel/p-channel approach also requires a control unit tocancel the undesirable gm variations. Generally, the complexity associated withsuch designs stems from the fact that the input stages need to satisfy both small-signal and large-signal requirements simultaneously. However, in the context ofan integrating VTC where the input is either sampled or its variations is negligibleduring a clock cycle, a simpler approach will suffice.An NMOS input device with a diode-connected load along with its simulateddrain current for the entire input range are shown in Figure 2.14a and Figure 2.14brespectively. As shown in the figure, a narrow linear region of the drain currentexists in the middle of the range where Min is in saturation. The drain-current curvesuggests that if the saturation region is extended and the non-linear sub-threshold(cut-off) and triode regions are avoided, one can get a linear current profile forthe entire range. Such an approach is schematically shown in Figure 2.15 wherethe drain currents (of Figure 2.14b) are primarily linearized (saturation region is450 0.2 0.4 0.6 0.8 112345input voltage (V)current ( µ A )IpIsumInNFigure 2.15: shifted drain currents of an NMOS device and summation of theshifted curves versus input voltage.M sM nIs u mVin MpVinR S R SVn VpIpIn DFigure 2.16: Schematic diagram of the circuit level implementation of theproposed constant-Gm voltage-to-current converter.extended), shifted to the left and right by certain amounts and then added together.As shown in the figure, the summation current Isum is a linear function of the inputvoltage Vin. Figure 2.16 schematically shows the circuit level implementation ofthe proposed scheme where the input is applied to the two input devices Mn andMp. The source degeneration resistors Rs, extend the linear region of operationof Mn and Mp. The drain currents are subsequently shifted to the right and leftthrough voltage level-shifters Vn and Vp which add a negative and positive shiftto the input voltage Vin respectively. Finally, the shifted currents In and Ip aresummed through the diode-connected PMOS, Ms.46Obviously, in order to obtain a linear current-voltage profile, the value of theshifts Vn and Vp have to be designed carefully. The positive level shifter Vp isresponsible to eliminate Mp’s sub-threshold (cut-off) region of operation bycancelling its threshold voltage. Ideally, in order to avoid the non-linear behaviourof Mp at the edge of inversion (point P in Figure 2.14b), Vp is designed slightlylarger than the threshold voltage of Mp, i.e:Vp = Vth,p +Voff,p (2.8)where, Voff,p is the offset voltage intentionally added to do away with the non-linearportion of Ip at the edge of inversion. The negative level-shifter Vn is designedto push the triode region of Mn out of the input range. More specifically, Vn isresponsible for turning Mn on when Mp is entering the triode region as the resultof further increase in the input voltage. For a large Rs (to limit Isum) and a largeaspect ratio for Ms, VD variation is negligible (i.e., VD ≈ VDD−Vth,s). Therefore,Mp enters triode when Vin + Vp−Vth,p = VDD−Vth,s (point N in Figure 2.15).Substituting Vp from Equation 2.8 yields:Vin|N = VDD−Vth,s−Voff,p (2.9)Vn is accordingly designed to turn on Mn at point N. In other words, at the edge ofMp’s triode region, Vin−Vn = Vth,n which gives:Vn = VDD− (Vth,s +Vth,n +Voff,p +Voff,n) (2.10)where, Voff,n is the offset voltage added to cancel the non-linear behavior of Mpduring transition from saturation to triode.2.4.3 Implementation of Voltage Level shifters and SourceDegeneration ResistorsThe two level shifts, Vn and Vp (shown in Figure 2.16) can be implemented throughthe source-follower architecture as shown in Figure 2.17a [57]. The desired level-shifts Vn and Vp could ideally be obtained by connecting the gate of the currentsource transistor (Mcn and Mcp) to Vn and VDD−Vp respectively. Since the loads47VinVnVDD- VpV pVnVinM n M pM c n M f pM f n M c p(a)MnR SS nS nMR sVbVs h(b)Figure 2.17: CMOS implementation of (a) voltage level shifters and (b)source degeneration resistors.driven by the source followers (gate terminals of Mn and Mp) do not draw anycurrent, the current source and follower transistors experience the same currentand if sized identically will produce identical gate-source voltages, i.e., Vgs,fn =Vgs,cn = Vn and Vsg,fp = Vsg,cp = Vp.The large source-degeneration resistors (Rs) are implemented by a smallaspect ratio NMOS devices (MRs) in triode as shown in Figure 2.17b. As shownin the figure, the drain of MRs is connected to its gate through a positivelevel-shifter to guarantee that it stays in triode regardless of its drain voltage (VSn)variations. In addition to the silicon area saved by implementing the largeresistors through the triode NMOS, the proposed architecture provides asecondary control mechanism to further linearize the desired currents In and Ip.More specifically, for a sufficiently large positive level-shift Vsh, MRs is pushedinto deep triode region and therefore its drain-source resistance is given by:Rs ≈1k · (VSn +Vsh−Vth,Rs)(2.11)where k = µnCox(W/L)Rs. In view of Equation 2.11, Rs is a weak function of VSnsuch that it has a larger value at the beginning of the input range and slightly dropswhen Vin and accordingly VSn increases. The non-linear dependance of Rs on thesource voltage benefits a linear current profile. Specifically, in the vicinity of thetransition point N (see Figure 2.15), Rsp keeps dropping while Rsn is at a highervalue which leads to smoother transitions from saturation to triode for Ip and fromcut-off to saturation for In.48CstoreV C Sc l k r e fVinvcompIchgId i s chgVin G mIprec l k c h gc l k p r e c l k r e fc l k d e lc l k r e fc l k r e fIcsSrst(a)clkrefd i s c h a r g e  c y c l ec h a r g e  c y c l e2Tc l kT p r eVCSV t hclk p reVinvclkdeldel 1t 0dela y tdel2Vcs1Vcs2(b)Figure 2.18: Comparator implementation. (a) Schematic diagram and (b)Timing diagram.2.4.4 Implementation of the Inverter-Based ComparatorIn derivation of Equation 2.7, it was assumed that the the comparator compares thecapacitor voltage (Vcs) with Vref = 0. In order to save layout area and power, thecomparator could be implemented with a simple inverter (in a a fashion similar tothe conventional CS VTC) such that the inverter compares the input voltage withits intrinsic threshold voltage Vth. This threshold voltage has to be cancelled priorto input proportional charge cycle. The inverter threshold cancellation scheme49is schematically shown in Figure 2.18a. As shown in the figure, at the start ofthe charge-cycle where the output of the inverter (Vinv) is high, the capacitor ischarged with the constant current Ipre. Once the voltage on the capacitor equalsVth, the inverter toggles to low, deactivating clkpre and activating clkchg. Therefore,Cstore is being charged at the input proportional rate (Gm×Vin) for the rest of thecharge cycle. A similar scenario holds for the discharge cycle where the invertertoggles to high once Vcs = Vth producing clkdel. Such a scheme guarantees thatthe input proportional charging lasts for a constant period regardless of the inputvalue. The timing diagram of the proposed threshold cancellation scheme is shownin Figure 2.18b. Following the same procedure as that of Equation 2.7, Vth iscancelled in the derivation of the desired delay which is given by:delay = k ·Vin(k =Gm · (Tclk/2−Tpre)Idischg)(2.12)where the constant value Tpre, is the time required for the storage capacitor tocharge at a constant rate (Ipre) from zero to the threshold voltage of the inverter.The three AND gates are designed to produce the appropriate signals to turn theswitches on/off at designated times. Note that during the discharge cycle, oncethe desired delay is obtained (i.e., Vinv toggles to high), Vcs could be kept intactsuch that the capacitor starts to charge form a value close to Vth at the beginningof the following charge cycle. However, the precharge/reset scheme (i.e., pre-charging the capacitor at the beginning of the charge cycle and resetting it at theend of the discharge cycle) is essential to avoid unnecessary power consumptionas keeping the input voltage of the inverter (Vcs) at a value close to its thresholdvoltage provokes a large static current drawn by the inverter.2.4.5 Design ConsiderationsThe complete circuit-level schematic of the proposed VTC is shown inFigure 2.19. As shown in the figure, the produced linear current is transferred tothe charge/discharge unit through a self-cascode current mirror [58]. Note thatduring the current copying interval (charge cycle), the drain voltage of the mirrorPMOS transistor Mm1,2 (i.e., Vcs) varies significantly and therefore, the high50VpVinMn MpMcn MfpMfn McpCstoreVC S VinvcompIpre c l k p r ec l k r e fc l k d e lc l k r e fc l k r e fIcsM R sVbVs h M R sV bVs hVinc l k c h gVbVbc l k c h g c l k p r ec l k r e fVbVbIchgc l k d e lIdischgVnMpreMd i s 2Ms 1Md i s 1Ms 2Mm1Mm2C onstant- G m v ol tage- to- cu rrent conv erter Th resh ol d cancel l ation and control l  u nitC h arge/ disch arge u nitIs u mFigure 2.19: Circuit level schematic of the proposed VTC.output impedance offered by the self-cascode architecture proves beneficial inproviding a high-precision copy of the produced linear current to the capacitor.The discharge current is also supplied by the self-cascode NMOS transistor(Mdis1,2) to guarantee a rather constant current despite Vcs variations duringdischarge cycle. The pre-charge transistor Mpre is designed with a large aspectratio to provide a large current in order to minimize the pre-charge time.In regards to the proposed VTC architecture, there are some important pointsand trade-offs to be carefully considered in the design process which are listed asfollows:1. Regarding the charge current transfer scheme, one can directly drive the storagecapacitor by a PMOS input voltage-to-current converter and thus avoid the currentmirror and the associated complications altogether. However, such an alternativeis impractical for two reasons.First of all, the drain voltage (Vcs) variation of input devices will severelyaffect the linearity of the produced summation current. Secondly, switching offthe summation current (Ichg) during the discharge cycle pushes the two inputdevices into deep triode. The input devices require a certain amount of time forthe transition from triode to saturation at the start of the next charging cycle. Theotherwise unnecessary transition time affects the speed performance of the51voltage-to-current converter and limits the maximum sampling frequency.Moreover, the prolonged setup time leads to a nonlinear and inaccurate transientcurrent at the start of each charging cycle. Although a constantly on input branch(in the proposed design) comes at the cost of extra current consumption, thepower overhead is well justified. More specifically, the proposed scheme enablesincorporating a current mirror with a high output impedance at the drain of Mm1,2to mitigate the effect of Vcs variations on Ich accuracy. Furthermore, theaforementioned transition could be much shorter for the mirror current comparedto the scenario where the entire input current is switched.It is worth mentioning that as a viable approach to conserve power, the inputbranch can be turned off through voltage switching (i.e., grounding the gates ofthe input devices during the discharge cycle). However, such a scheme is ruledout as an attractive alternative in the proposed design since voltage switching isgenerally slower than current switching. Moreover, voltage switching producescurrent spikes at clocks transitions which is undesired in the context of VTC.2. As described in Section 2.4.2, a linear input dependent current Isum, requiresperfectly matched input devices Mn and Mp (see Figure 2.16). the accuratematching is essential to provide identical current slops while each input deviceoperates in saturation (Mp from zero to N and Mn from N to VDD in Figure 2.15).Also for ideal level shifters, matched input devices guarantee that the transitionoccurs at the desired input level (point N). To achieve a good matching and inorder to minimize process and temperature variations, the two input devices areinterdigitated and laid out inside a ring of dummy transistors.3. It was mentioned in Section 2.4.3 that the positive and negative level shifts canbe obtained by applying VDD − Vp and Vn to the gates of current sourcetransistors Mcp and Mcn respectively. However, to avoid the complexity imposedby the two bias generation circuitries, the two current source transistors aredesigned to generate the desired level shifts while being driven by a single biasvoltage Vb. The same bias voltage Vb is also used to drive thesource-degeneration resistors, pre-charge and discharge current sources as shownin Figure 2.19.520 0.2 0.4 0.6 0.8 voltage (V)delay (nS)  80MHz60MHz40MHz100MHz120MHz20MHzFigure 2.20: Simulated delay for the entire input range for different clockfrequencies.4. Another important issue regarding the operation of the proposed VTC is itsdependance on the clock frequency. More specifically, as suggested byEquation 2.12, the conversion gain (k sec/V), is directly proportional to the clockperiod Tclk. This has to be taken into account only if the VTC is to be used inapplications with variable clock/sampling frequency. Otherwise, the variableconversion gain could be simply calibrated in digital domain such that theminimum and maximum delays (corresponding to Vin = 0 and Vin = VDDrespectively) are extracted prior to the start of operation in order to normalize theresulted slope. Alternatively, the slope variations would be automaticallycancelled if all the internal clock frequencies are scaled with respect to thesampling clock (Tclk). For instance, if a counter is being used to digitize the delay,the clock frequency of the counter has to be sclaed in accordance with that of thesampling clock (Tclk). The conversion gain could also be calibrated in analogdomain through adjusting the pre-charge time (Tpre) and/or the discharge current(Idischg). As suggested by Equation 2.12, a constant k is obtained provided that(Tclk/2−Tpre)/Idischg remains constant regardless of Tclk variations.The simulated delay-Vin plots for different clock frequencies are shown inFigure 2.20. As shown in the figure, the conversion gain (ns / V) is proportional tothe the clock period. In addition to the slope of the delay plots, Tclk manifests itseffect on the produced delay through a separate mechanism. As shown inFigure 2.20, the delay plots saturate for large input voltages at small clockfrequencies (large Tclk). For large clock periods and accordingly long charge53t0 5 10 15 20 (nS)voltage (V)TpreVinfclk = 20 MHzTchargeFigure 2.21: Simulated transient voltage of storage capacitor during thecharge cycle.cycles, the storage capacitor will charge up to high values. A high Vcs (seeFigure 2.19) pushes the mirror transistor Mm1,2 into triode resulting in Ichgdegradation which is shown as the curved parts of delay plots for fclk = 40 MHzand fclk = 20 MHz. The simulated transient voltage of the storage capacitor, forthe entire input range (at 100mV increment) and for a clock frequency of 20 MHzis shown in Figure 2.21. As shown in the figure, Vcs starts to saturate for inputvoltages larger than 0.3 V. Also for Vin > 0.4V, Vcs is fully charged to VDD atthe end of the charge cycle which corresponds to a constant delay (Vin > 0.4) inFigure 2.20.To address the nonlinearity ensued as the result of Vcs saturation for smallerthan nominal sampling frequencies (fclk), a simple approach is to increase thestorage capacitance. Note that one can alternatively reduce the charge current orthe threshold voltage of the inverter, however, such approaches come at a higherprice in terms of complexity. Schematic diagram of Cstore modification schemealong with the simulated delay are shown in Figure 2.22. As shown, a controllerwill switch sclk/2 on to place an identically sized storage capacitor in parallel withCstore if the sampling frequency is to be half of the nominal frequency. The samescenario hold for sclk/4 if the sampling frequency is reduced down to a quarter ofthe designated frequency.54Ichgs clk / 2 s clk / 4C C 2CFigure 2.22: Storage capacitor modification scheme along with the simulateddelay.5. As shown in Figure 2.20, the delay plots have a non-zero value for Vin= 0 (i.e.,delay|Vin=0 6= 0). This offset is normally not a matter of concern in mostapplications. Moreover, if a zero delay for Vin= 0 is desired, the offset can besimply cancelled in digital domain during calibration by subtracting delay|Vin=0from the obtained result. The offset could also be cancelled in analog domain at ahigher cost in terms of complexity. To cancel the aforementioned offset, an inputcurrent corresponding to Vin= 0 has to be generated through a replica of thepositively level shifted input device (Mp and the associated shifter in Figure 2.19).The replica current has to be subtracted from the summation current Isum at theconstant-Gm unit or from the charge current (Ichg) at the charge/discharge unit (seeFigure 2.19) as shown in Figure 2.23 . Note that subtracting the replica currentIAZ form Isum as shown in Figure 2.23a, biases Ms close to the edge of inversiongiving rise to nonlinearity for small Vin values. Therefore, subtracting IAZ fromthe mirror current (Ichg) as shown in Figure 2.23b is a more attractive alternativeprovided that IAZ variations as the result of Vcs variations do not introducesignificant nonlinearity. In order to produce the correct replica current, MAZ hasto be sized according to the current mirror ratio.6. A useful feature of integrating converters is their intrinsic sampling property.If the input voltage to the converter is slow compared to the sampling clockfrequency (fclk), the storage capacitor can also perform as a sample-and-hold. Inthe context of the proposed VTC, if the input voltage variations during thecharging cycle are negligible, a sample-and-hold front-end could be avoided55MpM sIs u mMn M A ZIA ZMA Z  =  MpVi n Vi n(a)MpM sIs u mMn M A ZIZ OM A Z  Vi n Vi nCstoreIchgMmMpMmMs=Vcs(b)Figure 2.23: Delay offset cancellation by subtracting the replica currentfrom: (a) summation current, (b) charge current.without compromising the performance. Figure 2.24 shows the simulatedspectrum of the output delay for for sinusoidal inputs at different frequencies. Thefrequencies of input sine waves are non-integer divisors of the sampling frequency(fclk=80 MHz) starting from 1.1 MHz with 1 MHz increments. As shown in thefigure, with no sample-and-hold block incorporated, while the fundamentalcomponent remains rather unaffected, the harmonics and distortion levels of theoutput spectrum significantly increase for higher frequencies. Figure 2.25 showsthe spectrum of the output delay for a 15.1 MHz input sinusoidal when the inputis being sampled (during the discharge cycle) and held (during the charge cycle).As shown, incorporating a sample-and-hold block for higher input frequencies(with respect to the sampling frequency of 80 MHz) improves the dynamicperformance of the converter. Specifically as shown in the figure, the secondharmonic for a 15.1 MHz sinusoidal input is improved by 10 dB (34 dB to 24 dB)when the input is appropriately sampled and held.7. As a parting note, it should be mentioned that one can skip the voltage-to-current conversion step by directly sampling the voltage on the storage capacitor(during the charge cycle) to satisfy the requirements of Equation 2.7. Subsequently,the input voltage sampled on the storage capacitor could be discharged througha constant current source until a pre-defined threshold voltage is met. However,in order to support a rail-to-rail input range (0∼VDD), such a scheme requires asophisticated discharge current source to maintain an accurately constant currentover the entire range and/or a negative supply voltage.561 2 3 4 5 10 15 20 25 30 35 40ref204060Frequency (MHz)Power/Frequency (dB/Hz) 2nd harmonic 30.2 MHz 2nd harmonic 20.2 MHz Figure 2.24: Spectrum of the output delay for different input frequencieswithout sample-and-hold.5 10 15 20 25 30 35 40ref204060Frequency (MHz)Power/Frequency (dB/Hz)  without S&Hwith S&H2nd harmonic 24 dB Figure 2.25: Spectrum of the output delay for a 15.1 MHz sinusoidal inputwith and without sample-and-hold.2.4.6 Measurement ResultsA proof-of-concept prototype of the proposed VTC is designed and fabricated ina 0.13 µm CMOS process. The prototype is packaged in a standard ceramic quadflat package (CQFP). The entire VTC only occupies 60 µm×60 µm (3600 µm2)of silicon area as shown in Figure 2.26. Analog and digital blocks are separatelydriven by a supply voltage of 1V (VDDA = VDDDIG = 1V) and a single bias voltageof 0.5V is used to drive the level shifters, degeneration resistors and the discharge576 0 ȝm 6 0 ȝm C s toreFigure 2.26: Micrograph of the fabricated VTC.A g i len t DS O8 13 0 4 AV T CP ri n ted  Ci rcu i t BoardCQ F P  pack ag eIn fi n i i Max 116 9 AH P  4 15 5 AV inC L K Del ayA g i len t E 4 8 4 1Acl k r efcl k r efV bG N DV DD AV DDDFigure 2.27: Schematic diagram of the measurement setup.current source (Vb = 0.5V).The measurement setup used for measuring the performance of the proposedVTC is schematically shown in Figure 2.27. An HP-4155A semiconductorparameter analyzer is used to provide the input ramp (Vin), bias voltage Vb andalso the supply voltages (to enable current consumption measurement). The clocksignals clkref and clkref are supplied by Agilent-E4841A data Gen./Analyzer. The580 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 voltage (V)delay (nS)  simulationmeasurementfin =  80 MHzFigure 2.28: Measured and simulated delays for the entire input range.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1−1.0 −0.5 00.51.0input voltage (V)linearity error (%)  measurementsimulationfin = 80 MHzFigure 2.29: Measured and simulated linearity error for the entire inputrange.same module is used to provide a copy of clkref (shown as CLK in Figure 2.27)for delay measurement. An Agilent 12-GHz InfiiMax-1169A active probe is usedto capture the output delay signal and an Agilent 13-GHz Infiniium-DSO81304Aoscilloscope is used for delay measurement.The simulated and measured delay versus input voltage (at 50 mV increments)is shown in Figure 2.28 for an slow ramp as the input voltage and an 80 MHzreference clock. The systematic delay attributed to the length difference betweenthe sub-miniature version A (SMA) cables (those connecting clkref, clkref and CLKin Figure 2.27) and the active probe is measured for Vin = 0 and de-embeddedwith respect to the simulated delay profile. Note that it is the linearity of themeasured delay profile (i.e., constant slope of the curve) which is of significance590.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 11618202224input voltage (V)Current (µ A)  simualtionmeasurementVDD = 1VVb  = 0.5Vfin  = 80 MHzFigure 2.30: Measured and simulated analog current consumption of theVTC for the entire input range.as a performance metric. As mentioned in Section 2.4.5, the offset (i.e.,delay|Vin=0) can cancelled in digital domain during calibration. As shown in thefigure, the measured delay exhibits a good linearity performance and fits thesimulated delay profile for a wide range of input voltages. The measured delayline slightly deviates from the simulated one as the input voltage grows. Such abehaviour observed in measurements can be attributed to the inaccuracy of thecurrent mirror (Mm1,2 in Figure 2.19) in copying the summation current (Isum)when the voltage of the storage capacitor (VCS) grows too high. With reference toFigure 2.19, a large VCS prevents accurate current mirroring by decreasing thevoltage headroom of the mirror transistors (Mm1,2) and disrupting the balancebetween the source Isum and the mirror (Ichg) branches.Figure 2.29 shows the simulated and the measured linearity error for the entireinput range and a similar setup as that of Figure 2.28. As shown in the figure,the simulated result exhibits a linearity error smaller than ± 0.5 % for the entireinput range which corresponds to ∼ 7.64 ENOB. The measured error is within± 0.6 % for Vin < 0.95 V corresponding to ∼ 7.38 ENOB. The linearity errorpercentage grows to − 1.4 % for the full range (Vin = 1 V) which degrades theENOB to∼ 6.16. As discussed above, the linearity degradation at higher end of theinput range can be avoided by use of a more accurate current mirror. An exampleof such a modification to improve the current mirror performance is provided inSection 6.2. Note that the ENOB values reported are those of the VTC only and60in a complete time-mode ADC, other parameters also affect the overall linearityperformance of the system.For a 1 V supply voltage at 80 Mhz clock frequency, Figure 2.30 shows themeasured and simulated average current (power) drawn by the analog portion ofthe VTC (constant Gm voltage-to-current converter, charge and discharge unit andthe inverter-based comparator in Figure 2.19). Note that for large input values(i.e., Vin > 0.6 V), the rate of current consumption drops with Vin. As discussedabove, such a behavior is expected since the small voltage headroom of Mm1,2 (seeFigure 2.19) results a smaller mirrored current for a longer portion of the chargeinterval. The average current consumption of the digital portion of the VTC (digitalgates of the control unit) for a supply of 1 V is measured to ∼ 1.8 µA.Table 2.2 provides a performance summary of the proposed VTC and comparesthe results with similar works.Table 2.2: Comparison of the proposed VTC with similar works.Reference [50]? [52]?? [59]?? This work ??Technology 0.13 µm 90 nm 90 nm 0.13 µmConversion gain 2.5 ns/V 250 ps/V ∼ 400 ps/V ∼ 1.25 nS/VLinear range 200 mV 100 mV 150 mV 1 V aLinearity error 2 % N/A < 0.05LSB b < 1.4%Power consumption N/A 2.7 mW c 5.7 mW c 16.8 µW ∼ 22.8 µW d? Simulation results. ?? Maesurement results. a Entire input range. b LSB = 6.25 ps. c At 5 GHzsampling frequency. d At 80 MHz sampling frequency for 0 ∼ 1 V input. The digital power consumption is1.8 µW.2.5 ConclusionIn this chapter, first, an ultra-low-power SAR ADC is presented. The proposedDAC architecture allows operation of the SAR ADC with only four minimumsized capacitors which in turn, facilitates an small area and low powerconsumption. In order to further save power and layout area, the two buffersincorporated in the DAC architecture are dually used as the pre-amplifier stage forthe comparators. The proposed SAR ADC is designed in a 0.13 µm CMOStechnology and its performance is verified by post-layout simulation results.61Furthermore, an important building block of a time-mode ADC, namely, ahighly linear wide input range VTC is discussed. Circuit-level design techniquesare used to provide a linear performance for the output delay for a wide range ofinput voltages. The proposed VTC is fabricated in 0.13 µm CMOS technologyand its performance is validated through measurement results.Although SAR ADCs are widely used in RFID tags to perform theanalog-to-digital conversion, they are still dependent on capacitive DAC andanalog comparators which are typically area consuming and power hungry blocks.Time-mode ADCs on the other hand, are more compatible with all-digital CMOSimplementation which is specifically beneficial in the context of passive RFIDtags.62Chapter 3Efficient Power ConverterCircuits for RFID ApplicationsWireless energy harvesting (also known as RF energy harvesting) is an mergingtechnology that enables long and maintenance-free operation of low-powerelectronic devices.1 The applications for such wirelessly-powered devices span awide range including wireless chargers, biomedical implants, wireless sensornodes, RFID tags (semi-passive and passive), etc. Transmission of RF energy hasa long history dating back to the experiments of Heinrich Hertz in 1880 [60]. Thistechnology has come back into interest recently in response to the requirements ofRFID tags and wireless sensor nodes. RF energy delivery provides numerousadvantages over the conventional wired methods the most important of whichcould be summarized as [61]:• Eliminating the wiring and battery replacement costs and facilitating a cost-efficient implementation of the device.• Eliminating service failures due to depleted battery and facilitating amaintenance-free and reliable operation.RF-to-DC converter (rectifier) is a key building block of an RF energyharvesting system. As discussed in Chapter 1, the main task of the rectifier is to1http://ca.mouser.com/applications/energy harvesting wireless/63D CD Crectif ierR eactiveantenna impedance matching rectif ication b oost energystorage loadR F  p ower harvesting u nitfrequencyFigure 3.1: Schematic diagram of a generic RF power harvesting unit.receive the RF energy and to convert it to a stable DC power to supply thewirelessly-powered device. A crucial characteristic of the rectifier is itsconversion efficiency which directly determines the available power for the devicefrom the limited transmitted energy. More specifically, the performance of therectifier interactively decides the harvesting range, frequency range, sensitivity ofthe device and implementation scalability [62]. Extensive studies have beencarried out to improve the efficiency of the rectifiers which will be discussed inthe next section.3.1 Efficiency Analysis of UHF CMOS RectifiersThree major parameters directly influence the PCE of a rectifier, namely loadrequirements, frequency of operation and circuit topology (including antenna,matching network and the rectifier circuitry). Figure 3.1 schematically shows theinternal operation of a generic power harvesting unit highlighting the threeparameters that affect the PCE of the rectifier. With the first two parametersdictated by the application, the main research to enhance power conversionefficiency is targeted at proposing novel architectures and design techniques at acircuit level.In a circuit level analysis, PCE is mainly degraded as a result of two majormechanisms, namely forward voltage drop and reverse leakage current inswitching devices (diodes or transistors). Note that the matching networkefficiency will be covered later in this chapter and the adverse effect of parasiticsis of a second order importance and could be minimized through optimal sizing. Itis also worth mentioning that Schottky diodes provide a low potential barrier64which is very attractive to implement the switching device for UHF rectifiers [63].However, any desirable efficiency enhancement technique should avoidincorporation of Schottky diodes, floating gate transistors, low-thresholdtransistors, etc., as they are not supported in a low cost standard CMOStechnology.Conventional Dickson-based rectifier is a well-known architecture andextensive studies on efficiency enhancement techniques associated with thisarchitecture exists in the literature. Raben et al. [64] introduce an activediode-connected metal-oxide-semiconductor (MOS) transistor as the switchingdevice. An adaptive threshold cancellation scheme is proposed by Yo et al. [65].Umeda et al. [66] use floating voltage sources to cancel the threshold voltage ofswitches. Although static cancellation of the threshold voltage improves theforward voltage drop specification of the switches, such a scheme produces ahigher leakage current and degrades efficiency performance. Shokrani et al. [67]use the bulk connection of MOS switches to reduce their threshold voltage andleakage current.Lee and Ghovanloo [68] and Guo and Lee [69] propose use of high-speedcomparators to detect and control the reverse leakage currents in switches.Considering the power consumption and the complexity overhead, employinghigh speed comparator limits the usefulness of such techniques to low frequencyapplications. Comprehensive studies on optimization procedure and design issuesassociated with conventional (Dickson-based) rectifiers are provided in [70–76].Dickson-based rectifiers generally fail to perform desirably in terms ofefficiency in view of their characteristic inefficient architecture (specifically whenSchottky diodes and other high-cost technologies are not available). As a moreefficient alternative, differential-drive (4T-cell) architecture has been introduced tosimultaneously tackle the impacts of forward voltage drop and reverse leakagecurrent [77]. Differential-drive rectifiers provide a superior efficiency (comparedto Dickson-based rectifiers) at no significant cost in terms of complexity.Differential rectifier receives the input RF signals in a differential format and thecross-coupled bridge configuration allows low ON-resistance and small leakagecurrent simultaneously.The differential-drive rectifier introduced by Kotani et al. [78] achieves a high65PCE (%)VIN/ P INE ffi ci ency curv eopti mal i n pu tP CE MA Xd i s tan ce /  mi s alli g n men tFigure 3.2: Schematic diagram of the PCE curve of a generic rectifier.PCE of 62% for −6 dBm input power at 953 MHz input frequency. Mandal andSarpeshkar [79] investigate the potentials of using floating gate switchingtransistors in a double-poly technology to enhance the efficiency ofdifferential-drive rectifiers through reducing the threshold voltage of switches.Bakhtiar et al. [80] propose a biasing scheme to drive the gate of switches and setthe effective threshold voltage of transistors to a smaller value, therefore reducingthe turn-on voltage of the rectifier (i.e., achieving the maximum efficiency forsmaller input voltage). Wong and Chen [81] provide an analytical designapproach to enhance the efficiency of multi-stage differential-drive rectifiers.Huang et al. [82] use a high voltage-gain charge pump after the differentialrectifier to enhance the conversion efficiency. Mazzilli et al. [83] provides adesign methodology for an efficiency matching and compared various differentialrectifier topologies.Generally, a rectifier is designed and optimized to meet the requirements setby the application. Specifically, optimization is performed mainly on the basis ofthe load, frequency of operation and communication distance. Optimizationparameters include topology, transistor and capacitor sizing, number of stages,etc. For a fixed set of load requirement and frequency of operation, the PCE of arectifier peaks at an optimal input voltage/power level and drops drastically if theinput deviates from the optimal point as schematically shown Figure 3.2. Thisfollows that if the input RF level received by the tag antenna drifts away from theoptimal input voltage/power, the abrupt drop in PCE disables the rectifier tosufficiently supply the succeeding tags circuitry. Note that deviation from theoptimal input level occurs as the result of variations in the distance between the66MUDCn-1DCnMLMn 1 Mp1Mn 2 Mp2IN+IMN2IMP 1(a)0 05 1 1.5 2 2.5 30pi radVML VMU VMLIMN2IMP1T2T1DCnDCn−1(b)Figure 3.3: Conventional differential rectifier. (a) Architecture and (b)voltage-current waveforms at UHF.reader and the tag (in electromagnetically coupled systems) or misalignmentsbetween the primary and secondary coils (in inductively coupled systems). Asmentioned earlier, forward voltage drop and reverse leakage current are mainlyresponsible for PCE degradation. Therefore any attempt towards improving PCEhas to diminish the adverse effects of the two mechanisms. To this end, aconventional differential rectifier along with the current-voltage waveforms forthe two reciprocal PMOS and NMOS transistors (MP1 and MN2) are depicted inFigure 3.3 for a 950 MHz input frequency.Note that, the waveforms are shown for the second stage of three-stage67Figure 3.4: PCE curve and forward-to-reverse current ratios of MP2 versusinput voltage.rectifier and the Y-axis is graded arbitrarily. As shown in the figure, due to the RCnature of the circuit, the currents lead the voltages. More specifically, the forwardcurrent of IMP1 reverses its direction prior to VMU and DCn intersection at T2.Note that Mp1 switches its source and drain at T2. Prior to T2, MU and DCn serveas the source and drain respectively, while DCn and MU switch their tasks after T2and function as source and drain respectively. At lower frequencies, currentdirection reversal occurs subsequent to the intersection point where IMP1 starts intriode mode followed by saturation until the gate-source voltage (VML-DCn) fallsbelow the threshold voltage of IMP1 and sub-threshold current keeps flowing untilthe next current reversal (reverse-to-forward at 2.5 pirad as shown in Figure 3.3b).However, at UHF, currents and voltages are not perfectly in-phase, whichsubstantially complicates the analysis and optimization based on current-voltagewaveforms as proposed in [70] and [81]. The same scenario holds for MN2.As a more practical and straightforward approach, PCE could be studied as afunction of forward-to-reverse currents ratio for the entire input range. The PCEof a three-stage rectifier at 950MHz input frequency along with theforward-to-reverse current ratios for the two reciprocal switching transistors (MP1and MN2) are shown Figure 3.4 versus the input voltage. As shown in the figure,68the maximum efficiency point (corresponding to optimal input voltage) is almostperfectly aligned with the maximum forward-to-reverse current ratios for theswitching transistors which suggests that maximum PCE is obtained provided thatthe switches are operating at the maximum forward-to-reverse current ratio mode.Also as shown in Figure 3.4 the input range is divided into two regions, labeled asregion-I and region-II. In region-I, the gate of switching transistors areunder-driven, i.e., with respect to their threshold voltages, the gate-source voltageof the switches (e.g. VML-VMU in Figure 3.3a) are insufficient to fully turn thetransistors on in order to provide a large forward current to charge the associatednode. On the other hand, in region-II, the gate of switching transistors areover-driven, i.e., the gate-source voltage of switches are excessively large whichin turn increases the reverse current, giving rise to a smaller forward-to-reversecurrent ratio and consequently a smaller PCE. Note that with reference toFigure 3.3b, Iforward is the average of IMp1,N2 for the intervals of time whenIMp1,N2> 0 and Ireverse is the average of IMp1,N2 for the intervals of time whenIMp1,N2< 0 . It can be concluded from Figure 3.4 and the discussion made abovethat in order to address the PCE drop on the two sides of the maximum PCE point(optimal input voltage), the gate-drive voltage of switches need to be boosted inregion-I (where switches are under-driven) while they need to be attenuated inregion-II (where switches are over-driven).This could be further clarified in view of Figure 3.5 where the PCE curve isshown on the top, along with the average source-gate voltage of transistor MP1during the forward conduction interval, and the gate-source voltage of MP1during the reverse conduction. Forward conduction interval (T1∼T2 inFigure 3.3b) is defined as the time slot in which the intermediate nodeexperiences a higher voltage than the output node (i.e., VMU > DCn inFigure 3.3a). In other words, the intermediate node, MU, serves as the source andthe output node, DCn, serves as the drain for MP1 such that charge is transferredfrom the input to the output. Accordingly, the reverse interval is defined as thetime window when MU serves as the drain and DCn serves as the source(VMU < DCn) and charge is leaked from the output to the input node. Ashighlighted in the figure, at each stage of the rectifier, there is a certain gate-drivevoltage occurring at the optimal input voltage that maximizes the efficiency.69Figure 3.5: PCE curve and average gate-drive voltage during forward andreverse conduction.Similar graphs could be obtained for all other switching transistors at differentstages.It can be concluded from the discussion above that in order to achieve highefficiencies for smaller input levels, the gate of transistors need to be biased suchthat they receive optimal gate-drive voltages at the desired input level. Such abiasing scheme is schematically shown in Figure 3.6a where floating voltagesources are placed between the intermediate nodes (ML,U) and the gate oftransistors (Gp1,2 , Gn1,2). The floating voltage sources shift the DC level of theintermediate sinusoidal voltage to provide a boosted gate-drive voltage for theswitches. Note that PMOS switches require a negative shift while NMOSswitches receive a positive shift. The effect of the proposed biasing scheme as ashift in the PCE curve of the rectifier towards smaller input levels is schematicallyshown in Figure 3.6b.Generally the PCE curve of the differential rectifier could be shifted to the left(smaller input levels) and to the right (larger input levels) upon proper biasing ofthe gate of switches through floating voltage sources. However, the challengingdesign issue to be addressed is implementation of the floating voltage sources in anarea and power efficient manner such that a superior efficiency is obtained at the70MUDCn-1DCnMLMn 1 Mp1Mn 2 Mp2V P 1VP 2VN1VN2MUMLnegative shiftnegative shiftpositive shiftpositive shiftG n 1G n 2G p1G p2(a)PCE (%)VIN / P INBoos ted  P CE  P CE MA Xs maller i n pu tlev els(b)Figure 3.6: Proposed biasing scheme. (a) Gate-boosted differential rectifierand (b) schematic diagram of the shifted PCE curve.desired input level with minimal silicon area and power overhead.As discussed in this section, for a fixed set of requirements dictated by theapplication, any effort towards increasing the communication distance entailsincreasing the PCE of the rectifier for small input levels. It was shown that inorder to enhance the efficiency of the rectifier, the adverse effect of forwardvoltage drop and reverse leakage current could be mitigated through properbiasing of the gates of switches. Such a biasing scheme has to provide a boostedgate-drive voltage when the switches are under-driven for a wide range of inputlevels. In the following sections, efficiency enhancement techniques are presentedfor UHF differential rectifiers. The efficiency enhancement techniques are mainlybased on dynamically biasing the gate of switches through floating voltage71sources connected between the intermediate RF voltage and the gate of switches.The proposed biasing schemes are designed to comply with passive RFIDapplications and the demand for an external supply (other than the output of therectifier) is minimized. The proposed schemes are also studied in terms of poweroverhead and silicon area requirement.3.2 Proposed Switched Rectifier Scheme2As mentioned in Section 3.1, the input power received by the tags antenna dropsrapidly as a function of the distance from the reader (transmitter). Accordingly,insufficient power levels generate small peak-to-peak RF voltages at the input ofthe rectifier as as the peak voltage available at the chip input, under perfect powermatching conditions, is given by [84]:VINp ≈√PAVRANT1ωC (3.1)where PAV is the available power at the antenna, RANT is the antenna equivalentresistance, Ω is the antenna resonance frequency and C is the rectifier equivalentcapacitance. To enhance the input voltage to the chip, RANT has to be minimized,however the minimum antenna impedance is dictated by geometrical constraintsand maximum efficiency. Therefore as suggested by Equation 3.1, small input RFpowers generate insufficient input voltage levels at the input of the rectifier. In orderto enhance the resulted deteriorated PCE, gates of switches need to be boosted toshift the PCE curve towards small input levels.As mentioned in Section 3.1, to boost the gate of switches in region-I, thefloating voltage sources need to positively shift the RF gate voltage of NMOStransistors and negatively shift those of PMOS transistors. As a cost efficientcandidate to implement the floating voltage sources at each stage of the rectifier,the already generated intermediate voltage of the preceding and succeeding stagescould be used in a timely manner.Note that along with the DC output, the DC level of the intermediate voltageat each stage also builds up along the rectifier chain. Therefore, for each stage, the2The material presented in this section is based on [7]72MUnMLnM n 1 Mp1M n 2 Mp2MLn +1MUn +1MLn -1MUn -1CLK1CLK1CLK2CLK2DC nG LnG UnDC n -1(a)DC nMUnMUN+1MUn -1CLK1CLK2G UnMLnMLn +1 MLn -1G LnMUn -1MUnMUn +1t1 t2 t3 t4 W¶1 W¶2(b)Figure 3.7: Proposed Switched rectifier. (a) Schematic diagram and (b)Timing diagram [7].intermediate RF voltage of the preceding stage could be exploited as thenegatively shifted version, while that of the succeeding stage could be used as thepositively shifted version gate-drive voltage. To enhance the performance, theseintermediate voltages could be switched in a timely manner to drive the gates of73switches at each stage. The proposed switched rectifier is schematically shown inFigure. 3.7a. During the time interval t1∼t2 (MUN>DCn) when Mp1 isconducting in forward direction and Mn1 is isolating, CLK1 connects the gates ofthe top branch switches, GUn to the appropriate intermediate voltage of thepreceding stage, MLn-1. Consequently, MP1 (which is supposed to conduct)experiences a larger source-gate drive voltage and MN1 (which is supposed toisolate) undergoes a larger reverse bias. During the rest of the sinusoidal cycle,t1∼t’1 (MUN<DCn), when Mp1 is isolating and Mn1 is conducting, CLK1connects GUn to MLn+1 therefore reinforcing the reverse bias of Mp1 (which issupposed to isolate) and gate-source drive voltage of Mn1 (which is supposed toconduct). Same scenario holds for Mp2 and Mn2 in alternative cycles. The timingdiagram of the proposed switching scheme is shown in Figure 3.7b. Assuming anequal voltage increment at each stage, the proposed switching scheme brings agate-drive boost as large as the DC level increment at each stage i.e.:∆M dcUL = ∆DCn = cteVboost,SWi = ∆MdcUL = ∆DCi(3.2)where ∆M dcUL and ∆DCn are dc level increments for the intermediate voltage andDC output voltage at each stage respectively and Vboost,SWi = is the gate-drivevoltage enhancement achieved by the proposed switching scheme at the ith stageof the rectifier. Obviously, the first stage employs its own intermediate voltage(MUL,1) for MUL,n-1 as there is no preceding stage to the first stage. Accordingly,the last stage uses its own intermediate voltage for MUL,n+1. In the proposedswitching scheme, the clock signals (CLK1,2) at each stage need to be accuratelytimed to guarantee the maximum charge transfer in forward direction andminimum reverse leakage current. As shown in Figure 3.7b, CLK1 is ideally onfor t1∼t2 interval where MUN>DCn (shaded area). Although the proposed timingscheme improves forward charge transfer and reverse leakage isolation, it is notperfect since the reverse leakage starts prior to t2 as shown in Figure 3.3b.A regenerative amplifier performs the comparison between the DC output ofeach stage and the intermediate voltage as shown in Figure 3.8.74VDDMUnDC nCLK1CLK1V bt1 t¶1t2 t¶2t1 t¶1t2 t¶2Figure 3.8: Clock generation circuitry [7].3.2.1 Switched-Capacitor Gate-Boosting SchemeFor small input levels, the rectifier fails to produce substantial voltage incrementsat each stage which compromises the effectiveness of the switched architecture.Therefore, to enhance the input voltage range of the switched rectifier, additionalboosting is required to assist the voltage increment given by Equation 3.2 at eachstage.Accordingly, a floating voltage source is placed between the switchedintermediate voltage and the gate of transistors as shown in Figure 3.9a. In orderto control the magnified reverse leakage current as the result of the extra voltageshift, it is desirable for the floating voltage source to swap its terminalssimultaneous with appropriate clock signals at each stage as shown inFigure 3.9b. During the interval t1 ∼ t2 (CLK1) when MP1 is conducting and MN1is isolating, the floating voltage source adds −VGB1 to the switched voltageVM,Ln-1 therefore increasing the source-gate drive voltage of MP1 and reverse biasvoltage of MN1 by |VGB1|. During the rest of the sinusoidal cycle, t2 ∼ t’1(CLK1) when MP1 is isolating and MN1 is conducting, the floating voltage sourcereverses its terminals to add +VGB1 to the switched voltage VM,Ln+1 thereforeincreasing the reverse bias voltage of MP1 and gate-source drive voltage of MN1by |VGB1|. The same scenario holds for the bottom branch at appropriate clockcycles. Therefore, assuming equal voltage increments at each stage, the proposedgate-boosting scheme brings a gate-drive boost as large as:∆M dcUL = ∆DCn = cteVboost,GBi = ∆MdcUL +VGBi(3.3)75MUnMLnM n 1 Mp1M n 2 Mp2MLn +1MUn +1MLn -1MUn -1CLK1CLK1CLK2CLK2DC nG LnG UnDC n -1VG B1CLK1 CLK1VG B2CLK2 CLK2(a)DC nMUnMUN+1MUn -1CLK1G UnMLnMLn +1MLn -1t1 t2 t3 t4 W¶1 W¶2+VG B1-VG B1+V G B1-VG B1 -V G B1(b)Figure 3.9: Proposed Gate-boosted rectifier. (a) Schematic diagram and (b)Timing diagram [7].where, ∆M dcUL and ∆DCn are dc level increments for the intermediate voltage andDC output voltage at each stage respectively, Vboost,GBi is the gate-drive voltageenhancement achieved by the proposed gate-boosting scheme for the ith stage andVGBi is the voltage of the floating source at the ith stage.76V G BC b oos tCrefres hCLKrefCLK1 CLK1CLK1M F 1 M F 2MR 2MR 1V G BCLK1CLK1YXM1M4 M 3M2CLKrefCLKrefCLKrefFigure 3.10: Switched-capacitor implementation of the floating voltagesource [7].To implement the floating voltage source capable of interchanging itsterminals at appropriate clock cycles, the switched-capacitor (SC) architecture ofFigure 3.10 is proposed. Cboost is charged to VGB through M1-M4 after a fewclock cycles and performs as a voltage source subsequently. During CLK1, MF1and MF1 connects Cboost between nodes X and Y such that VXY = +VGB. DuringCLK1 , MF1,2 turn off and MR1,2 place Cboost between nodes Y and X providing anegative voltage between X and Y such that VXY = −VGB. Crefresh refreshes thevoltage on Cboost to compensate the charge loss due to leakage current of theswitches, the capacitors and the gate parasitics of the main switching transistors towhich the SC floating voltage is connected. Note that to drive M1-4 switches forrefreshing purpose (CLKref), a low-frequency clock is more attractive as it leadsto smaller power consumption, however if no appropriate low-frequency clocksignal exists on the chip, pre-generated CLK1 can be employed in order toconserve complexity and layout area.The final configuration of the proposed gate-boosted rectifier is schematicallydepicted in Figure 3.11 for a three-stage rectifier. Note that Figure 3.11 representsthe proposed switched rectifier if VGB generator network and the floating voltagesources are removed.77MU1ML1G L1G U1GNDVG B1VG B2MU2ML2G L2G U2VG B1VG B2MU3ML3G L3G U3VG B1VG B2B oost G en.  1DC1DC2DCoutV GB1V GB1 B oost G en.  2 V GB1V GB1 B oost G en.  3 V GB1V GB1C L K  G en.  1MU1ML1 DC1 C L K  G en.  2MU2ML2 DC2 C L K  G en.  3MU3ML3 DC 3Figure 3.11: Schematic diagram of the proposed gate-boosted rectifier [7].3.2.2 Design Considerations1. Power considerations: As mentioned in Section 3.1, the biasing schemesincorporated to enhance the efficiency of the rectifier require to be efficient interms of power overhead they impose on the rectifier and RFID tag. Morespecifically, the floating voltage sources have to be implemented in a powerefficient manner to minimize their loading effect on the rectifier.The proposed switched rectifier requires two comparators at each stage (total ofsix comparators for a three-stage rectifier) for clock generation. The twocomparators at each stage compare the DC output of the stage with the RFintermediate voltage of the top and bottom branches to produce the clock signals.The relaxed requirements on the accuracy of the comparators facilitate alow-complexity implementation. However, as the comparators are operating atUHF frequencies (950 MHz), they need to be designed carefully to avoid asignificant power overhead on the rectifier. In the clock generator of Figure 3.8,the supply voltage could be obtained from the external battery in semi-passivetags. Note that the output of the main rectifier could also be used to supply thecomparators in passive tags. However if the input level is too small, the rectifier78may fail to deliver sufficient power to the comparators. To start up the switchedrectifier when input level is insufficient, an auxiliary rectifier can be employed totemporarily supply the comparators. The auxiliary rectifier can then be switchedoff when the output of switched rectifier satisfies the desired value.The gate-boosted rectifier requires two SC voltage sources (in addition to the twoclock generators) at each stage. In the floating voltage source of Figure 3.10, VGBcould be supplied from a battery in semi-passive tags. VGB could also be simplyextracted from the DC output voltage of an intermediate stage. It should be notedthat very small gate-boosting voltages (with respect to voltages being generated ateach stage) mitigate the advantages of gate-boosting scheme and very high voltageslead to long, inefficient transitions at the edge of the clock. In passive tags whereVGB is supplied by the rectifier, the proposed voltage source does not severelyload the intermediate output node to which it is connected in virtue of its smallpower consumption. The power consumed by the voltage source of Figure 3.10mainly stems from the leakage current of the two MIM capacitors (Crefresh - Cboost),switch leakage currents and gate parasitics of the rectifier switching transistors andconsequently is in the order of few hundred nano-Watts.2. Area considerations: In addition to small power consumption, the proposedbiasing scheme needs to be implemented in an area efficient manner as demandedby the tight silicon area budget of most RFID applications. The comparatorincorporated in the switched rectifier consists of an amplifier and two digitalbuffers and could be implemented in an area efficient manner. The same is not thecase for the SC voltage sources as it contains two capacitors. A trade-off exists forthe value of the capacitors as dictated by the sizing of the rectifier transistors andfrequency of the switching. More specifically, Cboost in Figure 3.10 drives the gatecapacitance of two switching transistors and therefore has to be significantlylarger than the gate capacitances in order not to get fully discharged at each clockcycle. On the other hand, a very large capacitor prolongs the settling time andslows down the switching speed which may cause uncoordinated operation of theswitching and gate-boosting.7950 100 150 200 250 300 350 40000. load (kΩ) Output voltage (V) power (micro Watt)VoutILoadPin12243642Load Current (micro Amp)Figure 3.12: Output voltage and current of a rectifier stage versus load values[4].3.3 Proposed Auxiliary-Cell Boosting Scheme3As shown in Figure 3.5, to achieve a high PCE for small input voltages, theboosting scheme has to positively shift the gate voltage of the NMOS switchesand negatively shift the gate voltage of the PMOS switches to decrease theirrespective effective threshold voltage and accordingly increase their forwardcurrent. Switching scheme and SC voltage source can be used to implement thefloating voltage sources as described in Section 3.2. However, the complexity,layout area, and power consumption overhead imposed by the required multipleSC voltage sources and the clock generator makes such schemes less attractive inpassive RFID applications where area and power efficiency are of paramountimportance.As a more efficient approach, the gate of switching transistors could be drivenby the intermediate RF voltages generated at floating (load-less) auxiliary rectifiercells. Note that rectifiers are designed to produce a specific DC current (in acertain voltage range) whose value is dictated by the load specifications. Thedesignated current drive capacity of a rectifier is achieved through proper sizing ofthe switching transistors and capacitors and optimizing the number of stages. Thefixed current drive capacity follows that if the output load (resistance) increases,3The material presented in this section is based on [4].80MUDCoutGNDMLM n 1Mp1M n 2Mp2IN+IN-IN+MUDCou tG NDCu rren t d i recti onFigure 3.13: Schematic diagram of a reverse-rectifier cell and the associatedvoltage levels [4].the output current does not drop at the same rate and therefore, the output voltagegrows with the load. This is shown in Figure 3.12 for a single stage rectifier (foran arbitrarily chosen input voltage of 400 mV). As shown in the figure, the outputvoltage increases as a function of the output load value until it saturates at aspecific value. The saturation occurs as the rectifier fails to sufficient current atvery large load values and the voltage stops growing with the load value. Notethat as the load grows, the rectifier draws smaller currents from the input which inturn reduces the input power of the rectifier cell. This feature will prove beneficialin the proposed scheme as will be explained later.Based on the above discussion, a floating rectifier cell (i.e., a stage with anopen load) will produce a larger output voltage compared to a typical stage whichdrives the succeeding stage or the output node. Note that the DC level of theintermediate RF voltage at each stage increases in accordance with the outputvoltage. This characteristic of the rectifier cell could be exploited to obtainpositively shifted versions of the intermediate RF voltage to boost the gate ofNMOS switches in the main rectifier. However, as mentioned earlier, to boost thegate of PMOS switches, a negatively shifted version of the intermediate voltage isrequired (see Figure 3.5) which is not readily generated by the conventionaldifferential rectifier. A negative output voltage could be generated by reversingthe task of NMOS and PMOS switches, i.e., getting NMOS switches to conduct inthe positive cycle of the sinusoidal input and PMOS switches to conduct in the81MU1ou t1GNDML1IN+IN-MU2ou t2ML2IN+IN-MU3ou t3ML3IN+IN-ML1MU1ML2MU2ML3MU3G BN1 G BP 1 G BN2 G BP 2 G BN3 G BP 3ML1G BP 1G BN1 ML2G BP 2G BN2 ML3G BP 3G BN3G NDC S1C S2C S3Figure 3.14: Diagram of the intermediate and boosted gate-drive voltagesalong the rectifier chain [4].negative cycles of the input signal such that the current drawn from the outputnode towards the ground discharges the output node and generates a negative DCvoltage. Figure 3.13 shows the schematic diagram along with the generatedvoltage levels and current directions for the top branch of such a rectifier stagewhich will be referred to as a reverse-rectifier cell.The floating rectifier and reverse-rectifier cells could be used to provide therequired shifted drive voltages for each stage of the main rectifier. As shown inFigure 3.14, the DC level of the intermediate voltages MLi,Ui (and accordingly, thegate voltages) increase along the rectifier chain, i.e., the voltage levels are higherfor each stage relative to the previous stage. Therefore, the gate voltages of theswitching transistors at each stage need to be boosted separately. In the proposedarchitecture, two floating rectifier cells are utilized to drive the gate of the switchesat each stage of the main rectifier, i.e., one floating rectifier cell to drive NMOSswitches (GBNi) and one floating reverse-rectifier cell to drive the PMOS switches(GBPi). GBPi and GBNi are the intermediate node voltages of the floating rectifiercells which are appropriately shifted relative to the intermediate voltages of themain rectifier. With reference to Figure 3.14 the boost values are defined as:82VBoostPi = VMi(DC)−VGBPi(DC)VBoostNi = VGBNi(DC)−VMi(DC)(3.4)Care has to be taken to avoid over-boosting the gate of switches in the mainrectifier as over-compensation of the threshold voltage results in an increasedreverse leakage current and subsequently degraded PCE. Note that the DC level ofthe intermediate voltages in a differential rectifier cell directly follow the input DClevel. Therefore, the DC level of the intermediate voltages in the floating rectifiercell (VGBPi(DC) and VGBNi(DC)) could also be adjusted through setting the floatingcell‘s DC input voltage as the reference voltage. In order to guarantee a sufficientboosting level and at the same time avoiding over-boosting the gate of theswitches in the main rectifier, the reference (input) voltage of the floating rectifiercells (and consequently the intermediate node voltages VGBPi(DC) and VGBNi(DC))have to closely track and follow the intermediate voltages of the main rectifier(VMUi(DC) and VMLi(DC)). In other words, in Figure 3.14, VGBPi and VGBNi haveto trail VMLi such that a fixed distance between them (VboostPi and VboostPi) isalways maintained. The tracking could be simply achieved if the reference (input)voltage of the floating rectifier cells is extracted from the voltage levels of themain rectifier cell. For this purpose, in the proposed architecture, the DC input ofeach stage of the main rectifier (GND, out1 and out2 in Figure 3.14 ) serves as thereference for the associated floating rectifier cell which drives the NMOS switches(GBNi generator cells). Likewise, the DC output of each stage (out1, out2 andout3) of the main rectifier provides the reference voltage to the associated floatingreverse-rectifier cell which drives the PMOS switches (GBPi generator cells).Figure 3.15 shows the schematic diagram of the proposed auxiliary-cellboosting technique for the second stage of the main rectifier. As seen, the DCinput to the second stage,out1 , serves as the reference voltage for the floatingrectifier cell (labeled as REFN2) and the DC output of the second stage, out2,serves as the reference voltage for the reverse rectifier cell (labeled as REFP2).The two floating rectifier and reverse rectifier cells produce the boosted gate-drivevoltages GBNL2,U2 and GBPL2,U2 respectively, which are the shifted versions of the83MU2ou t2ML2IN+IN-G BNL2IN+IN-out FN2IN-ou t1IN+G BNU2G BP L2G BP U2REF N2REF P2F loati n g  recti fi er F loati n g  rev ers e-recti fi erout FP2Open outputsFigure 3.15: Schematic diagram of the proposed auxiliary-cell boostingscheme [4].intermediate voltages MU2,L2 such that the following conditions are satisfied:VGBNL2(DC) > VML2(DC),VGBNU2(DC) > VMU2(DC)VGBPL2(DC) < VML2(DC),VGBPU2(DC) < VMU2(DC)(3.5)Note that although the second stage of the main rectifier and the floatingrectifier cell both receive the same DC input, out1, the floating rectifier cellgenerates higher DC levels both at its intermediate nodes and the output(Equation 3.5) as it drives an open load while the main rectifier cell drives thesucceeding stage. The floating reverse rectifier cell is also designed to generateintermediate voltages with a smaller DC level than that of the main rectifierEquation 3.5.Figure 3.16 shows the simulated DC voltage levels generated at the secondstage of the proposed rectifier. As shown in Figure 3.16a, for different valuesof the input voltage (in+−), GBNL2 and GBPL2 are boosted (shifted) with respect toML2 and satisfy the condition mentioned in Equation 3.5. Also as shown in thefigure, the output of the floating rectifier, outFN2 has a larger DC value compared to84100 200 300 400 5000. amplitude (mV)voltage (V)out1GBPL2GBNL2ML2outFP2outFN2out2(a)t0 +2 +4 +6 +8 +1000. (ns)voltage (V)GBNL2GBPL2 ML2Vin = 200mVfin = 900MHz(b)Figure 3.16: Generated voltage waveforms at the second stage of theproposed rectifier. (a) DC level of the boosted gate drive voltages alongwith the input/output versus input amplitude, (b) Transient waveformof the intermediate node voltage and boosted gate-drive voltages [4].out2 and accordingly, outFP2 has a smaller DC value than that of out1. Figure 3.16bshows the transient RF waveforms of the intermediate voltages ML2 along with theboosted gate-drive voltages GBNL2 and GBPL2 for an input amplitude of 200 mV(circled area in Figure 3.16a) at 950 MHz. As seen, the RF sinusoidal GBNL2and GBPL2 are superimposed on their DC values and are negatively and positivelyshifted versions of ML2 respectively.It should be noted that although the boosting levels (VboostPi and VboostNi inEquation 3.4) need to maintain a fixed value regardless of the variations VMLi,UiDC value, their absolute value could be designed through proper sizing of thetransistors and capacitors in the floating rectifier cells. If required, higher boosting85G BNL1IN+GNDG BNU1G BP L1G BP U1REF N1REF P1IN-au x n1 au x p1G BNL2IN+out1G BNU2G BP L2G BP U2REF N2REF P2IN-au x n2 au x p2G BNL3IN+G BNU3G BP L3G BP U3REF N3REF P3IN-au x n3 au x p3out2out3Figure 3.17: Schematic diagram of the proposed auxiliary-cell boostedrectifier [4].levels could be achieved through adjusting the reference (input) voltage to thefloating rectifier cells or by cascading multiple auxiliary cells (where the last stagesees an open load).Based on the above discussion, the two floating rectifier and reverse floatingrectifier cells emulate the operation of the floating voltage sources of Figure 3.6required for the boosting purpose and consequently efficiency enhancement.The final configuration of the proposed auxiliary-cell boosting scheme isshown in Figure 3.17 for a three-stage rectifier where each stage receive theboosted gate-drive voltages from the two auxiliary cells allocated to drive theNMOS and PMOS switches separately. All the auxiliary cells receive their inputsfrom the input/output of nodes of the associated stage.3.3.1 Design Considerations1. Power considerations: As shown in Figure 3.12, when the resistive load of arectifier cell increases, its output voltage saturates at some specific voltage whilethe output current keeps dropping. Since for an open load, the output DC currenttends to zero, a floating (load-less) rectifier cell theoretically draws no current(power) from the input. In practice, a very small current is drawn from the inputnode which is limited to the current required for charging/discharging the parasiticcapacitances seen by the input. Therefore, the floating rectifier (reverse rectifier)cells provide boosting at practically no cost in terms of power consumption.Moreover, the proposed auxiliary-cell boosting scheme does not depend on anyexternal power source and performs the boosting in a self-sufficient manner. The86G BNL2IN-out FN2CP 1CC C P 2out 1MNF 2MNF 1 M P F 1MP F 2CP 3IN+MLF 2CCC C  =  2 0 0  f F   M P F1 , 2  :2 . 5  ȝm /  0 . 2  ȝm   M N F1 , 2  :2  ȝm /  0 . 2  ȝm  MLF 2Figure 3.18: Parasitics seen by the coupling capacitors in the floating rectifier[4].negligible power overhead and independence from external power source makesthe proposed auxiliary-cell boosting scheme fully compatible with passive RFIDtag applications.2. Area considerations: Since each stage of the rectifier requires two floatingrectifier cells (a total of six cells for a three-stage rectifier), layout area overheadimposed by the proposed scheme has to be considered cautiously. To conservesilicon area, the floating rectifier cells can be designed and implemented in muchsmaller values both for transistors aspect ratios and capacitor sizes. Also note thatas opposed to the main rectifier, floating rectifier cells do not require smoothingcapacitors at their output. Smaller transistors and coupling capacitors for floatingcells (compared to the main rectifier) are allowed since the only load they drive isthe capacitance at the gate of switching transistors in the main rectifier (seeFigure 3.15). Practically, the coupling capacitors of the floating cells could bevery small as long as they maintain a larger value than the summation of theparasitic capacitances they see at the node to which they are connected to. Morespecifically:CC CP1 +CP2 +CP3 (3.6)where, as shown in Figure 3.18, CC is the coupling capacitor of the floating cell,87CP1 and CP2 are the source/drain parasitic capacitance of MNF2 and MPF2respectively and CP3 is the summation of the parasitic gate capacitance of MNF1and MPF1, the gate of the switch driven by GBNL2 (see Figure 3.15) and theparasitic capacitance associated with CC itself. Note that MLF2 and GBNL2 inFigure 3.18 are the same nodes but labeled differently to avoid confusion. Theconstraint set by Equation 3.6 has to be satisfied in order to guarantee that theamplitude of the boosted (shifted) sinusoidal voltage, GBNL2 is not significantlyattenuated as the result of the capacitive division between CC and the parasiticsseen at MLF2. Note that amplitude attenuation of the sinusoidal RF gate-drive hasto be avoided as it deteriorates the efficiency of the rectifier and compromises theeffectiveness of the proposed boosting scheme. More specifically, GBNL2 (inFigure 3.17) is given by:GBNL2 = IN-×CCCC +CP1 +CP2 +CP3(3.7)Therefore, CC  CP1 + CP2 + CP3 follows that GBNL2 ≈ IN-. Such a constraintcould be easily met with a very small value for the coupling capacitor of thefloating rectifier cell relative to that of the main rectifier and thus the proposedarchitecture could be implemented with minimal area overhead. The typicalvalues of the transistors aspect ratios and the coupling capacitor value of thefloating rectifier cell associated with the second stage of the main rectifier areshown in Figure 3.183.4 Proposed Quasi-Floating-Gate Boosting Scheme4In the boosting schemes discussed (switched rectifier, SC gate-boosting andauxiliary-cell boosting), the boosting level is a fixed value. The level of boosting(Vboost) in the switched rectifier is set by the sizing of the rectifier components(transistors and capacitors) and is given by the DC voltage increments at eachstage. In the proposed SC gate-boosting scheme, the boosting level is thesummation of the voltage increment per stage and the external voltage (VGB)applied to the SC voltage source. Finally, in the proposed auxiliary-cell scheme,4The material presented in this section is based on [3].88the boosting level is set by sizing of the floating rectifier cells. The fixed boostinglevels result in a static biasing. In other words, although the maximum PCE(optimal point) occurs at smaller input levels, the optimal point is only achievedfor a single input level (see Figure 3.5). This follows that the PCE curve peaks at acertain input level and drops rapidly at the two sides of the optimal point.However, in many applications where the input level to the rectifier is variable, itis desired to secure a high PCE for multiple points or a wide range of inputs. Sucha scheme requires a dynamic biasing mechanism in which the boosting leveldynamically adapts with the input level such that the optimum biasing is achievedat multiple or a continuous wide range of input levels.In light of the discussion presented in Section 3.1, to obtain a flat PCE curve(i.e., extended high-efficiency range of operation), a boosting mechanism has to bedevised to:1. Positively boost the gate of switches for input levels smaller than the optimalpoint (region-I in Figure 3.5), in order to decrease the effective thresholdvoltage and accordingly increase the forward current.2. Preserve the already generated gate voltages at the optimal point (i.e.,provide a zero boost at maximum efficiency point).3. Negatively boost the gate of switches for input levels larger than the optimalpoint (see Figure 3.5) in order to increase the effective threshold voltage andaccordingly reduce the reverse leakage current.Such a boosting scheme is schematically depicted in Figure 3.19. Note that asopposed to Figure 3.6, the floating voltage sources are variable with the inputlevel. In region-I, for PMOS switches MP1 and MP2, the voltage sources VP1 andVP2 produce a negative voltage between ML-MU and GP1-GP2 respectively,therefore providing the appropriate negative offset such that VGP1,2 < VML,U.Likewise for NMOS switches MN1 and MN2, VN1 and VN2 produce a positiveshift such that VGN1,2 > VML,U. With further increase in the input voltage/power,the absolute value of the variable voltage sources decrease and tend to zero suchthat at the peak of efficiency (optimal input), VP1,2=VN1,2=0 andVGP1,2=VGN1,2=VML,U, i.e., the gates of switches receive the optimal DC levels89MN1 M P 1MN2 MP 2DCn-1DCnV P 1MLMUVN1VN2 VP 2effi ciency ( con venti on al)Max efficiencyV PV NR eg i on  I R eg i on  IIG N1 G P 1G N2 G P 2effi ci en cy  ( ex ten d ed )MLMU(a)R eg i on -I R eg i on -IIOpti mal poi n tE ffi ci en cy( conv en ti on al)G N1G N1G P 1G P 1M LMLG P 1 = ML = G N1G P 1 < ML < G N1 G N1< ML< G P 1E ffi ci en cy  ( ex ten d ed )(b)Figure 3.19: The proposed QFG-biased gate-boosting scheme. (a) schematicdiagram and (b) PCE curve and the boosted gate-drive voltages forNMOS and PMOS switches [3].equal to those of a non-boosted rectifier at the maximum efficiency point.Accordingly, in region-II, VP1,2 provide a positive offset (negative boost) forPMOS switches MP1,2 while VN1,2 produce a negative offset (negative boost) forNMOS switches MN1,2 such that VGN1,2 < VML,U< VGP1,2. The absolute valueof the floating voltage sources keep increasing with the input level in region-II asshown in Figure 3.19a. Figure 3.19a shows how the RF gate-drive voltages aresuperimposed on their boosted DC values in region-I, optimal point and region-II.Obviously in the discussion made above, the PCE curve and the associatedregions are those of the conventional (non-boosted) rectifier which is beingstudied as a basis for the proposed boosting scheme.Contrary to the static boosting schemes mentioned earlier (where the gates of90R F i nDC i nVBi asDC i nVBi asR Larg eC QFGG nG nR F i n  ( DC i n )G nR F i nVboost = Vbias  - DCinMN MNV boostFigure 3.20: Quasi-floating gate biased NMOS transistor [3].transistor are biased through a switching network, SC voltage source and auxiliaryrectifier cells), the dynamic boosting scheme entails a simpler access method tothe gate of switches. Quasi-floating gate architecture presented byRamirez-Angulo et al. [85], provides a direct and cost efficient access method tothe gate of MOSFET transistors. A QFG biased NMOS transistor is shown inFigure 3.20 along with the associated voltage levels. CQFG capacitively couplesthe ac signal, RFin to the gate of the NMOS transistor Gn, while a very largeresistor, RLarge weakly connects VBias to Gn in order to set the DC voltage of thegate to the desired value. RLarge is selected large enough to practically block theac component of the gate voltage. Therefore, as shown in Figure 3.20, RFin issuperimposed on the new DC value (Vbias). The combination of CQFG and RLargein the QFG fashion, emulates the function of a floating voltage source placedbetween RFin and Gn with an offset value as large as Voffset = Vbias−DCin. Inpractice, RLarge is implemented by the large and nonlinear leakage resistance of areverse-biased p-n junction of a transistor in cut-off region [85]. Figure 3.21shows a differential rectifier stage in which the gates of switches are biasedthrough QFG scheme.In order to obtain an extended high-efficiency range of operation (i.e., a flatPCE curve), a dynamic bias generator drives the bias nodes (BiasP,N) in theQFG-biased rectifier of Figure 3.21. Also with reference to Figure 3.20, thedynamic bias generator has to set the bias voltages such that the boost value,VN,P=Vbias N,P−VML,U(DC) meets all the three specifications listed earlier (seeFigure 3.19a). Such bias voltages to satisfy the required specifications for a flatPCE curve are schematically shown in Figure 3.22 in which the DC value of the91MUDCn-1DCnMLMn 1 Mp1Mn 2 Mp2Bi as NBi as PBi as NC QFGC QFGCQFGCQFGBi as PR Larg eR Larg e R Larg eR Larg eMLMUFigure 3.21: Proposed QFG-biased differential rectifier [3].intermediate voltage at each stage is selected as the reference voltage, upon whichBiasP and BiasN are generated. Note that at each stage of the rectifier, the DClevels of the intermediate voltages grow almost linearly with the input asschematically shown in Figure 3.22. BiasN is designed such that VN provides apositive shift in region-I and a negative shift in region-II while it is zero at theoptimal point. Accordingly, BiasP is selected such that VP produces negative shiftin region-I and positive shift in region-II while it is zero at the optimal point. Asshown in Figure 3.22 and assuming a linear growth for the intermediate voltageDCM,L-U, a good candidate for BiasN is a constant voltage level intersecting withDCM,L-U at the optimal point. Also, BiasP has to be set as a linearly increasingvoltage with a slope greater than that of DCM,L-U also intersecting with it at theoptimal point.As mentioned earlier, DCM,L-U has to be used as the reference for VBiasN,Pgeneration. However, VM, L-U is an RF voltage and extracting its DC valuerequires low-pass filtering which comes at the expense of layout area and powerconsumption. As a more efficient approach to generate all the bias voltages(VBiasN-1,2,3 and VBiasP-1,2,3 in a three-stage rectifier), the DC output of therectifier (OUTrec) could be used at minimal cost in terms of power and area. Sucha bias generator is shown in Figure 3.23 where all the bias voltages (VBiasN-1,2,3and VBiasP-1,2,3) are generated by a bandgap reference generator.As shown in Figure 3.23, M1-5 build the core of the bandgap reference92R egi on -I R eg i on -IIOptimal pointDCM,U-LBi asPBi as NV PV Neffi ci en cy  ( conv enti onal)In pu t v oltag eeffi ci en cy  ( ex ten d ed )VNV PVN = Bi as N-DCM,U-LVP = Bi as P -DCM,U-LFigure 3.22: Schematic diagram of the intermediate DC voltage, BiasP,BiasN and the boosting levels of the proposed biasing scheme [3].generator. At steady state operation (when VOUTrec is already established at theoutput of the rectifier), node VBiasN1 produces a fixed, supply insensitive voltagethe value of which could be adjusted by proper sizing of the transistors. For aconstant VBiasN1, M1 and M2 draw a constant current form OUTrec (i.e., ifM1 = M2, I1 = I2 = cte) which follows that the overdrop voltage of M1 isconstant and independent of the value of OUTrec. Therefore, VBiasP3 isestablished as a negatively shifted version of OUTrec. M6-9 and M8-11 mirror thecurrents of M1 and M5 respectively while M7-10 replicate the function of M3.Therefore, through proper sizing of M6-9 and M8-11 while M3=M7=M10, VBiasP2and VBiasP1 are generated in a similar fashion. Note that VBiasP2 and VBiasP1are also negatively shifted versions of OUTrec with larger shift values respectively(i.e., VBiasP3 > VBiasP2 > VBiasP1). Therefore, M6 and M9 are sized larger thanM1 in order to draw larger currents and accordingly higher overdrop voltages. Inorder to obtain the fixed voltage VBiasN2 and VBiasN3, M12-13 and M14-15replicate M2,4 and are sized properly to satisfy VBiasN3 > VBiasN2 > VBiasN1.Note that as opposed to the conventional bandgap reference generator, M5 andaccordingly, M8-11 replace the resistor to further conserve the layout area.Figure 3.24 shows the simulated output waveforms of the bias generator.93M1M2M3M5M4M6M7M8M9M10M11M12M13M14M15Bias P3Bias P2Bias P1Bias N1Bias N2Bias N3I1I2O U T r ecG N DFigure 3.23: The proposed bandgap Bias generator circuitry [3]. (V) (uA)OUTrecoptimalpointregion−IIregion−Icurrentdead zone BiasN2BiasN3BiasN1BiasP2BiasP1BiasP3DCM1Figure 3.24: Simulated voltage waveforms of the bias generator [3].Since the output of the rectifier, OUTrec grows linearly with the input voltage, avoltage ramp is used to simulate OUTrec. As seen, the bias voltage pairs (BiasN,P)are designed to intersect with the associated intermediate voltage (DCMi) at theoptimal point (only DCM1 is shown in the figure). Note that there exists adead-zone associated with the proposed bias generator, i.e., at the beginning of theramp, the bias circuitry fails to provide appropriate bias voltages as the supply isinsufficient. However, the dead-zone does not interfere with the operation of therectifier as it occurs at very small output levels where the rectifier is practicallyinactive. In order to design the intersection points, the DC value of theintermediate voltage of the non-boosted rectifier at the optimal point is selected as940 1 2 3 4 (micro second)voltage (V)BiasP2BiasN2GateN2GateP2transitionOUTREC(a)t0 +0.2 +0.41 +0.62 +0.83 +1.04 + (nano second)voltage (V) OUTRECGateP2GateN2BiasP2BiasN2(b)Figure 3.25: (a) Proposed gate boosting scheme. Transient output waveform,and (b) second stage bias and gate voltages [3].the target and the boosting scheme produces a flat PCE curve at the two sides ofthe mentioned optimal point.For an arbitrary input, Figure 3.25a shows the simulated bias voltagesBiasN2,P2 and the QFG-boosted gate-drive voltages GateN2,P2 for the second stageof the rectifier. Figure 3.25b showing the enclosed area, depicts in more detailshow the RF gatedrive voltages (GateN2,P2) are superimposed on the boosted DClevels (BiasN2,P2).Figure 3.26 shows the schematic diagram of a three-stage QFG biased rectifier.As seen, the output of the rectifier is the only input to the bias generator. Each QFGcell in the figure consists of four QFG resistor-capacitor pair to drive the gate ofthe four switches at each stage. The cells receive the two intermediate voltages ofthe stage and shift them towards the delivered bias voltages to produce the boostedgate-drive voltages.95BiasP3BiasN3BiasP1BiasN1BiasN2BiasP2OUTrecGND Q F Gout 1Q F G Q F Gout 2B ias G ener atorFigure 3.26: Schematic diagram of the proposed QFG boosted rectifier [3].3.4.1 Design Considerations1. Power considerations: The QFG architecture (combination of RLarge andCQFG) facilitates access to the gate of switches at practically no cost in terms ofpower consumption. RLarge could be selected large enough to allow a very smallDC current and therefore, its resistive power consumption is negligible. The onlysource of power consumption in the proposed QFG-boosting scheme is the biasgenerator (see Figure 3.23). The bias generator draws its required current directlyfrom the output of the rectifier which in turn, degrades the PCE. In order tominimize this effect, it has to be designed with minimal current (power)consumption. However, the bias generator has to readjust the generated biasvoltages in response to input level variations and insufficient current results in aslow response time. In a practical RFID application scenario, the rate at which theinput level and subsequently the output of the rectifier varies (usually as the resultof communication distance variations), is typically on the order of a fewmilliseconds and is far longer than the settling time of the bias generator.Slow settling time of the bias generator manifests itself at the start-up when theoutput capacitor starts to charge up and the output voltage rapidly increases to itsfinal value in a few hundred nanoseconds which is too fast for the bias generatorto follow (see the transition region in Figure 3.25a). Therefore, at the start up,96Mp1Bi as CQFGR Larg eVMLC G SSDC G DC G BBV GFigure 3.27: Parasitics associated with the gate of a QFG-biased switch.the rectifier receives incorrect bias voltages. However, this does not interfere withthe transient operation, as the QFG delay (which will be explained later) masks thebias voltage and the rectifier functions in a non-boosted fashion without receivingthe incorrect bias voltages. It is only long after the output has settled that thegate of switches settle to the generated bias voltages and by then, the correct biasvoltages are established. Therefore, as long as the settling time of the bias generatoris not longer than that of QFG delay, the latency of the bias generator does notinfluence the operation of the boosting scheme. This relaxed requirement facilitatesdesigning the bias generator with very small power consumption on the order ofone percent of the output power of the rectifier. The current consumption of thebias generator is shown in Figure 3.24.2. Area considerations: Coupling the RF intermediate voltage (VM, L-U) to the gateof switches through CQFG slightly attenuates the amplitude of the ac componentdue to the capacitive division formed between the gate capacitance of the switch,CG, and the QFG capacitor, CQFG. The ac component attenuation degrades thePCE and has to be minimized. Figure 3.27 shows the QFG-biased switch MP1along with the parasitic capacitances for which the delivered ac component at thegate could be written as [85]:97VG =s ·RLarge1+ s ·RLarge ·Ctot×(VML ·CQFG +VS ·CGS +VD ·CGD +VB ·CGB)(3.8)where Ctot, is the total capacitance seen at the RF intermediate voltage node(VM, L-U) and is given by:Ctot = CQFG +CGS +CGD +CGB (3.9)CGS, CGD and CGB are the gate-source, gate-drain and gate-bulk parasiticcapacitances of MP1 respectively. For UHF frequencies and assuming CQFG CGS + CGD + CGB, Equation 3.8 reduces to:VG =CQFGCtot×VML (3.10)The assumption CQFG CGS + CGD + CGB follows that Ctot≈CQFG and therefore,VG≈VML. It should also be noted that a very large CQFG will result in a longersettling time as will be discussed later. However, this trade-off between ac signalattenuation and settling time is not very challenging since the condition CQFG CGS + CGD + CGB could be easily satisfied with a reasonable settling time.The QFG architecture of Figure 3.21 forms a low-pass RC filter along the pathfrom the bias node (BiasN,P) to the gate of the associated switch (GN,P).Therefore, the DC value of the gate experiences a delay before fully settling to thedesired value VBiasN,P. More specifically, as a result of the input level variations,the output of the rectifier (OUTrec) changes and accordingly, the bias generatorprovides new bias voltages to readjust the boosting levels. However, the new biasvalues are received at the gate of switches with a delay. As shown in Figure 3.28 ,the equivalent capacitance seen by the QFG resistor (RLarge) is given by:Ceq = CG +{CQFG ||(CN +Cp1 +Cp2 +CC)} (3.11)98Mn 1 Mp1Mn 2 Mp2Bi asC Q F GR Larg eMLCNC P 2 C P 1CCC GBi asG PG PR Larg eCeqFigure 3.28: Low-pass filtering characteristic of QFG architecture.where Ceq is the capacitance seen by RLarge, CG is the gate capacitance of theswitch Mp1 (CG = CGS + CGD + CGB), CQFG is the QFG capacitance, CN is the totalcapacitance node ML sees toward the switch MN1 (i.e., CN = CQFG + CGn1), Cp1 andCp2 are the parasitic capacitances of the source/drain of Mp2 and Mn2 respectivelyand CC is the coupling capacitor. The coupling capacitor CC is typically muchlarger than all the parasitic components which yields CN+Cp1+Cp2+CC≈CC.As mentioned earlier, CQFG could be implemented with a very small value (equalto a quarter of CC in the proposed scheme). Therefore Ceq≈CG+0.2CC≈0.2CCwhich for a typical CC=500 fF gives an equivalent capacitance of 100 fF. Theaverage value of RLarge is on the order of 1 MΩ∼10 MΩ which gives the averagetime constant of T=RLarge×Ceq=0.1µs∼1µs for the QFG low pass filter. Thegate of switches require a few time constant periods to settle to the desired valueVBiasN,P (typically Tsettle=4·RLarge×Ceq=0.4µs∼4µs). The settling response timeof the QFG architecture approximated above is much faster than the rate of inputvariations in a practical RFID tag application (typically on the order of a fewmilliseconds). Therefore, the trade-off associated with the value of CQFG (acsignal attenuation and QFG delay) could be resolved with a reasonably smallvalue of CQFG and consequently minimal layout area overhead. Figure 3.29 showsthe settling behavior of the QFG architecture in response to a step function of99Figure 3.29: Transient response time of QFG architecture.amplitude 300 mV (600 mV to 900 mV) applied as VBias. As shown in the figure,the gate of the transistor settles with a good accuracy to the desired value ( i.e.,900 mV) within 2 µs.3. Bias generator design considerations: In regards to the operation of theproposed bias generator, there are a few issues in addition to power and areaoverhead which need to be considered carefully in the design process.a- The generated bias voltages (as a function of input level) are an approximationof the theoretical ideal values. In order to obtain ideal bias voltages (andconsequently optimum effective threshold values for switches) for any given inputlevel, the DC value of the intermediate voltage at each stage has to be extractedand processed. For any given input level, a feedback controller is required toexercise different bias values and continuously monitor the output voltage of therectifier for a maximum level. The bias voltages associated with the maximumlevel are the ideal values for the specific input voltage of interest. However, thecomplexity overhead would compromise the marginal efficiency improvementgained by such an ideal approach.b- The bias voltages by the bandgap reference generator will deviate from thedesignated values as the result of process and temperature variations. However, avery robust design for the bandgap reference generator is not mandatory as the100overall efficiency performance of the proposed QFG-boosted scheme is notsensitive to slight variations in the bias voltages. Moreover, an inherent feedbackloop partially corrects the generated bias voltages in case of discrepancy. Notethat if for any input level in region-I, the generated bias voltages are higher thanthe desired value, while the PCE drops, the output voltage grows since theswitches are over-boosted. However, with reference to Figure 3.23, higher outputvoltage OUTrec (and consequently higher intermediate voltage level DCM,U-L)produces smaller boost levels as VN,P =VBias N,P − DCM,U-L and therefore act tocorrect the over-boosting. In region-II, higher than desired bias voltages signifiesunder-boosting and therefore results in the decreased OUTrec which in turn workstowards decreasing the bias voltages and the negative boost. The reverse scenariooccurs if the bias voltages are smaller than what is desired.c- The resistance of the reversed-biased p-n junction (RLarge) is voltage leveldependant and changes with VBias and VG variations. However, its absolute valuedoes not interfere with proper operation of QFG scheme as long as its impedancemaintains large enough to block the ac component of the gate voltage andprevents DC current flow, to or from the bias node. The only effect of the variableRLarge manifests itself in the settling time of the QFG architecture. As explainedin details earlier, for typical capacitance values, a 10X increase in the value ofRLarge still gives reasonable settling times.d- As a final remark, it is worth mentioning that generally maintaining the highPCE for input levels beyond the maximum efficiency point (i.e., region-II) is not ascrucial as it is for input levels below it. In particular, a conventional (non-boosted)rectifier is designed to supply a load at the optimal efficiency point. Although theratio of the output to input power drops beyond the optimal point, the output powerkeeps growing with the input regardless of the efficiency drop. Thus, the load isguaranteed to receive the required energy for proper operation. A flat PCE curveproves specifically beneficial in applications where the input power (continuoussinusoidal wave) is only transmitted for a short period of time and the rectifierstores the received energy in a battery or a super capacitor. Therefore, higher PCEtranslates to a higher stored energy to run the tag for a longer time. Moreover, theproposed scheme facilitates optimizing the rectifier for smaller inputs.1013.5 Post-Layout Simulation Results for the ProposedEfficiency Enhancement TechniquesProof-of-concept prototypes of the three-stage rectifiers incorporating the proposedefficiency enhancement schemes were designed and laid out in a 0.13 µm CMOStechnology. The transistor aspect ratios were designed to optimize the performanceat the frequency of operation and based on load requirements. Capacitors wereimplemented by MIM structure. The three proposed efficiency enhanced rectifierswere studied in terms of PCE, output voltage and power, load value and frequencyof operation.3.5.1 Switched Rectifier and switched-capacitor Boosted Rectifier 5External VDD = 0.6 V, VB = 0.3 V and VGB = 0.2 V are externally applied as theclock generator supply, the clock generator tail bias voltage and the SC voltagesource boost value respectively. For an input frequency of 950 MHz andRL=10 kΩ, Figure 3.30a and Figure 3.30b show the PCE curves for the switchedand SC rectifiers respectively versus the input voltage and power. The PCE curveof the conventional (non-boosted) rectifier is also shown for comparison. Notethat the power axis only refers to the proposed rectifiers and does not show theinput power of the conventional one. The power consumption of the clockgenerators and the VGB network are accounted for in obtaining the PCE. The sixclock generators (two for each stage) dissipate a total power of 7.2 µW and the sixVGB distributers consume 6.5 µW. As shown, the switched rectifier achieves a74% PCE at −10 dBm which outperforms the conventional rectifier.It should be noted that compared to the conventional rectifier, the switchedrectifier fails to enhance the PCE for small input levels as the voltage increment ateach stage is insufficient for proper operation of the proposed boosting scheme.The SC rectifier on the other hand receives the external VGB and outperforms theconventional rectifier at very small input levels (long communication distances).The SC rectifier achieves a PCE of 57% at −26 dBm. In terms of input voltagethe maximum efficiency for the gate-boosted rectifier occurs at 350 mV inputamplitude which proves a significant enhancement over the corresponding5The material presented in this subsection is based on [7].1020.2 0.4 0.6 0.8 120406080input voltage (V)PCE (%)  −30 −20 −15 −10 −8input power (dBm)switchedconventionalfin= 950 MHzRL = 10 kΩ(a)0.2 0.4 0.6 0.8 1102030405060input voltage (V)PCE (%)  −27 −26 −23 −15 −5input power (dBm)SCfin= 950 MHzRL = 10 kΩconventional(b)Figure 3.30: PCE performance (a) Switched rectifier, and (b) switched-capacitor rectifier [7].maximum efficiency input voltage of 800 mV for its switched rectifiercounterpart. Moreover, as inferred from Figure 3.30, the gate-boosted rectifier iscapable of providing acceptable PCE for input voltage amplitudes well below thethreshold voltage of CMOS transistors in 0.13µm technology whereVthn = 0.355 V and Vthn = −0.325 V. However, the input voltage rangeenhancement is achieved at the cost of more power consumption (exposed bybooster network) and consequently smaller overall PCE. Also as shown, withrespect to switched rectifier, PCE of gate-boosted rectifier drops for smaller values1030.2 0.4 0.6 0.8 10.511.52input voltage (V)output voltage (V)  RL= 10 kΩRL= 50 kΩRL= 100 kΩfin = 950 MHz(a)0.2 0.4 0.6 0.8 10.511.52input voltage (V)output voltage (V)  RL= 10 kΩRL= 50 kΩRL= 100 kΩfin = 950MHz(b)Figure 3.31: Output voltage versus load value. (a) Switched rectifier, and (b)switched-capacitor rectifier [7].of input power and input voltage, which is due to the fact that beyond a certainpoint corresponding to maximum efficiency, extra boosting poses additionalleakage currents which leads to the observed PCE degradation.The rectified output voltage versus load value of the switched and SC rectifiersare shown in Figure 3.31a and Figure 3.31b respectively. As shown in the figures,the SC-boosted rectifier provides a lower turn-on voltage compared to the switchedrectifier. For a load of 100 kΩ, the output voltage of 0.5 V is achieved at the inputvoltage of 0.45 V and 0.22 V for the switched rectifier and SC rectifier respectively.Also note that larger load generates larger output voltage and consequently higher1040.4 0.6 0.8 150100150200input voltage (V)output power (µW)  RL = 10 kΩRL = 50 kΩRL = 100 kΩfin = 950 MHz(a)0.4 0.6 0.8 150100150200250input voltage (V)output power (µW)  RL = 100 kΩRL = 50 kΩRL = 10 kΩfin = 950 MHz(b)Figure 3.32: Output power versus load value. (a) Switched rectifier, and (b)switched-capacitor rectifier [7].voltage increments at each stage which in turn enhances the switching schemeperformance.The output power versus load value of the switched and SC rectifiers are shownin Figure 3.32a and Figure 3.32b respectively. As shown in the figures, the SC-boosted rectifier provides a higher output power for similar input voltage.Finally, the frequency performance of the two rectifiers are depicted inFigure 3.33 for 950 MHz and 2.4 GHz input frequencies. As shown, the PCEperformance is degraded at higher frequency which is attributed to the higher1050.3 0.4 0.5 0.6 0.7 0.8 0.9 120406080input voltage (V)PCE (%)  fin = 950 MHzfin = 2.4 GHz(a)0.2 0.3 0.4 0.5 0.6 0.7 0.82030405060input voltage (V)PCE (%)  fin = 950 MHzfin = 2.4 GHz(b)Figure 3.33: Frequency performance. (a) Switched rectifier, and (b)switched-capacitor rectifier [7].power consumption of the clock generator. Moreover, the comparatorincorporated to provide the clock edges fail to perform as accurately at 2.4 GHz.The adverse effect of parasitic capacitances of both switches and switchingtransistors also contribute in degradation of PCE at higher frequencies.3.5.2 Auxiliary-cell Boosted Rectifier 6The proposed auxiliary-boosted rectifier is fully compatible with UHF passiveRFID applications and requires no external supply or circuitry. For a 950 MHz6The material presented in this subsection is based on [4].1060.1 0.2 0.3 0.4 0.520406080input voltage (V)PCE (%)−38 −19 −14 −10 −6input power (dBm)+30%Aux−boosted conventionalfin = 950MHZRL = 50 kΩFigure 3.34: PCE of the proposed auxiliary-cell boosted rectifier [4].input frequency and 50 kΩ load, the PCE of the proposed auxiliary-boostedrectifier along with that of the conventional (non-boosted) rectifier are shown inFigure 3.34. As compared to the conventional architecture, the enhancedefficiency scheme provides a higher PCE for smaller input levels whichcorresponds to a longer communication distance.As seen from the figure, the efficiency curve of the proposed rectifier is shiftedto the left relative to the convectional rectifier and a PCE of 54% is achieved atthe low input voltage/power of 200 mV (− 19 dBm) while the PCE is 24% for itsconventional counterpart at the same input level. The PCE curve could be furthershifted to the left (towards smaller inputs) through optimizing the floating rectifiercells and therefore manipulating the boosting levels. Note that the peak PCE valuefor the proposed rectifier is approximately 1% smaller than that of the conventionalrectifier which can be attributed to the power consumption of the floating rectifiers(boosting generation circuitry).For a load of 50 kΩ, the output voltage of the proposed auxiliary-boostedrectifier is compared with that of the conventional rectifier in Figure 3.35. Asshown in the figure, the boosted rectifier generates a 0.6 V output at the input levelof 0.2 V, while this value is 0.25 V for its conventional counterpart.As a function of the load resistance, the output voltage, PCE and the output1070.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50.511.52input voltage (V)output voltage (V)+0.35 VconventionalAux−boosted fin = 950 MHzRL = 50 kΩFigure 3.35: Output voltage of the proposed auxiliary-cell boosted rectifier[4].power of the proposed auxiliary-boosted rectifier are shown in Figure 3.36a,Figure 3.36b and Figure 3.36c respectively. Since the boost-generator (floatingrectifier cells) receives their reference from the output voltages of the mainrectifier stages, they track the DC level variation of the output as the result of loadvariations. Therefore, the gates of switches receive appropriate boostingregardless of the load (output voltage variations) and the load dependencyobserved is what is expected from the conventional rectifier. In other words, theboosting generator does not impose additional load dependency.Finally, the frequency dependency of the proposed auxiliary-boosted rectifier isshown in Figure 3.37 for 950 MHz and 2.4 GHz input frequencies. In virtue of thesmall aspect ratios of the boosting generator (floating rectifier cells), the proposedrectifier is not severely affected by the increase in the frequency of the input. Theminor PCE degradation at 2.4 GHz compared to 950 MHz frequency is attributedto the adverse effect of parasitic of the floating cells as well as the main rectifier.3.5.3 Quasi-Floating-Gate Boosted Rectifier 7The proposed QFG-boosted rectifier is fully compatible with UHF passive RFIDapplications and no external supply or circuitry is used. The bias generator7The material presented in this subsection is based on [3].1080.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50.511.52input voltage (V)output voltage (V)  RL = 20kΩRL = 50kΩRL = 100kΩ(a)0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.520406080input voltage (V)PCE (%)  RL = 20kΩRL = 50kΩRL = 100kΩ(b)0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.550100input voltage (V)output power (µ W)  RL = 20kΩRL = 50kΩRL = 100kΩ(c)Figure 3.36: Performance of the proposed auxiliary-cell boosted rectifier asa function of load value. (a) Output voltage, (b) PCE and (c) Outputpower [4].1090.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.520406080input voltage (V)PCE (%)  fin = 2.4GHzfin = 950MHzRL = 50 kΩFigure 3.37: Frequency dependency of the proposed auxiliary-cell boostedrectifier [4].(bandgap reference) is supplied by the main rectifier output.For a 30 kΩ load and at 2.4 GHz input frequency, the PCE of the proposedQFG-boosted rectifier is shown in Figure 3.38 along with the PCE of theconventional (non-boosted) rectifier. Compared to the conventional rectifier, theQFG-boosting scheme provides a rather flat PCE curve around the maximumefficiency point (Vin=0.45 V) by reducing the rate at which efficiency dropsthrough dynamically biasing the gate of switches. The PCE of the proposedrectifier stays over 60% for a wide input range from 0.25 V to 0.7 V (0.45 Vvoltage range corresponding to 12 dBm) while this range for its conventionalcounterpart is from 0.38 V to 0.56 V (0.18 V corresponding to 4 dBm). Note thatthe PCE of the QFG-boosted rectifier at the optimal point is slightly smaller thanthat of the conventional rectifier (66.6% compared to 68.9%) which is attributedto the power consumption of the bias generator.As discussed in Section 3.4, at the optimal point, the QFG-boosted rectifierand the non-boosted rectifier receive the same gate-drive voltages. Therefore theytheoretically achieve similar efficiency. However, the QFG-boosted rectifier stillsupplies current to the bandgap reference generator which slightly degrades its PCEperformance at the optimal point. The power overhead imposed by the referencegenerator is overcompensated for the rest of input range by virtue of optimumbiasing provided to the gate of switches and the resulted flat PCE curve. As shown1100.2 0.3 0.4 0.5 0.6 0.720406080input voltage (V)PCE (%)  −24 −12 −9 −7 −5 −3input power (dBm)QFG−boostedconventionalfin = 2.4 GHzRL = 30kΩFigure 3.38: PCE of the proposed QFG-boosted rectifier [3].in Figure 3.38, the PCE of the proposed rectifier drops rapidly for input amplitudessmaller than 0.25 V as the bias generator fails to produce correct bias voltageswhen the output of the rectifier (OUTrec) is too small (see the dead zone region inFigure 3.24).As a function of the load resistance, the output voltage, PCE and the outputpower of the proposed QFG-boosted rectifier are shown in Figure 3.39a,Figure 3.39b and Figure 3.39c respectively. As shown in the figures, since thebias voltages and the resulted boosting levels are generated in accordance with theoutput of the rectifier (in a feedback loop fashion as discussed in Section 3.4), theoutput voltage and PCE of the QFG-boosted rectifier is almost insensitive to loadvariations. This load independency relaxes the output regulation requirements andis specifically desirable in applications where the load is variable.The frequency dependency of the proposed QFG-boosted rectifier is shownin Figure 3.40. Note that the bandgap reference is not affected by the frequencyof operation as it receives the rectified DC output of the rectifier and generatesDC bias voltages. The degraded PCE performance of the rectifier at the higherfrequency is due to the parasitics of the main rectifier transistors and couplingcapacitors as well as the parasitics of QFG architecture.Figure 3.41 shows the current drawn by the bandgap bias generator from the1110.2 0.3 0.4 0.5 0.6 0.70.511.522.53input voltage (V)output voltage (v)  RL= 30 kΩRL= 40 kΩRL= 50 kΩ(a)0.2 0.3 0.4 0.5 0.6 0.7020406080input voltage (V)PCE (%)  RL= 50 kΩRL= 40 kΩRL= 30 kΩ(b)0.2 0.3 0.4 0.5 0.6 0.7100200300input voltage (V)output power (uW)  RL= 30 kΩRL= 40 kΩRL= 50 kΩ(c)Figure 3.39: Performance of the proposed QFG-boosted boosted rectifier asa function of load value. (a) Output voltage, (b) PCE and (c) Outputpower [3].1120.2 0.3 0.4 0.5 0.6 0.7203040506070input voltage (V)PCE (%)  fin= 2.4 GHzfin= 935 MHZFigure 3.40: Frequency dependence of the proposed QFG-boosted rectifier[3].0.2 0.3 0.4 0.5 0.6 0.700.511.522.53input voltage (V)current (uA)  0.511.522.53output voltage (V)OUTrecIbiasFigure 3.41: Current consumption of the bandgap bias generator [3].output of the rectifier. As shown, the current consumption of the referencegenerator grows linearly with its supply voltage (the output of the rectifier,OUTrec). At the optimal point (Vin = 0.45V), the bias generator consumes2.42 µW (corresponding to 1.77 V×1.37 µA) which contributes to the 2.3 %reduction of the efficiency (66.6% ) as compared to the conventional rectifier(68.9%).The layout views of the proposed rectifiers are shown in Fig. 42. As shown inthe figure, the switched rectifier area is 280µm×70µm, the switched-capacitorrectifier area is 690µm×420µm, the auxiliary-boosted rectifier area is300µm×220µm and the QFG-boosted rectifier area is 320µm×140µm.1136 9 0 um420 um2 8 0 um70 um3 2 0 um140 um3 00 um220 umS CS witch edQ FGA U XFigure 3.42: Layout view of the proposed rectifiers.Although the sizing requirements of capacitors associated with each boostingscheme are slightly different (as discussed earlier in this chapter), the number ofcapacitors per stage for each scheme could be considered as a rough estimation ofthe area overhead imposed by each technique. The switched rectifier does notrequire any capacitor and only relies on the clock generator and small-sizedswitches (see Figure 3.7) and therefore occupies the smallest area among theproposed rectifiers. On the other hand, the SC-boosted rectifier incorporates fourSC voltage sources at each stage with two capacitors per voltage source (Crefresh,CBoost in Figure 3.10), adding up to a total of eight capacitors per stage accountingfor its largest layout area. The auxiliary-boosted rectifier requires two rectifier114Table 3.1: Performance summary of the proposed efficiency enhancementtechniques and comparison with state-of-the-art [3, 4, 7].Reference Technology Frequency Load Vout (PCEmax) PCEmax PCE (LV)[78]a? 0.18 µm 953 MHz 10 kΩ 0.6 V (−12.5 dBm) 67.5 % (−12.5 dBm) 28 % (−19 dBm)[78]b? 0.18 µm 953 MHz 30 kΩ 2.5 V (−6 dBm) 62 % (−6 dBm) 10 % (−19 dBm)[79]?? 0.18 µm 950 MHz 2 µW 0.5 V (0.36 V) 23 % (0.36 V) 23 % (0.36 V)[80]? 0.18 µm 950 MHz 4 µA 0.5 V (0.36 V) 60 % (0.36 V) 46 % (0.3 VSW? 0.13 µm 950 MHz 10 kΩ 1.4 V (0.8 V) 74 % (−10 dBm) 24 % (0.5 V)SC? 0.13 µm 950 MHz 10 kΩ 0.6 V (0.34 V) 57 % (−26 dBm) 45 % (0.3 V)AUX? 0.13 µm 950 MHz 50 kΩ 1.25 V (0.29 V) 73 % (0.29 V) 54 % (0.2 V)QFG? 0.13 µm 2.4 GHz 30 kΩ 1.8 V (0.45 V) 66 % (0.3∼0.5 V) 60 % (0.25 V)?Post-layout simulation results. ?? Measurement results.asingle-stage prototype bthree-stage cwhole power extraction systemdPCE>60% for 0.25V-to-0.7Vcells per stage with two coupling capacitors each (Figure 3.15), adding up to atotal of four capacitors per stage. The QFG-boosted rectifier requires four QFGcells per stage with one capacitor per QFG cell (Figure 3.21) resulting in a total offour capacitors per stage. Note that the auxiliary boosted rectifier occupies alarger area compared to QFG-boosted rectifier since as opposed to theQFG-boosted rectifier, the size of the coupling capacitors in floating rectifier cellsgrows along the rectifier chain to produce sufficient boosting.Table 3.1 provides the performance summary of the proposed efficiencyenhanced rectifiers along with a comparison with the state-of-the-art designs inthe same category of UHF differential rectifiers. As shown in the table, theswitched rectifier archives a high PCE of 74% for a moderate input level of−10 dBm while the switched-capacitor rectifier provides a good PCE of 57% atthe low input level of −26 dBm. The auxiliary-boosted rectifier also provides ahigh PCE of 73% for the small input voltage of 0.29 V while the QFG-boostedrectifier achieves a goos PCE of 66% for a wide range of input voltages between0.3 V to 0.5 V.115Ls  ( f ix e d )Cin (var)f1         f2Rin antenna (RS)recti fi erFigure 3.44: Proposed matching scheme.3.6 Proposed Dual-Band Matching Scheme 8Although the rectifier constitutes the core of the wireless power harvesting unit, inpractice, it is the combined efficiency of the antenna and the rectifier (rectenna)that affects the overall performance of the power harvesting unit. Variousarchitectures have been proposed to facilitate a dual frequency band rectenna[86–89]. However, most of the designs address the problem by using discrete(off-chip) antenna structures which generally need a relatively large footprint andthus may not be applicable to applications that require a small antenna (e.g.,biomedical implants).It should be noted that the input impedance of a CMOS rectifier is a parallelcombination of a capacitor Cin and a resistor Rin as shown in Figure 3.44 [79].Therefore, for a fixed antenna architecture, one could modify the value of theinput capacitance (Cin) to obtain the required matching at different frequencies.The resistive (real) part of the input impedance represents the average DC currentdrawn by the input. As shown in Figure 3.45 for the first stage, the capacitive partof the input impedance accounts for the series combination of the couplingcapacitors CC and the parasitic capacitances seen at the intermediate node, Cpar.Note that for CC Cpar, the input capacitance is dominated by Cpar in which thecapacitance of Mn1 (CS,n1) is the biggest contributor. The value of CS,n1 is afunction of its gate bias voltage. Therefore, the input capacitance of the rectifiercan be adjusted by modulating the bias voltage of the NMOS switches of the firststage (Mn1,2). To avoid the adverse effects of the bias voltage variation on thePCE of the rectifier (as discussed in Section 3.4), an auxiliary floating cell could8The material presented in this subsection is based on [1].116GND ou t1M n 1 Mp1M n 2 Mp2i n +i n -C i n + CCCCCpari n +Ci n +CCCparCparCS ,n 1 C S ,p1C G, n2C G, p2C i n -Cs mC smFigure 3.45: Schematic of the first stage of the rectifier and its inputcapacitance.be connected in parallel with the main rectifier (similar to the technique proposedin Section 3.3) such that the desired variation in Cin is obtained by adjusting thebias voltage of the NMOS switches in a fashion similar to technique used inSection 3.4. The resonance frequency of the matching network in Figure 3.44 isgiven by fres = 1/2pi√LsCin. For a fixed LS, to obtain a voltage matching for twoinput frequencies f1 and f2 (where f1 < f2), Cin has to be adjusted such thatCin1/Cin2 = (f2/f1)2.As shown in Figure 3.46, Cin could be increased by connecting the gates of M1,2to a higher voltage (Vbias). The rectifier starts in mode-2 (fin = f2) with Cin = Cin2(as the flip-flop controller has reset SW = 0) and the output voltage starts to buildup.The transition from the higher frequency (f2) to the lower frequency (f1) isfollowed by a rapid drop in the output voltage of the rectifier (Vout) since thematching network (LS) does not resonate with Cin2 at f1 and the voltage matchingis compromised. The drop in the output voltage is sensed by the comparatorwhich subsequently sets SW = 1 through the controller. The increase in the gatebias voltage of M1,2 increases the input capacitance to C1 so that it resonates withLS at frequency f2 and establishes the voltage matching. The negativeedge-triggered flip-flop is connected in a divide-by-two mode to avoid theunnecessary transition of SW when the output voltage starts to grow.117GNDM ain R ectifierF FCLK R S TDQQ bbiasctrlout2 c om poutR ef G en.refcon trollerS Wmatching i n+i n-A u x i li ary  cell ( v ari ab le cap)  f 1- f 2antenna M1M2Figure 3.46: Block diagram of the proposed dual-band matching scheme.The reference voltage of the comparator is generated by a band-gap referencegenerator. The bias voltage is extracted from the output of the floating auxiliarycell (refer to Section 3.3) and is fed to the gates of M1,2 in a QFG fashion (refer toSection 3.4). Note that the value of bias voltage could be designed such that theinput capacitance covers the dynamic range of Cin and provides a range ofresonance frequencies. The comparator, reference generator and the flip-flopcontroller are supplied by the output of the main rectifier to enable a self-sufficientoperation of the proposed matching scheme.3.6.1 Simulation ResultsA proof-of-concept prototype of the proposed dual-band rectifier is designed andsimulated in a 0.13 µm CMOS technology. Two 20 nH inductors are used tomatch the 50 Ω source to the input capacitance of the rectifier. For a 50 kΩ load,Figure 3.47 shows the transient response of the proposed scheme for the sourceinput amplitude of 40 mV (before matching) at two different input frequencies of950 MHz and 2.4 GHz. As shown, the comparator triggers the control signal, ctrl,once out2 falls below the reference voltage. The flip-flop turns on the switchsignal (SW ), upon sensing the falling edge of ctrl to switch the input capacitanceto its higher value Cin1 (mode 1). SW turns off at the next falling edge of ctrl toswitch the rectenna back to mode-2.1180.5 1 1.5 2 2.5 3 3.5 4 4.5 500.51time (µs)voltage (V)SWf2 = 2.4 GHzf1 = 950 MHzRefctrloutout2Figure 3.47: Transient response of the proposed matching scheme.0.5 1 1.5 2 2.5 3−30−20−100Frequency (GHz)S 11 (dB)  SW = 1 (mode−1)SW = 0  (mode−2)f2 = 2.4 GHzf1 = 950 MHzFigure 3.48: Frequency response of the proposed matching scheme.Accounting for the power consumption of the comparator, band-gap referencegenerator and the flip-flop controller, the rectenna generates an output voltage of∼1 V in mode-2 (fin = 2.4 GHz) and achieves the PCE of 64% for an inputamplitude of 40 mV. The output voltage and PCE in mode-1 (fin = 950 MHz) are∼0.9 V and 55%, respectively. The slight degradation in output voltage and PCEperformance of the rectenna in mode-1 can be attributed to the larger portion ofthe input power being shunt to the ground due to the added input capacitance(through M1,2). The auxiliary cell generates a bias voltage (Vbias) of ∼0.6 V. Thesimulated frequency response of the proposed matching scheme is shown inFigure 3.48.1193.7 ConclusionIn this chapter, three efficiency enhancement techniques applicable to UHF RFIDrectifiers are presented. The proposed efficiency enhancement techniques improvethe PCE of the rectifier when the input level is small and therefore, facilitate alonger communication distance and/or higher energy levels delivered to the tagscircuitry.The proposed switched rectifier archives a high PCE value for larger inputlevels (compared to the convectional rectifier) while the SC rectifier provides ahigh PCE for smaller input levels which corresponds to longer communicationdistances. The switched and SC rectifier are dependent on high-speed clockgenerators and rather bulky switched-capacitor network. Moreover, the SCrectifier requires an external voltage (power) source for the start-up and therefore,does not easily lend itself to passive implementation.The AUX-boosted rectifier uses floating rectifier cells for the purpose ofvoltage-boost generation and is therefore, fully compatible with passive RFIDrequirements. However, a three-stage AUX-boosted rectifier requires six floatingrectifier cells (two for each stage) and consequently twelve capacitors. Althoughas discussed in Section 3.3.1, the requirements for the auxiliary cells are relaxed,the imposed area overhead has to be taken has to be accounted for.The QFG-boosted rectifier is the most attractive design among the proposedarchitectures in terms of area overhead and flexibility. The QFG structure allowsdirect access to the DC voltage level of the gate of switching transistors and can beused to dynamically adjust the PCE curve of the rectifier based on the applicationrequirements.Built upon the discussed efficiency enhancement techniques, a dual-bandmatching approach for the rectifier is presented. The proposed dual-bandmatching is based on dynamic modification of the input capacitance of therectifier in response to variations of the input frequency. The proposed techniquecan be extended to a multi-band matching approach and/or to extend thebandwidth of the matching network for a single-band operation.To study the performance of the proposed rectifiers in a practical applicationscenario, an ultra-low-power monitoring system for inductively-coupled120Decision circuitM onitoring sy stemT unabl e efficiency rectifierA l ignment T XA ntenna S mall power (alignment mode) S uf f icient power (monitoring mode)M onitoring T XR ef.C omp .PCEPow er l evelalignment monitoringFigure 3.49: Schematic diagram of monitoring system.biomedical implants is designed in [5, 8]. The monitoring system is equipped withan alignment mechanism. The alignment unit facilitates monitoring the receivedpower by the tag’s antenna in the proposed system. The received RF power by theantenna is rectified and the produced voltage is compared with an on-chipgenerated voltage. If the received power level is insufficient for proper operationof the main monitoring system, the tag transmits the appropriate signal to thereader, signifying the misalignment between the reader and the tag’s antenna.Note that although in the alignment mode, the received power by the tag isinsufficient to supply the monitoring system, the high efficiency rectifier providesenough energy for the the decision circuit and tag to transmit the misalignmentsignal. Upon receipt of the misalignment signal, the user can readjust the positionof the external reader so as to deliver sufficient power to the system.The entire system includes two transmitters, one low power transmitter foralignment mode and a more elaborate one for the monitoring mode. Alsoincorporated in the system is a decision circuit comprising of a comparator and areference generator. The decision circuit activates each of the two transmittersbased on the received power level.Also crucial to this design is a rectifier which is capable of providing twooptimal efficiency points, one for the alignment mode (low input power level) andone for the monitoring mode (sufficient input power level). The rectifier isoptimized for the monitoring mode (i.e., high input power level). In the alignmentmode when the tag receives small RF power and consequently small input voltage121is delivered to the rectifier input, floating voltage sources (in a fashion similar tothe design presented in Section 3.4) are incorporated to boost the gate-drivevoltage of the switches. During the monitoring mode, the decision circuitswitches off the booster circuit (voltage sources) such that the rectifier operates atits optimal point. Figure 3.49 schematically shows the operation principles of themonitoring system.The circuit blocks of the monitoring system are designed and simulated in a0.13 µm CMOS technology. Details of the design are presented in [8].To provide experimental results for a practical application scenario, anultra-low-power integrated circuit is designed for a telemonitoring systems. Thesystem comprises different building blocks including wireless power harvestingunit and a high efficiency rectifier, clock generator, capacitance-to-voltageconverter and transmitter. Design techniques are developed to significantly reducethe power consumption of the system. The high efficiency rectifier supplies theentire monitoring circuitry. The monitoring system is capable of operating with aninput level as low as − 43.76 dBm. For a rectified voltage as low as 0.35 V, asensitivity of 3.1 kHz/fF is achieved for the capacitance-to-voltage converter. Thisvalue is improved to 55.0 kHz/fF for a 1.0 V rectified voltage. Details of thedesign are presented in [8].122Chapter 4Power Efficient Receive andTransmit SchemesIn this chapter, power efficient schemes for receive and transmit mode of wirelesssensor nodes and RFID tags are discussed. In most of RFID applications, the tagneeds to be wary of the incoming command from the reader. Therefore, amechanism is required to guarantee the tag is constantly listening to thecommunication channel (even when no signal is being transmitted by the reader).the power consumed by the tag’s receiver during such idle mode is practicallywasted. Since the receiver contributes significantly to the overall powerconsumption of the tag, a method that reduces/eliminates such unnecessary powerdissipation could be quite beneficial in an efficient implementation of tags.Wake-up radio concept as an asynchronous (event-based) scheme cansignificantly reduce the power consumption of the tags receiver during the idlemode and will be discussed in this chapter.Typically, the power consumption of the transmitter unit is the biggestcontribute to the overall power consumption of any wireless communicationsystem. However, Passive RFID tags are generally incapable of accommodating asophisticated transmitter due to their very tight power budget. Therefore, analternative transmission method that reduces/eliminates the transmit mode powerdissipation would be very desirable in the context of passive RFID tags.Backscattering method is an attractive approach for the transmission of signals123from passive RFID tags as it basically eliminates the need for a dedicated (active)transmitter. Backscattering scheme is discussed in this chapter in the context oftelemonitoring systems for biomedical implants.4.1 Proposed High-Sensitivity Fully Passive Wake-UpRadioIn power-limited consumer wireless devices such as biomedical implants, wirelesssensor networks, wearable components, and Internet of things, energy saving isa critical design task. These devices are usually battery operated and have a radiotransceiver that is typically their most power hungry block. Wake-up radio schemescan be used to achieve a reasonable balance among energy consumption, range,data receiving capabilities and response time.4.1.1 Overview of Wake-up Radio SchemeWireless sensor networks (WSN) have been recognized as an enabling technologyfor a large variety of applications, including smart homes and cities, agriculture,transportation, health and fitness, entertainment, and structural health monitoring[90]. Strict energy constraints of battery-powered wireless sensor nodesnecessitate energy-aware design at both software and hardware solutions.Reducing the RF transceiver power consumption of the WSN sensor nodes is ofparamount importance, as the RF transceiver is one of the most power-hungrycomponents of the WSN node [91].Optimizing the power consumption of the wireless transceiver not onlydecreases the overall power consumption of the overall WSN system, but alsoprovides opportunities to add more functionalities. In addition, since the batterysize is typically an important portion of the overall node size, low-power circuitscould enable smaller batteries and thus lead to further miniaturization required bymany consumer applications such as wearable devices (smart watches andglasses), body area networks, and implantable devices [92].To reduce the power consumption of the RF transceiver, several techniqueshave been proposed ([91]-[112]). All these techniques are trying to reduce oreliminate the power due to the idle listening of the transceiver. The idle state is124when the RF transceiver is monitoring the communication channel for anincoming message. Unfortunately, this monitoring can only happen if the radio ison and it is listening to the channel. The idle listening state consumes significantpower [91]. Thus, significant efforts have been paid to alleviate this energy waste.A common approach to reduce such idle-state energy is to use duty cycling.This technique consists of switching from listening mode to sleep mode to furtherminimize the transceiver power consumption [91, 93, 100]. However, despite thepower reduction that this approach offers, it can limit the response time and agilityof the nodes as the radios could be off (or in the sleep mode) for a relatively largeportion of time. To exchange messages between two nodes, the receiver node mustbe awake when the sender initiates the communication. Thus, the receiver andthe transmitter node radios need to be synchronized. Synchronization approachescan be classified into three main categories: synchronous, pseudo-asynchronous,or pure asynchronous communication schemes [94, 98, 101]. Duty cycling is ingeneral a synchronous scheme, where the radio is woken up for a fixed or adaptiveperiod of time to listen to any relevant incoming messages.From a power consumption perspective, the asynchronous schemes are amongthe most efficient approaches, and an efficient realization of asynchronouscommunication is to use a wake-up radio receiver [113, 114]. Such a device iscoupled with the main radio transceiver having the role of listening continuouslyto the transmission medium and waking up the main transceiver only when anincoming message is detected. Typically, the WUR consumes much less powerthan the main radio transceiver and thus it facilitates a significant power saving.An ultra-low-power realization of the WUR receiver can be achieved by reducingor eliminating the idle listening time [96].There are a number of features that a WUR device has to support to improve itseffectiveness. First, the power consumption of the WUR has to ideally be ordersof magnitude lower than that of the main transceiver in the receiving mode. Otherimportant features include high sensitivity, robustness to interferers, selectivity,and latency. Usually, sensitivity is the most sought after optimization goal with theultimate aim to match the sensitivity of the main transceiver but at a much lowerpower. The sensitivity is directly related to the communication range: the higherthe sensitivity (measured as the capability to sense the weakest signal in dBm), the125longer the range. However, improving the receiver sensitivity is typically translatedto increased power consumption.In this work, a fully passive low-cost wake-up receiver is presented that takesinto account the abovementioned constraints and specifications. Specifically, thecontributions of this work are as follows: The design and implementation of awake-up radio which is fully passive. The WUR is capable to demodulate OOKmessages and at the same time harvest energy to supply the rest of the wake upcircuits. Furthermore, simulation and experimental validation of the proposedapproach, in terms of power, sensitivity, and data rate are presented.4.1.2 Related WorkResearch activities on the use of WUR in wireless sensor networks to reduce powerconsumption have been prolific in recent years. WUR systems can be classifiedinto three main categories: fully passive, semi-passive (or semi-active), and fullyactive circuits. The first group does not require an explicit power source as thecircuit harvests energy from the environment (e.g., from the incident RF power).RF power harvesting circuits are typically realized using charge pump, Schottkydiodes, and/or use CMOS technology. These circuits usually have a short range ofcommunication. The communication range can be extended to a few tens of metersby using higher transmission power, or where applicable a larger antenna. Thus,they are more suitable for short-range applications and those that do not require anyaddressing mechanism. For example, they are used in biomedical implants, bodyarea networks, near field communication and RFID. A major sub-block of a fullypassive WUR is a passive rectifier with interrupt, e.g., [2, 95, 103–105]. Althoughthe zero power consumption feature is attractive, in this work, we also focus onimproving the range of communication.Among the remaining two categories, namely, semi-active and fully activewake-up receivers, the semi-active approach is more commonly used. In thisapproach, only a minimal number of the receiver components are supplied by anexplicit power source. Popular approaches for realisation of such circuits includeusing an envelope detector or ad-hoc ICs for the RF front-end and then using acomparator to generate an interrupt. Similar architectures for ultra-low-power126WURs for WSN devices are proposed to reduce the sensor node listeningactivities, and thus drastically decrease the overall network power consumption[106–109]. All these solutions use Schottky diodes for envelope detectors and acomparator. Also, these solutions use multi-stage rectifiers rather than one stage.For example, an elegant solution which consumes only 89 nW uses a CMOScustom rectifier and a comparator and achieves a sensitivity of − 41 dBm [110].Fully active solutions use active components both for the rectifier and theinterrupt generator. For instance, a solution with a rectifier, wideband amplifierand the wake up signal recognition achieves a sensitivity of − 47.2 dBm [110],however, similar to other fully active solutions, the power consumption is ratherhigh (6 µW). As another example, an architecture which uses a low noiseamplifier (LNA) in a fully-active solution achieves a sensitivity of − 89 dBm[112]. The use of a LNA allows such a high sensitivity, however, at the cost of ahigh power consumption of few mW, which may offset the benefits of WURs.A thorough survey of various wake-up schemes and their advantages over thewake-on (duty cycling) schemes is presented by Jelicic et al. [94]. It is shown thatthe WUR that does not support addressing [108], has an advantage over the otherschemes due to its very low power consumption and low latency. However, anaddressing mechanism is required to reduce the power consumption duringnetwork formation, and if the wake-up receiver can receive and processcommands, the MAC data communication protocol can be optimized for lowpower consumption. There are two methods for implementing the addressingmechanism: a) custom circuit for addressing/address comparison [112] and b)using a generic microcontroller unit (MCU) [109]. The addressing methodologywill have implications on the overall power budget and will influence theselectivity of the system. This emphasizes the importance of the capability ofreceiving data, which is considered in our proposed approach.The system proposed in this work extends the state-of-the-art with respect topower consumption and data receiving capability. The design and implementationof a fully passive wake-up radio comprised of a CMOS rectifier and a comparatoris presented which generates interrupt from a demodulated OOK signal which canbe used for addressing.1274.1.3 Wake-Up Radio ConceptTo communicate between two wireless nodes, the receiver node must be awakewhen the sender initiates the communication, a scheme which is referred as arendezvous [113]. The receiver remaining awake even if it is not receiving anydata is one of the main consumers of the power in a wireless radio communicationsystem. This is why research efforts have been focused on reducing or eliminatingthe power consumption of idle listening via a number of novel hardware (e.g.,WUR), software (e.g., MAC and routing algorithms) and duty cycle optimizationapproaches [97, 98].There are three main classes of rendezvous schemes:1. Pure synchronous: In this scheme, the node clocks are pre-synchronized suchthat the wake-up time of each node is known in advance. This scheme requiresrecurrent time synchronization that consumes considerable energy. Moreover, thenodes wake up even if there is no packet to transmit or receive, causing idlelistening or overhearing.2. Pseudo-asynchronous (or cycled receiver): In this approach, source nodeswake up and emit a preamble signal that indicates the intention of the datatransmission. The preamble time has to be set long enough to coincide with thewake-up schedule of the destination node (i.e., longer than its sleep time). In thisscheme, time synchronization is not required, but nodes follow a duty cycle andconsume considerable energy for preamble signalling.3. Pure asynchronous: In this class, the sensor nodes are in deep sleep mode andcan be woken up by their neighbours on demand with low-power wake-upreceivers. Whenever a node intends to send a packet, it first wakes up thedestination node with a wake-up message and then sends the packet. Therefore,wake-up receivers are a solution to the redundant energy consumption caused byrendezvous.This work is focused on the pure asynchronous typology and itsimplementation by using a separate wake-up receiver to monitor thecommunication channel continuously, while the main radio is kept in the sleepmode during the times that it is not needed as schematically shown in Figure 4.1.128M ain R ad io R eceiver O N / O F FI nterruptWSN nodeWake upMain TX signalMain Radio Receiver (Pmain)Wake up Receiver (Pwu)Power consumptionC ontrol l ertim eW ake- Up  R ad io R eceiver W ake- p  R ad i  R eceiver Figure 4.1: Generic block diagram of a wireless node with a separate wakeup radio receiver [2].Sou rceD estinationD estinationDataW ak e- up  sig nalA C K A C KFigure 4.2: Asynchronous communication scheme using a wake up radio.When a node wants to communicate, it sends a wake-up signal which isdetected from the WUR to allow the central processing unit (CPU) to wake up themain radio to start the communication as shown in Figure 4.2.The wake up message can contain, for example, the address of the destinationnode to wake up only the desired neighbour. This is an optional feature thatdepends on the design or the application requirements. The most importantrequirement of the wake-up radio is to have a low power consumption, usually insub-µW or preferably few nano-watt range. Such low-power consumption allowsthe wake-up receiver to be continuously on, listening for the wake up signal whilethe main radio is switched off, achieving an overall power saving. Anotherimportant requirement of the WUR is its sensitivity which is typically measuredin dBm. A more sensitive device is able to receive weaker signals, which means alonger transmission range can be supported. To cover most communication ranges129that are applicable in WSNs and RFID tags, a sensitivity of better than − 20 dBmis desired. It is important to improve the sensitivity without increasing the powerconsumption of the receiver which is one of the main challenges in designingWURs. The WUR can use the same antenna, or use a different antenna. Thisdepends on the frequency and the modulation used by the main radio transceiver.If the main transceiver is operating at the same frequency band as the WUR and itsupports the WUR modulation format, then a single antenna can be used.The design of the wake-up radio requires meticulous consideration of designissues in RF, analogue electronics, and digital and system design to carefullyevaluate the following trade-offs:• Wake-up range vs. energy consumption.• Wake-up range vs. delay.• Same-band vs. different-band wake-up radio.• Addressing or without addressing.As discussed in [95] which is one of the pioneering works on application ofthe wake-up radio concept in wireless sensor networks, the following design goalsshould be targeted for WURs:• Low power consumption.• High sensitivity.• Resistance to interference.• Fast wake-up.The following subsections present design considerations of the proposed wake-up receiver which takes into account the above mentioned trade-offs and goals anda proof-of-concept implementation of the proposed wake-up receiver that confirmsthe performance of the proposed approach.130R ecti fi er out n-1 out nC QFGC QFGCQFGCQFGRL a r g eRL a r g e R L a r g eRL a r g eR ec t if r R ef erenc e G enerat or+-V D DR efR efVDD~GNDM at c h ing N et w orkW ak e- u p mes s age( O O K ) V D D W ak e- u p int erru ptC ompinFigure 4.3: Block diagram of the proposed WUR front-end [2].4.1.4 The Proposed Wake-Up Radio ArchitectureAs mentioned in Section 4.1.3, the WUR is expected to consume a negligiblepower compared to the main receiver, in particular, in the context of WSN nodes.The WUR is generally a very simple radio as it is primarily optimized for powerefficiency rather than high data rate and spectral efficiency (which are expectedfrom the main transceiver). As shown in Figure 4.3, a WUR front-end consists ofan antenna (usually shared with the main transceiver), matching network, voltagemultiplier (rectifier) and data slicer (comparator and the associated referencegenerator). Excluding the baseband processing circuitry and for a passive rectifier,the power consumption of the WUR front-end is limited to the power drawn fromthe main energy source (e.g., a battery) by the comparator and the referencegenerator.Although owing to the relaxed performance requirements of the WUR, thispower consumption is small, it should be accounted for in the overall power budgetof the node as the WUR needs to be active all the time listening to the channel.Accordingly, a WUR scheme that does not load the node battery and extracts itsenergy from the wake-up signal itself is highly desired.For this purpose, an RF to-DC converter (rectifier) is used to produce theenvelope of the OOK signal (wake-up message) and at the same time, efficientlyconvert the RF carrier to a DC voltage to supply the comparator and the referencegenerator used in the WUR system. Besides ultra-low-power consumption, high131sensitivity (long communication range) is another desirable feature of a WUR.For electromagnetic coupling, the received power at the WUR antenna is a strongfunction of the communication distance (i.e., the distance between the transmitterand the receiver) and drops rapidly with the distance as expressed by Friisequation (i.e., Equation 1.2 provided in Section 1.3 and repeated here in thecontext of WUR):PWUR = EIRPTX ·Gant ·PCErec ·(λ4pid)2(4.1)where PWUR is the required received power for the proper operation of the WUR,EIRPTX is the isotropic power radiated by the transmitter, Gant is the antenna gain,PCErec is the power conversion efficiency of the rectifier, λ is the wavelength ofthe transmitted RF signal, and d is the communication distance. Typically, theseparameters are dictated by the application and geometry requirements, and thus toincrease the operation distance for a fixed PWUR, usually the only practical choiceis to maximize PCErec.For a fixed WUR antenna impedance (typically 50 Ω) and a reasonablecommunication distance (in the context of WSN), the induced voltage at the inputof the rectifier (i.e., WUR antenna output) is normally too small to allow anefficient rectification. Therefore, in order to guarantee the proper operation of therectifier and accordingly the entire WUR front-end, a mechanism is required toenhance the efficiency of the rectifier for small input levels. It should be noted thatfor a low-cost standard CMOS implementation which is greatly desired forwireless sensor nodes, the use of low turn-on voltage Schottky diodes to serve asthe rectifier switches is not desired as they do not lend themselves to monolithicimplementation. For the proof-of-concept experimental prototype in this work, athree stage differential-drive rectifier optimized for small input levels at 868 MHzinput frequency is designed and implemented as shown in Figure 4.4. Note that aQFG-boosted version of this rectifier (refer to Section 3.4) is used for simulationpurposes.132MN MPMN MPGND DC1MN MPMN MPDC2MN M PMN M PoutFigure 4.4: Schematic diagram of the three-stage differential rectifier.5 (V)  5 (V)  5 10 15 20 25−303time (µs)Voltage (mV)  WUVDDInputRefCompin868 MHz100 kbpsFigure 4.5: Transient simulation of wake-up radio front-end [2].4.1.5 Simulation Results1For simulations, a prototype WUR front-end is designed and simulated in 0.13 µmCMOS and operates at 868 MHz carrier frequency and 100 kbps data rate. Athree-stage QFG biased differential rectifier receives −33 dBm (0.5 µW) from theantenna and delivers 0.25 µW DC power to drive the comparator and referencegenerator. As shown in Figure 4.5, for a 3 mV OOK signal, the rectifier generates∼800 mV DC voltage. A fraction of this DC voltage, taken from the output ofthe second stage of the rectifier (namely Compin in Figure 4.3) is compared withthe generated ∼300 mV reference. The comparator resolves within 5 µs and thusallows for a 100 kbps data rate.1The material presented in this subsection is based on [2].133300 μm150 μmFigure 4.6: Micrograph of the three-stage rectifier.Printed Circuit BoardRectifierCQFP packageGNDRefCompinVDDWUGNDGNDAgilent 83732BVinAgilent DSO81304AInfiniiMax 1169ATektronix DPO 4054VDDOOKWUinterruptcomparator100 kΩ 20 MΩ 20 MΩ 50 Ω 50 Ω attenuatorattenuatorbalunTek P6139AFigure 4.7: Block diagram of the measurement setup.4.1.6 Experimental ResultsFor the proof-of-concept prototype, A three-stage differential-drive rectifier isdesigned and implemented in a 0.13 µm standard CMOS process. The entirerectifier occupies an area of 300 µm × 150 µm. The micrograph of thethree-stage rectifier is shown in Figure 4.6. An external ultra-low-powercomparator is used to detect the output of the rectifier [115]. The measurementsetup is schematically shown in Figure 4.7.A balun generates differential RF signals from a single-ended input andattenuators are used to match the output load of the balun. The rectifier drives a134Figure 4.8: The rectifier output at 10kb/s data rate for a − 21 dBm inputpower.100 kΩ load that mimics the load of system. The input to the external comparatorCompin (see Figure 4.3) is generated by a resistive divider. The reference voltageof the comparator is applied externally. Note that in a full on-chip design, thiscomparator input and the reference could be supplied by the output of anintermediate stage of the rectifier and a bandgap reference generator, respectively.For a − 21 dBm input power at 10 kb/s OOK data rate, Figure 4.8 shows theoutput of the rectifier for a 100 kΩ load. As shown in the figure, for a typically lowdata rate of 10 kb/s, the output of the rectifier resembles the envelope of the inputOOK signal and therefore, could be directly applied to the succeeding base-bandprocessing unit.For a similar setup, the output of the rectifier is shown in Figure 4.9 for a50 kb/s and 100 kb/s data rates. As shown in the figures, the output of the rectifiertriggers at the appropriate rate to resemble the envelope of the detected data. Notethat the output of the rectifier drives the 8 pF input capacitance of the test probe,which in turn affects the rising and falling times of the waveform.Note that in this measurement setup, the input of the rectifier is not perfectlymatched to the output of the RF signal generator. The input power is estimated byde-embedding the effect of reflection using the expression [78]:Pin = Psig×|1−S211,diff| (4.2)135(a)(b)Figure 4.9: The rectifier output at: (a) 50 kb/s and (b) 100 kb/s for a− 21 dBm input power.where, Psig is the power delivered by the signal generator, Pin is the power receivedat the input of the rectifier and S11 is th reflection coefficient of the power deliveryline.Figure 4.10 shows the output of the entire WUR system (WUinterrupt inFigure 4.7) for 10 kb/s, 50 kb/s and 100 kb/s OOK inputs. The input power is setto − 20 dBm. As shown in the figure, the comparator output (WUinterrupt) is agood representation of the OOK signal envelope. The ultra-low-power comparator136Table 4.1: Performance summary of the proposed fully-passive WUR.frequency data rate power sensitivity Implementation[116] 2.4 GHz 50 kbps 20 µW −50 dBm Simulation[108] 433 MHz 5.5 kbps 270 nW −51 dBm DiscreteThis work 868 MHz 100 kbps 0 −33 dBm SimulationThis work 868 MHz 100 kbps 0 −21 dBm Measurementoperates at a minimum supply voltage of 0.68 V. The average power consumptionof the comparator at 0.68 V supply is measured to be 77 nW, 112 nW and 240 nWfor 10 kb/s, 50 kb/s and 100 kb/s input rates, respectively.For a load of 100 kΩ, the minimum input power for which the output of therectifier is a valid detectable representation of the input is measured to be− 26 dBm.Figure 4.11 shows the rectifier output for − 26 dBm input power. As shown inthe figure, the output voltage of the rectifier is insufficient to drive the comparator(and potentially the succeeding baseband processing unit).Table 4.1 provides a performance summary of the proposed WUR andcomparison with the state-of-the-art designs in the similar range of operationfrequency and data-rate.4.2 Feasibility Study of Backscattering ForTelemonitoring2Wake-up radio scheme as a power efficient approach in the receive mode wasdiscussed in Section 4.1. In this section, backscattering method as a powerefficient transmission scheme is studied. As discussed in Chapter 1,backscattering is commonly used for passive RFID tags at short communicationdistances. This scheme is specifically beneficial for telemonitoring systems inbiomedical implants. In this work, the use of backscattering for telemonitoring ofin-stent restenosis is investigated. Details of this study are provided in [8].2The material presented in this section is based on [8].137(a)(b)(c)Figure 4.10: Comparator output (WURinterrupt) at (a) 10 kb/s, (b) 50 kb/s and(c) 100 kb/s.138Figure 4.11: Rectifier output for an input power of − 26 dBm at 100 kb/sinput data rate.4.2.1 Overviwew of backscattering scheme for telemonitoringDifferent techniques have been employed to wirelessly transmit power tobiomedical implants. Inductive coupling (near field) [117–119], electromagneticcoupling (far field) [120, 121], and ultrasonic propagation [122] are among themost common means of wireless power delivery in the context of biomedicalimplants. The designs presented in [117–121] use active transmitters and thosepresented in [123–125] employ electromagnetic back-scattering approach and usea passive transmitter (relaxation oscillator, LC filter) in order to send the sensorydata to the reader. The active approach requires significantly higher power whichis not desirable in the context of wirelessly powered biomedical implants.The focus of this work is passive backscattering telemonitoring scheme.4.2.2 Telemonitoring of In-Stent RestenosisBackscattering is a communication method in which the transmitted signal(incident power) is reflected back to the direction of the transmitter, thusalleviating the need for a dedicated transmitter [126, 127]. In the context oftelemonitoring systems for biomedical implants ( more specifically in-stent139RF ch amb erPul seG en.D irectionalcoup l erS p ectrum anal yz erG round  beeff d ataR LoadAntenna stentS ensory d ata rep resentationf 1 f 0Figure 4.12: Schematic diagram of the test setup for backscatteringfeasibility study.restenosis monitoring which is the focus of this work), the operation procedure isas follows: An external (and typically high power) reader transmits an RF carriertowards the implant‘s antenna. The transmitted radio waves penetrate the patient’sbody tissue and are harvested by the power harvesting unit of the implant toactivate the tag IC. The implant’s circuitry once activated, will process thecaptured sensory data (e.g., blood pressure captured through capacitive sensors).The processed data is then transmitted to the reader (interrogator) throughbackscattering method. The transmission of data through this method is achievedby modulating the impedance of the implants antenna. One way of modulating theimpedance is by opening and closing the two terminals of the antenna by a switchwhich is controlled (turned on/off) by the data to be transmitted. The modulatedimpedance of the antenna is monitored and observed at the reader side, thus thedata is detected. Backscattering method can be used with different modulationschemes such as amplitude shift keying, frequency shift keying and phase shiftkeying [126].In this study, an antenna stent is used to serve as the implants antenna. A stentis a mesh tube device inserted in the blood passage to prevent flow constriction. Invirtue of such structure, this device can be modified and used as an inductive coiland thus can serve as an antenna in the communication link [128].140Figure 4.13: Backscattering-based measurement setup [8].4.2.3 Experimental ResultsTo study the feasibility of backscattering approach for biomedical implants, a testsetup is designed. The two terminals of the antenna (stent) are connected to a loadresistance. A square-wave 100 kHz signal (to resemble the sensory data) drives ananalog switch. The switch while closed, shorts the two terminals of the stentthrough bypassing the load resistance and when the switch is open, the twoterminals of the stent are connected to the load. Therefore, the stent impedance ismodulated with respect to the square-wave signal. The load resistance emulatesthe power (current) consumption of the implant in a practical scenario. RF carrieris transmitted to the antenna stent at 900 MHz. At the reader side, in order todetect the backscattered signal, a bidirectional coupler is used to isolate thereceived signal (backscattered by the antenna stent) and the transmitted signal (RFcarrier). A spectrum analyzer is used to detect the backscattered signal in order toretrieve the data. The sensory data modulates the switching frequency in asubcarrier modulation fashion [9]. Note that antenna stent’s impedance variation1410.1 1 10 100 1000−95−90−85−80−75−70−65Load resistance RL (kΩ)Backscattered power (dBm)  Pin=0.0 dBmPin=−10.0 dBmFigure 4.14: Measured backscattered power level versus different load valuesand input powers [8].also modulates the amplitude of the backscattered signal, however, detection ofsuch ASK signal requires a different receiver at the reader side (rather than anspectrum analyzer). Ground beef (applied in different thicknesses) is placedbetween the two antennas (reader and the implant) to mimic the real environment.The reader antenna, antenna stent and the analog switch are placed inside an RFshielded enclosure. Figure 4.12 ([8]) schematically shows the feasibility studysetup while Figure 4.13 ([8]) shows the in-vitro experimental setup used formeasurements.The backscattered power level for different load values (RLoad in Figure 4.12)and for two transmitted powers of 0 dBm and − 10 dBm are shown in Figure 4.13[8]. Although the backscattered level is small, it is simply detectable by a typicalreader. Also as demonstrated in Figure 4.13, a higher backscattered power level isreceived at the reader side, for larger load resistance values (smaller currentconsumption). This observation implies that a more power efficient implantcircuitry leads to a more reliable backscattering communication. More details ofthis study are presented in [8].1424.3 ConclusionIn this chapter, a fully-passive wake-up radio capable of harvesting its entirerequired energy from the wake-up message is presented. The zero-powerrequirement of the proposed WUR can be exploited to prolong the lifetime of theenergy source (battery) in wireless sensor nodes and active RFID tags. Theproposed WUR is also useful in semi-passive and passive RFID tags by separatingthe data detection and power harvesting processes. Note that the settlingrequirements of the high-efficiency rectifier used for the WUR is different fromthat of the power harvesting unit. More specifically, the WUR rectifier performsas an OOK detector and its settling time has to comply with the designated datarate. However, the settling time of the rectifier used for power harvesting onlyneeds to be compatible with power on/off cycles of the reader which is typicallymuch slower than the data rate.A high-efficiency rectifier for use in the WUR is designed and fabricated ina 0.13 µm CMOS technology. A discrete comparator and an external referencevoltage are employed to complete the WUR architecture. The performance of theproposed WUR is verified through simulation and measurement results.Also, the feasibility of backscattering technique in the context of biomedicalimplants is investigated. The impedance of an antenna stent is modulated byexternally generated pulses (to emulate the sensory data) in an in-vitromeasurement setup [8]. The measurement results verify the feasibility ofbackscattering technique to establish a communication between the implant’santenna (as the passive RFID tag or sensor node) and the reader, in biomedicalapplications.143Chapter 5Power Efficient Clock GeneratorCircuitAs discussed in Chapter 1, the clock generator is an integral part most passive RFIDtags and simple oscillators typically constitute the core of such clock generatorcircuits. Circuit-level design techniques to reduce the power consumption of theoscillators used in passive RFID tags is presented in this chapter.5.1 Proposed Ultra-Low-Power Voltage-Controlled RingOscillatorThe block diagram of a generic passive RFID tag (transponder) with an emphasison the task of the clock generator (oscillator) is shown in Figure 5.1. The analogfront-end is responsible for power harvesting and signal modulation/demodulationwhile the back-end processing unit controls data coding/decoding andmemory/sensor access. As shown in the figure, a clock generator is an integralpart of the processing unit. The EPCglobal™ Gen 2 mandates a minimum clockfrequency of 1.92 MHz to guarantee a high-performance data transfer [129],[130]. To generate the required clock, a viable solution is to extract it from theincoming RF signal. However, such an approach requires a chain of dividers toconvert the UHF carrier (860 MHz to 960 MHz) to the required baseband clockfrequency [131]. The complexity and power overhead imposed by the dividers144Baseb and Processing U nitClock G en.  (O S C)DemodulatorM odulatorPower H arv esting U nitCoder/DecoderControllerMemorySensor InterfaceA nalog Front- E ndAntennaPassiv e RFI D T agFigure 5.1: Block diagram of a generic passive RFID tag.typically rules out this scheme in passive RFID tags, suggesting incorporation of alocal (voltage-controlled) oscillator.5.1.1 Overview of Low-Power Oscillators for Passive RFID tagsPassive LC oscillators and ring oscillator (RO)s are the two main categories ofoscillators in CMOS technology. Unfortunately, the inductor as an essentialcomponent of LC oscillators does not simply lend itself to high-level ofintegration at UHF frequencies. LC oscillators also suffer from a limitedfrequency tuning range specifically in low-voltage applications where they have anarrow frequency tuning range [132]. In contrast, ring oscillators are notinherently dependent upon passive components (e.g., inductors) which is greatlydesirable in the context of passive RFID tag design. Apart from silicon areaconsiderations, low power consumption is also of paramount importance inpassive tags considering their tight power budget. The local oscillator is a majorcontributor to the overall power consumption in passive tags. It is worthmentioning that passive UHF tags use backscattering method for thecommunication from the tag to the reader and theoretically do not allocate powerfor data transmission.Extensive research has been conducted to address the power consumption ofthe ROs at a circuit-level perspective. Farzeen et al. [133], biases the delay cells145of a RO in the weak inversion region. The proposed oscillator achieves a powerconsumption of 24 nW for a 5.12 MHz oscillation frequency with 0.3 V powersupply. In a work presented by Park et al. [134], a supply voltage of 0.3 V allowsMOS transistors in the current-starved inverters to operate in subthreshold, near-threshold and above threshold regions. The proposed design consumes 95 nW forthe entire RO-based temperature sensor while oscillating at 2 MHz to 8 MHz. Cileket al. [131] controls the DC current of the current-starved inverters to minimizethe power consumption. The proposed RO of [131] oscillates at 1.28 MHz andconsumes 440 nW from a 0.9 V supply.In this work, the gate-drive voltage of CMOS transistors inpseudo-differential (PD) delay cells are boosted through the use of QFGarchitecture [85]. The boosted gate-drive voltages facilitate oscillation withsupply voltages as low as 90 mV which accordingly results in a low powerconsumption. The QFG technique practically imposes minimal area overhead andprovides a secondary control mechanism over oscillation frequency.5.1.2 Low-Power Ring Oscillator architectureAs mentioned in Section 5.1.1, low power consumption, small area, and tunabilityare major performance requirements of the local oscillator in the context of UHFpassive RFID applications. Ring oscillators are a suitable candidate for suchapplications. The delay cells in a ring oscillator are implemented as eithersingle-ended or differential inverting amplifiers [132]. While the single-endedring-oscillator (SRO) requires an odd number of stages (minimum of three stages),its differential counterpart could be implemented with lower number of stages(minimum of two stages accommodating four current branches). The differentialring oscillator provides a better common-mode noise and supply rejection ratioand is capable of producing quadrature output signals. The power consumption ofa ring oscillator is the summation of the static (PS) and dynamic (PD) power of theinverting amplifiers and is given by [135]:Ptot = PS +PD= Ileak ·VDD +N · f ·CL ·V2DD(5.1)146PD1V B n V B nV B pV B pO S C+ 1O S C- 1 O S C- 2OSC+ 1OSC- 1OSC+ 2OSC- 2VDD VDDVnVpPD 2O S C+ 2VnV pFigure 5.2: Schematic diagram of the proposed two-stage ring oscillator.where Ileak is the leakage current of the inverting amplifier, VDD is the supplyvoltage, N is the number of current branches, f is the frequency of oscillation andCL is the capacitance of the output nodes. As suggested by Equation 5.1, for agiven frequency of operation, the supply voltage, VDD, and the number of stages,N, have to be minimized to reduce the power consumption.In the proposed RO, a two-stage PD QFG architecture is employed. The PDarchitecture saves the voltage headroom for the tail transistor and allowsoscillation with the minimum number of stages. To meet the Barkhausen criterion[136], each PD stage utilizes a local positive feedback in the form of twocross-coupled PMOS devices. The schematic diagram of the proposedQFG-biased PDRO is shown in Figure 5.2 where the gate-drive voltages oftransistors are boosted through floating voltage sources. As shown in the figure,the floating voltage sources shift the AC input to the gates of transistors in apositive and negative direction for the PMOS and NMOS transistors, respectively.The boosted gate-drive voltages partially compensate the threshold voltage oftransistors, facilitating oscillation with supply voltages smaller than thesummation of the threshold voltages of the stacked transistors in the PDarchitecture. The floating voltage sources, VBp,n, can be efficiently implementedthrough the use of QFG architecture [85]. The QFG biasing scheme is shown inFigure 5.3a where the AC input (OSC) is coupled to the gate of the transistorthrough the capacitor CQFG while the large resistor Rlarge weakly connects the gateto the desired DC bias voltages (Vn,p). As shown in Figure 5.3b, the effectivevalue of the floating voltage sources are given by:VBn,p = Vn,p−VDCin (5.2)147V Bn =    V n -  DCinVB nVB pVnVpRlargeRlargeC Q FGCQ FGV Bp =  V p -  DCinDCinDCinV B nV B p VpVnRlargeRlargeCQ FGC Q FGV G pVG nO S CO S C(a)DCinV nV pDCinV nV pVG pVG nV BpV BnOSC(b)Figure 5.3: Implementation of the floating voltage sources through QFGarchitecture. (a) Schematic diagram of circuit-level implementation, (b)Schematic diagram of the boosted waveforms.where VDCin is the average voltage of the AC input, OSC, and is approximatelyequal to VDD/2 for a rail-to-rail oscillator output. Boosting the gate-sourcevoltages of the transistors as shown in Figure 5.3a virtually enhances the effectivesupply voltage by: VBn+|VBp| = Vn−Vp, which allows oscillation with smallerVDD. Note that Vp < VDCin and accordingly, VBp is a negative voltage offset (seeFigure 5.3a).5.1.3 Design ConsiderationsAs shown in Figure 5.3a, to save silicon area, the large resistor Rlarge can beimplemented by the large leakage resistance of the reverse biased p-n junction ofa PMOS in cut-off region [85]. The value of this resistor is not that critical as longas it is relatively large. The implementation of the coupling capacitor, CQFG,requires further attention during the design process. The value of CQFG affects theperformance of the RO through two separate mechanisms as follows:1. Coupling the AC signal, VOSC to the gate terminals through CQFG forms a1480.00006 0.00015100150200250Voltage (mV)t0 10 20 30 40 50 60 70 80 90 10050100150time (µS)Voltage (mV)VGnOSCVn = VDDf1,OSC = 4 MHz f2,OSC = 6.1 MHzFigure 5.4: Transient settling behavior of the proposed QFG-biased VCRO.capacitive divider at the gate of transistors and slightly attenuates the amplitude ofthe AC component. The QFG-coupled gate voltages VGn,p are given by (seeFigure 5.3a):VGn,p = VOSC×CQFGCQFG +CGn,p(5.3)where CGn,p is the total parasitic capacitance seen at the gate of NMOS andPMOS transistors. Equation 5.3 suggests the use of a large coupling capacitor inorder to fully exploit the available gate-drive voltage. However, aside from areaconsiderations, an excessively large CQFG increases the delay of the PD cells andaccordingly reduces the oscillation frequency. Moreover, as shown inEquation 5.1, the large output capacitance CL, increases the total powerconsumption of the oscillator. Therefore, for a fixed set of design parameters,there is an optimum range of CQFG which results in a good performance in termsof oscillation frequency, silicon area, and power consumption.2. The QFG architecture of Figure 5.3a forms a low-pass RC filter along the pathfrom the bias node (Vn,p) to the gate of transistors. Thus, the DC value of the gateexperiences a delay before fully settling to the desired value Vn,p. The settlingbehaviour is of particular importance if the RO is to be used as the VCO in a PLL.The time constant associated to this RC filter is given by:149OSC+1OSC-1VDD VDDVnVnVpVpOSC+2OSC-2VDD VDDVnVnV pVpO S C+ 1 O S C- 1O S C+ 2O S C- 2VCMVCMO S C- 1 O S C+ 1VCMO S C- 2VCMO S C+ 2VDD-H VDD-HVDD-HVDD-HRO +RO -V b tDelay  cell -  1 Delay  cell -  2 Q uadrature- to- dif f erential low- to- h igh  v oltage conv erterFigure 5.5: Schematic diagram of the proposed VCRO and voltage levelconverter.τ = Rlarge× (CQFG +CGn,p) (5.4)Equation 5.4 further highlights the significance of the CQFG value. In theproposed QFG-biased RO, for a nominal frequency of 4 MHz, the associated timeconstant is 12 µs which yields to Tsettle ≈50 µs. The 50 µs settling timecorresponds to 200 cycles of the oscillator output at 4 MHz which satisfies thesettling requirements of a VCO in PLL applications. As shown in Figure 5.3a, tosave area, the coupling capacitors are implemented with MOSCAP devices.To fully exploit the voltage levels already available in the circuit for the boostingpurpose, Vn and Vp are connected to VDD and ground, respectively, hence allowinga lower supply voltage value (see Figure 5.3a). Note that in view of Equation 5.2and the discussion that followed, such a biasing scheme enhances the effectivesupply voltage by VDD (i.e., Vn−Vp = VDD−0). Therefore, the supply voltageand accordingly Vn are used as the VCO control voltage while Vp is kept constantat zero. Figure 5.4 shows the transient waveform of VG,n in response to a step signalapplied to the control voltage (VDD=Vn). It is worth mentioning that both Vn andVp could be used as a secondary frequency tuning knob. As discussed earlier, fora fixed VDD, increasing Vn (Vp) virtually increases (decreases) the supply voltageand accordingly could be used to increase (decrease) the oscillation frequency.The circuit-level diagram of the proposed VCRO is shown in Figure 5.5. As15090 100 110 120 130 140 150 1602468supply voltage (mV) frequency (MHz) Vn = VDDVp = 0(a)120 125 130 135 1402. (mV)frequency (MHz)5 10 15 20VDD = 140mVVnVp(b)Figure 5.7: Oscillation frequency of the proposed VCRO. (a) As a functionof VDD, (b) As a function of Vn and Vp .Table 5.1: Performance summary of the proposed low-power voltage-controlled ring-oscillator.Reference [131]a [133]b [137]a [138]a This workcTechnology 0.14 µm 90 nm 0.13 µm 0.13 µm 0.13 µmArchitecture SRO PDRO Relaxation Relaxation PDROFrequency 1.28 MHz 5.12 MHz 5.65 MHz 2.52 MHz 4 MHzSupply 900 mV 300 mV 600 mV 800 mV 140 mVPower 440 nW 24 nW 720 nW 320 nW 3.6 nWa Measurement results. b Simulation results.c Post-layout simulation results.shown in the figure, to interface the output of the VCRO with a succeeding circuitrythat potentially uses a higher supply voltage, a quadrature-to-differential low-to-high voltage converter is proposed. The common-mode voltage of the input devicesin the proposed converter is boosted through the use of QFG technique. The twooutput inverter buffers produce 50% duty-cycle fully differential outputs with avoltage swing of 0 to VDD,H from the low-voltage quadrature inputs. Note that, thecapacitive loading effect of the converter slightly reduces the oscillation frequencyand thus has to be accounted for in the design of the VCRO.151Figure 5.8: Layout view of the proposed VCRO.5.1.4 Post-Layout Simulation ResultsA proof-of-concept prototype of the proposed VCRO is designed and laid out in0.13 µm CMOS technology. For a supply voltage in the range of 90 mV to160 mV, the input and load transistors in the delay cells operate in weak tomoderate inversion regions and are sized to minimize the power consumption.PMOS transistors in cut-off region are used to implement RLarge and MOSCAPdevices are used for CQFG. Figure 5.7a shows the oscillation frequency as afunction of the supply voltage, while Vn is tied to VDD (i.e., Vn = VDD) and Vp isconnected to ground (i.e., Vp = 0). As shown in the figure, an oscillationfrequency (fOSC) of 4 MHz is obtained for a 140 mV supply voltage. fOSC spans arange of 450 kHz to 9.2 MHz for a VDD variation of 90 mV to 160 mV. The powerconsumption of the VCRO for this range extends from 0.24 nW to 9.8 nW, with3.6 nW for the nominal oscillation frequency of 4 MHz. Figure 5.7b shows thefrequency as a function of Vn and Vp. For a fixed VDD of 140mV, increasing Vnfrom 120mV to 140mV increases fOSC from 2.4 MHz to 4 MHz while increasingVp from 0 to 20 mV decreases fOSC from 4 MHz to 2.7 MHz. For a VDDH=0.6 V,the proposed low-to-high voltage converter consumes a power of 320 nW togenerate a rail-to-rail differential clock (RO±) at 4 MHz frequency from the152quadrature inputs (0 mV-to-140 mV swing OSC±1,2) while Vbt=200 mV andVCM=400 mV (see Figure 5.5).The layout view of the proposed VCRO core is shown Figure 5.8. The proposedVCRO occupies an area of 500 µm2 (25 µm×20 µm) while only the first threemetal layers (in a 0.13µm CMOS technology) are used for routing.Table 5.1 provides a performance summary of the proposed VCRO andcompares it with the state-of-the-art VCOs in the similar range of oscillationfrequency.5.2 ConclusionAn ultra-low-power VCRO is presented in this chapter to be used as the core ofthe clock generation circuitry in passive RFID tags. The proposed VCRO relieson QFG architecture to allow a low voltage operation and consequently, lowpower consumption. The VCRO uses MOSCAPs for the QFG structure to savelayout area and is capable of accommodating two frequency control knobsthrough creating a separate access to the gates of the NMOS and PMOStransistors in the PD cells.153Chapter 6Conclusion and Future WorkPassive RFID tags offer several key advantages over their active counterparts andconventional identification systems. The most significant advantages brought bysuch tags could be summarized as low cost, small form factor and maintenance-freeoperation. In virtue of these advantages, passive tags are widely used in numerousapplications and the demand for such identification systems is expected to grow ata rapid pace in the near future.The absence of a dedicated energy source for the passive tags calls forintelligent design techniques to enable the tag’s circuitry to cope with the verytight power budget. Moreover, area efficiency is another crucial criteria to be metby the passive tags circuitry in order to guarantee a low cost implementation ofthe entire system.The focus of this work is on the design of efficient data and power convertercircuits for use in passive RFID applications. Different building blocks of a passiveRFID tag are designed with an emphasis on area and power efficiency mainly at acircuit level perspective.6.1 Low-Power and Area-Efficient SAR ADCAn ultra-low-power and area-efcient SAR ADC is presented in Section 2.2. TheADC achieves a low power performance through using two ultra-low-power unitygain buffers. The area is also significantly reduced by eliminating the need for the154conventional capacitive DAC array. The entire ADC only consumes 290 nW andachieves a FoM of 48 fJ/conversion step which makes it specifically attractive toserve as the core of the sensor interface in sensor-enabled passive RFID tags [6].The proposed SAR ADC presented in Section 2.2 demonstrates a goodperformance in terms of power consumption and area. However, there arepossibilities to enhance its performance by means of some supplementaryamendments summarized as follows:A Buffers Slew Rate and Gain EnhancementPerformance of an ADC is evaluated by means of its FoM as:FoM =P2ENOB · fsample(6.1)where P is the power consumption, ENOB is the effective number of bits andfsample is the sampling frequency. Therefore, for a given power consumption, toimprove the FoM, ENOB ( as a function of the gain of the buffers), and/or fsample,(as a function of the speed of the buffers ) has to increase. Thus, a feasible optionis employing a buffer/amplifier with a higher gain/speed and little extra powerconsumption.B Comparator Offset CancelationTo mitigate FoM degradation as a result of device mismatch in thebuffers/comparator and capacitor mismatch in the DAC, offset/mismatchcancelation mechanisms are required. The effect of the extra power consumptionimposed by offset/mismatch cancelation circuitries on the ADC FoM isovercompensated by the increased ENOB as suggested by Equation 6.1.C Rate-Resolution ScalabilityDue to the varying nature of the input signal, sampling rate and resolutionscalability is highly desired in RFID-based sensor network applications.Scalability allows for further power conservation when the performance and speeddemands are not high. This valuable feature can be achieved in the proposedscheme by means of clock/power-gating and asynchronous bit-decision timing[39].155T ime- to- digital conv erterSensor V ol tage-to- time converter( V T C )A nal og variabl e T ime- mod e variabl e D igital  variabl eT ime- mode analog- to digital conv erterF ast cl ockr esetT ime comparatorcounterFigure 6.1: Schematic diagram of a time-mode ADC.6.2 Wide Input Range voltage-to-Time ConverterA highly-linear wide input range VTC is presented in Section 2.4. VTC is a keybuilding block in time-mode signal processing systems. Time-mode systemstransfer the processing load from analog domain into time/digital domain.Therefore, such systems are very desirable in passive RFID tags due to theirintrinsic low power consumption and ease of integration.Wide input range and high linearity are among the most critical specificationsof a VTC block. In the proposed VTC, high-linearity is achieved throughre-ordering the charge and discharge cycles in conventional current-starved VTCs.also wide input range is obtained through the use of the proposed linearvoltage-to-current converter.The proposed VTC provides a good performance in terms of input range andlinearity and is suitable to operate as the interface for the time-mode signal156V refC s C d ivV inV refco mp ch ar ge V refchargecompI chargeS ample- and- h old /  div ider V oltage to current conv erter I ntegrator /  comparatorC intV inV refV ref  / 2 V ref  / 4 V ref  / 8V DA CVIcontrollerD0 D1 D2 ...V DAC S witch  controlFigure 6.2: Schematic diagram of the current-based SAR ADC.processing system. A time-mode analog-to-digital converter is TMSP systemwhich is of particular interest in the context of passive RFID tags. As a futureresearch track, the other building blocks of such an ADC namely a timecomparator and a high-speed counter can be designed and assembled with theproposed VTC to develop a complete system [21, 49]. The diagram of thetime-mode analog-to-digital converter is schematically shown in Figure 6.1As another future work track, a current-based SAR ADC can be designed usingthe techniques developed in the design of the linear VTC Section 2.4. Such anADC incorporates a sample-and-hold/divider, a linear voltage-to-current converter,an integrator/comparator and the control unit as shown in Figure 6.2. Initially theinput voltage is sampled by the sample-and-hold block. The voltage-to-currentconverter (similar to the one proposed in Section 2.4) produces the appropriatecurrent and charges the integration capacitor, Cint, during the charge phase. Thevoltage on Cs (i.e., Vin) is compared with the reference voltage, Vref, and the MSB(i.e., D0) is resolved. During the next charge cycle, the voltage-to-current converterdriven by the sample-and-hold/divider (which is already charged with Vref in thepreceding comparison cycle) adds/subtracts Vref to/from the voltage on Cs (i.e.,Vin at this point) depending on the previous bit B0. More specifically, If B0= 0,157Vref is added to and if B0= 1, Vref is subtracted from VCint. The resulted voltageis compared with Vref and the next bit is decided. From this point on, the sample-and-hold/divider divides its voltage by two at each comparison cycle to have theappropriate DAC voltage ready for the next charge cycle. In the third charge cycle,Vref/2 is added/subtarcted to/from VCint (depending on the value previous bit) andthe resulted voltage is compared with Vref to resolve the next bit. This procedureis repeated until all the bits are decided.The amplifier operates as a unity-gain buffer during the integration phase(charge cycle) and therefore, stabilizes the inverting input voltage at a value closeto Vref. Such an approach comes with a valuable advantage: the drain voltage ofthe current mirror transistors (Mm1,2 in Figure 2.19) remains constant during thecharge cycle which results in an accurate current copying. The feedback loop isopened during the comparison cycle and the amplifier performs as a comparator,comparing VCint with Vref. Based on the previous bit value, the controller decideswether Cint is to be charged or discharged during each charge cycle and generatesthe appropriate switching signals.The current-based SAR ADC eliminates the need for the bulky capacitive DACand operates with only three capacitors (two for the sample-and-hold/divider andone for integration). To decrease the power consumption, the current levels (in thevoltage-to-current converter) can be chosen arbitrarily small (i.e., as small as otherdesign parameters such as the size of the integration capacitor permit).6.3 Efficiency Enhancement Techniques for RectifiersThree efficiency enhancement techniques for CMOS differential rectifierscompatible with UHF passive RFID applications are presented in Section 3.2,Section 3.3 and Section 3.4. For small input levels, through proper boostingschemes, the gate-drive voltage of switches are biased at a level close to theoptimal value, therefore, higher efficiencies are achieved for smaller input levelswhich in turn facilitate longer communication distance for RFID tags. PCE ofUHF differential rectifiers are analyzed as a function of averageforward-to-reverse current ratio in the switches. Based upon the analysis, boostingtechniques are presented and studied in terms of power and area overhead and158R ectif ierW ir el ess p ow er  h ar vesting  unitO n- chipm atching network R egu l atorA ntenna to the tag’s c ir c u it r yFigure 6.3: Schematic diagram of the wireless power harvesting unit.design guidelines were provided. Post layout simulation results confirm thevalidity of the proposed techniques and high efficiencies were obtained at smallinput voltages.For the proposed switched-rectifier of Section 3.2, two prototype three-stageCMOS RF-to-DC converters for UHF RFID tags are designed and laid out in0.13 µm CMOS technology. Compared to conventional rectiers, both structuresprovide high power conversion efciency and low voltage operation capability. Toenhance the differential rectier PCE, a new switching scheme is proposed thatsimultaneously reduces the effective turn-on voltage and leakage current of switchtransistors. A simple clock generator is used to provide the appropriate clocksignals required for the switching. The proposed scheme is then improved interms of operation voltage range by applying an external voltage booster. Throughthe use of a floating voltage source capable of swapping its terminals, the gate ofcharge transfer switches are dynamically biased to alleviate the drawbacksassociated with static biasing scheme. Note that in start-up phase, both structuresrely on a power source for the purpose of clock and boost generation which can besupplied through an on-board battery in semi-passive tags. In passive RFIDapplication, an auxiliary rectifier cell has to be incorporated in order to supply therequired energy in start-up phase. The auxiliary rectifier can then be switched offwhen the output of the main rectifier reaches the desired value after which themain rectifier can continue its operation in a self-sufficient manner [7].To remedy the requirement for an external power source during the start-upphase, the enhanced efficiency rectifier of Section 3.3 is presented. For thisrectifier, A high PCE for small input voltages is achieved by boosting the gate159voltage of the switching transistors through a chain of auxiliary floating rectiercells. The proposed circuitry has a minimal power overhead and thus is suitablefor passive UHF RFID applications. A prototype three-stage rectier is designed ina 0.13µm standard CMOS technology and post-layout simulation results show thecapability of the proposed scheme in improving the efciency for small inputvoltage levels [4].As a design approach to deliver a high efficiency over a wide range of inputs,a dynamic biasing scheme is proposed in Section 3.4. This extended high-PCErange is obtained by dynamically biasing of the gate of switches through a QFGarchitecture. The dynamic bias voltages are generated by a chain of voltagereference generators. The proposed scheme could also be used to improve theperformance of the rectifier for very small input voltages, i.e., below the thresholdvoltage of transistors. Post-layout simulation results confirm the validity of theapproach. Compared to conventional rectifiers, a proof-of-concept example hasdouble the input range over which the PCE is more than 60% [3].The proposed efficiency enhancement techniques provide a high PCE for smallinput levels and are capable of increasing the communication range. As a futureresearch track, the proposed rectifiers can be assembled with practical antennas,on-chip matching networks and potentially a voltage regulator block to constitutea complete power harvesting unit. The diagram of such a power harvesting unit isschematically shown in Figure 6.36.4 Dual-Band Matching SchemeA rectifier with a dual band matching circuit is a very attractive in the context ofRFID tags. Such a rectifier facilitates energy harvesting at two distinct frequencybands and therefore opens up possibilities for numerous applications. InSection 3.6, through exploiting the techniques developed to enhance the efficiencyof UHF rectifiers, a dual-band matching scheme is implemented to enablewireless power delivery with close to optimum PCE at two different frequencies.The separation between the two frequencies could be adjusted (within the range ofthe input capacitance variations) through proper design of the bias voltage circuit.The proposed matching technique facilitates on-chip matching and operates in a160R ectif ierM ul ti- band match ing  sch emed y nam icm atching networkcontrol l erA ntenna R ef l ectio n  co ef f icien tf 0 f 1 f 2 f 3Figure 6.4: Schematic diagram of the multi-band matching scheme.self-sufficient manner.As a future work, a multi-band matching scheme can be designed toaccommodate all or most of the RFID frequency bands. Since different ISMbands are positioned significantly far away in the frequency spectrum, such anscheme requires a sophisticated dynamic impedance controller. Along withdynamically controlling the input capacitance of the tag (rectifier), designtechniques are required to also modulate the input inductance of the tag (matchingnetwork) to cover the wide dynamic range of input frequencies. The diagram ofsuch a multi-band matching scheme is schematically shown in Figure 6.46.5 Fully Passive Wake-Up RadioWake-up radio scheme provides a significant power saving during the idle receivemode of tag’s operation while the tag’s receiver needs to constantly monitor thechannel for a command signal from the reader. However, a successful realizationof this method is greatly dependent on the power consumption of the wake-upradio. In Section 4.1, a fully passive wake-up radio for RFID tags and wirelesssensor nodes is presented. Using a high-efficiency differential rectifier, the WURfront-end harvests its entire required energy from the wake-up signal withoutloading the main power source of the node. Detection for a − 21 dBm inputsignal at 100 kb/s data rate is achieved at the output of the external ultra-lowpower comparator. The minimum input power for which the rectifier generates a161detectable DC output is measured to be − 26 dBm. The WUR could be optimizedfor different carrier frequencies and data rates. Higher sensitivities could beachieved by further reducing the power consumption of the comparator and thereference generator through a fully integrated implementation and also byincorporating efficiency enhancement techniques for the rectifier [2].As a future work, the proposed fully-passive wake-up radio can be improvedin terms of sensitivity by means of enhancing the efficiency of the rectifier, using adetector (comparator and reference generator) with lower power consumption andincorporating a proper matching network. The implemented WUR can be tested ina field study under different signal transmission scenarios in a real environment.6.6 Study of Backscattering for TelemonitoringBackscattering is a power efficient scheme during the transmit mode of the tag as italleviates the need for a power hungry dedicated transmitter. This scheme is widelyused in passive RFID tags used in short range communication scenarios. To studythe feasibility of backscattering for biomedical implants, a measurement setup tomimic the real environment is designed. The experimental results obtained formthe measurements, confirm the feasibility of backscattering for telemonitoing inthe context of biomedical implants. Details of this study are provided in [8].As a future research, the backscattering scheme for biomedical implants canbe tested in an in-vivo fashion. Also, transmission of real sensory data while usingpractical antenna and a more elaborate impedance modulator can be followed as abeneficial research track.6.7 Low-Power Ring OscillatorClock generation circuitry is an integral part of most passive RFID tags. Likeother building blocks of the tag, clock generator need to perform its task with aminimal power and area overhead. Oscillators form the core of such clockgenerator blocks. Among the different architectures of oscillator, ring-oscillatorsare the most appropriate candidates for passive RFID applications in virtue oftheir small area and low power consumption. In Section 5.1, An ultra-low-powerVCRO for passive RFID tag applications is presented. Using QFG technique, the162Power M anagem ent UnitSol ar PanelPiez oel ectric cel lC ontrol l erUnit SensorTransceiverR F - to- D C  C onverterS el f - suf f icient RFID tag  /  w ir el ess sensor  nodeTherm o- E l ectric cel lFigure 6.5: Schematic diagram of the self-sufficient RFID tag/senor node.common-mode voltage of the devices in pseudo-differential delay cells areboosted, therefore, allowing oscillation with a low supply voltage. The QFGtechnique also offers a secondary frequency tuning knob. Aquadrature-to-differential low-to-high voltage converter is presented to interfacethe low-swing output of the proposed VCRO with a higher voltage domain.Post-layout simulation results of the proposed VCRO confirm a nominaloscillation frequency of 4 MHz with a supply voltage as low as 140 mV whileconsuming 3.6 nW power. The VCRO core occupies an area of 500 µm2.As a future work, the proposed power reduction scheme for ring-oscillatorscan be implemented in a CMOS technology so that the effects of the technique ondifferent performance metrics of the oscillator (e.g., phase noise) can bedeliberately studied. The proposed oscillator can also be examined in a PLLsystem or a complete clock generator circuitry.6.8 Future Target: Self-Sufficient RFID TagAs discussed in details in this thesis, eliminating the battery as the solenon-permanent power source of passive RFID tags and wireless sensor nodes is anattractive approach. A battery-less tag (sensor node) supports a long operationlife-time and facilitates further miniaturization of the node.As a target system, a self-sufficient RFID tag (sensor node) is envisioned. The163tag harvests its required energy from all the available environmental sourcesincluding RF waves, temperature gradient, vibrations and solar radiation. For sucha self-sufficient node, an efficient RF power converter is required to harvest thetransmitted RF energy. The target system can benefit from proposed techniques inthis thesis, such as power and area efficient data converters, efficient receive modescheme (WUR) and efficient transmit mode schme (backscattering for shortranges).Such a node requires an elaborate power management unit (PMU) todynamically find the optimal source for specific application scenarios. The PMU(potentially) stores the excess energy for future use in the event of insufficientharvested power and/or power source failures. The study and proposition of newtechniques to efficiently implement such a power management unit is a good topicfor future research. The self-sufficient node is schematically depicted inFigure 6.5.164Bibliography[1] P. Kamalinejad, K. Keikhosravy, R. Molavi, S. Mirabbasi, and V.C.M.Leung. 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