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Design techniques for low-power low-noise CMOS capacitive-sensor readout circuits Shiah, Jack Chih-Chieh 2015

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Design Techniques for Low-PowerLow-Noise CMOS Capacitive-SensorReadout CircuitsbyJack Chih-Chieh ShiahB. A. Sc., The University of British Columbia, 2007M.Sc., Columbia University, 2008A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFDOCTOR OF PHILOSOPHYinThe Faculty of Graduate and Postdoctoral Studies(Electrical and Computer Engineering)THE UNIVERSITY OF BRITISH COLUMBIA(Vancouver)August 2015c© Jack Chih-Chieh Shiah 2015AbstractIn recent years, the demand for low-cost, high performance, and miniaturesized MEMS capacitive inertial sensors (accelerometer/gyroscope) has beensteadily increasing. Use MEMS capacitive accelerometer as an example, forhigh precision applications, the resolution needs to be in the µg range at thefrequency of interest. These high performance sensors are now been usedin numerous applications that require more demanding specifications. Forinstance, they found their use in active suspension, adaptive brakes, alarmsystems, tilt control, vibration, shock measurements, platform stabilization,inertial measurement units, inertial navigation/guidance, machine control,microgravity measurements, seismology, geophysical sensing, oil-field appli-cations, earthquake detection, tactical missiles, robotics and minimally in-vasive surgery.The precision in a micro-sensory system is limited by the CMOS elec-tronic interfaces, due to the often higher electrical noise associated with thecircuits. Additionally, with the growing popularity for portable devices suchas cellular phones and tablets, power consumption also becomes an impor-tant factor. Therefore, the dissertation discusses and presents several circuitdesign techniques that improve important system parameters such as noiseand power. Moreover, a design flow is provided at the end of the thesis toiiAbstractdemonstrate a systematic approach to design the sensor interface circuits.Three major readout circuit blocks have been designed, built, and tested.The first interface uses a circuit technique such that the overall system isinsensitive to parasitic capacitances from the sensing nodes. Moreover, acalibration scheme is used to remove DC offset caused by sensor capacitancemismatch. The second interface uses two circuit design techniques calledcorrelated level shifting (CLS) and chopper stabilization (CS) to reducethe noise and the finite gain error from the operational amplifier (op amp),thereby improving both the noise and power performance of the system. Thefinal interface utilizes a modified CLS technique such that it also serves as anoise and power improving mechanism. The first two readout circuits havebeen tested and measured experimentally, while the third readout circuit isverified via post-layout simulation.iiiPrefaceI, Jack Shiah, am the principle contributor of all the chapters. Dr. ShahriarMirabbasi, who is my direct research supervisor, has provided overall tech-nical support and editing assistance on the manuscript. Dr. Edmond Cretu,Dr. Mrigank Sharma, and Dr. Elie Sarraf have provided technical supportin regards to the MEMS sensor, as well as system integration (Chapter 3).The MEMS capacitive accelerometer was designed by both Dr. MrigankSharma and Dr. Elie Sarraf.As mentioned below, some of the content of this thesis is written basedon the following published or to-be-submitted works:Conference Papers1. J. Shiah, H. Rashtian, and S. Mirabbasi, “A low-noise high-sensitivityreadout circuit for MEMS capacitive sensors”, in IEEE InternationalSymposium on Circuits and Systems (ISCAS), pp. 3280–3283, May2010 [1] → Chapter 3.2. J. Shiah, H. Rashtian, and S. Mirabbasi, “A Low-Noise Parasitic-Insensitive CMOS Switched-Capacitor Interface Circuit for MEMSCapacitive Sensors”, in International NEWCAS Conference, pp. 470–ivPreface473, June 2011 [2] → Chapter 3.3. J. Shiah, and S. Mirabbasi, “A 5-V 555-µW 0.8-µm CMOS MEMScapacitive sensor interface using correlated level shifting”, in IEEEInternational Symposium on Circuits and Systems (ISCAS), pp. 1504–1507, May 2013 [3] → Chapter 5.Journal Papers1. J. Shiah, and S. Mirabbasi, “A 5-V 290-µW Low-Noise Chopper-Stabilized Capacitive-Sensor Readout Circuit in 0.8-µm CMOS UsingCorrelated-Level-Shifting Technique”, in IEEE Transactions on Cir-cuits and Systems II: Regular Paper, vol. 61, no. 4, pp. 254–258, Feb.2014 [4] → Chapter 4.2. J. Shiah, M. Sharma, E. Sarraf, S. Mirabbasi, and E. Cretu, “AParasitic-Insensitive Chopper Stabilized CMOS Readout Circuit withSensor Mismatch Cancellation for Capacitive Micro-Accelerometers”,to be submitted. → Chapter 3.vTable of ContentsAbstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiPreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ivTable of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . viList of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ixList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xGlossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviiAcknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . xixDedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.2 Organization of the Thesis . . . . . . . . . . . . . . . . . . . 92 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.1 Capacitive Micro-Accelerometer . . . . . . . . . . . . . . . . 112.2 Fabrication Process of Micro-Sensors . . . . . . . . . . . . . 16viTable of Contents2.3 Classic Low-Frequency Noise/Offset Reduction Circuit Tech-niques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.3.1 Chopper Stabilization Technique . . . . . . . . . . . . 182.3.2 Correlated Double Sampling Technique . . . . . . . . 192.3.3 MEMS Capacitive Readout Circuits in the Literature 213 A Parasitic-Insensitive Chopper-Stabilized CMOS ReadoutCircuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.1 Overview: Micro-Accelerometer . . . . . . . . . . . . . . . . 313.2 Overview of Parasitics and Mismatches . . . . . . . . . . . . 343.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . 363.3.1 Charge-Transfer Amplifier . . . . . . . . . . . . . . . 373.3.2 S/H Stage . . . . . . . . . . . . . . . . . . . . . . . . 413.3.3 Operational Amplifier . . . . . . . . . . . . . . . . . . 423.3.4 Closed-Loop Noise and Offset Consideration . . . . . 443.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 463.4.1 Implementation . . . . . . . . . . . . . . . . . . . . . 463.4.2 Electrostatic Force Testing . . . . . . . . . . . . . . . 473.4.3 Signal of Interest and Noise Floor . . . . . . . . . . . 513.4.4 Electrostatic Spring Softening . . . . . . . . . . . . . 523.4.5 Device Performance Summary . . . . . . . . . . . . . 533.5 Chapter 3 Conclusion . . . . . . . . . . . . . . . . . . . . . . 554 A Low-Noise Chopper-Stabilized Capacitive-Sensor Read-out Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564.1 Overview of CLS Operation . . . . . . . . . . . . . . . . . . 58viiTable of Contents4.2 Readout Operation and Non-Idealities . . . . . . . . . . . . . 624.3 Readout Architecture and Op Amp Structure . . . . . . . . 664.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 704.5 Chapter 4 Conclusion . . . . . . . . . . . . . . . . . . . . . . 755 A 14-bit Σ∆ CMOS MEMS Capacitive Sensor Interface Us-ing Modified Correlated Level Shifting . . . . . . . . . . . . 765.1 Modified CLS Theory of Operation . . . . . . . . . . . . . . 785.2 CMOS Interface Circuit Architecture . . . . . . . . . . . . . 815.2.1 Front-End Circuit Block . . . . . . . . . . . . . . . . 835.2.2 Back-End Circuit Block . . . . . . . . . . . . . . . . . 855.3 Post-Layout Simulation Results . . . . . . . . . . . . . . . . 885.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 955.5 Chapter 5 Conclusion . . . . . . . . . . . . . . . . . . . . . . 986 Overall Design Flow and Discussion on Reported Readouts 996.1 Design Flow Chart and Detailed Explanation . . . . . . . . . 1006.2 General Discussion on Reported Readouts . . . . . . . . . . 1037 Conclusion and Future Work . . . . . . . . . . . . . . . . . . 1057.1 Research Contributions . . . . . . . . . . . . . . . . . . . . . 1057.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109viiiList of Tables3.1 Design Parameters of the Accelerometer . . . . . . . . . . . . 343.2 Device Sizing of the Op Amp . . . . . . . . . . . . . . . . . . 443.3 Performance Summary . . . . . . . . . . . . . . . . . . . . . . 544.1 Performance Summary and Comparison . . . . . . . . . . . . 745.1 Performance Summary and Comparison . . . . . . . . . . . . 94ixList of Figures1.1 A microphotograph of an example of a single chip MEMSsystem, which realizes the complete analog interface for acapacitive MEMS accelerometer [90]. . . . . . . . . . . . . . . 61.2 Block diagram of a14 bits open-loop Σ∆ CMOS SOI capaci-tive accelerometer [93]. . . . . . . . . . . . . . . . . . . . . . . 82.1 The simplified mechanical model of a single axis accelerometer(1-DoF resonator) having a proof mass m that is suspendedby a spring kx to the frame. The losses are modelled by adamper Dx. The variable x represents the position of theproof mass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2 A simplified diagram of mechanical structure of a differentialcapacitive accelerometer (at rest). When a force is appliedto the proof mass (right or left horizontally), the induceddisplacement causes the gap between the fingers d0 to vary,thus generates changes in capacitances for Cs+ and Cs−. . . . 14xList of Figures2.3 The modeling of the differential capacitive accelerometer inthe electrical domain. As shown in the figure, the MEMSsensor can be simply viewed as two variable capacitors Cs+and Cs−. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.4 Micro devices on silicon wafer from fabrication process [48]. . 172.5 Frequency domain representation of a chopper stabilized am-plifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.6 A MEMS capacitive readout example demonstrating corre-lated double sampling by using an error storage capacitor CH . 202.7 Electrical noise comparison between DT and CT based sens-ing circuits [90]. . . . . . . . . . . . . . . . . . . . . . . . . . . 222.8 Block diagram of the capacitive open loop ULP readout front-end [68]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.9 Block diagram of a first-order Σ∆ modulator. . . . . . . . . . 262.10 A first-order Σ∆ ADC for direct capacitance-to-digital con-version [48]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272.11 An example architecture of a CT-based capacitive readoutcircuit [91]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.1 The simulated result of 0x mode of the micro-accelerometerin CoventorWare. . . . . . . . . . . . . . . . . . . . . . . . . . 323.2 (a) A photograph of the fabricated capacitive micro-accelerometerunder test; (b) Equivalent electrical model. . . . . . . . . . . 32xiList of Figures3.3 A simple SC charge-transfer MEMS capacitive readout cir-cuit. The MEMS sensor is shown in the shaded area. Theparasitic capacitances, i.e., Cp1, Cp2, and Cp3, are also shownin the figure. . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.4 Overall system architecture of the implemented CMOS MEMSSiP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.5 The schematic of the proposed capacitive readout circuit thatconsists of a parasitic-insensitive charge-transfer amplifier withsensor mismatch cancellation and a S/H stage. . . . . . . . . 383.6 A CS parasitic-insensitive charge-transfer MEMS capacitivereadout circuit with sensor mismatch cancellation. The S/Hstage acts as a demodulator and produces a smoother signalat the output. . . . . . . . . . . . . . . . . . . . . . . . . . . . 403.7 The clock waveforms for the CMOS readout as shown in Fig. 3.6. 413.8 Simulation result showing that the DC voltage level at theoutput of the readout circuit is not affected by different valuesof parasitic capacitances. . . . . . . . . . . . . . . . . . . . . . 423.9 The schematic of the folded-cascode op amp designed to min-imize both thermal and flicker noise. . . . . . . . . . . . . . . 433.10 The S-i-P (CMOS and MEMS accelerometer integrated in apackage) is mounted on a PCB for testing. . . . . . . . . . . . 463.11 The test set up of CMOS MEMS S-i-P in simplified schematicform using electrostatic force testing. . . . . . . . . . . . . . . 473.12 The actual test set up to obtain measurements for the S-i-Pwith each equipment identified. . . . . . . . . . . . . . . . . . 50xiiList of Figures3.13 The relationship between electrostatic equivalent acceleration(ael) in terms of g to the sensor output voltage. Note thatthe probe has a 10× attenuation. . . . . . . . . . . . . . . . . 513.14 The spectra of the S-i-P output under sinusoidal input accel-eration of 1.2 mg at 500 Hz (RBW = VBW = 1 Hz). . . . . . 523.15 The effect of electrostatic spring softening is demonstratedhere: when the actuating voltage increases from 2.5 V to 5V, the resonant frequency of the accelerometer decreases. . . 534.1 CLS virtual ground error voltage reduction analysis: (a) opamp circuit without CLS and (b) op amp circuit with CLS. . 594.2 Operation of correlated level shifting (CLS). Three majorclock phases are required for the circuit operation: sample,estimate, and level shift. Single-ended structure is shown forsimplicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604.3 Operation of the proposed CS + CLS charge-transfer ampli-fier. Three major clock phases are required for the circuitoperation: sample, estimate, and level shift. Note that theop amp offset model is included at the inverting input. . . . . 624.4 Clock waveforms governing the operation of the proposed CS+ CLS charge-transfer amplifier. . . . . . . . . . . . . . . . . 63xiiiList of Figures4.5 Schematic of the proposed capacitive readout circuit whichconsists of variable capacitors (to mimic the capacitive sen-sor), switches for chopper stabilization, CLS charge-transferamplifier, S/H buffers and an externally connected unity gaindifferential amplifier (INA 105) for measurement purposes. . . 674.6 Digitally controlled bank of capacitors to mimic the MEMScapacitive sensor. . . . . . . . . . . . . . . . . . . . . . . . . . 674.7 The schematic of the folded-cascode op amp that is imple-mented to minimize thermal and flicker noise. . . . . . . . . . 694.8 Micrograph of the test chip in 0.8 µm CMOS. . . . . . . . . 704.9 The test setup that is implemented to obtain important mea-surement results. Each equipment in the figure is identifiedin white text. . . . . . . . . . . . . . . . . . . . . . . . . . . . 714.10 Differential output (in red) of the CMOS readout circuit withrespect to a differential capacitance variation of 24 fF chang-ing at approximately 400 Hz. . . . . . . . . . . . . . . . . . . 724.11 Measured sensitivity of the CMOS readout circuit at differentgain settings. The measured output voltage indicates the ACamplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734.12 The spectrum of the output from 10 to 600 Hz when theinput is applied at about 400 Hz. The capacitance noise flooris 0.018 aF/√Hz. . . . . . . . . . . . . . . . . . . . . . . . . . 73xivList of Figures5.1 (a) Operation of correlated level shifting (CLS). (b) Oper-ation of modified correlated level shifting (MCLS). Single-ended structure is shown for simplicity. . . . . . . . . . . . . . 795.2 The overall sensing interface architecture with the physicalsensor, front-end and back-end circuits. The front-end in-cludes a modified correlated level shifting charge-transfer am-plifier and a S/H stage while the back-end circuit includes anAAF plus a first-order Σ∆ ADC . . . . . . . . . . . . . . . . 825.3 Schematic of the proposed capacitive readout front-end cir-cuit which consists of variable capacitors (to mimic the MEMSsensor), modified CLS charge-transfer amplifier, and S/H dualbuffers. The clock waveforms are also included in this figure. 835.4 Schematic of the proposed capacitive readout back-end circuitwhich consists of an AAF and a SC Σ∆ ADC using CDS. Theclocks used in the back-end are two non-overlapping clocks. . 865.5 Layout of the proposed interface circuit in 0.8 µm CMOS.Note that the active area is enclosed in a white dotted box. . 895.6 Transient response of the CMOS readout circuit front-endwhen an input capacitance variation of 50 fF (100 fF differ-ential) is applied at 500 Hz. . . . . . . . . . . . . . . . . . . . 905.7 Simulated low-frequency noise response of the two approaches(CLS and proposed modified CLS). . . . . . . . . . . . . . . . 91xvList of Figures5.8 Transient response of the CMOS readout back-end when aninput capacitance variation of 50 fF (100 fF differential) isapplied at 500 Hz. The red bitstream is the output of the Σ∆ADC that is getting filtered. The brown signal represents thelow-pass filtered output, which tracks the input signal in blue. 925.9 The spectral content of the PWM output. The input signal isa sinusoidal capacitance variation with a frequency of 500 Hz.The Σ∆ ADC processes the input and shapes the quantiza-tion noise out of the signal band. The DR is ∼85 dB, whichtranslates to 14 bits of resolution. . . . . . . . . . . . . . . . . 935.10 Micrograph of the overall sensing device: CMOS readout cir-cuit is on the right where as the MEMS accelerometer is onthe left. The sensor and the electronics are wire-bonded to-gether in a single package. . . . . . . . . . . . . . . . . . . . . 965.11 Dedicated PCB to test the accelerometer sensing system whichis placed at the centre of the board. . . . . . . . . . . . . . . 976.1 A general readout circuit design flow chart. . . . . . . . . . . 101xviGlossaryMEMS Microelectromechanical SystemsCS Chopper StabilizationCDS Correlated Double SamplingCLS Correlated Level ShiftingMCLS Modified Correlated Level ShiftingADC Analog-to-Digital ConverterDAC Digital-to-Analog ConverterSC Switched-CapacitorDoF Degree-of-FreedomDSP Digital Signal ProcessingCT Continuous TimeDT Discrete TimeULP Ultra-Low-PowerAAF Anti-Aliasing FilterxviiGlossaryPWM Pulse Width ModulationAM Amplitude ModulationFFT Fast Fourier TransformxviiiAcknowledgementsThe work presented in this thesis is carried out in the System-on-Chip (SoC)lab at the University of British Columbia (UBC). The entire research isfunded in part by AUTO21 Network of Centres of Excellence, the NaturalSciences and Engineering Research Council of Canada (NSERC) and the In-stitute for Computing, Information and Cognitive Systems (ICICS) at UBC.CAD support and access to technology is facilitated by CMC Microsystems.I would like to thank all of the aforementioned affiliations for the financialand technical support throughout the years.Moreover, I would wish to express my gratitude towards my supervisor,Dr. Shahriar Mirabbasi, for his guidance and patience during the course ofthis research. I am grateful for the interesting research topic and the chanceto learn independently. I would also like to acknowledge Dr. Roberto Rosalesfor his help in regards to all the experimental equipment and for managingthe test lab. The two people I mentioned in this paragraph both have greatpersonalities and are two of the nicest human beings I know of.I would like to show my sincere appreciation towards Dr. Edmond Cretu,Dr. Elie H. Sarraf, and Dr. Mrigank Sharma, for providing great amount ofknowledge regarding MEMS micro-systems and numerous sensor elements.Without their aid, the experimental work would never have become a reality.xixAcknowledgementsMoreover, thanks to all my colleagues and friends in the SoC group for theirfriendly support.Last but not least, I want to thank my parents, Richard and Rose; mysister, Tammy; and my girlfriend, Joyce, for being so supportive no matterwhich stage of life I am at. Especially my mother, even during the darkestmoments, she has been nothing but encouraging to me.xxDedicationTo my parents.xxiChapter 1IntroductionMicro-electro-mechanical systems (MEMS) describe the technology of minia-ture devices that combine both electrical and mechanical components. Morespecifically, they generally consist of a microprocessor (electrical) and sev-eral functional blocks that interact with the mechanical surrounding such asmicro-sensors [5]. These sensors are extremely small, having feature sizes inthe micrometer scale. When the sensors are integrated within a broader sys-tem, combinations of different functionalities can be enabled, and amazingthings happen. Systems built in MEMS technologies are generally smallerthan a few millimetres.Thanks to the technology advancement of silicon integrated circuit (IC),electronics can fortunately be realized on a tiny piece of silicon. As of theyear 2014, transistor gate length is on the order of 10 nm [6], which issmaller than the Rhinovirus (∼20 nm). With such prosperous IC industry,MEMS devices can also be built using IC fabrication technology. This opensup tremendous opportunities and possibilities since micro-machined silicondevices (mechanical) can be compatible with the surrounding electronics[7]. Many industries benefit from this fact because of the batch fabricationtechniques. Sensors can be built in the micro scale with low cost and high1Chapter 1. Introductionreliability. Ever since the end of 1980, miniature silicon-based inkjet printerhead, pressure sensors, and accelerometers were already mass fabricated,which marks the beginning of a new “MEMS era” [8–11].The readout/interface circuits (electrical), combining with the mechan-ical micro-sensors, form a complete MEMS device. In a complete MEMSdevice, the readout essentially translates the analog mechanical informa-tion, such as acceleration or angular speed, into an electrical signal, whichis further processed by a computer. Such“complete system” allows MEMStechnology to break into new application fields. The fact that the perfor-mance of the complete MEMS system is often largely dependent on theelectrical readout, the development and design of such readout circuit hasmaintained as a hot research topic for more than two decades now. Thisthesis is also a research work based on the readout electronics.Among all the different MEMS applications, the focus of this thesis isrelated to MEMS inertial sensor, which can be treated as a measurementunit that measures acceleration, velocity, and orientation of a moving ob-ject. The two main sensing components that are required in an inertialsensing application are accelerometer and gyroscope. They are used in a va-riety of applications including gaming, human activity monitoring, vehicularnavigation, airplanes, drones, and earthquake detection [12–14].Certain applications are more demanding than others in terms of sensi-tivity, resolution, signal to noise ratio (SNR) and dynamic range. Use ac-celerometer as an example, the need for a highly sensitive, high resolution/low-g (µg), and small sized MEMS accelerometer has been growing. These highperformance sensors are now been used in numerous applications that re-2Chapter 1. Introductionquire more demanding specifications. For instance, these accelerometersfound their use in active suspension, adaptive brakes, alarm systems, tiltcontrol, vibration, shock measurements, platform stabilization, inertial mea-surement units, inertial navigation/guidance, machine control, microgravitymeasurements, seismology, geophysical sensing, oil-field applications, earth-quake detection, tactical missiles, robotics and minimally invasive surgery[15–17, 19–28, 41, 42, 49–55, 58, 65].In the inertial navigation category, the author in [29] notes that highperformance navigation grade (0.01 deg/hr and 25 µg) ring laser gyroscope(RLG) and inertial measurement unit (IMU) FOG IMUs are still relativelylarge and expensive. The same author states that MEMS system with per-formance of around 1 deg/hr and 100 µg would be available in the future.In the field of robotic surgery, inertial sensors are used for detecting theposition and orientation of the surgical tool. For example, the signal out-puts can be integrated to determine or estimate the distance travelled by asurgical tool. The authors in [30] propose an active hand-held instrumentto sense and compensate physiological tremor and other unwanted move-ments during a viteoretinal micro-surgery. The proposed system comprisessix inertial sensors to compute and control the motion of the tip.Additionally, seismic sensing for geophysical and oil explorations appli-cations represents challenges in high sensitivity and low-g measurements.The MEMS technological breakthrough can definitely provide technical andeconomical benefits for seismic acquisition system users. This requires mea-surement of extremely small acceleration signal, on the order of ∼ ng/√Hzat very low frequencies (less than 100 Hz). There seems to be a grow-31.1. Objectiveing trend in the industry to replace geophones with MEMS accelerometers,where large arrays of sensors tremendously increase the quality of seismicimaging. As a result, small size and weight of MEMS sensors can facilitatethe deployment of very large seismic surveys [31]. An example of an inertialsensor used for such application is reported in [32]. They report the usageof 3C MEMS-based digital accelerometer (two horizontal and one vertical).According to the market research done by IndustryARC [14], from theyear 2013 to 2018, the global inertial sensor market has a 10.5% of compoundannual growth rate (CAGR). This forecast is based on the fact that the keycomponents inside the sensory systems will be cheaper and more compactdue to technology advancement.It is worth to mention that a CAGR of 10.5% can be considered healthyand steady. However, this rate predicted by IndustryARC seems to be quiteconservative. From the market research conducted by MICROmanufactur-ing [33], inertial consumer combo sensors have a CAGR of 35%! The im-portance of the aforementioned research demonstrates a very strong trendin the inertial sensor market, which is the main motivation of this thesis.Note that the mechanical sensor of focus in the thesis is the accelerometer.1.1 ObjectiveThere are three major transduction mechanisms: piezoresistive, piezoelec-tric, and capacitive sensing [12]. Piezoresistive sensing detects the change ofresistance of the piezoresistive material due to acceleration induced stress,and this resistance change can be easily detected by the dedicated electron-41.1. Objectiveics. Piezoelectric sensing is based on a charge polarization of the piezo-electric material due to strain. Such charge polarization would produce achange in voltage. Lastly, capacitive sensing measures the change in capac-itance due to the relative movement of a proof mass and the frame. Amongthem, capacitive sensing has been widely used due to its high sensitivity,good noise performance, low temperature coefficient, and good compatibil-ity with CMOS technology for integrated sensor-based systems [34, 35]. Anexample of a capacitive accelerometer based MEMS chip is shown in Fig. 1.1[90]. Here, the mechanical sensor is implemented in the same chip as theelectrical readout. This way, the parasitic capacitance between the sensorand the readout can be minimized. This is especially beneficial if the deviceis intended for high-precision applications. Moreover, a single-chip solutionwould greatly reduce the size of the overall system, as well as the cost dueto the elimination of wire bonding.Many high-precision capacitive-sensing applications demand a high reso-lution sensor. The resolution of the system depends on the noise performanceof the devices within it. As an example, the noise floor of an accelerometerdetermines the minimum detectable acceleration. Noise performance of areadout circuit has been the key research in the past [41, 42]. Moreover,when the sensors are used in portable devices, power consumption becomesanother important factor. With such requirement on sensing accuracy andpower, noise and other non-idealities must be minimized in the interface sys-tem to obtain satisfactory performance. In a complete MEMS system, thereare two types of noise: mechanical (Brownian) and electrical. The mechan-ical noise is related to the sensor, whereas the electrical noise is associated51.1. ObjectiveFigure 1.1: A microphotograph of an example of a single chip MEMS sys-tem, which realizes the complete analog interface for a capacitive MEMSaccelerometer [90].with the readout circuit. For a sensor with proof mass m and viscous damp-ing coefficient b, its Brownian noise in the form of an equivalent accelerationnoise can be expressed as [91]:a2n =4kTb9.82m2[g2/Hz] (1.1)where k is the Boltzman constant (1.38 × 1023 J/K) and T is the absolutetemperature. Depending on the size of the proof mass, the noise can vary.Typically, this noise is very small for high resolution applications, which isin the µg/√Hz range. Due to the very low mechanical noise associatedwith the sensor, generally speaking, the electrical readout circuit puts the61.1. Objectivelimit on the resolution of the overall system. It is therefore very importantthat the noise floor of the electronic interface circuit is reduced to the levelof the sensor mechanical noise. The major noise contribution in a CMOSintegrated readout circuit is the flicker or 1/f noise of the input transistorsat very low frequencies. This noise originates from ”trapped” charges atthe interface between the substrate and the oxide. These charges can bereleased by the energy state and result in the noise in the drain current.There are many other mechanisms that are believed to generate flicker noise[57]. Additionally, another electrical factor that affects the resolution ofthe system is the offset of the input transistors. In terms of offset, it isconsidered as a DC signal which originates from the imperfection of thefabrication technology. As devices are going through fabrication steps, thelithography cannot be absolutely symmetrical, thus generating mismatchesin the transistors, which, in turn, produce DC offsets when circuits are built.As far as power is concerned, the MEMS device should be operated inopen-loop configuration. An example of an open-loop sensing accelerometercan be found in [90], and a closed-loop one can be found in [58]. A closed-loop system is able to increase the dynamic range, improve the linearity, andflatten the frequency response [59]. However, more components are requiredto implement a closed-loop system, which would consume a lot more power.Therefore, in order to achieve a low power device, operation in open-loopconfiguration may be more favourable. Chip area could be another spec-ification that needs to be met. With all of the aforementioned importantparameters of interest, the design of the electronic interface becomes a chal-lenging and demanding task.71.1. ObjectiveFigure 1.2: Block diagram of a14 bits open-loop Σ∆ CMOS SOI capacitiveaccelerometer [93].An example block diagram of an open-loop MEMS capacitive sensor isshown in Fig. 1.2, where the capacitive sensor (on the far left) producesthe input to the electrical system. The input is a capacitance variationgenerated from a force applied to the sensor. Then, the analog front-end,which converts the capacitance variation into a voltage signal. This signalis then filtered and digitized by an ADC in the back-end. Although allof the aforementioned circuit blocks are designed in this dissertation, theemphasis is on the capacitance-to-voltage converter, or the charge-transferamplifier block. The ultimate scientific goal is to propose analog circuitdesign techniques to improve readout circuit performance in terms of noiseand power, leading to a higher resolution, and lower power system.81.2. Organization of the Thesis1.2 Organization of the ThesisThis dissertation is organized into seven chapters. In the first chapter, themotivation behind the research and the main objective are introduced. Notethat the objective is the discussion on several proposed low-power low-noisecircuit design techniques for capacitive micro-sensors, in particular, inertialsensors such as an accelerometer (gyroscopes are not covered).In Chapter 2, an overview of capacitive micro-accelerometer is first pre-sented, including its theory of operation, modelling, and fabrication pro-cess. Then, well known circuit techniques that reduce low-frequency noiseand offset are discussed. The name of the techniques are correlated doublesampling (CDS) and chopper stabilization (CS). Finally, different types ofsensing readout circuits that have been used in either industry or academiaare described.In Chapter 3, a chopper stabilized parasitic-insensitive interface with sen-sor mismatch cancellation for capacitive micro-accelerometers is presented.First, the design and the specifications of the mechanical sensing element(accelerometer) is discussed. Then, the proposed switched-capacitor (SC)readout circuit that interfaces with the sensor is described in detail. In thisparticular work, the electrical readout and the mechanical sensor are wire-bonded inside a single package forming a system-in-a-package (SiP). Theexperimental results are shown at the end of the chapter.In terms of Chapter 4, a proposed capacitive readout circuit using cor-related level shifting (CLS) technique in conjunction with CS is described.The CLS technique was originally presented in [98] and it will be briefly91.2. Organization of the Thesisoverviewed in this chapter. The technique greatly boost op amp loop gain,thus achieving higher accuracy, which is beneficial for capacitive sensingreadout circuits. Additionally, CS is applied in the circuit to reduce offsetand 1/f noise. This integrated circuit is not interfaced with a MEMS sen-sor. Instead, a pair of on-chip variable capacitors are used to emulate themechanical sensing element. Experimental results are reported at the endof the chapter.In regards to Chapter 5, a modification to the CLS technique is proposedin which it reduces the offset and 1/f noise of the designed MEMS interfacefront-end, while preserving the benefits from the original CLS. The theory ofoperation of the technique is discussed in detail. Moreover, a Σ∆ analog-to-digital converter (ADC) is used in the back-end circuit block to digitize theanalog signal from the front-end. At the end of this Chapter, the post layoutsimulation and measurement results are presented, followed by concludingremarks.In Chapter 6, a general design flow describing readout circuit designprocess is presented, where MEMS accelerometer is used as an example.Moreover, the pros and cons of the reported readout circuits are discussed,such that the reader/designer is able to select suitable techniques for his/herown interface circuit design.In Chapter 7, the major achievements of this work are summarized asconcluding remarks. Additionally, some future directions for further inves-tigations are provided.10Chapter 2BackgroundAs discussed in the previous chapter, capacitive MEMS sensors are widelyused and can be found in many applications, such as high-precision iner-tial navigation. In this thesis, the ultimate scientific goal is to propose anddemonstrate analog circuit techniques that are beneficial to the readout usedin these high precision capacitive sensors. Therefore, in terms of the back-ground of the thesis, the basic knowledge of a capacitive sensor will be firstintroduced in the form of a capacitive micro-accelerometer, where its theoryof operation and electrical modelling will be discussed in detail. Secondly,some classic circuit techniques that would reduce the adverse effects whenthe capacitive sensor interfaces with the electronics will be presented. Fi-nally, a literature survey that demonstrates several state-of-the-art completeinertial MEMS devices concludes this chapter.2.1 Capacitive Micro-AccelerometerThe operation of a basic accelerometer can be explained with the aid of asimplified mechanical model illustrated in Fig. 2.1, where a proof mass m isconnected to a rigid body via a spring having a spring constant of kx. Also,the environment inside the frame provides damping Dx to reduce excessive112.1. Capacitive Micro-AccelerometerFigure 2.1: The simplified mechanical model of a single axis accelerometer(1-DoF resonator) having a proof mass m that is suspended by a spring kxto the frame. The losses are modelled by a damper Dx. The variable xrepresents the position of the proof mass.ringing. The mass can only move in the x-direction. Note that this exampleis essentially a one-degree-of-freedom (1-DoF) resonator, where a single-axis accelerometer is realized for the detection of translational (x-direction)acceleration.When an external force (Fext) is applied to the accelerometer in thepositive x-direction, the mass would be displaced by a distance x. Thespring would generate an elastic/restoring force (Fe) expressed as:Fe = −kxx (2.1)Moreover, in addition to the spring restoring force, there is a force that122.1. Capacitive Micro-Accelerometerdepends on the velocity of the proof mass. Such force represents the energylost in the resonator. The losses are caused by, for instance, material/anchorlosses, mode conversion losses, and, especially, viscous losses, which is gen-erally due to air damping [60]. The force exerted by the damper is:Fd = −Dxδxδt(2.2)Newton’s second law of motion states that in an inertial frame of ref-erence, the sum of all the forces acting on a mass is the mass times itsacceleration:ΣF = ma (2.3)Therefore, for the 1-DoF system shown in Fig. 2.1, the equation of motionfor the proof mass is [60]:max +Dxδxδt+ kxx = Fext (2.4)where ax = δ2x/δt2, and Fext represents all the externally applied forcesincluding the Brownian noise and electrostatic force.Equation (2.4) demonstrates a relationship between the displacementx, and the acceleration a. In other words, an external force acting on theaccelerometer induces a displacement on the proof mass, and this displace-ment can be detected to measure the amount of acceleration associated withthe external force. For a capacitive accelerometer, the generated displace-ment under an outside force causes a change in capacitance (∆C) which132.1. Capacitive Micro-AccelerometerFigure 2.2: A simplified diagram of mechanical structure of a differentialcapacitive accelerometer (at rest). When a force is applied to the proofmass (right or left horizontally), the induced displacement causes the gapbetween the fingers d0 to vary, thus generates changes in capacitances forCs+ and Cs−.can be converted into an electrical signal such as voltage or current via adedicated electronic readout circuit. The output of the interface circuit isthen fed through digital signal processing (DSP) and the acceleration canbe determined.A simplified structure of a differential capacitive accelerometer is shownin Fig. 2.2, where a movable proof mass can only go either left or rightdepend on the direction of the external force (left/right). d0 representsthe nominal distance between the “shaded” fingers. The fingers act as twoparallel plate capacitors (Cs+ and Cs−) where the capacitances depend onthe gap between the fingers:142.1. Capacitive Micro-AccelerometerCs+ =0rAold0 − x(2.5)Cs− =0rAold0 + x(2.6)where 0 is the vacuum permittivity, r is the relative permittivity, and Aolis the overlapping area between a pair of capacitive fingers.When a force is applied to the capacitive sensor, since the proof mass isnot fixed to any frame, it is free to move (only left/right in this example).Therefore, the fingers connected to the proof mass would move with the proofmass. The fingers attached to the anchors does not move because the anchorsare fixed in space. This will induce a differential change in the distancebetween the fingers when the proof mass move in either directions. Thischange in the distance will generate changes in the differential capacitancesaccording to (2.5) and (2.6).If the displacement x is much smaller than the gap d0:Cs+ = C0 + ∆C (2.7)Cs− = C0 −∆C (2.8)where C0 is the fixed sense capacitance and ∆C is the capacitance variationinduced by acceleration:C0 =0rAold0(2.9)152.2. Fabrication Process of Micro-SensorsVDDVSSSense NodeCS+ = C0 + ΔCCS- = C0 - ΔCFigure 2.3: The modeling of the differential capacitive accelerometer in theelectrical domain. As shown in the figure, the MEMS sensor can be simplyviewed as two variable capacitors Cs+ and Cs−.∆C =0rAolxd20 − x2(2.10)Equation (2.9) and (2.10) demonstrate that the differential capacitive ac-celerometer can be simply modelled as two variable capacitors in the elec-trical domain as shown in Fig. 2.3.2.2 Fabrication Process of Micro-SensorsAs mentioned in the Introduction, microstructures have adopted IC fabrica-tion technologies and can be made in batches for mass production purposes.In other words, a large number of individual micro-devices can be realizedsimultaneously on a common substrate, usually on a silicon wafer. This canbe illustrated in Fig. 2.4 [48]. The fabrication process involved in creating162.2. Fabrication Process of Micro-SensorsFigure 2.4: Micro devices on silicon wafer from fabrication process [48].the microstructures include thin film deposition, photolithography, etching,and many more. After the fabrication is completed, the wafer is diced (di-vided) into separate micro devices. Each device is its own entity.The two classical micro-fabrication techniques that have been used to im-plement MEMS capacitive sensors are surface micromachining [36–40, 42, 45]and bulk micromachining [43–47]. In surface micromachining, the mechan-ical microstructures are created by depositing and patterning thin films onthe surface of a substrate, i.e., a silicon wafer. The resulting structure hasa small mechanical proof mass, which limits the resolution of the micro-sensors. In contrast, bulk micromachined devices have much larger proofmass which leads to better resolution and higher sensitivity.172.3. Classic Low-Frequency Noise/Offset Reduction Circuit Techniques2.3 Classic Low-Frequency Noise/OffsetReduction Circuit TechniquesWhen a capacitive sensor such as the one explained in the previous section isinterfaced with CMOS electronics, the noise/offset coming from the electricalside becomes an issue. If the electrical noise is higher than the mechanicalnoise at the frequency of interest, the overall sensor resolution would belimited by the former. Such problem is briefly discussed in the Introduction.In CMOS circuits, when there is no noise/offset compensation applied,flicker noise is dominant in the low-frequency band. For many high preci-sion MEMS sensing applications, the input signal varies slowly; therefore,low-frequency noise should be carefully dealt with. Throughout the historyof CMOS circuit design, there are two classic circuit techniques that areintended to significantly reduce the flicker noise and offset: chopper sta-bilization (CS) and correlated double sampling (CDS) [96]. Although thetheory of operation between the two are different, they achieve the samegoal: reduction of low-frequency imperfections. In this chapter, both CSand CDS are introduced and discussed to give the reader an idea on howthese techniques work and operate.2.3.1 Chopper Stabilization TechniqueThe basic fundamental of CS can be best described graphically as shownin Fig. 2.5 [100]. A slow varying input signal Vin (signal of interest) is firstmodulated to higher frequency at fchop via Vchop shown as VA. The flickernoise should be insignificant compared with thermal noise at the modulating182.3. Classic Low-Frequency Noise/Offset Reduction Circuit TechniquesFigure 2.5: Frequency domain representation of a chopper stabilized ampli-fier.(chopper) frequency (fchop). The modulated signal with noise componentsare then amplified, and gone through the second modulation process viaVchop d. The signal of interest is demodulated back to the baseband, whilethe flicker noise is modulated to higher frequency fchop. A low pass filter(LPF) with a correct cutoff frequency at node VB would filter out the flickernoise, leaving the signal at the baseband free of 1/f noise. Detailed noiseanalysis can be found in [96].2.3.2 Correlated Double Sampling TechniqueIn terms of CDS, typically the circuit operates under two phase clockingwhere the op amp DC offset and low-frequency noise are sampled in onephase, and their effects are subtracted in the next phase by the instantaneousvalue of the contaminated signal. This operation can be best described bya simple example as shown in Fig. 2.6 [61]. In this example, the circuit192.3. Classic Low-Frequency Noise/Offset Reduction Circuit TechniquesFigure 2.6: A MEMS capacitive readout example demonstrating correlateddouble sampling by using an error storage capacitor CH .is a capacitive sensor readout, where the sensor is modelled by a pair ofdifferential variable capacitors. The reader can refer back to Fig. 2.3 formore details regarding such model.In the ideal case, where circuit non-idealities do not exist, the output ofthe readout circuit (Vo) is:Vo =2∆CCAVs (2.11)where ∆C is the change in capacitance, CA is the feedback capacitor, andVs is the voltage source that charges the capacitive sensor.Unfortunately, noise and offset always play a role when the circuit isimplemented in the real world. Therefore, CDS is used to greatly reducethe aforementioned op amp imperfections. The key player in this circuit202.3. Classic Low-Frequency Noise/Offset Reduction Circuit Techniquesis the error storage capacitor CH . At the end of φ1, the sampling switchlocated at the inverting input of the op amp is opened, thereby injectingcharge and kT/C noise into the amplifier summing node. During the secondhalf of φ2, the aforementioned charge injection and kT/C noise, plus theinput referred noise and offset of the op amp, are processed (amplified) andstored onto CH . When φ3 is high, voltage sources ±Vs are applied to thesensor capacitors, and the capacitance variation is translated into a voltagevariation at the amplifier output. At the same time, the output containsboth the signal of interest and the errors (noise and offset). These errors aresubtracted by the previously stored imperfections on CH , and results intoa much better signal to noise ratio. Moreover, it is worth mentioning thatthe offset, charge injection, and kT/C noise are completely cancelled to thefirst order. Detailed noise analysis can be found in [96].2.3.3 MEMS Capacitive Readout Circuits in the LiteratureIn this subsection, a number of innovative capacitive readout circuits inthe literature will be discussed. To sense and process a sensor’s physicalinformation, the interface circuit can be implemented in either discrete-time(DT) or continuous-time (CT) fashion. Also, as mentioned in the previouschapter, depending on the requirements of the application, the sensor systemcan be either open-loop or closed-loop. If a low-cost and low-power systemis desired in an application, open-loop style should be considered. On theother hand, if the end users are more interested in a large dynamic range andhigh linearity system, closed-loop sensor would be the obvious choice. Forthis thesis, power consumption is more of the focus instead of high linearity,212.3. Classic Low-Frequency Noise/Offset Reduction Circuit TechniquesFigure 2.7: Electrical noise comparison between DT and CT based sensingcircuits [90].therefore, open-loop readouts will be the main discussion.DT MEMS capacitive readout circuits essentially make use of switched-capacitor charge transfer amplifier scheme, which is very widely used in theliterature [61–68]. This approach is very robust and can be conveniently im-plemented in CMOS technology. The primary issue with switched-capacitorinterface circuit would be its high noise floor due to high kT/C noise atlow capacitance, thermal noise of resistive MOS switches, and noise folding.Fig. 2.7 shows an interesting plot that compares the acceleration noise be-tween DT and CT circuits [90]. Although DT circuits have the theoretical222.3. Classic Low-Frequency Noise/Offset Reduction Circuit TechniquesFigure 2.8: Block diagram of the capacitive open loop ULP readout front-end [68].worse noise performance, the power consumption usually is less than its CTcounterparts. This is because CT systems generally require more peripheralcircuit blocks such as demodulator or low pass filter (LPF). Note that CT-based readout can be either continuous-time current (CTC) sensing [69] orcontinuous-time voltage (CTV) sensing [69–71, 90, 91, 100]. In this thesis,only CTV would be discussed.Discrete-Time Based InterfaceThe first type of MEMS capacitive interface circuit that I would like to in-troduce is a DT, open-loop, ultra-low-power (ULP) readout. As mentionedpreviously, open-loop DT based circuits are more power efficient. ULP sen-sor interface circuits have been reported in [68, 72–74].In [68], the overall structure of the capacitive readout circuit can berepresented in a block diagram as shown in Fig. 2.8. This is a genericsensor interface chip, which means it can be applied to a broad range ofdifferent capacitive sensors. The externally applied input signal, i.e., anacceleration, is first converted into a force via a gain block G1, which isessentially the mass of the sensor (F = ma). Simultaneously, the force232.3. Classic Low-Frequency Noise/Offset Reduction Circuit Techniquesgoes through the resonator (HRES), in this case, the accelerometer, andgenerates a displacement between the “plates” that forms the capacitor.Note that the resonator is explained in Section 2.1. Such displacementcreates a capacitance variation throughG2 (refer to Section 2.1). The changein capacitance is then translated into a change in analog voltage variation viaa capacitance-to-voltage converter (HC−V ). Finally, the voltage variation isdigitized via an analog-to-digital converter (ADC). In this case, it is anopen-loop Σ∆ ADC.Since DT circuits exhibit more noise, noise reduction circuit techniquesshould be used. In [68], both CS and CDS are used to improve the overallresolution of the readout front-end. CS is used to mainly deal with the mis-matches between the two capacitance-to-voltage converters, whereas CDSis used to cancel the 1/f noise and amplifier offset. The detailed circuitschematics and analysis can be found in the paper. It is important to notethat the focus of the ULP chip is obviously low-power design, at the expenseof lower resolution, which is 9 bits.Another similar design can be found in [93], which is a capacitive read-out for a SOI accelerometer. Again, this is an open-loop design, wherethe authors decoupled the Σ∆ modulator from the sensor to achieve op-timized performance regardless of the sensor capacitance [92]. The sameblock diagram in Fig. 2.8 can also be applied for this circuit, except thatan anti-aliasing filter (AAF) is used in between the capacitance-to-voltageconverter and the Σ∆ ADC. The actual block diagram of this particularsystem is shown in Fig. 1.2 in the Introduction. The capacitance-to-voltageconverter is essentially the SC charge-transfer amplifier with programmable242.3. Classic Low-Frequency Noise/Offset Reduction Circuit Techniquesgain control that determines the dynamic range of the system. The authorsuse CDS in the capacitance-to-voltage converter to reduce op amp offset andlow-frequency noise. The signal out of the S/H block is fed to the ADC.Detailed circuit schematics and analysis can be found in the paper. Notethat in this design, the authors focus on the resolution of the system ratherthan the power consumption. The capacitance resolution of the readout is4 aF at 10 kHz and the system resolution is 14 bits.A more recent open-loop SC based MEMS capacitive readout can befound in [102]. In this paper, only the capacitance-to-voltage converter isshown. The authors use a very interesting approach where lateral-BJT de-vices are used as input differential pair. It is due to the fact that BJT showsmuch better noise performance compared to CMOS technology. To furtherreduce the low-frequency noise and offset of the readout, CS technique isapplied. The readout circuit shows very good noise performance (sub µgacceleration noise floor near DC).The last DT interface circuit that will be discussed is an open-loop typereadout that uses Σ∆ ADC topology. This type of readout circuit offersdirect capacitance-to-digital conversion. Due to the popularity of digitalsignal processing (DSP), and the fact that the world has become digitaleverywhere, it is often convenient to have the natural signal (analog) to bequickly converted into digital forms.There are many different types of ADC, where Σ∆ ADC is categorizedas an oversampling converter. Oversampling means that the output datarate is deliberately set to be much higher than the signal bandwidth (BW).Generally speaking, the input BW of a MEMS capacitive sensor is quite low,252.3. Classic Low-Frequency Noise/Offset Reduction Circuit TechniquesFigure 2.9: Block diagram of a first-order Σ∆ modulator.which makes it even easier to implement the ADC.The simplest form of a Σ∆ ADC (first-order) in block diagram is shownin Fig. 2.9 [75]. The converter consists of a negative feedback path witha DAC, a forward path with an integrator and an ADC. The ADC in theforward path can be a 1-bit quantizer (comparator).The main advantage of using an oversampling converter is that it pro-vides noise shaping and really suppresses the quantization noise. At thesame time, it relaxes the specification requirements for the analog front endcircuitries. For more detailed analysis on Σ∆ ADC, including its theory ofoperation and noise shaping discussion, please refer to [75].The Σ∆ topology is especially well suited for the readout of capacitivesensors, as it directly translates the capacitance variation into a series of dig-ital signal. This concept was originally proposed in [76], and the schematicof the readout is shown in Fig. 2.10. It can be seen that the first-order Σ∆ADC has the capacitive sensor element as the sampling capacitors, togetherwith an op amp with a feedback capacitor Ci, forms an integrator. Theoutput of the integrator feeds into a comparator (1-bit ADC), and the final262.3. Classic Low-Frequency Noise/Offset Reduction Circuit TechniquesFigure 2.10: A first-order Σ∆ ADC for direct capacitance-to-digital conver-sion [48].output is also used in the system feedback path (1-bit DAC). This circuitis essentially a first-order Σ∆ ADC, as described in Fig. 2.10. The out-put of the Σ∆ ADC is a pulse width modulated (PWM) signal, and oncethe output bit stream is filtered, the sensor information can be retrieved.Some of the more recent oversampled Σ∆ modulation-based sensor inter-faces are discussed in [77–81]. Additionally, there are other interesting directcapacitance-to-digital converters such as capacitance-to-frequency converter[82], and capacitance-to-pulse-duration interfaces [83, 84].Continuous-Time Based InterfaceAs mentioned earlier, a CT-based capacitive interface circuit exhibits betternoise performance due to the absence of switch noise and noise folding ascompared with its DT counterparts. A CT-based readout generally uses CSto reduce offset and 1/f noise. A classical CT interface can be found in [90].272.3. Classic Low-Frequency Noise/Offset Reduction Circuit TechniquesFigure 2.11: An example architecture of a CT-based capacitive readoutcircuit [91].A more recent CT readout can be found in [91]. The typical architecture of aCT-based interface circuit consists of a modulator that modulates the inputsignal to higher frequency, an amplifier that produces voltage output thatis proportional to input capacitance variation, a demodulator that bringsthe signal to the baseband, and a LPF that filters out high frequency noise.The overall sensing architecture demonstrated in [91] is shown in Fig. 2.11.The noise performance of these CT-based circuits are all very good (around50 µg).28Chapter 3A Parasitic-InsensitiveChopper-Stabilized CMOSReadout Circuit with SensorMismatch Cancellation forCapacitiveMicro-AccelerometersThis chapter presents the theory, design and measurement results of a switched-capacitor (SC) CMOS readout circuit for a capacitive single-axis micro-accelerometer. The CMOS and micro-electromechanical-system-based (MEMS-based) devices are integrated in a single package forming a system-in-a-package (SiP). The interface front-end provides cancellation of DC offsetcaused by parasitic capacitances (e.g., due to bond-pads, interconnects be-tween MEMS and electronic interface, capacitors themselves and sensor mis-29Chapter 3. A Parasitic-Insensitive Chopper-Stabilized CMOS Readout Circuit. . .match). Additionally, the readout circuit utilizes chopper stabilization (CS)technique to reduce DC offset and low-frequency noise associated with theop amps [96]. The measured sensitivity of the accelerometer is 144 mV/g.The SiP achieves 3.9 µg/√Hz acceleration noise floor and 0.05 aF/√Hzcapacitance noise floor at 500 Hz while consuming 4 mW from a single 5-Vsupply.The major contribution of the designed MEMS interface circuit is itsability to virtually remove the adverse effects of parasitic capacitances andsensor mismatches. The basic concept of the technique was first introducedin [2] and [85]. In [85], the parasitic-insensitive technique was discussedand implemented on a CMOS integrator, whereas in [2], it was applied to afully differential MEMS accelerometer. This chapter extends and providessimulation results and experimental verification of the proposed approachas well as more design insights in comparison to [2]. We also provide anoverview of the fabricated SOI MUMPS micro-accelerometer and a moredetailed analysis of the SC charge-transfer front-end.In the literature, [86] also discusses a parasitic-insensitive readout cir-cuit that interfaces with a MEMS gyroscope. The circuit architecture issimilar to [2] in terms of switch placement. A minor difference between thetwo readout circuits is that the sampling capacitors in [86] are being resetinitially. Moreover, the gyroscope in [86] is a single-ended device. Anotherparasitic cancellation technique can be found in [87], where the authorspresent a digital technique for capacitive sensors to calibrates non-idealitiessuch as parasitics in the calibration phase and cancel the adverse effects inthe measurement phase.303.1. Overview: Micro-AccelerometerThe chapter is broken down as follows: the micro-accelerometer is overviewedin Section 3.1, where both the physical structure and its electrical modelare described. Section 3.2 discusses two non-idealities, i.e., parasitic ca-pacitances and sensor capacitances mismatch that affect the DC level ofoutput voltage signal. Section 3.3 describes the CS circuit implementationof the proposed charge-transfer amplifier, which is insensitive to parasiticcapacitances and sensor capacitances mismatch. Experimental results arepresented in Section 3.4, followed by a presentation of concluding remarksin Section 3.5.3.1 Overview: Micro-AccelerometerThe designed MEMS accelerometer in this work is implemented in the SOIMUMPs technology (25 µm silicon thickness) [88]. The technology allowstwo device thicknesses: 25 µm and 10 µm. The substrate of the device isback etched to form a trench, thus eliminating the need for employing holes.This aspect of the technology is beneficial, as it adds to the proof massrequired for highly sensitive acceleration measurements.Design and modelling of the accelerometer is carried out in Coventor-Ware design environment. A proof mass is suspended using folded beamsto reduce the mechanical nonlinearity and axial loading limitation of sin-gle fixed-guided beams. Four distinct sets of gap varying combs are used,which can be used for actuation and sensing. The minimum gap possiblein SOIMUMPs technology is 2 µm, and the current design uses a gap of3 µm. Simulated result of the exaggerated 0x mode (first resonant mode313.1. Overview: Micro-Accelerometerxz yFigure 3.1: The simulated result of 0x mode of the micro-accelerometer inCoventorWare.V+V-Sense NodeCS+ = C0+ + ΔC+CS- = C0- - ΔC-Proof Mass&(a) (b)Figure 3.2: (a) A photograph of the fabricated capacitive micro-accelerometer under test; (b) Equivalent electrical model.in x-y plane in the x direction) of the resonator is shown in Fig. 3.1. Theimage is exaggerated (fingers shifted to the right) to show that even withlarge displacements, there are no cross axis displacements.A micrograph of the actual fabricated device (obtained from Polytec323.1. Overview: Micro-AccelerometerMSA-500 microsystem analyzer) is shown in Fig. 3.2(a).The mechano-electricalinterface can be modelled as a pair of differential capacitors Cs− and Cs+as shown in Fig. 3.2(b), where Cs− = C0− −∆C− and Cs+ = C0+ + ∆C+.Note that C0− and C0+ are the fixed (nominal) capacitances when the ac-celerometer is at rest. Ideally, they should be equal, however, these fixedcapacitances generally have a mismatch from practical fabrication proce-dures. The change in sensor capacitance (∆C−,+) is generated differentiallythrough the displacement x, which is caused by acceleration. For this gapvarying type of sensor, we have:C0−,+ =N0rAold0−,+(3.1)Cs−,+ =N0rAold0−,+ ± x= C0−,+(11± xd0−,+)(3.2)where N is the total number of parallel capacitors realized through the fin-gers, 0 is the permittivity of vacuum, r is the relative permittivity, Aol isthe overlapping area between each finger, and d0+,− is the nominal gap be-tween each finger. Assuming x d0+,− (which is a reasonable assumption,in particular for low-g acceleration), one can show that:∆C−,+ = C0−,+( xd0−,+1± xd0−,+)(3.3)To characterize the MEMS device optically, a Polytec MSA-500 mi-crosystem analyzer is used. This state-of-the-art equipment combines laserDoppler vibrometry for out-of-plane displacements measurements and video333.2. Overview of Parasitics and MismatchesTable 3.1: Design Parameters of the AccelerometerProof mass dimensions 1.8mm x 0.4mm x 25µmProof mass 59.1 µ gramOverlap area of each finger 540 µm2Capacitive gap 3 µmPull-in voltage 7.58 VSensitivity (differential) 13 fF/gResonant frequency 2.8 kHzBrownian noise floor 0.6 µg/√Hzstroboscopy for in-plane dynamics measurements. In the latter case, theequipment can detect device motions down to 2 nm resolution. From opti-cal characterization, the important design parameters of the SOI MUMPSmicro-accelerometer are listed in Table 3.1. Note that the pull-in voltageis the amount of voltage applied across the fingers such that the generatedelectrostatic force overcomes the spring force and as the result, would leadto fingers snapping together.3.2 Overview of Parasitics and MismatchesFig. 3.3 shows a simple structure of a SC charge-transfer readout front-end with the presence of parasitic capacitances Cp1, Cp2, and Cp3, whichrepresent the total parasitics at the corresponding nodes. Note that theMEMS capacitive sensor (mechanical part) is shown in the shaded area.Assuming the sensor is a micro-accelerometer, the function of the readoutcircuit is to detect the change in sensor capacitances due to an applied force343.2. Overview of Parasitics and MismatchesVoCiVDDVrefΦ2Φ2Φ1Φ1GndMEMS SensorGndCP1CP2CS+ = C0+ + ΔC+GndCS- = C0- - ΔC-Φ2Φ1nT nT + T/2 * Vref = VDD / 2Φ1CP3Figure 3.3: A simple SC charge-transfer MEMS capacitive readout circuit.The MEMS sensor is shown in the shaded area. The parasitic capacitances,i.e., Cp1, Cp2, and Cp3, are also shown in the figure.(or acceleration), and translate such capacitance variation into an outputvoltage. The operation of the circuit shown in Fig. 3.3 is as follows: duringφ1, the sense capacitances Cs+ and Cs− are charged to (VDD − Vref ) and−Vref , respectively, while the charge-transfering feedback capacitor Ci isdischarged to zero. Simultaneously, the parasitic capacitor Cp1 is chargedto VDD, while Cp2 is discharged. Note that the parasitic capacitor Cp3 (dueto parasitic capacitances associated with the node connected to the proofmass of the sensor) is immaterial in the overall transfer function because itis always charged to the reference voltage Vref (AC ground), i.e., VDD/2.When φ2 goes high, the sum of the charges stored in the aforementionedcapacitors are transferred to Ci and a new output is generated. Assumingthe open-loop gain of the operational amplifier (op amp) is large, the outputcan be expressed as:353.3. Circuit ImplementationVo =VDD2(1 +∆Cp − CMM −∆CTCi)(3.4)where ∆Cp is the difference between the two parasitics (∆Cp = Cp2 −Cp1).Additionally, CMM accounts for the sensor mismatch and is equal to thedifference between the two nominal capacitances (CMM = C0+ − C0−). Fi-nally, ∆CT = ∆C+ + ∆C−. As it can be seen from (3.4), the DC level ofthe resulting output is influenced by the parasitic ∆Cp and the sensor mis-match CMM , which would affect the maximum output swing of the readout,leading to less dynamic range.Generally speaking, the parasitic capacitances can be reduced effectivelyby minimizing the length of the interconnections, or by introducing individ-ual shielding for the sensor leads. Moreover, in some approaches, such as[91], one can reduce the sensitivity to parasitic capacitances by increasingthe gain of the op amps. Nevertheless, it is beneficial to design a circuitthat removes or minimizes the adverse effects of the parasitic capacitances.Such a circuit is discussed in the following section.3.3 Circuit ImplementationThe overall building blocks of the CMOS MEMS SiP and its required sig-nals are demonstrated in Fig. 3.4. The CS charge-transfer amplifier circuit isdirectly connected to the micro-accelerometer via bond wires. The charge-transfer amplifier circuit converts the sense capacitance variation (changingcharge) to an amplified output voltage where the peak-to-peak voltage am-plitude represents the displacement of the proof mass. This output signal363.3. Circuit ImplementationClock Generator (Agilent 81200)Single-Axis Capacitive AccelerometerCharge Transfer AmplifierS/H StageLow-Noise CMOS Interface ICSiPTuning VoltageFigure 3.4: Overall system architecture of the implemented CMOS MEMSSiP.enters a sampled and hold (S/H) stage which produces a smoother enve-lope detected signal. The externally applied tuning voltage is used to cancelthe DC offset caused by sensor capacitance mismatch. The required clocksignals are generated by an Agilent 81200 clock module. In the followingsubsections, each of the building blocks of the proposed CMOS interface ICis described in more detail.3.3.1 Charge-Transfer AmplifierTo improve the sensitivity of the capacitive readout circuit, the parasiticsand mismatches introduced in Section 3.2 should be carefully dealt with.The proposed parasitic insensitive circuit was originally presented in [2]. Inthis work, it is expanded, implemented, and measured. The interface circuitshown in single-ended configuration is illustrated in Fig. 3.5 to first explainthe parasitic-insensitive technique. The overall differential readout circuitwith CS will be shown after.The purpose of the circuit in Fig. 3.5 is to eliminate the DC offset that the373.3. Circuit ImplementationVoutCiVDDVrefΦ2Φ1Φ1Φ1Φ1GndΦ2Φ1Φ1Φ2VrefΦ2VrefCS+ = C0+ + ΔC+CS- = C0- - ΔC-MEMS SensorCP1CP2VrefΦ2Φ1CCMVtunenTnT + T/2 Φ1CHΦ2VrefS/H StageFigure 3.5: The schematic of the proposed capacitive readout circuit thatconsists of a parasitic-insensitive charge-transfer amplifier with sensor mis-match cancellation and a S/H stage.parasitics and mismatches create in (3.4). During the φ1 phase, similar tothe circuit in Fig. 3.3, Cs+ and Cs− are charged to (VDD/2) and (−VDD/2),respectively, while the integration capacitor Ci is discharged. The parasiticcapacitances Cp1 and Cp2, in this case, are connected to AC ground inboth clock phases, therefore, they are always discharged. Therefore, theseparasitic capacitances will not influence the transfer function. The capacitorCCM is used to store the correct charges to cancel DC offset due to mismatch(common-mode adjustment) and has the following charge (QCM ) in thisclock phase:QCM =(VDD2− Vtune)CCM (3.5)Note that the amount of charge stored on CCM can be adjusted by varyingVtune.When φ2 goes high, Cs+ and Cs− are discharged because their terminals383.3. Circuit Implementationare either connected to a DC source or virtual ground. The sum of thecharges stored in φ1 are transferred to Ci and a new output is formed:Vout =VDD2+QCMCi+VDD[CMM + ∆CT ]2Ci(3.6)Note that the parasitic capacitances Cp1 and Cp2 play no role in the transferfunction because they always remain discharged after settling.If the following condition is fulfilled by adjusting Vtune,QCMCi+VDDCMM2Ci= 0 (3.7)then the DC offset caused by sensor mismatch can be ideally eliminated,which would allow the circuit to operate at an optimal DC level. Also notethat dummy switches are used in the charge-transfer amplifier to reducethe effects of charge injection [89]. It is important to mention that in thisproof-of-concept prototype, the external adjustable signal Vtune is controlledmanually. Such signal can certainly be varied automatically by other moresophisticated implementation, but it is out of the scope of this work.To improve the noise performance of the system, chopper stabilization(CS) technique is also incorporated in the proposed parasitic-insensitivereadout circuit to further reduce low-frequency imperfections associated withthe op amp, i.e., offset and low-frequency noise. The exact differential struc-ture of the overall readout circuit is shown in Fig. 3.6 with the key clocksignals displayed in Fig. 3.7. Note that due to the use of CS technique,the sampling clock is divided into two phases: φ1a and φ1b as shown in Fig.3.6. During consecutive φ1a and φ1b phases, the input capacitor structure393.3. Circuit ImplementationCACS+CS-Φ2Φ1aΦ1aΦ2VDDDifferential Variable Sense CapacitorsΦ2aCharge Transfer Amplifier Φ1a + Φ1bΦ1bΦ1bChopper SwitchesCSVrefVDDVrefVrefVref✴ Vref = 0.5 × VDDCHCHVrefΦ2bS/H StageVout+Vout-Φ1a + Φ1bΦ1a + Φ1bΦ2Φ2CCMVrefΦ1aΦ1bVtune1Vtune2Cp1Cp2VoFigure 3.6: A CS parasitic-insensitive charge-transfer MEMS capacitivereadout circuit with sensor mismatch cancellation. The S/H stage acts as ademodulator and produces a smoother signal at the output.is alternately charged with opposite voltage polarity. During φ1a, CS+ ischarged to VDD/2, and CS− is charged to -VDD/2. During the followingφ1b, CS+ is charged to -VDD/2, and CS− is charged to VDD/2. Such oper-ation generates an amplitude modulated (AM) signal at the output of thecharge-transfer amplifier (during φ2), where the peak-to-peak amplitude isproportional to the difference in the sensor capacitors [97]. Also, note thatthe op amp input offset and the flicker noise primarily affect the DC voltagelevel of the output, but not the amplitude of the AC signal. Therefore, theaforementioned low-frequency non-idealities can be removed after the out-put is demodulated differentially. It can be shown that the final output Vout(differential output after S/H) can be expressed as:Vout = Vout+ − Vout− = VDD(CS+ − CS−Ci)(3.8)403.3. Circuit ImplementationΦ1bΦ2SampleΦ2a AmplifyΦ1aSampleΦ2b Clock WaveformsS/HS/HFigure 3.7: The clock waveforms for the CMOS readout as shown in Fig. 3.6.3.3.2 S/H StageThe output of the charge-transfer amplifier is fed to the S/H stage, which isimplemented by two simple op amps with negative feedback configurationas shown in Fig. 3.6. The S/H stage is meant to smooth out the higherfrequency modulated signal from the charge-transfer amplifier.Note that to reduce the adverse effects of charge injection in the S/Hcircuit, transmission-gate switches are used at the non-inverting input ofthe op amps. Furthermore, special attention has been paid to sizing of theNMOS and PMOS of the switch such that their charge injection almostcancel each other, which in turn results in a low overall charge injectionerror.Simulated transient response (differential S/H output) of the parasitic-insensitive readout circuit having different values for parasitics (Cp1 andCp2) is shown in Fig. 3.8. As it can be seen in the figure, the DC voltagelevel of the output is not affected and stays at 0 V.413.3. Circuit ImplementationFigure 3.8: Simulation result showing that the DC voltage level at the out-put of the readout circuit is not affected by different values of parasiticcapacitances.3.3.3 Operational AmplifierThe op amps that are used in all of the building blocks of the sensor interfacecircuit utilize the folded-cascode topology as shown in Fig. 3.9. Each opamp has a gain of 72.15 dB, a phase margin of 60◦, and a gain-bandwidthof 116.5 MHz at 500 fF load. Since the frequency of the variations in thesense capacitance are generally low for an accelerometer, minimization ofthe flicker noise is very important. The input-referred voltage flicker noisepower spectral density (PSD) of the folded-cascode op amp is [89]:v2n,f∆f=2Coxf[KFp(WL)1+KFn(WL)3g2m3g2m1+KFp(WL)9g2m9g2m1](3.9)where gmi is the transconductance of MOS transistor Mi, f is the frequencyof operation of the circuit, Wi and Li are the channel width and length of423.3. Circuit ImplementationVDDV-V+OutputM1M2M3M4M5M6M7M8M9M10Mb1Mb2Mb3Mb4Bias Circuit Single-ended Folded Cascode Operational AmplifierGndIREFVbiasFigure 3.9: The schematic of the folded-cascode op amp designed to mini-mize both thermal and flicker noise.transistor Mi, Cox is the gate oxide capacitance per unit area, and KFpand KFn are the flicker noise coefficients of PMOS and NMOS transistors,respectively. In this design, PMOS input differential pair is chosen becauseof its lower flicker noise coefficient. The input pair is also made large tofurther reduce flicker noise.Other than the flicker noise, the reduction of thermal noise is also takeninto account. The input referred thermal noise power can be expressed as[89]:v2n,thermal∆f≈ 2(4kT23gm1)(1 +gm3gm1+gm9gm1)(3.10)433.3. Circuit ImplementationTable 3.2: Device Sizing of the Op AmpTransistor Width LengthM1 100 µm 0.8 µmM3 21.4 µm 0.8 µmM5 10.2 µm 1.6 µmM7 10.2 µm 5.2 µmM9 10.2 µm 5.2 µmMb1 100 µm 0.8 µmMb2 21.4 µm 0.8 µmMb3 10.2 µm 1.6 µmMb4 10.2 µm 5.2 µmSince the input pair is made large, gm1 is large (gm ∝ W ), thus reducingthe thermal noise of the op amp. Another benefit of having large gm forthe input pair is that it increases the gain of the op amp. The trade-off ofhaving a large input pair would be the reduction of the bandwidth due to thelarger input capacitances. Fortunately, for this particular application wherethe input frequency is extremely low, the lower bandwidth is not a concern.The sizing of the transistors of the op amp is presented in Table 3.2. Notethat the reference DC current IREF is 12.5 µA.3.3.4 Closed-Loop Noise and Offset ConsiderationFrom the previous subsection, the total input-referred noise of the op ampis essentially:v2n,total∆f=v2n,f∆f+v2n,thermal∆f(3.11)443.3. Circuit ImplementationSince the sensing application operates at low frequency, flicker noise is thedominant noise, and thermal noise can be neglected for this analysis.Based on the readout circuit shown in Fig. 3.6, the total noise at theoutput (Vout+), can be expressed as:v2out ≈ v2n,f(1 +2C0Ci)2+ v2n,f (3.12)The total noise at the negative terminal (Vout−) has the same expressionas (3.12). Since flicker noise mainly affects the DC level at the output,the flicker noise has minimal effect on the differential final output (Vout+ -Vout−).Furthermore, note that C0 is the nominal capacitance when sensor is atrest. As it can be seen from (3.12), if the 2C0 is a small fraction of thefeedback capacitor Ci, the output noise can be reduced. However, since theoverall sensitivity (gain) of the readout circuit is inversely proportional to Ci,this feedback capacitance cannot be too large. Thus, for sizing the feedbackcapacitor Ci, there is a trade-off between noise and circuit sensitivity. Also,note that as discussed in Section 3.3.3, it is beneficial to keep the thermalnoise contribution v2n,thermal low based on (3.10).In terms of offset, the total offset that will appear at the positive terminalof the output (Vout+) can be expressed as:Vout,os ≈ Vos(1 +2C0Ci)+ Vos (3.13)where Vos is the input-referred offset of the op amp. The offset showing atthe negative terminal of the output has the same expression as (3.13) and453.4. Experimental Results+MEMSCMOSLid openedFigure 3.10: The S-i-P (CMOS and MEMS accelerometer integrated in apackage) is mounted on a PCB for testing.the differential final output will have no offset contribution (assuming thetwo S/H op amps are matched perfectly).3.4 Experimental Results3.4.1 ImplementationThe CMOS readout and the MEMS accelerometer are fabricated in Dalsa’s0.8 µm CMOS process and SOI MUMPS, respectively. The two chips areput into a single package to minimize parasitics. An image of the system-in-a-package (SiP) mounted on a PCB is shown in Fig. 3.10. The circuitdissipates about 4 mW from a single 5-V supply.463.4. Experimental ResultsVoutCiVDDVrefΦ2Φ1Φ1Φ1Φ1GndΦ2Φ1Φ1VrefΦ2VrefΦ2VrefMEMS Sensorsensing combssensing combsactuating combsVb2Vb1actuating combsCS+CS-CS+CS-Proof MassFigure 3.11: The test set up of CMOS MEMS S-i-P in simplified schematicform using electrostatic force testing.3.4.2 Electrostatic Force TestingIn the absence of a shaker table, the external accelerations are mimickedusing equivalent electrostatic forces, applied on a separate set of comb drives.The set up in simplified schematic form is illustrated in Fig. 3.11. Theaccelerometer dynamics can be modelled as:md2xdt2+Dxdxdt+ kx = Fel (3.14)where x is the displacement, m is the mass of the proof mass, Dx is thedamping coefficient, and k is the spring constant. Fel denotes the electro-static force and can be expressed as:Fel =0A2(d0 − x)V 2b (3.15)473.4. Experimental Resultswhere Vb is the actuation voltage across the plates. Note that only oneparallel plate capacitor is being considered in (3.15), i.e., one finger of themulti-finger structure.By applying AC voltages (Vb1 and Vb2) to the differential actuatingcombs, the sensor is put into motion due to the corresponding electrostaticforce, and the readout circuit outputs a voltage wave following the force(acceleration). If Vb2 = −Vb1 = Vb = VB sin(wt), Fel can be linearized asfollows (assuming x  d0):Fel = Fel2 − Fel1 =0A2d20[(Vb2 − Vref )2 − (Vref − Vb1)2]= −0Ad202VrefVb (3.16)Note that the frequency of Fel is identical to the frequency of Vb (i.e., w),therefore, the generated capacitance variation ∆C would also vary at w.This would be an issue if there is a signal feed through from the actuatingvoltages Vb to the output of the readout circuit. Such signal would have thesame frequency of w, and therefore, the signal of interest ∆C (acceleration),cannot be differentiated from the feed-through signal.The source of this feed-through can be explained as follows: when clockphase φ2 is on, there is a path from Vb1 and Vb2 to the op amp. Therefore,the output of the first stage of the readout front-end, which is providedbelow, would have some components from Vb2 and Vb1:483.4. Experimental ResultsVout,partial(s) =−Vb2(s)CS+Ci−Vb1(s)CS−Ci(3.17)If CS+ and CS− are equal, Vout,partial would be 0, and there would be no feedthrough. However, in practice, there will be mismatches in the fabricateddevice, which results in a portion of signal from Vb to feed through to theoutput of the charge-transfer amplifier. Since both the signal of interest andthe coupled signal vary at the same frequency, it is not possible to separatethem in the frequency domain. Note that this feed-through signal only existswhen electrostatic force testing is utilized.This problem can be solved if the AC actuating voltage Vb is applied toonly one side of the actuating combs, while the other side is kept at a DCvoltage (Vref ). The resulting force to displacement relationship would be:md2xdt2+Dxdxdt+(k −0Ad30V 2b)x = Fel =0A2d20V 2b (3.18)The electrostatic force can be further expanded to:Fel =0A2d20V 2B(1− cos(2wt)2)(3.19)It can be seen from (3.19) that the force has a frequency of 2w, which meansthe displacement and the eventual capacitance variation caused by it wouldalso have a frequency of 2w. Meanwhile, the signal that is coupled from theactuating voltage Vb is at the frequency of w; thus, the signal of interest canbe separated from the feed-through signal (in the frequency domain).The test set up is shown in Fig. 3.12. The sensitivity of the readout cir-493.4. Experimental ResultsS-i-PActuating Voltage GeneratorSpectrum AnalyzerClock GeneratorFigure 3.12: The actual test set up to obtain measurements for the S-i-Pwith each equipment identified.cuit is measured using electrostatic forces. The amplitude of the actuatingvoltage is varied from 2.5 V to 6.5 V, producing the corresponding electro-static force according to (3.19). It should be noted that, in order to measurethe sensitivity, the actuating frequency is kept at 50 Hz (close to DC). Notethat the applied actuating voltage needs to be under 7.58 V, which is thepull-in voltage of the accelerometer (Table 3.1). Since the actuating voltageis known, the electrostatic equivalent acceleration can be calculated as ael= Fel/m. The measured acceleration to the output voltage relationship isplotted in Fig. 3.13. The probe connected to the output has a 10× atten-uation, and thus the circuit exhibits a sensitivity of 144 mV/g. Moreover,the device is tilted vertically for the steady-state measurement of ±1g. At+1 g, the output voltage is at ∼2.65 V, whereas at -1 g, the output voltageis at ∼2.35 V.503.4. Experimental Results0 0.2 0.4 0.6 0.8 1 1.2 1.40510152025Electrostatic Equivalent Acceleration (mg)  Charge−Transfer Amplifier Output (µV)Measured DataLinear FitElectrostatic Equivalent l ration (mg)Readout Output Voltage (μV)482160Figure 3.13: The relationship between electrostatic equivalent acceleration(ael) in terms of g to the sensor output voltage. Note that the probe has a10× attenuation.3.4.3 Signal of Interest and Noise FloorThe signal and noise measurements are conducted using a spectrum ana-lyzer from Anritsu MS2034A. As previously mentioned, the signal of inter-est, namely, ∆C (or equivalently, acceleration), can be separated from thefeed-through signal in the frequency domain. The test input acceleration isgenerated by an electrostatic force that is produced through an actuatingAC voltage. The AC voltage has an amplitude of 6.5 V and is varying at250 Hz. Therefore, the electrostatic equivalent acceleration would have anamplitude of 1.2 mg with a frequency of 500 Hz. Fig. 3.14 shows the outputspectrum with the aforementioned input acceleration. It can be seen that513.4. Experimental ResultsActuating voltage amplitude = 6.5 VElectrostatic acceleration amplitude = 1.2 mg Noise floor = 3.9 µg/√Hz @ 500 Hz input acceleration➜ 0.85 mg (rms)Figure 3.14: The spectra of the S-i-P output under sinusoidal input accel-eration of 1.2 mg at 500 Hz (RBW = VBW = 1 Hz).the output noise power spectral density is 50 dBm below the signal levelat about −115 dBm, which corresponds to an acceleration noise floor of3.9 µg/√Hz and a capacitance noise floor of 0.05 aF/√Hz.3.4.4 Electrostatic Spring SofteningThe electrostatic spring-softening phenomenon was also observed. Equa-tion (3.18) shows that the overall spring constant under the influence ofelectrostatic force is:koverall = k −0Ad30V 2b (3.20)Since the resonant frequency of the accelerometer is equal to√koverall/m,523.4. Experimental Results0.5 1 1.5 2 2.5 3 3.5 4 4.5−85−80−75−70−65−60−55−50−45Frequency of Appled Electrostatic Force (kHz) Sensor Output Spectrum (dBm)  VB = 2.5 VVB = 5 VFigure 3.15: The effect of electrostatic spring softening is demonstratedhere: when the actuating voltage increases from 2.5 V to 5 V, the resonantfrequency of the accelerometer decreases.if the amplitude of Vb (denoted as VB) is increased, the resonant frequencyshould decrease. This effect is measured and shown in Fig. 3.15.3.4.5 Device Performance SummaryThe measured performance parameters are summarized in Table 3.3. Thekey parameters of interest are the acceleration noise floor and the powerconsumption as the noise floor sets the minimum acceleration that the sys-tem can sense, and the power optimization is always important, particularlyfor portable designs.Note that the low acceleration noise floor of this work is a result of careful533.4. Experimental ResultsTable 3.3: Performance SummaryParameter This WorkSensitivity (mV/g) 144Acceleration noise floor (µg/√Hz) 3.9Capacitive noise floor (aF/√Hz) 0.05Freq. where noise is measured (Hz) 500Technology (µm) 0.8Supply (V) 5Power (mW) 4design of both MEMS sensor and the sensor readout circuit. Special carehas been paid to minimize the noise of the readout circuit and its input-referred capacitance noise floor (measured in aF/√Hz). Also, the sensoris designed to have a high capacitance to acceleration ratio (measured incapacitance per g). The input-referred capacitance noise floor of the designis 0.05 aF/√Hz. The high capacitance to acceleration ratio of 13 fF/gcontributes to the low overall input-referred acceleration noise. The highcapacitance to acceleration ratio of the sensor originates from the thick proofmass of the device. For instance, the proof mass of the sensor used in thiswork is 59.1 µgm, as opposed to the 0.932 µgm proof mass reported in [91].The size of the proof mass is also an important factor in MEMS sensordesign, as the capacitance to acceleration ratio increases with the devicethickness, and furthermore, smaller gaps between the comb fingers increasethe net capacitance. The accelerometer used here uses a device thickness of25 µm, which is relatively large compared to that of the comparable designs.We have measured 4 different chips and chip to chip performance variationis within ±2%.543.5. Chapter 3 Conclusion3.5 Chapter 3 ConclusionA switched-capacitor charge-transfer interface circuit with DC-offset cancel-lation for MEMS capacitive micro-accelerometers is presented. It is shownthat the proposed circuit is insensitive to parasitic capacitances as well assensor mismatches. Additionally, the readout circuit utilizes CS to furtherreduce op amp offset and low-frequency noise. The CMOS readout and themicro-accelerometer are integrated in a package for testing. The electro-static force testing methodology is utilized. The measured acceleration andcapacitance noise floor for the readout are 3.9 µg/√Hz and 0.05 aF/√Hz atinput frequency of 500 Hz, respectively. The sampling clock runs at 10 kHzand the SiP consumes 4 mW.55Chapter 4A Low-NoiseChopper-StabilizedCapacitive-Sensor ReadoutCircuit UsingCorrelated-Level-ShiftingTechniqueVarious MEMS capacitive sensing interface circuits have been designed inboth academia and industry in which two particular circuit design techniqueshave been widely used, namely, chopper stabilization (CS) and correlateddouble sampling (CDS) [96]. As discussed in Chapter 2.3, the main purposeof both techniques is to minimize low-frequency imperfections such as DCoffset of the op amp and its flicker (1/f) noise. For CS, the low-frequencyinput signal is first modulated to a higher frequency where the effect of flicker56Chapter 4. A Low-Noise Chopper-Stabilized Capacitive-Sensor Readout Circuit. . .(1/f) noise is negligible (as compared to the thermal noise). The signal isprocessed and is demodulated back to the baseband after amplification, andis then filtered to attenuate the out of band noise. In terms of CDS, typicallythe circuit uses two phase clocking where the op amp DC offset and low-frequency noise are sampled in one phase, and their effects are subtractedin the next phase.In this chapter, a CMOS capacitive readout circuit for low-power MEMSinertial sensing applications is proposed to improve the overall accuracyand power consumption of the sensory system by incorporating a recentlyintroduced switched-capacitor (SC) technique called correlated level shifting(CLS) in conjunction with CS. CLS is used to reduce errors from finite opamp gain while introducing negligible kT/C noise [98]. Given the same opamp performance, a circuit with CLS is able to achieve a higher accuracyand lower power consumption compared to those without CLS. Comparedto CDS, which is commonly used in capacitive-sensor readouts, e.g., [93],an extra clock phase is required for CLS. However, for many sensor readoutapplications, where the speed that the circuit operates at is not very high(e.g., in kHz range), the extra clock phase would not cause a significant speeddisadvantage. Moreover, it is demonstrated that CLS has significantly betternoise performance than CDS at higher frequency. However, CDS does cancelvery low-frequency noise and offset, whereas CLS does not [98]. Therefore,the CS technique is also incorporated to implement the capacitive-sensorfront-end to not only reduce op amp errors due to its finite gain, but alsocancel the aforementioned very low-frequency imperfections. Note that theconcept of using CLS in conjunction with CS was first introduced in [99],574.1. Overview of CLS Operationwhere it was applied to a ∆Σ analog-to-digital converter (ADC). In thiswork, these two techniques are combined for a sensor readout circuit, andmoreover, the circuit structures used in [99] and this work are inherentlydifferent.In order to verify the functionality of the readout circuit, in this work,the capacitive sensor is physically emulated by a pair of on-chip differentialvariable capacitors that are in the femto Farads range. The proposed front-end is designed in a 0.8 µm CMOS technology, and consumes 290 µW froma single 5V supply. The readout circuit achieves a capacitance noise floor of0.018 aF/√Hz at 400 Hz with a sensitivity of 50 mV/fF.This chapter is organized as follows: an overview of CLS operation isdescribed in Section 4.1, then the readout operation and non-idealities arediscussed in Section 4.2, which shows the benefits of the proposed architec-ture. In Section 4.3, the readout circuit architecture and op amp structureare described in detail. Measurement results are presented in Section 4.4and concluding remarks are provided in Section 4.5.4.1 Overview of CLS OperationCLS is a powerful SC technique that is intended to significantly reduce errorsintroduced by the finite op amp gain, thereby improving the overall accuracyof the circuit. The basic idea behind the error reduction phenomenon canbe illustrated in Fig. 4.1 (a) and (b). Fig. 4.1 (a) shows an op amp used inan arbitrary feedback loop without CLS. The virtual ground error voltage(Verror) can be approximated to be −Vo/A, where Vo is the op amp output584.1. Overview of CLS OperationFigure 4.1: CLS virtual ground error voltage reduction analysis: (a) op ampcircuit without CLS and (b) op amp circuit with CLS.voltage shown in the Figure and A is the open-loop DC gain of the op amp.Traditionally, the error voltage Verror can be made smaller by making theop amp gain large, however, this would consume more power. Alternatively,the error can be reduced by making the voltage at the output of the op ampsmaller. This is exactly what CLS does. As shown in Fig. 4.1 (b), with theCLS technique used (having a level shifting capacitor CCLS), at the criticalphase, the error voltage Verror is reduced because the output of the op ampis Vo − Vx. This indicates that the virtual ground error has become:Verror ≈ −Vo − VxA(4.1)Equation (4.1) demonstrates that the error voltage Verror can be significantlyreduced by using CLS.A more detailed and mathematical discussion on the operation of the594.1. Overview of CLS OperationFigure 4.2: Operation of correlated level shifting (CLS). Three major clockphases are required for the circuit operation: sample, estimate, and levelshift. Single-ended structure is shown for simplicity.CLS technique is illustrated in Fig. 4.2, where a charge-transfer amplifier(capacitance-to-voltage converter) is used as an example. Note that single-ended circuit structure is used for the purpose of simplicity.As it can be seen in the figure, CLS consists of three clock phases: sample,estimate, and level shift. CS models the MEMS capacitive sensor (for thepurpose of the discussion, this sensor can be treated as a varactor). Thisvariable sensing capacitor can be written as: CS = C0 +∆C where typically∆C  C0. The input to this circuit is the capacitance variation ∆C. InFig. 4.2, CR is the reference capacitor and is equal to C0. CA is the feedbackcapacitor that dictates the sensitivity of the charge-transfer amplifier. CCLSis the capacitor used in CLS to reduce the op amp finite gain error and itspurpose is described in detail in [98]. The output at the end of the estimationphase is:VOUT,E1 =[VDD2+VDD2(∆CCA)](11 + 1K)(4.2)where K is the op amp loop gain during this clock phase, and can be ex-pressed as:604.1. Overview of CLS OperationK =ACACS + C0 + CA≈ACA2C0 + CA(4.3)where A is the DC gain of the op amp. Note that Vref = 0.5VDD.The output of interest happens in the level shifting phase and is denoted asVOUT,LS1, which can be expressed as:VOUT,LS1 =[VDD2+VDD2(∆CCA)](11 + 1KEQ)(4.4)where the equivalent loop gain KEQ is:KEQ =(2 + λ+K1 + λ)K ≈K21 + λ(4.5)where λ represents the effect of finite CLS capacitor CCLS , and can beexpressed as:λ =1CCLS(2C0CA2C0 + CA+ CL)(4.6)Assuming that there is no charge loss in CCLS , i.e., by making CCLS muchlarger compared to the load CL, the equivalent loop gain can be simplified:KEQ = K(2 +K) ≈ K2 (4.7)Equations (4.5) to (4.7) essentially demonstrate that CLS greatly in-creases the effective loop gain of the circuit. Due to this property, designerscan also achieve the same target specifications using less power. Moreover,it can be shown that CLS has a very good noise performance because im-614.2. Readout Operation and Non-IdealitiesCACS+CS-VrefVDD or Gnd Gnd or VDD VrefCCLSSamplingCACS+CS-VrefCCLSEstimateVrefVrefVOUT, ECACS+CS-VrefCCLSLevel ShiftVrefVrefVOUT, LSGndGndCLGndCLGndCLGndVOS+1VOS+1VOS+1Figure 4.3: Operation of the proposed CS + CLS charge-transfer amplifier.Three major clock phases are required for the circuit operation: sample,estimate, and level shift. Note that the op amp offset model is included atthe inverting input.perfections such as thermal noise, charge injection, errors from finite swing,and incomplete settling that are sampled onto CCLS during the estimationphase are reduced by the DC gain during the level shift phase. However, aspreviously mentioned, CLS does not cancel low-frequency noise and offsetat the input of the op amp [98].4.2 Readout Operation and Non-IdealitiesThe operating principle of the proposed CS plus CLS capacitive readout(charge-transfer amplifier) is shown in Fig. 4.3, where the circuit structurein each clock phase is displayed. The sampling clock waveforms are shown inFig. 4.4, where three main clock phases are present: sample, estimate, andlevel shift (ignore φLS,a and φLS,b for now). It is important to note that dueto the CS technique, the sampling clock is divided into two phases: φCa andφCb. During consecutive φCa and φCb sampling clock phases, the input ca-pacitor structure is alternately charged with opposite voltage polarity. That624.2. Readout Operation and Non-IdealitiesFigure 4.4: Clock waveforms governing the operation of the proposed CS +CLS charge-transfer amplifier.is, during φCa, CS+ is charged to VDD−Vref , and CS− is charged to −Vref .During the following φCb, CS+ is charged to −Vref , and CS− is charged toVDD−Vref . Such operation enables the creation of an amplitude modulated(AM) signal at the output of the charge-transfer amplifier, where the peak-to-peak amplitude is proportional to the difference in the sensed (variable)capacitances. Note that the op amp input offset and the flicker noise mainlyinfluence the DC voltage level of the output, but not the amplitude of theAC signal [97]. Therefore, the undesirable effects of such disturbances canbe removed after the output is demodulated differentially. Also, note that,in this work, Vref is equal to half of VDD. The amplifier output at the endof the estimation phase, φe that follows φCa (corresponding to the value ofthe capacitance during φCa), is:VOUT,E,φCa =[VDD2+ Vos(1 +2C0CA)+VDD2(CS+ − CS−CA)](11 + 1K)(4.8)634.2. Readout Operation and Non-IdealitiesSimilarly, the output signal at the end of the estimation phase, φe thatfollows φCb (corresponding to the value of the capacitance during φCb), is:VOUT,E,φCb =[VDD2+ Vos(1 +2C0CA)+VDD2(CS− − CS+CA)](11 + 1K)(4.9)where Vos is the offset of the op amp, CA is the feedback capacitor, CS+ =C0 + ∆C and CS− = C0 −∆C (C0 is the fixed nominal sensor capacitor).Additionally, K is the op amp loop gain during the estimation phase, andcan be written as:K =ACACS+ + CS− + CA=ACA2C0 + CA(4.10)The output signals of interest for the proposed readout circuit are gen-erated at the end of the level-shift phase:VOUT,LS,φCa =[VDD2+ Vos(1 +2C0CA)+VDD2(CS+ − CS−CA)](11 + 1KEQ)(4.11)644.2. Readout Operation and Non-IdealitiesVOUT,LS,φCb =[VDD2+ Vos(1 +2C0CA)+VDD2(CS− − CS+CA)](11 + 1KEQ)(4.12)where the equivalent loop gain, KEQ, is approximately K2 as mentioned in(4.7). Note that this approximation is deduced from the fact that there isnegligible charge loss from CCLS since it is much larger than the load. Asit can be seen, the equivalent loop gain is greatly improved, thus designerscan reduce the gain specification of the op amp. Assuming the bandwidthrequirement of the op amp remains the same, the amount of current neededto operate the circuit can also be reduced, leading to less power consumption.Once the output of the charge-transfer amplifier is demodulated differ-entially, the final output (referred to ground) of the readout circuit can beexpressed as:Vout = VDD2∆CCA(11 + 1KEQ)(4.13)where any offset is canceled because Vout is essentially the difference betweenequations (4.11) and (4.12). It can be seen from (4.13) that the accuracyof the output is closely related to parameter KEQ ≈ K2. Assuming A isfixed and finite, KEQ can be maximized if CA approaches infinity. How-ever, the larger CA is, the less sensitivity (Volts/Farads) the circuit canachieve. Therefore, the designer should take this trade-off into account.Moreover, the nominal sensor capacitor, C0, is application dependent, as654.3. Readout Architecture and Op Amp Structuredifferent sensors have different nominal capacitances. Therefore, one canmake the readout circuit more versatile by having the ability to vary CA,which in turn, would allow the circuit to have different gain settings. Thisway, the interface circuit can be used for a wider range of capacitive sensors.In the proof-of-concept chip implemented in this work, CA is realized as abank of 3 capacitors and can be programmed to be 200, 400, or 600 fF.In terms of noise, similar to the analysis presented in [98], we can derivethat the CLS network adds the following amount of noise to the circuit:V 2n ≈(1 + 2C0CA)2V 2n,opamp +kTCCLSA2(4.14)where Vn,opamp is the op amp noise that is sampled onto CCLS , k is the Boltz-mann constant, and T is the absolute temperature in Kelvins. Equation(4.14) shows the advantage of using CLS (as discussed in [98]): imperfec-tions such as thermal noise, charge injection, errors from finite op amp gain,and incomplete settling that are sampled onto CCLS during the estimationphase are reduced by the DC gain during the level-shift phase.4.3 Readout Architecture and Op Amp StructureThe schematic of the overall CMOS readout circuit and the variable capac-itive element (in the form of bank of capacitors) mimicking the sensor areshown in Fig. 4.5 and Fig. 4.6, respectively. The front-end circuit (Fig. 4.5)is composed of chopping switches, a CLS charge-transfer amplifier, sampleand hold (S/H) buffers that act as a demodulator, and finally an externally664.3. Readout Architecture and Op Amp StructureFigure 4.5: Schematic of the proposed capacitive readout circuit which con-sists of variable capacitors (to mimic the capacitive sensor), switches forchopper stabilization, CLS charge-transfer amplifier, S/H buffers and anexternally connected unity gain differential amplifier (INA 105) for mea-surement purposes.Figure 4.6: Digitally controlled bank of capacitors to mimic the MEMScapacitive sensor.connected unity gain differential amplifier (INA 105) that is used to facili-tate the measurement of the output noise and the output signal. In orderto test the interface circuit, the MEMS capacitive sensor is emulated by apair of on-chip differential variable capacitors CS+ and CS−, where eachCS+ and CS− consists of a fixed nominal capacitor C0 in parallel with 6capacitors (C1 to C6) that can be selectively switched in via their control674.3. Readout Architecture and Op Amp Structureswitches (Fig. 4.6). Note that to test different ranges of capacitance varia-tions, 3 different capacitor banks are used (only one is shown in Fig. 4.6).It is also important to note that C1 to C6 are equal in each set. Moreover,C0 has a nominal value of 200 fF, while the value of C1 for each set is 2 fF,4 fF, and 8 fF, respectively. The change in capacitance is first convertedto a charge and subsequently goes through the charge-transfer amplifierusing CLS. The output of the charge-transfer amplifier is a voltage signalthat is proportional to ∆C as explained in Section 4.2. Such output is fedto the S/H stage followed by an (off-chip) unity gain differential amplifier(INA 105) which converts the output differential signals of the S/H stageinto a single-ended one. Note that, in practice, such differential amplifier isnot necessary, since typically the output of the S/H stage is directly fed intoan ADC having differential inputs.The schematic of the op amp used in all of the building blocks is shownin Fig. 4.7. This op amp uses the folded-cascode topology and has a DCopen-loop gain of 68.1 dB, a phase margin of 61.9◦, and a gain-bandwidthof 2.5 MHz with an output compensation capacitor of 5 pF. It consumes88 µW from a 5-V supply and has an output swing of 3.25 V. Additionally,the bias for the op amp is supplied externally.The flicker noise associated with the op amp is given by [89]:v2n,flicker ≈KfCoxWL1f(4.15)where Kf is the flicker noise coefficient that is a process-dependent param-eter, Cox is the oxide capacitance per unit area, and f is the frequency. W684.3. Readout Architecture and Op Amp StructureVDDVminusVplusVoutM1M2M3M4M5M6M7M8M9M10Mb1Mb2Mb3Mb4Bias Circuit Single-ended Folded Cascode Operational AmplifierGndIREFVbFigure 4.7: The schematic of the folded-cascode op amp that is implementedto minimize thermal and flicker noise.and L denote the width and length of the input differential pair, respectively.For this design, a PMOS input pair is chosen because in the technology usedin this work, the flicker noise coefficient of PMOS devices is lower than thatof their NMOS counterparts. Additionally, to reduce the flicker noise, W ischosen to be relatively large (i.e., 100 µm). This large W will result in alarge gm (i.e., ∼78 µS) which as explained below will result in lower thermalnoise.The thermal noise (v2n,thermal) of the folded-cascode amplifier can beexpressed as [89]:v2n,thermal∆f≈ 2(4kT23gm1)(1 +gm3gm1+gm9gm1)(4.16)694.4. Measurement ResultsS/HS/HCS + CLS readoutVariable Capacitors Active Area0.65 mm24.7 mm4.7 mmFigure 4.8: Micrograph of the test chip in 0.8 µm CMOS.where gm is the transconductance of the corresponding transistor. From(4.16), one can conclude that the thermal noise can be optimized if thetransconductance of the input transistors (gm1) are maximized, and thetransconductance of the current mirror transistors (i.e., gm3 and gm9) areminimized. In this work, gm1, gm3, and gm9 are ∼78 µS, ∼46 µS, and∼20 µS, respectively.4.4 Measurement ResultsThe proposed capacitive readout circuit is fabricated in a 0.8 µm CMOStechnology. The chip has an active area of 0.65 mm2 and its micrograph isshown in Fig. 4.8. As explained earlier, to emulate the sensor differentialcapacitance, on-chip banks of capacitors are used in pairs. The test setup is704.4. Measurement ResultsClock SoftwareOscilloscopeClock GeneratorCMOS ReadoutPower SuppliesSpectrumAnalyzerINA 105Figure 4.9: The test setup that is implemented to obtain important mea-surement results. Each equipment in the figure is identified in white text.shown in Fig. 4.9 where each test equipment is also identified. The requiredclocks and capacitance control signals are generated by an Agilent 81200data generator. The sampling clock runs at 100 kHz, and the capacitancecontrol signals vary at roughly 400 Hz. The measured time domain responseof the readout circuit at CA = 200 fF with a differential capacitance varia-tion of 24 fF (∆C = 12 fF) running at ∼400 Hz is shown in Fig. 4.10. Notethat the green and blue signals are the outputs of the S/H buffers (VSH,topand VSH,bot in Fig. 4.5). The red signal is the difference between the twoS/H outputs, and it has an amplitude of 0.6 V. The measured sensitivity(voltage variation in response to capacitance variation) of the prototype atdifferent gain settings is plotted in Fig. 4.11. It can be seen that the circuithas a maximum gain of 50 mV/fF when CA is equal to 200 fF. Fig. 4.12714.4. Measurement ResultsFigure 4.10: Differential output (in red) of the CMOS readout circuit withrespect to a differential capacitance variation of 24 fF changing at approxi-mately 400 Hz.shows the output spectrum of the readout circuit when an input is appliedat approximately 400 Hz. As it can be seen, the noise floor at the vicinityof 400 Hz is −111 dBm, which can be converted to 0.891 µV /√Hz. Thecapacitance noise floor can then be calculated using the maximum sensitiv-ity of the interface circuit to be 0.018 aF/√Hz. The noise performance isexpected to remain relatively the same if the readout circuit is implementedwith a MEMS sensor in a single chip. A summary of the measured perfor-mance parameters in this design is shown in Table 4.1, where a comparisonwith other works [90, 91, 100–102] is also presented. It is important to notethat, although the presented readout circuit compares favourably to otherworks in terms of its power consumption, a few of the latter designs includemore on-chip circuitry such as clock generators and filters.724.4. Measurement Results10 15 20 25 30 35 40 45 50 55 6000.20.40.60.811.21.41.6Differential Input Capacitance Variation (fF)Differential Output Voltage (V)  CA = 200 fFCA = 400 fFCA  = 600 fFFigure 4.11: Measured sensitivity of the CMOS readout circuit at differentgain settings. The measured output voltage indicates the AC amplitude.Figure 4.12: The spectrum of the output from 10 to 600 Hz when the inputis applied at about 400 Hz. The capacitance noise floor is 0.018 aF/√Hz.734.4.MeasurementResultsTable 4.1: Performance Summary and ComparisonParameter This Work [90]* [91]* [100] [101]* [102]Capacitive noise floor (aF/√Hz) 0.018 0.02 0.016 0.2 0.19 0.42Frequency where noise is measured (Hz) 400 400 400 N/A average from 0 to 300 3Clock (kHz) 100 1000 500 1000 6 600Technology (µm) 0.8 0.5 0.35 0.35 0.35 0.6Supply (V) 5 5 3.3 5 2.5 – 3.6 3Power (mW) 0.29 30 2.57 5 1 – 1.44 3.75*These designs include more on-chip circuitry such as clock generators and filters.744.5. Chapter 4 Conclusion4.5 Chapter 4 ConclusionA differential low-power low-noise CMOS readout circuit intended for MEMScapacitive sensors is presented. The circuit utilizes techniques such as cor-related level shifting and chopper stabilization to reduce the adverse effectsof op amp finite gain as well as DC offset and low-frequency noise. In thiswork, on-chip banks of capacitors are used to physically emulate the MEMScapacitive sensor. The capacitances are varied via control clock signals. Thecircuit achieves a maximum sensitivity of 50 mV/fF. The capacitance noisefloor for the readout is 0.018 aF/√Hz at 400 Hz. The sampling clock runsat 100 kHz and the overall interface consumes 290 µW.75Chapter 5A 14-bit Σ∆ CMOS MEMSCapacitive Sensor InterfaceUsing Modified CorrelatedLevel ShiftingAs discussed in the previous chapter, several MEMS capacitive sensing in-terface circuits have been proposed in the literature, where two particularcircuit design techniques have been widely used. These are the chopper sta-bilization (CS) and the correlated-double-sampling (CDS) techniques [96].Both techniques are used to reduce the offset and the low-frequency noise,e.g., 1/f noise of the op amp. Additionally, a relatively recent circuit tech-nique, correlated level shifting (CLS), that aims to minimize the op ampfinite gain error is also introduced in [98], and used in [4] as a sensor read-out circuit. The heart of the previous chapter is essentially the combinationof CLS and CS such that the readout circuit improves its accuracy, noisefloor, and power performance. Note that the need to use CS is due to thefact that CLS does not cancel offset or very low frequency noise.76Chapter 5. A 14-bit Σ∆ CMOS MEMS Capacitive Sensor Interface Using Modified Correlated Level ShiftingIn this chapter, a SC sensor interface front-end circuit based on a vari-ation of CLS is proposed to retain the features associated with the readoutcircuit in the previous chapter, without the need to use CS. In other words,the proposed interface front-end in this chapter uses a single modified cor-related level shifting technique to not only minimize the op amp finite gainerror, but also reduce low frequency imperfections associated with the opamp. This modified CLS technique therefore improves the noise and powerperformance of the circuit simultaneously.To complete the sensor readout system, a back-end first-order 14-bit Σ∆ADC is interfaced with the front-end circuit to provide a 1-bit pulse-widthmodulated (PWM) digital signal at the system output. As opposed to thepreviously reported sensor readout architectures, in which the MEMS sen-sor is directly connected to the integrator block of a Σ∆ modulator [18, 66],the presented system architecture has the front-end circuit block that con-verts the change in capacitance to voltage, followed by the back-end ADCthat digitizes the amplified analog voltage signal from the front-end to a1-bit output digital stream. The advantage of this architecture is the decou-pling of the modulator from the sensor to achieve optimized performanceindependent of the sensor capacitance [93].The content of this chapter describes a fully differential low-noise SCreadout circuit that is intended for MEMS capacitive inertial sensors. Theoverall system architecture consists of two main sections: the front-end blockand the back-end block. The front-end circuit consists of the sensor andthe charge-transfer amplifier (capacitance-to-voltage converter) that uses avariation of correlated level shifting (CLS) technique to reduce the op amp775.1. Modified CLS Theory of Operationfinite gain error as well as to minimize the effects of op amp offset and low-frequency noise. The output at the charge-transfer amplifier is smoothenedout by a S/H stage. The back-end block consists of an anti-aliasing filter(AAF) followed by a 14-bit first-order Σ∆ ADC. The readout circuit isdesigned and laid out in a 0.8 µm CMOS process. For the purpose ofsimulations, the MEMS capacitive sensor is emulated by a pair of differentialvariable capacitors in Verilog-A. Post-layout simulation results demonstratethat the circuit achieves a capacitance noise floor of ∼0.25 aF/√Hz at500 Hz with a sensitivity of 12.42 mV/fF. The circuit consumes 1 mW froma single 5 V supply.This chapter is organized as follows: the theory of operation of the pro-posed modified CLS is discussed in Section 5.1, where a simple single endedcapacitive sensor readout circuit is used as an example. In Section 5.2, theoverall sensor system architecture is first introduced and described, followedby detailed discussions on the front-end and back-end circuit blocks thatmake up the whole system. Post-layout simulation results are reported inSection 5.3 and the concluding remarks are provided in Section 5.4.5.1 Modified CLS Theory of OperationAs discussed in the previous chapter (Chapter 4), in regards to the originalCLS, while it possesses the loop gain boosting characteristic while introduc-ing negligible noise, it has poor offset/very low-frequency noise performance.Please refer to Chapter 4 for detailed discussion on the operation of CLS.Therefore, we propose to slightly modify the original CLS so that the785.1. Modified CLS Theory of OperationCACSCRVrefVDD  VrefGnd  VrefCCLSSampleCACSCRVrefCCLSEstimateVrefVrefVOUT, E1CACSCRVrefCCLSLevel ShiftVrefVrefVOUT, LS1Gnd GndCLGndCLGndCLGnd(a)CACSCRVrefVDD  Gnd  VrefCCLSSampleCACSCRVrefCCLSEstimateVrefVrefVOUT, E2CACSCRVrefCCLSLevel ShiftVrefVrefVOUT, LS2GndGndCLGndCLGndCLGnd(b)Original Correlated Level ShiftingModified Correlated Level ShiftingVOS+1VOS+1VOS+1Figure 5.1: (a) Operation of correlated level shifting (CLS). (b) Operation ofmodified correlated level shifting (MCLS). Single-ended structure is shownfor simplicity.modified version is able to reduce offset and low-frequency noise while keep-ing the original advantages. Fig. 5.1 (a) and (b) shows both the original CLSand the modified CLS (MCLS) in capacitive sensor readout application. Tobriefly introduce both circuits in Fig. 5.1, CS models the MEMS capacitivesensor (in this work, CS is described using Verilog-A). This variable sensingcapacitor can be written as: CS = C0+∆C where typically ∆C  C0. CR isthe reference capacitor and is equal to C0. CA is the feedback capacitor thatdictates the sensitivity of the readout circuit. CCLS is the capacitor used inCLS to reduce the op amp finite gain error and its purpose is described in795.1. Modified CLS Theory of Operationdetail in Chapter 4.The operating principle of the proposed MCLS is shown in Fig. 5.1 (b),where an input-referred voltage offset Vos of the op amp is included in thefigure. Note that Vos can also represent very low-frequency noise as anapproximation. The only difference between the two approaches (originalCLS and modified CLS) is in the sampling phase. For the variant of CLSproposed in this work, instead of connecting the inverting input of the opamp to a DC source, a connection is made between the inverting node of theop amp to the output of the op amp, forming a negative feedback network.In this way, the offset of the op amp can be sampled onto CA in the samplingphase, and subsequently its value can be subtracted from the signal in thenext phases (CDS principle). The output at the end of the estimation phasecan be written as:VOUT,E2 ≈[VDD2+VosK+VDD2(∆CCA)](11 + 1K)(5.1)where K is the opamp loop gain during this clock phase, and can be ex-pressed as:K =ACACS + C0 + CA≈ACA2C0 + CA(5.2)In equation (5.2), A is the DC gain of the op amp. Also note that Vref =0.5VDD.The output at the end of the level shift phase (output of interest) canbe written as:805.2. CMOS Interface Circuit ArchitectureVOUT,LS2 ≈[VDD2+VosK+VDD2(∆CCA)](11 + 1KEQ)(5.3)where the equivalent loop gain KEQ can be approximated as:KEQ = K(2 +K) ≈ K2 (5.4)where the assumption lies within the fact that there is no charge loss inCCLS . This point has also been discussed thoroughly in Chapter 4 (Equation(4.5) to (4.7)).As it can be seen from both (5.2) and (5.3), if the proposed modifica-tion is applied, the op amp offset is reduce by a factor of K, which can bemaximized if CA approaches infinity (assuming A is fixed). However, thesensitivity of the circuit (Volts/Farads) is inversely proportional to CA, soif large sensitivity is a requirement in the system specification, then the de-signer should take this trade-off into account. On the other hand, the overalleffective loop gain is still equal to KEQ, which is approximately K2. Thisshows that the MCLS still has the benefits from the original CLS.5.2 CMOS Interface Circuit ArchitectureThe overall system architecture of the designed fully differential sensor in-terface circuit can be found in Fig. 5.2. As it can be seen in the figure,the sensor is directly connected to the front-end circuits, where a SC chargetransfer amplifier is used to convert the changing charge of the capacitiveMEMS sensor to an amplified voltage representing the physical signal of815.2. CMOS Interface Circuit ArchitectureFigure 5.2: The overall sensing interface architecture with the physical sen-sor, front-end and back-end circuits. The front-end includes a modifiedcorrelated level shifting charge-transfer amplifier and a S/H stage while theback-end circuit includes an AAF plus a first-order Σ∆ ADCinterest. Note that the charge transfer amplifier uses the modified CLS asdiscussed in the previous section.The voltage at the output of the charge transfer amplifier is sampledand subsequently enters the back-end circuit block. The first stage of theback-end circuitries is an anti-aliasing filter (AAF) that filters out high fre-quency components of the signal such that the signal is more band-limitedand is free of aliasing. The second stage of the back-end circuits is a firstorder SC Σ∆ ADC that consists of an integrator, followed by a comparator(1-bit quantizer) and a 1-bit feedback DAC. As mentioned previously, thisconfiguration decouples the Σ∆ modulator from the sensor capacitors suchthat the size of the sensor capacitances does not affect overall system perfor-mance. Moreover, the front-end can be clocked (sampled) at a much lowerfrequency compared with the back-end, as this is particularly useful when825.2. CMOS Interface Circuit ArchitectureVrefGndΦeΦeΦsΦsΦLSΦLSΦLSCCLSCRCRΦeΦsVrefCAΦsΦLSΦLSCCLSΦLSCAΦsVrefΦsΦeΦsVDDΦeVrefMEMS Proof MassCS+CS-ΦLSCHCHΦLSGndVO+VO-VSH, topVSH, botShaded Area: S/H ✴ Vref = 0.5 × VDD = 2.5 VΦsΦeΦLSSampleEstimateLevel ShiftClock WaveformsOPAMP 1OPAMP 2CS+ = C0 + ∆CCS- = C0 - ∆CMEMS Differential Capacitive SensorGndΦLSLevel ShiftInvertedFigure 5.3: Schematic of the proposed capacitive readout front-end circuitwhich consists of variable capacitors (to mimic the MEMS sensor), modifiedCLS charge-transfer amplifier, and S/H dual buffers. The clock waveformsare also included in this figure.the sensor capacitance is large (large time constant). The CMOS readout isimplemented in fully differential fashion to reduce common mode interfer-ence (substrate and supply noise), and to increase the dynamic range. In thefollowing subsections, each of the above mentioned blocks will be discussedin more detail.5.2.1 Front-End Circuit BlockAs it can be seen in Fig. 5.2, the front-end of the interface circuit consistsof a SC charge-transfer amplifier followed by a S/H stage. The detailed835.2. CMOS Interface Circuit Architectureschematics of the front-end is shown in Fig. 5.3, where three major buildingblocks can be identified: a MEMS differential capacitive sensor, the proposedfully differential charge-transfer amplifier that uses modified CLS (MCLS),and a sample-and-hold (S/H) output stage. The MEMS capacitive sensor isessentially a three terminal device, where two of the terminals are connectedto the inverting input of the op amps (OPAMP1 and OPAMP2), and thethird is the proof mass. The variable capacitors CS+ and CS− are differentialand can be expressed as CS+ = C0+∆C and CS− = C0−∆C. It is importantto note that this readout front-end theoretically can be interfaced with anytypes of capacitive differential sensor as long as the feedback capacitor CAis programmable and can be matched with the nominal sensor capacitance.The capacitance variations from the sensor are first converted into chargesthat are transferred onto the feedback capacitors CA, and are amplifiedthrough the charge-transfer amplifier. The resulting output is in voltage.The operating principle of such charge-transfer amplifier is explained in Sec-tion 5.1 in the context of a single-ended circuit. The clocks shown in Fig. 5.3essentially divide the system into three classical CLS phases: sample, esti-mate, and level shift. Note that the valid outputs VO+ and VO− appear atthe end of the level shift phase. The aforementioned outputs are fed to theS/H stage to obtain a smoother signal. The final differential output VOUTis essentially:845.2. CMOS Interface Circuit ArchitectureVOUT = VSH,top − VSH,bot≈[Vos1 − Vos2K+VDD∆CCA](11 + 1KEQ)(5.5)where Vos1 and Vos2 are the input referred offsets associated with OPAMP1and OPAMP2, respectively. Interestingly, it can be seen that the final offsetis significantly reduced by two phenomena. First, the final offset is propor-tional to the difference between the offset from OPAMP1 and OPAMP2.Assuming a good match between the two op amps, the offset can be veryminimal. Furthermore, the offset difference is then reduced by a factor ofK, which is derived in Section 5.1. Therefore, the offset and the very lowfrequency noise in this circuit can be decreased tremendously.The op amps used in the circuit are all identical folded-cascode structureswith a DC gain of 56.47 dB, a phase margin of 74.67◦, an output voltageswing of 3.7 V, and a gain-bandwidth of 13.64 MHz at 1 pF load. The dualbuffer consists of two op amps each configured as a unity gain buffer. Theschematic of the op amps can be found in Fig. 4.7.5.2.2 Back-End Circuit BlockReferring back to Fig. 5.2, it can be seen that the back-end of the interfacecircuit consists of an anti-aliasing filter (AAF) and a Σ∆ ADC. The outputfrom the S/H stage is applied through the AAF such that the signal ofinterest is more band-limited, and more suitable for sampling. The detailed855.2. CMOS Interface Circuit ArchitectureVSH, topVSH, botVbiasCCRRPd1P2C1,topCF P2 QP1P2P1 Pd1 CCDSP2 P1Pd1P2 C1,botP10.5VDDCF QP1P2P2P1CCDSP2 P2Diff OTAOTAOTAP2 CIPd1P2 CIPd11-bit QuantizerQQP2AAF Sigma-Delta ADCFigure 5.4: Schematic of the proposed capacitive readout back-end circuitwhich consists of an AAF and a SC Σ∆ ADC using CDS. The clocks usedin the back-end are two non-overlapping clocks.schematics of the back-end circuit block is shown in Fig. 5.4.The AAF is a buffered RC low pass filter (LPF) where the R is madeof a MOSFET operating in its linear region. The transistors in this casedo not generate much flicker noise, but the thermal noise will be added tothe input signal of the Σ∆ ADC. The thermal noise can be considered asa dithering mechanism which randomizes the quantization noise spectrum.Note that the 3-dB bandwidth of the filter is determined by the value of Rand C, where the resistance is set by the size of the transistors.The Σ∆ ADC is a first-order modulator, which consists of a fully differen-tial SC integrator, a clocked 1-bit quantizer (comparator) and a SC negativefeedback network (1-bit digital-to-analog converter). It is important to note865.2. CMOS Interface Circuit Architecturethat, the Σ∆ ADC is an oversampling data converter that shapes the quan-tization noise out of the signal band, meaning the ADC could achieve veryhigh resolution without the need of increasing analog components.For a first-order Σ∆ ADC, the dynamic range (DR) can be expressed as[104]:DR = 10log(92pi2)+ 30log(OSR) (5.6)where OSR is the oversampling ratio of the converter, which is essentiallythe sampling clock frequency divided by 2X the input signal bandwidth.Equation (5.6) indicates that, the DR of the ADC increases by 9 dB everytime the OSR doubles. This also translates into a 1.5 bits improvementsfrom doubling the OSR. For this particular design, the OSR is roughly 1000,therefore, the DR should be expected to be ∼85 dB.The circuit is clocked by two non-overlapping clocks P1 and P2. Pd1and Pd2 are slightly delayed version of P1 and P2, and they are used toreduce the negative effects of charge injection. When clock phase P1 is high(sampling phase), C1,top and C1,bot will be charged with the filtered outputvoltage of the front-end VSH,top and VSH,bot, respectively. At the same time,the feedback capacitors CF are charged to 0.5VDD. When P2 switches tohigh (integration phase), the difference between the input signal (output ofthe AAF) and the 1-bit digital-to-analog converter (DAC) will be integratedthrough the SC integrator, and the digital output bit stream will show up atthe output of the 1-bit quantizer. Moreover, the correlated double sampling(CDS) capacitors at the input of the op amp will store the offset and flicker875.3. Post-Layout Simulation Resultsnoise in the sampling phase. These offset and noise will then be canceledout during the integration phase. Also note that the Σ∆ ADC is separatedfrom the actual sensor, therefore, it is not required to have C1, CF , or CIprogrammable as the operation of the ADC does not depend on the sensorcapacitance.The internal structure of the 1-bit quantizer is basically an uncompen-sated op amp and a D flip-flop (DFF). The DFF is a falling edge triggerdevice, meaning that the comparator digital output will be latched at thefalling edge of P2. The sampling clock runs at 1 MHz. The noise shapingcapability of a Σ∆ ADC will push the quantization noise out of the signalband.5.3 Post-Layout Simulation ResultsThe readout circuit including the aforementioned front-end and back-endcircuitries is designed and laid out in a 0.8 µm CMOS process. The circuitlayout is shown in Fig. 5.5, where the active area is enclosed in a white dottedbox and has a dimension of 2 × 0.25 mm2. To simulate the interface, a pairof voltage-controlled differential capacitors CS+ and CS− are implementedin Verilog-A to emulate the MEMS capacitive sensor. In terms of the front-end circuitry, Fig. 5.6 shows the simulated transient response of the readoutfront-end with respect to a sinusoidal ∆C with an amplitude of 50 fF anda frequency of 500 Hz (100 fF if considered differentially). Note that thesampling clock frequency is set at 100 kHz.The output of the S/H stage has a differential amplitude of 1.242 V,885.3. Post-Layout Simulation Results2 mm0.25 mmActive AreaFigure 5.5: Layout of the proposed interface circuit in 0.8 µm CMOS. Notethat the active area is enclosed in a white dotted box.which corresponds to a differential sensitivity of 12.42 mV/fF. Moreover,an offset voltage source is intentionally placed at the input of an op amp(charge-transfer amplifier) during the simulation, and it can be seen thatthe DC level of the output is unaffected by the offset and is still at Vref of2.5 V. In Fig. 5.7, a comparison between the original CLS and the proposedmodified CLS in terms of low-frequency noise behaviour is demonstrated vianoise simulation. It can be seen that the proposed approach outperformsconventional CLS at very low frequencies (6 dB improvement at 1 Hz). Forthe proposed circuit, the equivalent output noise at 500 Hz is 3.05 µV /√Hz,which indicates an input-referred capacitance noise floor of approximately0.25 aF/√Hz. Based on this simulation result, it can be seen that the noisefloor of this readout circuit is higher compared with the previous designs.This can be attributed to the fact that more op amps and capacitors areused in this readout. The op amp is a major noise source, and capacitors895.3. Post-Layout Simulation ResultsTransient Response of the CMOS Readout Circuit (0 to 2ms) vtop = VSH, top vbot = VSH, bot 1.242✴ ∆C = 50 fF sin(2∏ 500t)Figure 5.6: Transient response of the CMOS readout circuit front-end whenan input capacitance variation of 50 fF (100 fF differential) is applied at500 Hz.in series with resistors will generate kT/C noise. For this particular read-out, the purpose is to show that CLS can be modified such that offset andvery low-frequency noise can be reduced. If the designer can implement afully differential amplifier as opposed to two differential input single endedoutput op amp, the noise can be reduced significantly. Moreover, by usinglarger capacitors, i.e., larger CR, kT/C noise can also be reduced. There-fore, this design would be more useful for sensors that have higher nominalcapacitances. Finally, the front-end circuit consumes 555 µW from a single5V supply.In regards to the back-end circuit block, the output of the Σ∆ ADC is apulse-width modulated (PWM) signal. The bitstream represents the input905.3. Post-Layout Simulation Results1 2 3 4 5 6 7 8 9 1000.0050.010.0150.020.025  Original CLSModified CLSAbout 6 dB Improvement @ 1 HzOutput Noise (V/√Hz)Frequency (Hz)Figure 5.7: Simulated low-frequency noise response of the two approaches(CLS and proposed modified CLS).analog signal. This analog signal is essentially the output of the S/H circuitsfrom the front-end circuit block. In this case, it is a sinusoidal voltage signaltracking the sinusoidal capacitance variation coming from the sensor.To first verify the functionality of the Σ∆ ADC, a first-order low-passRC filter with 3-dB bandwidth of 4 kHz is used at the output to averagedown the bitstream. Since the input signal is running at 500 Hz, the filteredoutput should be a 500 Hz signal as well. Fig. 5.8 shows the low-passfiltered output signal (LP out), the ADC output bitstream (Qb), and theinput voltage signal (cap2) that generates the sinusoidal ∆C. As it canbe seen, the filtered bitstream absolutely represents the analog input signalwith a slight delay.915.3. Post-Layout Simulation ResultsFigure 5.8: Transient response of the CMOS readout back-end when an inputcapacitance variation of 50 fF (100 fF differential) is applied at 500 Hz. Thered bitstream is the output of the Σ∆ ADC that is getting filtered. Thebrown signal represents the low-pass filtered output, which tracks the inputsignal in blue.The resolution is determined by examining the output spectrum of theΣ∆ ADC. The PWM bitstream data at the output is collected and FastFourier Transform (FFT) is applied to the data in Matlab to obtain thespectral content of the digital signal. Fig. 5.9 illustrates the power spectrumof the ADC output, where the noise shaping capability of the Σ∆ ADC isclearly shown. It can be seen that the CMOS interface circuit achieves aDR of roughly 85 dB, which is equivalent to a resolution of 14 bits. Lastly,the power consumption from the back-end is about 450 µW. Therefore, thetotal power consumption of the CMOS readout circuit is 1 mW.A performance summary of the design is provided in Table 5.1. For thepurpose of comparison, the measured performance of recent related works925.3. Post-Layout Simulation ResultsFigure 5.9: The spectral content of the PWM output. The input signal is asinusoidal capacitance variation with a frequency of 500 Hz. The Σ∆ ADCprocesses the input and shapes the quantization noise out of the signal band.The DR is ∼85 dB, which translates to 14 bits of resolution.[90, 91, 93, 101] is also included in the table. Note that [90] and [91] usecontinuous-time-based (CT-based) circuits, [101] uses pseudo-CT-based cir-cuit, and [93] uses discrete-time-based (DT-based) circuit. Generally speak-ing, CT-based circuits exhibit better noise performance at the cost of con-suming more power. Table 5.1 shows that the power and noise performanceof the proposed readout circuit compares favourably with the state-of-the-art designs.935.3.Post-LayoutSimulationResultsTable 5.1: Performance Summary and ComparisonParameter This Work* [90]** [91]** [101]** [93]**Noise Floor (aF/√Hz) 0.25 0.02 0.016 0.19 4Frequency where noise is measured (Hz) 500 400 400 average from 0 to 300 10kClock (kHz) 125 1000 500 6 1000Technology (µm) 0.8 0.5 0.35 0.35 0.25Supply (V) 5 5 3.3 2.5 – 3.6 2.5Power (mW) 1*** 30 2.57 1 – 1.44 6****Post-layout simulation results **Measured results ***Including a SC Σ∆ modulator945.4. Measurement Results5.4 Measurement ResultsThe CMOS readout circuit including both the front-end (charge-transferamplifier and S/H) and back-end (AAF and Σ∆ ADC) circuits is fabricatedin CMOS 0.8 µm technology. The overall size of the interface circuit chipis 25 mm2, however, the active area is only 0.5 mm2 as discussed in theprevious section. The sensor interface chip is wire-bonded to the MEMSaccelerometer in a single package. This accelerometer is described in Sec-tion 3.1 and the overall size of the sensor chip is 30.25 mm2. A micrographshowing the whole system inside the package is illustrated in Fig. 5.10, wherethe CMOS readout is on the right, and the MEMS sensor is on the left.The device package is mounted at the centre of a designed PCB fortesting purposes. The dedicated PCB is shown in Fig. 5.11. The DC bi-asing circuitries surround the packaged device, while the connectors sit atthe perimeter of the board. After powering up the chip and providing thenecessary biases, I notice that the DC voltage level at the output of thefront-end is roughly 0 V, which is substantially less than the expected valueof 2.5 V (VREF ). This phenomenon has not changed after careful boarddebugging. There are no short circuits on the PCB and the biasing are allcorrect. We have 3 packages for testing and they all show the same results.I believe this problem could be caused by either of the following:1. Mismatch between the nominal sensor capacitance C0 and the ref-erence capacitor CR of the charge-transfer amplifier: referring backto Fig. 5.1(b), assuming all ideal components, if CR is not equal tothe nominal capacitor C0, the output of the charge-transfer amplifier955.4. Measurement ResultsFigure 5.10: Micrograph of the overall sensing device: CMOS readout circuitis on the right where as the MEMS accelerometer is on the left. The sensorand the electronics are wire-bonded together in a single package.during the level shift phase can be expressed as:VOUT,LS2 =VDD2+VDD(C0 − CR)2CA+VDD2(∆CCA)(5.7)This indicates that the common-mode voltage at the output of thecharge-transfer amplifier can potentially drop to near zero value if:CR − C0CA≥ 1 (5.8)965.4. Measurement ResultsFigure 5.11: Dedicated PCB to test the accelerometer sensing system whichis placed at the centre of the board.For this design, CR is designed to be equal to the nominal capacitance(C0) value, which was provided by the MEMS designers. It is likelythat CR turned out to be larger than C0 from all the parasitics near it,which caused this saturation phenomenon. Although I had trimmingcapability for CR, the resolution is quite limited, as I did not designfor a wider range of reference capacitances.2. Chips are broken during the wire-bonding process: I believe this isanother likely root because the packaging service provider had to cut975.5. Chapter 5 Conclusionoff the back of the readout circuit chip partially in order for the devicesto fit inside the package.3. Device is damaged from electrostatic discharge (ESD): I did implementESD protection pads for the readout circuit, therefore, this may be lesslikely than other potential causes.4. The op amp is broken: I believe this is unlikely because the currentflowing through the op amp is correct from probing.To summarize, I believe the reasoning behind the malfunctioning chipcould be the mismatch between sensor capacitance (C0) and reference capac-itance (CR), and the damage caused during the CMOS MEMS integration.Therefore, the performance of the sensing system is purely based on post-layout simulations.5.5 Chapter 5 ConclusionA low-noise interface circuit for MEMS capacitive sensory systems usingmodified CLS technique is presented. It is shown that the proposed cir-cuit decreases the adverse effects of the op amp offset and low-frequencynoise while maintaining the major benefit of the CLS, that is, reducing theeffects of op amp finite gain. The design is laid out in 0.8 µm CMOS. Post-layout simulation results show that the interface system has a sensitivityof 12.42 mV/fF while consuming 555 µW from a single 5 V supply. More-over, the readout circuit can resolve input capacitance variations as low as0.25 aF/√Hz at 500 Hz.98Chapter 6Overall Design Flow andDiscussion on ReportedReadoutsSo far in this thesis, three major circuit design techniques for MEMS ca-pacitive sensor interface are proposed and analyzed in detail. In Chapter 3,the parasitic-insensitive chopper stabilized readout circuit is described. InChapter 4, the chopper stabilized correlated level shifting readout circuit ispresented. And finally in Chapter 5, the Σ∆ modified correlated level shift-ing readout is discussed. The primary objective of utilizing the above men-tioned techniques is to achieve a high resolution high performance MEMSdevice. In particular, the system should have very good noise and powermetrics and can be used in applications where high performance is required.It is however very important to put the circuit design techniques asideand form a clear design flow. In other words, when a problem is given, thedesigner should follow a design flow and choose the correct circuit techniqueto implement the MEMS sensing device such that the system performancespecifications are met efficiently.996.1. Design Flow Chart and Detailed ExplanationIn this chapter, the objective is to discuss the overall design flow fromsystem level down to circuit level. In Section 6.1, a design flow chart isfirst given, followed by detailed explanations for each step. In Section 6.2, ageneral discussion on each of the reported readout circuit is provided, suchthat the reader will be able to select suitable circuit techniques for his/herown design.6.1 Design Flow Chart and Detailed ExplanationFigure 6.1 shows a readout circuit design flow chart, where on the mechanicalside, MEMS accelerometer is used as an example.As discussed in the Introduction, for performance demanding applica-tions, high resolution MEMS devices are required. Take MEMS accelerom-eter as an example, the resolution needs to be in the µg range for inertialsensing. This system level resolution should be the first specification tobe examined, and the MEMS designer will implement a certain mechani-cal structural engineering procedure to ensure such resolution mechanically.With a sufficiently large proof mass, µg can be the mechanical Browniannoise floor. Therefore, with a good MEMS mechanical design, theoretically,the sensor is able to detect such small acceleration.Once the resolution in g is determined (step 1), based on the mechanicaldesign of the MEMS sensor, the relationship between acceleration and ca-pacitance variation can be derived from the mechanical sensor. By knowingthe minimum detectable acceleration, i.e., µg, the capacitance noise floor canbe calculated using mechanical sensitivity in F/g (step 2). Note that this1006.1. Design Flow Chart and Detailed Explanation1. MEMS accelerometer minimum detectable acceleration specification (µg)2. Use MEMS sensor mechanical sensitivity (F/g) to derive minimum detectable capacitance variation3. Assume a reasonable electrical readout gain (V/F) and determine the output voltage noise floor6. Assume CLS will be used, determine readout circuit specifications such as settling time, settling accuracy4. Choose a noise reduction technique: CS, CDS, etc. 5. Use IC noise analysis to determine capacitor values (kT/C) and op amp maximum allowable noise7A. Determine op amp gain, bandwidth, phase margin, etc.7B. Minimize power consumptionFigure 6.1: A general readout circuit design flow chart.topic is also discussed in Section 2.1. Such minimum capacitance variationbasically determins the type of readout circuit to be designed.The resulting readout circuit needs to resolve the aforementioned smallcapacitance variation. In other words, the output voltage noise of the read-out has to be minimized to meet such requirement. With reasonable assump-tion on the readout gain (V/F ), the output noise voltage can be determined(step 3).In step 4, the designer should choose a noise reduction technique. Forinstance, CS can be used to lower offset and flicker noise. However, extra1016.1. Design Flow Chart and Detailed Explanationclocking is required to implement CS, which would increase the overall powerconsumption. If CDS is used, although additional clocking is not needed,the extra capacitor used to store errors would introduce extra kT/C noise.Therefore, these interesting trade-offs between noise and power should beconsidered by the designer.In terms of step 5, circuit noise should be analyzed to determine capaci-tor values as well as op amp noise specification. The capacitor value mainlydictates the thermal noise level (kT/C). In regards to op amp, although boththermal and flicker noise exist, CS/CDS can reduce the latter. It is impor-tant to note that, it is not possible to keep increasing the capacitor valuebecause large capacitors consume area. Furthermore, the feedback capacitorin the charge-transfer amplifier determines the capacitance-to-voltage gain.Large feedback capacitor will deteriorate the gain of the circuit, which canbe undesirable (related to step 3).From Chapter 4 and 5, it can be seen that CLS is a very useful techniquein terms of readout circuit designing. Therefore, CLS should be assumed inthe design process because it increases the loop gain of the readout circuit(step 6). With that in mind, designer can derive the op amp specificationsbased on settling time and accuracy. The op amp open loop gain is notrequired to be too large due to the loop gain boosting property of CLS,so power consumption can be reduced. The settling time can be used todetermine the op amp frequency response (step 7A and 7B). By knowing allthe specifications, the designer can implement all the circuit blocks down tothe transistor level.1026.2. General Discussion on Reported Readouts6.2 General Discussion on Reported ReadoutsBased on the discussion from Section 6.1, there are many design consid-erations from step 4 and onwards. For high resolution readout circuits,it is important to utilize a noise reduction technique. In regards to thereported designs, CS is used in Chapter 3 and Chapter 4, whereas the read-out in Chapter 5 uses an offset compensation technique similar to CDS.The designs presented from Chapter 3 to 5 are in chronological order. Theparasitic-insensitive readout circuit uses CS and very large op amp inputdifferential pair to reduce noise. The issue with this is that the device willbe large, and there is no power minimization technique applied. Therefore,although good noise performance can be achieved, there are many aspectsof the design that can be improved. Chapter 3 will be removed from furtherdiscussion.Starting from Chapter 4, CLS has been used to improve settling accuracyand power consumption. By utilizing CS in conjunction with CLS, very goodnoise and power performance is achieved (0.018 aF/√Hz and 0.29 mW).It is however important to note that the power consumption reported inChapter 4 only includes the readout circuit, but not any other requiredperipheral circuitries such as clocks, filters, or ADCs.In terms of Chapter 5, a modified CLS technique is used to implementthe readout circuit. The designed interface circuit generates more noisecompared to Chapter 4. However, it should be noted that the circuit imple-mented in Chapter 5 is a fast prototyping experiment, where many designaspects can be improved theoretically. For example, there are more op amps1036.2. General Discussion on Reported Readoutsused in Chapter 5 compared to Chapter 4. The designer can implement afully differential op amp as opposed to two differential-to-single-ended opamps. By using a single fully differential op amp, the noise performance canbe improved. Moreover, the modified CLS technique does not require extraclocking scheme, which is needed by CS. Therefore, the circuit in Chapter 5should consume less power than the one in Chapter 4 when the whole systemis considered.In conclusion, if one hopes to design a readout circuit that has very goodnoise performance, the CS + CLS readout introduced in Chapter 4 can beconsidered. On the other hand, if the MEMS device requires very goodpower consumption while having reasonable noise floor, the modified CLScircuit described in Chapter 5 can be utilized. The development of CMOSinterface circuits in all the chapters aligns with the ultimate scientific goal:proposing analog circuit design techniques to effectively reduce noise andpower consumption for MEMS electronic readout. The key is to find goodbalance between noise and power by utilizing different approaches, in orderto develop the right circuits based on the given specifications.104Chapter 7Conclusion and Future Work7.1 Research ContributionsThe general theme of this thesis is the design and implementation of CMOSelectronics interfacing MEMS capacitive sensors. More importantly, the re-search is mainly focused on analog circuit design techniques that improve thepower and noise performance of the overall system. The sensor used in thiswork is a capacitive SOI MUMPS micro-accelerometer, and several readoutcircuits are proposed, designed, fabricated, and characterized. The front-endtypically consists of a sensor, a charge-transfer amplifier (capacitance-to-voltage converter), S/H circuits, and filters. The output from the front-endwould be a purely analog signal, where it is necessary to digitize the sig-nal using an ADC for further digital signal processing. A summary of theoverall work done in the research have been published in both conferenceproceedings [1–3] and journals [4]. Additionally, there is another journalmanuscript that will soon be submitted.• In Chapter 3, a CMOS readout circuit is designed and fabricated tointerface with a MEMS capacitive accelerometer. On the mechanicalside, the micro-sensor is implemented in SOI MUMPs technology in1057.1. Research Contributionswhich a large proof mass is utilized so that the sensor has high sen-sitivity and good noise performance. Special circuit techniques havebeen added to the readout electronic so that it is parasitic insensitive.Additionally, the circuit utilizes chopper stabilization (CS) techniqueto reduce the offset and low-frequency noise coming from MOS tran-sistors. In this work, the CMOS interface and the MEMS sensor arewire-bonded in a single package forming a system-in-a-package. Mea-surement results show that the sensing system exhibits good noiseperformance.• In Chapter 4, a switched-capacitor circuit technique called correlatedlevel shifting (CLS) is used in conjunction with CS for the design ofthe readout circuit front-end. CLS was first proposed in [98] and itsignificantly improves the overall loop gain of the op amp. This wouldincrease the accuracy of the output and loosen the gain specification ofthe op amp, which would reduce the power consumption of the system.The one drawback associated with CLS is that it does not cancel DCoffset and very low-frequency noise of the op amp. By adding CSinto the scene, the low-frequency imperfections (DC offset and 1/fnoise) associated with the op amp would be reduced. In this work, apair of on-chip variable capacitors are used to emulate the mechanicalsensing element. Experimental results show very good power and noiseperformance from the circuit.• Extending the novelty of CLS, a modification to the technique is pro-posed such that the modified version not only improves the loop gain1067.2. Future Workof the op amp, but also reduces its DC offset and low-frequency noise.Note that no other circuit techniques are required to reduce the noise.Everything related to this circuit technique is presented in Chapter 5,where principle of operation, circuit analysis, and post-layout simula-tions are presented. The modified CLS preserves the benefits of theoriginal one, and simulation results show that the modified version has∼6 dB noise improvement at low-frequency.• Chapter 6 provides a detailed design flow for the designers to followand implement the CMOS readout circuit efficiently and systemat-ically. Moreover, discussion and comparison on the aforementionedthree circuit design approaches is presented. Each design techniquehas its own merit and can be used depending on the application.7.2 Future WorkFuture directions for expanding the current research include:• As discussed in the Introduction and Background chapters, one of thedesign focus is power consumption, leading to the selection of open-loop readout. However, it is possible to incorporate the readout circuitin a closed-loop system too. One of the possible future work wouldbe to use the low-power low-noise charge-transfer amplifier inside aclosed-loop sensing system for superior linearity and dynamic range.• The proposed readout circuits should be connected with an ADC chipso the sensor’s output can be digitized and processed. So far the1077.2. Future Workmeasurement results are purely analog. It would be interesting to usea Σ∆ ADC to digitize the analog signal.• To achieve the most optimal performance, The MEMS capacitive sen-sor and the electronics should be implemented on the same wafer,making the chip monolithic and much smaller in size. This will greatlyreduce the parasitic effect from the mechanical sensor to the readoutcircuit. Moreover, this can avoid wire bonds that could potentially actas an antenna and receive unwanted noise. Wire-bonding the MEMSsensor and readout circuit is done in Chapter 3, but ideally, as men-tioned previously, fabricating both devices on the same wafer wouldachieve better results.• A shaker table is very important for characterizing and measuring thesensory system as it is able to provide sinusoidal acceleration to thedevices. For future work, one may use a shaker table to test the MEMSsensor with readout circuit.108Bibliography[1] J. Shiah, H. Rashtian, and S. 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