A SERIES RESONANT CONVERTER FOR VOLTAGE EQUALIZATION OF SERIES CONNECTED SUPERCAPACITOR, ULTRACAPACITOR OR LITHIUM BATTERY CELLS by Yanqi Yu A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE COLLEGE OF GRADUATE STUDIES (Electrical Engineering) THE UNIVERSITY OF BRITISH COLUMBIA (Okanagan) July 2015 © Yanqi Yu, 2015 ii Abstract Supercapacitors are energy storage devices with great potential in many industrial applications. Although they are not as energy dense as batteries, they have much higher power density. This unique feature enables them to be used to provide bursts of energy in electric vehicle applications. They can be connected in parallel with batteries to source and sink dynamic energy which increases the lifetime of the expensive lithium batteries. Typically, the maximum voltage of a single supercapacitor unit is low, e.g. 2.5 V. In many applications, manufacturers need much higher voltages, e.g. 400 V, so it is necessary to connect supercapacitors in series. A series connection of supercapacitor cells can result in voltage imbalance between cells, since individual supercapacitors have different tolerances. Voltage imbalance can lead to damage of the individual supercapacitors and even the failure of the total energy storage system. Cell voltage equalization is a strategy to maintain the reliability of the supercapacitor pack. A single series inductor-capacitor (LC) resonant tank is proposed in this thesis for the voltage equalization of series connected energy storage elements. The circuit can be used for lithium battery cells, or supercapacitors, but the focus of the work targets supercapacitors. The circuit includes two levels of source connected MOSFET switches for the connection between resonant tank converter and each supercapacitor cell. A controller arranges supercapacitor voltages in descending order and makes a decision based on whether switches associated with the corresponding supercapacitors should be operated. If the voltage difference is higher than the pre-determined allowable value, the microcontroller sends pulse width modulation signals to gate drivers which control the on-off time of the MOSFET switches. iii Simulation results are presented using PSIM and demonstrate that voltage differences among supercapacitors can be removed fast. Experimental results show that the prototype of the proposed circuit can reduce a voltage deviation of 527 mV down to 10 mV in 15 minutes. The circuit is small in size, achieves a relatively short voltage equalization time and has minimal loss, therefore largely alleviating the problems inherent to existing voltage equalization converters. iv Table of Contents Abstract ................................................................................................................................... ii Table of Contents ................................................................................................................... iv List of Tables .......................................................................................................................... vi List of Figures ....................................................................................................................... vii List of Symbols .........................................................................................................................x List of Abbreviations ........................................................................................................... xiii Acknowledgements .............................................................................................................. xiv Dedication ...............................................................................................................................xv Chapter 1: Introduction ..........................................................................................................1 1.1 Overview of Supercapacitor Characteristics .............................................................. 1 1.2 Supercapacitor Applications in Electric Vehicles ...................................................... 3 1.3 The Necessity of Voltage Equalization for a Supercapacitor String ......................... 4 1.4 Contribution of the Thesis ......................................................................................... 6 1.5 Thesis Outline ............................................................................................................ 6 Chapter 2: Review of Existing Topologies for Energy Storage Device Cell Voltage Equalization .............................................................................................................................8 2.1 Overview .................................................................................................................... 8 2.2 Categorization of Voltage Equalization Methods ...................................................... 8 2.3 Single Inductor Topology ........................................................................................ 10 2.4 Bi-directional Cûk Converter Topology .................................................................. 12 2.5 Single Switch Voltage Multiplier Topology ............................................................ 16 2.6 Buck-boost Shunting Converter Topology .............................................................. 18 2.7 Selective Flyback Converter Topology ................................................................... 21 2.8 Half-bridge Multi-winding Output DC-DC Converter Topology ........................... 24 2.9 Summary .................................................................................................................. 29 v Chapter 3: Proposed Series Resonant LC Voltage Balancing Converter ........................31 3.1 Overview .................................................................................................................. 31 3.2 Design Constraints ................................................................................................... 31 3.3 Motivation for Topology Design ............................................................................. 31 3.4 The Proposed Voltage Equalizer Circuit ................................................................. 33 3.5 Voltage Equalization Operation ............................................................................... 36 3.6 Mathematical Analysis of the Proposed Circuit ...................................................... 42 3.7 Analysis of the Equivalent Circuit ........................................................................... 44 3.8 Fourier Analysis of Resonant Inductor Current ....................................................... 46 3.9 Component Stress Analysis ..................................................................................... 48 3.10 Voltage Equalization Realization Algorithm ....................................................... 49 3.11 Summary .............................................................................................................. 52 Chapter 4: Simulation and Experimental Results ..............................................................53 4.1 Overview .................................................................................................................. 53 4.2 Simulation Results ................................................................................................... 53 4.3 Experimental Results ............................................................................................... 60 4.4 Summary .................................................................................................................. 66 Chapter 5: Conclusions .........................................................................................................68 5.1 Research Summary .................................................................................................. 68 5.2 Suggestions for Future Work ................................................................................... 72 References ...............................................................................................................................73 vi List of Tables Table 3.1 Voltage stress for MOSFET switches in different switch conduction periods ....... 49 Table 4.1 Proposed converter component list......................................................................... 61 Table 5.1 Performance comparison among voltage equalization topologies ......................... 71 vii List of Figures Figure 1.1 Battery and supercapacitor application in electric vehicle ...................................3 Figure 1.2 Voltage imbalance situation of supercapacitor ....................................................6 Figure 2.1 Passive voltage equalization topology using shunting resistors [17] ...................8 Figure 2.2 Single inductor topology [31] ............................................................................11 Figure 2.3 Equivalent circuit for single inductor topology when Vsc1>Vsc2 ....................12 Figure 2.4 Bi-directional Cûk converter topology [32] .......................................................13 Figure 2.5 Equivalent circuit when vsc1>vsc2 in the bidirectional Cûk converter .................13 Figure 2.6 Operation mode 1 of the bi-directional Cûk converter ......................................14 Figure 2.7 Operation mode 2 of bi-directional Cûk converter ............................................14 Figure 2.8 Operation mode 3 of bi-directional Cûk converter ............................................15 Figure 2.9 Single switch voltage multiplier topology [33] ..................................................17 Figure 2.10 Current flow during the on-state of the switch ...................................................17 Figure 2.11 Current flow during the off-state of the switch ..................................................18 Figure 2.12 Buck-boost shunting converter [34] ...................................................................19 Figure 2.13 Selective flyback converter topology [35] .........................................................22 Figure 2.14 Half-bridge multi-winding output DC-DC converter topology [36] ..................24 Figure 2.15 Operational process of half bridge multi-winding transformer topology. Mode 1: circuit operation when Q1 is on. ..........................................................26 Figure 2.16 Operational process of half bridge multi-winding transformer topology. Mode 2: circuit operation when D2 is on. ..........................................................27 Figure 2.17 Operational process of half bridge multi-winding transformer topology. Mode 3: circuit operation when Q2 is on. ..........................................................28 Figure 2.18 Operational process of half bridge multi-winding transformer topology. Mode 4: circuit operation when D1 is on. ..........................................................29 Figure 3.1 Proposed supercapacitor voltage equalization converter ...................................33 Figure 3.2 Analytical waveforms of resonant capacitor voltage, resonant inductor current and supercapacitor voltages in four modes. .......................................................37 Figure 3.3 Current flowing paths of the proposed converter. Mode 1: Energy transportation from high voltage supercapacitor to LC resonant equalization converter. ........38 viii Figure 3.4 Current flowing paths of the proposed converter. Mode 2: Energy flowing paths when resonant inductor releases its stored energy. ............................................39 Figure 3.5 Current flowing paths of the proposed converter. Mode 3: Energy transportation from equalization converter to low voltage supercapacitor. ..............................40 Figure 3.6 Current flowing paths of the proposed converter. Mode 4: Energy flowing paths when resonant inductor releases its stored energy in the opposite direction. ....41 Figure 3.7 Equivalent circuit during energy transportation process. ...................................45 Figure 3.8 Decomposition of resonant tank ladder waveform. ...........................................46 Figure 3.9 Algorithm for voltage equalization process .......................................................51 Figure 3.10 Detailed algorithm for the proposed three supercapacitor voltage equalization process. ...............................................................................................................52 Figure 4.1 Simulation diagram for the three supercapacitor voltage equalization topology. ............................................................................................................54 Figure 4.2 Simulation waveform of resonant inductor current............................................55 Figure 4.3 FFT analysis of resonant inductor current..........................................................56 Figure 4.4 General changing behavior of resonant inductor current. ..................................56 Figure 4.5 Simulation waveform of resonant capacitor voltage. .........................................57 Figure 4.6 Simulation waveform of MOSFET switch current. ...........................................58 Figure 4.7 Simulation waveforms of a single set of MOSFET switch voltages at different circuit level. (a) Voltage waveforms of higher circuit level switches. (b) Voltage waveforms of lower circuit level switches. ..........................................59 Figure 4.8 Simulation waveform of voltage equalization process. .....................................60 Figure 4.9 Photograph of the proposed circuit board prototype for supercapacitor voltage equalization. .......................................................................................................61 Figure 4.10 Experiment measurement waveform of resonant inductor current during the initial operation of the converter. Current scale = 0.5A/div; Time scale = 20µs/div. .............................................................................................................65 Figure 4.11 Experiment measurement waveform of resonant capacitor voltage during the initial operation of the converter. Voltage scale = 1.0V/div; Time scale = 20µs/div. .............................................................................................................65 ix Figure 4.12 Experiment measurement waveform of voltage equalization characteristics ....66 x List of Symbols C Capacitor C1* to C3* Reference capacitors Cr Resonant capacitor Crated Rated capacitance of supercapacitor D Duty cycle Dcw Freewheeling diode when inductor current flows in clockwise direction Dccw Freewheeling diode when inductor current flows in counter-clockwise direction D1a to D1d Full bridge rectifier diodes Din Diodes on the positive levels of switches Dip Diodes on the levels of P-channel switches Ds1 Zigzag diode ES Energy storage device fr Resonant frequency fs Switching frequency Ich Major charging current source 𝐼𝑑𝑖𝑠 Discharging current of a single supercapacitor 𝐼𝑟𝑒𝑐 Current received by the rest of supercapacitors Irms Root mean square value of resonant current Ipeak Peak value of resonant current 𝑖𝐿𝑚 Magnetizing inductor current ir Resonant current 𝑖𝑝𝑎𝑐𝑘 Current flowing through supercapacitor pack 𝑖𝑝𝑘 Peak current L Inductor xi 𝐿𝑚 Magnetizing inductor Lr Resonant inductor 𝑁 Total number of supercapacitors connected in a string n Sequence number of supercapacitors Rb1 to Rb2 Balancing resistors Rds Drain-to-source resistance Rp1 to Rp2 Leakage resistors Rtotal Total resistance in the equivalent circuit SC1 to SCn Supercapacitors Sin Switches on the negative levels of supercapacitors Sip Switches on the positive levels of supercapacitors T Switching period t0 Time instant when energy transportation starts t1 Time instant when resonant inductor current reaches its peak value Vcr Resonant capacitor voltage Vgs Gate to source voltage Vi Initial voltage of supercapacitor Vp Peak voltage of supercapacitor 𝑉𝑝𝑎𝑐𝑘 Voltage of entire supercapacitor pack Vrated Rated voltage of supercapacitor Vrms Root mean square value of resonant tank voltage Vsc Supercapacitor voltage 𝜔 Angular frequency Z Circuit impedance xii |𝑍| Magnitude of circuit impedance |𝑍(𝑓)| Magnitude of circuit impedance with respect to switching frequency xiii List of Abbreviations A Amperes AC Alternating Current ADC Analog to Digital Converter DC Direct Current EMI Electrical Magnetic Interference ESR Equivalent Series Resistance F Farads FFT Fast Fourier Transform H Henry Hz Hertz k Kilo (103) M Mega (106) m Milli (10−3) MIPS Microprocessor without Interlocked Pipeline Stages MOSFET Metal Oxide Silicon Field Effect Transistor PWM Pulse Width Modulation RMS Root Mean Square s Seconds V Volts W Watts μ Micro (10−6) Ω Ohms xiv Acknowledgements I would like to express my ever-lasting gratitude towards all the faculty members, staff and my fellow students at UBC Okanagan Campus, who have constantly supported my ideas and work in the field of electrical engineering. And I owe special gratitude towards Dr. W. Eberle, my supervisor, who supportively raised in-depth questions which enabled me to probe deeply into this field during my course and research project period. His clear thinking style, professional research capability, and integral industrial experience will influence me continuously. I also want to thank Dr. Stephen O’Leary for enlarging my vision of science and providing coherent answers to my endless questions. I would like to offer my thanks to all the people who generously supported me and provided me constructive academic and industrial experience during my life in Kelowna, including Xian Jin, Raed Mohsen Saasaa, Sepehr Zarif Mansour, Mohamed Hegazi, Hamid Reza Hafezi Nasab, Mohammed Yafia, Changle Zhu, Tim Giesbrecht and Yu Cao. Finally, I would like to acknowledge the financial support from The University of British Columbia in the form of University Graduate Fellowships (UGF). All my achievements until now are the contribution of my effort and infinite support from my academic colleagues. xv Dedication To my parents who have supported me throughout my years of education financially and spiritually. To my cousins who have encouraged to study for the master degree. 1 Chapter 1: Introduction 1.1 Overview of Supercapacitor Characteristics With the world’s economic development, the total amount of existing non-renewable energy resources has decreased gradually. At the same time, the requirement for developing new energy resources has increased sharply. During the past several decades, a wide variety of energy resources have been explored. These energy resources mainly range from solar, wind, and tidal energy to biofuel energy. However, due to the increasing demand of energy and high costs of new energy development, non-renewable energy such as oil and natural gas still plays a vital role in society. Electrical energy is one of the most widely consumed forms of energy in modern era. However, the low efficiency of electrical energy conversion presents challenges for the integration of renewables. In order to maintain sustainable energy development, it is critical to improve electrical energy utilization efficiency. Power electronics is the primary area for enhancing electrical energy utilization efficiency and the field has experienced rapid advancement over the past several decades. It has recently become prevalent in power conversion systems including AC/DC rectification systems, DC/DC conversion systems and DC/AC inversion systems. Power electronics also makes a significant contribution to electric transportation systems since electric vehicle technology has seen tremendous growth in the past decade. In electric vehicles, fuel cells, batteries and capacitors usually act as energy storage devices to replace gasoline engines used in gas-powered vehicles. This continued adoption could reduce the greenhouse gas emitted from vehicles and reduce fossil fuel energy consumption. Batteries are relatively energy dense (typically 100- 200 Wh/kg) [1], but their limited power density has directed the research to focus on battery/capacitor hybrid systems. Supercapacitors, 2 or ultracapacitors, hereafter referred to as supercapacitors are a new type of capacitor, with very high capacitance in the hundreds to thousands of Farads. Conventional capacitors are typically limited to tens of farads. Supercapacitors have low equivalent series resistance (ESR), high level of stability, wide temperature operating range and virtually infinite life cycles and this enables them to be substitutes for conventional batteries. Although supercapacitors have lower energy density (which is usually defined as the amount of energy kept in reserve per unit mass), they have much higher power density [2] (which is defined as the ratio of power to weight) than batteries. The power density for a typical supercapacitor cell can reach 2 kW/kg, while the energy density is 10 Wh/kg [3]. Due to their fast charge and discharge speed, they can easily satisfy electric vehicle demands for instantaneous power sourcing or sinking. Compared with batteries, which are rather difficult to manage because of their unstable internal chemical reactions [4], supercapacitors are much safer since they use static electricity for energy storage. Furthermore, unlike batteries which leak harmful chemicals into the environment when they are disposed of, supercapacitors are environmentally friendly [5]. In comparison with conventional batteries, the advantages of supercapacitors are summarized as follows: 1. High power density (ten times higher than that of typical batteries); 2. Environmentally friendly and safe; 3. Fast charge and discharge rate (supercapacitors can be recharged in less than thirty seconds); 4. Infinite charging and discharging cycles with little charge and discharge degradation; 5. Long calendar lifetime (typically 10 to 20 years); 3 6. Low internal resistance (higher current flow through with high efficiency). The disadvantages of supercapacitor in industrial applications include: 1. Low energy density; 2. High self-discharge rate; 3. Spark hazard when short-circuited; 4. Low maximum voltage per unit cell due to manufacturing limitations; (therefore requires series connection of supercapacitors to obtain high voltage). 1.2 Supercapacitor Applications in Electric Vehicles Supercapacitors are optimal devices for absorbing and delivering sudden power surges. The diagram for an example supercapacitor application in an electric vehicle is illustrated in Figure 1.1. DCDCDCACSupercapacitor stringBattery bankMwheelwheelMotor drive inverterElectric motor Figure 1.1 Battery and supercapacitor application in electric vehicle In a typical electric vehicle application, supercapacitors can be used in conjunction with batteries as temporary energy storage devices. On the theoretical level, it is possible to use 4 supercapacitors as the sole energy source to power electric vehicles. However, their low energy density usually prevents them from exclusive use, so battery-supercapacitor hybrid systems can be used. While most existing EVs on the market, including the Tesla Model S, Nissan Lead and Ford Focus EV exclusively use batteries, issues with battery heating during acceleration/ deceleration dynamics, battery pack lifetime reduction have become a major concern. To solve this, supercapacitors can be added in parallel connection with batteries to meet the requirements of peak power absorption [6]. The basic idea behind this transportation application is that when starting an electric vehicle, supercapacitors can reduce battery cycling [7]. Since the lifetime of batteries can be longer when they undergo small amount of discharge with low frequency, these supercapacitors could extend the lifetime of expensive batteries during braking [8]. Supercapacitors can also be used for energy regeneration. In a typical electric vehicle application, batteries cannot utilize the large charge current during braking, while supercapacitors can capture the braking energy and store the energy temporarily. They then redistribute the stored energy for vehicle start and acceleration [9]. In addition, if the batteries fail to work normally under harsh weather conditions, supercapacitors can provide energy since they have wide operating temperature range, typically -40 ºC to 85 ºC [10]. 1.3 The Necessity of Voltage Equalization for a Supercapacitor String Generally, individual supercapacitor cell voltages are quite low [11] (2.5 to 2.7 volts, typically). This is due to the fact that they are built with high capacitance (the maximum capacitance could reach up to 5000 Farads). For modern industrial applications, it is critical for energy devices to generate high voltages to minimize system currents for a given power level. As a result, series and parallel configurations of supercapacitors are necessary to obtain 5 a high voltage [12], e.g. 200V. The voltage characteristics of supercapacitors depend on many factors, including equivalent series resistances (ESR), self-discharge rates and capacitance tolerance [13]. Due to their tolerance, not all the supercapacitors connected in series have the same capacitance (supercapacitor tolerance is typically up to +/-20%). Since supercapacitors are configured in series, the current flowing through the string is identical for all cells. Supercapacitors redistribute the charge between them in order to ensure that there is equal amount of current flowing through them. This directly contributes to the imbalance of individual supercapacitor voltages in a string during a single charging and discharging cycle. As the charging and discharging process continues, the voltage difference among the supercapacitors is further enlarged. This can become a severe problem because overcharging contributes directly to supercapacitor cell overheating which can result in capacitor damage, including gas generation and electrolyte decomposition. Therefore, the life span of supercapacitors will be reduced [14], or more severely, instantaneous failure. On the other hand, supercapacitors with lower voltages cannot reach their full potential energy storage capacity during the same charging process [15]. If we assume three supercapacitors have individual capacitances of 1.2Crated, Crated and 0.8 Crated, then because of the constant charging current, the voltage distributed across each supercapacitor is 0.83Vrated, Vrated and 1.25 Vrated, as illustrated in Figure 1.2. If the rated voltage for each supercapacitor is 2.5V, then the highest voltage/lowest capacitance cell will achieve a voltage of 3V, which is beyond the surge voltage level of a typical supercapacitor. Since the energy stored in the vehicle is dependent on both the high voltage supercapacitor cells and the low voltage supercapacitor cell, it is imperative to take some measures to minimize voltage difference among supercapacitors. These measures include the use of voltage detection and equalization circuits. 6 1.2CC0.8CIUnder Voltage: 0.83 VratedNominal Voltage: VratedOver Voltage: 1.25 Vrated Figure 1.2 Voltage imbalance situation of supercapacitor 1.4 Contribution of the Thesis The major contributions of this thesis include the following: (1) A novel series LC resonant tank converter for voltage equalization of series connected supercapacitors; (2) An explanation of the advantages of using resonance to achieve maximum current in the proposed equalization circuit; (3) An explanation of the application of Fourier series analysis to the equivalent circuit model for the proposed equalization circuit; (4) Experimental results demonstrating the effectiveness of the proposed circuit. 1.5 Thesis Outline The thesis is organized into 5 chapters. 7 Chapter 1 provides a brief introduction of supercapacitors, current and future supercapacitor applications in the electric vehicle industry and the necessity of voltage equalization for supercapacitors. Chapter 2 reviews the existing passive and active voltage equalization topologies for supercapacitors. Chapter 3 presents the proposed single series LC resonant tank converter topology, its modes of operation, mathematical analysis for the equivalent circuit and simulation results. Chapter 4 presents the experimental setup of the proposed topology, the components used in the printed circuit board prototype, and the results generated during tests. Chapter 5 provides a summary of the work completed and results and includes additional topics for potential future work. 8 Chapter 2: Review of Existing Topologies for Energy Storage Device Cell Voltage Equalization 2.1 Overview In this chapter, a review of existing voltage balancing circuits is presented. A brief review of different active voltage equalization methods is carried out along with their respective advantages and disadvantages. The review outlines the limitations of the existing work in order to establish the motivation for the proposed circuit topology. 2.2 Categorization of Voltage Equalization Methods There have been several voltage equalization techniques proposed in the last twenty years. Generally, these voltage equalization methods can be categorized into two groups, passive voltage equalization methods and active voltage equalization methods [16]. Passive voltage equalization methods, such as the resistor shunting method, use energy-consuming devices such as resistors to remove excess energy from the higher-voltage supercapacitors. The extra energy flows through resistors and is dissipated as heat [17]，as illustrated in Figure 2.1. SC1SC2Rb1Rb2Rp1Rp2 Figure 2.1 Passive voltage equalization topology using shunting resistors [17] 9 Balancing resistors Rb1 and Rb2 are matched and are configured in parallel with the supercapaitors which have very high internal parallel leakage resistors Rp1 and Rp2, which model their leakage current. Therefore, by connecting an additional resistor to each supercapacitor, the equivalent resistance across the supercapacitors reduces significantly and the equivalent resistance for each supercapacitor is nearly equal. However, in order to effectively balance a wide cell, the balancing resistors should be less than two percent of the highest leakage resistance. For example, assume two supercapacitors are charged by a 5 V voltage supply. Their rated voltages are 2.5 V and their leakage resistances are Rp1=1 MΩ and Rp2=0.5 MΩ, respectively. Therefore, the corresponding actual voltages across each supercapacitor are 3.3 V and 1.7 V. The voltage mismatch is 1.6 V. If we add a 200 kΩ balancing resistor, which is twenty percent of the maximum parallel leakage resistance value, then the apparent equivalent resistance will be 167 kΩ for SC1 and 142 kΩ for SC2. Correspondingly, the voltages for the two supercapacitors will be 4.61 V and 0.39 V. In this case, the resulting voltage difference is even higher than the case without voltage equalization. The resulting voltage for the higher voltage supercapacitor likely would lead to supercapacitor degradation. If we connect a 20 kΩ balancing resistor, which is two percent of the maximum parallel leakage resistance value, the apparent equivalent resistance will be 19.6 kΩ for SC1 and 19.2 kΩ for SC2. Correspondingly, the voltages for the two supercapacitors will be 2.52 V and 2.48 V. These voltage levels within 20 mV of the nominated value, i.e. 2.5 V and the voltage difference of the two supercapacitors is reduced to 40 mV. Generally, the lower the value of the balancing resistors, the smaller the voltage difference that can be achieved. This process terminates when all the supercapacitors configured in the string obtain their voltages. 10 Despite the fact that this topology has a simple structure and control strategy, small relative package size and low relative cost, the efficiency of the topology is low since a considerable amount of energy is converted into heat. In addition, the excessive heat generated by the resistors in the circuit could increase the temperature in the supercapacitor circuit, and therefore reduce the lifetime of the supercapacitors, or lead to difficulties with heat management. On the other hand, active voltage equalization methods remove excess charge from high-voltage supercapacitors and transport the charge to the supercapacitors with lower voltages. These techniques employ energy storage elements such as inductors and capacitors to store energy temporarily. In terms of efficiency, the active voltage equalization methods are superior to passive voltage equalization methods because they can fully recover the energy in the original unbalanced supercapacitor cells. Recently, due to the limitations of passive voltage balancing, researchers have begun to investigate active voltage equalization topologies [18] [19] [20] [21]. Some of these topologies use switched capacitors [22] [23] [24] [25], or buck-boost converters [26] [27] to regulate the voltages of individual supercapacitors and the others utilize transformers [28] [29] [30] to dynamically achieve voltage balancing. Work in these areas is discussed in the following sub-sections. 2.3 Single Inductor Topology The single inductor voltage equalization topology proposed in [31] is illustrated in Figure 2.2. In this circuit, unidirectional switches are connected to the upper and lower side of the supercapacitors to maintain the direction of the inductor current. Bidirectional switches are 11 connected to the top and bottom of the entire supercapacitor string. The main current source, Ich, aids the charge transfer during the charging process. SC1SC2SC3S1S21S22S31S32S4D22D32D4D1D21D31 AIch B Figure 2.2 Single inductor topology [31] The circuit operation is described as follows. As illustrated in Figure 2.3, assuming VSC1 > VSC2. During the first half period of a single switching cycle, switch S1 and S21 are turned on such that the voltage across supercapacitor SC1 is applied to inductor L. Therefore, the current in the inductor increases linearly. During the second half period of the switching cycle, since the current in the inductor must maintain its direction, switch S1 is turned off while S32 is turned on to redistribute the energy stored in the inductor to SC2. 12 SC1SC2D32D21D21L S32 S21S21S1Discharging SC1Charging SC2Vsc1 Vsc2 Figure 2.3 Equivalent circuit for single inductor topology when Vsc1>Vsc2 If there are more supercapacitors that need to be discharged in the supercapacitor string, the switches associated with each supercapacitor should be turned on in sequence to prevent overcharging of the low voltage supercapacitors. In this case, the discharging current can be much larger than the charging current. In the most extreme case, for n supercapacitors, where there is only one weakly charged (i.e. low voltage) supercapacitor and the rest are all overcharged, the average current from the overcharged supercapacitors would be (n-1) Ich, which transfers the charge to the supercapacitor with less voltage. Therefore, the inductor must be designed to ensure the weakly charged supercapacitor can absorb all the charge delivered. The major advantage of this topology is that it employs only one inductor as the immediate energy storage device. However, the control strategy for the switches is complex. 2.4 Bi-directional Cûk Converter Topology The bi-directional Cûk Converter topology proposed in [32] is illustrated in Figure 2.4. The equivalent circuit for two supercapacitors assuming VSC1 > VSC2 is illustrated in Figure 2.5. 13 SC1SC2SC3C2C1L1L3L2L4IQ3Q4 Figure 2.4 Bi-directional Cûk converter topology [32] L2L1 C1SC2SC1Q1 Q2D1 D2I1 I2 Figure 2.5 Equivalent circuit when vsc1>vsc2 in the bidirectional Cûk converter Assume the voltage of supercapacitor SC1 is higher than that of SC2. There are three modes of circuit operation involved for this topology. During mode 1 in time interval 0 - D1T, where T is the switching period and D1 is the duty ratio for the time duration when only Q1 is turned on. Switch Q1 is turned on to allow SC1 to store energy into the inductor L1. Simultaneously, capacitor C1 discharges through Q1 to SC2, as shown in Figure 2.6. This mode ends when the voltage in C1 reaches zero. The capacitor voltage across C1 in this mode can be expressed as: 𝑣𝑐1 =𝑖1(1 − 𝐷)𝑇 − 𝑖2𝑡𝐶1 (2-1) 14 where i1 and i2 are the currents flowing through SC1 and SC2 respectively and D is the duty ratio for the time duration when both Q1 and D2 are turned on. SC1SC2L1L2Vsc1Vsc2C1 VC1 Figure 2.6 Operation mode 1 of the bi-directional Cûk converter During mode 2 between time interval D1T and DT, Switch Q1 remains on, while body diode D2 is forced to turn on. Then inductor L2 distributes its stored energy to supercapacitor SC2 through D2, as shown in Figure 2.7. The capacitor voltage across C1 in this mode remains zero. SC1SC2L1L2Vsc1Vsc2 Figure 2.7 Operation mode 2 of bi-directional Cûk converter During mode 3 between time interval DT and T, Q1 is turned off, while D2 remains on. Capacitor C1 is charged by SC1, while the voltage of SC2 is controlled by the current in inductor L2, as shown in Figure 2.8. 15 SC1SC2L1L2C1Vsc1VC1Vsc2 Figure 2.8 Operation mode 3 of bi-directional Cûk converter The capacitor voltage in this mode can be written as (2-2): 𝑣𝑐1 =𝑖1(𝑡 − 𝐷𝑇)𝐶1 (2-2) The capacitor C1 is charged to the same initial voltage as at time zero, therefore by capacitor charge balance, 𝐼1(1 − 𝐷)𝑇 = 𝐼2𝐷1𝑇 (2-3) which means: 𝐷1 =(1 − 𝐷)𝐼1𝐼2 (2-4) By integration of the capacitor voltage in mode 1, the average capacitor voltage and average diode voltage can be expressed by (2-5) and (2-6), respectively. 𝑉𝑐1 =𝑇2𝐶1𝐼1(1 − 𝐷)(1 − 𝐷 + 𝐷1) (2-5) 𝑉𝐷2 =𝐼1(1 − 𝐷)𝐷1𝑇2𝐶1 (2-6) 16 Since the average supercapacitor voltages are VSC1=VC1-VD2 and VSC2=VD2, the ratio between VSC1 and VSC2 can be expressed as: 𝑉𝑠𝑐2𝑉𝑠𝑐1=𝐷11 − 𝐷 (2-7) Substituting (2-4) into (2-6), the duty ratio D1 is given by: 𝐷1 = √2𝐶1𝑉𝑠𝑐2𝐼2𝑇 (2-8) Although this circuit has a relatively short voltage equalization time, the control pattern of the switches is complicated. 2.5 Single Switch Voltage Multiplier Topology The single switch voltage multiplier topology proposed in [33] is illustrated in Figure 2.9. In this circuit configuration, SC1 to SC3 are supercapacitors and C1* to C3* are reference capacitors whose voltages are also balanced during the equalization process. The inductor L1 in the circuit plays the role of a current source and the inductor L2 is placed to prevent a short circuit through diode Ds1. The diodes in the zigzag pattern transport the energy upward from the bottom of the circuit. 17 C3*SC3C2*SC2SC1DCL1L2C1*Ds1Dh1Ds2Ds3Dh2Dh3S Figure 2.9 Single switch voltage multiplier topology [33] When the switch S turns on, there is current flowing through the switch from the DC voltage source. The reference capacitors on the left-hand side are charged by the DC voltage source. There is a branch of balancing current flowing through the supercapacitors on the right-hand side to balance the voltages of the supercapacitors and the rest of current continues to flow upward to balance the voltage of the upper supercapacitors, as shown in Figure 2.10. SC1L1L2C1*iL1Ic1*Is Figure 2.10 Current flow during the on-state of the switch 18 When the switch turns off, the inductor distributes its stored energy to reference capacitor C1* through the diode Ds1, as shown in Figure 2.11. SC1L2C1*Ds1Dh1 Figure 2.11 Current flow during the off-state of the switch The voltages of the supercapacitors are applied across the reference capacitors through the diagonal diodes. With the flowing energy, all the voltages of reference capacitors can also be balanced. Although only one switch is used in the circuit and there is no necessity for voltage detection circuits since the energy transports from the bottom unit to the top unit automatically, this circuit suffers from the problem of a relatively long voltage equalization time. In addition, the switches and diodes suffer from high voltage and current stress. 2.6 Buck-boost Shunting Converter Topology The buck-boost shunting converter topology proposed in [34] is illustrated in Figure 2.12. In this circuit configuration, the supercapacitor string is charged by a constant current source I, which assists the process of charge transportation. Each supercapacitor in the string is connected in parallel with a buck-boost converter unit which plays the role of voltage equalization. Cr is a capacitor for temporary energy storage and it is connected with an additional buck-boost converter to retransfer its stored energy back to the current source. The 19 voltages of supercapacitors are measured by voltage detectors and then the measured voltages are compared with the average voltage of all supercapacitors. As long as the difference between the measured voltage and the average voltage exceeds a predetermined value, the corresponding buck-boost converter will be activated by the controller. SC4SC3SC2SC1D1D2D3D4CrS1S2S3S4L1L2L3L4DrSrLrI Figure 2.12 Buck-boost shunting converter [34] As an example, assuming supercapacitor SC1 has higher voltage than the others. Switch S1 is turned on to balance the voltage of SC1. The buck-boost converter shunting SC1 draws energy from SC1 and stores the energy in inductor L1. The current through the inductor increases linearly and reaches its peak current value when switch S1 is turned off. Then during the off-state of S1, the inductor releases its stored energy downstream to the other supercapacitors. Therefore, current flows out of the inductor and through SC2, SC3, SC4 and Cr. 20 When there are more supercapacitors that have higher than rated voltages, then the lower supercapacitor equalization circuits draw currents that are higher than the current provided by the constant current source. The current consists of the part of constant current source and the part dispensed from upper supercapacitors. Thus, the duty ratio of the lower supercapacitor units is larger than that of the upper units, and is given by: 𝐷 =𝐿𝑖𝑣𝑇 (2-9) However, the upper units have a higher decreasing rate of inductor current (𝑑𝑖𝑑𝑡=𝑣𝐿) than the lower units because they sustain higher reverse voltages when their corresponding switches turn off. The discharging current of a single supercapacitor can be expressed as: 𝐼𝑑𝑖𝑠 =1𝑇∫𝑉𝑡𝐿𝐷𝑇0𝑑𝑡 =12𝑉𝐷2𝑇𝐿 (2-10) And the current received by the remaining supercapacitors is given: 𝐼𝑟𝑒𝑐 =1𝑇(12𝑉𝑠𝑐 𝐷𝑇𝐿𝑉𝑠𝑐 𝐷𝑇(𝑁 − 𝑛 + 1)𝑉) (2-11) where Vsc stands for the individual voltage of a single supercapacitor, N is the total number of supercapacitors connected in a string and n is the sequence number of the supercapacitors. As an example of when there are more supercapacitors sustaining over-voltages, assume that SC1 and SC2 supercapacitor equalization units are activated. From the analysis above, the duty cycle of the circuit SC1 is less than that of the SC2 unit and therefore, switch S1 enters its off state before switch S2. There are three modes of operation for the converter unit. These are described in the following paragraphs. 21 In mode 1, switches S1 and S2 are turned on. As a result, the currents flowing into the inductors L1 and L2 increase linearly. In mode 2, switch S1 is turned off while switch S2 remains on. Consequently, the current flowing into inductor L1 decreases gradually while the current flowing into inductor L2 continues to increase. Either the current in the inductor L1 declines to zero before the instant when switch S2 is turned off or the inductor current becomes zero after the switching of S2. In mode 3, the stored energy in inductor L2 is transferred to capacitor Cr which accumulates the transported energy from the equalization units. When the stored energy exceeds the predetermined energy storage capacity value of capacitor Cr, capacitor Cr distributes its energy back to the supercapacitor string. The main advantage of this topology is its relatively low component count and cost. However, the switches suffer from high voltage stress and the control strategy for the switches is complex. 2.7 Selective Flyback Converter Topology The selective flyback converter topology proposed in [35] is illustrated in Figure 2.13. The input of the flyback transformer used in this topology is connected to each supercapacitor which is controlled by its own switch. The output of the converter is the total voltage of the supercapacitor string. Therefore, the entire topology is a pack-to-cell topology. 22 SC1SC2SC3S1pS1nS2pS2nS3pS3nD2pD3pT1D1 Lm D1pD2n Figure 2.13 Selective flyback converter topology [35] In this circuit configuration, each supercapacitor has a pair of switches and diodes connected to both the upper side and lower side of the transformer. The diode D(i+1)p connected in series with S(i+1)p is used to prevent the ongoing charging supercapacitor from being shorted when it is in the voltage balancing process. If D(i+1)p is removed, then Sip, Dip and the body diode of S(i+1)p would form a short circuit to the supercapacitor. The same principle can be applied for the connection of D(i+1)n. However, the top and bottom supercapacitors do not have adjacent supercapacitors connected on the upper side and lower side respectively. Consequently, diodes connected in series with these switches are not required. The circuit has two modes of operation which are described in the following paragraphs. 23 In mode 1, the voltage detector associated with each supecapacitor finds the higher voltage supecapacitor and the corresponding switches Sip and Sin are turned on. The supecapacitor voltage is applied to the transformer primary winding and the magnetizing inductor current in the transformer increases linearly until it reaches the preset peak current value, as given by: 𝑖𝐿𝑚(𝑡) =𝑉𝑠𝑐(𝑡 − 𝑡0)𝐿𝑚 (2-12) In mode 2, switch Sip remains turned on and switch Sin is turned off. The magnetizing inductor current is reflected to the secondary side of transformer and the diode D1 is forced to turn on. The reflected energy is transported back to the supercapacitor string. This mode ends when the reflected current becomes zero. The reflected current is given by: 𝑖𝑝𝑎𝑐𝑘(𝑡) =1𝑛[𝑖𝑝𝑘 −𝑉𝑝𝑎𝑐𝑘𝑛𝐿𝑚(𝑡 − 𝑡1)] (2-13) After mode 2, all the switches wait until another switching signal is generated. The main advantage of this topology is its fast speed to achieve voltage equalization. There is no necessity for external power sources due to the fact that the energy reflected from the primary side of the transformer can be delivered back to the supercapacitor string. It can also achieve voltage balancing with high efficiency due to the minimization of power flow paths. Nevertheless, the disadvantage is that the voltage stress and current stress for the switches and diodes are high. Apart from that, the magnetic losses in the circuit are high, which results in low efficiency of the circuit. 24 2.8 Half-bridge Multi-winding Output DC-DC Converter Topology The half-bridge multi-winding output DC-DC converter topology proposed in [36] is illustrated in Figure 2.14. SC1SC2D1bD1dD2bD2dC1C2Q1Q2D1D2LmD1aD1cD2aD2cI Figure 2.14 Half-bridge multi-winding output DC-DC converter topology [36] The topology consists of a multi-winding transformer and multiple diode bridge rectifiers. The multi-winding transformer has identical turns on the secondary windings to ensure the same ratio from the primary side to secondary side. The supercapacitor voltages are controlled by their own diode bridge rectifiers. The equalization current in the circuit flows through the lowest voltage supercapacitor in the string. This is because when the rectifier diodes in the bridge rectifiers for the lowest voltage supercapacitor conduct, the voltage of the lowest 25 voltage supercapacitor is applied across all secondary windings. For the other secondary windings, their voltages are less than their corresponding supercapacitor voltages, resulting in the blockage of rectifier diodes. When the lowest voltage supercapacitor reaches the voltage level of the second lowest supercapacitor, the rectifier diodes associated with these two supercapacitors are turned on to allow equalization current to flow through these two supercapacitors. The analogy can be extended for many supercapacitors in the string. There are four operation modes involved in the circuit. The circuit operation is explained in the following paragraphs. In mode 1, illustrated in Figure 2.18, switch Q1 is turned on and there is an inductor current flowing through Q1 into the dot of the primary winding and thus a positive voltage is applied to the primary winding of the multi-winding transformer. For a single unit such as SC1, diodes D1a and D1d in the diode rectifier are forced to turn on to allow the secondary reflected current to flow into supercapacitor SC1. The magnetizing inductor current on the primary winding increases gradually and supercapacitor SC1 is charged. 26 SC1SC2D1bD1dD2bD2dC1C2Q1Q2D1D2LmD1aD1cD2aD2cI Figure 2.15 Operational process of half bridge multi-winding transformer topology. Mode 1: circuit operation when Q1 is on. In mode 2, illustrated in Figure 2.18, switch Q1 is turned off. However, diodes D1a and D1d in the diode rectifier continue to conduct, which results in the commutation of the magnetizing inductor current. Since the magnetizing inductor current cannot change direction instantaneously, it freewheels through the body diode of switch Q2. The current reflected from the primary side still charges the corresponding supercapacitor SC1. At the end of this energy exchange process, the magnetizing inductor current returns to zero. 27 SC1SC2D1bD1dD2bD2dC1C2Q1Q2D1D2LmD1aD1cD2aD2cI Figure 2.16 Operational process of half bridge multi-winding transformer topology. Mode 2: circuit operation when D2 is on. In mode 3, illustrated in Figure 2.17, switch Q2 starts to conduct. Since the magnetizing inductor current becomes zero, Q2 conducts. The magnetizing inductor current flowing through Q2 comes out of the dot of the primary winding and thus a negative voltage is applied to the primary winding of multi-winding transformer. Therefore, diodes D1b and D1c are forced to conduct to allow the current reflected from the primary side to provide charge to the corresponding supercapacitor SC1. At the end of this energy exchange process, the magnetizing inductor current reaches its negative peak value. 28 SC1SC2D1bD1dD2bD2dC1C2Q1Q2D1D2LmD1aD1cD2aD2cI Figure 2.17 Operational process of half bridge multi-winding transformer topology. Mode 3: circuit operation when Q2 is on. In mode 4, illustrated in Figure 2.18 , switch Q2 turns off. However, diodes D1b and D1c in the diode rectifier continue to conduct. The magnetizing inductor current freewheels through the body diode of switch Q1. The current reflected from the primary side charges the corresponding supercapacitor. At the end of this energy exchange process, the magnetizing inductor current returns to zero to allow zero voltage switching for switch Q1 in the next switching cycle. 29 SC1SC2D1bD1dD2bD2dC1C2Q1Q2D1D2LmD1aD1cD2aD2cI Figure 2.18 Operational process of half bridge multi-winding transformer topology. Mode 4: circuit operation when D1 is on. The major advantage of this topology is that there is a relatively low number of switches. Furthermore, it can achieve voltage equalization in a relatively short time without the need for voltage detection circuits. However, the multi-winding transformer needs to be customized specifically in order to satisfy different configurations of series connected supercapacitors. Lastly, the circuit is extremely large when one hundred or more supercapacitors are connected in series. 2.9 Summary In this chapter, a comprehensive review of recent supercapacitor voltage balancing circuit topologies was presented. These topologies are used to provide a solution for the voltage imbalance of supercapacitors in the applications of electric vehicles applications. Although the 30 shunting resistor approach has a relatively simple structure and low cost and has been commonly used in vehicles already, it is unappealing since the equalization circuit dissipates excess energy in the circuit. In addition, very high thermal energy generated by the resistors reduces the lifetime of the supercapacitors. Therefore, several inductor and capacitor based circuits were presented, including single inductor converters, a bi-directional Cûk converter, a single switch voltage multiplier, a buck-boost shunting converter and several transformer based topologies, including the selective flyback transformer and half-bridge multi-winding DC-DC converters. These converters have the advantages of relatively fast voltage equalization speed and high efficiency. However, the relative costs and sizes of circuit package prohibit them from application in electric vehicles. 31 Chapter 3: Proposed Series Resonant LC Voltage Balancing Converter 3.1 Overview This chapter provides an outline of the proposed topology for the voltage equalization of supercapacitors. The chapter is arranged as follows. In Section 3.2, the major design constraints for developing new voltage equalization methods are explored. In Section 3.3, motivations for designing the new prototype are explained. In Section 3.4, the design of the new topology is presented along with a circuit analysis. In Section 3.5, an analysis of the circuit operation is presented. In Section 3.6, the voltage and current stress for different levels of switches are analyzed and evaluated. The conclusions are presented in Section 3.7. 3.2 Design Constraints Before designing a new voltage equalization converter, there are factors and constraints that need to be taken into account in order to achieve optimal performance and desired characteristics which include small package size, low cost, low weight, no need for customizing transformers for an arbitrary number of cells, a high degree of extendibility,and a fast voltage equalization speed. Correspondingly, the demerits consist of large package size, high cost and weight, complicated customized transformers for anarbitrary number of cells, lack of extendibility, and long voltage equalization time. Although some of the existing topologies reviewed in Chapter 2, have some of the above mentioned desired characteristics, each has drawbacks as well. 3.3 Motivation for Topology Design The size of the voltage equalization converter circuit package is a critical issue in electric vehicle applications. Generally, transformer-based converters have a larger size than non- 32 isolated converters. Capacitor-based converters typically have smaller package sizes, but the voltage equalization process is sluggish, i.e. typically 5 hours [37]. In order to design a voltage equalizer with relatively smaller size and faster voltage balancing speed, inductive elements can be added to capacitor-based converters. Since sizes of reactive components can decrease by increasing the switching frequency, the optimal strategy to reduce the size of the entire package for voltage balancing circuits is to increase the switching frequency of the circuit. However, when switches are operating at high frequencies, switching losses become significant. This results in lower energy efficiency of the circuit, and therefore less energy is recovered from high voltage cells to transfer to low voltage cells. In order to lower switching losses in the circuit, resonant circuits can be used. Resonant converters have been used in various applications such as switch mode power supplies and power factor correction circuits. A resonant converter includes a resonant tank which consists of inductors and capacitors. The benefits of resonant converter include its high efficiency, reduced volume of inductive elements and reduced electro-magnetic interference (EMI) effects. A resonant circuit can be operated in three frequency ranges, at the resonant frequency, above the resonant frequency or below the resonant frequency. Nearly lossless, soft switching is a key benefit of resonant converters. Zero voltage switching and zero current switching are two types of soft switching. To achieve zero current switching, the switching frequency must be below the resonant frequency, where the capacitive impedance dominates the circuit. When the circuit is operating at a switching frequency above the resonant frequency, the inductor current lags the resonant tank voltage of the circuit. Therefore, the lagging current can discharge the switch parasitic capacitances down to zero volts before the switch is turned on, allowing for the current to flow with zero voltage and 33 hence achieve zero voltage switching. This means that the sinusoidal waveform of the inductor current lags the fundamental portion of the square waveform of the voltage. Hence, there is almost no switching loss generated during the turn on of MOSFET switches. 3.4 The Proposed Voltage Equalizer Circuit The proposed series LC resonant voltage equalizer is illustrated in Figure 3.1. This voltage equalizer consists of a series LC resonant converter which is connected to each supercapacitor in the string (SC1, SC2… SCn) by a group of four switches. MOSFET switches are used in the proposed topology because of their capability of high frequency operation and easy usage. CrS11S14S22S24S21S23Sn2Sn1Sn4Sn3S12S13LrABSC1SC2SCnDcwDccw1Dccw2 Figure 3.1 Proposed supercapacitor voltage equalization converter 34 During the voltage balancing process, the group of four switches corresponding to each supercapcitor cell can provide bidirectional energy paths which effectively reduce the voltage equalization time. The two series connected switches in each circuit level are source connected. This is because all the switches at different circuit levels should be triggered on and off by different isolated gate drivers. If all the switches are connected in the manner that the drain of one switch is connected to the source of another switch, the total number of isolated gate drivers will increase significantly. The common source connection of switches renders the usage of only one isolated gate driver on each circuit level. The gate signal from a single gate driver can be applied to the gate of two switches simultaneously, triggering them on and off, thereby providing an energy flow path. The anti-series switches are used to prevent body diode conduction since low voltage MOSFETs cannot block a negative voltage due to the MOSFET intrinsic body diode. Lastly, three diodes Dcw, Dccw1, Dccw2, are configured in series and parallel with the LC resonant tank in order to provide a continuous flowing path for the resonant inductor current. In the existing solutions, excessive capacitor energy is successively transported up the string of series supercapacitors from one to the next, which increases balancing time and leads to the potential for over-voltage on an intermediate cell. However, in the proposed circuit, energy can be transported directly from the source supercapacitor to the target supercapacitor through the single resonant converter. This is because in most practical cases, not all supercapacitors connected in the string have departed voltages from the desired voltage level. Some supercapacitors might have approximately the same voltage as the rated voltage when they are charged and hence, there is no necessity to equalize their voltages. Therefore, only the cells with out of tolerance voltages should have their voltages equalized. 35 The proposed circuit structure enables supercapacitor voltage equalization selectively by accurate voltage detection. The single LC resonant tank performs the similar function as the transformer in the designs presented in Chapter 2 by providing energy transfer paths among the supercapacitors connected in isolation. In contrast to transformer based schemes, the single resonant tank reduces the converter cost sharply and enables a potentially smaller package. In the case where hundreds of supercapacitors are series connected, the scheme can be conveniently modified by adding additional sets of switches in parallel with existing levels of switches instead of adding extra windings of transformers as in the transformer based topologies. In order to further minimize the voltage equalization time, the switching frequency is set to be close to the resonant frequency, where the impedance of the converter reaches its lowest value and therefore higher current can be achieved in the energy flow path in each switching cycle. This results in more energy transported in each switching cycle and therefore a shorter voltage balancing time can be expected. When the higher voltage supercapacitor and the lower voltage supercapacitor are selected in the string by a voltage detection circuit, the switches associated with the higher voltage supercapacitor are triggered on resulting in charge flowing from this supercapacitor to the series LC resonant tank. The resonant tank stores the energy transported from the high voltage supercapacitor temporarily and releases the energy to the lower voltage supercapacitor to increase its voltage in the second phase of the switching cycle. 36 3.5 Voltage Equalization Operation Since in the general case, the proposed voltage equalizer only balances the two supercapacitors with the greatest voltage difference, the proposed voltage equalization circuit operation is presented for two cells. The following analysis is conducted assuming that supercapacitors SC1 and SCn have voltage values where VSC1 is greater than VSCn. The circuit operation for the proposed converter can be divided into four modes, described in the following paragraphs. The waveforms for all four modes are provided in Figure 3.2. 37 iLrVcrVscGate1Gate2HighLowHighLow0.5TDead timettttHighHighLowLow1.5TDead timeTDead time2TDead timettVES1VESnMode 1Mode 2Mode 3Mode 4 Figure 3.2 Analytical waveforms of resonant capacitor voltage, resonant inductor current and supercapacitor voltages in four modes. Figure 3.3 illustrates the equivalent circuit during mode 1. 38 SC1SC2SCnS11S14S22S24S21S23Sn2Sn1Sn4Sn3S12S13 CrLrABDccw1DcwDccw2 Figure 3.3 Current flowing paths of the proposed converter. Mode 1: Energy transportation from high voltage supercapacitor to LC resonant equalization converter. During the first half switching cycle, since the voltage of SC1 is higher than that of SCn, all four switches associated with SC1 are turned on.Therefore, SC1 is connected to the LC resonant tank directly. The charging current flows through the resonant inductor and capacitor, resulting in an increase of the resonant inductor current and resonant capacitor voltage. When the resonant capacitor voltage reaches the same voltage level as the supercapacitor SC1, the voltage across the resonant inductor becomes zero, and the current flowing through the inductor reaches its positive peak value. After this critical point, supercapacitor SC1 continues to charge the resonant capacitor and the SC1 voltage is less than the resonant capacitor voltage. Therefore, the voltage across the resonant inductor is now negative. This negative voltage 39 contributes to a gradual decrease of the inductor current. At the moment when all the switches connected to supercapacitor SC1 are turned off, mode 2 begins. The equivalent circuit during mode 2 is illustrated in Figure 3.4. CrSC1SC2SCnS11S14S22S24S21S23Sn2Sn1Sn4Sn3S12S13LrABDccw1DcwDccw2 Figure 3.4 Current flowing paths of the proposed converter. Mode 2: Energy flowing paths when resonant inductor releases its stored energy. In mode 2, since the inductor current cannot change its direction immediately, diode Dcw is forced to be on in order to provide a path for the resonant inductor current. When the inductor current returns to zero, the resonant capacitor voltage reaches its positive peak value. The resonant capacitor holds this voltage until the beginning of the next half of the switching cycle, as illustrated in Error! Reference source not found.. The equivalent circuit during mode 3 is illustrated in Figure 3.5. 40 SC1SC2SCnS11S14S22S24S21S23Sn2Sn1Sn4Sn3S12S13 CrLrABDccw1DcwDccw2 Figure 3.5 Current flowing paths of the proposed converter. Mode 3: Energy transportation from equalization converter to low voltage supercapacitor. This mode begins when the switches associated with supercapacitor SCn conduct. During the second half of switching cycle, the energy transport direction is reversed. The resonant capacitor releases all its reserve energy to supercapacitor SCn. The resonant inductor current flows in the opposite direction, gradually bringing its voltage back to zero. When the resonant capacitor voltage reaches the same level as supercapacitor SCn, the resonant inductor current reaches its negative peak. Then the resonant capacitor voltage further decreases, resulting in a low current flowing in the circuit. When the switches associated with supercapacitors SCn are turned off, mode 4 begins. The equivalent circuit during mode 4 is illustrated in Figure 3.6. 41 CrSC1SC2SCnS11S14S22S24S21S23Sn2Sn1Sn4Sn3S12S13LrABDccw1DcwDccw2 Figure 3.6 Current flowing paths of the proposed converter. Mode 4: Energy flowing paths when resonant inductor releases its stored energy in the opposite direction. The resonant inductor current still cannot change its direction and therefore it forces the conduction of diodes Dccw1 and Dccw2. The resonant inductor current flows through diode Dccw1, the supercapacitor string and diode Dccw2 back to resonant capacitor. The analysis of the circuit operation for mode 3 and 4 is similar to the analysis in the first half of the switching cycle, i.e. modes 1 and 2. This energy transport process continues in successive switching cycles until the voltage difference of the two supercapacitors reaches a pre-selected target value. 42 3.6 Mathematical Analysis of the Proposed Circuit During a switching cycle, the supercapacitor voltages are changing. However, the voltage variations are small and can be assumed to be constant during one switching cycle. The following analysis assumes that the resistance in the circuit can be neglected. During the first half of the switching duty cycle, the LC resonant tank is connected to SC1 in order to receive charge. The voltage across the resonant inductor is the voltage difference between supercapacitor SC1 and capacitor Cr. The resonant inductor voltage is given by: 𝐿𝑟𝑑𝑖𝑟𝑑𝑡= 𝑉𝑆𝐶1 − 𝑉𝐶𝑟 (3-1) The resonant inductor current is given by: 𝑖𝑟 = 𝐶𝑟𝑑𝑉𝐶𝑟𝑑𝑡 (3-2) Combining (3-1) and (3-2), a second order LC differential equation is given by: 𝐿𝑟𝐶𝑟𝑑2𝑉𝑐𝑟𝑑𝑡2+ 𝑉𝐶𝑟 = 𝑉𝑆𝐶1 (3-3) The general solution for the differential equation is: 𝑉𝑐𝑟 = 𝐴1 cosωt + 𝐴2 sinωt + 𝑉𝑠𝑐1 (3-4) The initial condition for the resonant capacitor voltage at the instant t0 is, 𝑉𝐶𝑟(𝑡0) = 𝑉𝑖 , and the initial condition for the resonant inductor current is, 𝑖𝑟(𝑡0) = 0. Therefore, the terms 𝐴1 and 𝐴2 are given by: 𝐴1 = (𝑉𝑖 − 𝑉𝑠𝑐1) cosω𝑡0 (3-5) 𝐴2 = (𝑉𝑖 − 𝑉𝑠𝑐1) sinω𝑡0 (3-6) 43 Substituting these two constants into equation(3-4), the resonant capacitor voltage can be expressed as: 𝑉𝐶𝑟 =(𝑉𝑖 − 𝑉𝑆𝐶1) 𝑐𝑜𝑠ωt𝑐𝑜𝑠ω𝑡0 + (𝑉𝑖 − 𝑉𝑆𝐶1)𝑠𝑖𝑛ω𝑡𝑠𝑖𝑛ω𝑡0 + 𝑉𝑆𝐶1 =(𝑉𝑖 − 𝑉𝑆𝐶1) 𝑐𝑜𝑠ω(t − 𝑡0) + 𝑉𝑆𝐶1 The resonant current is given by : (3-7) 𝑖𝑟 = (𝑉𝑖 − 𝑉𝑆𝐶1) 𝐶𝑟ω𝑠𝑖𝑛ω(t − 𝑡0) (3-8) In the beginning of the second half of the switching cycle, switches S11, S12, S13, S14 are turned off and switches Sn1, Sn2, Sn3, Sn4 are turned on. In this case, the resonant tank is connected to SCn instead of SC1. The stored charge is delivered from the resonant tank to supercapacitor SCn to increase its voltage. The voltage across the resonant inductor is the voltage difference between supercapacitor SC2 and capacitor Cr. Similarly, a second order LC differential equation can be derived as: 𝐿𝑟𝐶𝑟𝑑2𝑉𝑐𝑟𝑑𝑡2+ 𝑉𝐶𝑟 = 𝑉𝑆𝐶2 (3-9) The solution for the differential equation is: 𝑉𝐶𝑟= 𝐴1𝑐𝑜𝑠ωt + 𝐴2𝑠𝑖𝑛ω𝑡+𝑉𝑆𝐶2 (3-10) The initial voltage for the resonant capacitor at the instant t1 is 𝑉𝐶𝑟(𝑡1) = 𝑉𝑝 , and the initial current for the resonant inductor is 𝑖𝑟(𝑡1) = 0. Therefore, the constants of the differential solution are given by: 𝐴3 = (𝑉𝑝 − 𝑉𝑆𝐶2) 𝑐𝑜𝑠ω𝑡1 (3-11) 44 𝐴4 = (𝑉𝑝 − 𝑉𝑆𝐶2)𝑠𝑖𝑛ω𝑡1 (3-12) Substituting these constants into equation (3-10), the resonant capacitor voltage is given by: 𝑉𝐶𝑟 =(𝑉𝑝 − 𝑉𝑆𝐶2) 𝑐𝑜𝑠ωt𝑐𝑜𝑠ω𝑡1 + (𝑉𝑝 − 𝑉𝑆𝐶2)𝑠𝑖𝑛ω𝑡𝑠𝑖𝑛ω𝑡1 + 𝑉𝑆𝐶2 =(𝑉𝑝 − 𝑉𝑆𝐶2) 𝑐𝑜𝑠ω(t − 𝑡1) + 𝑉𝑆𝐶2 The resonant current is given by : (3-13) 𝑖𝑟 = (𝑉𝑝 − 𝑉𝑆𝐶2) 𝐶𝑟ω𝑠𝑖𝑛ω(t − 𝑡1) (3-14) Based on the above mathematical analysis, it can be seen that when the equalizer starts to compensate voltages, the voltage of the resonant capacitor is its initial voltage 𝑉𝑖. After one quarter of the switching period, the resonant capacitor voltage reaches 𝑉𝑆𝐶1, the same voltage level of discharged supercapacitor. When half of the switching period passed, that is, ω(t −𝑡0)=𝜋, the resonant capacitor voltage becomes 2𝑉𝑆𝐶1 − 𝑉𝑖 . When ω(t − 𝑡1)=3𝜋2 , the resonant capacitor voltage reaches 𝑉𝑆𝐶1 again. Therefore, the resonant capacitor has a sinusoidal oscillating voltage waveform with a positive peak value of 2𝑉𝑆𝐶1 − 𝑉𝑖 and a negative peak value of 𝑉𝑖. 3.7 Analysis of the Equivalent Circuit The equivalent circuit of the charging, or discharging process can be derived as a simple resistor-inductor-capacitor network with a supercapacitor as the main voltage source. Figure 3.7 illustrates the equivalent circuit model. 45 Lr CrABR total Figure 3.7 Equivalent circuit during energy transportation process. The impedance of the circuit is given by: 𝑍 = 𝑅𝑡𝑜𝑡𝑎𝑙 + 𝑗𝑤𝐿𝑟 +1𝑗𝑤𝐶𝑟 (3-15) where Rtotal is the total resistance of the circuit, which includes the on time resistance of the MOSFET switches, the internal resistance of the resonant inductor, the internal resistance of the resonant capacitor, and the resistance of the supercapacitors. Therefore, the magnitude of the impedance is given by: |𝑍(𝑓)| = √𝑅𝑡𝑜𝑡𝑎𝑙2 + (2𝜋𝑓𝐿𝑟 −12𝜋𝑓𝐶𝑟)2 (3-16) where F is the frequency in Hertz. Since the resistance, inductance and capacitance are all known parameters with fixed values, the impedance is dependent only on the circuit switching frequency. The impedance of the equivalent circuit can be changed by modifying the frequency of the resonant tank voltage, which is controlled by the frequency of the MOSFET switches supplying the voltage waveform of the supercapacitors to the resonant tank. 46 3.8 Fourier Analysis of Resonant Inductor Current When the proposed converter operates, the voltage across the resonant tank is equal to the voltage of the supercapacitors. In the case where Vsc1 and Vscn are applied to the resonant tank separately, the voltage of the resonant tank is Vsc1 for almost half of the switching cycle and Vscn for the other half of the switching cycle, as shown in tVABV 1Vscnt t(Vsc1 + Vscn) / 2(Vsc1 – Vscn) / 2(Vscn – Vsc1) / 2= +VAB VABTVsc1Vscn Figure 3.8. A short dead time is added between the switching transitions from the set of switches controlling SC1 and the set of switches controlling SCn. This dead time is negligible in the analysis of the equivalent circuit. Therefore, in a switching cycle, a pulsing voltage is applied to the resonant tank. This pulsing voltage consists of two components, one is a constant voltage with its magnitude equal to average voltage of the two supercapacitors, and a square wave with an amplitude that is the same as the voltage difference between the two supercapacitors. tVABVsc1Vscnt t(Vsc1 + Vscn) / 2(Vsc1 – Vscn) / 2(Vscn – Vsc1) / 2= +VAB VABTVsc1Vscn Figure 3.8 Decomposition of resonant tank ladder waveform. 47 Since the average voltage across the resonant inductor is zero in the steady state, the constant voltage component is solely applied to the resonant capacitor. Therefore, only the square wave voltage is applied to the resonant inductor. Using a Fourier series for the square voltage, it is clear that it consists of a DC component and multiple AC components including a fundamental component at the switching frequency and higher order harmonics, as given by: V(t) = a0 +∑(an cosn2πtT+bn sinn2πtT) ∞n=1 (3-17) The coefficient a0 represents the DC component and can be calculated as: a0 =1𝑇∫ 𝑉(𝑡)𝑑𝑡𝑇0 =1𝑇∫ 𝑉𝑠𝑐1𝑑𝑡0.5𝑇0 + 1𝑇∫ 𝑉𝑠𝑐𝑛𝑑𝑡𝑇0.5𝑇 = 𝑉𝑠𝑐1+𝑉𝑠𝑐32 (3-18) The coefficient an can be calculated as follows: an =2𝑇∫ 𝑉(𝑡) cosn2πtT𝑑𝑡𝑇0 = 2𝑇∫ 𝑉𝑠𝑐1 cosn2πtT𝑑𝑡0.5𝑇0+2𝑇∫ 𝑉𝑠𝑐𝑛 cosn2πtT𝑑𝑡𝑇0.5𝑇 = 0 (3-19) Similarly, coefficient bn can be calculated as follows: bn =2𝑇∫ 𝑉(𝑡) sinn2πtT𝑑𝑡𝑇0 = 2𝑇∫ 𝑉𝑠𝑐1 sinn2πtT𝑑𝑡0.5𝑇0+2𝑇∫ 𝑉𝑠𝑐𝑛 sinn2πtT𝑑𝑡𝑇0.5𝑇 (3-20) 48 = 2𝑉𝑠𝑐1− 2𝑉𝑠𝑐𝑛𝑛𝜋 Although the pulsating voltage waveform is applied to the resonant tank, only a sinusoidal waveform of resonant inductor current appears in the resonant tank since the resonant tank converter acts as a tuned filter and removes all the higher order harmonic components. Therefore, only the fundamental component significantly contributes to the formation of the resonant inductor current waveform and energy transport process. Therefore, only coefficient b1= 2𝑉𝑠𝑐1− 2𝑉𝑠𝑐𝑛𝜋 is significant in the analysis. Coefficient b1 represents the peak value of the inductor voltage. The RMS value of the resonant inductor voltage is given by: 𝑉𝑟𝑚𝑠 =√2𝑉𝑠𝑐1 − √2𝑉𝑠𝑐𝑛𝜋 (3-21) Since the impedance of the circuit is given by (3-16), the peak and RMS values of the resonant inductor current can be derived as given by (3-22) and Error! Reference source not found., respectively. Since all parameters in these two equations are known, the peak and RMS values are easily calculated. These values are significant in the selection of the resonant inductor and MOSFET switches. 𝐼𝑝𝑒𝑎𝑘 =2𝑉𝑠𝑐1 − 2𝑉𝑠𝑐𝑛𝜋√𝑅𝑡𝑜𝑡𝑎𝑙2 + (𝑤𝐿𝑟 −1𝑤𝐶𝑟)2 (3-22) 𝐼𝑟𝑚𝑠 =√2𝑉𝑠𝑐1 − √2𝑉𝑠𝑐𝑛𝜋√𝑅𝑡𝑜𝑡𝑎𝑙2 + (𝑤𝐿𝑟 −1𝑤𝐶𝑟)2 Error! Reference source not found. 49 3.9 Component Stress Analysis The switches on the different levels within the circuit have the same current stress ratings. The current flowing through each switch equals the current flowing through the resonant tank. However, for the switch voltage stress, special attention should be paid to the top group and bottom group of switches. If there are only three supercapacitors connected in series, most of the switches withstand only one supercapacitor voltage. But for the top level group and bottom level group of switches, they need to withstand the voltages of the series supercapacitors. The voltage stress for the different levels of switches for a three supercapacitor topology is provided in Table 3.1. Table 3.1 Voltage stress for MOSFET switches in different switch conduction periods From the table shown above, general conclusions can be drawn for a case with N series connected supercapacitors. When top level switches S11, S12, S13, S14 are on, the voltage stress for the bottom level switches SN1, SN2, SN3, SN4 is (N-1) times the series connected supercapacitor voltage, i.e. (N-1) VSC. When the bottom level switches SN1, SN2, SN3, SN4 are on, the voltage stress for the top level switches S11, S12, S13, S14 is also (N-1) times the series connected supercapacitor voltage (N-1)VSC. S11, S12, S13, S14 turn on Voltage Stress for S21, S22 Voltage Stress for S23, S24 Voltage Stress for S31, S32 Voltage Stress for S33, S34 VSC1 VSC2 VSC1+VSC2 VSC2+VSC3 S21, S22, S23, S24 turn on Voltage Stress for S11, S12 Voltage Stress for S13, S14 Voltage Stress for S31, S32 Voltage Stress for S33, S34 VSC1 VSC2 VSC2 VSC3 S31, S32, S33, S34 turn on Voltage Stress for S11, S12 Voltage Stress for S13, S14 Voltage Stress for S21, S22 Voltage Stress for S23, S24 VSC1+VSC2 VSC2+VSC3 VSC2 VSC3 50 However, for the rest of the switches, if the series connected supercapacitor number is an odd number and the sequence number counting from the top is less than 𝑁+12, then the stress for that pair of switches is (𝑁 − 𝑛)VSC. Otherwise, the stress is (𝑛 − 1)VSC. On the other hand, if the number of series connected supercapacitors is even and the sequence number counting from the top is less than 𝑁2, then the stress for that pair of switches is (𝑁 − 𝑛)VSC. Otherwise, the stress is (𝑛 − 1)VSC. 3.10 Voltage Equalization Realization Algorithm In order to equalize supercapacitor voltages in the string, an algorithm is necessary to select which supercapacitors are to be connected to the equalization converter. The voltage equalization control process is illustrated in Figure 3.9. First, the voltages of supercapacitors are measured by voltage measurement devices. Second, the control device arranges the voltages in descending order. Then the process enters into a repetitive loop by selecting the highest voltage and lowest voltage first. If the highest voltage is larger than the rated voltage, then the switches corresponding to the highest voltage supercapacitor and lowest voltage supercapacitor should be activated to redistribute the charge on these two supercapacitors. If the highest voltage is below the rated voltage, then the voltage difference is calculated by the controller. If the voltage difference between the highest and lowest voltage supercapacitors is within an allowable range, e.g. 20mV, then there is no need to equalize the voltages of all the supercapacitors and the voltage equalization process completes. Otherwise, the corresponding switches are activated until the allowable voltage difference is reached. 51 Mesure and arrange supercapacitor voltages in order Compare voltages with rated voltageFind supercapacitors with highest and lowest voltage Voltage difference is within allowable rangeEnable switches of highest voltage supercapacitor and lowest voltage supercapacitorVoltage equalization process terminatesYNHighest voltage is higher than rated voltageYN Figure 3.9 Algorithm for voltage equalization process If three series supercapacitors are used as an example, then the detailed voltage equalization algorithm is provided in Figure 3.10. The allowable voltage difference is set to 10 mV. This example algorithm follows the general process outline in Figure 3.9. The algorithm works to successfully equalize all cells and terminates when all cells are within 10 mV of each other. 52 Supercapacitor voltages V1, V2, V3 are obtained Voltage equalization process endsV1>V2Y NV2>V3V1>V3Activate switches controlling SC1 and SC3NActivate switches controlling SC1 and SC2NActivate switches controlling SC3 and SC2V1>V3NActivate switches controlling SC2 and SC3V2>V3Activate switches controlling SC2 and SC1NActivate switches controlling SC3 and SC1Highest voltage -lowest voltage > 0.01VNYHighest voltage > rated voltageYN Figure 3.10 Detailed algorithm for the proposed three supercapacitor voltage equalization process. 3.11 Summary In this chapter, the proposed topology for voltage balancing of supercapacitors has been introduced. A theoretical analysis of the circuit component waveforms in different operational intervals is included. A mathematical analysis based on the equivalent circuit of the proposed converter was developed and a theoretical analysis of the inductor current waveform is included. The voltage stress analysis for each level of switches has also been presented, which is required for MOSFET switch selection. 53 Chapter 4: Simulation and Experimental Results 4.1 Overview In this chapter, simulation and experimental results are presented in order to verify the functionality of the proposed voltage equalization converter. The chapter is arranged as follows. Simulation results are presented in Section 4.2. In Section 4.3, the experimental hardware prototype is presented and the components used for the prototype are detailed explained. Experimental waveforms that verify the performance of the converter are presented and evaluated. A conclusion is drawn based on performance of the simulated and experimental waveforms in Section 4.4. 4.2 Simulation Results In order to verify the validity of the theoretical analysis in the previous chapter, a simulation analysis was conducted using the power electronics simulation software PSIM 9.3.2 from Powersim Technologies. A three-supercapacitor voltage equalization converter system model was built for the topology. The simulation schematic is provided in Figure 4.1. Each of the three supercapacitors had a capacitance of 300 F and the voltages of SC1, SC2 and SC3 were initially set to 2.50V, 2.30V and 2.00V, respectively. The sets of switches were controlled by pulse width modulation signals with a duty cycle of 49% each. In each switching period, only two sets of switches were operated. These two sets of switches were manipulated by complementary signals. A dead time of 1% of the switching period was selected to provide a path for the resonant inductor current between the complementary switching actions. The resonant inductor was selected to be 2.2 µH and the resonant capacitor value was 10 µF. The initial voltage of the resonant capacitor was set to zero. Therefore, the resonant frequency was 54 33.9 kHz calculated, using 𝑓𝑟 =12𝜋√𝐿𝑟𝐶𝑟. In order to operate near resonance, the switching frequency was set to 34 kHz. C block control Figure 4.1 Simulation diagram for the three supercapacitor voltage equalization topology. The simulated waveform for the resonant inductor current is provided in Figure 4.2. As can be observed, the waveform is sinusoidal, which means only the fundamental component in the resonant tank voltage significantly contributes to the resonant current. This matches the theoretical analysis presented in the previous chapter regarding resonant tank voltage Fourier series decomposition. This can be further verified by the Fast Fourier Transform (FFT) of the current waveform, as illustrated in Figure 4.3. In the resonant inductor current FFT results, the fundamental component of resonant inductor current is 1.72 A, while the other odd 55 components of the waveform including the third, fifth and seventh-order harmonics are 530 µA, 170 µA and 77 µA, respectively. The fundamental component is more than three orders of magnitude higher than the harmonics, and therefore, it is clearly the dominant component. Figure 4.4 shows the general longer duration (i.e. four switching cycles) changing behavior of the resonant inductor current. The initial peak value of the resonant inductor current is 3.5 A. This peak value gradually decreases cycle by cycle through the rebalancing process. When the voltage equalization process completes, the value of the resonant inductor current is zero, which means there is no charge transport in the circuit, since there is no voltage difference between the supercapacitors. 1.7A Figure 4.2 Simulation waveform of resonant inductor current. 56 1.72A0.00053A 0.00017A Figure 4.3 FFT analysis of resonant inductor current. 3.5A Figure 4.4 General changing behavior of resonant inductor current. The simulation waveform of the resonant capacitor voltage is provided in Figure 4.5. As can be observed, the resonant capacitor voltage is also sinusoidal with its average voltage being nearly equal to average voltages of all the supercapacitors, which is 2.25V in this example. 57 The highest and lowest values of resonant capacitor sinusoidal voltage occur exactly when the resonant inductor current reaches zero, as the current leads the voltage by 90 degrees. 2.25V Figure 4.5 Simulation waveform of resonant capacitor voltage. Figure 4.6 shows the current waveform for two MOSFET switches. As can be observed, since the directional definition of the MOSFET switch current is from drain to source, one of the common source connected switches on the same circuit level has a negative current, but with the same waveform shape and magnitude. The MOSFET switch waveform for the same circuit level switches is only half of the resonant inductor current waveform since they only conduct for half of the switching cycle. 58 1.7A Figure 4.6 Simulation waveform of MOSFET switch current. Figure 4.7 shows the simulation waveform of the MOSFET switch voltages for the highest and lowest level converters. The voltage across the switches at the higher circuit level is the voltage sum of supercapcitor SC1 and SC2, which is 4.8V. The voltage of the switches at lower circuit level is the voltage sum of supercapcitor SC2 and SC3, which is 4.3V. 59 4.8V(a) 4.3V(b) Figure 4.7 Simulation waveforms of a single set of MOSFET switch voltages at different circuit level. (a) Voltage waveforms of higher circuit level switches. (b) Voltage waveforms of lower circuit level switches. 60 The voltage equalization trend is illustrated in VSC1VSC2VSC3Figure 4.8. The initial voltage difference of 500 mV between the most deviated supercapacitors SC1 and SC3 is reduced to 10 mV at 600 seconds. VSC1VSC2VSC3Figure 4.8 Simulation waveform of voltage equalization process. 61 4.3 Experimental Results The proposed voltage equalization circuit was built and tested experimentally for three series connected supercapacitors. A photo of the prototype is provided in Figure 4.9. The supercapacitors were assembled on a perforated board and were connected to a printed circuit board using 14 gauge wires. The connectors between the perforated board and the PCB allow a flexible disconnection between charged supercapacitors and the converter board. MOSFET switchResonant tankGate drive converter Figure 4.9 Photograph of the proposed circuit board prototype for supercapacitor voltage equalization. The components were selected using the voltage and current ratings from the simulation results. Table 4.1 shows the key circuit components selected for the prototype. 62 Table 4.1 Proposed converter component list Component Value Supercapacitor SC1-SCn Cooper Bussman PowerStor capacitors, 300 F Resonant inductor Lr 2.2 µH (XAL5030MEB) Resonant capacitor Cr 10 µF (12063D106KAT2A) MOSFET switches S11-Sn4 N-Ch MOSFET switches IRF8721, Ron = 8.5 mΩ Three Cooper Bussman PowerStor supercapacitors, XB3550, were selected because of their low capacitance tolerance of +/- 10%, low equivalent series resistance of 7 mΩ and wide operating temperature range of -25°C to 70°C. The capacitance for each supercapacitor is 300F and the rated voltage is 2.5V. Their surge voltage is 2.85V for 1 second. For supercapcitor voltage detection, AD629 difference amplifiers from Analog Devices were used. This unity gain difference amplifier can convert differential voltages into single ended signals accurately under very high common-mode voltages. The resonant inductor was selected to be 2.2 µH and the resonant capacitor was 10 µF. For the purpose of the converter performance comparison between simulation results and experimental results, the voltages of the supercapacitors were pre-charged to the same voltage level as the voltages in the simulation. The initial voltages for the three supercapacitors were therefore 2.5V, 2.3V and 2.0V, respectively. The MOSFET switches used in the design were IRF8721 from International Rectifier. These switches were selected because of their low drain-to-source resistance, Rds, typically 8.5 mΩ and low gate charge, 8.3 nC at Vgs= 4.5V. For the N-type MOSFET switches, the threshold 63 voltage varies between 0.7 and 1V. The MOSFETs can be turned on by applying a gate to source voltage, Vgs, higher than the threshold voltage. For the proposed topology, two MOSFET switches in each circuit level have their sources connected. The drains of the switches are connected to a supercapacitor at one end and the LC resonant tank at the other. This common source connection allows for the use of only one gate drive circuit. The switches connected on different circuit levels have floating grounds. The gate drivers for different circuit levels of switches require different voltage supplies and the reference points of these voltage supplies should be isolated from the sources of the switches they control. In this design application, since multiple power supplies are undesirable in practice, isolated voltage supplies were used to provide floating gate driver voltages. The isolated voltage supplies are obtained using isolated DC-DC converters, TMR3-1223 from Traco Power. These DC-DC converters provide electrical isolation up to 1500 V. They can be powered by variable input voltages from 9V to 18V and the output voltage of the converters is fixed to 15 V. For the gate driver selection, the control signals and power signals should be isolated. An ACPL-H312 gate drive optocoupler was selected due to its wide input operating voltage range, high switching speeds and high common-mode rejection voltage. It has high output peak current, up to 2.5 A. In the circuit, six isolated DC-DC converters were all powered by a DC voltage supply with at 15 V. The outputs of the DC-DC converters were all voltages regulated to 15V, which is within the recommended operating voltage supply ratings of the gate drive optocouplers. A gate resistance was placed between the gate of the MOSFET switch and the output of the gate 64 driver. Generally, gate resistance cannot be high because switching speed will be limited. However, the gate resistance cannot be too low, otherwise the electrical magnetic interference (EMI) generated can become unacceptably high. The gate resistance was selected to limit the peak gate current below the maximum current of the gate driver. Based on the design specification, the gate resistance was required to be at least 15 V/ 2.5 A= 6 Ω. Using a 50% safety margin, 10 Ω gate resistors were used. The voltage equalization control circuit was realized by an AVR ATmega328 microcontroller. This microcontroller has an advanced 20 MIPS architecture with six channel, 10-bit analog to digital converter (ADC). In the application of supercapacitor voltage equalization circuit, the voltages of the supercapcacitors have two terminals with positive leads on the top and negative leads at the bottom. Consequently, these double ended supercapacitor voltages should be modified to suit the input of the microcontroller. In the design, the double ended voltages are first converted into single ended voltages using unity gain differential amplifiers. The outputs of the unity gain differential amplifiers were connected to three of the six ADC converter units in the microcontroller, transferring the sensed single-ended signals into the inputs of the ADC converter units. There are also six digital PWM output channels in the microcontroller. Each of the six PWM channels has controllable duty cycles, phase differences, and frequencies. The main function of the microcontroller is to sense the supercapacitor voltages and then make comparisons between the values of the supercapacitor voltages. When the microcontroller finds the highest voltage supercapacitor and lowest voltage supercapacitor, a decision is made inside the microcontroller regarding which set of MOSFET switches should be operated. If the voltage difference between the highest voltage supercapacitor and lowest 65 voltage supercapacitor is smaller than 10 mV, the switches in the equalization converter are not required to operate. The microcontroller should apply a command to terminate PWM signal generation. Control signals are generated on the basis of the final decisions made and sent to the inputs of the corresponding gate drivers, allowing the control of the MOSFET switches. The experimental measured resonant inductor current and resonant capacitor voltage waveforms are illustrated in Figure 4.10 and Figure 4.11, respectively. The waveform for the resonant inductor current is sinusoidal, with zero average value, matching the simulation results. The waveform of the resonant capacitor voltage is also sinusoidal with its average voltage being the average supercapacitor voltage of those being balanced, e.g. 2.25V. 1.6A Figure 4.10 Experiment measurement waveform of resonant inductor current during the initial operation of the converter. Current scale = 0.5A/div; Time scale = 20µs/div. 66 (Vsc1+Vsc3)/2Figure 4.11 Experiment measurement waveform of resonant capacitor voltage during the initial operation of the converter. Voltage scale = 1.0V/div; Time scale = 20µs/div. Figure 4.12 shows the voltage equalization profile for supercapacitors SC1, SC2 and SC3. The initial largest voltage difference of 527 mV was gradually reduced. The deviation between Vsc1 and Vsc3 was reduced to 10 mV when the voltage equalization process terminated. The total equalization time was less than 15 minutes. 67 Figure 4.12 Experiment measurement waveform of voltage equalization characteristics 4.4 Summary In this chapter, simulation results were presented to demonstrate the validity of the theoretical analysis regarding sinusoidal waveforms of resonant inductor current and resonant capacitor voltage. Experimental results were presented for a prototype of a three supercapacitors system, and the components used for building the prototype were described. The experimental prototype was implemented to verify the theoretical and simulation results in the previous and this chapter, respectively. The expected waveforms were achieved therefore showing the correlation between the simulated waveforms and experimental waveforms. 1.922.12.22.32.42.52.60 100 200 300 400 500 600 700 800 900 1000Voltage (Volts) Time duration (Seconds)Vsc1 Vsc2 68 Chapter 5: Conclusions This chapter summarizes the research presented in this thesis and concludes with suggested improvements for the proposed voltage equalization circuit for future work. 5.1 Research Summary The demands for new energy sources and improved energy efficiency in the application of electric vehicles has resulted in the development of large capacity batteries and capacitors. In comparison to conventional capacitors, supercapacitors have high energy capacity. Because of their high power density, low internal resistance, excellent dynamic response, infinite charge and discharge cycles and long lifetime, supercapacitors have become increasingly popular in the energy industry. The technologies used in supercapacitor production have led to extremely high capacitances for supercapacitor cells. The typical value of a commercial supercapacitor can reach up to 3000 F. With improvements in capacitor manufacturing, large value capacitors are expected to become common and low cost. However, capacitor cell voltages are limited to 2.5 V to 2.7 V. The lower voltage of a single cell means that in order to achieve a much higher voltage for real world applications, including electric vehicle drivetrains, it is necessary to connect cells in series. Usually, for the application of a typical electrical vehicle, the voltage rating is around 400 V. Therefore, the total number of series connected supercapacitor cells is more than 100. However, the capacitance tolerances of each cell affect the uniformity of supercapacitors. Even for capacitors produced at the same time, their capacitance may be different. As a result, the voltage of each supercapacitor varies when charged. Since the cells are usually charged in 69 series by a constant source, the cells connected in the string with low capacitances have higher voltages, which can lead to the failure of a supercapcitor cell, while the cells connected in the string with high capacitances are charged to a lower voltage which means the entire capacity of the supercapacitor string cannot be fully utilized. Therefore, voltage cell balancing is important for series connected supercapacitor applications. Currently, the methods of supercapacitor voltage equalization vary. The published methods include passive voltage equalization and active voltage equalization. The passive voltage balancing methods mainly use a simple connection of resistors and switches to dissipate the extra energy received by individual cells. These topologies are appealing in low voltage applications but generally, they have poor efficiency and they are not desirable in high applications, though they are already used in modern transportation industries. Active voltage equalization methods, including the switched capacitor methods and DC-DC transformer-based power converters can achieve voltage equalization with much higher efficiency. The basic principle of voltage equalization for these topologies is to redistribute the energy from one section of the supercapacitor string to the other sections. This thesis (work) has presented the advantages of some published topologies over others and the corresponding disadvantages. The disadvantages of the mentioned topologies include high relative costs and the relative weight of the components, high voltage and current stress on the switches used, and long voltage equalization time. For most active voltage equalization approaches, the control of the topology is complex. For the single inductor topology, although the cost of the package is lower compared to others, the control of the switches is quite complex. The bi-directional Cûk converter can achieve bidirectional energy flow, but the relative costs of the circuit are high and the control pattern of the switches is also complicated. The single 70 switch voltage multiplier is appealing due to its low relative cost. However, the diodes used in the circuit produce losses and the speed for the voltage balancing process is low. Furthermore, the voltage and current stresses for the switch and diodes are high. For the buck-boost shunting converter, each cell is connected to a buck-boost converter and therefore it can control supercapacitors independently. However, the switch and diode stresses are relatively high with the increasing number of cells connected in the string. The control patterns of the switches are also complex. The selective flyback converter has a relatively fast voltage balancing speed and the equalization process has high efficiency since the energy is transferred back to the supercapacitor string. However, the topology is a transformer-based converter and therefore its costs are relatively higher compared with transformer-less topologies. The half-bridge multi-winding output DC-DC converter has a lower number of switches, but this converter has a multi-winding transformer needs to be customized specifically to satisfy the arbitrary number of cells. In addition, the size of the topology is extremely large with increasing number of cells connected in a string. The major motivation of the proposed topology design is to reduce the voltage equalization time, while minimizing losses and not using complicated multi-winding transformers. The proposed topology uses a series LC resonant tank. By minimizing the circuit impedance near the resonant frequency, the proposed circuit topology can equalize supercapacitor voltages quickly be maximizing charge transfer in each switching cycle. The proposed voltage equalization converter only equalizes those supercapacitors which start with very high voltage differences, e.g. 750 mV. The circuit topology has multiple cells in a single converter unit structure, enabling high extendibility. Therefore, the high extendibility renders more adaptability to voltage level variation in industrial applications. In comparison with multiple 71 voltage equalization units, the single resonant tank also reduces the relative costs and relative size of the circuit package since only two components are required. Table 5.1 provides a comparison of different topologies in terms of voltage equalization time, relative size and relative cost of circuit packages. Table 5.1 Performance comparison among voltage equalization topologies Topology Specification Initial Voltage Deviation (mV) Final Voltage Deviation (mV) Voltage Equalization Time (Minutes) Relative Size Relative Cost Single inductor converter [31] 4.0 AH Batteries 300 50 20 Medium Low Time shared flyback converter [21] 2.65 Ah Batteries 200 50 67 Medium Medium Selective flyback converter [35] 1.3 AH Batteries 200 50 90 Medium Medium Quasi-resonant converter [38] 10.0 AH Batteries 1000 50 42 Medium High Buck- boost shunting converter [34] 4.0 AH Batteries 560 50 45 Medium Medium Cuk converter [32] 10.0 AH Batteries 500 50 25 Medium High Inductor shunting converter [27] 2.2 AH Batteries 250 50 40 Medium Low The proposed converter 300F Capacitors 527 50 7.5 Small Low As can be observed from this table, the proposed voltage equalization converter has short voltage equalization time, small relative size, and low relative cost. 72 PSIM simulation and experimental results were presented in Chapter 4 to verify the validity of the operation of the circuit and the theoretical analysis presented in Chapter 3. A three supercapacitor prototype was built and tested design was presented and the converter successfully balanced two cells starting with an initial voltage difference of 527 mV down to 10 mV in 15 minutes. 5.2 Suggestions for Future Work Although the conclusions drawn from the analysis regarding the proposed voltage equalization scheme are positive, there are still practical design issues regarding the topology. The DC-DC converters used for the isolation between different levels of switches are very expensive, which directly increase the cost of the entire package. For future design considerations, small pulse transformers powered by a single DC-DC power converter could be employed to provide a floating switch reference. 73 References [1] S. Vazquez, S. Lukic, E. Galvan, L. Franquelo and J. Carrasco, "Energy storage systems for transport and grid applications," IEEE Trans. Ind. Electron.,, vol. 57, no. 12, pp. 3881-3895, 2010. [2] R. Lu, L. Tian, C. Zhu and H. Yu, "A new topology of switched capacitor circuit for the balance system of ultra-capacitor stacks," in Proc. IEEE Vehicle Power and Propulsion Conference, 2008. [3] A. Burke, "Batteries and ultracapacitors for electric, hybrid, and fuel cell vehicles," in Proc. IEEE, 2007. [4] Y. Hori, "Future vehicle society based on electric motor, capacitor and wireless power supply," in Proc. IEEE International Power Electronics Conference (IPEC), 2010. [5] J. Han, I. Seo, J. Shon and H. Jeon, "Development of On-line type Dynamic Voltage Compensation System Using Supercapacitor," in Proc. IEEE International Power Electronics Conference (IPEC), 2008. [6] M. Ortúzar, J. Moreno and J. Dixon, "Ultracapacitor-based auxiliary energy system for an electric vehicle: Implementation and evaluation," IEEE Trans. Ind. Electron., vol. 54, no. 4, p. 2147–2156, 2007. [7] O. Onar and A. Khaligh, "A Novel Integrated Magnetic Structure Based DC/DC Converter for Hybrid Battery/Ultracapacitor Energy Storage Systems," IEEE Trans. Smart Grid, vol. 3, no. 1, p. 296–307, Mar. 2012. [8] J. Bauman and M. Kazerani, "A Comparative Study of Fuel-Cell – Battery , Fuel-Cell – Battery – Ultracapacitor Vehicles," IEEE Trans. Veh. Technol., vol. 57, no. 2, pp. 760-769, 2008. [9] O. Laldin and M. Moshirvaziri, "Predictive Algorithm for Optimizing Power Flow in Hybrid Ultracapacitor / Battery Storage Systems for Light Electric Vehicles," IEEE Trans. Power Electron., vol. 28, no. 8, p. 3882–3895, 2013. [10] "PowerStor XL60 Series - Cooper Industries," Max, Oct. 2014. [Online]. Available: www.cooperindustries.com/content/dam/.../bus-elx-ds-10339-xl.pdf. [11] H. Khant, K. Matsui and M. Hasegawa, "Proposal and improvements of voltage equalizers for EDLCs," in Proc. IEEE International Conference on Power Electronics and Drive Systems, 2013. 74 [12] J. Cao, N. Schofield and A. Emadi, "Battery balancing methods: A comprehensive review," in Proc. IEEE Vehicle Power and Propulsion Conference, 2008. [13] R. Nelms and L. Spyker, "Classical Equivalent Circuit Parameters for a Double-Layer Capacitor," IEEE Trans. Aerosp. Electron. Syst., vol. 36, no. 3, p. 829–836, 2000. [14] D. Linzen, S. Buller and E. Karden, "Analysis and evaluation of charge-balancing circuits on performance, reliability, and lifetime of super-capacitor systems," IEEE Trans. Ind. Appl., vol. 41, no. 5, pp. 1135-1141, 2005. [15] M. Uno and K. Tanaka, "Single-switch cell voltage equalizer using multi-stacked buck-boost converters operating in discontinuous conduction mode for series-connected energy storage cells," IEEE Trans. Veh. Technol., vol. 60, no. 8, pp. 3635-3645, 2011. [16] T. Phung, J. Crebier, A. Chureau and A. Collet, "Optimized structure for next-to-next balancing of series-connected Lithium-ion cells," in Proc. IEEE Applied Power Electronics Conference and Exposition (APEC), 2011. [17] N. Tan, S. Inoue, A. Kobayashi and H. Akagi, "Voltage balancing of a 320-V, 12-F Electric Double-Layer Capacitor bank combined with a 10-kW bidirectional isolated DC--DC converter," IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2355-2365, 2008. [18] M. Uno and A. Kukita, "Double-switch equalizer using parallel- or series-parallel-resonant inverter and voltage multiplier for series-connected super-capacitors," IEEE Trans. Power Electron., vol. 29, no. 2, pp. 812-828, 2014. [19] K. Matsui, T. Tsuji and M. Hasegawa, "A novel voltage equalizer for supercapacitors in multiple-connection," in Proc. IEEE International Conference on Power Electronics and Drive Systems (PEDS), 2009. [20] H. Khant, K. Yamakita, K. Matsui and M. Hasegawa, "Various voltage equalizers for EDLCs using CW circuit," in Proc. IEEE International Symposium on Industrial Electronics, 2013. [21] A. M. Imtiaz and F. H. Khan, "Time shared fly-back converter based regenerative cell balancing technique for series connected Li-Ion battery strings," IEEE Trans. Power Electron., vol. 28, no. 12, pp. 5960-5975, 2013. [22] H. Park, C. Kim, K. Park, G. Moon and J. O. Lee, "Design of a Charge Equalizer Based on Battery Modularization," IEEE Trans. Veh. Technol., vol. 58, no. 7, p. 3216–3223, 2009. [23] A. Baughman and M. Ferdowsi, "Double-Tiered Switched-Capacitor Battery Charge Equalization Technique," IEEE Trans. Ind. Electron., vol. 55, no. 6, p. 2277–2285, 2008. 75 [24] R. Lu, C. Zhu, L. Tian and Q. Wang, "Super-capacitor stacks management system with dynamic equalization techniques," IEEE Trans. Magn., vol. 43, no. 1, p. 254–258, 2007. [25] M. Uno and H. Toyota, "Supercapacitor-based energy storage system with voltage equalizers and selective taps," in Proc. IEEE Power Electronics Specialists Conference (PESC), 2008. [26] Y. Lee and M. Cheng, "Intelligent Control Battery Equalization for Series Connected Lithium-Ion Battery Strings," IEEE Trans. Ind. Electron., vol. 52, no. 5, p. 1297–1307, 2005. [27] P. Cassani and S. Williamson, "P. A. Cassani and S. S. Williamson, “Feasibility Analysis of a Novel Cell Equalizer Topology for Plug-In Hybrid Electric Vehicle Energy-Storage Systems," IEEE Trans. Veh. Technol., vol. 58, no. 8, p. 3938–3946, 2009. [28] N. Kutkut, H. Wiegman, D. Divan and D. N. , "Design considerations for charge equalization of an electric vehicle battery system," IEEE Trans. Ind. Appl., vol. 35, no. 1, pp. 28-35, 1999. [29] H. Park, C. Kim, G. Moon and J. Lee, "Two-Stage Cell Balancing Scheme for Hybrid Electric Vehicle Lithium-Ion Battery Strings," in Proc. IEEE Power Electronics Specialists Conference (PESC), 2007. [30] M. Tang and T. Stuart, "Selective buck-boost equalizer for series battery packs," IEEE Trans. Aerosp. Electron. Syst., vol. 36, no. 1, p. 201–211, 2000. [31] S. Park, T. Kim, J. Park, G. Moon and M. Yoon, "A New Battery Equalizer Based on Buck-boost Topology," in Proc. IEEE Internatonal Conference on Power Electronics, 2008. [32] Y. Lee and G. Chen, "Battery Equalization Using Bi-directional Cûk Converters in DCVM Operation," in Proc. IEEE Power Electronics Specialists Conference (PESC), 2005. [33] K. Matsui, T. Suzuki, H. Shimada and M. Hasegawa, "Analysis and Improvements of Novel Voltage Balancer for an Electric Double Layer Capacitor Employing a CW circuit Keyword," in Proc. European Conference on Power Electronics and Applications, 2009. [34] C. Moo, Y. Hsieh and I. Tsai, "Charge Equalization for Series-connected Batteries," IEEE Trans. Aerosp. Electron. Systs., vol. 39, no. 2, pp. 704-710, 2003. 76 [35] J. Shin, G. Seo, C. Chun, B. Cho and A. Struct, "Selective Flyback Balancing Circuit with Improved Balancing Speed for Series Connected," in Proc. IEEE International Power Electronics Conference (IPEC), 2010. [36] A. Xu, S. Xie and X. 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A series resonant converter for voltage equalization of series connected supercapacitor. ultracapacitor… Yanqi, Yu 2015
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Title | A series resonant converter for voltage equalization of series connected supercapacitor. ultracapacitor or lithium battery cells |
Creator |
Yanqi, Yu |
Publisher | University of British Columbia |
Date Issued | 2015 |
Description | Supercapacitors are energy storage devices with great potential in many industrial applications. Although they are not as energy dense as batteries, they have much higher power density. This unique feature enables them to be used to provide bursts of energy in electric vehicle applications. They can be connected in parallel with batteries to source and sink dynamic energy which increases the lifetime of the expensive lithium batteries. Typically, the maximum voltage of a single supercapacitor unit is low, e.g. 2.5 V. In many applications, manufacturers need much higher voltages, e.g. 400 V, so it is necessary to connect supercapacitors in series. A series connection of supercapacitor cells can result in voltage imbalance between cells, since individual supercapacitors have different tolerances. Voltage imbalance can lead to damage of the individual supercapacitors and even the failure of the total energy storage system. Cell voltage equalization is a strategy to maintain the reliability of the supercapacitor pack. A single series inductor-capacitor (LC) resonant tank is proposed in this thesis for the voltage equalization of series connected energy storage elements. The circuit can be used for lithium battery cells, or supercapacitors, but the focus of the work targets supercapacitors. The circuit includes two levels of source connected MOSFET switches for the connection between resonant tank converter and each supercapacitor cell. A controller arranges supercapacitor voltages in descending order and makes a decision based on whether switches associated with the corresponding supercapacitors should be operated. If the voltage difference is higher than the pre-determined allowable value, the microcontroller sends pulse width modulation signals to gate drivers which control the on-off time of the MOSFET switches. Simulation results are presented using PSIM and demonstrate that voltage differences among supercapacitors can be removed fast. Experimental results show that the prototype of the proposed circuit can reduce a voltage deviation of 527 mV down to 10 mV in 15 minutes. The circuit is small in size, achieves a relatively short voltage equalization time and has minimal loss, therefore largely alleviating the problems inherent to existing voltage equalization converters. |
Genre |
Thesis/Dissertation |
Type |
Text |
Language | eng |
Date Available | 2015-07-17 |
Provider | Vancouver : University of British Columbia Library |
Rights | Attribution-NonCommercial-NoDerivs 2.5 Canada |
DOI | 10.14288/1.0166391 |
URI | http://hdl.handle.net/2429/54090 |
Degree |
Master of Applied Science - MASc |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Engineering, School of (Okanagan) |
Degree Grantor | University of British Columbia |
Graduation Date | 2015-09 |
Campus |
UBCO |
Scholarly Level | Graduate |
Rights URI | http://creativecommons.org/licenses/by-nc-nd/2.5/ca/ |
Aggregated Source Repository | DSpace |
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