A PREDICTIVE ANALOG DEAD-TIME CONTROL CIRCUIT FOR A HIGH EFFICIENCY SYNCHRONOUS BUCK CONVERTER by Luyan Mei A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in The College of Graduate Studies (Electrical Engineering) THE UNIVERSITY OF BRITISH COLUMBIA (Okanagan) May 2012 © Luyan Mei, 2012 Abstract The synchronous buck DC-DC power converter is the most common switching converter circuit used to step down a DC input voltage to a low logic level DC output voltage in computer applications. The synchronous buck converter has two power MOSFET switches that turn on in a complementary fashion. However, to avoid high input current spikes, a short duration of deadtime (i.e. a time interval when neither switch is on) is required. During dead-time intervals, the buck converter synchronous MOSFET internal body diode conducts the high inductor current, leading to high losses. To minimize this loss, a dead-time controller circuit is required to minimize the dead-time. The majority of existing predictive dead-time controllers are digital. These dead-time controllers have problems caused by their discrete output including dithering in steady state and reduced accuracy. Furthermore, existing dead-time controllers are limited to buck converter switching frequencies of 300kHz. Therefore, for operation at switching frequencies above 300kHz, dead-time controllers need to be faster and should operate without dithering. A one-step predictive dead-time control circuit for the synchronous buck converter is proposed in this thesis. It consists of a novel dead-time detection circuit and an analog optimization circuit. The detection circuit utilizes an integrated dead-time detection diode, which can be manufactured on the same die as the synchronous MOSFET in the buck converter. This results in an accurate detection signal indicating body diode conduction of the synchronous MOSFET. The dead-time optimization circuit is an analog circuit, which eliminates the shortcomings of digital control. The proposed circuit is verified using PSIM simulation software. In comparison to the adaptive dead-time control using a TPS2832 MOSFET gate driver with minimal of 15ns deadii time, the proposed dead-time control circuit reduces the body diode conduction time of the synchronous MOSFET to 2ns at 10A half load, 12V input, 1.2V output and 500kHz switching frequency. As a result, the efficiency of the buck converter is increased from 89.2% to 90.8%. iii Table of Contents Abstract ................................................................................................................................. ii Table of Contents .................................................................................................................. iv List of Tables ....................................................................................................................... vii List of Figures ..................................................................................................................... viii List of Symbols ..................................................................................................................... xi List of Abbreviations and SI Units ........................................................................................ xvi Acknowledgements ............................................................................................................ xvii Dedication..........................................................................................................................xviii Chapter 1 Introduction ............................................................................................................1 1.1 Introduction of Dead-time in Synchronous Buck Converters ............................................1 1.2 Research Motivation and Objectives ...............................................................................3 1.2.1 Dead-time Detection Circuit ....................................................................................4 1.2.2 Dead-time Optimization Circuit ...............................................................................4 Chapter 2 Literature Review ....................................................................................................5 2.1 Overview ......................................................................................................................5 2.2 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) ....................................5 2.2.1 Structure of MOSFETs ............................................................................................5 2.2.2 MOSFET Mode of Operation...................................................................................7 2.3 Dead-time Control Review.............................................................................................8 2.4 Review of Dead-time Detection.................................................................................... 10 2.4.1 Maximum Efficiency Point Tracking ...................................................................... 10 2.4.2 Sensorless Optimization of Dead-time .................................................................... 11 2.4.3 Logic Gate Used as a Detector ............................................................................... 12 2.4.4 One-step Dead-time Correction .............................................................................. 14 2.4.5 Detecting MOSFET Qdet ........................................................................................ 15 2.4.6 Adaptive Timing Control with Phase Detector ........................................................ 17 2.5 Summary .................................................................................................................... 18 Chapter 3 Proposed Body Diode Detection Circuit.................................................................. 20 3.1 Overview .................................................................................................................... 20 iv 3.2 Dead-time Detection Circuit......................................................................................... 20 3.3 Detection Signal Adjustment Circuit............................................................................. 23 3.4 Implementation of the Detection Diode ......................................................................... 26 3.5 Detection Circuit Design Procedure.............................................................................. 27 3.5.1 Buck Converter Design ......................................................................................... 28 3.5.2 Dead-time Detection Circuit Design ....................................................................... 29 3.6 Design Example and Simulation Results ....................................................................... 32 3.6.1 Design Example .................................................................................................... 32 3.6.2 Simulation Results Using PSIM9 ........................................................................... 34 3.7 Summary .................................................................................................................... 36 Chapter 4 Proposed Dead-time Optimization Circuit ............................................................... 37 4.1 Overview .................................................................................................................... 37 4.2 Dead-time Optimization Circuit.................................................................................... 37 4.2.1 The PWM Signal Processing Circuit....................................................................... 38 4.2.2 The Detection Signal Processing Circuit ................................................................. 41 4.2.3 The Dead-time Optimization Circuit....................................................................... 44 4.3 Dead-time Optimization Circuit Design Procedure ........................................................ 49 4.3.1 The PWM Signal Processing Circuit Design Procedure ........................................... 49 4.3.2 Detection Signal Processing Circuit Design Procedure............................................. 51 4.4 Design Example and Simulation Results ....................................................................... 53 4.4.1 Design Example .................................................................................................... 53 4.4.2 Simulation Results ................................................................................................ 55 4.5 Summary .................................................................................................................... 58 Chapter 5 Simulation Results of the Dead-time Control Circuit................................................ 59 5.1 Overview .................................................................................................................... 59 5.2 Closed-loop Control .................................................................................................... 59 5.3 PWM Rising Edge with Dead-time Control................................................................... 62 5.4 Dual PWM Edge Dead-time Control............................................................................. 65 5.5 Comparison with Adaptive Dead-time Control .............................................................. 70 5.5.1 Body Diode Conduction Time Comparison............................................................. 70 5.5.2 Efficiency and Loss Comparison ............................................................................ 72 5.6 Summary .................................................................................................................... 77 v Chapter 6 Conclusions and Future Work ................................................................................ 78 6.1 Conclusions ................................................................................................................ 78 6.2 Summary of Contributions ........................................................................................... 79 6.3 Future Work................................................................................................................ 80 References ........................................................................................................................... 81 Appendix A.......................................................................................................................... 84 vi List of Tables Table 3.1 Operation condition summary for vx and Ddet state .................................................. 22 Table 3.2 Buck converter design parameters ......................................................................... 32 Table 3.3 Buck converter resultant parameters ...................................................................... 33 Table 3.4 The selected MOSFETs, inductor and capacitor for the objective buck converter ..... 33 Table 3.5 Detection circuit parameters ................................................................................. 34 Table 4.1 The parameters in the design of the PWM signal processing circuit ......................... 54 Table 4.2 The parameters in the design of the detection signal processing circuit .................... 55 Table 4.3 Parameters of the comparator LT1394 ................................................................... 55 Table 5.1 Simulated efficiency measurement data of the buck converter with proposed deadtime control circuit ............................................................................................... 74 Table 5.2 Simulated efficiency measurement data of the benchmark circuit ............................ 74 Table 5.3 Power loss reduction by the proposed circuit.......................................................... 76 Table A.1 Preferred values for passive circuit components ..................................................... 84 vii List of Figures Figure 1.1 The buck converter ...............................................................................................1 Figure 1.2 The synchronous buck converter............................................................................2 Figure 1.3 Ideal Q1 and Q2 gate signal waveforms ...................................................................2 Figure 1.4 Waveforms of Q1 and Q2 gate signals with dead-time ..............................................3 Figure 2.1 n-type MOSFET (a) circuit symbol and (b) device structure ....................................6 Figure 2.2 Circuit symbol of a three-pin n-type MOSFET........................................................6 Figure 2.3 (a) The physical origin of the body diode and, (b) circuit symbol of power MOSFET with body diode ....................................................................................7 Figure 2.4 The conductive channel between drain and source terminals when a positive Vgs is applied between the gate and source terminals ........................................................7 Figure 2.5 An adaptive dead-time control circuit [1]................................................................9 Figure 2.6 A curve of efficiency versus dead-time................................................................. 10 Figure 2.7 Block diagram for sensorless optimization of dead-times....................................... 12 Figure 2.8 A NOR gate is utilized to detect body diode conduction in [1] ............................... 13 Figure 2.9 Voltage waveforms of the switch node voltage, Vx, Q2 gate signal, Vgs2 , and the NOR gate output................................................................................................. 14 Figure 2.10 Block diagram for the digital one-step dead-time correction .................................. 15 Figure 2.11 The detection MOSFET is implemented on the same die as Q2 and the body diodes of the two MOSFETs conduct simultaneously ............................................ 16 Figure 2.12 The detection MOSFET, Qdet , with the dynamic dead-time controller ..................... 16 Figure 2.13 A dead-time control loop which does not require a digital processor....................... 18 Figure 3.1 Proposed dead-time detection circuit for the synchronous buck converter ............... 21 Figure 3.2 The detection signal from the proposed dead-time detection circuit ........................ 23 Figure 3.3 The adjustment circuit used to modify the detection signal .................................... 24 Figure 3.4 Voltage variations at point a, b, and c as well as input and output ports in the detection signal adjustment circuit ....................................................................... 25 Figure 3.5 (a) The detection diode, Ddet , is proposed to be manufactured beside the synchronous MOSFET, Q2 , on the same die and (b) the circuit symbol for this device ................................................................................................................ 27 viii Figure 3.6 Simulation circuit of the buck converter with the proposed dead-time detection circuit ................................................................................................................ 35 Figure 3.7 Simulated of the synchronous MOSFET voltage, vx, detection voltage, vdet , and rising edge detection flag, vdet_r . ........................................................................... 36 Figure 4.1 Block diagram of the proposed dead-time control circuit ....................................... 38 Figure 4.2 The objective output waveform from the PWM signal processing circuit with a PWM input signal............................................................................................... 39 Figure 4.3 The proposed PWM signal processing circuit ....................................................... 40 Figure 4.4 Waveforms for the input signal, Q3 gate signal, and the output signal of the proposed PWM signal processing circuit .............................................................. 40 Figure 4.5 The expected output waveform of the detection signal processing circuit, where the body diode conduction signal is the input. ....................................................... 42 Figure 4.6 The proposed detection signal processing circuit ................................................... 43 Figure 4.7 The input signal, Q4 gate signal, and output signal of the proposed detection signal processing circuit................................................................................................ 44 Figure 4.8 The proposed dead-time optimization circuit ........................................................ 45 Figure 4.9 Signal waveforms of the non-optimized PWM signal, vC2 , vC3 , and the comparator output or the optimized PWM signal in the proposed dead-time optimization circuit when t5 is smaller than DT ........................................................................ 46 Figure 4.10 Signal waveforms of the non-optimized PWM signal, vC2 , vC3 , and the comparator output or the optimized PWM signal in the proposed dead-time optimization circuit when t5 is greater than DT ......................................................................... 48 Figure 4.11 The dead-time optimization simulation circuit ...................................................... 56 Figure 4.12 Simulation results of the dead-time optimization circuit (a) the delayed detection signal for the rising edge, the PWM signal, and the gate signal, (b) the enlarged drawing of the above signals ............................................................................... 57 Figure 5.1 A current mode PWM controller for the buck converter......................................... 60 Figure 5.2 Waveforms from the current mode PWM controller .............................................. 61 Figure 5.3 Four switching cycles of the output voltage of the buck converter .......................... 62 Figure 5.4 The proposed dead-time control circuit for the rising edge combined with the current mode PWM control circuit ....................................................................... 63 ix Figure 5.5 (a) PWM controller output, vpwm , Q1 gate signal, vg1 , and vx over five switching cycles; and (b) vpwm, vg1 , and vx illustrating one pulse width .................................... 65 Figure 5.6 Complete dead-time optimization circuit including dual edge PWM dead-time control and closed-loop output voltage regulation ................................................. 67 Figure 5.7 (a) Waveforms of the Q1 gate signal, PWM signal, Q2 gate signal, inverted PWM signal, and the voltage at the joint point of the two MOSFETs; (b) one PWM pulse; (c) body diode conduction time at the rising edge; (d) body diode conduction time at the falling edge....................................................................... 69 Figure 5.8 The benchmark circuit (fixed dead-time control) ................................................... 70 Figure 5.9 Buck synchronous MOSFET voltage at a load current of 15A (a) benchmark fixed dead-time control (b) proposed dead-time control ................................................. 71 Figure 5.10 Buck synchronous MOSFET voltage at a load current of 20A (a) benchmark fixed dead-time control (b) proposed dead-time control ................................................. 72 Figure 5.11 A comparison of the buck converter efficiency between the proposed circuit and the benchmark circuit at different load currents..................................................... 75 Figure 5.12 Comparison of the conduction loss in the proposed circuit and benchmark ............. 77 x List of Symbols b MOSFET body terminal C Capacitor of the power stage filter C1 Capacitor in the detection circuit C2 Capacitor in the PWM signal processing circuit C3 Capacitor in the detection signal processing circuit Cctr Control capacitor Cmin Minimal capacitance to limit the output voltage ripple D Duty cycle d MOSFET drain terminal D(n) Moving average duty cycle d(n) Current duty cycle D[5:1] 5-digits output of the finite state machine Dbody Body diode of the synchronous MOSFET Ddet Dead-time detection diode Dsyn Synchronous diode DT Dead-time DT0 Initial dead-time value DW Dead-time width e the base of natural logarithm Eff (n) Buck converter efficiency at current switching cycle Eff (n-1) Buck converter efficiency at previous switching cycle fs Switching frequency g MOSFET gate terminal g1 Gate signal for the power MOSFET g2 Gate signal for the synchronous MOSFET IB Input bias current of a comparator iC1 Capacitor C1 current iC2 Capacitor C2 current iC3 Capacitor C3 current xi Id Drain current of MOSFETs iDbody Body diode current of the synchronous MOSFET iDdet Detection diode current Idet Drain-source current of the detection MOSFET Ids Drain-source current of MOSFETs iin Input current of the buck converter Iin_avr Average input current of the buck converter Iin_c Input current of a comparator IL Inductor current Iload Load current of the buck converter ILoad Average load current IQ2 Drain-source current of the synchronous MOSFET iR2 Resistor R2 current iR3 Resistor R3 current iR4 Resistor R4 current iR5 Resistor R5 current K Magnification parameter of the voltage amplifier Krip % Output voltage peak-to-peak ripple L Inductor of the power stage filter Lcri The critical inductance that ensures continuous current mode Oreg Flip-flop output Pin Average input power of the buck converter p in Input power of the buck converter Pls Power loss at the buck converter Pls1 Power loss of the buck converter with the proposed dead-time controller Pls2 Power loss of the buck converter with the benchmark circuit Pout Average output power of the buck converter p out Output power of the buck converter Q1 Power MOSFET of the buck converter Q2 Synchronous MOSFET of the buck converter Q3 MOSFET in the PWM signal processing circuit Q4 Charging up MOSFET in the detection signal processing circuit xii Q5 Discharging MOSFET in the detection signal processing circuit Qdet Dead-time detection MOSFET Qg Gate charge of a MOSFET R1 Resistor in the detection circuit R2 Charging up resistor in the PWM signal processing circuit R3 Discharging resistor in the PWM signal processing circuit R4 Charging up resistor in the detection signal processing circuit R5 Discharging resistor in the detection signal processing circuit RL Equivalent load resistance Ron On resistance of MOSFETs s MOSFET source terminal SiO2 Silicon dioxide t Time variable T Switching period t1 Objective rising time of vC2 t2 Experimental rising time of vC2 at the proposed circuit t3 Experimental falling time of vC2 at the proposed circuit t4 Objective time to charge up C3 in each switching cycle t5 Experimental time starting to charge up C3 at proposed circuit t6 Delay generated by the optimization circuit for the rising edge of the PWM pulse t7 Delay caused by the optimization circuit at the trailing edge of the PWM pulse tbc_r Body diode conduction time at the rising edge tbc_t Body diode conduction time at the trailing edge tcon Detected body diode conduction time, output of the detection circuit tcon_org Original body diode conduction time td Time delay generated by dead-time controllers td (n) Dead-time for the current switching cycle td (n-1) Dead-time of the previous switching cycle td1 Time delay at the rising edge of the PWM pulse td2 Time delay at the trailing edge of the PWM pulse tdo Optimal dead-time toff Switch off time of a MOSFET xiii ton Switch on time of a MOSFET tpd Propagation delay of logic gates tQ4_on Duration of the MOSFET Q4 being turned on trr Reverse recovery time of a diode V1 Voltage source for the detection circuit V2 Voltage source for signal shifting va Voltage signal at point a in the adjustment circuit vb Voltage signal at point b in the adjustment circuit vc Voltage signal at point c in the adjustment circuit vC1 Voltage across the capacitor C1 in the detection circuit vC2 Voltage across the capacitor C2 in the PWM signal processing circuit VC2_h High voltage value of vC2 VC2_l Low voltage value of vC2 vC3 Voltage across the capacitor C3 in the detection signal processing circuit VC3_h High voltage value of vC3 VC3_l Low voltage value of vC3 vDdet Anode voltage of the detection diode vdet Dead-time detection signal voltage vdet_r Detection signal voltage for the rising edge of the PWM pulse vdet_t Detection signal voltage for the trailing edge of the PWM pulse Vdmax Maximal value of the dead-time detection voltage Vdmin Minimal value of the dead-time detection voltage Vds Drain-source voltage of MOSFETs VF-body Forward voltage of the synchronous MOSFET body diode VF-det Forward voltage of the detection diode vg1 MOSFET Q1 gate signal vg2 MOSFET Q2 gate signal Vgs Gate-source voltage of MOSFETs Vgs2 Gate-source voltage of the synchronous MOSFET Vhigh Voltage value of logic high vin Input voltage of the buck converter Vin Average input voltage of the buck converter xiv Vlogic Analog voltage level of a logic gate Vout Average output voltage of the buck converter vout Output voltage of the buck converter Vout_rms Root-mean-square of the buck converter output voltage vpwm Output of a PWM controller vpwm_i Inverted output of a PWM controller vR2 Voltage across the resistor R2 vR3 Voltage across the resistor R3 vR4 Voltage across the resistor R4 vR5 Voltage across the resistor R5 VS1 Voltage source for the control circuit Vth Threshold voltage of MOSFETs vx Voltage at the junction point of the power MOSFET and the synchronous device α Low pass filter factor; between 0 and 1 ΔEff Efficiency improvement ΔP% Power loss reduction percentage ΔPls Power loss reduction by the proposed circuit Δtd Dead-time step ΔVout-pp Vout Peak-to-peak output voltage ripple η Power efficiency of buck converters τ1 Time constant of the detection circuit τ2 Time constant of the rising transient at the PWM signal processing circuit τ3 Time constant of the falling transient at the PWM signal processing circuit τ4 Time constant of the rising transient at the detection signal processing circuit τ5 Time constant of the falling transient at the detection signal processing circuit xv List of Abbreviations and SI Units A Amperes C Coulombs DC Direct Current DPWM Digital Pulse Width Modulation F Farads FSM Finite State Machine H Henries Hz Hertz IC Integrated Chips k Kilo (103 ) M Mega (106 ) m Milli (10-3 ) MEPT Maximum Efficiency Point Tracking MOSFET Metal Oxide Silicon Field Effect Transistor n Nano (10-9 ) n-type Negative-type PID Proportion-integral-derivative p-type Positive-type s Seconds V Volts W Watts μ Micro (10-6 ) Ω Ohms xvi Acknowledgements First, I want to thank my supervisor, Dr. Wilson Eberle, for his patience, support, and help throughout my master‟s study in the School of Engineering at UBC, and especially his guidance for my thesis project. Moreover, I want to thank my colleagues in the Power Electronics Group in for their helpful advice. I would also like to thank my family for their unconditional support during my work on the thesis. My father, Renxiang Mei, my mother, Huamei Xu, my sister Zhihong Mei and my 2-year old niece, Yi Chen have greatly encouraged me through the challenge during my study. At last, I want to thank my dear friends in Kelowna, Man (Sapphire) Ding, Xian (Peter) Jin, Feng (Vicki) Wei, Xuegui Song, Xianchang Li, Faria and Hannah. They have helped me tremendously during my stay in Kelowna. xvii Dedication To my parents xviii Chapter 1 Introduction 1.1 Introduction of Dead-time in Synchronous Buck Converters A buck converter is a step down DC to DC conversion circuit. Figure 1.1 is the simplest and most widely used DC-DC converter topology. It is a switching mode power supply, with a frequency generally ranging from 50kHz to 1MHz. It is often used in modern low voltage DC power supplies, such as battery-supplied electronics, point of load converters and microprocessor power supplies. Q1 + Dsyn Vin - + Controller Vx - + L C Vout - Figure 1.1 The buck converter A synchronous buck converter uses a power MOSFET to replace the rectifier diode in order to achieve higher efficiency, because for low output voltage applications, a MOSFET exhibits lower conduction loss than a diode. Figure 1.2 illustrates the circuit of a synchronous buck converter, and Figure 1.3 shows its ideal gate-to-source driving waveforms. Q1 is called the control switch while Q2 is called the rectifier switch or synchronous rectifier. Ideally, Q1 and Q2 are turned on in a complementary fashion such that at t=DT, Q2 is turned on while Q1 is turned off simultaneously, and vice versa at t=0 or T. 1 + + Q1 + L Q2 Vin - Vx Controller C - Vout - Figure 1.2 The synchronous buck converter Q1 gating voltage Q1 on Q1 off t Q2 on Q2 gating voltage Q2 off DT T t Figure 1.3 Ideal Q1 and Q2 gate signal waveforms Due to the non-zero turn-on and turn-off time of power MOSFETs, a dead-time needs to be inserted into the transition intervals, as shown in Figure 1.4. Without dead-time, it is possible that Q2 will turn-on when Q1 is not totally off, resulting in a shoot through current from the source through Q1 and Q2 to ground, leading to reliability problems and excessive power loss. Alternately, if the dead-time is longer than required such that Q2 is not turned-on when Q1 has been off, the body diode of Q2 is forced on, providing a continuous path for the inductor current. Generally, a body diode has greater conduction loss than a MOSFET channel. As a result, excessive dead-time results in a lower efficiency for the converter. 2 Q1 on Q1 gating voltage Q1 off t Q2 on Q2 gating voltage Q2 off Dead-time DT Dead-time T t Figure 1.4 Waveforms of Q1 and Q2 gate signals with dead-time 1.2 Research Motivation and Objectives High efficiency is a requirement for the buck converter and all power converters. Their ability to achieve high efficiency (e.g. typically > 85%) is one of the reasons that buck converters are so widely used in power conversion. Therefore, much research has been done to increase efficiency. One method is to reduce the body diode conduction of the synchronous MOSFET in the buck converter. Buck converters typically switch at frequencies between 200kHz and 500kHz. High switching frequencies result in better performance and design characteristics in many aspects, including a fast transient response, a smaller inductor, and a smaller capacitor. However, frequency dependent losses including switching loss, gate loss and body diode conduction loss increases with frequency. High switching loss and gate loss are not easily addressed; however, fast dead-time control circuits can minimize dead-time related conduction loss in order to achieve high efficiency. The objective of this thesis is to propose a dead-time control circuit that reduces dead-time to a minimum value in comparison to benchmark circuits used presently in industry. A dead-time control circuit requires dead-time detection and dead-time optimization circuits, which are 3 discussed in the following subsections. 1.2.1 Dead-time Detection Circuit The dead-time detection circuit needs to be sensitive. Otherwise it is impossible for the control circuit to achieve a small dead-time if the detector cannot even sense body diode conduction. Moreover, the detection circuit should be able to generate an output signal that precisely tells the body diode conduction time. Without doubt, it is beneficial if the circuit can be made denser. 1.2.2 Dead-time Optimization Circuit Dead-time optimization circuits can be either analog or digital. However, most dead-time controllers are digital since it is relatively simple to insert dead-time to the PWM pulses. An important objective for the circuit is high speed so that the processing time is much less than the switching period which can be very small for high frequencies. Finally, since the timing of the pulses is critical for proper efficient converter operation, the optimization circuit should synchronize the gate signals for the two MOSFETs. 4 Chapter 2 Literature Review 2.1 Overview In this chapter, the MOSFET semiconductor device is briefly introduced, and then a review of dead-time control circuits is presented. The advantages and shortcomings of the existing circuits are compared and summarized, thereby establishing the technical modification for the work presented in the remainder of the thesis. 2.2 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) Among semiconductor devices, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are the most widely used switching devices in low power and high frequency power conversion applications, due to desirable characteristics including, low on-state voltage drop, low gate drive currents, high current handling capability, and low cost. In this section, the basic structure and models of operation of power MOSFETs is introduced. 2.2.1 Structure of MOSFETs MOSFETs are semiconductor devices with four terminals including the drain, source, gate, and body. The semiconductor material used for the source and drain terminals in MOSFETs are categorized as n-type or p-type. For n-type MOSFETs, n-type source and drain are added to the body of p-type silicon substrates. A layer of insulative material, silicon dioxide (SiO2 ), is then manufactured on top of the substrates. Figure 2.1 illustrates the circuit symbol and device structure of an n-type MOSFET. 5 Source (s) d g Gate (g) n+ b Drain (d) n+ p-substrate s Body (b) (a) (b) Figure 2.1 n-type MOSFET (a) circuit symbol and (b) device structure For power MOSFETs, the body terminal is connected to the source, so the device effectively becomes a three-terminal device. Figure 2.2 illustrates the three-pin symbol of an n-type MOSFET. d g b s Figure 2.2 Circuit symbol of a three-pin n-type MOSFET An intrinsic p-n junction exists between the p + body region and the implanted n + region, as shown in Figure 2.3 (a). This p-n junction is called the body diode in power MOSFETs. Figure 2.3 (b) illustrates the circuit symbol of a power MOSFET with a body diode. 6 Gate (g) Source (s) n+ Drain (d) n+ p+ d PN junction Body diode g s Body (b) (a) (b) Figure 2.3 (a) The physical origin of the body diode and, (b) circuit symbol of power MOSFET with body diode 2.2.2 MOSFET Mode of Operation This subsection presents the modes of operation for a MOSFET. When a positive voltage source, Vgs , is applied between the gate and source terminals, as shown in Figure 2.4, the gate, the insulative silicon oxide and the base create a capacitive region. The positive voltage draws negative particles to the top of the p-substrate, thus forming a conductive electric channel. Current flows in this channel if another voltage source is present across the drain and source terminals. Source (s) Vgs - + Gate (g) n+ e- -e- -ee e +++++ Drain (d) n+ p-substrate Body (b) Figure 2.4 The conductive channel between drain and source terminals when a positive Vgs is applied between the gate and source terminals As a first order approximation, MOSFETs have three operation modes depending on the 7 magnitude of the applied voltages. 1) Cutoff mode This mode occurs when Vgs < Vth , where Vth is the threshold of the device. That is, the gate- source voltage is too small to enable the formation of the conductive channel. This mode is the “off” mode, since the device cannot conduct current. 2) Triode mode When Vgs > Vth , but Vds < Vgs - Vth , the MOSFET device works like a resistor. The magnitude of the current, Ids is linearly related to Vds for a given value of Vgs . 3) Saturation mode The device is called saturated when Vgs > Vth , and Vds > Vgs - Vth . The value of Ids is controlled by Vgs and is independent of Vds . The resistance between the drain and source terminals in the triode mode is called the on resistance, which is an important parameter in every MOSFET datasheet. The on resistance of a power MOSFET usually lies in the milliohm range, so it is typically ignored, except for use in loss calculations. Due to high drain current and low drain voltage, power MOSFETs are intended to operate in the triode mode (low resistance) in the on state, and in the cutoff mode (very high resistance) in the off state. 2.3 Dead-time Control Review Dead-time control techniques can be divided into three types - fixed dead-time control, adaptive dead-time control, and predictive dead-time control [1]. With fixed dead-time, a constant uncontrolled dead-time is added to the gate signal for the 8 synchronous MOSFET. The fixed dead-time must be long enough to avoid over shoot in any conditions, regardless of changes in temperature, load, and the type of MOSFET device. Therefore, to avoid any chance of shoot through, the dead-time is usually much longer than that needed in most situations, resulting in excessive body diode conduction. Adaptive dead-time control, however, is able to adjust the dead-time according to the current conditions in the circuit. An example of an adaptive dead-time control circuit is shown in Figure 2.5 [1]. With this technique, there is a feedback loop, which acts to detect body diode conduction. As a result, this method can only decrease body diode conduction rather than eliminate it. + Q1 + + L Q2 Vin Vx - - C Vout - PWM signal Figure 2.5 An adaptive dead-time control circuit [1] The third type of dead-time control is predictive dead-time control, which uses information of the previous switching cycle to determine the dead-time needed in the current cycle. Depending on the numbers of cycles needed for the buck converter to reach steady state, predictive dead-time control can be further categorized into unit bit delay adjustment and one step adjustment. 9 2.4 Review of Dead-time Detection 2.4.1 Maximum Efficiency Point Tracking A method named “Maximum Efficiency Point Tracking” (MEPT) was proposed in [2]. This method was originally used in solar arrays, and later extended to the field of dead-time control. Figure 2.6 shows the efficiency curve of a buck converter in a certain dead-time range. td (n) represents dead-time values at current switching cycle, and Eff (n) is the corresponding efficiency. Similarly, the previous step dead-time is td (n-1) and the efficiency Eff(n-1). ΔEff and Δtd are given by (2.1) and (2.2). ( ) ( ) ( ) ( (2.1) ) (2.2) Efficiency (Eff) Maximum Efficiency Body-diode conduction range Shoot through range ∆td td0 Optimum dead-time Dead-time (td) Figure 2.6 A curve of efficiency versus dead-time If ΔEff and Δtd have the same sign, that is both being positive or negative, dead-time for the 10 coming switching cycle is that of last switching cycle plus one step dead-time value, Δtd ; otherwise, the dead-time is decreased by one step. The dead-time controller starts with a fixed worse-case dead-time, which ensures safety operating at all conditions. The dead-time is then modified step by step until the maximum efficiency is found. One advantage of this method is that the algorithm is simple. The input current is sensed and used instead of maximum efficiency, since the lowest input current corresponds to the highest efficiency, if the output voltage is regulated. Therefore, an extra sensor is not needed because the input current is usually monitored for safety reasons. Another advantage is that the controller will adapt to the optimum dead-time if the load or input voltage changes. Disadvantages include long transient times and limited accuracy, depending on the step size of the dead-time. Since dead-time is changed step by step rather than continuously, there is a high chance that the actual optimum dead-time exists between two stepped dead-time values. 2.4.2 Sensorless Optimization of Dead-time Another digital algorithm of dead-time control named sensorless optimization is proposed in [3]. The block diagram of this dead-time controller is provided in Figure 2.7. The PID controller adjusts the duty cycle to regulate the output voltage of the buck converter. In steady state, the optimum dead-time value produces the lowest duty cycle value. The output of the PID compensator is utilized to find the optimum dead-time. The dead-time optimizer starts with a fixed maximum dead-time value, which ensures safe operation of the buck converter under all conditions. Next, the dead-time is decreased step by step until it reaches the dead-time value which yields the lowest duty cycle. To avoid sudden changes, a moving average duty cycle, D(n), is used in the algorithm rather than the current duty cycle, d(n). The moving average duty cycle, given by (2.3), functions as a low pass filter. 11 ( ) ( ) ( ) ( ) (2.3) where α is a factor between 0 and 1and D(n) is equal to d(n) in steady state. g1 g2 Duty cycle d(n) DPWM td2 PID Controller td1 Low pass filter Dead-time Optimizer D(n) LP(z) d(n) Figure 2.7 Block diagram for sensorless optimization of dead-times There are several similarities between this sensorless dead-time optimizer and the previous MEPT algorithm. First, no extra sensor is needed to detect dead-time. In both algorithms, detection signals are generated from parameters which already exist in the voltage regulation loop. Second, both dead-time controllers start from a preset maximum value and are decreased step by step until the optimum value is found. For these reasons, the two algorithms are similar such that they share the same advantages and disadvantages. 2.4.3 Logic Gate Used as a Detector A NOR gate and a comparator are used to detect the body diode conduction of MOSFET Q2 in [1]. The circuit is provided in Figure 2.8. Waveforms of the NOR gate output, comparator output, Q2 drain-to-source voltage, Vx , and gate-to-source voltage, Vgs2 , are provided in Figure 2.9. Only when both Vgs2 and Vx are low will the NOR gate output be high. Therefore, the presence of a high NOR gate output illustrates body diode conduction and therefore excess dead12 time. The dead-time in the controller is decreased by one step size for the next switching cycle until the high pulse of the NOR gate output is eliminated. When the NOR gate output remains low, a one-step size delay is added to the dead-time for the next switching cycle. As a result, a two-step dead-time size dithering occurs in steady state. The NOR gate is used to detect the body diode conduction before Q2 turns on; while the comparator is used to detect body diode conduction after Q2 turns off. This leads to complications in the control circuit and in addition, it takes several switching cycles to eliminate body diode conduction. + Q1 + + L Q2 Vin - Vgs2 Vx Vout C - NOR gate output comparator output Figure 2.8 A NOR gate is utilized to detect body diode conduction in [1] 13 Vx NOR gate output Vgs2 comparator output 0 t Figure 2.9 Voltage waveforms of the switch node voltage, Vx , Q2 gate signal, Vgs2, and the NOR gate output 2.4.4 One-step Dead-time Correction To avoid these shortcomings, an improved method, called “one-step digital dead-time correction” was proposed in [4]. A block diagram of this method is provided in Figure 2.10. The comparator in [1] is eliminated and the NOR gate is used to detect body diode conduction during the turn on and turn off transition intervals. This simplifies the circuit and improves its performance, since the NOR gate is faster than the comparator. After dead-time detection is achieved with the NOR gate, a pulse width measurement is implemented to measure the width of the NOR gate output pulse, DW. In the next switching cycle, DW is subtracted from the dead-time, DT. Theoretically, the body diode conduction can be eliminated in the next switching cycle rather than in several switching cycles, so “one-step correction” can be achieved. However, as in [1], a step-size dead-time value, DT0, is added when the output of the NOR gate remains low. Therefore, the dithering at the two-step size window remains as in [1]. 14 DT=DT_ini DPWM programmable dead-time DT=DT-DW Pulse width measurement Dead-time correction DT=DT+DT0 DW yes DW=0? no Figure 2.10 Block diagram for the digital one-step dead-time correction 2.4.5 Detecting MOSFET Qdet Dynamic dead-time control is introduced in [5]. Instead of a NOR gate, or a comparator, a detecting MOSFET, Qdet , is used. This MOSFET can be fabricated on the same die as the synchronous rectifier MOSFET Q2 , as illustrated in Figure 2.11. The dynamic dead-time control circuit with the buck converter is illustrated in Figure 2.12. When the body diode of Q2 is on, Vx is slightly negative (e.g. -0.7V). In addition, since Qdet is in parallel with Q2 , its body diode is also forced on. Therefore, when the body diode of Q2 is on, the voltage across C1 decreases. The time 15 that C1 voltage stays low reflects the body diode conduction time of Q2 . The finite state machine (FSM) controls a binary-weighted capacitor, which in turn adjusts the dead-time in the dead-time adjustor (DTA). If the output of the RS flip-flop, Oreg , is „1‟, the dead-time will be reduced in the next switching cycle; while if Oreg is „0‟, the FSM output, D[5:1], is increased, and therefore the next switching cycle dead-time is increased. V1 Q2 gate n+ Q2 IL n+ n+ Qdet n+ IQ2 Idet p-substrate Figure 2.11 The detection MOSFET is implemented on the same die as Q2 and the body diodes of the two MOSFETs conduct simultaneously R1 0.2V The detection MOSFET Qdet S C1 R SET CLR Q Q Finite State Machine (FSM) D[5] D[4] D[3] D[2] D[1] + Q1 + L Q2 Vin - + Vx Controller - C Vout - Figure 2.12 The detection MOSFET, Qdet , with the dynamic dead-time controller 16 This dynamic dead-time control is similar to other digital controllers in many aspects except for the body diode conduction detection circuit, which has the built-in detecting MOSFET, unique from other detecting methods. This built-in detector is able to make the integrated control circuit denser than a separate discrete circuit. In addition, it reduces the influence of parasitic electric parameters between the sensor and the Q2 body diode, eliminating the wire between them. As a result, this sensor can be more accurate than the methods in [1]-[4]. Furthermore, this analog detecting technique is also suitable for an analog controller and thus the disadvantages of digital controllers can be eliminated. 2.4.6 Adaptive Timing Control with Phase Detector In [9], dead-time control is achieved without the need for a sophisticated digital signal processor. The control circuit presented in [9] is provided in Figure 2.13. The two comparators and the phase detector generate pulses at the “UP” output to increase the next switching cycle dead-time, or pulses at the “DN” output to reduce the dead-time. This control loop only optimizes the dead-time when the synchronous MOSFET Q2 is turned on. A symmetric dead-time control loop is required for the buck converter when Q1 is turned on and Q2 is turned off, because the control loop in Figure 2.13 only optimizes the dead-time interval before Q2 turns on. 17 Vth Phase detector φB TIMER UP VC φA OUT RS latch S SET Q2 Q DN Cctr R CLR Q Q2 turn on signal Figure 2.13 A dead-time control loop which does not require a digital processor This dead-time control circuit overcomes those shortcomings brought in by digital processors, since the dead-time is adjusted continuously rather than step by step. Moreover, the two-step size window dithering in steady state in digital controllers is also eliminated. 2.5 Summary Body diode conduction detection and dead-time optimization circuits have been reviewed. The work is summarized as follows. Body diode detection methods differ in three ways. Some algorithms use parameters already monitored by the buck converter output voltage controller, such as input current or output voltage [2], [3]. Others use discrete components, like a NOR gate or a comparator, to detect body diode conduction directly [1], [4]. Finally a built-in detecting MOSFET, which is implemented on the same die of the synchronous MOSFET Q2 , is recently proposed to detect dead-time [5]. Unit bit dead-time optimization algorithms have been presented in [1]-[3], and [5]. These 18 methods work quite similarly despite the different dead-time detection algorithms used. However, if the dead-time for the last switching cycle is too long, it is reduced by one unit bit for the following cycle. A preset maximum dead-time value is stored in the controller and the iterative process stops when the optimum value is found. The number of switching cycles needed to reach steady state, and the accuracy of the optimum dead-time, depend on the size of the unit bit. In contrast with unit bit dead-time adjustment, the one step adjustment algorithm attempts to reach steady state in one switching cycle [4]. The duration of body diode conduction of the last switching cycle is measured first and then the dead-time for the next switching cycle is set as that of last switching cycle minus body diode conduction time. This algorithm results in a short transient time. In the chapters that follow, a novel analog body diode detection circuit is proposed in Chapter 3, followed by a novel analog dead-time optimization circuit in Chapter 4. The proposed circuits are combined and PSIM simulation results are used to verify and benchmark the contributions in Chapter 5. The conclusions are presented in Chapter 6. 19 Chapter 3 Proposed Body Diode Detection Circuit 3.1 Overview A sensitive detection circuit is critical for dead-time control circuits. In Chapter 2, it was noted that a comparator, or a NOR gate, is a relatively simple way to detect body diode conduction among all the other discussed methods. However, a built-in detector can achieve better performance than discrete devices, because for today‟s devices that operate at high frequencies, a properly integrated detector can minimize parasitic elements. Therefore, in this chapter, an integrated dead-time detection diode is proposed and the detection circuit operation discussed. This chapter is organized in the following manner. The dead-time detection circuit is introduced in Section 3.2, followed by a description of an adjustment circuit. The adjustment circuit used to convert the detected non-regular waveform to a pulse waveform is introduced in Section 3.3. In Section 3.4, the detection diode implementation is explained. A design procedure with circuit parameters used is then presented in Section 3.5. Finally, a design example and simulation results are presented in Section 3.6. 3.2 Dead-time Detection Circuit The proposed dead-time detection circuit for the synchronous buck converter is provided in Figure 3.1. A detection diode, Ddet , and an auxiliary circuit, consisting of a resistor, R1 , comparator, C1 , and a low DC voltage source, V1 (e.g. 0.1V), are used to detect the conduction of the Q2 body diode. 20 R1 Proposed dead-time detection circuit + Ddet Q2 - Controller + vdet - C1 + Q1 Vin V1 L vx - iL C + Vout - Figure 3.1 Proposed dead-time detection circuit for the synchronous buck converter In order to illustrate the circuit operation, the output voltage of the capacitor C1 is analyzed under three different operating conditions of the buck converter: 1) The power MOSFET Q1 is on while the synchronous MOSFET Q2 is off. Switch node voltage vx in Figure 3.1 is equal to the input voltage Vin , which is 12V in the design example of this thesis. V1 is a small value voltage source, having a value under 0.2V. As a result, a reverse voltage is formed over the diode Ddet and Ddet is therefore biased off. The output voltage signal vdet is the voltage across capacitor C1 and is equal to V1 during this time. 2) The power MOSFET Q1 is off while the synchronous MOSFET Q2 is on. The inductor current flows through MOSFET Q2 during this time, so voltage vx is negative and the absolute value of vx is the product of the current through Q2 and the on-state resistance of Q2 . Usually, the on-state resistance of a power MOSFET is quite small, ranging from several milliohms to several hundred milliohms depending on the type of the MOSFET. As a result, vx is usually greater than -0.5V during this time. For the components and circuit operating conditions in this thesis, vx is approximately -0.1V when Q2 is on. Thus, diode Ddet is biased off and the vdet is 21 equal to V1 . 3) The power MOSFET Q1 is off and the synchronous MOSFET Q2 is also off. A prerequisite to use this dead-time detector is that the buck converter is operating in continuous mode (i.e. iL > 0). Since neither switch is on, the body diode of MOSFET Q2 is forced on to provide a path for the inductor current. As a result vx drops to a negative value, which is the voltage drop over the p-n junction of Q2 , and is approximately equal to -0.7V for silicon MOSFETs. Since the voltage source, V1 , is positive, a voltage drop, which exceeds 0.7V, is applied to Ddet , and thus, it is biased on. Therefore, capacitor C1 is discharged and the output voltage, vdet , drops. A summary of the states of Ddet during the three operation states of the buck converter is provided in Table 3.1. Figure 3.2 provides the waveforms of the voltage signal vdet , along with the gate signals for MOSFETs Q1 and Q2 . The time interval of signal vdet being low represents the period when the body diode of the synchronous MOSFET Q2 is conducting. In other words, it is this period of time that is desired to be eliminated in order to increase the efficiency. Although vdet contains the information of the unwanted dead-time, its waveform is not ideal as a detection signal for the controller. A pulse signal would be preferred, and for this reason, a second circuit is added to adjust the direct detection signal. This adjustment circuit is described in the following subsection. Table 3.1 Operation condition summary for vx and Ddet state vx Detection diode, Ddet Q1 on, Q2 off Vin (12V) Off Q1 off, Q2 on -iLRon (≥ -0.1V) Off Q1 off, Q2 off -0.7V On 22 Q1 gate signal Q2 gate signal t vdet V1 t DT T t Figure 3.2 The detection signal from the proposed dead-time detection circuit 3.3 Detection Signal Adjustment Circuit The proposed signal adjustment circuit is provided in Figure 3.3. The purpose of this adjustment circuit is to convert the dead-time detection signal, vdet , into a pulse waveform so that it will be easier for the controller input. Figure 3.4 shows voltage variation at several points of the circuit, including those at points a, b, and c as well as the input and output ports. 23 Point b AND gate Output Signal Point a Input Signal Voltage Amplifier Pulse Signal Figure 3.3 The adjustment circuit used to modify the detection signal 24 vdet V1 0 t va KV1 0 t vb 1 0 t Output 1 0 DT T t Figure 3.4 Voltage variations at point a, b, and c as well as input and output ports in the detection signal adjustment circuit The adjustment circuit first magnifies the input signal vdet by K times through a voltage amplifier, generating signal va . K is an adjustable parameter of the voltage amplifier and is chosen to be a positive integer for this design. Then a logic inverter changes va to be pulse signal vb . Both the power MOSFET Q1 and the synchronous MOSFET Q2 are switched on and off once in every switching cycle. Therefore, each has two on-off transitions during one switching cycle, one while switching on and the other while switching off. Thus, there are two dead-time pulses in a switching cycle, as given by vb in Figure 3.4. However, these two pulses are usually not of the same width because Q1 and Q2 typically have different characteristics and therefore 25 have different switching characteristics. Moreover, the inductor current also varies at the two switching edges. In steady state the inductor current reaches its maximum value when the MOSFET Q1 turns off and minimum value when Q1 turns on. Therefore, the two dead-time intervals should be optimized independently. Accordingly, a 50%-duty-cycle selecting pulse at the switching frequency is applied to one input of the AND gate in Figure 3.3, while vb is applied to the other. Thus, if the selecting pulse does not have any phase delay, the dead-time signal at the switching on edge is output to the optimization circuit; otherwise, if the selecting pulse has a phase delay of 180 degrees, the dead-time signal at the switching off edge is output. For the design example in this chapter, the latter signal is chosen, as shown in Figure 3.4. 3.4 Implementation of the Detection Diode The trend in modern power integrated circuit manufacturing is to build two, or more devices on the same die in order to reduce parasitic elements. In this section, the detection diode is proposed to be manufactured on the same die as the synchronous MOSFET Q2 . The structure of the MOSFET has been reviewed in Chapter 2. The proposed implementation for the detection diode Ddet is illustrated in Figure 3.5(a). The detection diode can be located immediately to the right of the MOSFET Q2 with an isolation barrier in the p-substrate. The cathode of Ddet is connected to the drain of Q2 , which is consistent with the circuit arrangement shown in Figure 3.5(b). 26 Q2 gate Q2 source Q2 drain n+ n+ n+ p-substrate Q2 (a) psubstrate Isolation D det barrier Ddet Q2 drain Q2 (b) Figure 3.5 (a) The detection diode, Ddet , is proposed to be manufactured beside the synchronous MOSFET, Q2 , on the same die and (b) the circuit symbol for this device There are three advantages of the proposed implementation. First, it is denser than two discrete semiconductors, Ddet and Q2 , so, the dead-time controller can be made smaller. Second, this implementation gives a shorter connection between the Q2 drain and the Ddet cathode than that of two discrete devices. This results in less parasitic inductance and capacitance, which enables the controller to be utilized in higher frequency applications. Third, since Ddet and Q2 are using the same semiconductor material, the body diode of Q2 and the detection diode Ddet have the same forward voltage drop, enabling the detection circuit to be more sensitive and accurate. 3.5 Detection Circuit Design Procedure Relationships between the circuit parameters of the buck converter are discussed in this section and equations are given in order to illustrate how one parameter influences another. Understanding these relationships enables a designer to choose the right devices for the circuit design and to optimize the expected results. Usually, parameters are chosen sequentially, starting from the initial given ones. Here, the application of the buck converter and design objectives are given. The design procedure for a buck converter is first introduced, followed by the design of the 27 proposed dead-time detection circuit. 3.5.1 Buck Converter Design Given the input voltage, Vin , output voltage, Vout , switching frequency, f s , load current, Iload , and peak-to-peak output voltage ripple assuming 100% efficiency, the duty cycle, D, of the power MOSFET is given by (3.1), and the switching period T, is given by the inverse of frequency fs , as in (3.2). (3.1) (3.2) In a design, the specifications for the two MOSFETs in the buck converter need to be decided using the above parameters. The switching speed for both MOSFETs should be sufficient such that the turn-on and turn-off transient times are much smaller than T. In addition, the drainsource voltage rating of both power MOSFETs must be larger than Vin , and the drain current rating must be larger than Iload . The larger the ratings chosen, the more robust the design will be. However, high ratings require MOSFETs that are large and therefore more expensive. Typically, the Vds voltage rating is chosen to be about twice as large as Vin , leaving some safety margin in the design. Another factor that needs to be considered is the overall efficiency of the buck converter. For the power MOSFET Q1 , the switching loss can be larger than the conduction loss, thus MOSFETs with faster switching speeds, and therefore smaller die size, are preferred. However, the synchronous rectifier MOSFET Q2 does not have switching loss, but it does handle high currents, so minimizing conduction loss is most important and thus a large die size is preferred. After selecting the MOSFET switches, the inductor value must be determined. The critical inductance value for continuous current mode is given by (3.3), where Rl in the equation 28 represents the resistance of a resistive equivalent load, given by (3.4). In order to produce a smooth output current, the buck inductor is usually chosen to be twice as large as Lcri , or even larger if the volume and the cost of the inductor are tolerable. (3.3) (3.4) The last component to be chosen for the power stage circuit is the capacitor. The minimal capacitance value, Cmin , is given by (3.5), where L is the chosen inductance value and Krip% is the allowed maximum output voltage ripple. A capacitance of 1.5 to 2 times Cmin is typically selected. (3.5) ( ) 3.5.2 Dead-time Detection Circuit Design The detection diode Ddet is proposed to be fabricated together with the synchronous MOSFET Q2 , so instead of finding an appropriate pre-made diode product, the manufacturing requirements need to be defined. The forward voltage drop of the detection diode, VF-det , is a critical parameter since its value should be greater than V1 +iLRon to prevent undesired forward biasing of Ddet during the synchronous MOSFET on time. However, VF-det should be less than V1 +VF-body, where VF-body is the forward voltage of the synchronous MOSFET‟s body diode. Otherwise the detection diode will not turn on as desired when the synchronous MOSFET body diode is on. Therefore, the forward voltage of the detection diode, VF-det , should meet the conditions described in (3.6). (3.6) 29 Voltage source, V1 , is used to provide a reference voltage for the detection signal. Since (3.6) should be met and the forward voltage of a silicon diode is typically 0.7V, V1 should be less than 0.7V. Therefore, a typical value for V1 is 0.1V. To choose R1 and C1 , we need to analyze the variables in the circuit during the time when capacitor C1 is being charged and discharged. Both the rising and falling transition times are much less than the dead-time, therefore the inductor current, iL , can be assumed to be constant, as given by (3.7), where iDdet is the current through the detection diode Ddet , and iDbody is that of the Q2 body diode. Expressions for the circuit current and voltage during the transition can be derived from (3.8) and (3.9), where vDdet (iDdet ) is the detection diode forward voltage given from the diode characteristic curve when detection diode current is at iDdet , and vDbody(iDbody) is the body diode forward voltage at iDbody. vC1 is the voltage across capacitor C1 , which is also the output signal of the detection circuit. Therefore, vdet = vC1 . (3.7) ( (3.8) ) ( ) ( ) (3.9) It is not necessary to solve (3.8) and (3.9), since we are most interested in the impact of R1 and C1 on the detection voltage, vdet , as it drops. It is noted that the smaller C1 and R1 are, the faster the transition is. During the rising transition of the detection voltage, vdet , the diode Ddet turns off. Voltage source V1 , resistor R1 , and capacitor C1 , form a typical first-order RC circuit. The circuit variables are given by (3.10) and (3.11), where iC1 is the current flowing through C1 . 30 (3.10) (3.11) Substituting (3.10) into (3.11), results in a first-order ordinary differential equation, as given by (3.12). The solution to (3.12) is given by (3.13), where the time constant τ 1 is expressed in (3.14). Variable vC1 (t) is the voltage across capacitor C1 at time t. So, vC1 (∞) is the capacitor voltage value at infinite time, in other words, the steady state value, and vC1 (0 +) is that at time zero, or the initial state value. (3.12) () ( ) [ ( ) ( )] ⁄ (3.13) (3.14) The time constant is defined as the time needed for variable vC1 (t) to reach 63% of the steady state value, vC1 (∞). It is often used to represent, or to estimate the transient speed. Therefore, the smaller C1 and R1 are, the smaller τ1 is, and the faster the rising transition will be. Conversely, when the detection diode is on, the voltage across R1 is approximately V1 , so R1 must be large enough so as not to dissipate too much power. For the detection signal adjustment circuit, the magnification parameter, K, of the voltage amplifier needs to be decided. K is given by (3.15), where Vlogic is the threshold voltage of logic high. (3.15) Parameters K and V1 are relatively less critical, compared to other parameters discussed above, such as the time constant τ 1 , the power stage inductor L, and capacitor C. K can be any 31 value that meets (3.15), and theoretically, V1 can be any value that turns on the detection diode only during the body diode conduction time. 3.6 Design Example and Simulation Results 3.6.1 Design Example The proposed dead-time controller is designed for computer regulators, which convert a 12V input voltage to a 1.2V output at a switching frequency of 500kHz and a load current of up to 25A. These parameters and a typical output voltage ripple specification of 1% are summarized in Table 3.2. The parameters provided are used in the design of the buck converter and its dead-time control circuit. Table 3.2 Buck converter design parameters Parameter Value Switching Frequency, fs 500kHz Input Voltage, Vin 12V Output Voltage, Vout 1.2V Load Current, Iload 15A Output Voltage Peak-to-peak Ripple, Krip% 1% Using the design parameters in Table 3.2, the resultant circuit parameters from the design are provided in Table 3.3. 32 Table 3.3 Buck converter resultant parameters Parameters Value Duty Cycle, D 10% Switching Period, T 2us Load Resistance, Rl 80mΩ Critical Inductance, Lcri 72nH Minimal Capacitance, Cmin 300uF Using the parameters in Table 3.2 and Table 3.3, the power stage devices for the buck converter can be chosen, as shown in Table 3.4. Key parameters from the datasheets of these devices are also given. A Si7866DP MOSFET is selected for Q1 [14] and an IRF6691 is selected for Q2 [15]. Table 3.4 The selected MOSFETs, inductor and capacitor for the objective buck converter MOSFETs Power MOSFET Q1 Si7866DP Synchronous MOSFET Q2 IRF6691 Drain-source Voltage, Vds 20V 20V Drain Current, Id 18A 26A Switch On Time, t on 60ns 95ns Switch Off Time, toff 55ns 10ns On Resistance, Ron 2.6mΩ 1.8mΩ Passive Component Value Value Inductor, L 150nH Capacitor, C 560uF The proposed detection circuit parameters are provided in Table 3.5. A 1N4148 detection diode was selected. Its parameters are also provided in Table 3.5 [16]. 33 Table 3.5 Detection circuit parameters Parameters Value Voltage Source, V1 100 mV Resistor, R1 200 Ω Capacitor, C1 90 pF Magnification Times, K 25 Voltage Source, V2 2.5 V Detection Diode 1N4148 Reverse Recovery Time, trr 4 ns Forward Voltage, VF-det 0.62 V-0.72 V 3.6.2 Simulation Results Using PSIM9 PSIM9 was used to simulate the proposed detection circuit in a synchronous buck converter. The circuit used in the simulation is provided in Figure 3.6. 34 V1 R1 C1 Ddet Q1 Q2 L C Vin Figure 3.6 Simulation circuit of the buck converter with the proposed dead-time detection circuit Simulation waveforms of vx, vdet , and the detection signal at the rising edge vdet_r are provided in Figure 3.7. It is noted that body diode conduction occurs when vx goes negative, which occurs twice in a switching period. When vx goes negative, the vdet voltage drops, as expected and the rising edge detection logic signal goes high. Therefore, the proposed circuit functions as expected. 35 D Q2 drainsource voltage [V] tbc_r tbc_t Intervals of body diode conduction Detection capacitor voltage [V] Detection signal voltage [V] tcon Figure 3.7 Simulated of the synchronous MOSFET voltage, vx , detection voltage, vdet , and rising edge detection flag, vdet_r. 3.7 Summary In this chapter, a novel body diode conduction detection circuit has been proposed for the synchronous buck converter. In addition to the circuit, a recommended silicon implementation, design procedure, design example and simulation results have been presented. In order to minimize body diode conduction, a dead-time optimization circuit is required after the detection circuit. Therefore, a novel dead-time optimization circuit is proposed in Chapter 4. 36 Chapter 4 Proposed Dead-time Optimization Circuit 4.1 Overview Using the body diode conduction detection signal of the synchronous MOSFET body diode, there are several methods which can be used to minimize dead-time, depending on the type of the dead-time detector employed for the buck converter. Existing analog and digital methods have been summarized in Chapter 2. In this chapter, a novel analog dead-time optimization circuit is proposed. This chapter is organized in the following manner. The circuit operation is presented in Section 4.2. A design procedure is presented in Section 4.3. A design example and simulation results are presented in Section 4.4. Conclusions are presented in Section Error! Reference source not found.. 4.2 Dead-time Optimization Circuit The proposed optimization circuit can be divided into two circuits, one for the PWM signal processing, and the other for the detection signal processing. A block diagram of the proposed dead-time control circuit is shown in Figure 4.1. The PWM signal processing and detection signal processing circuits are introduced in subsections 4.2.1 and 4.2.2, respectively. An explanation of how the combined circuit optimizes dead-time in subsection 4.2.3. 37 Dead-time Detection Vin vx Synchronous Buck Converter Detection Signal Processing Circuit PWM Signal Processing Circuit vout comparator Gate Signal Load PWM Controller Proposed Dead-time Optimization Circuit Figure 4.1 Block diagram of the proposed dead-time control circuit 4.2.1 The PWM Signal Processing Circuit The purpose of the PWM signal processing circuit is to convert the perpendicular rising edge of the PWM signal to an inclining edge, as illustrated in Figure 4.2. The reason for this conversion will be explained later. The parameter t1 in Figure 4.2 is determined by the processing circuit. 38 Vhigh PWM signal 0 DT T VC2_h Objective vC2 t1 DT T Figure 4.2 The objective output waveform from the PWM signal processing circuit with a PWM input signal The simplest circuit that can achieve the ramped slope is a voltage driven resistor-capacitor (RC) circuit where the ramp amplitude is less than a single time constant. The time constant of an RC circuit determines the slope of the ramp, or how fast the capacitor voltage changes. Therefore, the above mentioned t1 in Figure 4.2 can be related to the time constant of an RC circuit. The proposed PWM signal processing circuit is illustrated in Figure 4.3. Waveforms for the circuit are illustrated in Figure 4.4. The input of this circuit is the PWM signal for the power MOSFET, or the inverted PWM signal for the synchronous MOSFET. The output signal of the circuit is the voltage across capacitor C2 , which is vC2 . VS1 is the voltage source for the control circuit. 39 VS1 R2 vC2 R3 C2 Q3 PWM signal NOT gate Figure 4.3 The proposed PWM signal processing circuit Vhigh PWM signal 0 DT T DT T Vhigh Q3 gate signal 0 VC2_h vC2 VC2_l t2 DT DT T DT+t3 Figure 4.4 Waveforms for the input signal, Q3 gate signal, and the output signal of the proposed PWM signal processing circuit 40 The circuit operation is explained as follows. Initially, Q3 is in the off-state and vC2 is equal to VS1 . When Q3 is turned on, capacitor C2 discharges through R3 and Q3 until it reaches a new steady state value, VC2_l , which depends on the voltage divider formed by R2 and R3 . vC2 remains at this lower value until Q3 is turned off at the beginning of the next switching cycle, when capacitor C2 is charged to VS1 through R2 . It is noted that t1 in Figure 4.2 and t2 in Figure 4.4 are the same parameter. The former is a design objective while the latter is a parameter of the proposed design. Parameters t2 and t3 in Figure 4.4 are controlled by the value of the components used in the Figure 4.3 circuit, and will be discussed later in the design procedure section. 4.2.2 The Detection Signal Processing Circuit The body diode conduction signal is required to be modified. The detection signal processing circuit should generate a voltage signal, which represents the length of the body diode conduction time. Therefore, the circuit output should vary proportional to the excess dead-time. Waveforms of the input and the expected output are given in Figure 4.5. At time t4 , the output voltage, vC3 , is charged up to the reference voltage, VS1 , for the new switching cycle. The time interval, tcon , is the body diode conduction time, during which vC3 is dropping linearly. 41 Body diode conduction signal Vhigh 0 tcon VC3_h Objective voltage, vC3 VC3_l 0 t4 T Figure 4.5 The expected output waveform of the detection signal processing circuit, where the body diode conduction signal is the input. The proposed detection signal processing circuit is illustrated in Figure 4.6. The circuit input is the body diode conduction detection signal which feeds the gate node of MOSFET Q5 . The circuit output is vC3 which is the voltage across the capacitor C3 . MOSFET Q4 is used to charge up the capacitor C3 during each switching cycle. 42 VS1 Q4 R4 vC3 R5 Proposed dead-time detection circuit + Vin - + Q1 Q2 vx - Q5 Detection signal + L C C3 Detection signal processing circuit Vout - Figure 4.6 The proposed detection signal processing circuit The circuit operation is explained as follows. The waveforms are provided in Figure 4.7. At time zero, the buck converter power MOSFET, Q1 , starts to conduct current and the body diode of the buck MOSFET Q2 is off, therefore the detection signal is zero. Since both MOSFETs Q4 and Q5 are off in the detection signal processing circuit, capacitor C3 holds its voltage from the previous state. Q4 is turned on at t5 by a square wave to charge up C3 for the upcoming switching cycle. vC3 rises to a voltage level VC3_h , which is proportional to VS1 . Then at the end of the switching cycle, synchronous MOSFET Q2 is turned off while Q1 has not yet been turned on. This leads to the body diode of Q2 , Dbody, conducting, resulting in the pulsed detection signal from the body diode detection circuit. As a result, Q5 turns on, and C3 is discharged through Q5 and R5 until Q5 turns off, or vC3 reaches a ground voltage level. Here, the body diode conduction time is very short, so when Q5 is turned off at time T, vC3 drops to a voltage value VC3_l , which is greater than the ground voltage, zero. VC3_l is held for the first period of the next switching cycle until Q4 43 turns on and the operation continues the same as the previous switching cycle. Vhigh Body diode conduction signal 0 Vhigh Q4 gate signal 0 tQ4_on tcon VC3_h vC3 VC3_l 0 t5 T Figure 4.7 The input signal, Q4 gate signal, and output signal of the proposed detection signal processing circuit 4.2.3 The Dead-time Optimization Circuit If vC2 from the PWM processing circuit is connected to the positive input of a comparator, while vC3 from the detection signal processing circuit is connected to the negative node of the same comparator, the output of the comparator would be the optimized PWM signal for the power MOSFET, Q1 . Thus, the proposed dead-time optimization circuit is illustrated in Figure 4.8. Waveforms of the input (controller) PWM signal, vC2 , vC3 , and the comparator output, which is the dead-time optimized PWM signal, are provided in Figure 4.9. 44 VS1 R2 VS1 vC2 + R3 vC3 C2 Q3 PWM signal NOT gate Gate signal R4 Q4 VS1 R5 C3 Detection Q5 signal Figure 4.8 The proposed dead-time optimization circuit 45 Vhigh PWM signal 0 DT vC2 VC2_h vC3 VC3_h vC2 & vC3 T VC3_l VC2_l t2 t5 DT T Vhigh Comparator output t6 t6 0 DT T Figure 4.9 Signal waveforms of the non-optimized PWM signal, vC2, vC3, and the comparator output or the optimized PWM signal in the proposed dead-time optimization circuit when t5 is smaller than DT The dead-time optimization circuit operation is explained as follows. At time zero, the PWM signal changes from low to high, causing vC2 to increase, while vC3 is at VC3_l . When vC2 reaches VC3_l , the comparator output turns from low to high. The delay of the rising edge between the comparator output and the PWM signal, noted as t6 in Figure 4.9, is the optimized dead-time for the rising edge of the PWM signal for the power MOSFET, Q1 . For the PWM falling edge, when the PWM signal switches from high to low at time DT, vC2 46 quickly drops less than vC3 , thus the comparator output switches from high to low. The drop occurs quickly provided the circuit parameters are properly chosen. This leads to virtually no delay between the trailing edges of the comparator output and the PWM signal. The parameters noted in Figure 4.9, such as VC2_h , VC3_h , and t2 , depend on the circuit elements and will be discussed in the next section. In addition, certain the parameters influence other parameters. For example, the value of tcon determines VC3_l. The longer tcon is, the lower VC3_l is, and thus, the shorter t6 is. For the waveforms in Figure 4.9, it is assumed that t5 is less than DT, however this is not always true. The parameter t5 is usually preset in the dead-time controller, while DT varies primarily with input voltage and also with load. Generally, when the duty cycle of the buck converter is relatively small, t5 is greater than DT. In these situations, waveforms of the proposed dead-time optimization circuit differ as illustrated in Figure 4.10. 47 Vhigh PWM signal 0 DT T vC2 VC2_h vC3 VC3_h vC2 & vC3 VC3_l VC2_l t2 t5 DT T Vhigh Comparator output t6 t6 0 DT T Vhigh AND gate output t6 0 t6 t7 DT t7 T Figure 4.10 Signal waveforms of the non-optimized PWM signal, vC2, vC3, and the comparator output or the optimized PWM signal in the proposed dead-time optimization circuit when t5 is greater than DT When DT is less than t5 , the trailing edge of the comparator output has a small delay, t7 , from that of the PWM signal. The delay is due to the capacitor voltage, vC2 , not being able to drop 48 instantaneously. This delay is much smaller in Figure 4.9 than in Figure 4.10, since the comparator output reverses when vC2 drops to VC3_h . In Figure 4.10, vC2 needs to drop further than VC3_l , resulting in the delay in the trailing edge. To avoid this delay, an AND gate is used, with the PWM signal and the comparator output as its two inputs. Therefore, the AND gate output has the rising edge with the optimized dead-time which eliminates the undesired delay at the trailing edge. 4.3 Dead-time Optimization Circuit Design Procedure In this section, equations of circuit variables are provided, in order to make it clear how circuit elements influence the waveforms. Design procedures for the PWM signal and detection signal processing circuits are also introduced. Requirements for each element in the circuit are provided as conclusions at the end of each subsection. 4.3.1 The PWM Signal Processing Circuit Design Procedure Referring to Figure 4.3 and Figure 4.4, during time 0 to t2 , MOSFET Q3 is off, so the current from the voltage source VS1 flows through R2 to charge up capacitor C2 . Therefore, the dynamic equations of the circuit during this interval are given by (4.1) and (4.2), where vC2 and vR2 are the voltages across elements C2 and R2 respectively, and iC2 and iR2 are the currents flowing through C2 and R2. It is noted that in the analysis that follows, all lower case voltages and currents are a function of time. (4.1) (4.2) Equations (4.1) and (4.2) can be written as a single first-order ordinary differential equation, as given by (4.3), with the initial state of the capacitor voltage given by (4.4). 49 (4.3) ( ) (4.4) The solution to (4.3) is provided in (4.5), where time constant τ 2 is the time for vC2 to reach 63% of VC2_h from VC2_l . Furthermore, at 3τ2 , vC2 rises 95% of VC2_h . Therefore, t2 in Figure 4.4 can be approximated using (4.6). ⁄ (4.5) (4.6) At time DT, Q3 is turned on by the inverted PWM signal, allowing C2 to discharge through R2 and Q3. The dynamic equations of this transition are given by (4.7) and (4.8), where vR3 is the voltage across R3 and iR3 is the current through R3 . (4.7) (4.8) Similarly, (4.7) and (4.8) can also be expressed as a first-order ordinary differential equation, given by (4.9). Equation (4.10) provides the initial state of vC2 . ( ) ( ) (4.9) (4.10) The solution to (4.9) is provided in (4.11), where the time constant of this first-order transition is τ 3 . The parameter t3 in Figure 4.4 is the time for vC2 to decrease from VC2_h to VC2_l. Therefore, t3 can be approximated by (4.12). 50 ⁄ (4.11) (4.12) Using (4.5) and (4.11), the parameters, VC2_h and VC2_l , in Figure 4.4, Figure 4.9, and Figure 4.10, are given by (4.13). (4.13) The parameter t3 should be much less than t2 (Figure 4.4), therefore, τ 3 should be much less than τ 2 . Accordingly, R3 is much less than R2 . Furthermore, if R3 is much less than R2 , VC2_l can drop to a very low value, leaving design flexibility for the choice of VC3_l. As for t2 , it should be less than DT, except for very low duty cycles, so the requirement can be expressed by (4.14) when choosing the resistor R2 and the capacitor C2 . (4.14) 4.3.2 Detection Signal Processing Circuit Design Procedure For the detection signal processing circuit, the discharge rate of capacitor C3 can be neither too fast nor too slow, so that during tcon (representing the body diode conduction time), vC3 will reduce from VC3_h to VC3_l , yet not to zero, nor VC2_l . vC3 will not be less than VC2_l , provided that tcon is between zero and 0.05T. The circuit elements should then be picked to meet this requirement. The dynamic equations of the circuit when capacitor C3 is charged at t5 (Figure 4.9) are derived in the same manner as that of capacitor C2 . Equations (4.15) and (4.16) are derived using Kirchhoff‟s voltage and current laws, respectively. Equations (4.15) and (4.16) can be written as a first-order ordinary differential equation, given in (4.17), where (4.18) is the initial state of vC3 . 51 The solution to (4.17) is provided in (4.19). (4.15) (4.16) (4.17) ( () ) (4.18) ( ) ⁄ (4.19) Similarly, dynamic equations during the transition when C3 is discharged are given by (4.20) and (4.21). The equivalent first-order ordinary differential equation is provided in (4.22) with its initial state. The solution to this equation is given by (4.23). (4.20) (4.21) ( () ) ⁄ (4.22) (4.23) The value of VC3_l , which is a floating variable related to the value of tcon , is expressed by (4.24). ( ⁄ ) (4.24) As noted at the beginning of this section, τ 5 can neither be too long, nor too short. A reasonable range for τ5 is three time constants between 5% and 15% of a switching period, expressed by (4.25). 52 (4.25) Among the four time constants, τ 2 - τ5 , in this section, τ 2 is more critical than τ3 . In addition, τ 5 is more critical than τ 4 . τ 2 represents the inverse of the rising slope of vC2 . If τ2 is large, vC2 rises slowly, resulting in a large dead-time. As an optimum minimized dead-time is required, we need to minimize τ 2 , while ensuring that τ 2 is sufficiently large to prevent cross-conduction. Therefore τ 2 is governed by (4.14). On the other hand, τ 3 is less important, since an AND gate is used to eliminate its effect at the falling edge of vC2 . Similarly, the value of τ 5 influences the dead-time directly while that of τ 4 does not. 4.4 Design Example and Simulation Results 4.4.1 Design Example Using the design procedure provided in Section 4.3, a PWM signal processing circuit design was completed. A list of the circuit elements and is provided in Table 4.1. Values of the resistors and capacitors are chosen according to the standard E24 values for circuit elements, as given in 0. An Si1555DL MOSFET was chosen for the Q3 MOSFET, due to its low gate charge and fast transition speed [17]. An NC7SZ04 inverter from FairChild Semiconductor was selected for the NOT gate. This device has a propagation delay of 2.9ns, which is suitable for a 500kHz switching frequency application [18]. 53 Table 4.1 The parameters in the design of the PWM signal processing circuit Parameter Value Voltage Source, VS1 6V Resistor, R2 430Ω Resistor, R3 51Ω Capacitor, C2 51pF MOSFET Q3 Si1555DL Gate Charge, Qg 0.8nC Switch On Time, ton 16ns Switch Off Time, toff 10ns Drain-source Voltage, Vds 20V Drain Current, Id 0.66A NOT gate NC7SZ04 Propagation Delay, tpd 2.9ns Input Rise and Fall Rate 5ns/V The circuit parameters used in the detection signal processing circuit are given in Table 4.2. The voltage source, VS1 , was chosen to be 6V, which is the same voltage required for the buck controller. Resistors R4 and R5 were chosen to be equal so that the charge and discharge transitions for capacitor C3 are symmetric, resulting in maximum design flexibility for tcon . 54 Table 4.2 The parameters in the design of the detection signal processing circuit Parameter Value Voltage Source, VS1 6V Resistor, R4 10kΩ Resistor, R5 10kΩ Capacitor, C3 5.1pF The final component in the dead-time optimization circuit that was selected is the comparator. Not all high speed comparators can meet the design requirements. More specifically, comparators with small bias currents do not work well in this application. The bias current is defined as the average of the two input currents, provided in the manufactures datasheet. Comparators with very low bias currents (e.g. several nA), tend to charge up capacitor C3 when vC2 is larger than vC3 , which leads to undesired circuit operation. Therefore, an LT1394 comparator was selected, which has an input bias current of 2µA [19]. Table 4.3 Parameters of the comparator LT1394 Comparator LT1394 Propagation Delay, tpd 7ns Input current, Iin_c 10mA Input Bias Current, IB 2µA 4.4.2 Simulation Results The proposed dead-time optimization circuit was simulated using PSIM9. The circuit is provided in Figure 4.11 and waveforms are provided in Figure 4.12. 55 vpwm Q3 R3 PWM signal processing circuit C2 VS1 R2 VS1 vC2 vg1 Q4 vC3 R4 R5 vdet_r_d C3 Detection signal processing circuit Q5 Figure 4.11 The dead-time optimization simulation circuit 56 Detection signal voltage [V] PWM signal voltage [V] Q1 gate signal voltage [V] (a) Detection signal voltage [V] tcon 20.3ns PWM signal voltage [V] Q1 gate signal voltage [V] td 6.09ns (b) Figure 4.12 Simulation results of the dead-time optimization circuit (a) the delayed detection signal for the rising edge, the PWM signal, and the gate signal, (b) the enlarged drawing of the above signals To test the proposed dead-time optimization circuit, pulse signals with a width of 20ns were input as a detection signal to replicate the output of the circuit proposed in Chapter 3. From 57 Figure 4.11(b), it is noted that the delay time between the rising edge of the PWM signal and that of the Q1 gate signal is 6.09ns. This indicates that the proposed circuit is able to produce a smaller dead-time, given a large dead-time from the previous switching cycle. Therefore, the circuit operates as expected 4.5 Summary In this chapter a novel dead-time optimization circuit has been proposed for the synchronous buck converter. In addition to the circuit, a design procedure, design example and simulation results have been presented. In order to minimize body diode conduction, which degrades the power converter efficiency, the proposed body diode detection circuit introduced in Chapter 3 and the proposed dead-time optimization circuit introduced in this chapter can be combined into a new dead-time controller circuit. The combined circuit and simulation results are presented in Chapter 5. 58 Chapter 5 Simulation Results of the Dead-time Control Circuit 5.1 Overview Body diode conduction in a synchronous buck DC-DC converter degrades the power conversion efficiency and increases heat generation in the buck synchronous MOSFET, which degrades the converter reliability. To solve this problem, a new circuit has been proposed to minimize body diode conduction. To minimize body diode conduction, detection and optimization circuits are required. A body diode conduction detection circuit was proposed in Chapter 3 and an optimization circuit was proposed in Chapter 4. In this chapter, a current mode PWM controller is first presented in Section 5.2. It is used to regulate the output voltage to compensate for input voltage, or load current changes. Next, the proposed dead-time controller is integrated with the PWM control circuit, forming the complete closed-loop buck converter control for the PWM rising edge in Section 5.3. The dual PWM edge combined circuit is presented in Section 5.4. These sections include simulation waveforms using PSIM9, verifying proper closed- loop operation of the buck converter. In Section 5.5, a comparison is made between the proposed circuit and a benchmark circuit, illustrating the improvements in dead-time and efficiency with the proposed circuit. 5.2 Closed-loop Control A current mode PWM controller was designed to regulate the output voltage of the buck converter [20]-[22]. The controller and synchronous buck converter are illustrated in Figure 5.1. Waveforms illustrating the current mode PWM controller operation are illustrated in Figure 5.2. The clock signal initiates the PWM pulse to turn the high-side buck switch at a fixed frequency, 59 e.g. 500kHz. The pulse ends when the inductor current reaches the threshold established by the error amplifier, which amplifies any low frequency error in the output voltage in comparison to the desired reference output. The error signal controls the inductor peak current rather than the width of the pulse, and therefore is called current mode control. Four switching cycles of the output voltage of the converter are illustrated in Figure 5.3. The maximal, average, and minimal value of the output at steady state is 1.212V, 1.200V, and 1.182V respectively. Therefore, the converter output ripple is 30mV. L + Q1 Vin Q2 Isense C Vout - Output voltage error amplifier RS latch Figure 5.1 A current mode PWM controller for the buck converter 60 Turns PWM on; set Clock voltage [V] Error voltage & current sensing voltage [V] Comparator output voltage [V] Latch output voltage [V] Comparator two inputs Turns PWM off; reset PWM pulses Figure 5.2 Waveforms from the current mode PWM controller 61 1.182 Output voltage [V] 1.200 1.182 Figure 5.3 Four switching cycles of the output voltage of the buck converter There are several advantages of current mode control. First, by controlling the peak current, the pole due to the buck converter output filter inductor is effectively removed from the dynamics, so there is only one pole due to the output capacitor, compared with 2 poles using voltage mode control [21]. Therefore, the error amplifier compensation circuit is simpler. Secondly, the input voltage changes are compensated instantaneously by the current sensor and PWM comparator, allowing the error amplifier to correct for load variation exclusively. Finally, current mode control monitors the peak inductor current, simplifying over current protection circuit design. 5.3 PWM Rising Edge with Dead-time Control The circuits proposed in Chapter 3 and Chapter 4 were integrated with the current mode PWM controller presented in Section 5.2. The combined circuit minimizes the dead-time for the rising edge of the PWM signal, and is illustrated in Figure 5.4. The proposed dead-time control circuit follows the current mode PWM controller output signal, vpwm . 62 Body diode conduction detection circuit V1 Q3 R1 R3 C2 VS1 C1 Ddet R2 vx vC2 L Q1 VS1 Q2 C Load vg1 Q4 R4 vC3 R5 vdet_r_d vpwm C3 Q5 Dead-time optimization circuit Current mode PWM controller Figure 5.4 The proposed dead-time control circuit for the rising edge combined with the current mode PWM control circuit The circuit in Figure 5.4 has 4 sub-circuits: 1) the synchronous buck converter power stage, 2) the current mode PWM control circuit, 3) the dead-time detection circuit, and 4) the dead-time optimization circuit. Each of these sub-circuits has been introduced. The current mode PWM controller generates PWM signals that ensure the output voltage of the buck converter meets the design specifications. The PWM signal and the dead-time detection signal from last switching cycle are input to the dead-time optimization circuit. The output of the dead-time optimization circuit is the gate signal for the power MOSFET Q1 , with an optimized minimal dead-time inserted on the rising edge of the original PWM signal to prevent simultaneous turn-on of Q1 and Q2 . 63 Simulation results of this circuit using PSIM9 are given in Figure 5.5. Waveforms of the output of the PWM controller, vpwm , the gate signal for Q1 , vg1 , and the voltage across Q2 , vx, are provided. Referring to Figure 5.5(b), it is clear that there is a small time delay, td , between the rising edge of vpwm and that of vg1 . This is achieved by the dead-time optimization circuit, and the value of td is affected by the body diode conduction time of the synchronous MOSFET Q2 in last switching cycle. The body diode conduction time of Q2 for this switching cycle, tcon_org , is noted, as well as td . 64 Q1 gate signal voltage & PWM signal voltage [V] Q2 drainsource voltage [V] (a) Q1 gate signal voltage & PWM signal voltage [V] td 14ns Q2 drainsource voltage [V] tcon_org 9ns (b) Figure 5.5 (a) PWM controller output, vpwm, Q1 gate signal, vg1, and vx over five switching cycles; and (b) vpwm, vg1, and vx illustrating one pulse width 5.4 Dual PWM Edge Dead-time Control In the last subsection, it was noted that the dead-time control of the proposed circuit is achieved by adding an optimized delay to the rising edge of the pulse. However, the trailing edge of the pulse also requires dead-time optimization. Therefore, a second dead-time optimization 65 circuit can be added to postpone the rising edge of the Q2 gate signal to avoid current shoot through. The complete circuit with two dead-time optimizers adjusting the dead-time at either edge of the PWM pulse is provided in Figure 5.6. 66 vdet_r vdet_r_d Dead-time optimizer for the rising edge V1 Q3 R2 C2 Q2 Q1 vdet_t Dead-time optimizer for the falling edge C1 Ddet R3 VS1 vdet R1 Detection Circuit + vx - vC2 L C + vout - VS1 vg1 vg2 Q4 vC3 R4 Current mode PWM controller R5 C3 Q5 vpwm vpwm_i Figure 5.6 Complete dead-time optimization circuit including dual edge PWM dead-time control and closed-loop output voltage regulation 67 The complete dead-time control circuit was simulated using PSIM9. Waveforms of the Q1 gate signal, vg1 , the PWM pulse generated by the current mode PWM controller, vpwm , Q2 gate signal, vg2 , the inverted PWM pulse, vpwm_i , and the voltage across the synchronous buck MOSFET Q2 , vx, in steady state are provided in Figure 5.7. One PWM pulse of the above noted waveforms in provided in Figure 5.7(b). From the figure, it is noted that the rising edges of both vpwm and vpwm_i are postponed while the trailing edges are not. Since vpwm and vpwm_i are complementary, dead-time is added to both edges of the pulse. Body diode conduction of the synchronous MOSFET occurs when the waveform is negative. Body diode conduction intervals are visible in Figure 5.7(c) and (d). The body conduction time at the rising edge, tbc_r , is 4.06ns. While that at the trailing edge, tbc_t , is 3.98ns. These values are very low, and combined, represent less than 0.5% of a total switching period. 68 Q1 gate signal voltage & PWM signal voltage [V] Q2 gate signal voltage & inverted PWM signal voltage [V] Q2 drainsource voltage [V] (a) Q1 gate signal voltage & PWM signal voltage [V] Q2 gate signal voltage & inverted PWM signal voltage [V] Q2 drainsource voltage [V] (b) Q2 drainsource voltage [V] tbc_r 4.06ns (c) Q2 drainsource voltage [V] tbc_t 3.98ns (d) Figure 5.7 (a) Waveforms of the Q1 gate signal, PWM signal, Q2 gate signal, inverted PWM signal, and the voltage at the joint point of the two MOSFETs; (b) one PWM pulse; (c) body diode conduction time at the rising edge; (d) body diode conduction time at the falling edge 69 5.5 Comparison with Adaptive Dead-time Control In this subsection, the proposed circuit is compared with a benchmark adaptive dead-time controller. 5.5.1 Body Diode Conduction Time Comparison Adaptive dead-time control is used in the TPS2832, fast synchronous buck MOSFET driver IC. In the datasheet for this driver, it is noted that the minimal dead-time achievable is 15ns [23]. Therefore, a fixed dead-time controller was modeled in PSIM to represent the TPS2832 benchmark circuit. The dead-time was set to 15ns. The buck converter with the current mode PWM controller and a 15ns fixed dead-time controller is illustrated in Figure 5.8. Vin Q1 Q2 vx - vg1 + L + Isense C vout - vg2 td 15ns vpwmRS latch Fixed dead-time controller Current mode PWM controller Figure 5.8 The benchmark circuit (fixed dead-time control) Waveforms of the voltage across the buck synchronous rectifier, vx, for the benchmark circuit and the proposed circuit are provided in Figure 5.9 for a load current of 15A. The duration 70 when vx is negative is the conduction time of the synchronous MOSFET body diode. It is noted that the body diode conduction times at rising and trailing edges for fixed dead-time control are 15.4ns and 15.9ns, respectively, and those in the proposed circuit are 4.06ns and 3.98ns. Therefore, the body diode conduction time is reduced significantly at both edges of the PWM pulse. Similar buck synchronous MOSFET drain voltage waveforms are also provided in Figure 5.10 for a load current of 20A. At 20A load, the body diode conduction times with fixed deadtime control are 14.0 and 16.1ns, while those in the proposed circuit are 2.01 and 3.94ns. It is noted that for all edges in the two examples, the body diode conduction time has been reduced by at least a factor of four times, which reduces body diode conduction loss by at least four times. Fixed dead-time control Q2 drainsource voltage [V] tbc_r tbc_t 15.9ns 15.4ns Proposed dead-time control Q2 drainsource voltage [V] (a) tbc_t tbc_r 3.98ns 4.06ns (b) Figure 5.9 Buck synchronous MOSFET voltage at a load current of 15A (a) benchmark fixed dead-time control (b) proposed dead-time control 71 Fixed dead-time control Q2 drainsource voltage [V] tbc_r tbc_t 16.1ns 14.0ns (a) Proposed dead-time control Q2 drainsource voltage [V] tbc_r tbc_t 3.94ns 2.01ns (b) Figure 5.10 Buck synchronous MOSFET voltage at a load current of 20A (a) benchmark fixed dead-time control (b) proposed dead-time control 5.5.2 Efficiency and Loss Comparison In this subsection an efficiency comparison is presented between the benchmark fixed deadtime controller and the proposed dead-time controller. The purpose of reducing the body diode conduction time is to reduce the conduction loss in the device, thus improving the efficiency of the buck converter. The average input power of the buck converter over a switching cycle is given by (5.1). The input voltage can be considered as a constant, regardless of the line voltage variations. Therefore it can be taken out of the integration operator, and the input power can be expressed as the product of the DC input voltage and the average input current. ∫ ∫ ∫ (5.1) The average output power over a switching cycle is given by (5.2). Since it is the square of 72 the output voltage is integrated, the root mean square of the output voltage is required to get the average output power. The power conversion efficiency is the ratio of the output power to the input power and is given by (5.3). ∫ ∫ [( ) ] ∫ ( ) ( ) (5.2) (5.3) The circuit presented in Figure 5.6 was simulated using PSIM9. All parameters remained unchanged except the buck converter load resistance (i.e. 80mΩ in the figure). At 10A load current, the average input current of the buck converter with the proposed dead-time controller is 1.103A, and the root mean square of the output voltage is 1.201V. As a result, the average input power, output power and efficiency of the proposed circuit at 10A load current are given by (5.4), (5.5), and (5.6) respectively. (5.4) ( ) ( ) (5.5) (5.6) Similarly, using the benchmark circuit in Figure 5.8, the efficiency of the benchmark circuit at 10A load current is 89.2%. Therefore, an improvement of 1.6 % is achieved with the proposed dead-time control, corresponding to a power loss reduction of 0.24W, or 16.3% reduction in the total conduction losses. Additional simulations were run for both circuits at load currents in 5A increments from 5A to 25A. The average input current and the root mean square output voltage are recorded in Table 73 5.1 and 5.2. The data in Table 5.1 is for the converter with the proposed dead-time controller while the data in Table 5.2 is for the benchmark circuit. Using (5.1) to (5.3), the efficiencies of the buck converter can be calculated and these results are also given in Table 5.1 and 5.2. Efficiency curves as a function of a load are provided in Figure 5.11. From Figure 5.11, it is noted that there is an improvement of more than one percentage point across the full load range with the proposed circuit in comparison to the benchmark. In order to understand the impact of this efficiency improvement the converter conduction loss must be examined. Table 5.1 Simulated efficiency measurement data of the buck converter with proposed deadtime control circuit Load Current ILoad [A] Load Resistance RL [Ω] Average Input Current Iin_avr [A] Root Mean Square Output Voltage Vout_rms [V] Input Power Pin [W] Output Power Pout [W] Efficiency η [% ] 5 0.24 0.542 1.201 6.51 6.01 92.3% 10 0.12 1.103 1.201 13.24 12.02 90.8% 15 0.08 1.709 1.201 20.51 18.02 87.9% 20 0.06 2.329 1.200 27.94 24.01 85.9% 25 0.048 2.984 1.200 35.81 29.98 83.7% Table 5.2 Simulated efficiency measurement data of the benchmark circuit Load Current ILoad [A] Load Resistance RL [Ω] Average Input Current Iin_avr [A] Root Mean Square Output Voltage Vout_rms [V] Input Power Pin [W] Output Power Pout [W] Efficiency η [% ] 5 0.24 0.550 1.201 6.60 6.01 91.1% 10 0.12 1.123 1.201 13.48 12.02 89.2% 15 0.08 1.733 1.201 20.80 18.02 86.6% 20 0.06 2.355 1.200 28.26 24.01 85.0% 25 0.048 3.037 1.200 36.45 29.98 82.2% Converter conduction loss is the power that is dissipated by the buck converter MOSFET switches rather than the load. This loss is given by (5.7) since PSIM does not include second 74 order loss components, including switching loss, gate loss, and core loss. 94% 92% 90.8% 90% 89.2% Efficiency [%] 88% An improvement of 1.6% 86% 84% 82% proposed dead-time control circuit 80% benchmark 78% 76% 5 10 15 Load Current [A] 20 25 Figure 5.11 A comparison of the buck converter efficiency between the proposed circuit and the benchmark circuit at different load currents (5.7) Pls1 is the conduction loss in the buck converter with the proposed dead-time controller, while Pls2 is that of the benchmark circuit. By definition, Pls1 and Pls2 values at different load currents can easily be calculated using the data provided in Table 5.1 and 5.2. The difference in conduction loss between the proposed circuit and benchmark circuit is given by (5.8) (5.8) The loss reduction, expressed as a percentage relative to the benchmark converter power loss, is given by (5.9). (5.9) The absolute loss reduction and loss reduction data as a function of load are provided in 75 Table 5.3. Observing the last column of Table 5.3, it is noted that the proposed dead-time controller can reduce the power loss of the buck converter by up to 16.3%. The loss reduction is significant since the savings represents reduced localized heating in the synchronous rectifier MOSFET, which occupies a board are of less than 1cm2 . Reduced heat leads to increased device lifetime in addition to energy savings. Table 5.3 Power loss reduction by the proposed circuit Load Current IL [A] Proposed circuit power loss Pls1 [W] Benchmark circuit power loss Pls2 [W] Loss reduction ΔPls [W] Loss reduction percentage ΔP [% ] 5 0.50 0.59 0.1 15.1% 10 1.22 1.46 0.2 16.3% 15 2.49 2.78 0.3 10.5% 20 3.93 4.25 0.3 7.4% 25 5.83 6.47 0.6 9.9% Curves representing the conduction loss in the proposed circuit and benchmark circuit are provided in Figure 5.12. 76 7 6.47 proposed dead-time control circuit 6 benchmark 5.83 Conduction Loss [W] 5 4.25 4 3.93 2.78 3 2.49 2 1 0 1.46 0.59 A reduction of 0.64W, 9.96% 1.22 0.50 5 10 15 20 25 Load Current [A] Figure 5.12 Comparison of the conduction loss in the proposed circuit and benchmark 5.6 Summary Simulation results for the proposed dead-time control circuit were presented in this chapter. The synchronous buck converter with a current mode PWM controller is the application for the dead-time controller. A fixed dead-time benchmark circuit with 15ns dead-time was used for comparison with the proposed circuit. With the proposed analog dead-time control circuit, the body diode conduction time is minimized to under 5ns. The simulation results clearly demonstrate the reduction of the body diode conduction. The converter efficiencies resulting from the two dead-time controllers are also calculated and compared as a function of load current. In comparison to the benchmark fixed dead-time controller, the proposed dead-time controller enables an efficiency improvement of 1.6% for the synchronous buck voltage regulator. The reduction of the power loss in the buck converter is also analyzed to illustrate the significance of the improvement. The proposed buck converter reduces the total conduction losses by 16.3%. 77 Chapter 6 Conclusions and Future Work 6.1 Conclusions In Chapter 1, the synchronous buck converter and the concepts of body diode conduction and dead-time were introduced. In addition, the research motivation and objectives were established. In Chapter 2, a literature review was presented. In Chapter 3, a novel body diode conduction detection circuit was proposed. In addition to the circuit, a signal adjustment circuit was presented, a possible silicon implementation was proposed and a design procedure, design example and simulation results were presented. In Chapter 4, a novel dead-time optimization circuit was proposed, including signal processing circuits for body diode conduction detection and PWM signal processing. This was followed by a design procedure, design example and simulation results. In Chapter 5, a current mode control implementation was presented in order to enable closed-loop output voltage control. Then, the proposed circuits from Chapter 3 and Chapter 4 were combined with the controller and a complete dead-time control circuit was presented for a synchronous buck voltage regulator. The new proposed circuit was then compared with a commercially available dead-time control integrated circuit model as a benchmark enabling a direct comparison of time domain, efficiency and loss results via PSIM simulation. Notably, for the 12V to 1.2V power conversion application studied in this thesis, the proposed circuit can be projected to reduce the voltage regulator conduction loss by up to 0.64W, or 16.3% at 25A load. 78 6.2 Summary of Contributions The objective of this thesis is to propose a fast and accurate dead-time control circuit that can be applied to high frequency synchronous buck converters and that can minimize the body diode conduction time of the buck converter synchronous MOSFET. Simulation results were presented to prove that the proposed circuit meets the design specifications and manages to increase the efficiency of the buck converter. The novel contributions proposed in this thesis include the following. 1) The proposed dead-time detection circuit Integrating a detection diode on the same die as the synchronous MOSFET was proposed. With additional circuitry, the detection diode is able to provide an accurate signal of the body diode conduction time of the synchronous MOSFET. Furthermore, since the detection diode and the MOSFET are on the same die, external wires are not required, reducing parasitic components and therefore enabling the circuit to work at higher frequencies. 2) The proposed dead-time optimization circuit A novel analog dead-time optimization circuit was proposed. Rather than a digital optimization circuit using a digital signal processor, an analog circuit eliminates one-step window dithering in steady state, which is caused by not being able to have continuous dead-time values with a digital signal processor. Furthermore, a digital controller usually optimizes the dead-time step by step in each switching cycle. While the proposed optimization circuit is able to get the optimal dead-time in one switching period. Finally the proposed analog optimization circuit can be used with other dead-time detection circuits. 3) The proposed dead-time control circuit A dead-time control loop based on using the proposed detection and optimization circuits 79 was implemented and applied to a current mode controlled synchronous buck converter. One advantage of the proposed dead-time controller is accuracy. Due to the sensitive detection circuit and being able to have continuous dead-time control, the proposed dead-time controller manages to make the body diode conduction time quite small, e.g. 2ns at 20A load current. Another advantage is the potential for fast transient response since the proposed dead-time controller is a one-step predictive controller. It is able to achieve the optimal dead-time in one switching cycle. 6.3 Future Work The following future work can be considered. 1) Hardware implementation In this thesis, the simulation software PSIM9 was used to verify the proposed circuit. Although the simulation results prove the feasibility of the circuit and the potential for improved efficiency of the buck converter, there may be unexpected problems occurring in the real circuit, requiring modifications to the proposed circuit. 2) Additional applications The proposed dead-time control circuit was designed for the synchronous buck converter operating at 500kHz, 12V input, and 1.2V output, which is an application broadly used in computer voltage regulators. It is worth trying to make adjustments so that the proposed deadtime control circuit can be extended to a broader range of synchronous buck converter applications. 80 References [1] S. Mapus, “Predictive gate drive boosts synchronous dc/dc power converter efficiency,” Texas Instruments, Dallas, Application Report, SLUA281, April 2003. [2] J. A. Abu-Qahouq, H. Mao, H. J. Al-Atrash, and I. Batarseh, “Maximum efficiency point tracking (MEPT) method and digital dead-time control implementation,” IEEE Trans. Power Electronics, vol. 21, no. 5, pp. 1273-1281, Sep. 2006. [3] V. Yousefzadeh, D. Maksimovic, “Sensorless optimization of dead-times in dc-dc converters with synchronous rectifiers,” IEEE Trans. Power Electronics, vol. 21, no. 4, pp. 994-1002, July 2006. [4] A. Zhao, A. A. Fomani, and W. T. Ng, “One-step digital dead-time correction for dc-dc converters,” in Proc.25 th Annu. The Applied Power Electronics Conference and Exposition, pp. 132-137, Feb. 2010. [5] W. Yan, C. Pi, W. Li, and R. Liu, “Dynamic dead-time controller for synchronous buck converters,” IEEE Electronics Letters, vol. 46, pp. 164-165, Jan. 21, 2010. [6] O. Trescases, W. T. Ng, and S. Chen, “Precision gate drive timing in a zero-voltageswitching dc-dc converter,” in Proc.16 th Annu. International Symposium on Power Semiconductor Devices and ICs, pp. 55-58, May 2004. [7] A. Pizzutelli, A. Carrera, M. Ghioni, and S. Saggini, “Digital dead-time auto-tuning for maximum efficiency operation of isolated dc-dc converters,” in Proc. 38 th Annu. Power Electronics Specialists Conference, pp. 839-845, June 2007. [8] W. Al-Hoor, J. Abu-Qahouq, L. Huang, C. Ianello, W. Mikhael, and I. Bataseh, “Multivariable adaptive efficiency optimization digital controller,” in Proc. 39 th Annu. Power Electronics Specialists Conference, pp. 4590-4596, June 2008. 81 [9] B. Acker, C. R. Sullivan, and S. R. Sanders, “Synchronous rectification with adaptive timing control,” in Proc. 26 th Annu. Power Electronics Specialists Conference, pp. 88-95, June 1995. [10] A. V. Peterchev, and S. R. Sanders, “Digital loss-minimizing multi-mode synchronous buck converter control,” in Proc. 35 th Annu. Power Electronics Specialists Conference, pp. 3694-3699, June 2004. [11] F. Lima, M. Santos, J. Barata, and J. Aguiar, “Dead-time control system for a synchronous buck dc-dc converter,” in Proc. International Conference on Power Engineering, Energy and Electrical Drives, pp. 423-428, April 2007. [12] PSIM User Manual, Powersim Inc., Woburn, MA, 2001. [13] B. Andreycak, “The UC3823A,B and UC3825A,B enhanced generation of PWM controllers”, TI Unitrode Corporation, Merrimack, NH, Application Note, 1999. [14] Si7866DP N-Channel 20-V (D-S) MOSFET Data Sheet, Vishay Siliconix, Shelton, CT, Aug. 2003. [15] IRF6691 HEXFET Power MOSFET plus Schottky Diode Data Sheet, International Rectifier, El Segundo, CA, Nov. 2005. [16] IN4148; 1N4448 High-speed Diodes Data Sheet, Philips Semiconductors, Netherlands, Jan. 2002. [17] Si1555DL Complementary Low-Threshold MOSFET Pair Data Sheet, Vishay Siliconix, Shelton, CT, May 2010. [18] NC7SZ04 TinyLogic UHS Inverter Data Sheet, Fairchild Semiconductor Corporation, San Jose, CA, Feb. 1996. 82 [19] LT1394 7ns, Low Power, Single Supply, Ground-Sensing Comparator Data Sheet, Liner Technology Corporation, Milpitas, CA, 1998. [20] UC3842 Current-mode PWM Controller Product Specification, Philips Semiconductors, Netherlands, Aug. 1994. [21] UC3842/3/4/5 Provides Low-cost Current-mode Control Application Note, TI Unitrode Corporation, Merrimack, NH, pp. 53-66, Nov. 1998. [22] D. W. Hart, Introduction to Power Electronics. Upper Saddle River, NJ: Prentice-Hall, 1997, pp. 273-277. [23] TPS2832 ,TPS2833 Fast Synchronous-buck MOSFET Drivers with Dead-time Control Data Sheet, Texas Instruments Inc., Dallas, TX, Jan. 2001. 83 Appendix A. E24 is one of the standard ranges set by Electronic Industries Association (EIA) with a tolerance of 5% for passive component values. The numbers in the table are the available values for each decade. Table A.1 Preferred values for passive circuit components E24 (5%) 10 11 12 13 15 16 18 20 22 24 27 30 33 36 39 43 47 51 56 62 68 75 82 91 84
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A predictive analog dead-time control circuit for a high efficiency synchronous buck converter Mei, Luyan 2012
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Title | A predictive analog dead-time control circuit for a high efficiency synchronous buck converter |
Creator |
Mei, Luyan |
Publisher | University of British Columbia |
Date Issued | 2012 |
Description | The synchronous buck DC-DC power converter is the most common switching converter circuit used to step down a DC input voltage to a low logic level DC output voltage in computer applications. The synchronous buck converter has two power MOSFET switches that turn on in a complementary fashion. However, to avoid high input current spikes, a short duration of dead-time (i.e. a time interval when neither switch is on) is required. During dead-time intervals, the buck converter synchronous MOSFET internal body diode conducts the high inductor current, leading to high losses. To minimize this loss, a dead-time controller circuit is required to minimize the dead-time. The majority of existing predictive dead-time controllers are digital. These dead-time controllers have problems caused by their discrete output including dithering in steady state and reduced accuracy. Furthermore, existing dead-time controllers are limited to buck converter switching frequencies of 300kHz. Therefore, for operation at switching frequencies above 300kHz, dead-time controllers need to be faster and should operate without dithering. A one-step predictive dead-time control circuit for the synchronous buck converter is proposed in this thesis. It consists of a novel dead-time detection circuit and an analog optimization circuit. The detection circuit utilizes an integrated dead-time detection diode, which can be manufactured on the same die as the synchronous MOSFET in the buck converter. This results in an accurate detection signal indicating body diode conduction of the synchronous MOSFET. The dead-time optimization circuit is an analog circuit, which eliminates the shortcomings of digital control. The proposed circuit is verified using PSIM simulation software. In comparison to the adaptive dead-time control using a TPS2832 MOSFET gate driver with minimal of 15ns dead-time, the proposed dead-time control circuit reduces the body diode conduction time of the synchronous MOSFET to 2ns at 10A half load, 12V input, 1.2V output and 500kHz switching frequency. As a result, the efficiency of the buck converter is increased from 89.2% to 90.8%. |
Genre |
Thesis/Dissertation |
Type |
Text |
Language | eng |
Date Available | 2012-05-09 |
Provider | Vancouver : University of British Columbia Library |
Rights | Attribution-NonCommercial 3.0 Unported |
DOI | 10.14288/1.0072791 |
URI | http://hdl.handle.net/2429/42314 |
Degree |
Master of Applied Science - MASc |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Engineering, School of (Okanagan) |
Degree Grantor | University of British Columbia |
Graduation Date | 2012-11 |
Campus |
UBCO |
Scholarly Level | Graduate |
Rights URI | http://creativecommons.org/licenses/by-nc/3.0/ |
Aggregated Source Repository | DSpace |
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