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A low-phase-noise mm-wave oscillator and its application in a low-power polar transmitter Nouri, Neda 2011

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A LOW-PHASE-NOISE MM-WAVE OSCILLATOR AND ITS APPLICATION IN A LOW-POWER POLAR TRANSMITTER by Neda Nouri A thesis submitted in partial fulfillment of the requirements for the degree of  Doctor of Philosophy in The Faculty of Graduate Studies (Electrical and Computer Engineering)  The University of British Columbia (Vancouver) December 2011   Neda Nouri, 2011  Abstract  Over the past decade, there have been substantial activities as well as changes in the design of high-speed radio-frequency millimeter-wave (mm-wave) integrated transceivers and their building blocks such as oscillators, mixers, low-noise amplifiers, and power amplifiers. One of the popular mm-wave frequency bands is the 7 GHz unlicensed band available around 60 GHz, which is attractive for a variety of applications including wireless local area networks (WLANs), short-range high data-rate wireless personal area networks (WPANs), and vehicular radar. One of the critical challenges in the design of 60 GHz integrated transceivers is the local oscillator signal generation. One of the main objectives of this thesis is to present and experimentally validate techniques to achieve better phase noise for high-frequency oscillators, especially for high data rate applications.  This thesis studies the phase noise performance of a new rotary-wave coupled oscillator. The presented oscillator is a traveling-wave oscillator with a reduced phase distortion. This oscillator hybridizes the standing-wave oscillator and travelling-wave oscillator to take advantage of the benefits of each structure, i.e., low phase noise and low power consumption. The structure of this circuit is based on a travelling-wave oscillator tapped with four standingwave oscillators along a transmission line to accurately provide multiphase outputs. This oscillator produces eight phases, 45° apart from each other. A proof-of-concept prototype oscillator, fabricated in a 0.13-µm CMOS technology, provides a −17.5 dBm tone at 67 GHz and achieves a 5.2 GHz tuning range (8%) while it consumes 43.2 mW from a 1.2-V supply. The measured phase noise is −87 dBc/Hz (−102 dBc/Hz) at 1 MHz (10 MHz) offset. ii  As an application for this type of oscillator, a circular quadrature-amplitude modulation (QAM) small-signal polar transmitter is proposed and a proof-of-concept 16-level QAM modulator is designed and simulated. In this architecture, the proposed oscillator has been combined with an 8-to-1 multiplexer and four-level variable-gain amplifier to implement the QAM transmitter. Based on the post-layout simulation results, (which are in an excellent agreement with measured results for the oscillator block) the transmitter consumes 25% less power as compared to state-of-the-art 60-GHz transmitters with comparable performance.  iii  Preface  I, Neda Nouri, am the first author and principle contributor of all chapters. All chapters are coauthored with Dr. Shahriar Mirabbasi, who supervised the research and provided technical consultation and editing assistance on the manuscript. Chapter 3 is also co-authored with Dr. J. F. Buckwalter, who contributed in formulating the phase noise of the rotary-wave oscillator. Furthermore, appendix material is co-authored with Dr. M. R. Nezhad-ahmadi, who helped on the design review and Dr. S. Safavi Naeini who provided editing assistance. The following publications describe the work completed in this thesis. The second conference papers contain material that overlaps with the first journal paper.  Journal Papers Published N. Nouri, J. F. Buckwalter, “A Low-Power, Low-Phase-Noise 45-GHz Rotary Wave VoltageControlled Oscillator,” IEEE Transactions on Microwave Theory and Techniques, vol. 59, no. 2, pp. 383-392, February 2010. N. Nouri and S. Mirabbasi, “A 67-GHz Low-Phase-Noise Oscillator and Its Application in a Polar Transmitter,” Analog Integrated Circuits and Signal Processing, Springer, DOI: 10.1007/s10470-011-9747-x, pp. 1-10, August 2011. Conference Papers Published N. Nouri, M. Nezhad-Ahamdi, S. Mirabbasi, and S. Safavi-Naeini, “A Double-Balanced CMOS Mixer with On-Chip Balun for 60-GHz Receivers,” North East Workshop on Circuits and Systems (NEWCAS), Montreal, Canada, May 2010. N. Nouri, J. F. Buckwalter, “A 45GHz, 14mW Rotary Wave Voltage-Controlled Oscillator,” IEEE Silicon Monolithic Integrated Circuits in RF Systems, San Diego, USA, January 2009.  iv  Table of Contents  Abstract ………………………………..……………………………………..………….……..ii Preface……………………..……………………………………………………………...…...iv Table of Contents…………...………………………………………………………...…...……v List of Tables…………………...……………………………………………………...….…..vii List of Figures……………………………………………………………………….....….….viii Acknowledgments………………...………………………………………………....………xii CHAPTER 1 : Introduction ........................................................................................................... 1 1.1. Motivation........................................................................................................................ 1 1.2. Thesis Objective ............................................................................................................... 4 1.3. Thesis Organization ......................................................................................................... 7 CHAPTER 2 : Background ........................................................................................................... 9 2.1. Overview ........................................................................................................................... 9 2.2. Transmitter Architectures ................................................................................................ 9 2.2.1. Direct-Conversion Architecture .......................................................................... 10 2.2.2. Polar Transmitter Architecture ............................................................................ 11 2.2.3. Phase and Amplitude Modulations ..................................................................... 12 2.3. Complex Modulations ................................................................................................... 13 2.4. Polar Transmitter Implementation................................................................................ 17 2.5. Summary ......................................................................................................................... 19 CHAPTER 3 : Analysis and Design of Rotary-wave Oscillators .............................................. 20 3.1. Oscillator Fundamentals ................................................................................................ 20 3.2. Different Types of Oscillators ...................................................................................... 22 3.2.1. Ring Oscillators .................................................................................................... 22 3.2.2. LC Oscillators ....................................................................................................... 23 3.2.3. Transmission-Line ................................................................................................ 27 3.2.4. Distributed Oscillators ......................................................................................... 28 3.2.5. Millimeter-Wave Oscillators ............................................................................... 33 3.2.5.1. Standing-Wave Oscillators ....................................................................... 34 v  3.2.5.2. Rotary Traveling-Wave Oscillator ........................................................... 37 3.3. General Phase Noise Methods ...................................................................................... 40 3.3.1. Leeson’s Formula (Time-Invariant Phase Noise Model) ................................. 42 3.3.2. Rael’s Method [66] .............................................................................................. 43 3.4. The Proposed Design ..................................................................................................... 45 3.4.1. Standing-Wave Oscillator (SWO) ...................................................................... 48 3.4.2. Rotary -Wave Oscillator ...................................................................................... 55 3.4.3. Phase Noise in Rotary-Wave Oscillators ........................................................... 61 3.4.3.1. Phase Noise for the Loaded SWO............................................................ 61 3.4.3.2. Coupled Oscillator Dynamics .................................................................. 63 3.4.3.3. RWO Phase Noise Reduction and Simulation ........................................ 67 3.5. Circuit Implementation in 0.13-µm BiCMOS Technology ....................................... 70 3.5.1. RWO Measurement Results ....................................................................................... 74 CHAPTER 4 : Multiplexer and VGA design.............................................................................. 79 4.1. Overview ......................................................................................................................... 79 4.2. VGA Design ................................................................................................................... 82 4.3. Multiplexer ..................................................................................................................... 84 4.4. Summary ......................................................................................................................... 87 CHAPTER 5 : Measurement results ........................................................................................... 89 5.1. Overview ......................................................................................................................... 89 5.2. 16-QAM Transmitter Chip Implementation ................................................................ 94 5.3. Summary ......................................................................................................................... 98 CHAPTER 6 : Conclusions and Future Work .......................................................................... 100 6.1. Research Summary and Contributions ....................................................................... 100 6.2. Limitations and Future Work ...................................................................................... 103 References……………….. ........................................................................................................ 106  vi  List of Tables  Table 2-1: Allowed relative constellation error versus data rate……………………………… 15 Table 3-1: Performance comparison of microwave oscillators in silicon processes………….. 78 Table 5-1: Performance comparison of microwave oscillators in CMOS processes…………..99 Table 5-2: Transmitter post-layout simulation performance. ………………………………….99 Table A-1: Comparison with recent work on mm-wave mixers……………….....….………119  vii  List of Figures  Figure 1-1: The fT and fmax trends with scaling of CMOS technology according to the ITRS [15]. ................................................................................................................................................. 3 Figure 1-2: The proposed rotary-wave oscillator. ......................................................................... 5 Figure 1-3: A small-signal mixer-less polar transmitter architecture. .......................................... 6 Figure 2-1: Direct conversion architecture. ................................................................................. 10 Figure 2-2: Small signal polar architecture. ................................................................................. 12 Figure 2-3: Symbol constellations for different numbers of bits/symbol. .................................. 14 Figure 2-4: Error vector is the difference between the actual and ideal symbol vectors............ 15 Figure 2-5: The Kahn envelope elimination and restoration (EER) transmitter architecture [32]. ....................................................................................................................................................... 18 Fig. 3-1: (a) The basic feedback circuit, (b) One-port model. ..................................................... 21 Fig. 3-2: Ring oscillator. ............................................................................................................... 22 Fig. 3-3: Typical LC oscillator with cross-coupled pair providing negative resistance with added high pass filter to LC oscillator along with varactors. ...................................................... 24 Fig. 3-4: Method to enlarge the tuning range by using capacitor array. ..................................... 26 Fig. 3-5: (a) Colpitts oscillator, (b) its linear model [24]. ........................................................... 26 Fig. 3-6: Lumped transmission-line model with distributed transconductors. ........................... 27 Fig. 3-7: (a) Distributed amplifier, (b) negative resistance circuits: back-to-back inverters, (c) cross-coupled pair with current source. ....................................................................................... 29 Fig. 3-8: Distributed oscillator. .................................................................................................... 29 Fig. 3-9: A standing-wave formed from a right-travelling-wave (+z) and a left-travelling-wave (-z). ................................................................................................................................................ 33 Fig. 3-10: Interconnect with distributed transconductors. ........................................................... 34 Fig. 3-11: Moebius effect [49]. .................................................................................................... 37 Fig. 3-12: RTWO principle. ......................................................................................................... 37 Fig. 3-13: (a) Coupled LC oscillator (b) Coupled rotary wave oscillator. .................................. 39 Fig. 3-14: The phase noise per unit bandwidth. ........................................................................... 41 Fig. 3-15: A typical phase noise plot for a free running oscillator. ............................................. 42 viii  Fig. 3-16: Noise Sources from different parts of a cross-coupled transistor. ............................. 44 Fig. 3-17: Noise figure and fmax measurement for the NMOS device in 0.13-µm CMOS Technology [115].......................................................................................................................... 46 Fig. 3-18: Standing-wave oscillator and equivalent small-signal model. ................................... 48 Fig. 3-19: Capacitors related to cross-coupled transistors. .......................................................... 49 Fig. 3-20: QL vs. loading time constant for various QC (QTL = 15). ........................................... 51 Fig. 3-21: Spectre simulation of the phase noise at 1 MHz offset for a standing-wave oscillator as a function of bias current (W = 10µm). ................................................................................... 55 Fig. 3-22: Millimeter-wave RWO with four SWO stages distributed around a transmission line coupling network. ......................................................................................................................... 56 Fig. 3-23: Small-signal model of rotary-wave oscillators. .......................................................... 57 Fig. 3-24: Small-signal models of the standing-wave and rotary-wave oscillation modes. ....... 57 Fig. 3-25: Theoretical calculation of the ratio of rotary-wave to standing-wave currents for different transmission line quality factors, ( Q C = 5 )................................................................... 60 Fig. 3-26: Small signal model of noise injected into rotary-wave structure. .............................. 62 Fig. 3-27: Analytical calculation of the phase noise reduction from the introduction of additional coupling networks to the SWO resonator with respect to the SWO loading time constant (QTL = 15, QC = 5). .......................................................................................................... 63 Fig. 3-28: Determination of coupling strength from the combination of standing– and rotarywave modes. .................................................................................................................................. 63 Fig. 3-29: Analytical prediction of the coupling factor and phase as a function of the SWO loading time constant. ................................................................................................................... 65 Fig. 3-30: Harmonic balance simulation of the phase noise for an SWO, loaded SWO, and RWO (Ibias = 3.5mA, QTL = 20 )..................................................................................................... 69 Fig. 3-31: Simulation of phase noise reduction at 1 MHz offset for the RWO and SWO with no varactor loading versus bias current. ............................................................................................ 69 Figure 3-32: HFSS model for coupled transmission line. ........................................................... 70 Figure 3-33: Coupled transmission line quality factor for various width and spacing at 45 GHz. ....................................................................................................................................................... 71 Figure 3-34: (a) Technology layer models (b) SWO load layout imported from Cadence to HFSS. ............................................................................................................................................ 71 ix  Figure 3-35: Monte-Carlo simulation for transient output of the oscillator for all eight different phases. ........................................................................................................................................... 72 Figure 3-36: Chip microphotograph of the RWO with output multiplexer and buffer. ............. 73 Figure 3-37: Test chip setup. ........................................................................................................ 73 Figure 3-38: Measured output frequency spectrum at 45 GHz. .................................................. 75 Figure 3-39: Tuning range and amplitude variation of the measured RWO as compared to the simulation results. ......................................................................................................................... 76 Figure 3-40: Phase noise measurement for free-running oscillator at 45 GHz........................... 76 Figure 3-41: Measured phase noise at 1MHz for RWO current values and the FOM graph at 45 GHz. .............................................................................................................................................. 77 Figure 4-1: Different CMOS amplifier topologies (a) common source (b) common gate (c) common gate cascode amplifiers. ................................................................................................ 80 Figure 4-2: Four methods of controlling of gm (a) by changing the bias current (b) by adding the cascade transistor (c) a variable load and (d) a variable series feedback. ............................. 81 Figure 4-3: The current steering gain amplifier cell. ................................................................... 83 Figure 4-4: The 8-to-1 BiCMOS multiplexer. ............................................................................. 85 Figure 4-5: The 8-to-1 BiCMOS multiplexer layout. .................................................................. 86 Figure 4-6: Post-layout simulation for multiplexer gain representation. .................................... 87 Figure 4-7: 8-to-1 multiplexer including a 4-to-1 to select one of the four differential output of the oscillator, and a 2-to-1 multiplexer to select the sign. ........................................................... 88 Figure 5-1: 16-QAM polar transmitter......................................................................................... 89 Figure 5-2: Multi-phase rotary wave oscillator. .......................................................................... 90 Figure 5-3: Standing-wave oscillator (a) architecture, and (b) small signal model. ................... 91 Figure 5-4: Varactor realized in CMOS technology.................................................................... 93 Figure 5-5: (a) Varactor and (b) switched capacitor. ................................................................... 93 Figure 5-6: Chip die photograph. ................................................................................................. 95 Figure 5-7: Down-conversion mixer characteristic measurement. ............................................. 95 Figure 5-8: Post layout simulated outputs of RWO..................................................................... 96 Figure 5-9: Output spectrum of the polar transmitter. ................................................................. 96 Figure 5-10: Measurement tuning range for transmitter output. ................................................. 97 Figure 5-11: Output phase noise measurement at 67 GHz. ......................................................... 97 x  Figure 6-1: 16-QAM polar transmitter using the proposed RWO. ........................................... 102 Figure 6-2: PLL circuit for proposed oscillator. ........................................................................ 104 Figure A-1: 60 GHz double-balanced mixer with two passive baluns………...…….…...…..114 Figure A-2: 60 GHz passive balun…………………………………………………..……….115 Figure A-3: The measurement setup…………………………………………………..……..116 Figure A-4: Die micrograph of mixer chip including the PADs, buffer, and baluns…...….....116 Figure A-5: The measured output spectrum at IF which can be tuned by the employed varactor over the IF band...……………………………………………………………..…………..…117 Figure A-6: Measured conversion gain by sweeping LO and RF frequency by excluding the cable and prob losses……………………………………………………………...…...….…118  xi  Acknowledgments  First, I would like to express my gratitude to my advisor, Dr. Shahriar Mirabbasi, whose wise direction during my Ph.D. program was a great help in finishing this project. I am indebted to him for his tireless support and incredible patience in every step of my research. His immense knowledge and great personality are an inspiration for me.  I would also like to thank Dr. James F. Buckwalter for his never-ending help and guidance in developing and refining the ideas for my dissertation. His help was invaluable. I would always keep in mind he was my first high-frequency circuit design teacher.  My former manager, Dr. Ali Fotowat-Ahmadi, was a great help during the course of my work at Unistar-micro Technology Company; his guidance about both analog circuit design and my long-term career goals have been immeasurably appreciated.  My special thanks go to Wesley d’Haene my manager at Gennum Corporation for all his support and understanding during the last year of my program. I am lucky to work under his supervision.  I would also like to express my respect and appreciation to my dear colleagues at UBC for encouraging me to reach my goals. I also would thank Roozbeh Mehrabadi for the CAD support at SOC. My special thank will go to Dr. Roberto Rosales for his help. Whenever I needed to find my answer to any test-related issue, he was there to help with his great ideas.  xii  I thank CMC Microsystems Collaboratory for their fabrication and test support and facilities which made it possible to finish this project. Also, I am thankful for funding support from NSERC for my graduate studies.  Many special thanks go to my parents, Reza and Roghi, who have supported me throughout graduate school. I have achieved everything in my life because of their unconditional love and support. My brother, Nima, gets the special thank for showing me his strength and inspiring me to be strong and happy.  xiii  CHAPTER 1 : INTRODUCTION 1.1. Motivation Silicon-based radio-frequency (RF) technology has had a dramatic impact on variety of wireless applications, including personal mobile communication devices, military radar systems, radio astronomy, and space programs. Based on Shannon’s theorem, one way to increase the communication data rate is to use more bandwidth [1]. In 2001, the US Federal Communication Commission (FCC) allocated a bandwidth of 7 GHz at the frequency range of 57 to 64 GHz for wireless communication [1][2]. This is an unlicensed band, meaning that the users are not required to pay for or acquire any permission to operate in this frequency band. The major advantage of the 60 GHz band over the other unlicensed bands is its wider available bandwidth that enables high data-rate transmission. Also, the high absorption by oxygen at this frequency is another benefit for high security and interference-free operation, which makes this frequency band a suitable candidate for short range high-data-rate applications.  Furthermore, operation at 60 GHz provides more advantages in terms of integration as the wavelength of the signals within this band is around 2.5 mm in silicon. This is especially beneficial for integrating the antenna on the chip. On-chip antennas offer several significant benefits, such as obviating the use of expensive and lossy packaging, transmission of higher power for a given voltage swing, simplifying the coupling to the antenna, and the possibility of using multiple antennas in a beam-forming array [3][4].  1  This mm-wave band has become so popular that the IEEE 802.15.3c standard group is proposing to use it for wireless personal area networks (WPANs). Such WPAN systems operate at high data-rates (>2 Gb/s) in ranges shorter than 10 m [5]. The applications mentioned in this standard cover uncompressed video streaming, office desktop data transfer and kiosk file downloading.  Since the introduction of this unlicensed band, many works have been done on the integration of the transceivers for this frequency. Early designs were implemented in technologies such as SiGe and GaAs, where faster transistors were available [6]. However, due to the lower cost and higher level of integration of CMOS designs and improved speed of operation of CMOS transistors brought the interest of many groups, both in industry and academia, to be attracted to CMOS-based designs for this frequency band [1][7]–[13]. The high level of integration makes CMOS technology a compelling choice. However, implementing mm-wave in digital processes requires extra fabrication steps [1]. To accommodate the mm-wave designs, special thicker top metal layers have been provided in CMOS technology in order to enhance the opportunities for high frequency circuit design. These layers help to improve the design of the inductors and transmission lines with higher quality factor for RF and mm-wave frequencies.  Through continued scaling of the CMOS process, unity gain frequency (fT) and unity power gain frequency (fmax) of CMOS transistors are pushed beyond 100 GHz, and thus implementation of all-CMOS solutions at 60 GHz have become feasible. It should be noted that a major driving force behind CMOS technology scaling (also known as Moore’s Law) has been increasing the level of integration and cost reduction. As can be seen from the graph in  2  Figure 1-1, the technologies with feature size of 130nm or finer are suited for implementation of 60-GHz circuits.  Figure 1-1: The fT and fmax trends with scaling of CMOS technology according to the ITRS [14].  At mm-wave frequencies such as 60 GHz, the size of interconnect wires become comparable to the wavelength of signals (in silicon) and it will be very important to consider the effect of wire impedance in the design. In particular, the line impedance becomes comparable with the component impedances used in the circuit. Therefore, the choice of architecture, circuit design, and the layout can immensely affect the performance of the circuit.  One way to increase the data rate in a communication link is to use more complex modulation schemes with high-order constellations; however, such schemes are less tolerant to noise. In particular the local oscillators, the key block of many designs, are required to have a tighter phase noise performance.  For many short-range applications such as WPAN and wireless universal serial bus (USB), low-power transceivers capable of delivering reasonably high data rates (over 100 Mb/s) are required [6] [15]-[17]. In such systems, phase-locked loop (PLL)-based solutions are often 3  favored for low-power applications, because of their hardware efficiency. For high-data-rate applications (e.g., Worldwide Interoperability for Microwave Access (WiMAX), Long Term Evolution (LTE), and Enhanced Data Rates for GSM (Global System for Mobile Communications) Evolution (GSMEDGE), spectrally efficient modulation schemes such as quadrature amplitude modulation (QAM) are widely used [18]. In QAM schemes data symbols form a constellation that is distributed in a complex plane. The commonly used QAM schemes can be classified into two classes: square QAM [19] and circular (or star) QAM [19]. Circular QAM has the property that the peak-to-average power ratio of the transmitted signal is less than that of the square QAM [20]. This means that circular (star) QAM can operate at higher transmit power in a practical radio transmitter. In general, the low phase noise oscillator is a key in the design of high-data-rate QAM systems to minimize the bit error rate of the system.  In order to further reduce the baud-rate and to increase the spectral efficiency, more bits can be encoded in one symbol using the multi-level quadrature amplitude modulation (QAM) format [21][22]. For example, in 16 QAM signaling 4 bits are encoded in each symbol and thus the spectral efficiency doubles as compared to Quadrature Phase Shift Keying (QPSK or 4QAM). This comes, however, at the cost of reduced tolerance to signal-to-noise ratio (SNR) and phase noise. Therefore, employing a low-phase noise oscillator is important.  1.2. Thesis Objective Having briefly described the motivation for this research, a concise thesis statement is as follows: the aim of this research is to develop a new architecture for designing mm-wave  4  mixer-less transmitters in CMOS technology with an emphasis on the design and experimental validation of a low-phase-noise, low-power, multi-phase rotary-wave oscillator structure.  In particular, the following contributions are made:  1) Design of a multi-phase low-phase-noise rotary-wave oscillator that uses a hybridized structure based on a travelling-wave oscillator (TWO) and a standing-wave oscillator (SWO) to provide low phase noise outputs (shown in Figure 1-2). (Chapter 3)  Figure 1-2: The proposed rotary-wave oscillator.  The structure is suitable for generating the multi phases required in high data rate applications (for example, in the 16-QAM structure discussed in the thesis, eight different phases, 45° apart, are used). Once a wave becomes established, it takes a small amount of energy to sustain it. This is because unlike a ring oscillator, the energy that goes into charging and discharging MOS gate capacitances is re-circulated in the closed electromagnetic paths. This offers potential power savings as losses are not related to CV2f but rather to I2R dissipation in the conductors where R can be reduced, e.g., by adoption of 5  copper metallization. The travelling-wave oscillator is tapped with standing-wave oscillators (which conventionally use back-to-back inverters). Also, this architecture is very promising for low-phase-noise systems, as any noise perturbation will be averaged out along the transmission-line ring and will result in a lower phase noise.  2) Development of small-signal polar transmitter architecture (shown in Figure 1-3) for high-data-rate wireless communications: The mixer-less structure has been chosen to avoid/minimize the problems associated with the mixer feed-through and inphase/quadrature (I/Q) mismatch. As a proof of concept a 16-QAM transmitter is designed and fabricated. The rotary-wave oscillator is employed to provide both low power and low phase noise outputs. An 8-to-1 multiplexer along with two variable gain amplifiers (VGAs) is used to provide four different levels of gain to achieve the 16-QAM constellation (Chapter 4).  Figure 1-3: A small-signal mixer-less polar transmitter architecture.  A combination of a multiplexer and a current-steering variable-gain amplifier (VGA) is used to save area and provides the levels of amplification required for 16-QAM constellations. Typically, the distance between the rings is chosen to reduce the error vector magnitude (EVM) to within an acceptable range for the standard used. This multiplexer uses less  6  transistors as compared to the conventional one [4], which in turn means less noise will be added to the output.  To the best of the author’s knowledge, the approach of combining standing- and rotary- wave oscillators to make multiple phases for making QAM transmitters has not been used before although there is still considerable room for improvement as will be discussed in the future work section. Also the phase noise of the conventional rotary-wave oscillator has been analyzed, but the phase noise of the proposed hybrid RWO/SWO has not been previously analyzed.  1.3. Thesis Organization Chapter 2 overviews different polar transmitter topologies and provides a literature review of recent high-frequency transmitter designs. In particular, a mixer-less architecture is considered. In addition, a brief overview of the shortcomings and strengths of these designs is provided.  Chapter 3 provides a detailed explanation of different types of oscillators and phase-noise calculation methods and then presents the structure of the proposed rotary-wave oscillator. Also, a comprehensive analysis of the phase noise of this type of oscillator is provided.  In Chapter 4, the design of the combined multiplexer and VGA is described in detail. First, different structures of variable-gain amplifiers are compared, and then the design of both the multiplexer and VGA is discussed, which are building blocks of any transmitter.  Chapter 5 presents the measurement results of two fabricated chips. The first chip has been fabricated in a 0.13-µm BiCMOS technology and includes the oscillator and the 8-to-1 7  multiplexer to test the oscillator. The second chip is fabricated in a 0.13-µm CMOS technology and includes the main building blocks of the transmitter. Chapter 6 presents concluding remarks and directions for future work.  8  CHAPTER 2 : BACKGROUND 2.1. Overview This chapter provides the background and an overview of different transmitter architectures and a literature review of previously designed high-data-rate transmitters. Section 2.2 reviews the basic concept of the transmitter design. Section 2.3 discusses the modulation methods. In Section 2.4, different structures of polar transmitters are reviewed.  2.2. Transmitter Architectures Wireless transmitter architectures can be broadly divided into two groups: mixer-based and phased-locked loop (PLL)-based transmitters. PLL-based transmitters which are typically mixer-less are often favored for low-power applications and multi-mode operations. Mixerbased structures can be further categorized into direct-conversion and two-step conversion transmitters [23]. If the transmitted carrier frequency is equal to the local oscillator frequency, the transmitter architecture is called direct-conversion or homodyne architecture. On the other hand, if the baseband signal is up-converted in two steps, the transmitter architecture is called a two-step or heterodyne architecture. In direct conversion, the signal is directly transferred to the desired frequency. This method seemingly needs less complex circuitry and is more suitable for integration. However, it has two main problems, disturbance of transmit local oscillator, and local oscillator (LO) pulling [23]. The two-step transmitter is the approach to alleviate the LO pulling issue, by making the PA output frequency far from the frequency of the VCOs.  9  2.2.1. Direct-Conversion Architecture Figure 2-1 shows the architecture of a direct-conversion transmitter. In this type of transmitter, in-phase data, Iin, and quadrature data, Qin, are up-converted using orthogonal (quadrature) LO signals. The quadrature signals are then added and amplified. The RF signal (the input of the VGA) can be described using its baseband components, I(t) and Q(t), as follows:  V (t ) = I (t ) cos( ω o t ) + Q (t ) sin( ω o t )  (2-1)  where ωo is the RF carrier frequency.  Figure 2-1: Direct conversion architecture.  As mentioned before, the two major design challenges in a direct conversion transmitter (Figure 2-1) are disturbance of transmit local oscillator by the power amplifier and LO pulling. Because of the high power spectrum centered around the LO signal, its noisy output can corrupt the oscillator spectrum. The LO pulling phenomena can be alleviated by moving the PA spectrum sufficiently far from the LO spectrum.  10  The other issue that can be caused by the mixer is the LO feedthrough. The LO signal can directly feed to the output IF signal. The leakage can be minimized with careful design and layout of the mixers and quadrature local oscillator. Also, some calibration can be done on LO leakage through adding the proper amount of DC offset to either of I or Q signals. This technique is discussed by Cavers et al. [24] and is now commonly used in Cartesian transmitter design. Due to the above-mentioned problems, the design of direct-conversion transmitters is challenging.  2.2.2. Polar Transmitter Architecture In contrast with the Cartesian-based architectures such as the direct conversion structure, polar modulation techniques use magnitude and phase. Thus, they make it possible to process the two components (phase and magnitude) differently and more efficiently. As shown in Figure 2-2, the RF signal can be decomposed into polar form using the amplitude and phase of the RF carrier. With a polar representation, the modulated RF signal at the VGA input can be written as:  V ( t ) = a ( t ) cos (ωo t ) + ϕ ( t )  ,  (2-2)  where a(t) and ϕ(t) are the amplitude and phase of the carrier, respectively [25]. The phase component, i.e., phase modulation (PM) is processed using the PLL while the amplitude component, i.e., amplitude modulation (AM) is processed by the variable-gain amplifier (VGA). Efficient amplifiers can be used to amplify the signal at the PLL output, as it has a constant envelope (as opposed to variable envelope of the RF signal at the input of the VGA in Figure 2-1). This will reduce the power consumption of the transmitter. 11  Mapping the complex signal into its phase and amplitude components is a nonlinear and complicated process. Furthermore, it is not uncommon for the phase and amplitude signals to abruptly change directions, which means there is a need to widen the spectrum of the modulation. Polar transmitters can be categorized as: (1) small-signal polar transmitter: as shown in Figure 2-2(a), the AM and PM signals combine and are then transferred to the PA; (2) direct polar transmitter: it works by combining the AM and PM modulated signals at the high-power PA (shown in Figure 2-2(b)).  Figure 2-2: Small signal polar architecture.  2.2.3. Phase and Amplitude Modulations A detailed view of a PLL supporting phase modulation is shown in Figure 2-2(a). The feedback is applied to minimize the phase difference between the reference and the VCO output signal. The required phase is selected in the phase-select block and the output of the PLL is amplified by the variable-gain amplifier to provide the required amplitude for the 12  selected phase. The phase modulation is implemented by the PLL. In order to operate properly, the phase modulation signal must first be differentiated, because the control input to the VCO adjusts the output frequency, not the phase. This can be done by measuring the difference between consecutive PM samples.  An ideal polar modulator combines the amplitude and phase components to construct the desired complex transmit signal, which necessitates proper alignment of these two components. Any timing offset causes excess EVM. EVM will be described in more detail in the next subsection. In practice, the required accuracy depends on the data rate of the baseband transmit signal. Any group delay caused by filtering should be compensated for or removed.  2.3. Complex Modulations Digital modulation schemes encode data in symbols which can be considered as vectors with unique amplitude and phase. Each symbol can represent multiple bits of digital information, where more complex constellations represent more bits per symbol. In Figure 2-3(a), binary phase shift keying (BPSK) involves changing the phase of the carrier between two points that are 180° out of phase. In BPSK, only 1 bit is represented for each symbol. To improve the spectral efficiency, it is better to send multiple bits (for example, a pair or four bits) instead of one bit and represent them with different levels. For sending two bits, bm and bm+1, with one symbol, they can be represented as:  x (t ) = bm a c cos ω c t − bm +1 a c sin ω c t  (2-3)  Higher order modulation formats have more points in the symbol constellation. Figure 2-3(b) shows the constellation for a 4-QAM signal. This allows two bits to be encoded on each 13  symbol, increasing the data rate by a factor of 2 as compared to BPSK. Figure 2-3(c) shows a 16-QAM constellation which uses 4 bits per symbol. Higher order QAM schemes allow higher data transmission rates for a given symbol rate. This results in higher spectral efficiency, or higher data-rate for a given amount of available spectrum [26].  Figure 2-3: Symbol constellations for different numbers of bits/symbol.  However, given a fixed transmit power, by increasing the number of levels of amplitude and phase modulation, the distance between symbols and thus the symbol detection becomes more sensitive to noise. Constant envelope modulation schemes generally have to use lower symbol rates to keep the output spectrum within limits [26][27].  In practical systems, the transmitted symbol vectors suffer from noise and distortion. This noise and distortion causes an error between the ideal and actual symbol location which can be shown by an error vector. A common figure of merit for reliability of the symbol constellation is the error-vector magnitude (Figure 2-4). The EVM is calculated as a normalized average power of the error vector between the ideal and actual transmitted signal constellation points. Mathematically, EVM is typically defined as the root-mean-square quantity across a number of symbol measurements: 14  EV M =  1 N  N  ∑ (V ) 2  e  (2-4)  j =1  .V m  where Ve is the magnitude of the error vector for each symbol, Vm is the magnitude of the desired symbol vector, and N is the number of measurements.  The requirements for the maximum allowable EVM level used by the communication system. Specific requirements for the EVM of different MCSs considered in this work and the EVM measurement procedure are taken in accordance with the IEEE 802.11a standard [28]. The EVM requirements for the analyzed MCSs are listed in Table 2-1. The peak value for EVM may also be specified in the standard. EVM requirements vary widely depending on the standard [27].  Table 2-1: Allowed relative constellation error versus data rate.  Relative constellation error (dB)  Modulation  -5 , -8  BPSK  -10 , -13  QPSK  -16 , -19  16-QAM  Figure 2-4: Error vector is the difference between the actual and ideal symbol vectors.  15  If the EVM is measured over large values of N [29], then:  EVM =  No = Eo  1 SNR  (2-5)  where Eo/No and SNR are representing the energy per bit to noise power spectral density ratio, and normalized signal-to-noise ratio, respectively. These parameters offer a good representation of the polar transmitter performance.  Noise leads to random distribution of the error vectors, while distortion may cause patterns in the error vector that are correlated with the symbol amplitude and phase. In transmitters it is common to specify AM-AM (amplitude-driven amplitude) distortion and AM-PM (amplitudedriven phase) distortion [30]. AM-AM distortion is caused by variation in the transmitter gain as the signal amplitude changes. A common form of AM-AM distortion is quantified through the -1 dB compression point in RF amplifiers [27][30]. Compression happens due to the nonlinearity of the system, when the output amplitude is saturated and is not linearly proportional to the input amplitude.  In contrast to Cartesian transmitters where the data is encoded in Cartesian I and Q signal components, in polar transmitters the data is encoded in the amplitude and phase components of the signal. The polar representation can be calculated from the Cartesian representation as:  a (t ) = I (t ) + Q (t ) 2  16  2  (2-6)   Q (t )    I (t )   ϕ ( t ) = arctan   (2-7)  where a(t) and ϕ(t) are the time-domain amplitude and phase of the polar signal. A major difference between the polar and Cartesian representations is that the polar basis vectors, amplitude and phase, have different spectral properties as compared to the I and Q basis vectors. This can be seen from (2-6) and (2-7) as a and ϕ are derived from I and Q through nonlinear operations. Non-linearities in (2-6) and (2-7) cause the polar basis vectors to have a wider bandwidth as compared to the Cartesian I and Q components. To design the system with low EVM and high spectral reliability, the wider-band nature of the amplitude and phase paths should be considered at both the architecture and circuit level design steps.  2.4. Polar Transmitter Implementation There are several techniques that have been used to design a polar transmitter. The Kahn envelope elimination and restoration (EER) technique is an early example of polar modulation where the amplitude and phase are extracted directly from the modulated RF signal [31].  In the Kahn technique, shown in Figure 2-5, a limiter keeps the zero crossings of the RF signal intact (preserving the phase information), while converting the signal (which is applied to the input of the PA), to a constant envelope signal. The amplitude information is extracted with an envelope detector and then restored in the envelope of the transmitted signal, leading to the EER implementation. A more recent example of this technique is presented by Raab et al. [32]. The Kahn technique continues to be the basis of many of the modern polar transmitter structures [31][33]-[37].  17  Figure 2-5: The Kahn envelope elimination and restoration (EER) transmitter architecture [31].  There are many ways to implement the phase path in a polar system. As shown in Figure 2-5, the goal is to convert an RF signal representation of the baseband phase signal to a phase-modulated RF signal. The work of Staszewski in 2005 [38], opens the range of possibilities for such techniques. They show another version of the polar architecture highlighting the wide variety of such systems close to Figure 2-5. The PA is used as a variable-gain amplifier (VGA). In a general sense, any signal which modulates the amplitude of the carrier can effectively be used in a polar system.  Polar transmitters provide the potential for efficient implementation of multimode wireless transmitters. They provide a single architecture for different systems that eliminate RF mixers and their associated spurious and leakage problems. Also, due to amplifying a constant envelope signal, as compared to their Cartesian counterparts, they have better efficiency, leading to higher output power capability. However, their wider spectra and tighter accuracy requirements place greater demands on phase and amplitude modulation. The challenges in the design of polar transmitters can be summarized as follows:  (1) These types of transmitter usually require wider band signal components (i.e., polar amplitude and phase signals). A Cartesian representation with a simple band-limited 18  spectrum may have wider band spectral content with an equivalent polar representation. The wideband nature of the polar representation requires higher bandwidth circuit design for the amplitude and phase modulators.  (2) Another major issue for polar systems is distortion. In Cartesian transmitters, the PA operates with a fixed supply voltage and is only subject to the normal input-output nonlinear characteristics.  At low supply voltages, additional AM-PM distortion may be caused by the feed-through of the PA input signal to the output, which is problematic if the phase-path signal is a constant envelope [31]. The phase signal can also leak directly to the output of the PA or indirectly through the parasitic capacitors [25].  2.5. Summary Two major transmitter architectures and their advantages and disadvantages have been explained. The polar transmitter requires an accurate phase generation, which reduces the phase distortion and increases the accuracy of the system design. Accurate phase generation at mm-wave frequencies is challenging and one objective of this thesis is to design a class of mm-wave oscillators that generate multiple phases and a have low phase noise (Figure 1-3). In Chapter 3, the design and analysis of the multi-phase oscillators is explained in detail.  19  CHAPTER 3 : ANALYSIS AND DESIGN OF ROTARYWAVE OSCILLATORS Even though oscillators have been extensively used over the past decades, high-performance oscillators operating in the mm-wave range continue to pose various design challenges in today’s advanced technologies [1]. In this chapter, the discussion begins with oscillator fundamentals, and then continues by comparing different types of oscillators, and then the proposed new architecture for the rotary-wave oscillator is introduced. Also a comprehensive analysis of the phase noise of the proposed oscillator is presented.  3.1. Oscillator Fundamentals The local oscillator (LO) circuit is responsible for creating the internal oscillatory signals required in the transceiver which have a critical impact on the performance of the entire system. In most wireless applications, narrow-band channels reside close to each other, and even a slight non-linearity in the LO could cause significant distortion from adjacent channels [23] and enforce stringent requirement on the phase noise (PN) of the oscillators [39]. In addition to phase noise, there are application-specific requirements for the oscillator such as the oscillation frequency, output power, and frequency tuning range (e.g., 7 GHz for 60 GHz applications) that must be met.  Voltage-controlled oscillators (VCOs) are one of the main building blocks of LOs. In addition to the design issues mentioned above, capacitive loading on the oscillator output, which degrades the tuning range and phase noise, and passive component (e.g., inductors) losses become predominantly important in the microwave regime. 20  Fig. 3-1: (a) The basic feedback circuit, (b) One-port model.  Oscillation behavior can be explained with the well-known feedback model shown in Fig. 3-1(a), where an amplifier a(jω) is placed in a feedback loop with a feedback gain of β(jω). The overall transfer function is given by  H ( jω ) =  a ( jω ) Vout ( jω ) = Vin 1 − β ( jω ) a ( jω )  (3-1)  To make the structure oscillate at a certain frequency, ωo, the Barkhausen criterion should be satisfied:  a ( jω ) β ( jω ) = 1  (3-2)  That is, at the oscillation frequency, ωo, the magnitude of the loop gain is unity and the total phase shift around the loop is 0° (or a multiple of 360°).  Typically, oscillation initiates from noise or an input waveform with sufficient spectral content. In practice, the loop gain has to be greater than one in the beginning to start up the oscillation. Once the oscillation is started typically the loop gain drops to one. For a microwave circuit, a closed loop gain function (Eq.(3-1)), can be developed as follows. Fig. 21  3-1(b) shows the one-port model a generic oscillator; a simple tank with the impedance of ZL, and the active block which is responsible to generate negative impedance with the total impedance of Zin to cancel out the loss of the tank.  The resonator alone cannot sustain oscillation since part of the energy stored in the tank at every cycle is dissipated in the parasitic resistor of the tank. By using the active device, the energy loss is replenished in every cycle so that stable oscillation occurs.  3.2. Different Types of Oscillators There are different classifications for oscillators. One common classification is to categorize oscillators into three types: ring oscillators, LC oscillators, and distributed oscillators.  3.2.1. Ring Oscillators This type of oscillator, composed of several gain stages in a single feedback loop, is usually referred to as “resonator-less” oscillator. In most digital and analog applications, ring oscillators are used to generate the internal clock of the system. However, ring oscillators suffer from a relatively large phase noise which prohibits their use in applications with stringent phase noise requirement [40][41], especially, in wireless applications where many neighboring channels reside just a few kHz apart from each other. The advantage of this type of oscillator is its simplicity and wide tuning range. As shown in Fig. 3-2, a ring of inverters make a ring oscillator.  Fig. 3-2: Ring oscillator.  22  Total phase shift around the loop at the frequency of oscillation should be equal to 360° (or integer multiples of 360°). Assume N inverter stages each with phase shift of ∆ϕ are connected to each other. Then ∆ϕ can be calculated using:  180° 2 N ∆ϕ = 360 ⇒ ∆ϕ = N °  (3-3)  Ring oscillators are area-efficient structures that provide a wide tuning range for multi-phase outputs; however, they have a poor phase noise which is one of the major parameters to choose an oscillator structure especially for high frequencies.  3.2.2. LC Oscillators LC-tank oscillators are typically used in high-speed low-phase-noise systems. A simple yet symmetric configuration facilitates high-speed and differential design with a large output swing, reasonable tuning range, and low power consumption. It also allows for low-supply operation. One of the commonly used LC oscillator structures is the cross-coupled oscillator. Depending on the inductor quality factor (Q), cross-coupled oscillators can achieve low phase.  A typical realization of a cross-coupled oscillator is shown in Fig. 3-3, where the pair M1-M2 provides negative resistance -2/gm1,2 (differentially) to compensate for the inductor loss Rp, where gm is the transconductance of each transistor. At resonance, these two resistances cancel each other and the oscillation frequency is given by  ωo =  1 L PC P  23  (3-4)  where Lp and Cp denote the loading inductor and parasitic capacitance at output nodes, respectively, and D is (MOS) varactor that makes the oscillator tunable, i.e., a voltagecontrolled oscillator (VCO). Barkhausen criteria imply that if RP g m1,2 ≥ 1 then the circuit oscillates, while in a practical design a higher than unity value (≈3) is used to ensure oscillation over process, supply voltage, and temperature (PVT) variations.  Fig. 3-3: Typical LC oscillator with cross-coupled pair providing negative resistance with added high pass filter to LC oscillator along with varactors.  It is instructive to derive an alternative expression for oscillation frequency, ωo, with simplified conditions to examine what factors limit the operation frequency. The relation between Rp and ωo in stable oscillation can be represented as  R P = Qω o L =  1 g m1,2  24  (3-5)  ωo =  1 L ( CP + Cgs )  (3-6)  where Q represents the quality factor of the tank, and Cgs the average gate-source capacitance contributed by M1,2 (For simplicity, the varactor is ignored).  In practice, high-speed oscillation presents many challenges: (1) the on-chip inductors usually have a self-resonance frequency of a few tens of GHz; (2) due to the physical limitations for on-chip inductors, they cannot provide a high Q; (3) the varactors present a low quality factor which can degrade the overall Q of the tank; (4) in high frequencies, Cp is comparable with other parasitics. One solution for improving the Q of the tank, i.e., decreasing the tank loss at high frequencies, is to use transmission lines instead of inductors as the Q of transmission lines is higher than that of inductors.  An approach to reduce the noise contribution of the tail current source is illustrated in Fig. 3-3. A large bypass capacitor Cf absorbs the noise of the current source. With the Lf - Cpar network resonating at twice the output frequency, at the oscillation frequency the common-source node P still experiences high impedance to ground. The differential operation improves the common-mode rejection.  To extend the tuning range of such LC oscillators a popular techniques is to use a capacitor array (preferably binary-weighted for better efficiency) to coarsely tune the VCO frequency (Fig. 3-4) [42]. As shown in Fig. 3-4, by using 2N control switches, a wide range of frequencies can be covered. It should be noted that the poor quality factor of the varactors still degrades the phase noise of the oscillator. 25  Fig. 3-4: Method to enlarge the tuning range by using capacitor array.  Another important VCO topology that has been widely used in high-speed systems is Colpitts oscillator. First proposed in 1920’s [43], this type of oscillator could operate with only one transistor. Because of the better performance of the differential circuits at high-speed operation, a symmetric Colpitts oscillator with differential output is usually used [23]. A Colpitts oscillator uses a capacitive feedback from drain to source (Fig. 3-5(a)) and its oscillation criteria is RP g m ≥ 4 , where gm is the transconductance of NMOS transistor and Rp is the equivalent parallel resistance seen at the drain of the transistor including the nonidealities of inductors and capacitors.  Fig. 3-5: (a) Colpitts oscillator, (b) its linear model [23].  26  Looking from a different perspective, the Colpitts circuit can be considered as a negative resistance in parallel with an LC tank, Fig. 3-5(b) (if the bottom plate of C2 is considered connected to the gate of the NMOS device (AC ground)). In order to oscillate, the signal in the feedback path through the C1-L-C2 network must satisfy Barkhausen criterion. By applying this criterion on the oscillator open loop, the oscillation frequency can be calculated as    ωo =  1   LC1C2   C1 + C2   1+  1 1 1 1  ≈  +  2 Q L  C1 C2   (3-7)  Here, Q is the quality factor of the inductor. In Fig. 3-5(b), Rp = ωoLQ. Due to using only one transistor in this architecture, it exhibits good phase noise performance. Comparing Coplitts and cross-coupled oscillators, cross-coupled oscillators can provide a lower power consumption and wider tuning range (as Colpitts oscillators have a fixed capacitor as part of their structure).  3.2.3. Transmission-Line One of main components of the distributed oscillators is transmission line. A brief introduction of its basic parameters is presented as follow.  Fig. 3-6: Lumped transmission-line model with distributed transconductors.  27  The equivalent lumped model for a transmission line is shown in Fig. 3-6, where R, Lo, Co, and G are the lumped transmission-line parameters per unit length. The effective interconnect propagation constant, γ can be calculated by  γ=  ( R + j ω Lo )(G + j ωC o ) = α + j β  (3-8)  The propagation constant consists of the loss constant, α, and phase constant, β, as shown in (3-8). Assuming low-loss for the values of the transmission-line parameters, the equations for  α and β can be simplified to  α≈  GZ o R C o G Lo R + ≈ + 2 Lo 2 Co 2Z o 2  (3-9)  β ≈ ω Lo C o  (3-10)  where Zo is the characteristic impedance of interconnect and can be approximated as  Lo C o .  These equations provide some intuition about how α and β change as a function of transmission-line parameters. Any other losses added to the transmission line can be modeled as a series resistance or a parallel conductance.  3.2.4. Distributed Oscillators A distributed amplifier (Fig. 3-7(a)) can be placed in a feedback loop to form an oscillator (Fig. 3-8) [44]. The input signal propagates down the “gate” line and is amplified by the distributed devices. The outputs of the devices add coherently on the “drain” line. Because the capacitance of the active devices is absorbed into transmission lines, distributed amplifiers are 28  capable of providing a gain that exceeds the transmission line loss [41]. They are also wellsuited for integration in standard CMOS processes [45].  This approach shows some promise for overcoming interconnect losses at microwave frequencies. Instead of using a single transistor to provide negative resistance, it is preferable to distribute the negative resistance along the input and output lines to reduce gain limitations imposed by the transmission line (t-line) loss. Back-to-back inverters (Fig. 3-7 (b)) have been used [46] to provide the negative resistance. A better approach is to use cross-coupled NMOS transistors (Fig. 3-7 (c)) instead of back-to-back inverters that work up to very high frequencies. This approach allows tuning of the negative resistance through controlling the current source. As shown in Fig. 3-8, the output of a distributed amplifier is returned back to the input, yielding to wave circulation along the loop (a distributed oscillator).  Fig. 3-7: (a) Distributed amplifier, (b) negative resistance circuits: back-to-back inverters, (c) crosscoupled pair with current source.  Fig. 3-8: Distributed oscillator.  29  To insure the oscillation, the total delay of the inverting amplifier must translate to a phase shift of 180° at the frequency of interest. As mentioned before, to assure the oscillation, a minimum loop gain of unity is required, and the oscillation frequency can be calculated [47]. The transistor capacitance lowers the characteristic impedance and not translating to a time constant. Each common-source stage along with an additional length of t-lines increases the gain by gmZL/2, by assuming that the transmission line is loss-less. Assuming the n commonsource stages uniformly distributed over a t-line with a length of l. The characteristic impedance of the amplifier will be  Z oL =  Lo nC Co + gs l  (3-11)  The total voltage gain is equal to  AV =  ng m Z oL ng m = 2 2  Lo nC Co + gs l  (3-12)  As fT can be calculated from:  2π fT =  gm C gs  (3-13)  By replacing (3-13) in (3-12):  30  AV =  n 2π fT C gs 2  Lo nC Co + gs l  By considering that Co is negligible as compared to  (3-14)  nC gs l  , Av can be summarized as follow:  l AV = 2π fT v  (3-15)  Therefore, the Av can be written as:  AV =  π fT  (3-16)  2 fo  By assuming that the Av should be equal to one for oscillation  Av = 1  fo =  π 2  fT  (3-17)  Oscillation is therefore obtained at any point along the transmission line. Here, the transmission line loss is overcome by the gain generated along the line. It is more specific to assume that the two propagation lines in Fig. 3-8 are identical in the characteristic impedances, group velocities, and physical length. The oscillation period under such circumstances is twice the propagation time along the length l:  31  fo =  1 nC   2l Lo  Co + gs  l    (3-18)  It can be shown that the oscillation frequency is more than the device fT [47]. While looking attractive, the distributed oscillators suffer from a number of drawbacks: (1) the group velocities along the two lines may depart from each other due to the difference between the gate and drain capacitances; (2) the circuit needs larger area, and (3) the frequency tuning could be difficult. The third point becomes clear if adding any varactor to the lines can cause significant degradation on the oscillation frequency and the effective quality factor Q. Varying the bias voltage of the transistors may change the intrinsic parasitics (and therefore the oscillation frequency), but the imbalanced swing and the mismatch between the lines could make things worse.  It has been shown that the phase of an electrical standing-wave – one of the important aspect for clock distribution − is determined almost entirely by the transmission line loss and termination [48]. A standing-wave is a superposition of two traveling waves of equal magnitude and frequency that are propagating in opposite directions. Fig. 3-9 shows how a standing wave is generated and expressed by  θ θ   V ( z , t ) = A cos ( ωt − β z ) + A cos ( ωt + β z + θ ) = 2 A cos  β z +  cos  ωt +  2 2    (3-19)  where θ, A, and z are the phase relationship between the two traveling waves, the signal amplitude, and the distance of the wave travelled with reference to the wave origin, respectively. Eq. (3-19) shows that the magnitude of a standing-wave varies with position but 32  the phase is constant. Standing-waves contain magnitude values whose positions are determined by θ. The polarity of the wave changes at zero (on the other word, it is viewed as a discrete 180° phase change). Thus, a standing-wave can be generated by reflecting the incident wave back to the source and by superimposing the two incident and reflected waves.  Fig. 3-9: A standing-wave formed from a right-travelling-wave (+z) and a left-travelling-wave (-z).  3.2.5. Millimeter-Wave Oscillators Microwave oscillators with transmission-line-based tanks fall into two categories: standingwave oscillators (SWO) and rotary-wave oscillators (RWOs). Trade-offs between implementing each type of such oscillators depends on the design requirements. The SWO tends to minimize phase noise by appropriately tailoring the tank impedance for low loss based on the maximum current and voltage along the tank. On the other hand, the RWOs have been suggested to distribute negative resistance around a differential transmission line ring and provide multiple low phase-noise phases. In this research, a hyberdized version of RWO and SWO has been used.  33  3.2.5.1. Standing-Wave Oscillators Based on the discussion of standing-waves, the main limiting factor for generating ideal standing-waves is the lossy interconnects which can be compensated by using distributed gain circuits across the transmission line. The circuit (shown in Fig. 3-10) is a standing-wave oscillator composed of a tank (the resonator has made of lossy transmission lines) and gain stages (distributed negative transconductors (gd)) similar to all conventional RF oscillators) to overcome the loss of interconnects.  Fig. 3-10: Interconnect with distributed transconductors.  Assuming differential operation, the resonator has a virtual ground at both ends. The unloaded Q of the resonator can be calculated based on the interconnect properties by [49],  Q=  β 2α  (3-20)  To guarantee oscillation, the total transconductance gains should be equal to the interconnect loss. The oscillation frequency is determined by the resonant frequency of the resonator including the loading made by transconductances to make the effective loss to zero. As mentioned previously, the cross-coupled pair is a good choice for negative transconductor which can be characterized by an equivalent transconductance, gd, and capacitance, Cd. 34  Assuming that the transconductors are properly placed (based on the transistor sizing to make sure enough enough energy is provided to the wave to accommodate its propagation), they behave as a distributed equivalent transconductance, Gd, and distributed capacitance, Cd can be approximated by  Gd ≡  ng d l  Cd ≡  ncd , l  (3-21)  where n is the number of transconductors and l is the length of the interconnect (which they will add in parallel with the transmission line parameters Co and G). Based on adding the cross-coupled transconductances, the effective interconnect propagation constant, γ, can be calculated by  γ=  ( R + j ω Lo ) ( (G − Gd ) + j ω (C o + C d ) ) = α + j β  (3-22)  However, this equation does not provide any intuition about how each parameter is affected by the transconductors. By making some low-loss assumptions about the values of the transmission-line parameters the equations for the loss constant, α and the phase constant, β can be simplified as:  α≈  R 2  (Co + Cd ) (G − Gd ) Lo  +  2  Lo (G − Gd )Z o R ≈ + (Co + Cd ) 2Z o 2  β ≈ ω Lo ( C o + C d )  35  (3-23)  (3-24)  where Zo is the effective characteristic impedance of the interconnect and can be approximated by  Lo (C o + C d ) . These equations provide information on how α and β change with the  transmission-line parameters. The interconnect loss is a simple function of the series resistance, the conductance and transconductance, and the characteristic impedance. Note that ideally Gd is chosen such that there is no signal attenuation. By differentiating (3-23) and (324), the sensitivity of α and β to the transconductance can be expressed as  Z ∂α ≅− o ∂Gd 2  ∂β ≅0 ∂Gd  (3-25)  Based on this analysis, the characteristic impedance of interconnect determines the impact of the transconductance on the interconnect loss while the phase constant is completely independent of the transconductance. The analysis is slightly more complicated by adding the effects of Cd. Based on (3-25), parasitic capacitance both increases the loss (the first term) and decreases the effect of Gd (second term). In effect, the transconductor capacitance self-loads interconnect and reduces the effectiveness of the transconductor. Therefore, a good figure-ofmerit for the transconductor is  ωd ≡  gd cd  (3-26)  where ωd is similar to the high-frequency figure-of-merit (transit frequency) ωT for a transistor. The transconductor parasitic capacitance also increases the phase constant, effectively reducing the propagation velocity along interconnect.  36  3.2.5.2. Rotary Traveling-Wave Oscillator The rotary traveling-wave oscillator (RTWO) was first presented by John Wood et al., who realized CMOS test chips for 950 MHz and 3.4 GHz clocks [46]. The principle of the circuit is quite similar to two cross-coupled distributed oscillators. RTWOs are generated based on the Moebius effect, [46][48]: the differential line has two stable states; the one polarized positively, the other negatively. (Initial state of zero volts on the two lines is considered).  Fig. 3-11: Moebius effect [48].  Fig. 3-12: RTWO principle.  In the first case an open differential transmission line, with a delay of τ, is connected to a voltage source through a switch. When the switch is closed, the voltage wave signal travels along the line. As the wave travels, the signal will be weaken because of the transmission-line loss. The second case shows the differential line with a cross-coupled feedback, so that the signal is inverted after one round (delay τ). If the feedback is strong enough to reverse the 37  stable state of the line, then the state effectively switches. So the oscillation between the two polarized states occurs with a 2τ period.  There is no reason why the oscillation should prefer to occur in the counterclockwise or in the clockwise rotational direction as long as the system stays symmetric. In practice, the path is not perfectly symmetric and it is the direction with the lowest energy losses which is dominant.  The differential line has two stable states because of the cross-coupled inverters distributed around the ring (Fig. 3-12). Similarly to the single-ended distributed oscillators, the input and output capacitance of the inverters can be considered as distributed on the line. The oscillation frequency is given by the propagation speed of the voltage wave on the distributed line. The time that the voltage needs to propagate a one full circle on the ring represents half the period of the oscillation. It is interesting to note that it is the nonlinearity of inverters which is allowing oscillations. Indeed, if inverters were perfectly linear, the feedback reverse signal would just be able to compensate exactly the following polarization, leading to a zero polarized state and stopping any oscillation. There are several advantages in using such an oscillator as compared to the single-ended Distributed VCO or to a standard ring oscillator. The architecture is fully differential; the coupled strip lines have a better predictable inductance than a single strip line [46]. Indeed, the forward and backward paths of current are well defined for the strip pair as they have less dependency on substrate’s capacitance and substrate losses.  The resonator is fully closed which eliminates the bandwidth limitation caused by the impedance termination. The only section which disturbs the perfect symmetry is the feedback, 38  requiring the strip-line to pass in another metal layer (shown with gray line in Fig. 3-11) leading to a slight local mismatch of the impedance. Indeed, contrary to the ring oscillator, the energy which charges and discharges the MOS gate capacitances is part of the wave energy. This energy is not lost at each stage but re-circulates from one stage to another into the closed path [46].  Fig. 3-13: (a) Coupled LC oscillator (b) Coupled rotary wave oscillator.  In a conventional multi-phase LC oscillator, the coupling transistor is placed in parallel to the main switching pair (shown in Fig. 3-13(a)); therefore, the coupling factor is determined by the transconductance of the coupling transistor in the case of fixed oscillator cores [50][51]. Choosing larger coupling transistors, leads to higher transconductance, and the coupling factor will be higher while the phase imbalance will be lower. On the other hand, the higher transconductance will increase the noise contribution from the coupling transistors and stronger signal for a given power supply. Therefore, a trade-off between multi-phase 39  imbalance and phase noise is always present [52]. To solve this problem, the transmission line loading can be used in the coupling path (shown in Fig. 3-13-(b)) to increase the injection current and improve the coupling factor without increasing the transconductance of the transistors [52].  In contrast to LC-tank oscillators, wave-based oscillators are capable of providing an output frequency that is close to the transit frequency (fT) of the device by distributing parasitic capacitances along the transmission line [53]-[57]. The characteristics of the transmission line determine the oscillation frequency [57].  3.3. General Phase Noise Methods Different noise sources will affect an oscillator: thermal, shot, and flicker noise will produce fluctuations in the output of the oscillator in terms of amplitude and frequency and furthermore, substrate and supply noises are the other reasons for frequency impurity. These noise sources result in frequency fluctuations and their effect should be minimized. For example, using differential signaling would ideally eliminate the common-mode noise. The output of the oscillator is described as  Vout ( t ) = Vo 1 + a ( t )  f ωo t + ϕ ( t )   (3-27)  where the amplitude, Vo is the maximum voltage swing and f is a periodic function for representing the shape of the output waveform of the oscillator with the frequency of ωo, the phase fluctuation of ϕ(t), and the amplitude of a(t).  40  There are several ways for quantifying frequency instabilities of an oscillator. While detailed reviews of various techniques and measurement methods can be found in [58] -[61], the focus of this section is on the most popular figure of merit for characterizing the phase noise.  In the frequency domain, an oscillator’s frequency impurities are usually characterized in terms of the single sideband noise spectral density. It conventionally has the units of decibels below the carrier per Hertz (dBc/Hz) and is defined as:  P (ω + ∆ω ,1Hz )  L {∆ω} = 10 log  sideband o  Pcarrier    (  where Psideband ωo + ∆ω , 1Hz  )  (3-28)  represents the signal sideband power at a frequency offset,  ∆ω, from the carrier in a measurement bandwidth of 1Hz as shown in Fig. 3-14, and Pcarrier is the total power of the carrier.  Fig. 3-14: The phase noise per unit bandwidth.  The plot of the free-running oscillator phase noise (L{ω}) as a function of ∆ω on logarithmic scales is shown in Fig. 3-15. At large offset frequencies, there is a flat noise floor. The 41  spectrum of phase-noise can be described in three distinct regions: 1) rapid roll-off around the 3 2 carrier (close-in phase noise) with 1 f rate, 2) 1 f roll-off in intermediate offsets (out-of-  band region), and 3) flat phase noise where the phase noise hits the noise floor.  There are three popular approaches for analysis of the phase noise of circuits: Leeson’s model, Hajimiri’s approach, and Rael’s method. Hajimiri’s method is a useful numerical procedure to determine phase noise and provides insights into 1/f noise up-conversion and impact of noise current modulation. Rael’s method is useful for CMOS negative-resistance topology which provides a great insight into the design. In this research, both Leeson’s and Rael’s methods are applied in our oscillator phase noise calculation discussion.  Fig. 3-15: A typical phase noise plot for a free running oscillator.  3.3.1. Leeson’s Formula (Time-Invariant Phase Noise Model) The phase noise model proposed in [62] and later expanded in [63][64] is widely known as the Leeson’s model, and is the most popular model used in practice, partly due to its simplicity. It  42  is based on a linear time-invariant (LTI) approach for oscillators. It predicts phase noise as follows:   2FkT L {∆ω} = 10log   Ps     ω 2   ω13 f o 1 +    1 + 2 Q ∆ ω   L    ∆ω      (3-29)  where F is an experimental parameter, k is Boltzmann’s constant, T is the absolute temperature, Ps is the average power dissipated in the resistive part of the tank, ωo is the oscillation frequency, QL is the effective quality factor of the tank with all loadings accounted for (also known as loaded Q), ∆ω is the offset from the carrier, and ω 1/3 f is the frequency of 3  the corner between them 1 f and 1 f 2 regions, as shown in Fig. 3-15.  3.3.2. Rael’s Method [65] Rael discussed the factors which change the ‘F’ in the Leeson’s formula. In a negativeresistance differential pair oscillator (Fig. 3-16(a)), the F(∆f) can be represented as:   2F ( ∆f ) kT  ω 2  o L{∆ω} = 10log     Ps 2 Q ∆ ω   L   (3-30)  F ( ∆f ) = 1 +  2γ I bias R P 4 + γ g do , M 3 R P 9 πA  where F(∆f) is related to three different noise sources; noise from tank resistance, noise from differential pair, and noise from current source transistor, respectively (shown in Fig. 3-16).  43  Fig. 3-16: Noise Sources from different parts of a cross-coupled transistor.  To achieve minimum phase noise, it is desirable to minimize F(∆f). To better understand the noise coming from the tail current, the effect of the differential pair switching on the tail current should be considered as it acts similar to a single-balanced mixer. The noise is translated up and down in frequency, and enters the resonator. The single-balanced mixer shows the largest conversion gain around the fundamental switching frequency, that is why only mixing by the fundamental is important. Noise originating in the tail current at ωm upconverts to ωo±ωm. Similarly, noise at 2ωo±ωm, downconverts to ωo±ωm. The phase noise caused by thermal noise originally at  2ω o  , is:  4 kTR P  ωo  L {∆ω} = γ g do ,M 3 R P 9 PS  2Q ∆ω   2  (3-31)  where γ is the noise factor of a single transistor (usually, ~ 4/3). By adding an LC filter resonating at 2ωo in the common-mode, the 2ωo component will be attenuated (ideally eliminated). This is because the white noise of the tail current source experiences a significant conversion gain around the second harmonic of the oscillation frequency [65].  44  As mentioned before, the related noise of the differential pair in F(∆f) can be represented as  F ( ∆f  )=  2γ I bias R P πA  (3-32)  The output amplitude, A, is represented as (2/π)IbiasRP. It is not simple to replace A with its equivalent and cancel out the Ibias from numerator and denominator because as Ibias increases, there is a limit for output amplitude which is defined by the supply voltage. Above that maximum amplitude which is imposed by supply voltage, by increasing the Ibias, the amplitude will not change but the power consumption will increase. Therefore, the operation region of oscillation can be divided to two different regions: current-limited regime which is set by amplitude, and voltage-limited regime in which the amplitude is saturated. The best phase noise can be achieved at boundary of these two regimes.  3.4. The Proposed Design In this Section, the step-by-step design of the proposed oscillator is explained starting with the design of the standing-wave oscillator (SWO), and the rotary-wave oscillator (RWO), followed by discussions on phase noise in RWOs, phase noise in loaded SWOs, and the coupled oscillator dynamics. This chapter will conclude by RWO phase noise reduction techniques and related simulations.  As a starting point of the design, it is important to choose the transistor sizes properly to make the circuit operate at desired frequency with the minimum noise figure. The fmax and NF are plotted in Fig. 3-17 with respect to the width the transistor in a 0.13-µm CMOS technology for different current densities. Total width is kept constant as 50 µm. And the finger width varies 45  from 0.5 µm to 50 µm. As shown in Fig. 3-17, the current density varies from 50 µA/µm to 150 µA/µm. To be able to neglect the gate resistance, the finger width should be chosen narrow. Based on two parameters of maximum frequency of operation (fmax) and minimum noise figure (NFmin for the transistors, the finger width of 1 µm is chosen for this design). At this width both maximum fmax and minimum NF is achievable which is favorable for CMOS design in high frequency.  Fig. 3-17: Noise figure and fmax measurement for the NMOS device in 0.13-µm CMOS Technology.  fmax is a better parameter to be considered than fT because it considered the gate resistance. shown as follow:  f max ∝  fT Rgate  and the transient frequency can be calculated through;  46  (3-33)  2π fT =  1 ID W 2µnCOX ID LW L = 2 2 COX WL COX L 3 3  2µnCOX  gm = Cgs  (3-34)  For a given drain current density, i.e., ID/W, to the first order of approximation, based on the above equation, fT is independent of W ; therefore, the fmax is proportional to W1/2. The other important parameter is NF which is affected by different noise sources including gate, source, and drain, given as [66],  NF = 1 +  Rg Rs  (R +γ  g  + Rs )  Rs Rcho  2   f  ∗   fT   2  (3-35)  where Rg, Rs, and Rcho are the gate, source, and channel resistance, respectively. The relationship of fT with W is shown in (3-33). Rcho, Rg, and Rs can be calculated through  1 Rg = 3n f  Wf   1 R ω  ; L =   R ∗ L  ; Rcho = R ω W   2µnCOX I D s  T  L  2  (3-36)  and ID can be calculated through,  ID =  1 W 2 µnCOX (VGS − VT ) 2 L  (3-37)  For simplicity the gate related noise can be ignored. Looking into (3-34), and considering the relationship of RS, Rcho and fT with width, it can be easily seen that NF relatively changes with W3/2.  47  3.4.1. Standing-Wave Oscillator (SWO) The schematic of a differential quarter-wave (λ/4) SWO is shown in Fig. 3-18(a) with its equivalent differential small-signal model. A standing-wave is supported in the transmission line tank when negative resistance generated from cross-coupled NMOS transistors compensates the tank losses.  The transistors contribute loading through the drain-bulk capacitance, Cdb, gate-source capacitance, Cgs, and gate-to-drain overlap capacitance, Cgd, which is enhanced due to the Miller effect. Additionally, the output buffer differential capacitance, Cbuff, loads the tank. The desired frequency tuning range is provided through the tuning varactor, Cvar. An equivalent differential capacitance for the tank circuit is (shown in Fig. 3-19)  C equ = C var + 12 C db + 14 (C gs + C sg ) + 2C gd + C buff .  (3-38)  A minimum transconductance, gm, is required to overcome the tank losses due to the transmission line quality factor, QTL, and capacitance quality factor, QC.  Fig. 3-18: Standing-wave oscillator and equivalent small-signal model.  48  Fig. 3-19: Capacitors related to cross-coupled transistors.  As shown in [67], the impedance of the lossy transmission line is calculated from  Z ( −ℓ ) = Z o  Z L + jZ o tanh ( γ ℓ S Z o + jZ L tanh ( γ ℓ S  ) )  (3-39)  The used resonator is shorted at the end, therefore, the related admittance will be  Y TL =Y o coth ( γ lS )  (3-40)  where γ = α + j β is the propagation constant comprised of the attenuation (α) and phase (β) constants, Yo=1/Zo is the characteristic admittance, and ls is the transmission line length. The total differential admittance of the tank is  YSWO =  1 ( 2 jω Cequ + G − g m + Yo coth (γ ℓ S ) ) , 2  (3-41)  where G is the parasitic conductance including the NMOS channel conductance, gds, and conductance due to the series resistance of the varactor and device capacitances, GC. At the oscillation frequency, fo, the varactor conductance (which dominates the loss) is 49  GC =  ωo Cvar QC ωo Cvar 2 , ≈ = r ω C ( ) v o var QC 1 + QC2  (3-42)  where rv is the series resistance of the varactor. Hence, the loaded quality factor of the oscillator is defined by  QSWO =  ωo ∂Y SWO ∂ω 2 Y SWO ω=ω  (3-43)  o  For the SWO with a lossy tank and varactors, the loaded quality factor is  Q SWO  −1 2 1 τω o − v p ω o ℓ S csch ( γ ℓ S ) = , 2 jτω o + 12 GZ o + coth ( γ ℓ S )  (3-44)  where τ = 2 ZoCequ is a time constant for the capacitive loading of the transmission line and vp is the phase velocity ( vp =  1 ). When device loading is eliminated (i.e., Cequ , G = 0 ), the LC  loaded Q reduces to QL = β 2α , the unloaded quality factor of a λ/4 transmission line.  In Fig. 3-20, the loaded quality factor for the SWO tank is plotted versus the loading time constant (for different capacitance quality factors). The unloaded quality factor of the transmission line is assumed to be 15, a typical value for a shielded microstrip line in a silicon integrated circuit process. If the quality factor of the capacitance, QC, is very large, the quality factor of the tank improves since more energy is stored in the high quality capacitor.  50  Fig. 3-20: QL vs. loading time constant for various QC (QTL = 15).  Typically varactors offer a low quality factor in the range of 2 to 10 for the 60 GHz frequency range, and in this case, Fig. 3-20 illustrates the capacitive loading on the tank reduces the overall tank quality factor. In compare with the transmission line quality factor, the worse varactor quality factor will degrade the overall tank Q. The lower loaded quality factor will be shown to reduce the phase noise of the SWO. Based on the one-port oscillator model, the active and load admittances can be written as  YIN = − YL =  Yo coth ( γl S ) 2  gm 2 + j ωCequ +  G 2  (3-45)  From (3-45), the oscillation conditions (i.e., Γ L Γ IN = 1 ) are found by separating the real and imaginary parts of the oscillator admittance.  51  j ωτ + Im {coth γl s } = 0  ( G − gm ) Zo + Re {coth γl s } = 0  (3-46)  The reactive behavior of the oscillator in (3-46) indicates that the capacitive loading reduces the electrical length of the transmission line. The oscillation frequency of the SWO, fo, is calculated from a linear approximation around β l S = π 2 of the imaginary term in (3-46).  fo ≈  1  4(v ℓ s +τ ) −1 p  (3-47)  For a given oscillation frequency, the loading time constant reduces the necessary electrical length of the transmission line tank and allows more frequency tuning. From (3-46), the appropriate loading for tuning range of at least 5% implies a capacitive loading time constant of at least τ ≥ 0.05 ν P−1 lS . The real term in (3-45) indicates that capacitive loading reduces the loaded Q and increases the required transconductance to start-up and maintain the oscillation. Therefore, the minimum transconductance for oscillation is  g m ≥ G + Yo Re {coth γ l s } ≈  ω o C var QC  +  Yo QTL  (3-48)  The varactor tuning range determines the tuning range of the oscillator and tank loading from (3-47). Nonetheless, larger frequency tuning range for the SWO costs additional transconductance and power consumption.  Leeson’s formula predicts the phase noise of the SWO by accounting for the loaded quality factor and the oscillation power [68]. The noise of active and passive devices can be 52  decomposed into in-phase and quadrature noise contributions with respect to the oscillation and expressed as noise conductance, Gn, and susceptance, Bn.  Yn =  in ,Q i Ynoise Gnoise + jBnoise = = Gn + jBn = n , I + j , GL GL Vo Vo  (3-49)  where Ynoise = Gnoise + jBnoise is the equivalent noise admittance of the oscillator [73].  Gn = Gnoise GL , Bn = Bnoise GL , and GL is the oscillator load admittance in the free-running state, and Vo is the amplitude of oscillation. It has been shown that the noise conductance more strongly impacts amplitude fluctuations while the noise susceptance dominates the phase perturbation of the oscillator. Thus, we focus our attention to the noise susceptance, Bn.  The oscillator operation is generally chosen between the voltage- and current- limited regimes of operation based on the bias current, Ibias that generates a voltage swing, Vo, to minimize the oscillator phase noise [99]. For low bias currents, bias current variations result in a proportional change in this voltage swing. The phase noise at a frequency offset ∆ω for an SWO is [69]:  2  4kTF  ωo  L {∆ω} =   , GVo2  2QSWO ∆ω   (3-50)  where   4I ω π Vo F = 1 + γ  bias o +  π GS 2Veff  53    .   (3-51)  where Veff is the effective voltage of the bias transistor. The excess noise factor, F, consists respectively of noise contributions from the tank conductance, differential pair, and current source. The differential pair current noise depends on the channel noise coefficient, γ, bias current, and slope of the differential waveform, S. The current source noise is inversely proportional to the effective gate voltage, Veff . The relative contribution of each noise source depends on the Ibias, fo, and the transistor, fT [69]. For instance, high fT supports fast rise and fall times that in turn reduce the contribution of differential pair noise [71]. It should be added that the effect of the output extra parasitic can change the output rise and fall time.  At millimeter-wave frequencies, the slope is largely determined by the first harmonic, i.e., S =  ωo. For Ibias = 3mA, γ=4/3 , Veff = 0.2V, and Vo = 1V, the excess noise factor is sixteen. For QSWO = 15, the phase noise is -93 dBc/Hz at a 1 MHz offset. When Ibias reaches a critical level, additional current does not change Vo because of transconductance compression (gm saturated value).  In the voltage-limited regime, the phase noise is  2  i n2,Q    ωo ωo B n2  L {∆ ω } = 2 2   = 2  V o G  Q SW O ∆ω  G  Q S W O ∆ω   2  (3-52)  where in2, Q = 4 kT G F . The noise susceptance, Bn, is independent of Ibias, since in the voltage-limited regime, the amplitude voltage is saturated and thus does not depend on Ibias.  The phase noise of an SWO VCO is simulated in Spectre at 45 GHz for a tuning range of 5% based on an NMOS cross-coupled pair and plotted in Fig. 3-21 as a function of bias current. 54  As can be seen from the figure, the phase noise at a 1 MHz offset decreases by 10 dB as the tail current increases and flattens above 3 mA as the tank enters the voltage-limited regime.  Fig. 3-21: Spectre simulation of the phase noise at 1 MHz offset for a standing-wave oscillator as a function of bias current (W = 10µm).  3.4.2. Rotary -Wave Oscillator In our analysis, the proposed RWO is decomposed into two circuits; one that supports standing-wave modes and one that supports rotary-wave modes. The proposed RWO (shown in Fig. 3-22) comprises of four standing-wave oscillator stages (coupled together) distributed around a differential transmission line ring with one differential inversion along the transmission line ring.  To support the traveling wave around the loop, four SWO stages are coupled together with a λ/8 transmission line (i.e., β l R = π 4 ). Hence, the traveling wave locks each of the SWO stages at 45° with respect to its neighbors. Therefore, each SWO stage is effectively injection locked to the neighboring stage such that the overall structure behaves as a single oscillator. In 55  this topology, the direction of the rotating wave is arbitrary. Previous work has discussed how the direction of the rotating wave may preferentially be chosen [72]. One other way that has been suggested is having an imbalance in the fully symmetric layout which forces the wave to travel in the lower loss path [46].  Fig. 3-22: Millimeter-wave RWO with four SWO stages distributed around a transmission line coupling network.  A small-signal model of the proposed RWO is shown in Fig. 3-23. The oscillators are assigned an arbitrary absolute phase. By choosing one of the SWOs as a reference node at 0°, the standing-wave mode forces the nearest neighbors to have an identical phase. However, one oscillator must be out-of phase (180°) with respect to the reference oscillator. This implies that two virtual grounds exist along the horizontal and vertical axes. 56  Fig. 3-23: Small-signal model of rotary-wave oscillators.  Fig. 3-24: Small-signal models of the standing-wave and rotary-wave oscillation modes.  The horizontal virtual ground exists along the differential standing-wave oscillator admittance. Similarly, a vertical virtual ground exists at the oscillator that is on the opposite side of the reference oscillator because the path length corresponds to a 90° phase shift from the reference node.  The virtual ground cuts through this opposite oscillator and implies that only two neighboring oscillators couple to the reference oscillator. Consequently, the standing-wave admittance is calculated from the circuit model in the top of Fig. 3-24 and incorporates the contribution of 57  the original SWO tank as well as the coupling network. This is consequently referred to as the loaded standing-wave tank. The standing-wave oscillator injects a current, ISWO, into the coupling transmission lines. The current is split into two components that travel in opposite directions into the coupling network. The coupling admittance looking into the neighboring SWO is calculated as  YC , SWO = Yo  Yo coth ( γ l R ) + 2YSWO + Yo tanh ( γ l R ) 2Yo + 2YSWO tanh ( γ l R )  . (3-53)  The admittance of the loaded SWO is the parallel combination of two coupling networks and the single-ended admittance of the original SWO, i.e. Y = 2YSWO + 2YC , SWO . The proper length of the RWO coupling lines is derived from Im {2YSWO + 2YC , SWO } = 0 . Assuming that α = 0, the coupling transmission line length is determined from the roots of  (  ' cot ( β l R ) − 1 − 2 YSWO  ( (  ' − 5 + 1 − 2 YSWO  2  ) tan  2  2  ) tan (β l  (β l R )  + 2 tan ( β l R ) Im {Y  ' SWO  }  R  ) Im {Y  2  )  ' SWO  },  (3-54)  =0  where the prime superscript denotes an admittance normalized to Yo. When the SWO is tuned to resonate at the oscillation frequency ( ℑ {Y SW O } = 0 ), the solution to this equation is given ' by cot ( β l R ) = 1 − 2 YSWO  2  . Therefore, an SWO with high Q results in a coupling  transmission line length of β l R = π 4 . To absorb the loading capacitance, Cequ, into the RWO tank rather than the SWO tank, the coupling transmission line length has to be adjusted  58  according to (3-53). The Q of the loaded SWO tank is found by substituting the parallel admittance combination, 2YSWO + 2YC , SWO into (3-42);  ∂Y SW O ∂Y C ,SW O + ωo ∂ω ∂ω QL = . 2 Y SW O +Y C ,SW O  (3-55)  The Q of the loaded SWO tank is approximated from the parallel combination of Qs contributed by the SWO and coupling network, i.e., QL ≈ 2QSWO  QC , SWO . The quality factor  for the SWO in the presence of loading from the coupling transmission lines depends on whether the Q of the coupling network is greater or less than the quality factor of the SWO. If the SWO tank and coupling network have similar QS, the loaded Q is the same as the unloaded SWO Q.  The Q of the RWO also depends on the quality factor of the capacitive loading. For low parasitic conductance (large QC), the quality factor of the loaded SWO is higher than the RWO. For high parasitic conductance, the RWO has a higher tank quality factor. The RWO quality factor is improved with respect to the SWO quality factor because more energy is stored in the RWO coupling networks than in the SWO tank.  A rotary-wave current, IRWO, is also present through the RWO illustrated in Fig. 3-22 and presumably dominates the standing-wave mode. From the figure, the rotary-wave current bypasses the SWO cell and does not interact with the SWO admittance. The coupling admittance of the rotary-wave mode is found by the translation of the coupling admittance of the next stage through coupling transmission line. 59  Y C ,RWO =Y o  (Y C , RWO + 2Y SWO ) +Y o tanh ( γl R )  Y o + (Y C ,RWO + 2Y SWO ) tanh ( γl R )  (3-56)  Solving for YC,RWO,  YC , RWO  2     2 1 = YSWO ×  −1 + 1 + ' coth ( γl R ) +  '    YSWO  YSWO     (3-57)  Fig. 3-25: Theoretical calculation of the ratio of rotary-wave to standing-wave currents for different transmission line quality factors, ( Q C = 5 ).  The ratio of the rotary- and standing-wave currents determines whether the rotary-wave mode dominates the locked behavior and is plotted in Fig. 3-25 as a function of the loading time constant of the SWO. Notably, more current is stored in the rotary-wave current with respect to the standing-wave current as the loading capacitance is reduced. Additionally, the energy stored in the rotary-wave mode is increased with high quality factor transmission lines. Intuitively, the SWO and RWO modes become increasingly decoupled as the Q of the passive 60  elements increases. As the transmission line and capacitor quality factor reduces, less current propagates in the rotary-wave mode through the coupling network. If the ratio is small, the oscillator will no longer support rotary-wave oscillations.  3.4.3. Phase Noise in Rotary-Wave Oscillators The phase noise of the conventional rotary-wave oscillator has been analyzed in [62] and [69], but the phase noise of the proposed hybrid RWO/SWO has not been previously analyzed. This section quantifies the phase noise reduction of the proposed RWO with respect to an individual SWO. The phase noise analysis is decomposed into the impact of the rotary-wave coupling network and the coupled oscillator dynamics.  3.4.3.1. Phase Noise for the Loaded SWO A small-signal model for the noise is illustrated in Fig. 3-26. The noise current sources in the RWO are generated by the active devices in the SWO and will see the SWO coupling network admittance YC,SWO given in (3-52). Assuming the oscillator is biased in the voltage-limited regime, the phase noise for the loaded SWO is  B n2  ωo  L {ω} ∝ 2   G L  Q L ∆ω   2  (3-58)  where GL is the loaded conductance formed from the parallel combination of the SWO and the coupling network conductance; e.g., G L = GSWO + NGC ,SWO . N is the number of coupling networks seen at the SWO and QL is defined as (3-54). Normalizing the RWO phase noise to the SWO phase noise, the predicted phase noise reduction is  61  2  PNred  G  Q  =  SWO   SWO   GL   QL   2  (3-59)  If the coupling network and the standing-wave oscillator Q are similar, the Q of the loaded SWO is unchanged, i.e., QL ≈ QSWO , and only a small change in the phase noise occurs. However, the coupling network increases the conductance seen at the oscillator tank.  Fig. 3-27 plots the phase noise reduction of the loaded SWO with respect to the unloaded SWO. If only one coupling network is connected to the SWO, the phase noise is at most 6 dB lower since the conductance doubles. For the proposed RWO, each SWO sees two coupling networks and the phase noise decreases by as much as 9.5 dB. In both cases, the phase noise reduction is limited by the loading time constant as more energy is dissipated in the lossy capacitor. The reduction of phase noise due to the increase of parallel conductance must be accompanied by additional current/power consumption to maintain the voltage-limited operation.  Fig. 3-26: Small signal model of noise injected into rotary-wave structure.  62  Fig. 3-27: Analytical calculation of the phase noise reduction from the introduction of additional coupling networks to the SWO resonator with respect to the SWO loading time constant (QTL = 15, QC = 5).  3.4.3.2. Coupled Oscillator Dynamics Injection locking between each oscillator also impacts the phase noise. As each oscillator injects noise into the rotating wave, this noise induces a phase shift which continues to propagate around ring. The phase noise of coupled oscillators has been studied from the standpoint of standing-wave coupling for beam-steering applications by Chiang et al. [73]. This coupled oscillator treatment is adapted to develop an expression for the phase noise for the RWO phase noise.  Fig. 3-28: Determination of coupling strength from the combination of standing– and rotary-wave modes.  63  The phase perturbation of the ith oscillator in the RWO from the desired phase is represented as θ k → θ k + δθ k and is related to the noise susceptance, Bn, of the SWO where the noise contributions are assumed to be independent, identical random variables. In [73], the general frequency-domain phase dynamics of the coupled oscillators is given by  N I SW O , j jω B δθ k = − ∑ ε kj δθ k − δθ j ) − n , ( ω3dB I SW O , k GL j =1  where ω3dB = ωo 2QL ,  ε kj  (3-60)  is a coupling factor from jth oscillator to the kth oscillator, and  ISWO,j and ISWO,k are the amplitude of the current of the jth and kth oscillators, respectively. Finally, GL is the parallel conductance seen at the resonant tank, i.e., GL = GSWO + 2 GC , SWO . To solve the dynamics of the rotary-wave coupled oscillator system, the oscillator current at each stage and the coupling factor must be determined for the RWO. The superposition of the standing-wave and rotary-wave currents determines the current injected from one SWO to the next and is illustrated in Fig. 3-28. We arbitrarily assign the direction of propagation from left to right. Defining the current entering the SWO stage on the coupling transmission line as Iand the current that exits along the coupling transmission line as I+, the superposition of the two currents in Fig. 3-24 is   I RW O 1  −    I SW O 2   (3-61)  I 1 1 I + = I RWO + I SWO = I SWO  RWO +  2  I SWO 2   (3-62)  1 I − = I RW O − I SW O = I SWO 2  64  Since I + , k −1 = I − , k , the current injected from the k-1th SWO to the kth SWO is  ε k −1, k =  I SW O , k I SW O , k −1  =  I + , k −1 I SW O , k I SW O , k −1 I − ,k  Y C ,SW O +Y C ,RW O 2Y C ,SW O  Y C ,SW O  =  2Y SW O . +Y C ,RW O + 2Y SW O  (3-63)  Since each cell is identical, the coupling factor at each stage is identical, ε = ε k −1,k . Based on the admittances calculated in the previous section, the coupling factor is plotted in Fig. 3-29.  Fig. 3-29: Analytical prediction of the coupling factor and phase as a function of the SWO loading time constant.  For a small loading time constant, the coupling factor is small and implies that the SWOs are weakly coupled. Increasing the loading time constant increases the coupling factor and additionally introduces an undesirable coupling phase between the neighboring stages.  T  The phase perturbation of each SWO is expressed as a vector δθ = δθ1 δθ2 ... δθ N  . Therefore, the coupled phase dynamics in (3-60) are expressed in an N×N matrix that captures 65  the interaction of N SWOs. The coupling network topology is a matrix, N, that represents the RWO network. The RWO coupling matrix for four SWO is represented as a 4×4 matrix where each row expresses the dynamics from (3-60):   −ε − jw  ε N =  0   0  where, w =  0  0  −ε − jw  0  ε 0  −ε − jw ε  ε    0  , 0   −ε − jw   ω . Now, the coupled dynamics in (3-59) are expressed as ω3dB  (3-64)  N δθ =  Bn and the GL  phase perturbation due to the noise susceptance is  δθ = P  Bn , GL  (3-65)  where P = N-1. The phase noise of each SWO is expressed in terms of the phase noise contributions of each SWO in the system;  δθ k  2  B n2 = 2 GL  2  N  ∑p j =1  k ,j  ,  (3-66)  where pkj is an element in the matrix P. In the four element coupling network, the phase noise is:  66  2  δθ k  2  2  1  1 Bn2  w 6 + 4 w 4 ε 2 + 6 w 2 ε 4 + 4  1 Bn2  = 6   ≈  2 2 , 4  w G L  w + 4 w 4 ε 2 + 4 w 2 ε 4 + 16  w 2 G L2   (3-67)  where the final approximation holds at low frequency offsets, i.e., ∆ ω < ω3.dB . The term in parenthesis represents the phase noise of the uncoupled SWO. Therefore, the coupling reduces the phase noise by a factor of N, in this case an additional 6 dB. At large frequency offsets, the phase noise reduction approaches 0 dB.  3.4.3.3. RWO Phase Noise Reduction and Simulation Substituting the phase noise reduction due to the loaded tank conductance and the coupled oscillator dynamics, the phase noise reduction for low frequency offsets is approximated as  2  PN red  2  G  Q  1 =  SWO   SWO  . G Q N  L   L   (3-68)  For a four-oscillator RWO, SWO coupling reduces the phase noise by an additional 6 dB compared to (3-58). As the frequency offset approaches the injection locking bandwidth, i.e., ∆ ω → ω 3dB , the phase noise reduction due to coupling degrades and approaches 0 dB. Since  the coupling strength is relatively large (ε~0.4), the phase noise reduction extends above 100 MHz; well beyond the 1 MHz of interest in many communication applications. Therefore, the minimum phase noise reduction of the RWO with respect to the SWO is roughly 15.5 dB. The overall absolute phase noise can be expressed as  67  2  1  G SW O  L {∆ω} =   L SW O {∆ω} , N  GL   (3-69)  where LSWO {∆ω} is calculated in (3-50 (a)). To verify this analysis, harmonic balance simulations of the SWO, loaded SWO, and RWO using a 0.13µm NMOS process is presented in Fig. 3-30.  Each SWO is biased at 3.5 mA and the nominal oscillation frequency is 45 GHz. When the SWO is loaded by the finite-Q coupling network, the phase noise of the loaded SWO is 7 dB lower than the original SWO. This is less than the 9.5 dB predicted from (3-58) as accounted for by the capacitive loading of the NMOS transistors. Below the 1/f corner (around 200 kHz) of the oscillator, the phase noise reduction is smaller. For the RWO, the phase noise is suppressed by an additional 4 dB relative to the loaded SWO at a 1 MHz offset. Therefore, the simulated phase noise reduction is predicted from a combination of the increased tank conductance and the interaction between SWOs through the RWO network.  The phase noise at a 1-MHz offset is plotted as a function of the bias current in Fig. 3-31 for the unloaded SWO and the RWO, ignoring the impact of varactors. The quality factor of the varactor is low and will degrade the phase noise of the oscillator. To have a fair comparison between the phase noise of the oscillators and not VCOs, the varactors are ignored for comparing the phase noise of RWO and SWO.  68  Fig. 3-30: Harmonic balance simulation of the phase noise for an SWO, loaded SWO, and RWO (Ibias = 3.5mA, QTL = 20 ).  Fig. 3-31: Simulation of phase noise reduction at 1 MHz offset for the RWO and SWO with no varactor loading versus bias current.  At a low bias current (in the current-limited regime), the phase noise reduction is 10 dB. As the bias current increases and the oscillator enter the voltage-limited regime, the phase noise  69  reduces by around 16 dB. This agrees relatively well with the prediction of the bound on the phase noise reduction of 15.5 dB. Additionally, the minimum phase noise occurs at 4 mA as opposed to 3 mA due to the low tank conductance.  3.5. Circuit Implementation in 0.13-µm BiCMOS Technology The RWO circuit is fabricated in a seven metal-layer, 0.13-µm SiGe BiCMOS process. The implemented circuit includes the rotary-wave oscillator, an 8-to-1 phase selector, and a 50-Ω output buffer described in [16]. Microstrip transmission lines are realized with thick aluminum metal layers (AM) and a copper metal layer (MQ) as a shielded ground to eliminate substrate coupling (modeled in HFSS and shown in Figure 3-32).  Figure 3-32: HFSS model for coupled transmission line.  The series and shunt losses of coupled transmission lines affect the quality factor, and consequently the phase noise of the oscillator. The geometry of the interconnect width (w) and separation (s) impacts the transmission line losses. Increasing either w or s tends to decrease series loss due to the reduced skin effect but it increases shunt loss due to increased losses in the silicon dioxide. The Q for the thick-metal transmission line is plotted as a function of these parameters in Figure 3-33. 70  Also not only one transmission line has been simulated in HFSS to choose the proper width and length, but also the SWO load transmission line has been simulated in HFSS to make sure of proper quality factor shown in Figure 3-33. As shown in Figure 3-34(a), the top metal layers are thicker and more proper for high frequency design to achieve lower parasitic capacitors.  Figure 3-33: Coupled transmission line quality factor for various width and spacing at 45 GHz.  Figure 3-34: (a) Technology layer models (b) SWO load layout imported from Cadence to HFSS.  71  To achieve high Q, the spacing between the RWO differential transmission line are optimized for width of 4 µm and space of 16 µm, respectively, resulting in a differential characteristic impedance of 50 Ω while maintaining area efficiency. The attenuation of these transmission lines is 0.92 dB/mm. The length of the SWO and RWO transmission lines are respectively 0.185 mm and 0.45 mm. The SWO transmission line length absorbs the additional loading introduced by the varactors and transistor parasitic capacitances.  Figure 3-35: Monte-Carlo simulation for transient output of the oscillator for all eight different phases.  A Monte Carlo simulation of the RWO is plotted in Figure 3-35 and shows the simulated output for mismatch and process variations at all eight oscillator nodes of the RWO. The steady-state phase difference of each oscillator is 45° apart. Monte Carlo simulation shows that in 92% of 100 runs, the phase mismatch between each SWO is less than 1° (0.38 psec) against circuit mismatch and 8% of the runs it is less than 0.95° (0.35 psec). As mentioned before, each SWO stage is loaded with an output buffer to isolate the oscillator core from a differential 8:1 multiplexer. To drive the 50-Ω output impedance, the phase selector output is buffered by a differential 50-Ω driver. The multiplexer is implemented in two stages; the first stage is a 4:1 multiplexer implemented with four HBT differential pair legs and NMOS 72  cascode transistors. The second stage is a 2:1 multiplexer selects the differential output phase. To drive the 50-Ω output impedance, the phase selector output is buffered by a differential 50Ω driver.  Figure 3-36: Chip microphotograph of the RWO with output multiplexer and buffer.  Figure 3-37: Test chip setup.  73  The die micrograph of the circuit and the die under test with probe station are illustrated in Figure 3-36 and Figure 3-37, respectively. The layout of the chip occupies a total area of 0.9 mm × 0.7 mm. The active area of the RWO, including buffers between the oscillator and phase selector, is 500 µm × 500 µm. Notably the first multiplexer of the phase selector is located in the interior of the RWO to allow symmetric loading of the RWO. The second multiplexer is placed outside of the RWO. Therefore, only one differential signal is routed underneath the RWO, which has been modeled with transmission line.  3.5.1. RWO Measurement Results The rotary-wave oscillator operates at 1.2 V with a current consumption of 11.5 mA. Therefore, the oscillator core consumes 13.8 mW. The phase selector and 50-Ω driver operate from a 2.5 V supply and draw 8.5 mA and 10 mA current, respectively. The overall power consumption of the chip including the output buffers is 58.4 mW. The chip is tested with onwafer probing using Picoprobe 40A GSG RF probes. An Agilent E4448A 50GHz spectrum analyzer measured the frequency and phase noise characteristics. One differential output is terminated by a 50-Ω termination through a bias-tee to generate a single-ended output.  In Figure 3-38, the measured frequency spectrum illustrates a carrier power of -21.5 dBm at 45 GHz. The reason for achieving lower frequency of oscillation in measurements as compared to simulations can be attributed to the fact that the foundry-provided models used in this design were characterized only up to 40 GHz. To alleviate this problem, in the next design, HFSS modeling is used for the transmission lines’ model over the desired frequency range.  74  When the cable loss of 10 dB and probe losses of 1.5 dB are de-embedded from the power measurement, the actual power of the oscillator circuit is -10 dBm. The path through the RWO buffer, phase selector, and output buffer accounts for additional 10 dB of loss between the RWO core and the bondpads and suggests an oscillator core power of 0 dBm. Spurious tones are present on the oscillator spectrum at a 5 MHz offset from the carrier as well as at 25 MHz offset. While the voltage supply, VDD, is biased using batteries, a switching supply is used to bias the current source which introduced the spurious tones.  Figure 3-38: Measured output frequency spectrum at 45 GHz.  Figure 3-39 shows the amplitude and frequency dependence of the oscillator over the tuning range. Only 2 dB of variation is seen in the amplitude while achieving a 6.5% tuning range. The simulation result in Spectre is plotted in the dashed line and compared to the measurement result; plotted in the solid-line. The difference between the measured and the simulated tuning range is less than 2 GHz while the amplitude error is less than 1 dB. The simulation result predicts less variation in amplitude than the measured tuning range.  75  Figure 3-39: Tuning range and amplitude variation of the measured RWO as compared to the simulation results.  Figure 3-40: Phase noise measurement for free-running oscillator at 45 GHz.  Figure 3-40 shows the phase noise measurement of the free-running oscillator. At 45 GHz, the phase noise is -91.32 dBc/Hz at a 1 MHz offset at a 3 mA bias. This oscillator has a phase noise of -112 dBc/Hz at an offset of 10 MHz.  As shown in Figure 3-41, the phase noise at a 1 MHz offset decreases as the tail current increases and flattens as the tank leaves the current-limited regime. From this plot, the 76  minimum phase noise is -93 dBc/Hz at a tail current of 4 mA. Above this current level the phase noise increases indicating the onset of the voltage-limited oscillation regime. This compares favorably with the simulation for the phase noise variation of the individual SWO in Fig. 3-31.  Figure 3-41: Measured phase noise at 1MHz for RWO current values and the FOM at 45 GHz.  Additionally Figure 3-41 illustrates the FOM for the oscillator;   f FOM = PN − 20 log  o  ∆f    Pdc   + 10 log    1mW    (3-70)  The optimum operating point from the standpoint of the FOM is when the bias current for each SWO cell is chosen to be equal to 4 mA. The FOM is slightly lower than previous work (Table 3-1) but this oscillator is capable of providing multiple phases. In comparison with other works, the phase noise of the fabricated chip is higher than the rest in the price of lower power as one of the major goals of this design is to be low power. Otherwise, by increasing the oscillator power consumption, a better noise performance is achievable. 77  Table 3-1: Performance comparison of microwave oscillators in silicon processes.  Paper #  [15]  [75]  [76]  This Design  Technology (nm)  65  180  90  130  Frequency (GHz)  54  30  58  45  Tuning Range (GHz)  6.1  0.25  5.2  2.92  Phase Noise @ 1MHz (dBc/Hz)  -95  -104  -91  -93  Power Consumption (mW)  7.2  52  8.1  19.2  FOM (dBc/Hz)  -178  -175  -177  -173  Area (mm2)  0.23  1.1  0.07  0.25  78  CHAPTER 4 : MULTIPLEXER AND VGA DESIGN Variable-gain amplifiers (VGAs) are one of the important building blocks of communication systems. Particularly, in transmitters, they have been used extensively in implementation of different modulation schemes. Also, they are almost ubiquitously used in transceivers to improve the overall linearity and dynamic range. In this chapter, first different types of variable-gain amplifiers (VGAs) are reviewed. Then the design of the proposed VGA is presented. Next, the multiplexer structure that is used to choose the desired phase is explained, followed by a discussion on the design of the combined multiplexer and VGA.  4.1.  Overview  In previously reported VGA designs, gain-control mechanisms are typically achieved by using ladder attenuator [77], variable transistor transconductance (gm) [78], current splitting [79], feedback triode region transistor [80], and adding cascade transistor, variable load resistor, and current steering [81]. As shown in [77] and [80] attenuator and feedback transistor introduce high loss in mm-wave range. The current splitting topologies, developed by K. L. Feng et al. [79], are not suitable for low power mm-wave applications, because of their narrow gain control range and high loss in mm-wave range. Among these variable-gain mechanisms, the topology proposed in [81] has the advantages of wide and linear gain control range, low dc power, as well as simple topology, and thus is suitable for high-frequency design.  From the amplifier design point of view, different CMOS amplifier topologies such as common-gate (CG), common-source (CS), and cascode are utilized and implemented for millimeter-wave receivers including 60 GHz band [83]. The schematics in Figure 4-1 show 79  the CS, CG, and cascode amplifiers. The common-gate structure provides a wideband input matching with good reverse isolation. However, the CG noise figure is larger than the noise figure in the CMOS CS or cascode amplifiers. Compared to the CS or CG topologies, the cascode topology is more stable. Higher gain can be achieved in cascode topology, but the noise figure is higher due to the additional noise introduced by the cascode transistor. In fact, the cascode topology can be considered as cascaded combination of CS and CG stages.  Figure 4-1: Different CMOS amplifier topologies (a) common source (b) common gate (c) common gate cascode amplifiers.  As mentioned before, different VGA topologies that have been investigated in the literature. One way to control the gain (i.e., gm) is by changing the bias current of the transistor, as shown in Figure 4-2(a). Reducing the tail current lowers the gm of the differential pair and consequently the gain of the stage. Reducing the tail current source causes the voltage drop across the load to decrease and thus changes the output common-mode voltage. To compensate this voltage change, additional current can be passed through the load (shown as 80  IAGC/2 in Figure 4-2(a)) [82]. A drawback of this technique is that the maximum input voltage for linear operation is reduced with the reduction in the gain, which results in the lowest gain setting for the largest input signal. Another approach is to change gm via reducing the drainsource voltage by adding cascode transistors (see Figure 4-2(b)). The gate voltage of the cascode transistors, VAGC, controls the gain. By not changing the tail current, the output common-mode voltage remains constant and the output dynamic range is less sensitive to the gain setting.  Figure 4-2: Four methods of controlling of gm (a) by changing the bias current (b) by adding the cascade transistor (c) a variable load and (d) a variable series feedback [82].  81  The third method is to change the load resistance. Since the gain of an amplifier stage is approximately equal to RLgm, varying RL changes the gain. In order to achieve a constant input range, one can use a differential variable load, as shown in Figure 4-2(c). A technical problem with this approach is the change of resistor over process (variations) which should be compensated for carefully. Figure 4-2(d) shows a differential pair with series feedback provided by the variable source degeneration resistor, RAGC. In this example, the tail current Io is split in two halves; a single tail-current source could be connected to the midpoint of RAGC. This stage has an approximately constant bandwidth, a constant output common-mode voltage, however, its dynamic range as the gain increases needs to be improved.  4.2.  VGA Design  In the proposed VGA design, a current steering mechanism is adopted to achieve wide and linear gain control range [81]. The unit gain control cell is illustrated in Figure 4-3. M1 and M2 are combined as a cascode device and M3 is used for gain control. To explain the variable-gain behavior, a simple analysis is given in [81] by Gopinathan et al. for calculating the current and transconductance of transistor M2. The current passing through M2, i.e., im, can be expressed as:    2 1 1  k1 (VG 2 − VC1 ) im ≅  +  io  2 4 I o − 1 k1 (VG 2 − VC1 )2  4    (4-1)  where Io is the current of transistor M1, k1 is the transcunductance parameter and is equal to  µ n (W L ) 2 C ox . The transconductance of the current steering gain amplifier cell, Gm, can be express as: 82  Gm =  di m dV in    2 1 1  di o k 1 (V G 2 −V C 1 ) ≅ +   2 4 I o − 1 k 1 (V G 2 −V C 1 )2  dV in 4     2 1 1 k 1 (V G 2 −V C 1 ) = +  2 4 I o − 1 k 1 (V G 2 −V C 1 )2  4     g m1    (4-2)  where gm1 is the transconductance of M1. The dc current Io remains constant during the application of gain control bias when M2 and M3 are operating in the active region. The current im is controlled by the gain control bias (VC1) based on equation (4-2), while Gm and the smallsignal gain of the VGA are controlled by im.  Figure 4-3: The current steering gain amplifier cell.  To achieve the maximum gain performance, appropriate channel width to length ratio (W/L) for the transistors should be chosen.  In the high-gain mode, the gate voltage VC1 of the gain control transistor, M3, is biased below the threshold voltage to keep it off. While the gain control transistor is off, im = io. The current 83  im flows through the CG and CS transistors (M2 and M1) which are biased in active region so that the VGA is operating in the high gain mode. When VC1 of the gain control transistor goes high, M3, is turned on. According to equation (4-2), as VC1 increases the transconductance (Gm) decreases, and thus the gain of the current steering gain amplifier cell decreases. To ensure that the CG transistor can be turned off, i.e., im = 0. The size of the gain control transistor is selected to be larger than that of the CG transistor. All networks are conjugate matched to achieve the maximum gain.  4.3.  Multiplexer  Each SWO stage is loaded with an output buffer (shown in Figure 4-4) to isolate the oscillator core from a differential 8-to-1 multiplexer. The multiplexer is implemented in two stages; the first stage is a 4-to-1 multiplexer implemented with four differential pairs and NMOS cascode transistors. The second stage is a 2-to-1 multiplexer to select the differential output phase. To drive the 50-Ω output impedance, the phase selector output is buffered by a differential 50-Ω driver.  As previously mentioned, all eight phases of the LO should be accessible separately. In order to minimize the complexity of the phase-selection circuitry, the appropriate phase of the LO for each path is selected in two steps. The idea is to sense multiple phases by means of differential pairs, choosing each pair by non-overlapping pulses. As a result, the output signal is equal to one of the input pairs at the time. Initially, an array of four differential pairs (M1M2) with switchable transistors (M3-M4) at the load of each 2-to-1 multiplexer and a shared tuned load (λ/4 transmission line) are used to select one of the four output pairs of the oscillator by using one of the select bits (sel[0:3]) (Figure 4-4(a)). 84  Figure 4-4: The 8-to-1 BiCMOS multiplexer.  The designed multiplexer for the first chip is as shown in Figure 4-4(a) which is designed and fabricated in a BiCMOS technology. For the second chip, the entire transmitter circuit is implemented in a CMOS technology and all BJT transistors are replaced by CMOS transistors.  In the basic mode of operation, at any given time, one of the LO phases is fed to the output of the main analog multiplexer, while other phases are fed to the output of the unused multiplexer. In the next step, a 2-to-1 multiplexer selects the sign bit (Figure 4-4(b)), resulting in complete access to all LO 8 phases by choosing either the select bit number 4 or 5. The above-mentioned configuration reduces the necessary number of phase selectors (i.e., differential pairs in our case) from 23 to 22+2 for each path. Adding a cross-coupled differential pair at the output of the multiplexer can partially cancel the loss associated with the transmission line outputs at the expense of higher power consumption. Phase interpolation 85  can be achieved by turning on more than one switch transistor at any given time, forcing the output to be the sum of all the turned-on phases. A first-order interpolation can be achieved by turning two adjacent paths ON simultaneously, doubling the phase resolution. Thus, there is a possibility of getting more phases than the eight original phases produced by the LO.  Figure 4-5: The 8-to-1 BiCMOS multiplexer layout.  The layout of the multiplexer is shown in Figure 4-5. The 4-to-1 multiplexer is drawn on top to fit interior of the RWO to save area. All the lines drawn from 4-to-1 multiplexer to the 2-to1 multiplexer are modeled by transmission lines to make sure of the required frequency operation.  86  A number of simulations have been done on the designed polar oscillator in Cadence. Applying two different control gate voltages to the current steering transistor, two levels of gain are achievable for each VGA cell as shown in Figure 4-6 (note that for VGA with two such stages in cascade for levels of gain are achieved). If needed (e.g., for higher-order QAM systems), more levels of gains can be achieved by changing the control voltage of the VGA.  Figure 4-6: Post-layout simulation for on VGA cell.  As a proof-of-concept, a 16-QAM polar transmitter (four-level gain) is implemented. To apply different gains on each phase, a current steering gain structure (M5 - M6) is added to the multiplexer to make a combined multiplexer and variable-gain amplifier (see Figure 4-7). By choosing different values for VC1 and VC2, different levels of gain are applied to the output signal.  4.4.  Summary  This chapter is started with a brief explanation on different VGA structures followed by the multiplexer structure. Also it is explained how the combined structure of VGA and multiplexer is used in this research. The multiplexer is implemented in BiCMOS for the first 87  fabrication and all in CMOS for the second fabrication (Figure 4-7). The high gain benefit of using BJT is given in the price of more integration. The effort to reduce the number of transistors is taken to decrease the total noise of CMOS multiplexer.  Figure 4-7: 8-to-1 multiplexer including a 4-to-1 to select one of the four differential output of the oscillator, and a 2-to-1 multiplexer to select the sign.  88  CHAPTER 5 : MEASUREMENT RESULTS 5.1.  Overview  In this chapter, the measurement results of the two chips designed and fabricated during the course of this research are presented. The first chip, explained in Chapter 3, is designed in a BiCMOS technology and includes the proposed RWO oscillator and an 8-to-1 multiplexer. It operates at 45 GHz, providing eight different phases. To implement the entire polar transmitter plus improving the level of integration and adding more functionality, the transmitter (shown in Figure 5-1) is designed and implemented in a 0.13µm CMOS technology.  Figure 5-1: 16-QAM polar transmitter.  The second chip extends the first chip by adding the VGA block to the circuit and also included the improvements mentioned in Chapter 3: increasing the frequency range of operation up to 5.2 GHz which is desired for 60 GHz technology. The entire polar transmitter  89  circuit based on the components discussed in the previous chapters is shown in Figure 5-1. It includes the proposed RWO and a combined 8-to-1 multiplexer with a 4-level-gain VGA.  The proposed RWO has been already explained. The distributed nature of the oscillator absorbs transistor parasitic capacitances into transmission lines. As shown in Figure 5-2, each SWO stage is effectively injection locked to the neighboring stage such that the overall structure behaves as a single oscillator.  Figure 5-2: Multi-phase rotary wave oscillator.  As the phase noise of the oscillators is one of their most important characteristics, in comparison with the designed oscillator in BiCMOS, the following techniques are used to improve the phase noise, phase error, and tuning range of the CMOS VCO.  To minimize the phase noise, a transmission-line-based filter (Tf along with parasitic capacitance at the source of M1 and M2, shown in Figure 5-3 (a) which resonates at 2ωo is 90  added in the common node of the differential pair to attenuate the second-order harmonic. This filter significantly improves the phase noise of the CMOS SWO [84]. The capacitor (Cf) is added to provide a low impedance path to minimize the effect of the thermal noise of the tail transistor around 2ωo. This component of the noise contributes to phase noise when the oscillator mixer-based structure down-converts it to ωo [84].  Figure 5-3: Standing-wave oscillator (a) architecture, and (b) small signal model.  91  Although there are techniques for phase mismatch calibration in rotary-wave oscillators [69], applying such techniques to mm-wave oscillators is more challenging due to the adverse effects of parasitic capacitances on the frequency of operation. In this work, each oscillator is separately controlled to oscillate at the desired frequency and as will be shown later, a phaseoffset calibration technique is applied to the last stage of the 2-to-1 multiplexer to compensate for device mismatches.  To achieve a wide tuning range, both coarse and fine tuning methods are used to cover multiple overlapped tuning sub-bands and thus covering the desired frequency range [85][86]. Figure 5-3 illustrates the designed multi-phase SWO VCO with both coarse and fine tuning circuits to cover a 5.2 GHz tuning range. An accumulation-mode varactor (Figure 5-5 (a)) is used to provide the fine tuning. For coarse tuning, the switching capacitor technique is used to achieve four overlapping frequency ranges (using control bits Bo and B1). Previous designs with similar RWO structure [87] have focused on fine tuning which has resulted in design trade-offs between the quality factor (Q), phase noise, and the tuning range. The Q of the varactor has a great impact on the total phase noise of the oscillator. To maximize the varactor Q (which in turn limits the tuning range of the oscillator), the minimum length varactors should be used because the varactor resistance (Rv ∝ L/W) and capacitance (Cv ∝ WL) are directly proportional to the length of the varactor. Based on simulations, reducing the effect of the parasitic resistor of the varactor, using a number of small varactors in parallel is better than using a large varactor.  To provide an intuitive explanation for this statement, note that a varactor is typically implemented as shown in Figure 5-5 (a). As the n-well material has a high resistivity (shown 92  in Figure 5-4), the series resistor of the varactor with the reversed-biased diode lower the quality factor of the capacitor.  Figure 5-4: Varactor realized in CMOS technology [47].  Figure 5-5: (a) Varactor and (b) switched capacitor.  In the context of capacitor switching, it is important to consider all parasitic capacitors associated with each switch. As shown in Figure 5-5 (b), the maximum and minimum value for the switched capacitor is changing between Ct when Vctrl is ON and (Cdb,Ms+ Cgd,Ms) when Vctrl is OFF.  The parasitic capacitances contributing to the output capacitance are (shown in Figure 5-3 (b)) the drain-bulk capacitance; Cdb, gate-source capacitance, Cgs, and gate-drain overlap capacitance, Cgd, which is enhanced due to the Miller effect. Additionally, the output buffer differential capacitance, Cbuff, loads the tank. The desired frequency tuning range is achieved 93  through tuning the varactor and its parasitice, Cvar and Cpar. An equivalent differential capacitance for the tank circuit for the fine tuning is  Cequ = Cvar + C par + Cdb + C gs + 4C gd + Cbuff  (5-1)  A large tuning range requires minimizing the capacitances that are not contributed by the varactor and suggests using smaller devices. However, a minimum transconductance, gm, is required to overcome the tank losses due to the transmission line quality factor, QTL, and capacitance quality factor, QC. Also, for the coarse tuning capacitance, shown in Figure 5-5  (  (b), the two different values of Ct + Cgd , Ms2 + Cdb, Ms2  )  (  and 2Ct + Cgd , Ms1 + Cdb, Ms1  ) should be  considered when the MS1 is ON and MS2 is OFF and vice versa, respectively.  5.2.  16-QAM Transmitter Chip Implementation  The circuit is designed and laid out in an eight metal layer 0.13-µm CMOS process. The circuit includes the proposed rotary-wave oscillator, a phase selector, a VGA, and a 50-Ω output buffer. The die micrograph of the transmitter circuit is shown in Figure 5-6, which occupies a total of 0.9 mm × 1 mm. This includes the GSG high-frequency probe pads, three sets of DC probe pads, and the 50-Ω output buffer. The active area of the RWO including the buffers between oscillator and phase selector is 500 µm × 500 µm. It should be noted that the phase selector (4-to-1 multiplexer) and two levels of gain for VGA are placed inside the RWO to allow symmetric loading of each SWO and saving the area.  Since this chip is designed to operate at 60 GHz, however, the spectrum analyzer (E4448A) available to us is working up to 50 GHz. Therefore, to be able to test the chip, it is required to use a down-conversion mixer. For measuring the loss of the down-conversion mixer, a PSA 94  spectrum analyzer is used along with a signal generator. The connections are done with SMA cables and 1.85-mm cable as shown in Figure 5-7.  Figure 5-6: Chip die photograph.  Figure 5-7: Down-conversion mixer characteristic measurement.  To measure the total losses of the mixer and cable, the RF input amplitude is swept for a range of frequencies and the 1-dB compression point has been measured. Cadence SpectreRF is used to design and simulate the proposed circuit. A transient simulation of the RWO is plotted in Figure 5-8 which shows the output waveforms at all eight different phases of the RWO. These outputs are 45° apart from their adjacent outputs. Figure 5-9 shows the output spectrum of the transmitter. The measured output at the frequency of 67 GHz is equal to -32.5 dBm, excluding  95  the RF cable loss, the mixer conversion loss, and 1.5 dB loss of the probe, the RF signal level at the input of the mixer is equal to −15.5 dBm.  Figure 5-8: Post layout simulated outputs of RWO.  Figure 5-9: Output spectrum of the polar transmitter.  Figure 5-10 shows four levels of coarse tuning that are achieved by changing the switching capacitor block control bits from 00 to 11. Then by continuous change of the varactor, the frequency is adjusted. By this tuning, the 5.2 GHz of tuning range is achieved. Also on each coarse tuning step, the amplitude of the output will change mostly by 2.3 dBm.  96  Figure 5-10: Measurement tuning range for transmitter output.  Figure 5-11: Output phase noise measurement at 67 GHz.  Figure 5-11 shows the measured phase noise spectrum. At 67 GHz, the measured phase noise is -82.26 dBc/Hz and -93.49 dBc/Hz at a 1MHz and 10 MHz offset, respectively. By excluding the phase noise of the external mixer (i.e., -14 dBc/Hz), the actual phase noise of the oscillator is -96 dBc/Hz (-106.49 dBc/Hz) at 1 MHz and 10 MHz offsets, respectively. The polar transmitter operates from a 1.2 V supply and draws 30 mA current. The oscillator core consumes 14 mW. By changing the VC1 and VC2, the output amplitude level can be changed for 4 levels of gain to form a 16-QAM constellation by turning ON and OFF the current-steering transistors as control bits from 00 to 11. 97  The error-vector magnitude of the modulator is calculated through:  EV M =  1 N  N  ∑ (V ) 2  e  j =1  (5-2)  . m V  where Ve is the magnitude of the error vector for each symbol, Vm is the magnitude of the desired symbol vector, and N is the number of measurements. From comparing the ideal amplitude and the measured magnitude of the output spectrum, there is an error of -27.5 dB which is acceptable based on the IEEE 802.11a standard [28].  5.3.  Summary  In this chapter, the measurement results for the 0.13-µm CMOS 67 GHz rotary-wave oscillator along with post layout simulations for 16-QAM polar transmitter are presented. The experimental results show that the oscillator achieves a 5.2-GHz tuning range (8%) and consumes 36 mA from a 1.2-V supply. The measured phase noise at 67 GHz is −96 dBc/Hz (−106.49 dBc/Hz) at 1 MHz (10 MHz) offset. This phase noise difference shows that the measured and post-layout simulated phase noise of the oscillator match well. Also, the EVM is -27.5 dB. The performance comparison of microwave oscillators in CMOS process and the post-layout simulation results of the polar transmitter are shown in Table 5-1 and Table 5-2, respectively.  98  Table 5-1: Performance comparison of microwave oscillators in CMOS processes.  Paper #  [69]  [88]  This Work  Technology (nm)  130  90  130  Frequency (GHz)  59  58  67  Tuning Range (GHz)  13.9  5.2  5.2  Phase Noise @ 1MHz (dBc/Hz)  -108  -91  -96  Power Consumption (mW)  132  8.1  14  Area (mm2)  0.17  0.07  0.3  Table 5-2: Transmitter post-layout simulation performance.  Parameters  Transmitter Simulation  Technology (nm)  130 CMOS  Frequency (GHz)  67  Tuning Range (GHz)  5.2  Phase Noise @1MHz (dBc/Hz)  -96  Power Consumption (mW)  43.2  Modulation data rate  16-QAM - 2.5Gb/s  99  CHAPTER 6 : CONCLUSIONS AND FUTURE WORK This chapter summarizes the contributions of the research. Furthermore, the limitations of the work and avenues for future research are discussed.  6.1.  Research Summary and Contributions  The growing demand for higher-rate wireless data transfer (e.g., gigabit wireless Ethernet) has resulted in a plethora of research activities in transceiver design for mm-wave bands where relatively less populated spectrum with larger bandwidths are available [1][91][98]. For example, the available 7-GHz spectrum in the unlicensed 60-GHz band provides sufficient bandwidth for high-data-rate applications such as gigabit wireless Ethernet, video distribution through mobile devices and content exchanging of compressed/uncompressed streaming data [92]. Point-to-point streaming video links for high-definition multimedia interface (HDMI) replacement have already been demonstrated at 60 GHz [1].  Mobile devices require low power consumption, placing the emphasis on energy-efficient circuits. However, modulation formats such as quadrature amplitude modulation (QAM) and orthogonal frequency-division multiplexing (OFDM) that are commonly used in high-data rate systems require more stringent phase-noise requirement (below -90 dBc/Hz @ 1MHz) for reliable operation in the 60-GHz band [96]. Unfortunately, there is a trade-off between low phase noise and low power consumption [62], [96]. Phase noise also tends to degrade with the wider tuning range required for robustness to process, voltage, and temperature variations [100]. Furthermore, for QAM-type schemes, multiphase local oscillators (LOs) facilitate frequency conversion of in-phase and quadrature RF signals. 100  In this work, a new architecture for a low phase noise, low power, and multi-phase oscillator is developed which hybridizes standing- and rotary- wave oscillators suitable for high-data-rate applications. This structure has been chosen to take advantage of both the low phase noise of SWO and the multi-phase accessibility of the RWO with the high Q transmission line structure. During the course of this research, two proof-of-concept prototype chips are designed, fabricated and successfully tested. As a proof of performance, a mixer-less architecture for a polar transmitter is developed in CMOS technology.  The oscillator structure is suitable for generating the multi phases required in high data rate applications (for example, in the 16-QAM structure discussed in this thesis, eight different phases, 45° apart, are used). Once a wave becomes established, it takes a small amount of power to sustain it. The travelling-wave oscillator is tapped with standing-wave oscillators to sustain the wave travelling along the transmission line ring. Also, this architecture is very promising for low-phase noise systems, as any noise perturbation will be averaged out along the transmission-line ring and will result in a lower phase noise.  As a proof of concept a 16-QAM transmitter is designed and simulated (shown in Figure 6-1). The mixer-less structure has been chosen to avoid/minimize the problems associated with the mixer based transmitter. The rotary-wave oscillator is employed to provide both low power and low phase noise outputs. An 8-to-1 multiplexer along with two variable gain amplifiers (VGAs) is used to provide four different levels of gain to achieve the 16-QAM constellation.  In a Cartesian architecture, the complex output is encoded with band-limited I and Q vectors. Other issues with Cartesian transmitters are LO leakage, LO pulling, and imbalance of the  101  quadrature LO signals. On the other hand, mixer-less polar transmitters are dealing with amplitude and phase with wideband spectral properties desired in 60 GHz design.  Figure 6-1: 16-QAM polar transmitter using the proposed RWO.  The first fabricated chip includes a 45-GHz rotary-wave oscillator and is fabricated in a 0.13-µm BiCMOS technology. The phase-noise analysis predicts a maximum phase-noise reduction of 15.5 dB due to the coupling behavior in respect to non-coupled single oscillator. The oscillator draws 16 mA from a 1.2-V supply. The measured phase noise of the 45-GHz RWO is -93 dBc/Hz at 1-MHz offset. This oscillator provides a 2.9-GHz tuning range with eight outputs 45° apart. In addition to chip implementation, a comprehensive analysis on the phase noise of the oscillator has been provided.  In the second chip, a 67-GHz tunable rotary-wave oscillator is implemented in a 0.13-µm CMOS technology. The experimental results show that the oscillator achieves a 5.2-GHz 102  tuning range (8%) and consumes 14 mW from a 1.2-V supply. The measured phase noise at 67 GHz is −96 dBc/Hz (−106.49 dBc/Hz) at 1 MHz (10 MHz) offset.  As an application of the proposed oscillator, a 67 GHz circular-QAM transmitter topology is presented and a prototype 16-QAM system is designed and simulated in the same 0.13-µm CMOS technology. The polar transmitter draws 36 mA from a 1.2-V supply. The transmitter consumes 2 to 4× less power as compared to the other state-of-the-art 60-GHz transmitters with similar noise performance. Using a VGA, the 4-levels of output amplitude levels are achieved to form the 16-QAM constellations. Post layout simulation results show a phase noise of −98 dBc/Hz at 1 MHz. This phase noise difference shows that the measured and postlayout simulated phase noise of the oscillator is in excellent agreement. Also, the EVM is -27.3 dB.  6.2.  Limitations and Future Work  There are many interesting avenues to improve the proposed architecture and make it more accurate from both design and test point of views. High-frequency testing is always challenging, in particular measuring and capturing 60-GHz signals in the time-domain requires specialized high-speed oscilloscopes which unfortunately were not available during our testing period. Due to the lack of access to such oscilloscopes, it was not possible to measure and record the physical multi-phase outputs of the oscillator. However, the functionality of the oscillator and the frequency of oscillation of its outputs were measured using a spectrum analyzer. Also, due to the limited available chip area as well as high-speed probes, we were not able to include a pad to inject high frequency injection signal to the oscillator for measuring its locking range. 103  Furthermore, based on the work done in this research and from a survey of recent published data, new directions for further research have surfaced that would expand the scope and impact of the limitations and future the work. Some of these ideas are discussed in below:  1) Use the proposed oscillator in a phase-locked loop (PLL) (shown in Figure 6-2) or use an injection signal to enhance the performance of the oscillator. Although these approaches have been confirmed by simulations, verification via testing would be valuable.  Figure 6-2: PLL circuit for proposed oscillator.  2) Amplitude variation can deteriorate the oscillator operation and consequently the transmitter performance, in particular in high data rate applications. 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Meyer, “A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, 2005, pp. 909–917. [101] S. Emami, C. H. Doan, A. M. Niknejad, and R. W. Brodersen, “A 60-GHz down-converting CMOS single-gate mixer,” IEEE Radio Frequency integrated Circuits (RFIC) Symposium, 2005, pp. 163 – 166. [102] B. Razavi, “A 60-GHz CMOS receiver front-end,” IEEE Journal of Solid-State Circuits, vol. 41, no. 1, 2006, pp. 17 – 22. [103] R. E. Amaya and C. J. Verver, “A 60 GHz CMOS balanced downconversion mixer with a layout efficient 90° hybrid coupler,” IEEE Custom Integrated Circuits Conference, 2009. [104] P. Sakian, R. Mahmoudi, P. v. Zeijl, M. Lont and A. Roermund, “A 60-GHz double-balanced homodyne down- converter in 65-nm CMOS process,” Proceedings of the 4th European Microwave Integrated Circuits Conference, 2009.  112  Appendix: Double-Balanced Down-conversion CMOS Mixer with On-Chip Balun for 60-GHz Receivers Down-conversion mixers, being responsible for translating the input RF signal to an intermediate frequency (IF), are one of the key building blocks of almost all wireless receivers. In the context of spectral analysis and measurement, they can be used to downconvert a high-frequency signal to a frequency that is within the frequency range of the measurement instrument, e.g., a spectrum analyzer. In this research, although we eventually used the mm-wave measurement instruments available to us through CMC Microsystems Testing Collaboratory to test the 60-GHz oscillator designed in the course of this research, we also designed a 60-GHz down-converter mixer to have the opportunity to test the oscillator using the 27-GHz spectrum analyzer available at UBC SOC lab. Furthermore, such mixer can be used in a dual-conversion, RF phase- shifting array architecture. In this appendix, we present the design of such a mixer whose design requirements are low noise, high linearity, large LO-to-RF and LO-to-IF isolations, and moderate conversion gain.  A. Mixer Design To achieve low noise figure (NF) performance and high SNR in the overall system, the 60GHz mixer structure is chosen to be differential. The double-balanced structure in Figure A-1 provides a better LO-to-RF isolation compared to the single-gate mixers [101] or singlebalanced mixers [102]. The LO-to-RF isolation is crucial for the successful performance of the 113  overall receiver especially in direct-conversion receivers or for the cases where the front-end has some gain at the LO frequency.  Figure A-1: 60 GHz double-balanced mixer with two passive baluns.  Also, the linearity can be improved by increasing the gate overdrive voltage. The transconductance stage transistor can be operated in strong inversion if a sufficient overdrive is obtained. The trade off in improving the linearity is to lowering the conversion gain.  The down-converting mixer in the proposed architecture provides a reasonable gain over the IF center frequency range of 11.4 to 12.8 GHz. It is needed to provide at least 2-GHz bandwidth (typical channel bandwidth) around the center frequency. For this purpose, a tunable filter shown in Figure A-1 is implemented to provide the wideband output. A varactor 114  is employed to provide tuning for the IF output frequency. Inductive load is used for higher conversion gain and increased headroom. At the resonant frequency of the tank, the gain becomes gmRF (gm is the transconductance of the input transistor, and RF is the total resistance of the output tank). As mentioned in [84], CN and TN are added to improve the noise figure of the overall mixer.  Two passive baluns (Figure A-2) are used to provide single-ended to differential conversion at the RF and LO inputs of the mixer. The balun has a relatively small footprint at mm-wave frequencies (83 × 83 µm2) and is implemented in the top two metals (MA as signal layer and E1 as the ground layer). Metal width, spacing, number of turns and sizing are all optimized to provide low insertion loss and maximum voltage swing at the output port by using HFSS.  Figure A-2: 60 GHz passive balun.  B. Simulations and Measurement Results The mixer is fabricated in a 0.13-µm CMOS technology that has 8-metal layers (3 thin, 2 thick copper layers and 3 RF layers). An output buffer using the shunt peaking technique is implemented in order to drive the 50-Ω load of the measurement instruments. The measured results presented in this section reflect the performance of the mixer and the subsequent 115  buffer. For these measurements (Figure A-3) DC probes, 5C2CR probe, 5D25X probe, and Agilent E4448A PSA spectrum analyzer are used.  Figure A-3: The measurement setup.  Figure A-4: Die micrograph of mixer chip including the PADs, buffer, and baluns.  The die micrograph of the fabricated mixer is shown in Figure A-4. The overall system, including the two on-chip baluns, test PADs, mixer and the buffer, occupies an area of 1100 × 746 µm2. Electro-static-discharge (ESD) protection has been added to all PADs. To  116  report the chip measurement results, the losses associated with the probes and interconnect cables should be excluded from the measured results.  Figure A-5 shows the spectrum of the mixer IF output (black curve). The output at the frequency of 12.2 GHz is equal to −44 dBm. By excluding the 7.2 dB loss of the IF cable and 1.5 dB loss of the probe, the output power at the IF of 12 GHz is equal to −35 dBm.  Also, at the RF port, excluding 15 dB loss of the RF cable and 1.5 dB loss of the probe, the RF signal level at the input of the mixer is equal to −36.5 dBm. Therefore, the conversion gain of the mixer is equal to 1.5 dB. Considering all the losses at the LO port the input LO signal is 1.5 dBm. Based on the measurement results, the IF output covers a 2.3 GHz bandwidth. The center frequency of IF can also be tuned by the varactor (gray line in Figure A-5).  Figure A-5: The measured output spectrum at IF which can be tuned by the employed varactor over the IF band.  Figure A-6 depicts the interpolated measured (diamonds are measured points) conversion gain variation over the IF frequency range. As shown on this figure, the IF bandwidth is about 2.3 GHz. The simulated IIP3 of this mixer by applying the same amplitude of RF and LO as 117  the measurement situation, is equal to 14.2 dBm. Moreover, the mixer core works from a 1.5V voltage supply and consumes 6 mW. The buffer operates from a 1.3-V supply and consumes 7.8 mW. The overall chip including the buffers consumes 13.8 mW. Performance summery and comparison with recent work on mm-wave mixers are provided in Table A-1.  Figure A-6: Measured conversion gain by sweeping LO and RF frequency by excluding the cable and probe losses.  C. Conclusion In conclusion, in the Appendix, the design of a 0.13-µm CMOS 60-GHz down-converting double-balanced mixer is presented. The designed mixer shows 1.7 dB of conversion gain at LO level of 1.5 dBm over the 2.3 GHz bandwidth at IF frequency. The IIP3 of 14.2 dBm has been simulated for the mixer. The total chip power consumption is equal to 13.8 mW, where the mixer core and buffer consume 6 mW and 7.8 mW respectively  118  Table A-1: Comparison with recent work on mm-wave mixers.  [101]  [103]  [104]  This Work  Topology (CMOS)  0.13µm  0.13µm  65nm  0.13µm  LO-to-RF isolation(dB)  36  17.6  --  > 30dB  Lo-to-IF isolation(dB)  -  24.3  --  > 40dB  Conversion gain  2  0.3  2  1.7  IIP3 (dBm)  -8  --  -6  14.2  Noise Figure  -  10.8  15  13  LO Power (dBm)  -  0.5  --  1.5  Paper #  119  

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