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A DSP based AC electronic load for unintentional islanding tests Feng, Wei 2009

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A DSP-based AC Electronic Load for Unintentional Islanding Tests by Wei Feng B.Sc., Tsinghua University, Beijing, China, 2004 M.Sc., Institute of Electrical Engineering, CAS, China, 2007 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in The Faculty of Applied Science (Electrical and Computer Engineering) THE UNIVERSITY OF BRITISH COLUMBIA (Vancouver) August 2009 c© Wei Feng 2009 Abstract The distributed generation (DG) system for the renewable energy resources is being used more and more widely around the world in the past decades. In order to protect the whole power system from the islanding situation, the interface inverters of the DG system have to pass the unintentional islanding test. In this study, a single phase AC electronic load is introduced to simulate the local loads under unintentional islanding conditions. This thesis proposes a proper schematic of the electronic loads based on the H-bridge dc-dc converter and analyzes the performance of this system with PowerSIM. Then, a set of specifications for different ranges of the electronic loads are calculated through theoretical formulas and the PSIM simulations. Meanwhile, the transfer function of the system is also derived to analyze the stability of the PI control system. According to the theoretical analysis and simulations, a control program is implemented based on the Texas Instruments (TI) Digital Signal Processor (DSP) TMS320F2407A for the different kinds of electronic loads. A test circuit is then built to validate the performance of the system. Some experiments are performed for the resitive, inductive and capacitive loads respectively. ii Table of Contents Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 Project Background . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.1 Unintentional Islanding Test Scheme . . . . . . . . . 3 1.2.2 AC Electronic Loads for Unintentional Islanding Test 4 1.3 Thesis Objective . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Principles of the Simulated Loads . . . . . . . . . . . . . . . 6 2.1 Schematic of Electronic loads . . . . . . . . . . . . . . . . . . 6 2.1.1 H-Bridge Bidirectional Current Source . . . . . . . . 7 2.1.2 The Range of Inductor Current . . . . . . . . . . . . 8 2.2 AC Small-Signal Modeling and PI Control Method . . . . . . 9 2.2.1 AC Small-Signal Model . . . . . . . . . . . . . . . . . 10 2.2.2 The Transfer Function of Control System . . . . . . . 11 2.2.3 Control System Stability Analysis . . . . . . . . . . . 12 2.3 System Performance Analysis . . . . . . . . . . . . . . . . . . 13 2.3.1 Current Ripple . . . . . . . . . . . . . . . . . . . . . . 13 2.3.2 Relationship between Response Time and Zsim . . . . 17 2.3.3 Conclusions of System Performance . . . . . . . . . . 17 2.4 Calculation of Circuit Parameters . . . . . . . . . . . . . . . 18 2.4.1 Introduction of PSIM Simulation Diagram . . . . . . 18 2.4.2 DC Bus Voltage: Vdc . . . . . . . . . . . . . . . . . . 19 iii Table of Contents 2.4.3 Series Resistor: R1 . . . . . . . . . . . . . . . . . . . 19 2.4.4 Switching Frequency: fpwm . . . . . . . . . . . . . . . 20 2.4.5 Inductor: L . . . . . . . . . . . . . . . . . . . . . . . 20 2.4.6 Calculation of the Range of Zsim . . . . . . . . . . . . 22 2.4.7 Duty Ratio D . . . . . . . . . . . . . . . . . . . . . . 25 2.4.8 Specifications of Electronic Loads . . . . . . . . . . . 27 2.5 Simulations of Electronic Loads . . . . . . . . . . . . . . . . 28 2.5.1 Resistive Load Simulation . . . . . . . . . . . . . . . 28 2.5.2 Inductive Load Simulation . . . . . . . . . . . . . . . 32 2.5.3 Capacitive Load Simulation . . . . . . . . . . . . . . 35 3 Hardware Implementation . . . . . . . . . . . . . . . . . . . . 36 3.1 Introduction of System . . . . . . . . . . . . . . . . . . . . . 36 3.2 IGBT Inverter Module . . . . . . . . . . . . . . . . . . . . . 37 3.3 IGBT Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . 38 3.4 Voltage Measuring Circuit . . . . . . . . . . . . . . . . . . . 41 3.5 Current Measuring Circuit . . . . . . . . . . . . . . . . . . . 44 3.6 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . 45 3.7 Protection Circuits . . . . . . . . . . . . . . . . . . . . . . . 46 3.8 DSP Control Board . . . . . . . . . . . . . . . . . . . . . . . 47 3.9 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4 Software Implementation . . . . . . . . . . . . . . . . . . . . . 49 4.1 Program Overview . . . . . . . . . . . . . . . . . . . . . . . . 49 4.2 Variables Normalization . . . . . . . . . . . . . . . . . . . . . 51 4.2.1 Q Format . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2.2 Normalization of Voltage and Current . . . . . . . . . 51 4.3 System Initialization . . . . . . . . . . . . . . . . . . . . . . . 52 4.3.1 Event Manager Modules Initialization . . . . . . . . . 52 4.3.2 ADC Module Initialization . . . . . . . . . . . . . . . 53 4.3.3 I/O Ports Module Initialization . . . . . . . . . . . . 54 4.4 Interrupt Service Routine (ISR) . . . . . . . . . . . . . . . . 54 4.5 Generation of Sine Wave . . . . . . . . . . . . . . . . . . . . 55 4.6 Digital PI Control . . . . . . . . . . . . . . . . . . . . . . . . 57 4.7 RLC Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 58 5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 61 5.1 Experimental Conditions . . . . . . . . . . . . . . . . . . . . 61 5.2 Resistive Load Results . . . . . . . . . . . . . . . . . . . . . 62 5.2.1 The Range of Resistance Loads at L = 2.6mH . . . . 62 iv Table of Contents 5.2.2 Switching Frequency and Current Ripple . . . . . . . 64 5.2.3 Series Inductor L and Current Ripple . . . . . . . . . 65 5.3 Inductive Load Results . . . . . . . . . . . . . . . . . . . . . 67 5.4 Capacitive Load Results . . . . . . . . . . . . . . . . . . . . 69 6 Conclusions and Future Work . . . . . . . . . . . . . . . . . . 71 6.1 Synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3 Suggestions for Future Work . . . . . . . . . . . . . . . . . . 73 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Appendices A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 A.1 Schematics of Control Board . . . . . . . . . . . . . . . . . . 76 A.2 Schematics of Power Board . . . . . . . . . . . . . . . . . . . 81 A.3 PCB Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 B Schematics for 3-Phase Islanding Test . . . . . . . . . . . . . 89 C Unintentional Islanding Test Conditions . . . . . . . . . . . 91 v List of Tables 2.1 Inductor Values for the Resistive Simulated Loads . . . . . . 20 2.2 Inductor Values for the Inductive or Capacitive Simulated Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3 Inductor Values for the Inductive or Capacitive Simulated Loads (Rounding) . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4 Minimum Rsim for the Given Series Inductor . . . . . . . . . 25 2.5 Minimum Lsim (or Csim) for the Given Series Inductor . . . . 25 2.6 The Resolution of Rsim . . . . . . . . . . . . . . . . . . . . . 26 2.7 The Resolution of Lsim (or Csim) . . . . . . . . . . . . . . . . 27 2.8 Specifications for the Resistive Simulated Loads . . . . . . . . 28 2.9 Specifications for the Inductive or Capacitive Simulated Loads 28 3.1 Values of the dead times of RC networks . . . . . . . . . . . . 40 5.1 Comparisons of Current Ripple between Simulation Results and Experimental Results . . . . . . . . . . . . . . . . . . . . 64 5.2 Comparisons of Current Ripple at 20kHz . . . . . . . . . . . 65 5.3 Comparisons of Current Ripple at 20kHz . . . . . . . . . . . 66 vi List of Figures 1.1 Generic System for Unintentional Islanding Test . . . . . . . 3 1.2 Electronic Loads for Unintentional Islanding Test . . . . . . . 4 2.1 Diagram of Electronic Loads . . . . . . . . . . . . . . . . . . 6 2.2 Controllable Current Source with Regulated DC Bus Voltage 7 2.3 H-Bridge Inverter With Regulated DC Bus: Switching Status 8 2.4 Schematic Diagram of PWM Modulator . . . . . . . . . . . . 11 2.5 Block Diagram of the System Transfer Function . . . . . . . . 12 2.6 Bode Diagram of the Open-Loop Transfer Function . . . . . . 13 2.7 Resistance Load Simulation . . . . . . . . . . . . . . . . . . . 19 2.8 Unit Step Response at Rsim = 2p.u. . . . . . . . . . . . . . . 22 2.9 Voltage across Rsim = 2p.u. . . . . . . . . . . . . . . . . . . . 23 2.10 Unit Step Response at Rsim = 1p.u. . . . . . . . . . . . . . . 23 2.11 Voltage across Rsim = 1p.u. . . . . . . . . . . . . . . . . . . . 24 2.12 Unit Step Response at Rsim = 20p.u. . . . . . . . . . . . . . . 24 2.13 Relationship between Rsim and D . . . . . . . . . . . . . . . 26 2.14 Resolution at Rsim = 2000pu . . . . . . . . . . . . . . . . . . 27 2.15 Rsim = 0.5p.u. at fpwm = 20kHz . . . . . . . . . . . . . . . . 29 2.16 Current Ripple at Rsim = 0.5p.u. . . . . . . . . . . . . . . . . 29 2.17 Rsim = 1p.u. at fpwm = 20kHz . . . . . . . . . . . . . . . . . 29 2.18 Current Ripple at Rsim = 1p.u. . . . . . . . . . . . . . . . . . 29 2.19 Rsim = 2p.u. at fpwm = 20kHz . . . . . . . . . . . . . . . . . 30 2.20 Current Ripple at Rsim = 2p.u. . . . . . . . . . . . . . . . . . 30 2.21 Rsim = 2p.u. at fpwm = 20kHz . . . . . . . . . . . . . . . . . 30 2.22 Current Ripple at Rsim = 2p.u. . . . . . . . . . . . . . . . . . 30 2.23 Rsim = 20p.u. at fpwm = 20kHz . . . . . . . . . . . . . . . . 31 2.24 Current Ripple at Rsim = 20p.u. . . . . . . . . . . . . . . . . 31 2.25 fpwm = 10kHz, Rsim = 2p.u. and L = 2.6mH . . . . . . . . 31 2.26 Current Ripple at Rsim = 2p.u. and fpwm = 10kHz . . . . . . 31 2.27 Control Loop for Inductance Loads Simulations . . . . . . . . 32 2.28 Simulated Inductor Voltages at ‖Lsim‖ = 0.5p.u. and 1p.u. . . 33 vii List of Figures 2.29 Simulated Inductor Voltages at ‖Lsim‖ = 1p.u. and 10p.u. . . 34 2.30 Simulated Inductor Voltages at ‖Lsim‖ = 10p.u. and 100p.u. . 34 2.31 Current Ripple at Lsim = 1p.u. . . . . . . . . . . . . . . . . . 34 2.32 Current Ripple at Lsim = 10p.u. . . . . . . . . . . . . . . . . 34 2.33 Simulated Capacitor Voltages at ‖Csim‖ = 1p.u. and 10p.u. . 35 2.34 Simulated Capacitor Voltages at ‖Csim‖ = 10p.u. and 100p.u. 35 3.1 Hardware System of Electronic Loads . . . . . . . . . . . . . 36 3.2 Structure of IGBT Module . . . . . . . . . . . . . . . . . . . 37 3.3 Structure of IGBT Driver Module: 6SD106EI . . . . . . . . . 38 3.4 HalfBridge Mode Selection . . . . . . . . . . . . . . . . . . . . 39 3.5 Protection Circuit of Driver Module 6SD106EI . . . . . . . . 40 3.6 Voltage Sensor Connection . . . . . . . . . . . . . . . . . . . . 41 3.7 Voltage Measuring Circuit . . . . . . . . . . . . . . . . . . . . 42 3.8 Voltage Scaling from Primary current to DSP Analog Voltage 43 3.9 Structure of DSP On-chip ADC . . . . . . . . . . . . . . . . . 43 3.10 Current Measuring Circuit . . . . . . . . . . . . . . . . . . . . 44 3.11 Current Scaling from Primary Current to DSP Analog Voltage 45 3.12 Temperature Sensor Circuit . . . . . . . . . . . . . . . . . . . 45 3.13 Temperature Hysteresis Loop . . . . . . . . . . . . . . . . . . 46 3.14 System Protection Circuit . . . . . . . . . . . . . . . . . . . . 47 4.1 Program Flow Chart . . . . . . . . . . . . . . . . . . . . . . . 50 4.2 ADC Conversion Time . . . . . . . . . . . . . . . . . . . . . . 53 4.3 Timer 1 and 2 ISR Sequence . . . . . . . . . . . . . . . . . . 54 4.4 Flowchart of PDPINTA ISR . . . . . . . . . . . . . . . . . . 55 4.5 Sine Look-up Table . . . . . . . . . . . . . . . . . . . . . . . . 56 4.6 Phase Detection Diagram . . . . . . . . . . . . . . . . . . . . 59 4.7 The Flow Chart of the Current Calculation Block . . . . . . . 60 5.1 Control Circuit Board . . . . . . . . . . . . . . . . . . . . . . 61 5.2 Power Circuit Board . . . . . . . . . . . . . . . . . . . . . . . 61 5.3 The Whole Circuits . . . . . . . . . . . . . . . . . . . . . . . 61 5.4 Experimental System . . . . . . . . . . . . . . . . . . . . . . . 61 5.5 Rsim = 0.5p.u. at fpwm = 20kHz . . . . . . . . . . . . . . . . 63 5.6 Current Ripple at Rsim = 0.5p.u. . . . . . . . . . . . . . . . . 63 5.7 Rsim = 1p.u. at fpwm = 20kHz . . . . . . . . . . . . . . . . . 63 5.8 Current Ripple at Rsim = 1p.u. . . . . . . . . . . . . . . . . . 63 5.9 Rsim = 2p.u. at fpwm = 20kHz . . . . . . . . . . . . . . . . . 63 5.10 Current Ripple at Rsim = 2p.u. . . . . . . . . . . . . . . . . . 63 viii List of Figures 5.11 Rsim = 2p.u. at fpwm = 10kHz and L = 2.6mH . . . . . . . . 64 5.12 Current Ripple at Rsim = 2p.u. and fpwm = 10kHz . . . . . . 64 5.13 Rsim = 2p.u. at fpwm = 20kHz and L = 2.6mH . . . . . . . . 65 5.14 Current Ripple at Rsim = 2p.u. and fpwm = 20kHz . . . . . . 65 5.15 L = 2.6mH, Rsim = 2p.u. and fpwm = 20kHz . . . . . . . . . 66 5.16 Current Ripple at L = 2.6mH . . . . . . . . . . . . . . . . . . 66 5.17 L = 26mH, Rsim = 2p.u. and fpwm = 20kHz . . . . . . . . . 66 5.18 Current Ripple at L = 26mH . . . . . . . . . . . . . . . . . . 66 5.19 Lsim = 0.5p.u. at fpwm = 20kHz . . . . . . . . . . . . . . . . 67 5.20 Lsim = 1p.u. at fpwm = 20kHz . . . . . . . . . . . . . . . . . 67 5.21 L = 2.6mH ,Lsim = 1p.u. and fpwm = 20kHz . . . . . . . . . 68 5.22 L = 26mH ,Lsim = 1p.u. and fpwm = 20kHz . . . . . . . . . 68 5.23 Current Ripple at L = 2.6mH . . . . . . . . . . . . . . . . . . 68 5.24 Current Ripple at L = 26mH . . . . . . . . . . . . . . . . . . 68 5.25 Csim = 0.5p.u. at fpwm = 20kHz . . . . . . . . . . . . . . . . 69 5.26 Csim = 1p.u. at fpwm = 20kHz . . . . . . . . . . . . . . . . . 69 5.27 L = 2.6mH ,Csim = 1p.u. and fpwm = 20kHz . . . . . . . . . 70 5.28 L = 26mH ,Csim = 1p.u. and fpwm = 20kHz . . . . . . . . . 70 5.29 Current Ripple at L = 2.6mH . . . . . . . . . . . . . . . . . . 70 5.30 Current Ripple at L = 26mH . . . . . . . . . . . . . . . . . . 70 6.1 Simplified Electronic Load Diagram . . . . . . . . . . . . . . 72 6.2 Combination Electronic Load Diagram . . . . . . . . . . . . . 73 A.1 PowerSupply AD.SCHDOC . . . . . . . . . . . . . . . . . . . 77 A.2 VoltageSensor.SCHDOC . . . . . . . . . . . . . . . . . . . . . 78 A.3 CurrentSensor.SCHDOC . . . . . . . . . . . . . . . . . . . . . 79 A.4 TMPSensor.SCHDOC . . . . . . . . . . . . . . . . . . . . . . 80 A.5 Driver.SCHDOC . . . . . . . . . . . . . . . . . . . . . . . . . 81 A.6 MUBW20.SCHDOC . . . . . . . . . . . . . . . . . . . . . . . 82 A.7 Control Board PCB . . . . . . . . . . . . . . . . . . . . . . . 83 A.8 Control Board PCB Top Layer . . . . . . . . . . . . . . . . . 84 A.9 Control Board PCB Bottom Layer . . . . . . . . . . . . . . . 85 A.10 Power Board PCB . . . . . . . . . . . . . . . . . . . . . . . . 86 A.11 Power Board PCB Top Layer . . . . . . . . . . . . . . . . . . 87 A.12 Power Board PCB Bottom Layer . . . . . . . . . . . . . . . . 88 B.1 Schematics for 3-phase Islanding Test . . . . . . . . . . . . . 90 ix Acknowledgements I wish to express my deepest gratitude to my supervisor, Dr. William G. Dunford. During the thesis research, Dr. William G. Dunford provided enormous help and encouragement. This work would not be possible without his broad knowledge and patient instruction. I would like to thank Dr. Juri Jatskevich for his insights and valuable suggestions toward the completeness of this thesis. I would like to express my thanks to Michel AlSharidah who worked with me together in this research and shared with me his experience and optimism in the islanding tests and simulations. Thanks are extended to my colleges Tom De Rybel, Dean Chen, Yong Zhang and Mehmet Sucu for their great suggestions. Finally, I am expressing my sincerest gratitude to my parents and my girlfriend for their love and support during my studies. 1 Chapter 1 Introduction 1.1 Project Background Distributed Generation (DG) which is gaining more and more interest around the world generally refers to small-scale (typically 1kW – 50MW ) electric power generators that produce electricity at a site close to customers or that are tied to an electric distribution system. Among DG technologies, some are tried and tested but a number are new and developing technolo- gies which use renewable energy sources, such as wind energy, biofuels and photovoltaic (PV) energy. Compared with the traditional larger power stations, DG promises sig- nificant reductions in the power transportation cost and reduces the capital and operating costs which will encourage their further growth. The inte- gration of Distributed Generation into the main electricity networks doesn’t only bring in numerous benefits but some security issues. The anti-islanding protection[1] is the most frequent issue raised by DG interconnection to the utility networks because the island is an unregulated power system. Its be- haviour is unpredictable due to the power mismatch between the load and generation and the lack of voltage and frequency control. Therefore, it is creating the possibility of damage to customer equipment in a situation over which the utility has no control. In wind and PV energy applications, the inverter is the most frequently used interface[2] which interconnects DG to the grids. According to IEEE standard 1547, the inverters used as interface in the distributed generation systems have to pass a series of tests and evaluation before interconnec- tion to the utility. The unintentional islanding test is to verify that the anti-islanding protection of the DG interconnection component is capable of detecting the islanding conditions and ceasing to energize the electric power system. In the unintentional islanding test, a resistance, inductance and capacitance (RLC) load is employed as simulated local loads and shall be tuned at the nominal frequency of electricity networks. With increasing of the power rating of DG, the size of RLC loads used in the unintentional islanding test become bigger and bigger which makes 2 1.2. System Overview the tuning process of RLC circuits very time-consuming and inconvenient. Therefore, a compact and programmable electronic load is needed which can simulate different RLC networks. 1.2 System Overview 1.2.1 Unintentional Islanding Test Scheme As described in the previous section, an interface inverter has to pass the un- intentional islanding test before put into practical use. IEEE standard 1547 defines a generic system for unintentional islanding test which is illustrated in Figure 1.1. ∆P, ∆Q P, Q P+∆P, Q+∆Q V, f Figure 1.1: Generic System for Unintentional Islanding Test In the normal operation mode, switches S1, S2 and S3 are closed and the electricity network, local loads and DG interface inverter are interconnected together. The real and reactive power consumed in local loads are provided by both utility network and distributed generation system. Once the switch S1 is open, the electricity network is unable to provide power for customers and local loads are connected solely to DG system which is called ”islanding situation”. If the power generated by the DG system matches the RLC load power, i.e., in Figure 1.1, ∆P = ∆Q = 0. Under this condition, even if switch S1 is open, the voltage and frequency at the Point of Common Coupling (PCC) 3 1.3. Thesis Objective will not be changed and an unintentional islanding situation occurs which is considered the worst case for islanding detection. 1.2.2 AC Electronic Loads for Unintentional Islanding Test In this thesis, a single phase AC electronic load is designed to replace the RLC load shown in Figure 1.2 so that the tuning of RLC circuits can be achieved more easily by adjusting the values of electronic loads in the soft- ware. ∆P, ∆Q P, Q P+∆P, Q+∆Q V, f Figure 1.2: Electronic Loads for Unintentional Islanding Test The AC electronic loads consist of three parts: • A bidirectional H-Bridge based current source. • Voltage and current sensor circuits. • A TMS320LF2407A DSP control board. 1.3 Thesis Objective The objective of this thesis is to clarify the practical approaches needed to set up a programmable AC electronic load used in unintentional islanding test. The specific objectives include: • To find a suitable structure of the bidirectional current source 4 1.3. Thesis Objective • To find the design criteria of H-bridge based current source for the different ranges of the resistive, inductive and capacitive electronic loads with the 60Hz AC source. • To build a DSP-controlled H-bridge based current source. • To develop a control method for the programmable RLC electronic loads • To generate a DSP program for the TMS320LF2407A DSP. • To simulate different ranges of resistive, inductive and capacitive loads with a 60Hz sinusoidal voltage excitation and verify the theoretical analysis using the prototype. The thesis is organized into six chapters. Chapter 1 gives a brief intro- duction of the system and outlines the objectives of this thesis. In Chapter 2, the principles of the AC electronic loads are proposed and the PSIM simulations for different electronic loads are performed to give a set of spec- ifications of the system. Chapter 3 is focused on hardware setup for the electronic loads. Chapter 4 will be dealing with software implementation. Some design illustration concerning software is presented. Selective exper- imental results are included in Chapter 5. The last chapter concludes the design and the implementation and proposes some work needed to be done in the future. 5 Chapter 2 Principles of the Simulated Loads In this chapter the principles of the simulated loads will be introduced step by step. First of all, the schematic of the simulated loads will be proposed carefully. Secondly, the ac small-signal model of the circuit will be derived as well as the stability of the system. Then, the relationship between the parameters of the circuit and the range of the simulated loads will be ana- lyzed. At the end, a series of PSIM simulations for different kinds of loads will be performed and several groups of parameters will be given for different ranges of the simulated loads. 2.1 Schematic of Electronic loads Figure 2.1: Diagram of Electronic Loads Figure 2.1 shows the diagram of the electronic loads. It can be seen that the different load will draw the different current I from the input voltage source and thus the load characteristics can be changed if the output current of the source is under control. For an AC input source, the direction of the output current could be either positive or negtive, which means a bidirectional controllable current source is needed to control the output current of the source so that it can 6 2.1. Schematic of Electronic loads simulate different load characteristics. In this project, an H-bridge inverter- based bidirectional current source will be designed as an electronic load. 2.1.1 H-Bridge Bidirectional Current Source dc 2 1 g R L L Figure 2.2: Controllable Current Source with Regulated DC Bus Voltage The schematic of the H-bridge inverter-based bidirectional current source is illustrated in Figure 2.2. It is very similar to the traditional H-bridge dc- dc converter but the difference is that the port “AB” is used as the input port instead of the output port. The parameters of the circuit is explained as follows: • DC bus voltage. In order to make this circuit work properly, the DC bus voltage is regulated by a DC power supply which must be positive so that there are no short-circuits caused by the flywheel diodes which may lead to the serious damage of IGBTs. • Resistor R1. In the real system, a series resistor R1 always exists because of the equivalent series resistance of the inductor L and the resistance of the conductors. • Resistor R2. The resistor R2 is a dumping resistor and used to provide a closed loop for the inductor current IL. • Inductor L. the series inductor L is capable of smoothing the current IL so that this circuit can work as a current source. 7 2.1. Schematic of Electronic loads 2.1.2 The Range of Inductor Current In the following parts, the range of the current IL will be derived in order to analyze the electronic load characteristics. In simple terms of, a DC voltage source Vg will be applied in the circuit as an input source. However, the results are also available for low-frequency AC voltage sources, such as 60Hz. As depicted in Figure 2.2, the duty ratio D is the fraction of time that the switches S1 and S4 spend in the conducting position, and is a number between zero and one. The complement of the duty ratio, D′, is defined as (1 −D), which means the fraction of time that the switches S2 and S3 spend in the conducting status. The small ripple approximation and the principles of inductor volt- second balance[3] will be applied here to find the steady state of the inductor current IL. Figure 2.3 illustrates the operation topologies of the H-bridge inverter with regulated DC bus when the switches commutate. 2 1 g R L L 2 1 g R L L DC DC Figure 2.3: H-Bridge Inverter With Regulated DC Bus: (a) the first subin- terval: D, (b) the second subinterval: D′ As illustrated in the Figure 2.3(a), during the first subinterval, DT , the switches S1 and S4 are on and the other switches S2 and S3 are off. The inductor voltage for this subinterval is given by vL = Vg − Vdc − iL ×R1 (2.1) Use of the small ripple approximation, iL ≈ IL, leads to vL = Vg − Vdc − IL ×R1 (2.2) 8 2.2. AC Small-Signal Modeling and PI Control Method Similarly, during the second subinterval, D′T , the status of the switches are illustrated in the Figure 2.3(b). The inductor voltage for this subinterval is vL = Vg + Vdc − iL ×R1 (2.3) Use of the small ripple approximation again leads to vL = Vg + Vdc − IL ×R1 (2.4) According to the principles of inductor volt-second balance, the total volt-seconds applied to the inductor over one switching period is < vL >= 0 (2.5) Substitution of Eq.(2.2) and Eq.(2.4) into Eq.(2.5), and the result is D (Vg − Vdc − ILR1) +D′ (Vg + Vdc − ILR1) = 0 (2.6) Upon collecting terms, one obtains Vg = (2D − 1)Vdc + ILR1 (2.7) From Eq.(2.7), the average inductor current IL can be obtained IL = Vg + (1− 2D)Vdc R1 (2.8) Therefore, the controllable range of the current flowing through the in- ductor L can be derived easily according to Eq.(2.8). When the switches S2 and S3 are always on, the inductor current IL reaches to the maximum value; when the switches S1 and S4 are always off instead, the minimum value can be obtained. The results are given by ILmax = (Vg + Vdc)/R1 ILmin = (Vg − Vdc)/R1 (2.9) 2.2 AC Small-Signal Modeling and PI Control Method In this section, the ac small-signal modeling technique is employed for the derivation of the system transfer function and a conventional PI controller is designed accordingly for the PWM current controller. 9 2.2. AC Small-Signal Modeling and PI Control Method 2.2.1 AC Small-Signal Model The ac small-signal model is always used in the analysis of the dynamic performance of power electronic circuits. With this model, the transfer function of the system can be derived which is very useful for the stability analysis of the control system. However, this model only works at the low- frequency and the disturbance of the switching frequency will be neglected. According to Figure 2.3, the voltage equations during these two intervals can be derived respectively. d : vg = vdc + 〈iL (t)〉Ts ·R1 + Ld〈iL(t)〉Tsdt d′ : vg = −vdc + 〈iL (t)〉Ts ·R1 + Ld〈iL(t)〉Tsdt (2.10) Where 〈iL (t)〉Ts denotes the average of 〈iL (t)〉 over an interval of length Ts which represents one PWM switching period. Using Eq.(2.10), the average of voltage vg over one switching period equals: ( d+ d′ ) vg = ( d− d′) vdc + (d+ d′) [〈iL (t)〉Ts ·R1 + Ld 〈iL (t)〉Tsdt ] (2.11) Upon collecting items, it can be rewritten as: vg = (2d− 1) vdc + 〈iL (t)〉Ts ·R1 + L d 〈iL (t)〉Ts dt (2.12) Perturbing the inductor current, duty-cycle, input voltage and DC bus voltage with small signals of ∧ iL, ∧ d, ∧ vg and ∧ vdc respectively; also, assuming the quiescent value of these variables are IL, D, Vg and Vdc then: 〈iL (t)〉Ts = IL + ∧ iL (2.13) d = D + ∧ d (2.14) vg = Vg + ∧ vg (2.15) vdc = Vdc + ∧ vdc (2.16) Insert Eq.(2.13) to (2.16) into Eq.(2.12), one obtains: 10 2.2. AC Small-Signal Modeling and PI Control Method Vg + ∧ vg = [ 2 ( D + ∧ d ) − 1 ] [ Vdc + ∧ vdc ] + ( IL + ∧ iL ) R1 + L d ( IL + ∧ iL ) dt (2.17) Linearizing Eq.(2.17), the ac small signal equation can be derived: ∧ vg = (2D − 1) ∧vdc +2Vdc ∧ d+R1 ∧ iL +L d ∧ iL dt (2.18) Taking the Laplace transform for Eq.(2.18), the inductor current to duty ratio transfer function can be obtained: Gid (s) = ∧ iL ∧ d ∣∣∣∣∣∣ ∧ vdc, ∧ vg=0 = −2Vdc R1 + sL (2.19) 2.2.2 The Transfer Function of Control System In this system, a traditional PI compensator is chose for the current feedback loop due to the uncompensated system containing a single pole. The transfer function of the compensator can be expressed as: Gc (s) = kp + ki s (2.20) The function of the pulse-width modulator is to produce the duty ratio d that is proportional to the output voltage of the compensator. Figure 2.4 shows the schematic diagram of the pulse-width modulator. M s s s saw c Figure 2.4: Schematic Diagram of PWM Modulator 11 2.2. AC Small-Signal Modeling and PI Control Method In terms of the waveform above, the duty cycle d will be a linear function of Vc. Hence, we can write d (t) = vc (t) VM (2.21) Perturbation and linearization of Eq.(2.21), the transfer function of the pulse-width modulator is: Gpwm (s) = ∧ d ∧ vc (2.22) Based on the analysis above, the system transfer function can be derived as follows (Figure 2.5). Note that the pwm modulator outputs d′ in our design, and thus a negative transfer function of the circuit is applied. In addition, a saturation block is also added to the PI compensator to eliminate the effect of integral saturation. M id sim p i err c ref Figure 2.5: Block Diagram of the System Transfer Function 2.2.3 Control System Stability Analysis In this project, a set of PI parameters of the control system is obtained using PSIM simulations and practical experiments: • PI parameters: kp = 1 and ki = 5× 105. • Saturation block: -20 to 20. • PWM modulator: VM = 40. According to the analysis above, the stability of these PI parameters can be investigated using Simulink7.0 and LTIViewer in MATLAB2008a. The bode diagram of the open-loop transfer function is depicted in Figure 2.6. It can be seen that the phase margin is always larger than zero so the system is stable. 12 2.3. System Performance Analysis Frequency (rad/sec) 10 2 10 3 10 4 10 5 10 6 10 7 -180 -135 -90 P ha se  (d eg ) -50 0 50 100 From: In1 (pt. 1)  To: Gain1 (pt. 1) M ag ni tu de  (d B ) Figure 2.6: Bode Diagram of the Open-Loop Transfer Function 2.3 System Performance Analysis The electronic load designed in this project works in the switching mode, so the triangle waveforms are used to track the given sinusoidal waveforms. In order to meet the accuracy requirements, the effects of circuit parameters on the switching ripples and the system response time have to be investigated carefully. Therefore, this section will explore the relationship between the circuit parameters and the system performance. 2.3.1 Current Ripple Figure 2.2 shows that the inductor L which prevents the current from being changed suddenly plays the most important role in the current control. In this section, the effect of circuit parameters on the current ripple will be investigated carefully and the formula of the current ripple will be derived for the calculation of circuit parameters according to the given accuracy demands . The current ripple used here is defined as ∆iL/2IL. Where ∆iL is the peak-to-peak current change and IL is the average current over one switching period. The following parts will introduce the relationship between the cur- rent ripple and the circuit parameters for the simulated resistive, inductive 13 2.3. System Performance Analysis and capacitive loads separately. Current Ripple for Resistive Loads In simple terms, a DC voltage source Vg is employed as the input voltage source as shown in Figure 2.2 and the circuit is controlled to simulate the resistance characteristic. To the extent of an low-frequency AC voltage source, such as 60Hz, the analysis still works fine because the AC source can be discretized into a series of DC voltage source at low frequency. As illustrated in Figure 2.2, the current change ∆iL is related to the inductor L and the current ripple ∆iL/2IL should be as small as possible so that the high frequency noise of the electronic loads can be decreased greatly. Only consider the intervals D′T that S2 and S3 are on. According to the inductance characteristic, one obtains L diL dt = vL (2.23) Where vL = Vdc + Vg − vR1 (2.24) When R1  Rsim(Rsim: simulated resistor), vR1 can be ignored vL ≈ Vdc + Vg (2.25) Insert Eq.(2.25) into Eq.(2.23), one obtains L diL dt ≈ Vdc + Vg = (1 + k)Vg (2.26) Where Vdc = Vg, then the current change ∆iL is equal to ∆iL = (1 + k)Vg L ×∆t (2.27) Using Eq.(2.8), the steady state of inductor current IL is given by IL = Vg+(1−2D)Vdc R1 = Vg+(1−2D)kVgR1 = 1+(1−2D)kR1 Vg (2.28) 14 2.3. System Performance Analysis Because the circuit is working as resistance loads, the average current of inductor IL is also equal to IL = Vg Rsim (2.29) The duty ratio D can be derived through combination of Eq.(2.28) and Eq.(2.29) 1+(1−2D)k R1 × Vg = VgRsim ⇒ D = 12k ( k + 1− R1Rsim ) (2.30) The time interval ∆t can be obtained using Eq.(2.30) ∆t = (1−D)× Tpwm = (k−1)Rsim+R12·k·Rsim × Tpwm (2.31) Combining Eq.(2.27) and Eq.(2.29), the ratio of the current change ∆iL to inductor current IL is equal to ∆iL IL = (k + 1)Rsim L ×∆t (2.32) Insert Eq.(2.31) into Eq.(2.32), the current ripple is obtained ∆iL 2IL = 12 × (k+1)RsimL × (k−1)Rsim+R12·k·Rsim × Tpwm = 12 × TpwmL × (k2−1)Rsim+(k+1)R1 2k (2.33) The equation above indicates that the current ripple ∆iL/2IL is a func- tion of the simulated resistive load Rsim, the PWM period Tpwm and the value of the inductor L when k and series resistor R1 are constant. Accord- ing to this function, the following relationship can be concluded: • The maximum impedance of the simulated loads which is achievable on this system can be derived by Eq.(2.33) when all the circuit parameters and the current ripple requirement are given. • The larger inductor L, the smaller the current ripple. Hence, the minimum value of the inductor L can be calculated with Eq.(2.33) when the simulated resistive load Rsim and the current ripple are given. • The higher switching frequency fpwm, the smoother the current ripple. 15 2.3. System Performance Analysis Current Ripple for Inductive and Capacitive Loads The expression of current ripple for the inductive and capacitive loads are exactly same, so here we only take the inductive loads for example to derive the current ripple expression. From the schematic of the current source, it can be concluded that the largest current ripple will occur when the AC input source reaches zero. Therefore, following the similar process shown in the previous section, one obtains L diL dt ≈ VL (2.34) Where vL = Vdc − vR1 (2.35) When R1  Zsim(Zsim: the impedance of the simulated inductive or capac- itive loads), vR1 can be ignored vL ≈ Vdc (2.36) Insert Eq.(2.36) into Eq.(2.34), one obtains L diL dt ≈ Vdc = kVg (2.37) Then the current change ∆iL is equal to ∆iL = kVg L ×∆t (2.38) According to Eq.(2.8), when Vg = 0, the average current IL over one switch- ing cycle is given by IL = 1− 2D R1 kVg (2.39) When Vg = 0, the average current IL also equals IL = Vg ‖Zsim‖ (2.40) Combining Eq.(2.39) and (2.40), the duty cycle D is equal to D = 1 2 ( 1− R1 k ‖Zsim‖ ) (2.41) 16 2.3. System Performance Analysis When R1  ‖Zsim‖, the duty cycle D is approximately 0.5 and the time interval ∆t = 0.5Tpwm. Therefore, combining Eq.(2.38) and (2.40), the current ripple for inductive or capacitive loads is ∆iL 2IL = 1 2 × k ‖Zsim‖ L × Tpwm 2 (2.42) The expression above shows the similar function as the resistive loads. However, compared with the function of the resistive loads, the current ripple of the simulated inductive or capacitive loads will be larger with the same circuit parameters. 2.3.2 Relationship between Response Time and Zsim To simulate electronic loads under low-frequency voltage source, the re- sponse time of the system should be small enough so that the system is capable of tracking the required load characteristic curves. The following derivations are based on the resistive simulated loads and the conclusion is also available for the inductive or capacitive simulated loads. According to Eq.(2.27) and (2.31), the current change function can be derived ∆iL = (1 + k)Vg L × (k − 1)Rsim +R1 2k ×Rsim × Tpwm (2.43) It can be derived that if the circuit parameters keep constant, the current change ∆iL will increase with the decreasing of Rsim. However, the series inductor L will prevent the current from changing suddenly and thus the response time will increase greatly when the simulated load Rsim decreases. Hence, for a given series inductor L and other given parameters, the mini- mum achievable impedance of the simulated loads can be found considering the proper response time. In the following part, the unit step response of the system will be investigated to find the proper minimum values for the given parameters previously. 2.3.3 Conclusions of System Performance The previous sections explain the relationship between the circuit parame- ters and the system performance. Therefore, a general design procedure can be used according to the requirements of the system performance: • First of all, determine the proper values of k and fpwm and the maxi- mum impedance of the simulated loads. 17 2.4. Calculation of Circuit Parameters • Secondly, according to the current ripple requirement, calculate the minimum inductor L with Eq.(2.33) or Eq.(2.42). • At the end, find the minimum impedance of the simulated loads ac- cording to the given circuit parameters so that the response time of the system is small enough for the 60Hz AC source. 2.4 Calculation of Circuit Parameters The schematic and performance of the system have been explained previ- ously. This section will introduce how to calculate the circuit parameters according to the given accuracy demands and a set of values of circuit pa- rameters will be listed for the different ranges of the simulated loads. The analysis proposed here is all based on the PSIM simulations and the theo- retical derivation. 2.4.1 Introduction of PSIM Simulation Diagram Powersim (PSIM) is a powerful circuit simulation software which is specially suited to power electronic circuit simulations. All kinds of semiconductor parts and the control blocks have been integrated in the software package, which makes it very easy to use. In order to analyze the circuit parameters, a PSIM simulation program for the simulated resistive loads will be used in this section and the con- clusions obtained from this system is also suitable for the inductive and capacitive loads with some minor changes. Figure 2.7 shows the schematic of the resistive load simulation consist- ing of the H-Bridge current source and the control program. The control program senses the inductor current iL and the input voltage source Vg to calculate the error between the actual voltage and the demanded voltage using equation: error = Vsource − Isense ×Rsim (2.44) Where Rsim represents the resistance of the simulated resistive loads. With a set of proper PI parameters (given in the previous section), the error Verr can be obtained which is used to compared with a saw-tooth waveform to generate PWM signals. In the PSIM simulation, the per-unit system is employed and the voltage and current base values are equal to 30V and 0.78125A separately which are also used in the DSP program and thus the impedance base value is 38.4Ω. The choice of the base values will be explained in the chapter four. 18 2.4. Calculation of Circuit Parameters Figure 2.7: Resistance Load Simulation 2.4.2 DC Bus Voltage: Vdc As discussed in the previous sections, the DC bus voltage Vdc must be posi- tive so that there are no short-circuits and according to Eq.(2.9), Vdc should be greater than or equal to Vg to increase the range of the inductor current, in other words, to increase the range of the electronic loads. A parameter of k is defined as the ratio of Vdc to Vg and should be larger than or equal to 1. However, if k is 1, it’s going to take a very long period to decrease the current due to the zero reverse voltage across the series inductor; if k is much larger than 1, the current ripple will be increased significantly. Through the practical experiments, the parameter of k is kept to be 1.3 to improve the dynamic performance of the device as well as the current ripple. 2.4.3 Series Resistor: R1 From Eq.(2.9), ILmax = (Vg + Vdc)/R1, it can be seen that the minimum impedance of electronic loads is decided by the series resistor R1. When 19 2.4. Calculation of Circuit Parameters Vdc = 1.3Vg, the minimum simulated impedance |Zsim|min = R1/2.3. In our system, the series resistor R1 is 17Ω and the minimum limitation of the simulated impedance is about 7.4Ω. 2.4.4 Switching Frequency: fpwm As discussed previously, the current ripple depends upon the switching fre- quency fpwm and the higher switching frequency, the smaller current ripple. In this project, the switching frequency fpwm is set to 20kHz which is the most typical frequency of IGBTs. 2.4.5 Inductor: L It has been discussed in the previous sections that the value of inductor L is determined by the requirement of the current ripple (Eq.(2.33) and Eq.(2.42)). On the other hand, once the inductor value and other parameters are chosen, the range of the impedance of the simulated loads can be calculated with the consideration of both the current ripple and the response time. The following parts will show how to calculate the inductor value and the range of the simulated loads. Calculation of Inductor L For resistive loads, three different ranges of the simulated loads are given in Table 2.1. From Eq.(2.33), a set of minimum values of the series inductor L can be calculated for the resistive loads according to the given current ripple and the maximum impedance of the simulated loads. Assume the current ripple ∆iL/2IL should be less than 0.3, the minimum inductors for the simulated resistive loads are shown as follows. Range of Rsim Lmin Maximum Current Ripple 0− 2p.u. 2.6mH 0.34 (actual value: 0.3) 0− 20p.u. 26mH 0.21 0− 200p.u. 260mH 0.19 Table 2.1: Series Inductors for Different Ranges of Resistance Loads: switching frequency fpwm = 20kHz, voltage ratio k = 1.3, series resistor R1 = 17Ω and the impedance base value ‖Z‖ = 38.4Ω 20 2.4. Calculation of Circuit Parameters It can be found that the current ripple is larger than 0.3 at Rsim = 2p.u. but the real current ripple is equal to 0.3 because the equation we used here is derived with the approximation of R1  Rsim but Rsim = 2p.u. is comparable with R1. Therefore, the actual current ripple at small simulated resistance is less than the calculated value (the real current ripple can be found using the PSIM simulations in Figure 2.20). The similar results for the inductive or capacitive simulated loads can be obtained with Eq.(2.42). Considering the hardware consistency, the same set of values of the series inductor L as shown in Table 2.1 will be used in the calculations, so the maximum impedance of the simulated loads and the associated current ripple are calculated as follows. Maximum ‖Zsim‖ Series Inductor L Maximum Current Ripple 1.25p.u. 2.6mH 0.30 12.5p.u. 26mH 0.30 125p.u. 260mH 0.30 Table 2.2: Series Inductors for Different Ranges of Inductive or Capacitive Loads: switching frequency fpwm = 20kHz, voltage ratio k = 1.3, series resistor R1 = 17Ω and the impedance base value ‖Z‖ = 38.4Ω Practically, with the consideration of simplicity, another set of values of ‖Zsim‖ is given in Table 2.3 after the rounding adjustment. The parameters listed above are all based on the assumption that the current ripple is less than 0.3. If a smaller current ripple is required for the specific application, the simplest approach is just to increase the switching frequency fpwm proportionally and retain other parameters. Maximum ‖Zsim‖ Series Inductor L Maximum Current Ripple 1p.u. 2.6mH 0.24 10p.u. 26mH 0.24 100p.u. 260mH 0.24 Table 2.3: Series Inductors for Different Ranges of Inductive or Capacitive Loads: switching frequency fpwm = 20kHz, voltage ratio k = 1.3, series resistor R1 = 17Ω and the impedance base value ‖Z‖ = 38.4Ω 21 2.4. Calculation of Circuit Parameters 2.4.6 Calculation of the Range of Zsim As discussed above, once the current ripple requirement and the series in- ductor are given, the maximum achievable impedance of the simulated loads is also set up. However, not all impedances less than the maximum value are able to be simulated with this system. In this section, the response time of the system will be analyzed and the minimum achievable impedance of the simulated loads can be determined by the response time. Simulation Results of the Response Time Here we takes L = 26mH for example to find the minimum limitation of the impedance. In the PSIM simulations shown in Figure 2.7, the parameters are: fpwm = 20kHz, Rsim = 2p.u.(76.8Ω), R1 = 17Ω and L = 26mH. To explore the unit step response, a unit step input voltage source Vg is applied. Figure 2.8 depicts the unit step response of the system at Rsim = 2p.u.. Replacing the unit step source with a 60Hz AC source, the voltage across Rsim(2p.u.) is plotted in Figure 2.9. It can seen that the rise time is equal to 0.46ms and the settling time is 3.50ms which is fast enough for the application of 60Hz. 200.00 202.00 204.00 206.00 208.00 210.00 212.00 Time (ms) 0.0 0.50 1.00 1.50 2.00 V_Rsim (2pu) Vg rise settle Figure 2.8: Unit Step Response at Rsim = 2p.u. However, if the resistive simulated load Rsim keeps going down to 1p.u., 22 2.4. Calculation of Circuit Parameters 0.0 -0.50 -1.00 -1.50 0.50 1.00 V_Rsim Vg 0.0 -0.50 -1.00 -1.50 0.50 1.00 1.50 V_Rsim 120.00 130.00 140.00 150.00 160.00 Time (ms) 0.0 -0.50 -1.00 -1.50 0.50 1.00 Vg _Rsim (2pu) g 1 0 0.0 -0 -1. -1 1. 0. 0. -0.5 -1.0 -1. 1. 1. 0. 0. -0. -1.0 -1.5 Figure 2.9: Voltage across Rsim = 2p.u. the unit step response time will increase consistently as shown in Figure 2.10. Replacing the unit step input source with a 60Hz AC source, the voltage waveform across Rsim is depicted in Figure 2.11. It can be seen that the average value of VRsim is no longer equal to the input voltage due to the long response time. 200.00 202.50 205.00 207.50 210.00 212.50 Time (ms) 0.0 0.50 1.00 1.50 V_Rsim (1pu) Vg rise settle 10% error Figure 2.10: Unit Step Response at Rsim = 1p.u. 23 2.4. Calculation of Circuit Parameters 170.75 170.80 170.85 170.90 Time (ms) 990.00m 1000.00m 1010.00m 1020.00m V_Rsim (1pu) Vg 150.00 160.00 170.00 180.00 190.00 Time (ms) 0.0 -0.50 -1.00 0.50 1.00 V_Rsim (1pu) Vg Zoom In Figure 2.11: Voltage across Rsim = 1p.u. On the other hand, if Rsim increases, the response time will keep decreas- ing and the response time for Rsim = 20p.u. is illustrated in Figure 2.12. Compared with the response time at Rsim = 2p.u., the response time at Rsim = 20p.u. is much faster but more ripples. 100.00 102.00 104.00 106.00 Time (ms) 0.0 -1.00 1.00 2.00 3.00 V_Rsim Vg rise settle 48% error Figure 2.12: Unit Step Response at Rsim = 20p.u. 24 2.4. Calculation of Circuit Parameters The Range of Zsim Based upon the discussion above it can be concluded that the minimum achievable impedance of the simulated loads is determined by the response time if the value of the series inductor is given. With the help of PSIM simulations, a set of values of the minimum Rsim is found in Table 2.4. Series Inductor L Minimum Rsim 2.6mH ≥ 0.2p.u. 26mH ≥ 2pu 260mH ≥ 20pu Table 2.4: Minimum Rsim for the Given Series Inductor: switching fre- quency fpwm = 20kHz, voltage ratio k = 1.3, series resistor R1 = 17Ω and the impedance base value ‖Z‖ = 38.4Ω Similarly, the minimum impedance of the inductive or capacitive sim- ulated loads is also able to be found in the table below with the PSIM simulation programs. Series Inductor L Minimum Lsim (or Csim) 2.6mH ≥ 0.1p.u. 26mH ≥ 1pu 260mH ≥ 10pu Table 2.5: Minimum Lsim (or Csim) for the Given Series Inductor: switching frequency fpwm = 20kHz, voltage ratio k = 1.3, series resistor R1 = 17Ω and the impedance base value ‖Z‖ = 38.4Ω 2.4.7 Duty Ratio D This section will introduce the effect of the duty cycle D on the range and resolution of the simulated loads. According to Eq.(2.28) and Eq.(2.29), a resistive simulated load can be represented as: Rsim = Vg IL = R1 1 + (1− 2D) · k (2.45) In a continuous system, the value of Rsim could be infinite when the denominator is approaching zero. However, the real system we used in this 25 2.4. Calculation of Circuit Parameters project is a digital system with a 16-bit DSP so the step size of the duty ratio D is 1 / 216. With this step size, the range of the resistive load is illustrated in Figure 2.13 for the given parameters above. 0 0.2 0.4 0.6 0.8 1 -1 -0.5 0 0.5 1 1.5 2 2.5 3 x 10 6 Duty Ratio D R si m Relationship between D and Rsim Figure 2.13: Relationship between Rsim and D It can be found that the slope of the function Rsim (D) will increase significantly when the duty cycle D approaches the value which makes the denominator equal zero (Here it is 0.8846). This phenomenon indicates that if the step size of D is fixed, the resolution of the simulated resistive load is going down when D approaches that sensitive value. In order to achieve a higher resolution of the simulated resistive load, the simulated impedance should fall into a reasonable range depending on the required resolution. Using Eq.(2.45), the resolution can be calculated for the simulated resistive loads shown in the previous section (See Table 2.6). Range of Rsim Resolution (%) < 2p.u. ≤ 0.018 < 20p.u. ≤ 0.18 < 200p.u. ≤ 1.8 Table 2.6: The Resolution of Rsim: switching frequency fpwm = 20kHz, voltage ratio k = 1.3, series resistor R1 = 17Ω and the impedance base value ‖Z‖ = 38.4Ω 26 2.4. Calculation of Circuit Parameters For the impedance larger than 200p.u., the resolution becomes too small to be applied in the practical system. Figure 2.14 depicts that the resolution of Rsim at 2000p.u. is going up to 18.7% and this error is too big for a practical application. 0.8841 0.8842 0.8843 0.8844 0.8845 -2 -1 0 1 2 3 4 x 105 X: 0.8845 Y: 6.744e+004 Duty Cycle D R si m  (O hm s) Resolution of Rsim (%) X: 0.8845 Y: 8.004e+004 Resolution 18.7% at Rsim = 2000pu Figure 2.14: Resolution at Rsim = 2000pu According to Eq.(2.41), the similar results can be derived for the induc- tive or capacitive simulated loads (as shown in Table 2.7) Range of Lsim (or Csim) Resolution (%) < 1p.u. ≤ 0.0089 < 10p.u. ≤ 0.090 < 100p.u. ≤ 0.90 Table 2.7: The Resolution of Lsim (or Csim): switching frequency fpwm = 20kHz, voltage ratio k = 1.3, series resistor R1 = 17Ω and the impedance base value ‖Z‖ = 38.4Ω 2.4.8 Specifications of Electronic Loads From the previous discussion, a series values of the circuit parameters can be derived for the resistive, inductive and capacitive simulated loads shown in the Table 2.8 and 2.9 respectively. 27 2.5. Simulations of Electronic Loads Rsim Inductor L Resolution (%) Current Ripple 0.5− 2p.u. 2.6mH ≤ 0.018 ≤ 0.3 2− 20p.u. 26mH ≤ 0.18 < 0.3 20− 200p.u. 260mH ≤ 1.8 < 0.3 Table 2.8: Specifications for the Resistive Simulated Loads: switching fre- quency fpwm = 20kHz, , voltage ratio k = 1.3, series resistor R1 = 17Ω and the impedance base value ‖Z‖ = 38.4Ω Lsim (Csim) Inductor L Resolution (%) Current Ripple 0.5− 1p.u. 2.6mH ≤ 0.00089 ≤ 0.24 1− 10p.u. 26mH ≤ 0.090 ≤ 0.24 10− 100p.u. 260mH ≤ 0.90 ≤ 0.24 Table 2.9: Specifications for the Inductive or Capacitive Simulated Loads: switching frequency fpwm = 20kHz, , voltage ratio k = 1.3, series resistor R1 = 17Ω and the impedance base value ‖Z‖ = 38.4Ω These parameters are all obtained based on the 0.3 current ripple as- sumption and increasing the switching frequency is able to achieve the smaller current ripple. 2.5 Simulations of Electronic Loads In this section, RLC electronic loads will be simulated using PSIM8.0 sepa- rately to verify the principles derived in the previous sections and the cal- culations of the specifications suggested above. 2.5.1 Resistive Load Simulation The PSIM simulation program for the resistive simulated loads has been depicted in Figure 2.7. Based upon the previous introduction and the pa- rameters, the simulations can be performed and the waveforms are shown below for the current ripple analysis. Current Ripple and Inductor L According to Eq.(2.33), the current ripple can be calculated when R1  Rsim. But when the resistance of the simulated load is comparable to R1, the 28 2.5. Simulations of Electronic Loads actual ripples are smaller than the calculated values obtained with Eq.(2.33). For example, assume the switching frequency fpwm = 20kHz, voltage ratio k = 1.3, series resistor R1 = 17Ω and series inductor L = 2.6mH. The calculated ripple is equal to 0.19 at Rsim = 0.5p.u., 0.24 at Rsim = 1p.u. and 0.34 at Rsim = 2p.u.. However, in the PSIM simulations, the actual ripples can be obtained (See Figure 2.15 to 2.20) and equal 0.13, 0.19 and 0.3 separately which are smaller than the calculated values. 130.00 140.00 150.00 160.00 170.00 Time (ms) 0.0 -0.50 -1.00 0.50 1.00 V_Rsim (0.5pu) Vg V_Rsim Vg Zoom In Figure 2.15: Rsim = 0.5p.u. at fpwm = 20kHz 154.10154.12154.14154.16154.18154.20154.22154.24 Time (ms) 0.90 0.95 1.00 1.05 1.10 V_Rsim (0.5pu) Vg ΔiL/2IL=0.13 Figure 2.16: Current Ripple at Rsim = 0.5p.u. 140.00 160.00 180.00 Time (ms) 0.0 -0.50 -1.00 0.50 1.00 V_Rsim (1pu) Vg V_Rsim Vg Zoom In Figure 2.17: Rsim = 1p.u. at fpwm = 20kHz 154.02154.04154.06154.08154.10154.12154.14 Time (ms) 0.80 0.90 1.00 1.10 1.20 V_Rsim (1pu) Vg ΔiL/2IL=0.19 Figure 2.18: Current Ripple at Rsim = 1p.u. 29 2.5. Simulations of Electronic Loads 140.00 160.00 180.00 Time (ms) 0.0 -0.50 -1.00 -1.50 0.50 1.00 1.50 V_Rsim (2pu) Vg V_Rsim Vg Zoom In Figure 2.19: Rsim = 2p.u. at fpwm = 20kHz 154.016 154.048 154.08 154.112 154.144 Time (ms) 0.70 0.80 0.90 1.00 1.10 1.20 1.30 V_Rsim (2pu) Vg ΔiL/2IL=0.30 Figure 2.20: Current Ripple at Rsim = 2p.u. To investigate the current ripples for 2p.u. ≤ Rsim ≤ 20p.u., the 2.6mH inductor is replaced with a 26mH inductor to simulate Rsim = 2p.u. and 20p.u. respectively. Using Eq.(2.33) again, the current ripple equals 0.21 at Rsim = 20p.u.. The waveforms of voltage across Rsim and the associated current ripples are depicted in Figure 2.21 to 2.24. Figure 2.24 shows that the current ripple at Rsim = 20p.u. equals 0.20 which is very close to the calculated value 0.21 because Rsim = 20p.u. = 768Ω is much bigger than R1 = 17Ω. In Figure 2.22,the current ripple is 0.03 at Rsim = 2p.u. and L = 26mH. Compared with the value when L is 2.6mH, the current ripple goes down to 10% which is inversely proportional to the series inductor L same as the relationship shown in Eq.(2.33). 130.00 140.00 150.00 160.00 170.00 Time (ms) 0.0 -0.50 -1.00 0.50 1.00 V_Rsim (2pu) Vg V_Rsim Vg Zoom In Figure 2.21: Rsim = 2p.u. at fpwm = 20kHz 154.105 154.142 154.179 Time (ms) 980.00m 1000.00m 1020.00m V_Rsim (2pu) Vg ΔiL/2IL=0.03 1.02 1.00 0.98 Figure 2.22: Current Ripple at Rsim = 2p.u. 30 2.5. Simulations of Electronic Loads 130.00 140.00 150.00 160.00 170.00 Time (ms) 0.0 -0.50 -1.00 -1.50 0.50 1.00 V_Rsim (20pu) Vg V_Rsim Vg Zoom In Figure 2.23: Rsim = 20p.u. at fpwm = 20kHz 154.123 154.154 154.185 154.216 154.246 Time (ms) 0.80 0.90 1.00 1.10 1.20 V_Rsim (20pu) Vg ΔiL/2IL=0.20 Figure 2.24: Current Ripple at Rsim = 20p.u. Current Ripple and Switching Frequency fpwm Using Eq.(2.33), the current ripple is inversely proportional to the switching frequency fpwm and the PSIM simulation results are shown in following figures. It can be seen in Figure 2.26 that the current ripple ∆iL/2IL equals to 0.61 and is 2 times of the current ripple at 20kHz which proves the inversely proportional relationship between the current ripple and the switching fre- quency. 130.00 140.00 150.00 160.00 170.00 Time (ms) 0.0 -1.00 1.00 V_Rsim (2pu) at 10kHz Vg V_Rsim Vg Zoom In Figure 2.25: fpwm = 10kHz, Rsim = 2p.u. and L = 2.6mH 153.92 154.00 154.08 154.16 Time (ms) 0.40 0.80 1.20 1.60 V_Rsim (2pu) at 10kHz Vg ΔiL/2IL=0.61 Figure 2.26: Current Ripple at Rsim = 2p.u. and fpwm = 10kHz 31 2.5. Simulations of Electronic Loads 2.5.2 Inductive Load Simulation Voltage Magnitude Phase Angle Figure 2.27: Control Loop for Inductance Loads Simulations For the inductance load simulations, no changes have to be done in the circuit but the control algorithm which is shown in Figure 2.27. The control program senses the inductor current iL and input voltage Vg at first. Then, the magnitude and phase angle of Vg are detected and with 90 degrees phase delay, a new voltage magnitude is calculated which can be compared with the inductor current iL directly. Waveforms for Different Ranges of the Inductive Loads With the control program mentioned above, the inductive loads simulations can be achieved using the parameters given previously. The parameters used in the simulations are: Vg = 10V , fpwm = 20kHz, ‖Lsim‖ = 0.5p.u. and 1p.u., R1 = 17Ω and L = 2.6mH. The waveforms of simulated inductor voltages are depicted in Figure 2.28. It can be found in Figure 2.28 that the AC input voltage Vg is leading the current flowing through the series inductor and resistor by 90 degrees which 32 2.5. Simulations of Electronic Loads 0.0 -5.00 -10.00 -15.00 5.00 10.00 15.00 V_Lsim (1pu) Vg 100.00 110.00 120.00 130.00 140.00 150.00 Time (ms) 0.0 -0.20 -0.40 0.20 0.40 V_sensed (1pu) V_cmd 0.0 -5.00 -10.00 5.00 10.00 V_Lsim (0.5pu) Vg 100.00 110.00 120.00 130.00 140.00 150.00 Time (ms) 0.0 -0.20 -0.40 0.20 0.40 V_sensed (0.5pu) V_cmd _Lsim (1pu) Vg V_cmd_sensed (1pu) _Lsim (0.5pu) Vg V_cmd_sensed (0.5pu) 15. 10. 5.0 0.0 -5.0 -10.0 -15. 0.4 0.2 0. -0.2 -0.4 10.0 5. 0.0 -5. -10. 0.4 0.2 0. -0.2 -0.4 100.00 110.00 120.00 130.00 140.00 150.00 100.00 110.00 120.00 130.00 140.00 150.00 Time (ms) Figure 2.28: Simulated Inductor Voltages: Vsensed is the simulated inductor voltages in per-unit system and Vcmd is the AC input voltage source in per- unit system with 90 degrees phase delay represents the inductive load characteristics. The waveforms for other ranges of the inductive simulated loads are illustrated in Figure 2.29 and 2.30. Current Ripple Waveforms From the previous discussion, when ‖Zsim‖ ≥ R1, the current ripple can be calculated using Eq.(2.42); when ‖Zsim‖ is comparable with the series resistor R1, the actual current ripple should be smaller than the calculated value. Figure 2.31 and 2.32 show the current ripples of the inductive simu- lated loads when L = 26mH and fpwm = 20kHz. As shown in these figures, the current ripple at Lsim = 10p.u. is 0.23 33 2.5. Simulations of Electronic Loads 100.00 110.00 120.00 130.00 140.00 150.00 Time (ms) 0.0 -5.00 -10.00 5.00 10.00 V_Lsim (1pu) Vg Vg V_Lsim10. 5. 0. -5. -10.0 10 . 1 0.0 12 . 1 .0 14 . 1 0.0 100.00 110.00 120.00 130.00 140.00 150.00 160.00 Time (ms) 0.0 -5.00 -10.00 5.00 10.00 V_Lsim (10pu) Vg 10. 5. 0. -5. -10. Vg V_Lsim 100.0 110.0 120.0 130.0 140.0 150.0 160.0 Time (ms) Figure 2.29: Simulated Inductor Voltages at ‖Lsim‖ = 1p.u. and 10p.u. 100.00 110.00 120.00 130.00 140.00 150.00 160.00 Time (ms) 0.0 -5.00 -10.00 5.00 10.00 V_Lsim (10pu) Vg 100.00 110.00 120.00 130.00 140.00 150.00 160.00 Time (ms) 0.0 -5.00 -10.00 5.00 10.00 V_Lsim (100pu) Vg 10. 5. 0.0 -5 -10.0 1 .0 1 . 12 . 13 . 1 .0 1 .0 1 .0 10. 5. 0.0 -5 -10 100.0 110.0 120.0 130.0 140.0 150.0 160.0 Time (ms) Vg Vg V_Lsim V_Lsim Figure 2.30: Simulated Inductor Voltages at ‖Lsim‖ = 10p.u. and 100p.u. 191.62191.64191.66191.68191.70191.72191.74 Time (ms) 325.00m 327.50m 330.00m 332.50m 335.00m 337.50m 340.00m V_Lsim (1pu) Vg ΔiL/2IL=0.21 cmd Figure 2.31: Current Ripple at Lsim = 1p.u. 208.32 208.36 208.40 208.44 Time (ms) 0.25 0.30 0.35 0.40 V_Lsim (10pu) Vg ΔiL/2IL=0.23 cmd Figure 2.32: Current Ripple at Lsim = 10p.u. which is very close to the calculated value 0.24; the current ripple at Lsim = 1p.u. is 0.21 which is smaller than the calculated value 0.24 because 1p.u. is comparable with the series resistor R1. 34 2.5. Simulations of Electronic Loads 2.5.3 Capacitive Load Simulation The control program of capacitance loads simulations is almost the same as the program used in the inductance loads simulation except that the phase angle of series inductor current iL leads that of input voltage Vg by 90 degrees instead of 90 degrees delay. Using the parameters given previously, Figures 2.33 and 2.34 show the waveforms of the different ranges of capacitive loads. 110.00 120.00 130.00 140.00 150.00 160.00 Time (ms) 0.0 -5.00 -10.00 5.00 10.00 V_Lsim (1pu) Vg 110.00 120.00 130.00 140.00 150.00 160.00 Time (ms) 0.0 -5.00 -10.00 5.00 10.00 V_Lsim (10pu) Vg VgV_Csim V_Csim (1pu) Vg VgV_Csim Csim (10pu) Vg Figure 2.33: Simulated Ca- pacitor Voltages at ‖Csim‖ = 1p.u. and 10p.u. 130.00 140.00 150.00 160.00 170.00 Time (ms) 0.0 -5.00 -10.00 5.00 10.00 V_Csim (10pu) Vg 130.00 140.00 150.00 160.00 170.00 Time (ms) 0.0 -5.00 -10.00 5.00 10.00 V_Csim (100pu) Vg VgV_Csim VgV_Csim Figure 2.34: Simulated Ca- pacitor Voltages at ‖Csim‖ = 10p.u. and 100p.u. 35 Chapter 3 Hardware Implementation Based on the theory discussed in chapter 2, a practical AC electronic load system will be built for experimental results. In this chapter, emphasis will be given on how to choose suitable components and integrate them to form a prototype of AC electronic load. 3.1 Introduction of System The whole system is depicted in Figure 3.1. It consists of a regulated DC bus, an H-bridge inverter, a current filter, an IGBT driver module, sensor circuits, a DSP control board and a power supply circuit. Isolated IGBT Driver DSP Control Board Sensor Circuits Power Supply 2 Voltage, Current and Temperature Signals Figure 3.1: Hardware System of Electronic Loads The sensor circuits sense voltage, current and temperature signals. Volt- age and current signals will be used to calculate current reference in the DSP 36 3.2. IGBT Inverter Module software, and temperature signal will be used for overheat protection. An on-board power supply with some accessorial components provides ±15V , +15V and +5V for the whole hardware system. In the following parts, each subsystem will be introduced in detail. 3.2 IGBT Inverter Module In this design, an IGBT module, MUBW 20-06 A7[4], produced by IXYS Corporation is employed to set up the H-bridge inverter. As depicted in Figure 3.2[4], the IGBT module includes a three phase full-bridge rectifier, a three phase DC-AC inverter and a NTC temperature sensor. For the application of single phase AC electronic loads, only the 3-phase inverter and NTC temperature sensor will be used. © 2004 IXYS All rights reserved 1 - 8 41 9 Converter - Brake - Inverter Module (CBI2)  Input Rectifier Bridge D11 - D16 Symbol Conditions Maximum Ratings VRRM 1600 V IFAV TC = 80°C; sine 180° 30 A IDAVM TC = 80°C; rectangular; d = 1/3 29 A IFSM TVJ = 25°C; t = 10 ms; sine 50 Hz 400 A Ptot TC = 25°C 120 W Symbol Conditions Characteristic Values (TVJ = 25°C, unless otherwise specified)  min. typ. max. VF IF = 35 A; TVJ =   25°C  1.4 1.7 V         TVJ = 125°C 1.4 V IR VR = VRRM; TVJ =   25°C 0.2 mA          TVJ = 125°C 2.0 mA t rr VR = 100 V; IF = 20 A; di/dt = -20 A/µs 1 µs  RthJC (per  diode) 1.06 K/W Three Phase Brake Chopper Three Phase Rectifier Inverter VRRM =  1600V VCES =  1200 V VCES =  1200 V IDAVM =  44 A IC25 =  35 A IC25 =  50 A IFSM =  400 A VCE(sat) =  2.3 V VCE(sat) =  2.6 V MUBW 35-12 A7 IXYS reserves the right to change limits, test conditions and dimensions. NTC  D11  D13  D15  D12  D14  D16 1 2 3  D7 T7 T1  D1 T3  D3 T2 T4 T6 T5  D4 D2  D6  D5 21 22 7 6 45 16 15 18 17 20 19 11 1023 24 14 8 9 12 13 Application: AC motor drives with ● Input from single or three phase grid ● Three phase synchronous or asynchronous motor ● electric braking operation Features ● High level of integration - only one power semiconductor module required for the whole drive ● Fast rectifier diodes for enhanced EMC behaviour ● NPT IGBT technology with low saturation voltage, low switching losses, high RBSOA and short circuit ruggedness ● Epitaxial free wheeling diodes with Hiperfast and soft reverse recovery ● Industry standard package with insulated copper base plate and soldering pins for PCB mounting ● Temperature sense included Figure 3.2: Structure of IGBT Module According to the supposed conditions of unintentional islanding test (Appendix C), a voltage rating above 120VRMS and a current rating above 8.33ARMS are required. The chosen IGBT module, MUBW 20-06 A7, which can stand up to 600V and 35A, meets these requirements. The integrated temperature sensor consists of an NTC thermistor whose resistance gets smaller with the increasing of temperature. This sensor will be used in the design to prevent IGBTs damage from overheating. 37 3.3. IGBT Driver Circuit 3.3 IGBT Driver Circuit Main purpose of the IGBT Driver is to provide enough power to the gate to make the IGBT switch properly. In this system, a compact IGBT driver module (6SD106EI) by Concept Technologie[5] was used at hand which is able to output high gate current of ±6A. This driver module can operate in two different modes: direct mode and half-bridge mode and is capable of outputting either six independent driver signals or three pairs of driver signals with dead time. Safety is another important issue in IGBT driver selection and the driver 6SD106EI integrate a short circuit and over-current protection circuit inside. 6&$/('ULYHU Data Sheet 6SD106E Page 2 Internet: www.CT-CONCEPT.com Block Diagram Viso1 VDC GND Rg Rg IGD IGD LDI Viso1 Viso2 Viso2 Electronic Level Power Isolation Power Level Semiconductor Driver onInterface on PWM oscillator Electrical SCALE Driver Module (external) Rth Rth VDD GND Fig. 1   Block diagram shows 2 channels (i.e. one third) of the 6SD106E The block diagram shows two channels (i.e. one third) of the 6SD106E six-pack driver. There is only one PWM oscillator, whereas all other components are present in triplicate. Figure 3.3: Structure of IGBT Driver Module: 6SD106EI Figure3.3[5] shows the structure of a two-channel driver on the chip set. For a three-phase version, there is only one PWM oscillator, all other components are present in triplicate. For each channel, the driver module contains the electrical isolation be- tween the control and power sides which prevents damage of control sides from high voltage and current of power sides. The internal block IGD con- tains an over-current and short-circuit protection circuit for the power tran- sistors, a feed monitoring circuit as well as a status acknowledgement circuit. 38 3.3. IGBT Driver Circuit An electrically separated power supply can provide ±15V for the drive elec- tronics via an integrated DC/DC converter. Mode Selection As mentioned above, the driver module 6SD106EI can operate in two dif- ferent modes. Two sets of complementary drive signals are needed for the H-Bridge inverter. Hence, in this specific system, the driver module will work in the half-bridge mode[5] which is able to output three pairs of com- plementary IGBT drive signals. 6&$/('ULYHU Description and Application Manual Page 20 Internet: www.CT-CONCEPT.com 0V -15V +15V +15V Gate G2 PWM Input -15V +15V Gate G1 Fig. 8   Signals curves of the circuit as per Fig. 7 Half-bridge mode with dead time In half-bridge mode, two channels are always operated as a half bridge. In this mode, the SCALE driver can generate the required dead times directly in a range from about 100ns up to several microseconds. Only two external RC n tworks are required (see page 26 for dimensioning). All power semiconductors can be turned off by switching the release input (InB) to low. Rg Rg Rth Rth + DC Link - DC Link G1 G2 E1 E2 C1 C2 Rth1 Rth2 IGD LDI GND VCC (LDI) MOD VL/Reset InA InB SO1 SO2 RC1 RC2 4k7 15k +VCC +VCC Reset PWM Input (TTL) SO Channel 1 Channel 2 SCALE Driver Module Inductive load GND Enable (TTL) 4V7 10k 10k 100p100p GNDGNDGND IGD Fig. 9   Application example for half-bridge mode with dead time generation Figure 3.4: HalfBridge Mode Selection In order to select the half-bridge mode, the pin MOD should be con- nected to GND and inputs pins of RC1 and RC2 must be connected to RC networks. The dimensioning will be discussed further in the next section. Dead Time Because any real power electronic devices do not turn on or off instanta- neously, it is necessary to include a protection time, called the dead time, to avoid cross conduction of two switching devices in the same leg of the H-bridge inverter. The dead time can be set either in DSP software or in the driver module 6SD106EI by selecting the half-bridge operation mode. In this design, the dead time is set in the driver module. In the half-bridge mode, RC networks must be connected to the pins RC1 and RC2. According to Table.3.1, 22kΩ and 150pF are selected and the dead time is set to 2.1µs. 39 3.3. IGBT Driver Circuit R C typ. dead time 10k 47pF ≈ 200ns 10k 100pF ≈ 500ns 15k 120pF ≈ 1.1µs 22k 150pF ≈ 2.1µs 33k 220pF ≈ 4.6µs Table 3.1: Values of the dead times of RC networks Short-Circuit and Over-Current Protection Every channel of the driver module is equipped with a Vce monitoring circuit as illustrated in Figure 3.5[5]. A resistor (Rthx) is connected to the pin Rthx as a reference. It defines the maximum voltage drop across the turned-on power transistor at which the protection function of the drive circuit is activated and thus the power transistor is turned off. 6&$/('ULYHU Description and Application Manual Page 28 Internet: www.CT-CONCEPT.com Pin Ex (emitter terminal) The “x” in “Ex” stands for th  number of the drive channels in multi-channel drivers. This terminal should be connected to the emitter or source terminal of the power transistor. The connection must be as short as possible and be run directly to the emitter or source terminal of the power element. This terminal should be used in modules with auxiliary emitters or an auxiliary s urce. This terminal is also used as the low end of the reference resistor Rthx. Where possible, this should be connected directly t  the terminal Ex of the river. Pi  Cx (collector sense) The “x” in “Cx” stands for the number of the drive channels in multi-channel drivers. This terminal is used to measure the voltage drop across the turned-on power transistor in order to ensure protection from short circuit and overload. It should be noted that it Rm V+V+ Ca Cx 5WK[ Gx Ex Rthx RGx Dm (2 x 1N4007) SCALE Driver Module IGD 001 4 5 150uA1,4mA OVERCURRENT MEASURING Fig. 13   Principle of the collector sense circuit Figure 3.5: Protection Circuit of Driver Module 6SD106EI If the voltage at Cx exceeds the voltage at Rthx, a Vce or under-voltage error occurs and the protection function is activated. The driver blocks the power semiconductor and accepts no drive signals. Meanwhile, the status outputs SOx (See Figure3.4, The “x” in “SOx” stands for the number of the drive channel in the driver module.) for the corresponding channels 40 3.4. Voltage Measuring Circuit are pulled to the logic low level which will be used in the DSP protection routine. The pin Cx must be never connected directly to the collector of the power transistor and a high-blocking diode is needed to protect the mea- suring terminal Cx. For 600V IGBT modules, one diode of type 1N4007 is connected to pin Cx. It is recommended that the peak repetitive reverse voltage of these diodes be over-dimensioned by at least 40%. According to the application manual of 6SD106EI, a threshold voltage Vth = 5.85V is recommended to use in IGBT drives. The reference resistor Rth can be calculated as follows: Rth = Vth 150µA = 5.85V 150µA = 39kΩ (3.1) 3.4 Voltage Measuring Circuit Voltage measuring circuit consists of a voltage sensor, voltage level shifter circuits and a voltage buffer. In the following section, these blocks will be introduced one by one in detail. Voltage Sensor Voltage is measured with a voltage transducer LV 25-P (LEM Inc.). Its range goes up to 500V which is suited for 120VRMS and the output of this sensor is a current with the ratio of 2.5 : 1 of the primary current. This module is supplied by ±15V power and the connection is depicted in Figure 3.6. Bottom view Right view Top view Dimensions  LV 25-P (in mm. 1 mm = 0.0394 inch) Remarks · IS is positive when VP is applied on terminal +HT. · This is a standard model. For different versions (supply voltages, turns ratios, unidirectional measurements...), please contact us. Mechanical characteristics · General tolerance ± 0.2 mm · Fastening & connection of primary 2 pins 0.635 x 0.635 mm · Fastening & connection of secondary 3 pins Æ  1 mm · Recommended PCB hole 1.2 mm Secondary terminals Terminal + : supply voltage + 12 .. 15 V Terminal M : measure Terminal - : supply voltage - 12 .. 15 V Connection LEM  reserves the right to carry out modifications on its transducers, in order to improve them, without previous notice. Instructions for use of the voltage transducer model LV 25-P Primary resistor R 1 : the transducer’s optimum accuracy is obtained at the nominal primary current. As far as possible, R 1 should be calculated so that the nominal voltage to be measured corresponds to a primary current of 10 mA . Example: Voltage to be measured VPN = 250 V a) R 1 = 25 kW  / 2.5 W, IP = 10 m A Accuracy = ± 0.8 % of VPN (@ TA = + 25°C) b) R 1 = 50 kW  / 1.25 W, IP =   5 m A Accuracy = ± 1.6 % of VPN (@ TA = + 25°C) Operating range (recommended) : taking into account the resistance of the primary windings (which must remain low compared to R 1, in order to keep thermal deviation as low as possible) and the isolation, this transducer is suitable for measuring nominal voltages from 10 to 500 V. Standard 00        Year  Week or N° SP.. swiss made Back view Figure 3.6: Voltage Sensor Connection For voltage measurements, a current proportional to the measured volt- ge must be passed through n external resistor R1 which is selected by the user and installed in series with the primary circuit of the transducer. In our case, R1 = 6kΩ was selected to measure 60V voltage which corresponds 41 3.4. Voltage Measuring Circuit to 10mA primary current in the testing experiments. For the real islanding test,a 17kΩ resistor will be used to measure 120VRMS voltage. Voltage Level Shifter A voltage level shifting circuit is required because the input voltage range of ADC module on the ezDSPlf2407A board used in this case is 0V − 3.3V which is different from that of the voltage sensor output. This function can be implemented with a two-level operational amplifier (OPA) circuit as shown in Figure 3.7. 5.1K R6 30K R3 12K R4 3.3K R5 100nF C1 100nF C2 150pF C3 -15i 1 2 3 CN7 VT LV 25-P -15i +15i +15i -15i VM1 2 3 1 4 1 1 1 U4A LM324AM 4 1 1 5 6 72 U4B LM324AM +15I -15I 30K R2 240 R1 1 2 N C 3 U5 LM4040A30IDBZR-3.0 4 1 1 8 10 9 3 U4C LM324AM +15i -15i  Figure 3.7: Voltage Measuring Circuit The current signal from LV 25-P is transformed into a voltage signal with R1, the range of which is −6V to 6V . The voltage across R1 is then offset with the first level OPA circuit and the output voltage of U4A is given by: Vout1 = VREF ( 1 + R3 R2 ) − VIN × R3 R2 (3.2) The voltage VREF is voltage across the precision voltage reference LM4040A and equals to 3V . Through the second level OPA circuit, the output voltage of U4B is scaled by: Vout = −R5 R4 × Vout1 (3.3) 42 3.4. Voltage Measuring Circuit Plugging in values for the components in Figure 3.7, the scaling of signals from the primary current to DSP analog voltage is illustrated in Figure 3.8. IN out1 out Current Sensor Offset Coefficient Figure 3.8: Voltage Scaling from Primary current to DSP Analog Voltage Voltage Buffer The ADC module in DSP is an unbuffered multiplexed ratiometric ADC which contains a multiplexer, a sample/hold circuit and an ADC compara- tor. This type of ADC has no internal buffer amplifiers to introduece input offset and gain errors. The structure of ADC is shown in Figure 3.9. A disadvantage of this kind of on-chip ADC is that the sample capacitor within the ADC is directly charged by the external signal, and the charge left on the sample capacitor by the previous conversion of a channel can affect the accuracy of the channel currently being converted if inadequate settling time is allowed for a given source impedance. This phenomenon is referred to as channel-to-channel crosstalk[6]. sample MUX Figure 3.9: Structure of DSP On-chip ADC 43 3.5. Current Measuring Circuit In order to avoid the crosstalk, the source impedance of input signals should be much less than the input impedance of ADC. Therefore, a voltage buffer U4C in Figure 3.7 is added to decrease the output impedance of the scaling circuit so that ADC module can work properly. 3.5 Current Measuring Circuit The current measuring circuit is mostly the same as the voltage measuring circuit except a few changes of parameters. In this case, the current is measured with a LEM current transducer LT 100-S, the range of which goes up to ±100A. The output of this module is a current with a ratio of 1 : 1000 of the primary current. With the consideration of accuracy, the current should be close to 100A. The current measuring circuit is illustrated in Figure 3.10. 5.1K R6 30K R3 12K R4 3.3K R5 100nF C1 100nF C2 150pF C3 -15i 1 2 3 CN1 CT LT 100-S -15i +15i +15i -15i CM1 2 3 1 4 1 1 1 U1A LM324AM 4 1 1 5 6 72 U1B LM324AM +15I -15I 32K R2 62 R1 1 2 N C 3 U5 LM4040A30IDBZR-3.0 4 1 1 8 10 9 3 U1C LM324AM +15i -15i  Figure 3.10: Current Measuring Circuit Substitution of parameters shown in the figure above into Eq.(3.2) and (3.3), a solution for scaling of current signals is depicted in Figure 3.11. In the testing experiments, the maximum current is below 3A and 32 turns of coil is used so that the range of measured current is close to 100A, the primary nominal current of the current sensor. 44 3.6. Temperature Sensor IN out1 out Current Sensor Offset Coefficient Figure 3.11: Current Scaling from Primary Current to DSP Analog Voltage 3.6 Temperature Sensor A temperature sensor circuit is provided on the PCB to achieve IGBT over- heat protection. The temperature sensor used in this project is an NTC thermistor integrated in the IGBT module. According to the datasheet of this module, the IGBT operating temperature has a range from −40 ◦C to 125 ◦C and the NTC thermistor resistance equals to 300Ω at 125 ◦C. Because the NTC thermistor resistance varies with temperature signifi- cantly, a circuit detecting the variation of thermistor resistance can be ap- plied for temperature sensing. In the practical application, a failure recovery from an over-heat fault will take a period of time. Therefore, a hysteresis comparator circuit shown in Figure 3.12 is used as temperature sensor circuit to aviod frequent alarms. 2 4 5 3 1 2 U3A LM339AM 1.5K R14 300 R15 5K R12 3K R13 D4 2.5v +5 +5 100nF C31 Vout R16 Vin VREF  Figure 3.12: Temperature Sensor Circuit 45 3.7. Protection Circuits As depicted in Figure 3.12, in normal conditions, the temperature keeps below 125 ◦C and the thermistor resistance R16 > 300Ω. The output of comparator U3A is zero. When the temperature rises above the maximum value, R16 is less than 300Ω and the output of U3A jumps up to high voltage level (VH = 5V ). Due to the hysteresis loop R12, the lower limit of Vin is solved by: Vin min = VREF − R16 ‖ R15 R16 ‖ R15 +R12 × VH (3.4) Substitution of parameters shown in Figure 3.4 into Eq.(3.4) yields Vin min = 2.35V , which means Vout will not drop to zero unless Vin is less than 2.35V instead of 2.5V . Convert voltage to resistance and a range of resistance from 300Ω to 338Ω can be obtained. Looking up the characteristic of thermis- tor resistance versus temperature leads to a temperature hysteresis loop in Figure 3.13. ℃ ℃ ℃ Figure 3.13: Temperature Hysteresis Loop 3.7 Protection Circuits The pin PDPINTA of ezDSPlf2407A[7] is used to prevent the system from overheat and over-current faults. If this pin is driven low, a fault occurs in DSP program and all PWM output pins will be put in the high-impedance state immediately. A logic circuit collecting all fault signals of the system is applied as an interface shown in Figure 3.14. 46 3.8. DSP Control Board Temperature Sensor 1 2 4 5 6 U1A SN74ALS21AD 6 1 U2A SN74LVC2GU04 SO_W SO_V SO_U PDPINT  Figure 3.14: System Protection Circuit The pin “Temperature Sensor” is the output of temperature sensor cir- cuit which is in high voltage level when an overheat fault occurs. In order to fit the logic level of PDPINTA, an inverter SN74LVC2GU04 is used to invert the logic level. Pins of “SO x” (x = U, V orW ) are the status pins of driver module. When an over-current fault occurs, the logic levels of “SO x” are pulled down to zero and a PDPINTA interrupt is activated in DSP program. 3.8 DSP Control Board An ezDSPlf2407A board manufactured by TI company is employed in this case as a control unit. It contains a TMS320LF2407A digital signal pro- cessor, an on-board JTAG connector which provides interface to emulators for program debugging, and other peripherals. The major features of the TMS320F2407A include: • A high-speed CPU with 40MHz clock rate and capable of processing 40 million instructions per second (MIPS). • 64K words of on-chip data/program RAM, 32K words of on-chip pro- gram ROM or Flash EEPROM, 64K words of program, 64Kwords of data and 64K words of I/O space of addressing space. • Sixteen multiplexed analog inputs 10-bit ADC core with built-in Sam- ple and Hold (S/H) circuit and fast conversion time (S/H + Con- version): 375ns. It supports up to four trigger sources for start-of- conversion (SOC) sequence and autosequencing function. • Two Event Manager (EV) modules provide a broad range of functions and features that are particularly useful in motion control and motor control applications. 47 3.9. Power Supply • 40 multiplexed general-purpose I/O pins. • Watchdog Timer which monitors software and hardware operations, and implements system reset functions upon CPU disruption. • Controller Area Network (CAN). • Serial communications interface (SCI). The EV modules in this DSP are very versatile and the major features are: • Two general-purpose (GP) timers. • Three general-purpose up and up/down timers, each with a 16-bit compare unit capable of generating one independent PWM output. • Pulse-width modulation (PWM) circuits that include space vector PWM circuits, dead-band generation units, and output logic. • Three 16-bit simple compare units capable of generating 4 independent PWM outputs. • Three capture units. • Quadrature encoder pulse (QEP) circuit. 3.9 Power Supply The printed circuit boards are supplied by a commercial switching power supply VOF-65-15. Two other commercial dc dc converters were used to provide proper supply voltage for the circuits. A 5V dc dc converter (CC10- 1205SF-E) supplies the ezDSP board, the temperature sensor circuit and the protection circuit; a ±15V supply (CC10-1212DF-E) provides power for the op amp circuits; the switching power supply (VOF-65-15) feeds the driver circuits. All these converters were equipped with the suggested input and output filters as stated in the corresponding data sheets and application notes. The input filter consists in all three cases of a Π-type filter, consisting of two capacitors and one inductor. On the output side, there are only smoothing capacitors and a zener diode, to protect devices from an unexpected over- voltage. The complete power supply circuit is shown in the Figure A.1 in the Appendix A.1. 48 Chapter 4 Software Implementation The hardware system of AC electronic loads has been described in the pre- vious chapter. In this chapter, a software applied to implement the control algorithm will be introduced in detail. All implementations of software are based on TI’s (Texas Instruments) DSP TMS320LF2407A and the associ- ated assembly language. 4.1 Program Overview As the previous introduction, the DSP TMS320LF2407A has many periph- erals and is enough for this application. The peripherals used in the control program contains: event managers (EV), general purpose timers 1 and 2, the PWM generation unit, the 16-channel ADC unit and the digital I/O ports module[8],[9],[10]. The AC electronic loads control program has several major functions: accurate voltage and current acquisition, current command calculation and PWM duty cycle update. With the consideration of software portability, the program was divided into several sub-function blocks. The flowchart of the control program is shown in Figure 4.1. The control program consists of four routines: • System initialization and Main Loop. All initializations are finished in this routine and an endless loop is waiting for different ISRs to achieve all major features of AC electronic loads. • Timer1 Interrupt service routine (ISR). This routine calculates the required current command and update PWM duty ratios. • Timer2 Interrupt service routine (ISR). Average voltage and current sampling are implemented in this routine. 49 4.1. Program Overview • PDPINTA Interrupt service routine (ISR). Over-heat and over-current protection is achieved here and makes the whole system safer and more reliable. Start System Configuration Initialize Variables and Constants Setup Watchdog and I/O Pins Setup EV, GP Timers and PWM Pins Configure ADC Interrupts Initialization Main Loop Timer1 ISR Timer2 ISR Clear INT Flags Enable Interrupts PDPINT ISR T1 ISR Start Start Timer2 and ADC First Sampling? Read ADC Data Calculate Average Values Voltage/Current Normalization Current Command Calculation PI Control PWM Duty Update Back to Main Loop Yes No T2 ISR Start Reset T2 Interrupt Read Voltage/Current Data Save Accumulation Back to Main Loop Figure 4.1: Program Flow Chart The following sections will explain the details of these routines. 50 4.2. Variables Normalization 4.2 Variables Normalization TMS320LF2407A is a 16-bit fixed-point DSP and unable to represent floating- point numbers directly. Therefore, the normalization of variables is required in the program so that the real values of voltage and current signals can be represented correctly. 4.2.1 Q Format In fixed-point DSPs, all the numbers must be represented as a collection of bits. Each bit represents either “0” or “1”, hence the number system naturally used in microprocessors is the binary system. In order to represent fractional numbers, fixed-point system requires the programmer to create a virtual decimal place in between two bit locations for a given number. Q- format is such kind of fractional fixed-point representation suitable for DSPs algorithms[11]. The labeling convention of Q-format is as follows: Q [QI] . [QF ] (4.1) Where QI is the number of integer bits and QF is the number of frac- tional bits. In a 16-bit DSP used in our system, the sum of QI and QF equals to 15 and the MSB is the sign bit. In addition and subtraction of two Q-format numbers, the fixed-point decimal places must be aligned and an appropriate dynamic range has to be chosen to handle the overflow of the addition. In multiplication, the number of integer and fractional bits in the product is the sum of the corresponding multiplier and multiplicand Q-format numbers as described the following equations: QIproduct = QImultiplicand +QImultiplier QFproduct = QFmultiplicand +QFmultiplier (4.2) 4.2.2 Normalization of Voltage and Current As mentioned above, there is a trade-off between dynamic range and preci- sion for Q-format numbers. Higher precision leads to a narrower dynamic range, hence the real voltage and current values need to be normalized and thus the Per Unit (PU) system will be applied to achieve the high precision as well as the wide dynamic range. Because the measured current in the experiments is less than 3A, 32 turns of the current will be measured to achieve higher accuracy. 51 4.3. System Initialization In this system, the base values of variables are as follows: Vbase = 30V Ibase = 100A/(4 · 32turns) = 0.78125A |Z|base = Vbase/Ibase = 38.4Ω With the consideration of both precision and dynamic range, the PU values will be represented in Q[3].[12] format (or Q12). The maximum values of current and voltage in the experiments are imax = 3.125A and Vmax = 60V . When the current reaches the maximum value, the ADC result ibinary is 512. The corresponding per-unit value of the Q-format num- ber is given by iPUQ12 = (imax/ibase) × 212 = 214, and a conversion ratio Kcurrent = iPUQ12 / ibinary = 214 / 512 = 32. All measured values of current can be converted into the PU values in Q12 format: iPUQ12 = Kcurrent × ibinary (4.3) Following the same steps, the voltage conversion ratio Kvoltage equals to 16 and the conversion formulas is vPUQ12 = Kvoltage × vbinary (4.4) 4.3 System Initialization To implement the specific functions, the initialization module performs the following tasks. 4.3.1 Event Manager Modules Initialization As mentioned above, event manager modules are the most significant func- tion blocks which provide a flexible method for controlling both dedicated I/O and shared pin functions. The following blocks are initialized in this module: PWM generation block To drive the H-bridge inverter, four PWM pins 1-4 are employed and the po- larity of PWM pins are set in Compare Action Control Register A (ACTRA) as follows: • PWM 1 and 4 are active high. 52 4.3. System Initialization • PWM 2 and 3 are active low. PWM 1-4 corresponds to switches 1-4 and “active high” means the out- put of PWM pins are set to one when a compare match happens. Addition- ally, asymmetric PWM waveforms are used in this program and associated timers are set to continuous-up count mode. General-Purpose (GP) Timers 1&2 GP timer 1 is employed in the software to control the switching frequency of PWM signals. Usually, PWM frequencies are in the range of 10kHz. In this project, a PWM frequency of 20kHz has been chosen. GP timer 2 is used to setup the voltage and current sampling frequency. In order to achieve higher precision, the sampling frequency is set to 160kHz. 4.3.2 ADC Module Initialization ADC Clock Prescaler ADC conversion time consists of two time segments: Sample/Hold (S/H) window and conversion window, as shown in Figure 4.2. The S/H window can be tailored to accommodate the variation in source impedances by the ACQ PS3-ACQ PS0 bits and the CPS bit in the ADCTR1 register. In this project, the ACQ PS3-ACQ PS0 bits are set to “0111b” and the CPS bit is set to “0b” to accommodate a 2290Ω source impedance. ADC Clock Prescaler 7-17Analog-to-Digital Converter (ADC) 7.3 ADC Clock Prescaler The S/H block in the 240xA ADC can be tailored to accomodate the variation in source impedances. This is achieved by the ACQ PS3−ACQ PS0 bits and the CPS bit in the ADCTR1 register. The analog-to-digital conversion process can be divided into two time segments, as shown in Figure 7−6. Figure 7−6. ADC Conversion Time • • • • • • S/H window (2 * PS) Conversion (11 * ACLK) 1 complete ADC conversion PS = a prescaled CPU clock PS will be the same as the CPU clock if the prescaler = 1 (i.e., ACQ PS3−ACQ PS0 bits are all zero) and if CPS = 0. For any other value of the prescaler, the magnitude of PS will be magnified (effectively increasing the S/H window time) as described by the “Acquisition Time Window” column in the bit description for ACQ PS3−ACQ PS0. If the CPS bit is made 1, the S/H window is doubled. This doubling of the S/H window is in addition to the “stretching” provided by the prescaler. Figure 7−7 shows the role played by the various prescaler bits in the ADC module. Note that PS and ACLK will be equal to CPU clock if CPS = 0. Figure 4.2: ADC Conversion Time 53 4.4. Interrupt Service Routine (ISR) ADC Conversion Sequencer The ADC module in TMS320LF2407A contains a 16-state sequencer which can perform a series of conversions without external intervention and the conversion sequence is stored in the ADC input channel select sequencing control registers (CHSELSEQn). In this project, a timer2 underflow interrupt is used as a trigger to start an auto-conversion sequencer. The number of auto-conversions is two and a single sampling of voltage and current signals is performed for each trigger. 4.3.3 I/O Ports Module Initialization The commercial driver module contains an enable pin InB (shown in Fig- ure 3.4) which is able to block all PWM channels if pulled to zero. There- fore, the PDPINTA interrupt service routine employs the digital I/O port IOPB4 as an enable pin for the commercial driver module to achieve the protection function. The pin IOPB4 is configured as an output port with the I/O mux control register A (MCRA) and set to zero when a fault occurs. 4.4 Interrupt Service Routine (ISR) As shown in Figure 4.1, three ISRs are applied to perform the current control and protection functions. Timer 1&2 ISRs The major features of Timer 1&2 ISRs have been described in Figure 4.1. Here the discussion will be focused on the time sequence between two ISRs. In these two routines, the timer underflow events are configured to generate interrupts which means an interrupt event will occur once the counter of timer 1 or 2 reaches “0000h”. PWM Figure 4.3: Timer 1 and 2 ISR Sequence 54 4.5. Generation of Sine Wave Figure 4.3 depicts the time sequence of two ISRs (TxU ISR represents the associated interrupt routine, x = 1or2). It can be seen that each un- derflow interrupt event of timer2 will perform two conversions: one is volt- age sampling and the other is current sampling. Due to the ADC auto- conversion sequencer, the pointer of the sequencer will move to the address of next two channels in the sequence. Because the frequency of timer2 is eight times of the timer1’s, 16 conversions are implemented in one PWM period and the pointer of the ADC sequence is set to the original address automatically. Additionally, timer 1 and 2 must be synchronized to keep the correct time sequence between two timers. Therefore, the timer2 is reset and started at the beginning of each T1U ISR. PDPINTA ISR With the protection circuit shown in Figure 3.14, the system is capable of monitoring the overheat and overcurrent faults. Figure 4.4 shows that the pin IOPB4 is set to low level which will block all PWM outputs of the driver module so that the whole system is able to survive a severe accident. Start PDPINTA ISR Save Interrupt Context Set IOPB4 to Zero Restore Interrupt Context End ISR Figure 4.4: Flowchart of PDPINTA ISR 4.5 Generation of Sine Wave To simulate an inductive or capacitive load with different input sources, a general approach based on LdiL/dt = vL or Cdvc/dt = ic might be possible. In each PWM switching period, ∆iL or ∆vc can be calculated using these 55 4.5. Generation of Sine Wave two equations and after comparison with the actual ∆iL or ∆vc, a new duty cycle D can be calculated and used to control the current to track the required load characteristics. However, this prototype only focuses on the 60Hz sinusoidal voltage source and thus a sine look-up table will be implemented to achieve the inductive or capacitive loads. Compared with the general approach, the sine look-up table needs less operation time. The table contains 512 words to represent sine values of phase angles in the range of [0◦, 360◦]. As a result, the resolution on phase angle of electronic loads is limited to 360/512 = 0.703125◦. In the binary system of DSP, the phase angle θ varies from 0 to 4095. As only 512 words are available to represent this range, θ is divided by 8 and stored into the variable index that will be used to address the lookup table. The content of the table row pointed by the index is fetched in indirect addressing mode via AR5 auxiliary register (Figure 4.5). This content coded in Q12 format is stored in the variable sincos that will be used in the phase angle calculation of electronic loads. 0 50 101 ... 4095 4096 4096 4096 4095 ... 101 50 0 65486 65435 ... 61441 61440 61440 61440 61441 ... 65435 65486 0 π/2 π 3π/2 2π >>3bits Index Sine Table Address θ Figure 4.5: Sine Look-up Table Note that 90◦ is added to θ to get the cosine value of the phase angle. This operation corresponds to addition of 128 (512/4) to the value of index. 56 4.6. Digital PI Control 4.6 Digital PI Control The PI controller is a generic control loop feedback mechanism widely used in industrial control systems. It is an effective approach in nearly all types of the feedback system, especially for systems containing a single pole. In our control program, a digital PI control will be implemented. An analog PI controller can be expressed by: u (t) = KP [ e (t) + 1 TI ∫ t 0 e (t) dt ] + u0 (4.5) Where KP is the proportional gain, TI is the time constant of the con- troller and thus the integral gain KI = KP /TI ; e (t) and u (t) are the input and output of the controller respectively. The proportional term means that the system responds in proportion to the deviation from the set point and determine the sensitivity of the controller to the error. A high proportional gain results in a large change in the output for a given change in the error. If the proportional gain is too high, the system can become unstable. In contrast, a small gain results in a small output response to a large input error, and a less sensitive controller. The integral term means that the system will respond in proportion to the integral of the error over time. A small time constant accelerates the movement of the process towards setpoint and eliminates the residual steady-state error that occurs with a proportional only controller. However, since the integral term is responding to accumulated errors from the past, it can cause the present value to overshoot the setpoint value. In order to implement the PI controller in a DSP, it has to be converted into digital form. A common way of doing this is to discretize the controller to approximate the continuous time derivatives as follows: uk = KP ek + Tpwm TI k∑ j=0 ej + u0 (4.6) Where k represents the kth sampling, Tpwm is the switching period and u0 is the initial value of the output. Considering the kth and (k − 1)th samplings, the change of output at the kth sampling can be derived: ∆uk = uk − uk−1 = KP (ek − ek−1) + TpwmKIek (4.7) Upon collecting items, one obtains uk = uk−1 + (KP + TpwmKI) ek −KP ek−1 (4.8) 57 4.7. RLC Algorithm With Eq.(4.8), a digital PI controller can be implemented easily in the DSP program. Additionally, a saturation block is also implemented in the program to protect the control system from the integration saturation. 4.7 RLC Algorithm The device we designed outputs different kinds of load characteristics by controlling the inductor current. Hence, a current command calculation block shown in Figure 4.1 is required for different electronic loads and the algorithms of different loads will be described here. For the resistive loads, the current command calculation is quite straight- forward and easy to implement in the DSP program. As a resistor, the current flowing through and the voltage across it are in phase, and thus the inductor current iL is proportional to the source voltage Vg at each sampling point. Therefore, in the software, the current command can be obtained by simply dividing Vg by the simulated resistor Rsim. When it comes to the inductive or capacitive loads, however, such a simple algorithm couldn’t be used any more due to the phase difference between iL and Vg. Because the inductive and the capacitive loads have similar V − I characteristics, only the algorithm of the inductive loads will be discussed here in detail. Phase Detection Block In order to simulate the inductance V − I characteristic with respect to the reference voltage Vg, it is necessary to detect the phase angle of Vg so that the control software can output the correct current with 90-degree phase delay (90-degree lead for the capacitance loads). In our program, the first cycle of Vg is used for phase detection without any other operations. As shown in Figure 4.6, checking the zero points of Vg is an effective approach of the phase detection. In the program, two variables are defined to save the previous and current voltage values: V1 is the old value and V2 is the current value. When V1 > 0 and V2 ≤ 0, Z1 can be found and the phase angle is 90◦ (vg = Vg × cos (ωt)); when V1 < 0 and V2 ≥ 0, Z2 can be found and the phase angle is 270◦. Once the zero-crossing and the phase angle are detected, the correct phase shift φ can be generated using ωt+ φ (φ = 90◦ for the inductive loads). 58 4.7. RLC Algorithm 1 2 g L 1 2 2 1 Figure 4.6: Phase Detection Diagram Frequency Detection Block In the first cycle of Vg, the frequency is also detected to calculate the phase angle using θ = ωt. Digitalizing this equation, one obtains θ = ω ·∆t = 2pif ·N · Tpwm (4.9) Where f is the frequency of Vg, Tpwm is the switching period and N repre- sents the Nth switching cycle. The frequency f also equals f = 1 Nperiod × Tpwm (4.10) Where Nperiod represents the period of Vg which can be got by Nperiod× Tpwm. Insert Eq.(4.10) into Eq.(4.9) and θ can be derived θ = 2pi × N Nperiod (4.11) In the program, once the first zero point of Vg is found, a counter FRQ CNT will be started immediately until the second zero point occurs and the period Nperiod is equal to 2 × FRQ CNT . Then, the phase angle can be derived using Eq.(4.11) and the program will start to generate the correct current command from the second zero point. Magnitude Detection Block The current command icmd equals Icmd · cos (ωt+ φ), where Icmd is the magnitude of the current and can be obtained by Icmd = ‖Vg‖ ‖Z‖ (4.12) 59 4.7. RLC Algorithm Z represents the impedance of the inductive load (or the capacitive load) and the voltage magnitude can be detected in the first cycle of Vg by checking the maximum value of Vg. Figure 4.7 shows the flowchart of the current calculation block. The variable PhD FLAG indicates whether the phase detection is finished or not and the program will jump over the current calculation block unless PhD FLAG 6= 0. PhaseDetection Start 1st. Zero Point Found? FRQ_CNT ++ Save |Vg|max If larger than the previous value Calculate Icmd Using Sine Look-up Table 2nd. Zero Point Found? END PhD_FLAG=0? No Yes Yes No Yes No Figure 4.7: The Flow Chart of the Current Calculation Block 60 Chapter 5 Experimental Results In the previous discussions, the principles, hardware and software imple- mentations of this AC electronic load system have been introduced in detail. The following chapter will show a series of experimental results to prove the principles and real hardware system. 5.1 Experimental Conditions On the basis of theory study and software simulation a prototype is re- searched and developed shown in Figure 5.4.  Figure 5.1: Control Cir- cuit Board  Figure 5.2: Power Circuit Board  Figure 5.3: The Whole Circuits  Figure 5.4: Experimental System 61 5.2. Resistive Load Results The experimental system consists of: • A system control board including: voltage and current sensor circuits, protection circuits, an ezDSP board and power supply circuits. • A IGBT-based power board containing: an IGBT driver circuit and an H-bridge IGBT inverter. • A 3-phase AC source and a 3-phase transformer used to adjust the voltage level of AC source. • A DC power supply HPD 30-10 by XANTREX which can provide 60V and 3A DC source • Two series inductors, 2.6mH and 26mH, are used for ripple studies. • A 315Ω power resistor is used as the parallel resistor. In the experiments, a 4-channel 500MHz Oscilloscope ( Lecroy 6050A) is used to measure and save the results. 5.2 Resistive Load Results With the consideration of simplicity and typicality, the electronic load ex- periments will start with resistance loads. The peak voltage of AC source Vgpeak = 10V , the voltage ratio k = 1.3 and thus DC bus voltage Vdc = 13V . 5.2.1 The Range of Resistance Loads at L = 2.6mH In the PSIM simulations, it is found that the value of the series inductor L has to be changed with the variation of electronic load impedances. Accord- ing to Table 2.8, an inductor of 2.6mH is selected to achieve resistance load experiments, the range of which is from 0.5p.u. to 2p.u.. The experimental results are depicted in Figure 5.5 to 5.10. The variable VRsim shown in following figures represents the voltage across Rsim which is calculated by VRsim = iL × Rsim and supposed to equal to the AC source Vg. It can be seen that VRsim is mostly same as Vg, both in magnitude and in phase. On the other hand, the current ripple increases with increasing of Rsim and introduces more high frequency interference. The current ripples for different Rsims can be obtained in the following Figures 5.6, 5.8 and 5.10. 62 5.2. Resistive Load Results -0.1 -0.08 -0.06 -0.04 -0.02 0 -10 -5 0 5 10 VRsim and Vg (Rsim = 0.5pu) V R si m  (V )   -0.1 -0.08 -0.06 -0.04 -0.02 0 -10 -5 0 5 10 Time (seconds) V g  (V )   Figure 5.5: Rsim = 0.5p.u. at fpwm = 20kHz -0.0634 -0.0633 -0.0632 -0.0631 -0.063 -0.0629 -0.0628 -9 -8 -7 -6 -5 -4 VRsim and Vg (Rsim = 0.5pu) V R si m  (V ) -0.0634 -0.0633 -0.0632 -0.0631 -0.063 -0.0629 -0.0628 -10 -8 -6 -4 Time (seconds) V g  (V ) ΔiL/2IL =0.22 ΔVg/Vg =0.26 Figure 5.6: Current Ripple at Rsim = 0.5p.u. -0.1 -0.08 -0.06 -0.04 -0.02 0 -15 -10 -5 0 5 10 15 VRsim and Vg (Rsim = 1pu) V R si m  (V ) -0.1 -0.08 -0.06 -0.04 -0.02 0 -15 -10 -5 0 5 10 15 Time (seconds) V g  (V ) Figure 5.7: Rsim = 1p.u. at fpwm = 20kHz -0.0304 -0.0303 -0.0302 -0.0301 -0.03 -0.0299 -0.0298 -10 -8 -6 -4 VRsim and Vg (Rsim = 1pu) V R si m  (V ) -0.0304 -0.0303 -0.0302 -0.0301 -0.03 -0.0299 -0.0298 -10 -9 -8 -7 -6 -5 Time (seconds) V g  (V ) ΔiL/2IL=0.33 ΔVg/Vg =0.18 Figure 5.8: Current Ripple at Rsim = 1p.u. -0.1 -0.08 -0.06 -0.04 -0.02 0 -15 -10 -5 0 5 10 15 VRsim and Vg (Rsim = 2pu) V R si m  (V ) -0.1 -0.08 -0.06 -0.04 -0.02 0 -15 -10 -5 0 5 10 15 Time (seconds) V g  (V ) Figure 5.9: Rsim = 2p.u. at fpwm = 20kHz -0.0359-0.0358-0.0357-0.0356-0.0355-0.0354-0.0353-0.0352-0.0351-0.035 -15 -10 -5 VRsim and Vg (Rsim = 2pu) V R si m  (V ) -0.0359-0.0358-0.0357-0.0356-0.0355-0.0354-0.0353-0.0352-0.0351-0.035 -11 -10 -9 -8 -7 Time (seconds) V g  (V ) ΔiL/2IL=0.42 ΔVg/Vg =0.22 Figure 5.10: Current Ripple at Rsim = 2p.u. 63 5.2. Resistive Load Results Table 5.1 shows the comparisons of current ripple between the results of PSIM simulations and the experimental results. It can be seen that the experimental results have 30% to 40% error with respect to the simulation results. The main reason is because of the noise introduced by the AC source Vg and the noise ∆Vg/Vg shown in Figure 5.6, 5.8 and 5.10 is around 20%. Rsim(p.u.) Simulation Results Experimental Results Error(%) 0.5 0.13 0.22 40.9 1.0 0.19 0.33 42.4 2.0 0.30 0.42 28.6 Table 5.1: Comparisons of Current Ripple between Simulation Results and Experimental Results 5.2.2 Switching Frequency and Current Ripple According to Eq.(2.33), the PWM switching frequency is inversely propor- tional to the current ripple. In this section, the effect of fpwm will be studied at 10kHz and 20kHz separately and Rsim is set to 2p.u.. Figures 5.11 to 5.14 show the current ripples at different frequencies. -0.1 -0.08 -0.06 -0.04 -0.02 0 -20 -10 0 10 20 VRsim and Vg (Rsim = 2pu & fpwm = 10kHz) V R s i m  ( V ) -0.1 -0.08 -0.06 -0.04 -0.02 0 -10 0 10 Time (seconds) V g  ( V ) Figure 5.11: Rsim = 2p.u. at fpwm = 10kHz and L = 2.6mH -0.032 -0.0318 -0.0316 -0.0314 -0.0312 -0.031 -20 -15 -10 -5 0 5 VRsim and Vg (Rsim = 2pu & fpwm = 10kHz) V R si m  (V ) -0.032 -0.0318 -0.0316 -0.0314 -0.0312 -0.031 -10 -8 -6 Time (seconds) V g  (V ) ΔVg/Vg =0.25 ΔiL/2IL=0.95 Figure 5.12: Current Ripple at Rsim = 2p.u. and fpwm = 10kHz Table 5.2 shows the comparisons of experimental results at different switching frequencies. It can be derived that the current ripple at 10kHz is about 2.6 times of the ripple at 20kHz.Considering the measurement errors 64 5.2. Resistive Load Results -0.1 -0.08 -0.06 -0.04 -0.02 0 -10 0 10 VRsim and Vg (Rsim = 2pu & fpwm = 20kHz) V R s i m  ( V ) -0.1 -0.08 -0.06 -0.04 -0.02 0 -10 0 10 Time (seconds) V g  ( V ) Figure 5.13: Rsim = 2p.u. at fpwm = 20kHz and L = 2.6mH -0.0354-0.0353-0.0352-0.0351-0.035-0.0349-0.0348-0.0347-0.0346-0.0345 -15 -10 -5 VRsim and Vg (Rsim = 2pu & fpwm = 20kHz) V R si m  (V ) -0.0354-0.0353-0.0352-0.0351-0.035-0.0349-0.0348-0.0347-0.0346-0.0345 -12 -10 -8 -6 Time (seconds) V g  (V ) ΔiL/2IL=0.42 ΔVg/Vg =0.22 Figure 5.14: Current Ripple at Rsim = 2p.u. and fpwm = 20kHz and the noise introduced by Vg, the experimental result agrees well to the theoretical value “2 times”. fPWM (kHz) Simulation Results Experimental Results Error(%) 10 0.6 0.95 36.8 20 0.3 0.42 28.6 Table 5.2: Comparisons of Current Ripple at 20kHz 5.2.3 Series Inductor L and Current Ripple The inductance of the series inductor L is also supposed to be inversely proportional to the current ripple and the associated experimental results are illustrated in Figure 5.15 to 5.18 to prove this relationship. For the experiments, two inductors of 2.6mH and 26mH are selected and the switching frequency equals to 20kHz and Rsim is still set to 2p.u.. It can be seen that the current ripple with the 2.6mH inductor is 7.7 times of the current ripple with the 26mH inductor which has about 20% error compared with the theoretical value “10 times”. With the consider- ation of measurement errors and the noise of the input source, the series inductance is inversely proportional to the current ripple(Table 5.3). 65 5.2. Resistive Load Results L(mH) Simulation Results Experimental Results Error(%) 26 0.03 0.06 50.0 2.6 0.30 0.46 34.8 Table 5.3: Comparisons of Current Ripple at 20kHz -0.1 -0.08 -0.06 -0.04 -0.02 0 -10 0 10 VRsim and Vg (Rsim = 2pu & L = 2.6mH) V R s i m  ( V ) -0.1 -0.08 -0.06 -0.04 -0.02 0 -10 0 10 Time (seconds) V g  ( V ) Figure 5.15: L = 2.6mH, Rsim = 2p.u. and fpwm = 20kHz -0.0354 -0.0352 -0.035 -0.0348 -0.0346 -0.0344 -15 -10 -5 VRsim and Vg (Rsim = 2pu & L = 2.6mH) V R si m  (V ) -0.0354 -0.0352 -0.035 -0.0348 -0.0346 -0.0344 -12 -10 -8 -6 Time (seconds) V g  (V ) ΔVg/Vg =0.22 ΔiL/2IL=0.46 Figure 5.16: Current Ripple at L = 2.6mH -0.1 -0.08 -0.06 -0.04 -0.02 0 -10 -5 0 5 10 VRsim and Vg (Rsim = 2pu & L = 26mH) V R s i m  ( V ) -0.1 -0.08 -0.06 -0.04 -0.02 0 -10 -5 0 5 10 Time (seconds) V R s i m  ( V ) Figure 5.17: L = 26mH, Rsim = 2p.u. and fpwm = 20kHz -0.048 -0.0478 -0.0476 -0.0474 -0.0472 -0.047 -9 -8 -7 -6 VRsim and Vg (Rsim = 2pu & L = 26mH) V R si m  (V ) -0.048 -0.0478 -0.0476 -0.0474 -0.0472 -0.047 -10 -9 -8 -7 -6 -5 Time (seconds) V R si m  (V ) ΔiL/2IL=0.06 ΔVg/Vg =0.18 Figure 5.18: Current Ripple at L = 26mH 66 5.3. Inductive Load Results 5.3 Inductive Load Results The principles and PSIM simulations of inductance have been introduced previously and the experimental results will be shown in this section. From Table 2.9, the parameters for different inductance ranges can be found. Here, two inductors of 2.6mH and 26mH are selected, the switching frequency is 20kHz and the DC bus voltage Vdc = 1.5× Vg. The range of Inductance loads at L = 2.6mH First of all, the range of inductance loads at L = 2.6mH will be depicted in Figures 5.19 and 5.20. -0.1 -0.08 -0.06 -0.04 -0.02 0 -6 -4 -2 0 2 4 6 Time (seconds) V o l t a g e  ( V ) VLsim and Vg (0.5pu)   VLsim Vg Figure 5.19: Lsim = 0.5p.u. at fpwm = 20kHz -0.1 -0.08 -0.06 -0.04 -0.02 -6 -4 -2 0 2 4 6 Time (seconds) V o l t a g e  ( V ) VLsim and Vg (1pu)   VLsim Vg Figure 5.20: Lsim = 1p.u. at fpwm = 20kHz 67 5.3. Inductive Load Results The variable VLsim in the figures represents the voltage across Lsim and can be calculated by VLsim = iL × ‖Lsim‖. It can be found that the mag- nitude of VLsim is mostly equal to Vg’s and has 90 degrees phase delay to Vg. Similarly with the resistance loads, the current ripple goes up with the increasing of the impedance Lsim. Series Inductor L and Current Ripple In order to obtain better performance, the current ripple should be reduced to a certain range and the most efficient method is increasing the series inductance. In the experiments, 2.6mH and 26mH inductors are used sep- arately to show the improvement on current ripples (Figure 5.21 to 5.24) Figure 5.21: L = 2.6mH ,Lsim = 1p.u. and fpwm = 20kHz Figure 5.22: L = 26mH ,Lsim = 1p.u. and fpwm = 20kHz -0.0885 -0.0885 -0.0884 -0.0884 -0.0883 2 3 4 5 6 Time (seconds) Vo lta ge  (V ) VLsim and Vg (1pu)   ΔiL/2IL=0.5 VLsim and Vg (2.6mH 1pu) Figure 5.23: Current Ripple at L = 2.6mH -0.0954 -0.0953 -0.0953 -0.0952 4.2 4.3 4.4 4.5 4.6 4.7 Time (seconds) Vo lta ge  (V ) VLsim and Vg   VLsim Vg VLsim and Vg (26mH 1pu) ΔiL/2IL=0.05 Figure 5.24: Current Ripple at L = 26mH It can be seen in the figures above that the current ripple decreases significantly with the increasing of series inductance. The current ripple at 68 5.4. Capacitive Load Results L = 2.6mH is 10 times of the ripple at L = 26mH, which means the current ripple is inversely proportional to the series inductance. 5.4 Capacitive Load Results The capacitance loads have the same features as the inductance loads and the only difference is that the phase angle of capacitance loads leads the AC source Vg by 90 degrees instead of 90 degrees delay. The following figures depict the range of capacitance loads at L = 2.6mH. -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 -6 -4 -2 0 2 4 6 Time (seconds) V o l t a g e  ( V ) VCsim and Vg (0.5pu)   VCsim Vg Figure 5.25: Csim = 0.5p.u. at fpwm = 20kHz -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 -6 -4 -2 0 2 4 6 Time (seconds) V o l t a g e  ( V ) VCsim and Vg (1pu)   VCsim Vg Figure 5.26: Csim = 1p.u. at fpwm = 20kHz Figures 5.27 to 5.30 show the the relationship between current ripple and series inductance. From the experimental results, it can be derived that the 69 5.4. Capacitive Load Results current ripple is inversely proportional to the series inductance as same as the conclusion of inductive loads. Figure 5.27: L = 2.6mH ,Csim = 1p.u. and fpwm = 20kHz Figure 5.28: L = 26mH ,Csim = 1p.u. and fpwm = 20kHz -0.0397 -0.0397 -0.0396 1 2 3 4 Time (seconds) Vo lta ge  (V ) VCsim and Vg (1pu)   VCsim Vg ΔiL/2IL=0.95 VLsim and Vg (2.6mH 1pu) Figure 5.29: Current Ripple at L = 2.6mH -0.0774 -0.0774 -0.0773 -0.0772 -0.0772 4 4.2 4.4 4.6 4.8 Time (seconds) Vo lta ge  (V ) VCsim and Vg (26mH 1pu)   VCsim Vg ΔiL/2IL=0.1 VLsim and Vg (2.6mH 1pu) Figure 5.30: Current Ripple at L = 26mH 70 Chapter 6 Conclusions and Future Work In this thesis, a DSP-controlled programmable AC electronic loads used in the unintentional islanding test has been implemented. A number of issues regarding the principles and the specifications of electronic loads have been investigated. In this final chapter a summary of the contributions contained in this thesis is made and some conclusions from this work are also presented. In the final section ideas for extending the results of this thesis are presented. 6.1 Synopsis The chapter 2 introduced the basic principles of the AC electronic loads designed in this project. A schematic of AC electronic loads based on the H-bridge dc-dc converter with a regulated DC bus voltage was presented first. Then, some theoretical analysis of the limitations of this circuit was developed and the relationship between the parameters of the circuit and the range of the electronic loads was introduced to determine the specifications of this circuit for different electronic loads. At the end, some simulations using PSIM were performed to verify the specifications for different ranges of electronic loads obtained from the principles. Additionally, the ac small- signal model of this system was derived and a set of PI parameters was obtained using MATLAB and PSIM. In the following chapter the hardware implementation was presented in detail. The features of the main parts, such as the IGBT module, the driver module and the ezDSP board, were introduced as well as the configura- tions of these parts. Then, the voltage and current measuring circuits, the temperature sensor and the protection circuits were presented. The chapter 4 described the realization of the control program on TI’s DSP TMS320LF2407A. At the beginning, a Q-format floating point rep- resentation for the fixed-point DSP was introduced and the normalization of voltage and current in the per-unit system was developed. A digital PI 71 6.2. Conclusions control program was also presented here. At the end, the current control algorithm for different types of loads was described. The chapter 5 showed the experimental results for different loads and conditions. The current ripples of the experimental results were analyzed and matched well with the theoretical analysis in the chapter 2. 6.2 Conclusions This thesis has explored the design of an AC electronic loads used for the unintentional islanding test and a real hardware system has been developed and tested with a 60Hz AC voltage source. According to the experimental results, it is proved that this system is able to simulate different types of loads and in this project it was programmed to simulate resistive, inductive and capacitive loads. In order to simulate a complex circuit, some minor modifications of the current command calculation algorithm are required. Therefore, this device could work as a programmable AC electronic loads for the real unintentional islanding test. However, because this system is based on an H-bridge inverter and works in the switching mode, the current ripple is much higher than that of the traditional electronic load which works in the linear mode.  August 08                                      Tel: 408.830.9742 • Fax: 408.830.9749 • www.aosmd.com  1            Start-Up Test Using Electronic Load Zach Zhang, Alph  & Omega Semiconductor, Inc.  1. Introduction to Electronic Load  Electronic loads, such as Chroma 6310 series, can be configured as constant current (CC) mode, constant voltage (CV) mode and constant resistance (CR) mode. In CC mode, the load will sink a current in ac o dance with the programmed value regardless of input voltage. In CV mode, the load will sink current to control the voltage source in programmed value. In CR mode, the load sinks a current linearly proportional to the input voltage in accordance with the programmed resistance. Int rnal feedback control ircuit contr ls the load current based on its mode set up and input voltage.  A simplified electronics load diagram is shown in Figure 1. Use CC mode as example, Iset is the load current set value. Isense is the actual load current sense signal. The feedback circuit consists of error amplifier and feedback network Zf. The amplifier compares the Iset and Isense, the output signal is used to control power transistor Q1 base voltage. As a result, the power transistor Q1 only pulls current Iload equal to Iset, into the electronic load. When Iload < Iset, feedback circuit will turn on Q1 harder to pull more current until Iload = Iset. When Iload > Iset, feedback circuit will turn on Q1 less to pull less current until Iload = Iset.    Figure 1: Simplified electronics load diagram  Besides operation modes, there are other parameters that need to be programmed before each use. They are Turn-on Voltage (Von), Von Latch switch and Slew Rate, etc. The electronic load starts to sink current when the input voltage reaches Von voltage. Enabled Von latch means the load will sink current continuously when the input voltage reaches Von voltage. Disabled Von latch means the load will stop sinking current when its input voltage is below Von voltage level. The slew rate is defined as current change over time. Regardless the input voltage, the load will sink current at programmed slew rate.  Application Note PIC-004 Figure 6.1: Simplified Electronic Load Diagram Figure 6.1 shows the simplified structure of the traditional electronic load. Iset is the load current set value. Isense is the actual load current 72 6.3. Suggestions for Future Work sense signal. The feedback circuit consists of error amplifier and feedback network Zf . The amplifier compares the Iset and Isense, the output signal is used to control power transistor Q1 base voltage. As a result, the power transistor Q1 only pulls current Iload equal to Iset, into the electronic load. When Iload < Iset, feedback circuit will turn on Q1 harder to pull more current until Iload = Iset. When Iload > Iset, feedback circuit will turn on Q1 less to pull less current until Iload = Iset. Therefore, a combination of the switching mode and the linear mode might be a better solution for the higher accuracy requirement (shown in Figure 6.2). The switching mode block could track the required load char- acteristics and the linear mode block can compensate the current ripple induced by the switching operation to achieve the smoother load character- istics. AC Iload Switching Mode Linear Mode Figure 6.2: Combination Electronic Load Diagram 6.3 Suggestions for Future Work It has been proved that the system designed in this thesis is able to work as an electronic load. But in order to finish the real unintentional islanding test, there is still a lot of work to do. • A DC power supply which can output up to 220V is required for the real islanding test. As the previous analysis, the system need a 73 6.3. Suggestions for Future Work regulated DC bus voltage. Therefore, the islanding test needs a high voltage DC power supply to provide a high enough DC bus voltage. • A three-phase four-leg inverter is required for the three-phase uninten- tional islanding test. In our design, the system is an H-bridge inverter which is only able to do the single phase islanding test. For the three- phase test, a four-leg inverter should be used and the schematic is shown in the Appendix B. • The output filter has to be designed for the real test. Due to the switching parts are used in the circuit, a lot of high frequency inter- ference is introduced. But in the real islanding test, too much noise will lead to the testing failure. Therefore, an output filter is needed to reduce the high frequency noise. (Shown in the Appendix B) • A phase-locked loop (PLL) circuit is required for the frequency detec- tion. In our design, the frequency detection was implemented in the DSP program. However, it is not very accurate and unable to per- form a real-time frequency detection. The PLL circuit can detect the real-time frequency of the applied voltage source and provide a high precision. • Modify the current calculation algorithm for the islanding test. The islanding test requires a variable LC circuit with respect to the differ- ent output reactive power generate by the device under test. So a new current calculation algorithm has to be implemented. 74 Bibliography [1] Niklas Strath. Islanding Detection in Power Systems. Lund University, 2005. [2] Konrad Mauch Wilsun Xu and Sylvain Martel. An Assessment of Distributed Generation Islanding Detection Methods and Issues for Canada. CETC-Varennes, 2004. [3] Robert W. Erickson and Dragan Maksimovic. Fundamentals of Power Electronics. Springer, 2000. [4] MUBW20-06A7 Datasheet. IXYS Corporation, 2004. [5] Six-pack SCALE Driver 6SD106E for IGBTs and Power MOSFETs. CONCEPT: www.IGBT-Driver.com, 2000. [6] Alex Tessarolo. SPRA989A: F2810, F2811, and F2812 ADC Calibra- tion. Texas Instruments, 2004. [7] TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals. Texas Instruments, 2006. [8] TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruc- tion Set. Texas Instruments, 1999. [9] TMS320C1x/C2x/C2xx/C5x Assembly Language Tools: User’s Guide. Texas Instruments, 1995. [10] David M. Alter. Getting Started in C and Assembly Code With the TMS320LF240x DSP. Texas Instruments, 2002. [11] Erick L. Oberstar. Fixed-Point Representation and Fractional Math. Oberstar Consulting, 2007. 75 Appendix A Schematics A.1 Schematics of Control Board 76 A.1. Schematics of Control Board 1 2 3 4 C N 1 +1 5 +1 5 10 uF C6 10 uF C7 10 uF C 8 10 uF C9 10 uF C1 0 10 uF C3 10 uF C1 2 10 uF C 11 10 uF C4 10 uF C5 3. 5u H L1 +V in 1 RC 2 -V ou t 4 Co m 5 Tr im 6 +V ou t 7 -V in 3 C C1 C C1 0- 12 12 D F- E 10 uFC2 10 uFC1 4 0. 1u F C1 0. 1u F C1 3 D 1 16 V D 2 16 V +1 5i -1 5i +1 5 10 uF C2 01 0u F C 21 10 uF C 22 10 uF C2 31 0u F C 24 10 uF C1 7 10 uF C2 6 10 uF C 25 10 uF C1 81 0u F C 19 3. 5u H L2 +V in 1 RC 2 N C 4 -V ou t 5 Tr im 6 +V ou t 7 -V in 3 C C2 C C1 0- 12 05 SF -E 10 uFC1 6 0. 1u F C1 5 D 3 5V +5  Figure A.1: PowerSupply AD.SCHDOC 77 A.1. Schematics of Control Board 5.1K R20 30K R17 12K R21 3.3K R19 100nF C33 100nF C34 150pF C32 -15i 1 2 3 CN7 -15i +15i +15i -15i VM1 30K R23 12K R26 3.3K R25 150pF C35 1 2 3 CN8 -15i +15i VM2 30K R28 12K R31 3.3K R30 100nF C37 100nF C38 150pF C36 1 2 3 CN9 -15i +15i +15i -15i VM3 2 3 1 4 11 1 U4A LM324AM 4 11 5 6 72 U4B LM324AM 4 11 8 10 9 3 U4C LM324AM 4 11 14 12 13 4 U4D LM324AM 2 3 1 4 11 1 U6A LM324AM 4 11 5 6 72 U6B LM324AM +15I +15I +15I -15I -15I -15I -15I +15I 30K R18 Res1 30K R24 30K R29 240 R16 Res1 240 R22 Res1 240 R27 Res1 1 2 N C 3 U5 LM4040A30IDBZR-3.0 4 11 8 10 9 3 U3C LM324AM 4 11 14 12 13 4 U3D LM324AM 4 11 8 10 9 3 U6C LM324AM +15i -15i +15i -15i +15i -15i  Figure A.2: VoltageSensor.SCHDOC 78 A.1. Schematics of Control Board 5.1K R5 30K R2 12K R6 3.48K R4 100nF C28 100nF C29 150pF C27 -15i 1 2 3 CN2 -15i +15i +15i -15i CM1 30K R8 12K R11 3.48K R10 150pF C30 1 2 3 CN3 -15i +15i CM2 2 3 1 4 1 1 1 U1A LM324AM 4 1 1 5 6 72 U1B LM324AM 4 1 1 8 10 9 3 U1C LM324AM 4 1 1 14 12 13 4 U1D LM324AM -15I -15I -15I +15I +15I +15I 1 2 N C 3 U2 LM4040A30IDBZR-3.0 62 R1 Res1 62 R7 Res1 32K R9 Res1 32K R3 Res1 2 3 1 4 1 1 1 U3A LM324AM 4 1 1 5 6 72 U3B LM324AM +15i -15i +15i -15i  Figure A.3: CurrentSensor.SCHDOC 79 A.1. Schematics of Control Board 2 45 312 U 3A LM 33 9A M 1. 5K R 14 30 0 R 15 5K R 12 3K R 13 D 4 2. 5v +5 +5 +1 5 +5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 JP 1 CM 1 CM 2 V M 1 V M 2 V M 3 1234 CN 6 H ea de r 4 +5 12 CN 5 10 0n F C3 1 FR Q CN FR Q C N SW SW TM P TM P TM P9 TM P9 1234 CN 4  Figure A.4: TMPSensor.SCHDOC 80 A.2. Schematics of Power Board A.2 Schematics of Power Board G N D 1 U _S O 2 2 U _M od 3 U _R C2 4 U _I nB 5 U _I nA 6 U _R C1 7 U _V L 8 U _S O 1 9 G N D 10 G N D 11 V D C 12 V D C 13 V _S O 2 14 V _M od 15 V _R C2 16 V _I nB 17 V _I nA 18 V _R C1 19 V _V L 20 V _S O 1 21 G N D 22 G N D 23 V D D 24 V D D 25 W _S O 2 26 W _M od 27 W _R C2 28 W _I nB 29 W _I nA 30 W _R C1 31 W _V L 32 W _S O 1 33 G N D 34 W _G 1 35 W _E 1 36 W _R th 1 37 W _C 1 38 Fr ee 39 Fr ee 40 W _G 2 41 W _E 2 42 W _R th 2 43 W _C 2 44 Fr ee 45 Fr ee 46 V _G 1 47 V _E 1 48 V _R th 1 49 V _C 1 50 Fr ee 51 Fr ee 52 V _G 2 53 V _E 2 54 V _R th 2 55 V _C 2 56 Fr ee 57 Fr ee 58 U _G 1 59 U _E 1 60 U _R th 1 61 U _C 1 62 Fr ee 63 Fr ee 64 U _G 2 65 U _E 2 66 U _R th 2 67 U _C 2 68 Co nc ep t1 6S D 10 6E R2 4. 7K R3 22 K 22 K R4 4. 7K R5 4. 7K R1 2 2KR6 22 K R7 4. 7K R8 4 .7 K R9 2 2K R1 0 22 K R1 1 4. 7K R1 2 39 K R1 3 18 0 R1 4 3 9K R1 5 1 80 R1 6 3 9K R1 7 18 0 R1 8 3 9K R1 9 1 80 R2 0 3 9K R2 1 18 0 R2 2 3 9K R2 3 1 80 R2 4 15 0p F C3 15 0p F C4 15 0p F C5 15 0p F C6 15 0p F C7 15 0p F C8 D 2 4V 7 D 3 4V 7 D 4 4V 7 D 5 D 6 D 7 D 8 D 9 D 10 +1 5 +1 5 +1 5 +5 +1 5 +1 5 +1 5 +5 +1 5 +1 5 +1 5 +5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 JP 1 U C1 U C2 U G 1 U G 2 U E1 U E2 V C1 V C2 V G 1 V G 2 V E1 V E2 W C1 W C2 W G 1 W G 2 W E1 W E2 +5 +1 5 10 uF C1 0. 1u F C2 D 1 16 V 1234 P1 H ea de r 4 +5 12 P2 H ea de r 2 TM P9 TM P TM P 14 7 1245 6 U 1A SN 74 A LS 21 A D D 22 15 V D 21 15 V D 20 15 V D 19 15 V D 18 15 V D 17 15 V D 15 15 V D 14 15 V D 13 15 V D 12 15 V D 11 15 V D 16 15 V 6 1 U 2A SN 74 LV C2 G U 04  Figure A.5: Driver.SCHDOC 81 A.2. Schematics of Power Board 11 22 33 4 4 5 5 6 6 7 7 8 8 9 9 1010 1111 1212 1313 1414 1515 1616 1717 1818 1919 2020 2121 2222 2323 2424 Inv1 MUBW20-06A7 TMP9 1 2 3 JP2 1 2 3 JP3 UC1 UC2 UG1 UG2 UE1 UE2 VC1 VC2 VG1 VG2 VE1 VE2 WC1 WC2 WG1 WG2 WE1 WE2 2700uF C9 * 1.5uF C10 * 1.5uF C11 * +5 5 R25 Thermistor  Figure A.6: MUBW20.SCHDOC 82 A.3. PCB Layouts A.3 PCB Layouts Figure A.7: Control Board PCB 83 A.3. PCB Layouts Figure A.8: Control Board PCB Top Layer 84 A.3. PCB Layouts Figure A.9: Control Board PCB Bottom Layer 85 A.3. PCB Layouts Figure A.10: Power Board PCB 86 A.3. PCB Layouts Figure A.11: Power Board PCB Top Layer 87 A.3. PCB Layouts Figure A.12: Power Board PCB Bottom Layer 88 Appendix B Schematics for 3-Phase Islanding Test 89 Appendix B. Schematics for 3-Phase Islanding Test Figure B.1: Schematics for 3-phase Islanding Test 90 Appendix C Unintentional Islanding Test Conditions Unintentional Islanding Test Test conditions: 1. Single Phase120V /60HZ /1kW 2. PF=[1,0.37, 0.707 ] ⇔ Q f=[0,2.5, 1 ] Values Table: Criteria Value Unit Notes Pload 1000 W Qload 0 VAR Matched LC VEPS 120 V RMS fEPS 60 Hz VIUT 120 V Inverter Under Test PIUT 1000 W IIUT 8.33 A RMS PFIUT 0.95 =18.195o Qf 1 RLC below designed for this Qf Rload 14.4 OHM V2/P LLoad 38.197 mH R / 2 f oQ f  , iL(0)=11.785A CLoad 184.207 F Q f / 2 f o R Qf 2.5 RLC below designed for this Qf Rload 14.4 OHM V2/P LLoad 15.28 mH R / 2 f oQ f  , iL(0)=11.785A CLoad 460.52 F Q f / 2 f o R Q f=RCL for a parallel RLC load, and QF= 1PF 2−1 . P IUT=PLoadPEPS & QIUT=QLoadQEPS 91

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                            <div id="ubcOpenCollectionsWidgetDisplay">
                            <script id="ubcOpenCollectionsWidget"
                            src="{[{embed.src}]}"
                            data-item="{[{embed.item}]}"
                            data-collection="{[{embed.collection}]}"
                            data-metadata="{[{embed.showMetadata}]}"
                            data-width="{[{embed.width}]}"
                            data-media="{[{embed.selectedMedia}]}"
                            async >
                            </script>
                            </div>
                        
                    
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