DESIGN AND IMPLEMENTATION OF A BOOST ACTIVE POWER FACTOR CORRECTOR by KUIYUAN WU B. A. Sc., Southwest Jiao Tong University, 1990 M. A. Sc., Chinese Academy of Sciences, 1997 A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF APPLIED SCIENCE in THE FACULTY OF GRADUATE STUDIES (Electrical and Computer Engineering) THE UNIVERSITY OF BRITISH COLUMBIA (Vancouver) June 2008 © Kuiyuan Wu, 2008 Abstract The input current harmonics of the rectifier are very harmful. Not only do they reduce the power factor of the AC-DC converter and cause a lot of electrical energy loss, but also damage other devices and pollute the line power system. Measures should be taken to reduce these harmonics. The commonly used method is to design an effective PFC circuit for the AC-DC converter. In this thesis, a Boost APFC circuit will be discussed in detail. This thesis presents a solution to design an appropriate APFC circuit with one Kilowatts output power and make this APFC circuit work satisfactorily from full load to half load scope. In this thesis, a detailed design process will be described for this project, including topology choice, theoretical calculation of the main components values, the determination of the main components for this circuit, circuit simulation and experimental verification. In the end, a concise conclusion will be made and the future improvement for this project will be introduced. Several commonly used control methods for the Active Power Factor Corrector circuit will be compared and then a good method will be chosen for this project. The average current control method is finally decided to use for this circuit and the basic control chip UC3854 is used to build the control circuit for this project. The simulation and the final experimental results all verify that this is an appropriate choice for this project. According to the schematic design and the simulation revision, a test prototype is built to verify the performance. Several tests are implemented and the final experimental results indicate that this circuit design can satisfy the project specification and it is feasible for this project. 11 Table of Contents Abstract.ii Table of Contents iii List of Tables vi List of Figures vii Acknowledgements xi Chapter 1 Introduction 1 1.1 AC-DC Rectifier Overview 1 1.2 Two Widely Used Methods to Improve the Power Factor of the AC-DC Converter 3 1.2.1 Using Common “L” Filter 3 1.2.2 Using Active Power Factor Corrector 5 1.3 Thesis Motivation and Objective 7 1.4 Project Specifications 8 Chapter 2 Schematic Design of Boost Active Power Factor Corrector 9 2.1 Main Circuit Topology 9 2.2 The Theory of the Boost APFC 12 2.3 Determination of Several Component Values 18 2.3.1 Calculation of Inductance in Main Circuit 18 2.3.2 Calculation of Capacitance in Main Circuit 20 2.3.3 Calculation of Current Sense Resistor 22 2.3.4 Calculation of Voltage Divider Rv1 and RVD 22 2.3.5 Calculation of Oscillator Components RSET and CT 23 111 2.3.6 Several Important Control Inputs .24 2.3.7 Three Important Protection Inputs 25 Chapter 3 Hardware Implementation 26 3.1 Choice of the Main Circuit Components 26 3.1.1 The Choice of Single Phase Full-wave Bridge Rectifier 26 3.1.2 Selection of Main Switch IGBT 29 3.1.3 The Choice of Diode in Boost Converter 31 3.1.4 The Choice of the Output Capacitor 33 3.1.5 The Determination of Inductor 35 3.2 The Basic Control Chip for This Circuit 41 3.2.1 Introduction of UC3854 41 3.2.2 PIN DESCRIPTIONS of UC3854 41 3.3 IGBT Gate Driver for This Circuit 45 Chapter 4 Project Simulation 47 4.1 The Simulation for 230V/5OHz Input Power 47 4.1.1 The Simulation Circuit 48 4.1.2 Simulations 49 4.2 The Simulation for 230V/6OHz Input Power 55 4.3 The Simulation for 220V/5OHz Input Power 61 4.4 The Simulation for 220V/6OHz Input Power 67 4.5 The Simulation for 200V/6OHz Input Power 73 4.6 The Simulation for 200V/50Hz Input Power 79 4.7 The Simulation for 240V/6OHz Input Power 85 4.8 The Simulation for 240V/5OHz Input Power 91 Chapter 5 Experimental Results 98 5.1 The Experimental Results for Current Sensing Resistor Rs of 0.1 Ohm and IGBT Gate Driving Resistor Rg of 150 Ohms 98 iv 5.2 The Experimental Results for Current Sensing Resistor Rs of 0.1 Ohm and IGBT Gate Driving Resistor Rg of Different Values 105 5.3 The Experimental Results for Current Sensing Resistor R=0.05Q and Gate Driving Resistor Rg=l5OC) 108 Chapter 6 Conclusion and Future Work 112 6.1 Conclusion 112 6.2 Future Work for This Project 113 References 115 Appendix A: Permeability versus DC Bias Curve 117 Appendix B: Permeability versus Frequency Curve 118 Appendix C: Normal Magnetization Curve 119 V List of Tables Table 3.1 Full Bridge Rectifier Parameters 29 Table 3.2 Parameters of IGBT 31 Table 3.3 Parameters of the Main Circuit Diode 33 Table 3.4 Parameters of the Output Capacitor 35 Table 3.5 Data of Kool MM Core 77090 39 Table 3.6 Magnet Wire Table 40 vi List of Figures Fig. 1.1 AC-DC Rectifier Circuit 1 Fig. 1.1[A] AC-DC Rectifier Simulation 2 Fig. 1.2 FFT Spectrum of 3 Fig. 1.3 Rectifier with “L” Filter 4 Fig. 1.3[A] Simulation of Rectifier with “L” Filter 4 Fig. 1.4 Spectrum of ‘in with “L” Filter 5 Fig. 2.1 Buck Converter Circuit 9 Fig. 2.2 Buck-boos Converter circuit 10 Fig. 2.3 Cuk Converter circuit 11 Fig. 2.4 Boost Converter circuit 11 Fig. 2.5 Boost APFC Circuit with Average Current Control 14 Fig. 2.6 Simulation of Inductor Current and Output Voltage 15 Fig. 2.7 Boost APFC Schematic Circuit 16 Fig. 2.8 Equivalent Circuit of IGBT 18 Fig. 2.9 Simulation Output Voltage of the Boost APFC 21 Fig. 2.10 Simulation Input DC Voltage of the Boost Converter 21 Fig. 3.1 The Complete Boost APFC Circuit 27 Fig. 3.2 The Simulation Wave Form of the Input Current ‘in 28 Fig. 3.3 Simulation Inductor Current Waveform 30 Fig. 3.4 The Simulation Output Voltage Wave Form at One-third Load 33 Fig. 3.5 Core Selector Chart 38 Fig. 3.6 Block Diagram of UC3854 42 Fig. 3.7 IGBT with Miller Capacitance 46 Fig. 4.1 Simulation Circuit for 230V/5OHz/6OHz 48 vii Fig. 4.2 Simulation of and I for Full Load Situation 49 Fig. 4.2[A] Simulation of V0 and ‘md for Full Load Situation 50 Fig. 4.3 Simulation of ‘in and V1 for Half Load Situation 51 Fig. 4.3[A] Simulation of I and V0 for Half Load Situation 52 Fig. 4.4 Simulation of ‘in and V, for One Third Load 53 Fig. 4.4[A] Simulation of ‘md and V0 for One Third Load 54 Fig. 4.5 Full Load Simulation of V1 and (f6OHz) 55 Fig. 4.5[A] Full Load Simulation of ‘md and V0 (f=6OHz) 56 Fig. 4.6 Half Load Simulation of Im and Vin (f6OHz) 57 Fig. 4.6[AJ Half Load Simulation of ‘md and V0 (f=6OHz) 58 Fig. 4.7 One-third Load Simulation of and V1 (f=6OHz) 59 Fig. 4.7[A] One-third Load Simulation of ‘md and V0 (f=6OHz) 60 Fig. 4.8[A] Full Load Simulation of Ii, ‘md and V0 (220V/5OHz) 62 Fig. 4.9 Half Load Simulation of Im and Vm (220V/5OHz) 63 Fig. 4.9[A] Half Load Simulation of I, ‘md and V0 (220V/5OHz) 64 Fig. 4.10 One-third Load Simulation of and V10 (220V/5OHz) 65 Fig. 4.10[A] One-third Load Simulation of V0, and ‘md (220V/5OHz) 66 Fig. 4.11 Full Load Simulation of ‘in and V1 (220V/6OHz) 67 Fig. 4.11[A] Full Load Simulation of I, ‘md and V0 (220V/6OHz) 68 Fig. 4.12 Half Load Simulation of and V10 (220V/6OHz) 69 Fig. 4.12[A] Half Load Simulation of ‘md and V0 (220V/6OHz) 70 Fig. 4.13 One-third Load Simulation of Im and Vmn (220V/6OHz) 71 Fig. 4.13[A] One-third Load Simulation of ‘in, ‘mnd and V0 (220V/6OHz) 72 Fig. 4.14 Full Load Simulation of Vin, ‘in and V0 (200V/6OHz) 73 Fig. 4.14[Aj Full Load Simulation of ‘md and Vd (200V/6OHz) 74 Fig. 4.15 Half Load Simulation of V10 and Im (200V/6OHz) 75 Fig. 4.15[A] Half Load Simulation V0, ‘md and Vd (200V/6OHz) 76 viii Fig. 4.16 One-third Load Simulation of V1 and ‘in (200V/6OHz) 77 Fig. 4.16[A] One-third Load Simulation of V0, ‘md and Vd (200V/6OHz) 78 Fig. 4.17 Full Load Simulation of and (200V/5OHz) 79 Fig. 4.17[A] Full Load Simulation of ‘md, Vd and V0 (200V/5OHz) 80 Fig. 4.18 Half Load Simulation of V and (200V/5OHz) 81 Fig. 4.18[A] Half Load Simulation of ‘md, Vd and V0 (200V/5OHz) 82 Fig. 4.19 One-third Load Simulation of V1 and 110 (200V/5OHz) 83 Fig. 4.19[A] One-third Load Simulation of V0, ‘md and Vd (200V/5OHz) 84 Fig. 4.20 Full Load Simulation of and ‘in (240V/6OHz) 85 Fig. 4.20[A] Full Load Simulation of V0, ‘md and Vd (240V/6OHz) 86 Fig. 4.21 Half Load Simulation of V1and im (240V/6OHz) 87 Fig. 4.21[A] Half Load Simulation of V0, ‘md and Vd (240V/6OHz) 88 Fig. 4.22 One-third Load Simulation of V1 and (240V/6OHz) 89 Fig. 4.22[A] One-third Load Simulation of V0, ‘md and Vd (240V/6OHz) 90 Fig. 4.23 Full Load Simulation of V111 and ‘in (240V/5OHz) 91 Fig. 4.23[A] Full Load Simulation of V0, ‘md and Vd (240V/5OHz) 92 Fig. 4.24 Half Load Simulation of V111 and (240VI5OHz) 93 Fig. 4.24[A] Half Load Simulation of V0, ‘md and Vd (240V/5OHz) 94 Fig. 4.25 One-third Load Simulation of V1 and (240V/5OHz) 95 Fig. 4.25[AJ One-third Load Simulation V0, ‘md and Vd (240VI50Hz) 96 Fig. 5.1 Full Load Experimental Results of V111 and (7OVrms/6OHZ) 99 Fig. 5.2 Full Load Experimental Results (l47Vrmd6OHZ) 100 Fig. 5.3 Three-quarters Load Experimental Results (75VrmsI6OHZ) 102 Fig. 5.3[A] Three-quarters Load Experimental Results (150Vrms/6OHZ) 103 Fig. 5.4 Full Load Experimental Results (l3OVrmIRg=85Q) 105 Fig. 5.5 Full Load Experimental Results (150VrmsfRg2700) 106 Fig. 5.5[A] Full Load Experimental Results of V0 (150Vrms/Rg27OQ) 107 ix Fig. 5.6 Deficient Load Experimental Results (R=180Q1V 96VJRg=27OO) .108 Fig. 5.7 Half Load Experimental Results (22Vrms/3OO)/Rg 1500) 109 Fig. 1 Permeability versus DC Bias Curve 117 Fig. 2 Permeability versus Frequency Curve 118 Fig. 3 Normal Magnetization Curve 119 x Acknowledgements At first, I must express my great thanks to my supervisor, Dr. William G. Dunford for his support, advice and guidance throughout the whole process of my graduate study and project research at UBC. Numerous interactions with my colleagues, such as Mr. Weidong Xiao, Mr. Yong Zhang, Mr. Detao Mao and Mr. Liwei Wang gave me a lot of help throughout my graduate study; here, I express my great thanks to all of them. Thanks are also extended to all other power faculty members and colleagues for their help and guidance for my graduate study. Finally, I must express my sincere gratitude to my parents for their inspiration and support during all my studies. xi Chapter 1 Introduction Chapter 1 Introduction 1.1 AC-DC Rectifier Overview For the AC-DC-DC switching power supply, a full wave rectifier and a parallel capacitor are often used to get the initial DC voltage for the following DC-DC converter. Because the rectifier is non-linear and the filter capacitor is an energy-storage component, the combination of them will make the input current distort greatly [1]. Please see Fig. 1.1 [Aj for the corresponding waveforms where “t” for time (milliseconds) , “V,” for electrical input voltage (Volts), “V0” for output voltage (Volts) and “I,” for electrical input current (Amperes). Please see Fig. 1.2 for the corresponding spectrum of ‘in. in md vo Fig. 1.1 AC-DC Rectifier Circuit 1 Fig. 1.1[A] AC-DC Rectifier Simulation I: Input Line Current (Amperes) V1: Input Line Voltage (Volts) lind: Rectified DC Current (Amperes) V0: Output Voltage of the Rectifier (Volts) Chapter 1 Introduction 11’ / I’S / 5’ ‘\, / 5’ ‘S ‘ ‘5’ ..... \ç....../.. -S . - / - - . / 08 5304 170.80 10100 190I)0 200.00 111114(11111> 20.00 20.08 10.00 0.0 -1000 -2000 -00.00 430.80 20000 00 -20080 -40000 101 30.00 25.00 20.00 1500 1030 5.00 0.0 -030 225.80 [5 /5 5’ [ j 5’320.00 S.’ ,- 5’ . .. . 000 j I ‘ \ I880 \ J I 300.20 \.L \... SS ‘1 “. ‘1 “J255.08 150.00 170.08 100.00 190.30 200.00 111114(1118> 2 Chapter 1 Introduction Fig. 1.2 FFT Spectrum of I, The pulsing input current contains a lot of harmonic components. This will reduce the power factor greatly. Besides this, a lot of current harmonic emission will make the line voltage distort and the adjacent equipment out of order. In order to reduce the pollution caused by input harmonic current of AC-DC converter and improve the input power factor, measures should be taken to limit the harmonic components of the input current. 1.2 Two Widely Used Methods to Improve the Power Factor of the AC-DC Converter 1.2.1 Using Common “L” Filter One way is to add an inductor between the rectifier and the filter capacitor C to form an L filter; another way is to connect an L filter at the AC side of the rectifier. Certainly, these two methods can be combined together, and this will be more effective 500 400 300 200 1 00 1.00 Fre5uey (KHz 2.35 300 400 05 3 Chapter 1 Introduction V L 1::::: r’””vT;1””\z”7””””c” —‘ I: Input Line Current (Amperes) V11: Input Line Voltage (Volts) Tinie (rns) [1]. Please see Fig. 1.3[Aj for the corresponding waveforms for this topology where “t” for time (milliseconds), “V” for input electrical voltage (Volts) and “in” for electrical current (Amperes). Figure 1.4 gives the FFT spectrum of ‘in under this situation. in Yin lind 4SOmH Vo - 150 • RO Fig. 1.3 Rectifier with “L” Filter fin 4QQ:QQ 2QO •400OO isea.9 160.00 170.00 130.00 190.00 200.00 Fig. 1.3[A] Simulation of Rectifier with “V’ Filter 4 Chapter 1 Introduction un 115 L 150 125 1.00 0.75 0.25 0.0 ____________ 0.0 1,00 ZOO 3.00 4.00 5.00 Frequency (KHz Fig. 1.4 Spectrum of I, with “L” Filter By comparing these two figures, it can be found that the “L” filter makes the input current from the line power much smoother than the pulsing input current created by the capacitor input filter. Therefore, the power factor will be improved. The advantages of this method are simple, cheap, reliable and low EML The disadvantages for this way are large volume, heavy and difficult to make the power factor approach unity. Its function is relevant to line frequency, load change and the variation of the input line voltage. There is high charging and discharging current between the inductor and the capacitor. It is often used in the situation without very strict requirement of input power factor, such as the frequency converter. 1.2.2 Using Active Power Factor Corrector The objective of active power factor correction is to make the input to a power supply look like a simple resistor. An active power factor corrector does this by programming the input current in response to the input voltage. As long as the ratio between the voltage and current is a constant, the input will be resistive and the power 5 Chapter 1 Introduction factor will be equal to one. When the ratio deviates from a constant, the input current will contain phase displacement, harmonic distortion or both. Either one will degrade the power factor. The most general definition of power factor is the ratio of real power to apparent power. PPF= (1-1)(Vrmsxlrms) Where P is the real input power; Vrms and Irms are the root mean square (RMS) voltage and current of the load, or power factor corrector input in this case [5], [7]. If the load is a pure resistance, the real power and the product of the RMS voltage and current will be the same and the power factor will be equal to unity. If the load is not a pure resistance, the power factor will be less than unity. Phase displacement is a measure of the reactance of the input impedance of the active power factor corrector. Any amount of reactance, either inductive or capacitive will cause phase displacement of the input current waveform with respect to the input voltage waveform. The phase displacement of the voltage and current is the classic defmition of power factor which is the cosine of the phase angle between the voltage and current sinusoids. PF = cos (1-2) The amount of displacement between the voltage and current indicates the degree to which the load is reactive. If the reactance is a small part of the impedance, the phase displacement will be small. An active power factor corrector will generate phase displacement of the input current if there is phase shift in the feed-forward signals or in the control loops. Any filtering of the AC line current will also produce phase displacement. Harmonic distortion is a measure of the non-linearity of the input impedance of the active power factor corrector. Any variation of the input impedance as a function of the input voltage will cause distortion of the input current and this distortion is the other contributor to poor power factor. Distortion increases the RMS value of the current 6 Chapter 1 Introduction without increasing the total average power being drawn. Therefore, a non-linear load will have a poor power factor because the RMS value of the current is high but the total average power delivered is small. If the non-linearity is small the harmonic distortion will be low. Distortion in an active power factor corrector comes from several sources: the feed-forward signals, the feedback loops, the output capacitor, the inductor and the input rectifiers. An active power factor corrector can easily achieve a high input power factor, usually much greater than 0.9. However, power factor is not a sensitive measure of the distortion or the displacement of the current waveform. It is often more convenient to deal with these quantities directly rather than with the power factor. For example, 3% harmonic distortion alone has a power factor of 0.999. A current with 30% total harmonic distortion still has a power factor of 0.95. A current with a phase displacement of 25 degrees from the voltage has a power factor of 0.90. A DC-DC switching converter can be connected between the rectifier and load to realize active power factor corrector topology [1], [11]. In this way, the wave shape of the input current can be made similar to that of input line voltage by applying the current feedback control technology [1], [13]. Therefore, the power factor can be improved to 0.99 or higher. Its advantages include high power factor [0.97—0.99], very low total harmonic distortion, stable output voltage, small volume and low weight. Its disadvantages include complex electrical circuit, expensive cost and high EMI. Certainly, these will make the efficiency reduce a little. 1.3 Thesis Motivation and Objective The objective of this thesis is to clarify the practical approaches to set up an active power factor corrector; this circuit must satisfy the power factor requirement from full load to half load range. The specific objectives include: 7 Chapter 1 Introduction (1) To choose a reasonable topology for this APFC project (2) To calculate the main component values with power electronic theory (3) To determine appropriate control method for this project (4) To simulate this APFC circuit during the required load scope and input power (5) To test the prototype and characteristics related to the theoretical analysis This thesis is organized into six chapters. Chapter 1 gives a brief introduction of the commonly used methods to improve power factor and outlines the objectives of this thesis. In Chapter 2, an appropriate main circuit topology and a suitable control method for this project will be explained at first and then the detailed theoretical calculation of the main components value will be given. Chapter 3 is focused on main component part number determination, hardware choice and setup for this boost APFC circuit. Chapter 4 will deal with the simulation of the determined topology in the required load scope and input power. Revision to the project circuit and some experimental results are included in Chapter 5. The last chapter gives a conclusion of this project design and suggests some meaningful work to be done in the future. 1.4 Project Specifications According to the requirement for this active power factor corrector, the specifications for this project are determined as following: (1) Pout: 1000W (2) V range: AC 20OV - 23OV (3) Line frequency range: 50Hz 60Hz (4) Output voltage: 400Vd (5) Input power factor: 0.99 or higher 8 Chapter 2 Schematic Design of Boost Active Power Factor Corrector Chapter 2 Schematic Design of Boost Active Power Factor Corrector 2.1 Main Circuit Topology It is very important to choose an appropriate topology in engineering project design; otherwise, it is impossible to make the circuit perform satisfactorily. Theoretically, any kind of DC-DC converter, such as Buck, Boost, Buck-boost or Cuk converter can be used as the main circuit of a power factor corrector, but the Boost converter is widely used because of its special advantages. Finally, the Boost converter is chosen to be the power circuit of this APFC project. These four converters will be compared and the reason for this topology selection will be explained in the following: Buck Converter The Buck converter is as following: Vo Fig. 2.1 Buck Converter Circuit The relation between its input voltage Vg and output voltage V0 is: V0DVg (24) V0 is the output voltage; Vg is input voltage and D is the duty cycle of the converter (OD1) [11], [9]. It can be seen that the buck converter can only lower the input 9 Chapter 2 Schematic Design of Boost Active Power Factor Corrector voltage; however, as a part of a large power supply, it is often required that the output voltage of the APFC circuitry is in the range of 38OVolts to 42OVolts so that it can reduce the loss and improve the efficiency. This is the output voltage specification for this project. Obviously, the Buck converter can not satisfy the requirement either for European standard (230V150 Hz) or North American standard (120V/6OHz). Therefore, it is not appropriate for this project. Buck-boost Converter The Buck-boost converter is as following: Vo Fig. 2.2 Buck-boos Converter circuit The relationship between its input voltage Vg and its output voltage Vo is: V0 DVg I (1D) (2-2) D is the duty cycle of the converter (0D1) [11], [9]. This converter can both boost and lower the input voltage. Only from the view of satisfying the output voltage requirement, it can solve this question. However, the input current of this converter is not continuous and its input power factor is not satisfactory. Obviously, this conflicts with the aim of the power factor corrector. If it is used as the power circuit, a Low—Pass LC filter must be added to its input and this will make the circuit complicated. All these characteristics suggest that a better converter topology should be chosen for this project. Cuk Converter The Cuk converter is as following: 10 Chapter 2 Schematic Design of Boost Active Power Factor Corrector Fig. 2.3 Cuk Converter circuit The relationship between its input voltage Vg and its output voltage V0 is: V0 DVg I (1D) (2-3) D is the duty cycle of the converter (OD1) [11], [9]. It can increase or decrease the input voltage and its input current is continuous. It seems that the Cuk converter is a right choice for this question, however, it can be found that the Cuk converter is more complicated than Boost converter. Besides this, the energy transformation mainly relies on the capacitor Cj in Cuk converter; this will require that the capacitor Cj can endure great ripple current. This kind of capacitors is expensive and their reliability is not very good. Considering all of these factors, other simple feasible methods should be searched for this project. Boost Converter The Boost converter is as following: Fig. 2.4 Boost Converter circuit The ideal relationship between its input voltage Vg and its output voltage V0 is: LI R 11 Chapter 2 Schematic Design of Boost Active Power Factor Corrector = 1-D (2-4) D is the duty cycle of the converter (OD1) [11], [9]. Its input current is continuous and this will reduce the input current harmonics greatly. It is simple compared with Cuk and revised Buck-boost converter. It is easier to drive the power switch because the potential of its reference point (Source pole) is zero. The disadvantage of the boost regulator is the high output voltage required. The output voltage must be greater than the highest expected peak input voltage, but, it doesn’t matter for this project. After careful comparison of these four kinds of converters, it can be seen that the Boost converter is a good choice for this project. 2.2 The Theory of the Boost APFC The input current of the boost regulator must be forced or programmed to be proportional to the input voltage for power factor correction. Feedback is necessary to control the input current. The power circuit of a boost power factor corrector is the same as that of a DC to DC boost converter. There is a diode bridge rectifier ahead of the inductor to rectify the AC input voltage but the large input capacitor which would normally be associated with the AC to DC conversion function has been moved to the output of the boost converter. If a capacitor follows the input diode bridge rectifier, it is a small one used only for noise control. The output of the boost regulator is a constant voltage but the input current is programmed by the input voltage to be a half sine wave. The power flow into the output capacitor is not constant but is a sine wave at twice the line frequency since power is the instantaneous product of voltage and current. The output capacitor stores energy when the input voltage is high and releases the energy when the input voltage is low to maintain the output power flow. Generally speaking, there are three common controlling methods for Boost APFC. They are average current control, peak current control and hysteritic current control. Among these three methods, the average current control method is often used because the 12 Chapter 2 Schematic Design of Boost Active Power Factor Corrector total harmonic distortion is very low and the average current I. is insensitive to the noise in this way. Certainly, the error between the peak value of the inductor current i and the average current in this way is lower than that in the other two ways. The average current control can be used in continuous conduction mode and discontinuous conduction mode. The other two methods can be used only in continuous conduction mode and the current peak value is sensitive to noise. For the Boost APFC with average current control, please see Fig. 2.5 [1]. An active power factor corrector must control both the input current and the output voltage. The current ioop is programmed by the rectified line voltage so that the input to the converter will appear to be resistive. The output voltage is controlled by changing the average amplitude of the current programming signal. An analog multiplier creates the current programming signal by multiplying the rectified line voltage with the output of the voltage error amplifier so that the current programming signal has the shape of the input voltage and the average output voltage amplitude which controls the output voltage. Here, the inductor current is measured directly; the obtained signal R is sent to CA---current error amplifier. The reference current of CA is the output signal of multiplier “M” which has two input signals---one is the error signal of output voltage V0/H and reference voltage Vref; the other is the measured value of Vd. VdC is full wave rectified value of input sine voltage V,. Therefore, the reference current signal is double half sine wave voltage. After comparing with standard current, the variation of the high frequency signal of the input inductor current will be averaged by the current error amplifier---CA. After the amplified average current error signal is compared with ramp oscillator wave, the PWIVI will send the appropriate driving signal to the power switch IGBT and determine the proper duty cycle for this power switch. In the end, the current error will be corrected fast and accurately and the input power factor will be improved nearly to unity. The wave shape of the inductor current L is shown as Fig. 2.6. In order 13 Chapter 2 Schematic Design of Boost Active Power Factor Corrector to be clear, the two kilohertz is used as the input line frequency in this demonstrative example. Fig. 2.5 Boost APFC Circuit with Average Current Control 14 389.90 1 / f 380.80 ---/ :/ c 300,75 ‘r ‘--.. 389.70 ..\. . .1.i. 38565 (I 389.60 300,00 300,20 350.40 300.00 390.80 400.00 Time (me) Chapter 2 Schematic Design of Boost Active Power Factor Corrector 10.00 8,00 6.00 4.00 2.00 0.00 -2.00 300.00 300.20 399A0 309.60 389.80 Time (ms) 00.00 Fig. 2.6 Simulation of Inductor Current and Output Voltage lind: Inductor Current (Amperes) V0: Output Voltage (Volts) According to this average current control theory, the basic control chip UC3854 is used to construct the whole control circuit for this boost active power factor corrector. Please see Fig. 2.7 for the fmal schematic Boost APFC circuitry. 15 Chapter 2 Schematic Design of Boost Active Power Factor Corrector UC3854 Controlled PEC Converter Fig. 2.7 Boost APFC Schematic Circuit Here, the choice of the switching frequency and main power switch will be Em Note: This circuit can be simulated by the full version 16 Chapter 2 Schematic Design of Boost Active Power Factor Corrector explained separately because they are important for the converter to have satisfactory performance. 1: The Choice of the Switching Frequency: It is well known that the switching frequency correlates to the performance of the power factor corrector. When the frequency is lower than 20kHz, the performance of the power factor corrector will not be satisfactory, the ripple will be large, the instant responding will be slow, the weight and volume of the equipment will increase greatly and it will produce the tiresome ac noise [2], [4]. When the frequency is more than 150 kHz, it will be favorable to improve the function of the power converter, such as to lower the ripple, to shorten the responding time and to reduce the volume and weight, but it will also bring about some defects, such as to increase radio-frequency interference (RFI), to make a higher demand on the high frequency properties of the main power switches, high frequency inductors and capacitors. Especially, the switching loss will increase and the efficiency will be decreased obviously for large power application [2], [4]. All these will increase the difficulty and the cost to build this power factor corrector. Considering all of these factors, it is appropriate to choose a frequency from 20 kHz to 150 kHz for this boost converter. In this range, there is no tiring ac sound and the power factor corrector is good in volume, weight, ripple, instant responding speed and the cost to build it; it can satisfy the requirement of many equipments. In the end, the value of 100 kHz is chosen as the switching frequency of the main converter; the final experimental results prove it is proper. Certainly, with the improvement of the electrical cell element properties and the development of power electronic technology, the frequency of the active power factor corrector will be higher in the future. 2 : The Choice of the Main Power Switch: The IGBT is chosen as the main power switch for the boost converter. The IGBT is equivalent to the combination of a MOSFET and a PNP transistor. Please see Fig. 2.8. This makes it have advantages of MOSFETs and transistors. Transistors have low saturated voltage and high current density, but the transistor needs high driving current. 17 Chapter 2 Schematic Design of Boost Active Power Factor Corrector On the contrary, the driving power for the MOSFET is very little, its on-and-off speed is very fast, but its turn-on state voltage is high and its current density is low. These make IGBT have low driving power and low saturated voltage. At present, the voltage and current level of IGBT is nearly the same as those of transistors. It is suitable to act as main switches for large power, high frequency converters. C Fig. 2.8 Equivalent Circuit of IGBT 2.3 Determination of Several Component Values Because the common working knowledge of the Boost converter is very simple, there is no need to explain the steady working process of this converter or to investigate its conduction mode in detail. It can work well both in continuous conduction mode and discontinuous conduction mode if the average current control method is used for the boost active power factor corrector. Here, only the theoretical calculation of several main components value will be discussed in detail because the input power for the boost converter is half sine wave voltage, not a constant DC voltage and this is the difference between boost APFC circuit and the common boost converter. 2.3.1 Calculation of Inductance in Main Circuit The inductance determines the amount of high frequency current ripple in the input current. Its value is chosen to satisfy the limit for some specific current ripple [11]. In E 18 Chapter 2 Schematic Design of Boost Active Power Factor Corrector order to calculate the main inductance, it should be clear that there are two frequency currents in the APFC circuit. The frequency of the reference current is the same as the input line frequency; the frequency of the regulated current is the high frequency decided by the control circuit, for this project, it is equal to 100 kFTz. The principle to design the inductance is to make the maximum inductor current ripple satisfy its restraint. For this project, this restraint is:Jl2.5%iL. According to this principle, the required inductance value can be decided. From the knowledge of the boost converter, the inductor current ripple 1L is: AlL A1LPP VifldDT (2-5) Here, Vd is the average value of the rectified input DC voltage; Ts is the high frequency switching period [11], for this question, it is: Ts =lOi.is For ideal situation, the average inductor current can be expressed as following: (2-6)1—D R0 1—D v0: average value of output voltage; j,: average value of output current. Therefore, the following expression can be derived for this question: 1L/ =-xDT2L V0 2L V = DTR0(1-D)2 0.125 (2-7) It is equivalent to the following relation: L 4R0TsD(1 — D)2 (2-8) If the satisfactory value of the inductance is to be determined, the maximum value for4R0TD(1 — D)2 must be known first. Because the values of R0 and T are constant, only the maximum value of D (1 — D)2 need to be calculated. In order to be convenient, It is written as: f(D) = D(1 — D)2 = D3 — 2D + D (2-9) By equating the derivative of f(D) to be zero, the corresponding values of the duty cycle can be got as following: Dj=1;D2=1/3 19 Chapter 2 Schematic Design of Boost Active Power Factor Corrector It is well known that the boost converter can not work at the condition of “D=1”, it will be enough to consider the situation of “D= 1/3”. Because the second derivative of f(D) is: fb) = 6D — 4 (2-10) Its value at “D=1/3” is equal to “f() = —2 it can be concluded that the expression f(D) will reach its maximum value at D=113 and its maximum value is equalto: f() = 4/27 (2-11) Now, the inductance value can be calculated as following: L 4 x 150 x--x 1 0.89(mH) (2-12)27 lOOxl000 Certainly, this is the approximate calculation. After simulation revision, in the end, the value of this inductance is taken as: L =lmH. Although the input voltage has different values at different time, it is still able to use the ideal case formula to calculate the inductance. This is because the input line frequency (50Hz or 60Hz) is much lower than the switching frequency of the converter (100kHz), the value of the input half sine wave DC voltage of the boost converter can be considered to remain nearly the same during one short switching period. 2.3.2 Calculation of Capacitance in Main Circuit The factors involved in the decision of the output capacitance include the switching frequency current ripple, the second harmonic current ripple, the DC output voltage, the output voltage ripple and the hold-up time. The total current through the output capacitor is the RMS value of the switching frequency ripple current and the second harmonic of the current. The large electrolytic capacitors which are normally chosen for the output capacitor have an equivalent series resistance which changes with frequency and is generally high at low frequencies. The amount of current which the capacitor can handle is generally determined by the temperature rise. It is usually not necessary to calculate an exact value for the temperature rise. It is usually adequate to calculate the temperature 20 Chapter 2 Schematic Design of Boost Active Power Factor Corrector rise due to the high frequency ripple current and the low frequency ripple current and add them together. The capacitor data sheet will provide the necessary ESR and temperature rise information. The hold-up time of the output voltage often dominates any other consideration in output capacitor selection. Hold-up time is the length of time that the output voltage remains within a specified range after input power has been turned off. Hold-up time of 15 to 50 milliseconds is typical. In off-line power supplies with a 400Vdc output the hold-up requirement generally works out to between lpF and 2pF per watt of output power. In this 1Kw project design, the output capacitance is l000jiF. If hold-up is not required, the capacitance will be much smaller, perhaps 0.2iF per watt, and then ripple current and ripple voltage are the major concern.The output voltage waveform of this Boost APFC circuit under European input power is as following: 104.00 402.00 / \ / \ / \ / \ / ::: / / / \ / / 396.00 . \ / / \ / 304.00 \/‘‘“\,f’:\’’’”. 302.00 150,00 100,00 170,00 190.00 190,00 200,00 Fig. 2.9 Simulation Output Voltage of the Boost APFC V0: Output Voltage of the Boost APFC (Volts) The input DC voltage for this boost converter is as following: V n d 350.00 I I . . .s. c*.’: :7Th 7 V V 16(100 170.00 180.00 100.00 200.00 lime (rn’s) Fig. 2.10 Simulation Input DC Voltage of the Boost Converter V8d: Rectified DC Input Voltage (Volts) 21 Chapter 2 Schematic Design of Boost Active Power Factor Corrector Hold-up time is a function of the amount of energy stored in the output capacitor, the load power, output voltage and the minimum voltage the load will operate at. This can be expressed in an equation to define the capacitance value in terms of the hold-up time. — 2XPoutX1tC0 — 2 2 (2-13)V0 V0(mjfl) Where C0 is the output capacitance, P01 is the load power, ‘t is the hold-up time, V0 is the output voltage and V0(min) is the minimum voltage the load will operate at [51. For this project converter: P0 is 1kW, ‘t is 34msec, V0 is 400V and V0(min) is 300V, so, C0 is equal to 971iF. In the end, the output capacitance value is chosen as: Co=l000jiF 2.3.3 Calculation of Current Sense Resistor A peak value from 0.5 Volts tol.0 Volts or so across the current sense resistor provides a signal large enough to have a good noise margin but which is small enough to have low power dissipation. There is a great deal of flexibility in choosing the value of the current sense resistor. For this project circuit, it can be found that the peak current through this resistor is equal to: M 1.414x1000 1.414x1000x0.125 ‘Pk(max) = ‘Pk + = 200 + 200 = 7.95(A) (2-14) R5 = Vrs = 0.125(Ohms) (2-15) ‘Pk(max) “ The value of 0.10 Ohm is chosen for this current sense resistor temporarily. 2.3.4 Calculation of Voltage Divider R1 and RVD The criteria for the choice of the value of R1 are reasonably vague. The value must be low enough so that the operational amplifier bias currents will not have a large effect on the output and it must be high enough so that the power dissipation is small. In this APFC converter, a 511 kO resistor was chosen for R1 and it will have power dissipation about 300mW. 22 Chapter 2 Schematic Design of Boost Active Power Factor Corrector The output voltage is set by the values of voltage divider Rvi and RVD. The value of Rv1 is already determined, so, the value of RVD can be determined from the desired output voltage and the reference voltage which is equal to 7.50Volts. RVD RvJXVref = 511X7.5 9.76(kf) (2-16) VOVref 400—7.5 Finally, the value of RVD is chosen as lOkC) and this will give an output voltage of 39OVdc. This could be trimmed up to 400Vdc with a 414k0 resistor in parallel with RVD, but for this application 390Vdc is acceptable. RVD has no effect on the AC performance of the active power factor corrector. Its only effect is to set the DC output voltage. 2.3.5 Calculation of Oscillator Components RSET and CT The PWM oscillator frequency in Figure 2.7 is equal to 100kHz. This value is determined by CT at pinl4 and RSET at pin 12. RSET should be chosen first because it affects the maximum value of ‘MULT according to the equation: —3.75V ‘MULTmax = (2-17) This effectively sets a maximum PWM-controlled current. With RSEI=lOkO, —3.75 ‘MULTmax = 10000 = —375(4) (2-18) Also note that the multiplier output current will never exceed twice of ‘AC. With the 4k0 resistor from the multiplier output to the 0.10 Ohm current sense resistor, the maximum current in the current sense resistor will be equal to: I — IMULTmaxX4000 — — ‘max 01 — - Having selected the value of Rs-, the current sense resistor, and the resistor from the multiplier output to the current sense resistor, we can calculate the value of CT for the desired PWM oscillator frequency from the following equation: CT = 1.25 = 1.25 = 1.25(nF) (2-20) RSETXfS 1OKx100K 23 Chapter 2 Schematic Design of Boost Active Power Factor Corrector 2.3.6 Several Important Control Inputs 1. VSENSE (Output DC voltage sense): The threshold voltage for the VSENSE input is equal to 7.5Volts and the input bias current is typically equal to 5OnA. The values shown in Figure 2.7 are for an output voltage of 400Volts. In this circuit, the voltage amplifier operates with a constant low frequency gain for minimum output excursions. The feedback capacitor with the value of 47nF places a 15Hz pole in the voltage ioop that prevents the 120Hz ripple from propagating to the input current. 2. ‘AC (Line waveform): In order to force the line current wave-shape to follow the line voltage, a sample of the power line voltage in waveform is introduced at pin 6. This signal is multiplied by the output of the voltage amplifier in the internal multiplier to generate a reference signal for the current control loop. This input is not a voltage, but a current (hence ‘Ac). It is set up by the 150k0 and 520kC) resistive divider (see Figure2.7). The voltage at pin 6 is internally held at 6Volts. The two resistors are chosen so that the current flowing into pin 6 varies from zero (at each zero crossing) to about 6001iA at the peak of the wave-shape. The following formulae were used to calculate the values of these resistors: — Vpk — 1.414x230 VAC — -6= - ‘VACpk Xl Finally, the value of this resistor is chosen as 520kC) R81 = RI/AC = 135(kfl) (2-22) Finally, the value of this resistor is chosen as 150k0 (Vpk is the peak value of line voltage) 3. IsENSE/Multiplier Output (Line current): The voltage drop across the 0.10 Ohm current-sense resistor is applied to pins 4 and 5 as shown. The current-sense amplifier also operates with high low-frequency gain, but unlike the voltage amplifier, it is set up to give the current-control loop a very wide bandwidth. This enables the line current to follow the line voltage as closely as possible. 24 Chapter 2 Schematic Design of Boost Active Power Factor Corrector In the present circuit, this amplifier has a zero at about 500Hz, and a gain of about 18dB thereafter. 2.3.7 Three Important Protection Inputs 1. ENA (Enable): The ENA input must reach 2.SVolts before the REF and GT Dry outputs are enabled. This provides a means to shut down the gate in case of trouble, or to add a time delay at power up. A hysteresis gap of 200mV is provided at this terminal to prevent erratic operation. Under-voltage protection is provided directly at pinl5, where the on/off thresholds are l6Volts and lOVolts. If the ENA input is unused, it should be pulled up to VCC through a current limiting resistor of 22k0. 2. SS (Soft start): The voltage at pin 13 (SS) can reduce the reference voltage used by the error amplifier to regulate the output DC voltage. With pin 13 open, the reference voltage is typically equal to 7.SVolts. An internal current source delivers approximately -14iA from pin 13. Thus a capacitor connected between that pin and the ground will charge linearly from zero to 7.5Volts in 0.54C seconds, with C expressed in microfarads. 3. PKLIM (Peak Current Limit): Use pin 2 to establish the highest value of current to be controlled by the power switch. With the resistor divider values shown in Figure2.7, the 0.OV threshold at pin 2 is reached when the voltage drop across the 0. lOOhm current sense resistor is 7.5V*1.8k/lOk=1.35Volts, corresponding to 13.SAmperes. A bypass capacitor from pin 2 to the ground is recommended to filter out very high frequency noise. The values of other components can be determined according to the manual of UC3 854 and the requirement of this project by trial and error method with the help of PSIM software. The calculation of them will not be listed here. 25 Chapter 3 Hardware Implementation Chapter 3 Hardware Implementation Based on the theory discussed in chapter 2, a practical boost active power factor corrector will be built for experiment. In this chapter, emphasis will be given on how to choose components and put them together to form a prototype of boost active power factor corrector. 3.1 Choice of the Main Circuit Components The practical boost active power factor corrector circuit is depicted in Error! Reference source not found.. It includes an AC-DC rectifier, a boost DC-DC converter, an analog control circuit built with UC3854 basic control chip and other accessory components. It works on popular AC-DC-DC topology. The process to choose appropriate components for main circuit and control circuit will be discussed in detail. At first, the part number of main circuit components will be determined in this section. 3.1.1 The Choice of Single Phase Full-wave Bridge Rectifier The appropriate rectifier diode should be chosen according to its maximum reverse break voltage, average current through this diode, maximum current through this diode and its dissipation power. Therefore, these four parameters should be calculated at first and then determine the suitable bridge rectifier for this project. 1: The Maximum Reverse Break Voltage Because this is a single phase full wave bridge rectifier, the maximum reverse break voltage applied to each diode of this rectifier is equal to the maximum phase line voltage. According to this knowledge, there is: VDrmax 23O’1’ = 325 (V) (34) 26 Chapter 3 Hardware Implementation UC3854 Controlled PFC Converter Fig. 3.1 The Complete Boost APFC Circuit Note: This circuit can be simulated by the full version 27 Chapter 3 Hardware Implementation 2: The Average Current through Diode For the full bridge rectifier, the current through diode is equal to the input line current of the rectifier when the diode is “ON’ and every pair of diodes will conduct during half cycle if the load is resistive. For ideal case, the output power of this power factor corrector is equal to the input power for this circuit. Because this is a power factor corrector, the input power factor is nearly equal to one for approximate calculation. According to this principle, there is: = Urmslrms = = Vo/R = 4002/iso 1066.67 (W) (3-2) 4ms = POUt/Urms = 1066.67/200 5.33(A) (3-3) ‘max = 533 X 7.5(A) (3-4) Therefore, the average current through the diode is equal to: (iDA> = fiDAdt = f7.5sinwtdt = 2.39(A) (3-5) 3: The Maximum Current through the Diode Obviously, the maximum current through the diode is equal to the maximum value of the input line current for the full wave bridge rectifier. Therefore, there is: IDmax7.5(A) (36) Please see Fig. 3.2 for the input current wave form to make a choice for the diode. I: Input Line Current (Amperes) Fig. 3.2 The Simulation Wave Form of the Input Current I 28 Chapter 3 Hardware Implementation 4: Dissipation Power The dissipation is mainly produced when the diode is in “ON” state. Therefore, the dissipation power for each diode in the rectifier bridge is equal to: I0VDAIDAdt = fiDAdt = VD(iDA) = 0.7 x 2.39 1.673(W) (3-7) Therefore, the total dissipation power of these four diodes in the input rectifier is approximately equal to four times of “PD” for convenient calculation: PD4 =PD =6.7(W) (3-8) According to these four parameters, the part number of the input bridge rectifier for this circuit is chosen as: KBU8G; its parameters are in the following table: Maximum Forward Forward Operating Recurrent Peak Average Rectified Voltage Drop (V) Temperature Range Reverse Voltage (V) Current (A) (°C) 400 8.0 1.1 -55 125 Table 3.1 Full Bridge Rectifier Parameters 3.1.2 Selection of Main Switch IGBT In order to choose an appropriate IGBT module, three parameters should be known at first. They are peak voltage across IGBT, peak current through IGBT and RMS current through IGBT. These three parameters will be calculated in the following: 1: The Peak Voltage across IGBT According to the common knowledge of the boost converter, the diode will conduct during the period of [DT5,T5] in each switching cycle and the voltage across IGBT will be equal to the output voltage, therefore, this peak voltage is equal to the maximum output capacitor voltage. From Fig. 2.9, it can be seen that the maximum output capacitor voltage is approximately equal to 402 Volts. VQp = Voutmax +A V = 402 + tDT5 402 + 2X150x1000x106 402 (V) (3-9) 29 Chapter 3 Hardware Implementation 2: The Peak Current through IGBT The main switch IGBT will conduct during the period of [0, DTs] in each switching cycle and the inductor current will be equal to the current through IGBT, so, the peak current through IGBT is equal to the maximum value of the inductor current. Although this value can be calculated approximately according to the common knowledge of the boost converter, it will be better to use the simulation results to determine this value so that a more accurate estimation can be made. Please see Fig. 3.3 for the inductor current wave form under full load condition. From this inductor current wave form, it can be seen that the peak current value through IGBT is equal to: ‘Qp = ‘L + ‘‘L TE + 7.5(A) (3-10) md 8.00 6.00 4. 2.00 0.00 -2,00 150.00 180.00 170.00 180.00 180.00 Tim e(ms) 200.00 Fig. 3.3 Simulation Inductor Current Waveform lind: Rectified Input DC Current (Amperes) 30 Chapter 3 Hardware Implementation 3: RMS Current through IGBT When the switching frequency is much higher than the ac line frequency, then the RMS value can be well-approximated as a double integral. The square of the current is integrated first to find its average over a switching period, and the result is then integrated to find the average over the ac line period. ‘Lrms X = 400x400 = 4.64(A) (3-11)R0 230 150x230 ‘Qrms ‘Lrms 4.64(A) (342) Certainly, the RMS current value of IGBT can be calculated as following: ‘Qrms = fTj 1Q2dt = J1 çTa 1 ft+Ts L (r) dr dt I 8V — ‘Lrms41 = 4.64 Ii — --- 2.58(A) (3-13)3ir 400 According to these values estimated above, the part number of IGBT for this project is chosen as: IRG4PC3OWPBF. Its parameters are listed in the following table. The WARP for this kind of IGBT is: 60kHz —l50kHz. VCES (V) VcoN) (V) Ic (25°C) (A) Tc (100°C) (A) PD (W) 600 2.7 23 12 100 Table 3.2 Parameters of IGBT 3.1.3 The Choice of Diode in Boost Converter At first, it should be known which kind of diode should be chosen for this boost converter. Generally speaking, for this kind of high frequency application, a fast recovery diode, an ultra-fast recovery diode or a Schottky diode should be used. In order to make an appropriate choice for this project, the reverse peak voltage across the diode, the average current through the diode and the RMS diode current should be known. In the following, these three parameters will be calculated at first and then the suitable diode for 31 Chapter 3 Hardware Implementation this boost converter will be chosen. 1: The Reverse Peak Voltage across the Diode According to common knowledge of the boost converter, the main switch will conduct during the period of [0, DT5] in each switching cycle and the diode will be in “OFF’ state in this period of time, therefore, the reverse voltage across this diode is equal to the output voltage “V0”. Certainly, the reverse peak diode voltage “VDp” is equal to the maximum of the output voltage. According to this principle, there is: VDP = V0, + 1xV0 V0, + x DT5 407(V) (3-14) 2: The Average Current through the Diode ‘Davg = L dt = 1[fDTs iDdt + j7 iDdt] = 1 [(IL+1tL)±(IL_LtL)j X (I. — D)Ts = ‘L X (1 — D) = X (1 D) = Jo = = 2.67(A) (3-15)R0 150 3: The RMS Current Value through Diode Because the duty cycle of the boost converter is less than “1.0” for steady state, the RMS current value through diode must be less than that of inductor current. From the expression (3-11), it can be seen that the RMS value of inductor current is equal to 4.64 Amperes. Therefore, there is: ‘Drms 4.64(A) (316) With regard to the strict mathematical calculation, it is easy to do it in a similar way according to the definition of RMS. There is no need to calculate it again. According to simulation, its value is equal to: ‘Drms = 3.04(A) (347) 4: The Loss on Diode due to Voltage Drop Generally speaking, the voltage drop across a diode is about “0.7Volts” when the diode is “ON”. Therefore, the loss is approximately equal to: D1oss 0.7 X ‘Drms = 0.7 X 3.04 2.128(W) (348) 32 Chapter 3 Hardware Implementation According to these calculated values and the requirement of this project, the ultra-fast high voltage rectifier (one diode) is used. Its part number is: STTH8LO6. Please see Table 3.3 for its parameters. Reverse Peak Voltage (V) Forward RMS Current (A) Forward Voltage (V) 600 8 1.05 40750 407.00 406.00 406 00 406.50 405.00 4040 Fig. 3.4 The Simulation Output Voltage Wave Form at One-third Load V0: Output Voltage of This APFC (Volts) From this figure, it can be seen that the maximum output voltage value is about Table 3.3 Parameters of the Main Circuit Diode 3.1.4 The Choice of the Output Capacitor The principle to choose a capacitor is to make clear its peak voltage value and its RMS current value at first and then to choose a suitable capacitor with a margin of 15% -, 20% calculated value. Here, these two parameters will be calculated in the following: 1: The Peak Voltage Value of the Output Capacitor It is very important to make the peak voltage value of the capacitor less than its rated value, otherwise, the capacitor will break. In order to satisfy this requirement, its peak voltage value for every possible cases should be known and choose the worst one to act as a reference. Please see Fig. 3.4 for the output voltage wave form at one-third load situation. 104.00 150.00 160.00 170.00 180 C,,.) 200.00 33 Chapter 3 Hardware Implementation 407.2 Volts. Because the output voltage is equal to the capacitor voltage, the peak capacitor voltage value is equal to: V, = V0, 407.2(V) (3-19) 2: The RMS Current through the Capacitor ‘Crms = j2dt = [JDTS (_Vo)2 dt + ç’; ( V) dt] (3-20) R0 (1 D)R0 From this expression, it can be found that the duty cycle “D” should be known at first in order to calculate the RMS value of the current. The purpose to calculate RMS value is to estimate its dissipation; it is a total average effect for the capacitor. Therefore, the average input voltage value and the rated output voltage value of the boost converter should be used to get the average duty cycle for this converter under steady state. The average input voltage value of the converter is: — 2fT/2VSiflwtdt Vm 2)<325 = 207(V) (3-21) V0 = (3-22) 1— D = = 0.52 (3-23) V0 398 Therefore, the average duty cycle for this converter under steady state is equal to: D = 1 — 0.52 = 0.48 (3-24) In practice, it is well known that the conduction resistance R0 of IGBT, the winding resistance of the inductor, the conduction resistance of the diode and its conduction voltage drop will make the output voltage reduce. In order to make the output voltage equal to the rated value, the feedback control circuit will increase the duty cycle accordingly. Therefore, it will be a little more reasonable to calculate the RMS current value with “D =0.5”. In this way, the RMS current value through the capacitor can be calculated as following: ‘Crms = J(400)2 )< 0.5 + (400)2 x 0.5 = 2.67(A) (3-25) 34 Chapter 3 Hardware Implementation According to these two parameters, the part number of the output capacitor is chosen as: DCMC1O2T500BC2B; please see Table 3.4 for its parameters. Capacitance(1iF) Rate Voltage (V) RMS Current (A) ESR (mO) 1000 500 4.1 138.7 Table 3.4 Parameters of the Output Capacitor 3.1.5 The Determination of Inductor The determination of an inductor is to determine what kind of magnetic core and the suitable magnet wire should be used. After determination of the magnetic core and magnet wire, the required winding turns should be calculated approximately to get the required inductance. Generally speaking, there are two commonly used methods to design the inductor. They are AP method and KG method. Here, another method is used to design this inductor according to the instruction manual of MAGNETICS company. 1: The Determination of the Magnetic Core From the introduction of their several magnetic cores, it can be seen that the MAGNETICS Kool Mu powder cores are distributed air gap cores made from a ferrous alloy powder for low losses at elevated frequencies. The near zero magneto-striction alloy makes Kool Mji ideal for eliminating audible frequency noise in filter inductors. In high frequency applications, core losses of powdered iron, for instance, can be a major factor in contributing to undesirable temperature rises. Hence, Kool Mji cores are ideal because their losses are significantly less, resulting in lower temperature rises. It is possible that Kool M.i cores will offer a reduction in core size over powdered iron cores in a similar application. All these make them ideally suited for switching regulator inductors, flyback transformers and power factor correction (PFC) inductors. Therefore, the Kool Mu core is chosen for this inductor. There are two kinds of powdered Kool Mu cores, torroids cores and E cores. The principle to choose the suitable core is simple and cheaper. If the power is not very big, the torroids cores should be considered at first. Therefore, the Kool Mu powdered cores are used for this application. In the following, 35 Chapter 3 Hardware Implementation the appropriate core size number, the number of turns and the wire size for this inductor will be determined according to their manual step by step easily. For the detailed description of this procedure, please see them from: http://www.mag-inc.com. The core and wire will be determined in the following according to this procedure. 2: Calculation of “LI2” L =inductance required with dc bias (milli-Flenrys); I=dc current (Amperes) Because the small signal average current through the inductor is approximately dc half sine wave with the magnitude of 7.5 Amperes, the low frequency (5011z/6OFIz) average value can be used to represent its dc current. Its average value is: (‘L> f02ImS1flWtC1t = fImSiflWtdQi)t) = = 4.78(A) (3-26) LI2 = 1.0 x 4.782 23 (mH — Amperes2) (3-27) 3: Locate the LI2 value on the Core Selector Chart. Follow this coordinate to the intersection with the first core size that lies above the diagonal permeability line. (Small core sizes are at the bottom; large core sizes are at the top.) This is the smallest core size that can be used. From the Kool Mj.t Core Selector Chart, it can be seen that this coordinate passes through 60i section. Therefore, the core part number is: 77090; two stacked 77090 cores are used to make this inductor. 4: Determination of the Initial Number of Winding Turns From the core data sheet, the nominal inductance for this core can be found as: AL =86mHJl000turns ±8% Therefore, the minimum nominal inductance of this core is equal to: ALmin = 86 — 86 X 8% = 79•12(mH) (3-28) The inductance for a given number of turns is related to the nominal inductance by following expression: L = (3-29) Where: L = Inductance for N turns (mH) L1000 = nominal inductance (mHJ1000 turns) 36 Chapter 3 Hardware Implementation Therefore, the required winding turns to produce lml-I inductance can be calculated as following: 1 — L1000N2 — 79.12N2 — 106 — 106 N = 112 (turns) (3-30) 5: Calculation of Adjusted Number of Turns In order to get the adjusted number of turns, the bias in oersteds should be calculated at first. From the data sheet, the magnetic path length can be seen as: ‘e = 11.63 cm; According to the given expression, there is: H 0.4xirxNI = 0.4 x ir x 112 x -- 58(oersteds) (3-31) 11.63 From the Permeability vs. DC Bias curves of this core, the roll-off in per unit of initial permeability (ipu) can be determined as: 68% Therefore, the number of adjusted turns is equal to: Na = 165(turns) (3-32) 6: Choice of Wire Number The appropriate wire can be determined according to the current capacity easily. Here, AWG 16 magnet wire is chosen for this inductor. According to the relevant information about the inductor, it can be wound easily. Certainly, the winding turns perhaps need to be adjusted a little so that the inductance is equal to imil. With regard to other components in main circuit, there is no need to explain how to determine them in detail. 37 Chapter 3 Hardware Implementation This figure is removed because of no copyright permission. Fig. 3.5 Core Selector Chart 38 Chapter 3 Hardware Implementation This table is removed because of no copyright permission. Table 3.5 Data of Kool Mji Core 77090 39 Chapter 3 Hardware Implementation This table is removed because of no copyright permission. Table 3.6 Magnet Wire Table 40 Chapter 3 Hardware Implementation 3.2 The Basic Control Chip for This Circuit 3.2.1 Introduction of UC3854 Here, the basic control chip UC3854 is chosen to build the control circuit for this project. The APFC provides active power factor correction for power systems that otherwise would draw non-sinusoidal current from sinusoidal power lines. This device implements all the control functions necessary to build a power supply capable of optimally using available power-line current while minimizing line-current distortion. To do this, the UC3854 contains a voltage amplifier, an analog multiplier/divider, a current amplifier, and a fixed-frequency PWM. In addition, the UC3854 contains a power MOSFET compatible gate driver, 7.5V reference, line anticipator, load-enable comparator, low-supply detector, and over-current comparator. The UC3 854 uses average current-mode control to accomplish fixed frequency current control with stability and low distortion. Unlike peak current-mode control, average current control accurately maintains sinusoidal line current without slope compensation and with minimal response to noise transients. The UC3 854 high reference voltage and high oscillator amplitude minimize noise sensitivity while fast PWM elements permit chopping frequencies above 200kHz. The UC3854 can be used in single and three phase systems with line voltages that vary from 75Volts to 275Volts and line frequencies across the 50Hz to 400Hz range. To reduce the burden on the circuitry that supplies power to this device, the UC3 854 features low starting supply current. These devices are available packaged in 16-pin plastic and ceramic dual in-line packages, and a variety of surface-mount packages. 3.2.2 PIN DESCRIPTIONS of UC3854 In order to build an effective control circuit for this boost active power factor corrector with the basic control chip UC3 854, its inner structure and the function of its pins should be known. In this way, the whole control circuit can be built according to its instruction and the whole project circuit requirement. In order to be convenient to 41 Chapter 3 Hardware Implementation understand it easily, its structure diagram is listed as following: VAOUT MULTOUT CAOUT PKLJM Gnd (Pin 1) (ground): All voltages are measured with respect to Gnd. VCC and REF should be bypassed directly to Gnd with a O.1iF or larger ceramic capacitor. The timing capacitor discharge current also returns to this pin, so the lead from the oscillator timing capacitor to Gnd should also be as short and as direct as possible. PKLMT (Pin 2) (peak limit): The threshold for PKLMT is O.OV. Connect this input to the negative voltage on the current sense resistor as shown in Figure 3.1. Use a resistor to REF to offset the negative current sense signal up to Gnd. CA Out (Pin 3) (current amplifier output): This is the output of a wide-bandwidth op amp that senses line current and commands the pulse width modulator (PWM) to force the correct current. This output can swing close to Gnd, allowing the PWM to force zero duty cycle when necessary. The current amplifier will remain active even if the IC is disabled. The current amplifier output stage is an NPN emitter follower pull-up and an 8k resistor to ground. ISENSE (Pin 4) (current sense minus): This is the inverting input to the current amplifier. This input and the non-inverting input Mult Out remain functional down to and V$ENSE I SEN$E CT RSeT Fig. 3.6 Block Diagram of UC3854 42 Chapter 3 Hardware Implementation below Gnd. Care should be taken to avoid taking these inputs below —O.5V, because they are protected with diodes to Gnd. Mutt Out (Pin 5) (multiplier output and current sense plus): The output of the analog multiplier and the non-inverting input of the current amplifier are connected together at Mult Out. The cautions about taking ISENSE below —O.5V also apply to Mult Out. As the multiplier output is a current, this is a high impedance input similar to ISENSE, so the current amplifier can be configured as a differential amplifier to reject Gnd noise. IAC (Pin 6) (input AC current): This input to the analog multiplier is a current. The multiplier is tailored for very low distortion from this current input (IAC) to Mult Out, so, this is the only multiplier input that should be used for sensing instantaneous line voltage. The nominal voltage on JAC is 6V, so in addition to a resistor from IAC to rectified voltage, connect a resistor from TAC to REF. If the resistor to REF is one fourth of the value of the resistor to the rectifier, then the 6V offset will be cancelled, and the line current will have minimal cross-over distortion. VA Out (Pin 7) (voltage amplifier output): This is the output of the op amp that regulates output voltage. Like the current amplifier, the voltage amplifier will stay active even if the IC is disabled with either ENA or VCC. This means that large feedback capacitors across the amplifier will stay charged through momentary disable cycles. Voltage amplifier output levels below 1 V will inhibit multiplier output. The voltage amplifier output is internally limited to approximately 5.8V to prevent overshoot. The voltage amplifier output stage is an NPN emitter follower pull-up and an 8k resistor to ground. VRMS (Pin 8) (RMS line voltage): The output of a boost PWM is proportional to the input voltage, so when the line voltage into a low-bandwidth boost PWM voltage regulator changes, the output will change immediately and slowly recover to the regulated level. For these devices, the VRMS input compensates for line voltage changes 43 Chapter 3 Hardware Implementation if it is connected to a voltage proportional to the RMS input line voltage. For best control, the VRMS voltage should stay between 1.5V and 3.5V. REF (Pin 9) (voltage reference output): REF is the output of an accurate 7.5V voltage reference. This output is capable of delivering lOmA to peripheral circuitry and is internally short circuit current limited. REF is disabled and will remain at OV when VCC is low or when ENA is low. Bypass REF to Gnd with a 0.1iF or larger ceramic capacitor for best stability. ENA (Pin 10) (enable): ENA is a logic input that will enable the PWM output, voltage reference, and oscillator. ENA also will release the soft start clamp, allowing SS to rise. When unused, connect ENA to a +5V supply or pull ENA high with a 22k resistor. The ENA pin is not intended to be used as a high speed shutdown to the PWM output. VSENSE (Pin 11) (voltage amplifier inverting input): This is normally connected to a feedback network and to the boost converter output through a divider network. RSET (Pin 12) (oscillator charging current and multiplier limit set): A resistor from RSET to ground will program oscillator charging current and maximum multiplier output. Multiplier output current will not exceed 3.75V divided by the resistor from RSET to ground. SS (Pin 13) (soft start): SS will remain at Gnd as long as the IC is disabled or VCC is too low. SS will pull up to over 8V by an internal 14iA current source when both VCC becomes valid and the IC is enabled. SS will act as the reference input to the voltage amplifier if SS is below REF. With a large capacitor from SS to Gnd, the reference to the voltage regulating amplifier will rise slowly, and increase the PWM duty cycle slowly. In the event of a disable command or a supply dropout, SS will quickly discharge to ground and disable the PWM. CT (Pin 14) (oscillator timing capacitor): A capacitor from CT to Gnd will set the PWM oscillator frequency according to this relationship: F =1 .25IRSET - CT VCC (Pin 15) (positive supply voltage): Connect VCC to a stable source of at least 2OmA above 17V for normal operation. Also bypass VCC directly to Gnd to absorb 44 Chapter 3 Hardware Implementation supply current spikes required to charge external MOSFET gate capacitances. To prevent inadequate GT Dry signals, these devices will be inhibited unless VCC exceeds the upper under-voltage lockout threshold and remains above the lower threshold. GT Dry (Pin 16) (gate drive): The output of the PWM is a totem pole MOSFET gate driver on GT Dry. This output is internally clamped to 15V so that the IC can be operated with VCC as high as 35V. Use a series gate resistor of at least 5 ohms to prevent interaction between the gate impedance and the GT Dry output driver that might cause the GT Dry output to overshoot excessively. Some overshoot of the GT Dry output is always expected when driving a capacitive load. 3.3 IGBT Gate Driver for This Circuit Insulated gate bipolar transistors (IGBTs) are gaining considerable use in circuits requiring high voltage and current at moderate switching frequencies. Much of the popularity of IGBT stems from its simple MOSFET-like gate drive requirement. IGBT gate drive requirements can be divided into two basic application categories: Those that do not apply high dv/dt to the collector/emitter of the IGBT when it is off, and those that do [14], [15]. Examples of the former are boost regulators and forward converters, where only one switch is employed or multiple switches are activated synchronously. High dv/dt is applied during the off-state in most bridge circuits such as inverters and motor controllers, when opposing devices are turned on. Simultaneous conduction of opposing devices can occur in such circuits, often with catastrophic results if proper gate drive and layout precautions are not followed. This behaviour is caused by parasitic collector to gate (Miller) capacitance, effectively forming a capacitive divider with the gate to emitter capacitance and thus inducing a gate to emitter voltage as illustrated in Fig. 3.7. 45 Chapter 3 Hardware Implementation C I — -Ccg - IGT z Cge E Fig. 3.7 IGBT with Miller Capacitance When high off-state dv/dt is not present, the IGBT can be driven like a MOSFET using any of the gate drive circuits in the UC37XX family as well as from the drivers internal to many switching power supply controllers. Normally fifteen volts is applied from gate to emitter during the on-state to minimize saturation voltage. The gate resistor or gate drive current directly controls IGBT turn-on; however turn-off is partially governed by minority carrier behaviour and is less affected by gate drive. Therefore, the internal gate drive in UC3854 and a gate resistor RG (1500) are used to drive IGBT directly in this project circuit. 46 Chapter 4 Project Simulation Chapter 4 Project Simulation The schematic circuit and the hardware implementation for this project have been described in chapter 2 and chapter 3. The next step for the engineering design is to make the whole project simulation and revise the original circuit until the project specifications can be satisfied. Here, the PSIM 6.0 is used to simulate this whole project circuit for all possible situations. After the simulation and revision, the satisfactory results are gained. Here, it can be seen that this APFC circuit can work very well under the European input line power (230V/5OHz/6OHz) and the Asian line power (220V/5OHz/6OHz). The reason to take these two standards into account for this project design is mainly to enlarge its application area and make this APFC circuit more useful. In the end, another two simulations for input line powers of 200V/5OHz/6OHz and 240V/5OHz/6OHz will be listed respectively. 4.1 The Simulation for 230V/5OHz Input Power Three different situations will be simulated under this input power. They are full load (Ro=1500), half load (Ro=3000) and one-third load (Ro=4500) because the active power factor corrector must be able to work satisfactorily when the load changes. This wide load scope will be able to satisfy the practical engineering requirement. You will find that the no load situation is not taken into account for the project simulation here. The reason is that the input power will be equal to zero theoretically when the output power is equal to zero. Therefore, it will have very little influence on the input power and other neighboring equipments. Besides this, it can be found that the current feedback branch will be broken when the output current is equal to zero, so, it can be concluded that this circuit can not realize the APFC function for the no load situation. Certainly, the 47 Chapter 4 Project Simulation output current is not equal to zero for practical engineering problem, but it is very little and can be neglected. 4.1.1 The Simulation Circuit UC3854 Controlled PFC Converter Fig. 4.1 Simulation Circuit for 230V/5OHz/6OHz 48 4.1.2 Simulations 1: The waveform at full load situation (R15O Ohms/f=5OHz): 400.00 20000 0.00 •200.0D .400.00 On 10.00 0.00 0.00 •000 -10 00 Chapter 4 Project Simulation 200 5.00 4.00 3.00 2.00 1.00 0 00 0 00 Feqnoy(MHz) Fig. 4.2 Simulation of V and for Full Load Situation 10000 Thle (mo) 17000 180.00 0.02 0.04 0.00 0.08 0.10 V1: Input Line Voltage (Volts) Tm: Input Line Current (Amperes) 49 Chapter 4 Project Simulation 404.00 302 00 400 00 398.00 306.00 394.00 392.00 160.00 200.00 nd 200 .00 Fig. 4.2[A] Simulation of V0 and ‘md for Full Load Situation 1md Rectified DC Current (Amperes) V0: APFC Output Voltage (Volts) For ideal case, the input power is equal to output power, there is: = = jj2 398x398 = 1056 (W) (4-1) PF = = 1056 0.998 (4-2) VrmsXlrms 230X4.597 160.00 170.00 100.00 190.00 Time (ms) 8.00 600 4.00 2.00 .2.00 150.00 160.00 170.00 180.00 100.00 Time (me) 50 Chapter 4 Project Simulation 2: The wave forms at half load (R=300 Ohms/f=5OHz): 6.80 Mn 100MB 20:: 4c 28008 18.00 160.00 170,00 180.00 190.00 200.00 lime (no) 2.50 2.00 1.50 1.00 o.oo 0.00 _- 0.00 0.02 0.04 0.06 0.06 0.10 Frequency(MHz) Fig. 4.3 Simulation of ‘in and Vin for Half Load Situation Vu2: Input Line Voltage (Volts) I: Input Line Current (Amperes) 51 Chapter 4 Project Simulation 5.00 4.00 3.00 2.00 1.00 0.00 -1.00 150.00 ‘106.00 ‘106.00 ‘104.00 ‘103.00 402.00 ‘101.00 150.00 md 160.00 170.00 100.00 190.00 Time (ms) 200.00 160.00 170,00 100.00 190.00 200.00 Time(ms) Fig. 4.3[A] Simulation of ‘md and V0 for Half Load Situation Jind: Rectified DC Current (Amperes) V0: APFC Output Voltage (Volts) 52 Chapter 4 Project Simulation 3: The waveform at one third load situation(R=450 Ohms/f=5011z): 100 flO 170 no ioono 200n0 0,00 002 0.04 0.00 0.08 0.10 Frqoeny(MHz) Fig. 4.4 Simulation of I• and V1, for One Third Load V1: Input Line Voltage (Volts) I: Input Line Current (Amperes) 3.00 2no 1 no -1.00 -2.00 .3.00 An 400.00 200.00 0.U0\ / -20000 NI -400.00 ___________________________......... .___________________________ - 100.00 1in (mo) 1.70 1.50 1.25 1.00 0.75 0.50 0.20 0.00 53 Chapter 4 Project Simulatioa 407.50 40700 406 50 4t 50 405.50 aJ5.0o 404.50 404.00 150.00 Fig. 4.4[A] Simulation of ‘md and V0 for One Third Load Tind Rectified DC Current (Amperes) V0: APFC Output Voltage (Volts) From these simulations listed above, it can be seen that this Boost APFC circuit can satisfy the requirement under the required load scope. This suggests that it is a feasible design for this project and it can improve the power factor nearly equal to unity and reduce the harmonic distortion greatly. O.OOTJI• 4 :ul -0.50 150.00 150.00 17000 160.00 100.00 200.00 Time (me) 150.00 170.00 180.00 100.00 200.00 Time (me) 54 Chapter 4 Project Simulation 4.2 The Simulation for 230V/6OHz Input Power In order to verify that this Boost APFC circuit can work well when the input line frequency is 60Hz, the simulation for this situation is made. It is meaningful to do so because the line frequency for North American Standard is 60Hz; this project design will be more applicable if it can satisfy the specifications under this situation. The simulations are as following: 1: The waveform at full load situation (R=150 Ohms! f=6OHz): 10.00 410.00 OOO / 20000 •400M0 ____________________ ____ ________________ _______ 150.00 160,00 170.00 100.00 190.00 200.00 lime (ins) Fig. 4.5 Full Load Simulation of V11 and ‘in (f=6OHz) V0: Input Line Voltage (Volts) Ith: Input Line Current (Amperes) 55 Chapter 4 Project Simulation Fig. 4.5[A] Full Load Simulation of ‘md and V0 (f=6OHz) lind: Rectified DC Current (Amperes) V0: APFC Output Voltage (Volts) It can be found the power factor for 60Hz is nearly the same as that for 50Hz. hd 8.00 6.00 4.00 2.00 0.00 -2.00 150.00 402.00 400.00 398.00 396.00 304,00 392,00 150.00 160.00 170.00 180.00 100.00 Time (mi) 200.00 160.00 170.00 180.00 100.00 200.00 Time (ms) 56 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 V1: Input Line Voltage (Volts) I: Input Line Current (Amperes) Chapter 4 Project Simulation 2: The waveform at half load situation (R=300 Ohms! f=6OHz): 400.00 2.00 0.00 400.00 150.00 160.00 170.00 100.00 100.00 Time (ms) 200,00 0.00 0.02 0.04 0.00 0.00 0.10 Frequericy(MHZ) Fig. 4.6 Half Load Simulation of ‘in and V1 (f=6OHz) 57 Imd: Rectified DC Current (Amperes) V0: APFC Output Voltage (Volts) Chapter 4 Project Simulation 5.00 400 3.00 2.00 1.00 0.00 •1.OO 160.00 100.00 170.00 180.00 100.00 200.00 Time (ms) 406.00 405.00 404.00 403,00 402.00 401.00 150.00 160.00 170.00 180.00 100.00 Tirne(m) 200,00 Fig. 4.6[A] Half Load Simulation of ‘md and V0 (f=6OHz) 58 Chapter 4 Project Simulation 3: The waveform at one-third load situation (R=450 Ohms/f =60Hz): 3.00 2M0 1.00 0.00 •1 .00 2.00 3.00 10 400,00 200.00 0.00 •200.00 •400.00 100.00 1600 170.00 100.00 100.00 2000 lime (no) 2.50 2.00 i.so[ . 1.00 . 0.50 , 0.00 0 00 0.02 0 04 0.06 0.08 0.10 Frequency(MHz) Fig. 4.7 One-third Load Simulation of Im and V1, (f=6OHz) Vj: Input Line Voltage (Volts) I: Input Line Current (Amperes) K...:/ / / N\\j lii 59 Chapter 4 Project Simulation 3.00 2.50 2.00 1.50 1.00 0.50 0.00 Fig. 4.7[AJ One-third Load Simulation of ‘md and V0 (f=6OHz) Imd Rectified DC Current (Amperes) V0: APFC Output Voltage (Volts) From the simulations listed above when input line frequency is equal to 60Hz, it can be found that the Boost APFC circuit still works well and the power factor is nearly equal to unity. 0.50 150.00 160.00 17000 180.00 100.00 200.00 Time (ms) 407.00 406.50 406.00 405.50 404.50 404.00 150.00 Time (ms) 150.00 170.00 180.00 100.00 200.00 60 Chapter 4 Project Simulation 4.3 The Simulation for 220V/5OHz Input Power In order to verify that this Boost APFC circuit can be used for Asian Standard (220V/5OHz) input line power, the simulations for this situation are made under three cases: full load, half load and one-third load. The simulation wave forms are listed in the following. It can be found that this project design can work very well for the Asian Standard input power, too. Therefore, this project design is a very useful circuit. This will be very important for a commercial project design because many large companies are international companies at present and they probably have branch companies in Europe, North America or Asian countries. If this characteristic can be taken into account and make the design satisfy this requirement, it will be very helpful to promote the commercial market for the project design. 1: The waveform at full load situation (R=150 Ohms! f=5OHz): Fig. 4.8 Full Load Simulation of ‘in and (220V!5OHz) Vm: Input Line Voltage (Volts) Im: Input Line Current (Amperes) 10.00 5.00 0.00 -5.00 -10,00 400.00 200.00 0.00 -200.00 -400.00 150.00 150.00 170.00 100.00 100.00 lime (ins) 200.00 61 0.00 2 00 -2.00 0.04 0.06 0.09 Fr.quency(MHz) Fig. 4.8[A] Full Load Simulation of ‘md and V0 (220V/SOHz) For the ideal case, input power is equal to output power, there is: = = = 398:398 1056 (W) PF = P = 1056 0.993 Vrmslrms 220x4.835 Chapter 4 Project Simulation 0 00 100.00 100.00 170.02 100.00 100.00 Time (me) 200.00 H ::. k-i. - \... 7 . 204.00[ / 002.00 __-....-. -: 000 j—- _____ — 4.00 2.00 2 00 1.00 000 _._.-_ —. 0.00 0.02 0.10 Jind: Rectified DC Current (Amperes) V0: APFC Output Voltage (Volts) (4-3) (4-4) 62 600 400.00 200,00 0,00 -200.00 -40000 0.00 0.02 0fl4 0.06 0.08 0.10 Chapter 4 Project Simulation 2: The waveform at half load situation (R=300 Ohms! f=5011z): 150.00 180.00 170.00 180.00 190.00 Time (me) ‘“-I 200.00 3.50 2.50 2.00 1.50 1.00 0.50 0.00 F re q U CC (1.1 Hz) Fig. 4.9 Half Load Simulation of and (220V/SOHz) V: Input Line Voltage (Volts) I: Input Line Current (Amperes) 63 400 200 000 .2.00 -400 -0.00 500 —- -- _______ — -. —- ---- --- — -100 15000 16000 17000 18000 19000 200.00 ir Chapter 4 Project Simulation lime (rns) 408.00 405 404.00 403.00 402.00 401.00 150.00 180.00 170.00 180.00 190.00 Time (n,s) 200.00 Fig. 4.9[A] Half Load Simulation of ‘md and V0 (220VI5OHz) ‘ind Rectified DC Current (Amperes) V0: APFC Output Voltage (Volts) 64 Chapter 4 Project Simulatioa 3: The waveform at one-third load situation (R=450 Ohms! f=5OHz): 480.00 20000 8.00 200.00 -400.00 — 10.00 160.00 170.00 180,00 200.00 0.00 0.02 0.04 0.06 0.08 0.10 Fig. 4.10 One-third Load Simulation of ‘in and Von (220V!5OHz) V: Input Line Voltage (Volts) I: Input Line Current (Amperes) 400 2.00 0.00 -2.00 -4.00 11mg (ris) 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 00 Frequency(MHz) 65 Chapter 4 Project Simulation 400.00 407.00 40600 405.00 404.00 403.00 160.00 200,00 4.00 2.00 0.00 •2.0D -4.00 4.00 3.00 2.00 1.00 0.00 -1.00 150.00 200.00 Fig. 4.10[A] One-third Load Simulation of V0, ‘in and ‘md (220V/5OHz) Imd: Rectified DC Current (Amperes) V0: APFC Output Voltage (Volts) From these simulation waveforms, it can be seen clearly that the performance of this active power factor corrector can work excellently for Asian Standard input power and the input power factor is nearly equal to one for three cases. 160.00 170.00 100.00 100.00 Ttme (ms) 160.00 170.00 180.00 100.00 lim€ (ms) 66 Chapter 4 Project Simulation 4.4 The Simulation for 220V/6OHz Input Power In order to check whether this circuit can work with 60Hz line frequency input power or not, the simulation for this kind of input power is made. It will be meaningful for North American countries if it can work well too. Simulations for three cases (Full load, half load and one-third load) are made to verify that it can work satisfactorily. 1: The waveform at full load situation (R=150 Ohms! f=6OHz): 10.00 -10.00 - -.-.. -. 400.00 —.——.—...—....-___________ _________________ 20000 -7 . //‘\ - 0.00 -200.00 \......;// -400.00 _________________________ ______ _____- _____________ 160.00 16000 170.60 160.00 160.00 200.00 1ir,. (r,s) 7.00 6.00 6.00 4.00 3.00 2.00 : 1.00 0.00 —.——. -... . 0.00 0.02 0.04 0.06 0.06 0.10 Fr,q.ny(MHz) Fig. 4.11 Full Load Simulation of ‘in and V1 (220V/6OHz) V: Input Line Voltage (Volts) Im: Input Line Current (Amperes) 67 Chapter 4 Project Simulation 000 5.00 0.00 .5.00 .10.00 8 00 6.00 4.00 2,00 000 -2.00 150.00 200.00 10200 400.00 308.00 306.00 394.00 302.00 150.00 Fig. 4.11[A] Full Load Simulation of Im, ‘md and V0 (220V/6OHz) lind: Rectified DC Current (Amperes) V0: APFC Output Voltage (Volts) It can be found that the power factor for 60Hz is nearly the same as that for 50Hz. [rd 160.00 170.00 180.00 00.00 Time (ins) Time (ms) 160.00 170.00 100.00 190.00 200.00 68 Chapter 4 Project Simulation 2: The waveform at half load situation (R=300 Ohms! f=6OFIz): 6.00 -6,00 4000 ‘‘ 20::: /\ /\ /\ •200 -400M0 160.00 160.00 170.00 100.00 100.00 200.00 lime (ins) 4.00 3.00 2,00 . 1,00 0,00 —- ,-.——__..— -___ 0.00 0.02 0.04 0.06 0.08 0.10 Frequenoy(MHz) Fig. 4.12 Half Load Simulation of I and V1 (220V/6OHz) V: Input Line Voltage (Volts) 1133. Input Line Current (Amperes) 69 8.00 406.00 406.00 404.00 402.00 402.00 hr md ‘10 200.00 200.00 Chapter 4 Project Simulation .6.00- : _-_ 5.00 4.00 3,00 2.00 1.00 0.00 •1.00 150.00 150.00 170.00 180.00 100.00 lime (ins) 401.00 150.00 100.00 170.00 100.00 100.00 Time (ms) Fig. 4.12[A] Half Load Simulation of I, ‘md and V0 (220V/6OHz) I1M: Rectified DC Current (Amperes) V0: APFC Output Voltage (Volts) 70 Chapter 4 Project Simulation 3: The waveform at one-third load situation (R=450 Ohms! f=6OHz): 4.00 200 0.00 -2.00 .400 400,00 200.00 0.00 -200.00 -400.00 160.00 160.00 170.00 Tue (no) 100.00 2.80 2.03 1.50 1.00 0.50 000 — 0 00 0.00 0.10002 004 0.08 Frequeriey (MHz) Fig. 4.13 One-third Load Simulation of ‘in and Vin (220V!6OHz) V: ffiput Line Voltage (Volts) I: Input Line Current (Amperes) 71 Chapter 4 Project Simulation 4.00 2 00 000 -2.00 -4.00 4.00 3.00 2.00 1.00 0.00 -1.00 160.00 405 404.50 Fig. 4.13[A] One-third Load Simulation of ‘md and V0 (220V/6OHz) 200.00 Tmd Rectified DC Current (Amperes) V0: APFC Output Voltage (Volts) From these three simulation waveforms, it can be found that this circuit can be used directly in this situation. Certainly, it is meaningful to check that this project circuit can work well when the input power is 220V/5OHz/6OHz only for use in one region. This is because the input line voltage often has an error and fluctuations, too. Id lime (ms) 160.00 170.00 160.00 100.00 200.00 407.00 6.00 405 50 Time (ins) ‘104.00 15000 160.00 170.00 180.00 190.00 72 4.5 The Simulation for 200V/6OHz Input Power Chapter 4 Project Simulation 30000 .----—-.——- 200.00 [../.Th.... 101.00 \./. _ _______ 10.00 .000ç/’s -10.08 -.-----—..——____________________________ 100.fi2 160.00 170.00 100.00 200.00 000 O 00 Here, the performance of this active power factor corrector for this situation will be checked. At first, the simulation for input line frequency of 60Hz will be made. The corresponding wave forms are listed as following. 1. The wave form under full load situation (R=l500hms/f =60Hz) lime (ms) 402J ‘100.00 30800 396.00 304.00 392.00 100,00 100,00 170.00 180.00 100.00 Time (ms) 200 00 Fig. 4.14 Full Load Simulation of V1, ‘in and V0 (200V/6OHz) V: kiput Line Voltage (Volts) I: Input Line Current (Amperes) V0: APFC Output Voltage (Volts) 73 Chapter 4 Project Simulation 10.00 8.00 6.00 4,00 200 0.00 -2.00 300.00 250.00 200.00 1.00, 100.00 50.00 0.00 150.00 [ird / / r \ / _____ \/ lime (mc) 160.00 170.00 100.00 100.00 hr 200.00 8.00 6.00 . 4.00 2.00 0.00 ‘———--.‘..—..-- — ———.—-— Frequency (MHz) Fig. 4.14[A] Full Load Simulation of ‘md and Vd (200V/60Hz) lind: Rectified DC Current (Amperes) Vd: Rectified DC Voltage (Volts) 000 0.02 0.04 0.06 0.08 0.10 74 2. The wave form for half load situation (R=3000hms/f =60Hz) Chapter 4 Project Simulation 100.00 \ / /‘ :::Lzzzzzzzz/ 6.00 4.00 2.00 0.00 .2.00 -4.00 Frequny (MHz) Fig. 4.15 Half Load Simulation of V and (200V/6OHz) 160.00 170.00 100.00 1im (ms) 200.00 -600 150.00 4.00 3.00 2.00 1.00 0.00 0.00 0.02 0.04 0.08 0.08 0.10 V1: Input Line Voltage (Volts) I: Input Line Current (Amperes) 75 5.00 4.00 3.00 2.00 1.00 0.00 -1.00 300.00 — 250.00 200.00 150.00 100.00 50.00 0.00 150.00 Chapter 4 Project Simulation 406.00 405.00 404.00 403.00 102.00 401.00 150.00 160.00 170.00 180.00 100.00 Time (ms) 200.00 / _ /7 \/‘ V 160.00 170,00 100.00 190.00 200.00 lime(ms) Fig. 4.15[A] Half Load Simulation V0, ‘md and Vd (200V/6OHz) lind: Rectified DC Current (Amperes) Vd: Rectified DC Voltage (Volts) V0: APFC Output Voltage (Volts) 76 Chapter 4 Project Simulation 3. The wave form for one-third load situation (R=4500hms/f =60Hz) /: I--...*cr..——\z/cz/ 4.00 2.00 0.00 0.00 0.02 004 0.06 0.08 0.10 Frequency(MHz) Fig. 4.16 One-third Load Simulation of Vb and ‘in (200V/6OHz) V: ifiput Line Voltage (Volts) I: thput Line Current (Amperes) 300.00 200.00 100.00 000 -100.00 -200.00 -300.00 -2.00 -4.00 150.00 160.00 170.00 180.00 180.00 lime (ms) 200.00 3.00 2.50 2 00 1.50 1.00 0.50 0.00 77 Chapter 4 Project Simulation 105.50 405.00 104.50 4040 200.00 4.00 3.00 2.00 1.00 0.00 -1.00 300.00 200.00 200.00 100.00 100.00 00.08 0.00 150.00 160.00 170.00 180.00 180.00 200.00 lime (ms) Fig. 4.16[A] One-third Load Simulation of V0, ‘md and Vd (200V/6OHz) Tind Rectified DC Current (Amperes) Vd: Rectified DC Voltage (Volts) V0: APFC Output Voltage (Volts) 407.00 406.00 150.00 160.00 170.00 180.00 190.00 Time (ms) / \/ 78 4.6 The Simulation for 200V/5OHz Input Power Chapter 4 Project Simulation In this section, the performance of this Boost APFC under 50Hz input line frequency will be checked. It is useful to do this because it is possible for this circuit to work under this input power situation. The simulations are listed in the following. 1. The wave form under full load situation (R= 1 500hms/f =50Hz) L ___ __ 800 6.00 4.00 3.00 2.00 1 00 0 00 0.00 002 004 0.06 0.08 0.10 300.00 200.00 100.00 0.00 -100.00 -200.00 -300.00 10 00 5.00 0.00 -5.00 -10.00 150.00 16000 170.00 r. (ms) 180.00 100.00 F.qny(MH) Fig. 4.17 Full Load Simulation of V and Im (200V/5OHz) V: Input Line Voltage (Volts) L: Input Line Current (Amperes) 79 Chapter 4 Project Simulation 8.00 6.00 4.00 2,00 0.00 300.00 E1 P\ //\ P\ 150.00 160.00 170.00 180.00 190.00 200.00 lind: Rectified DC Current (Amperes) Vd: Rectified DC Voltage (Volts) V0: APFC Output Voltage (Volts) Time (mo) 10.00 404.00 402.00 400.00 39 00 30 00 30400 30200 150.00 Fig. 4.17[A] Full Load Simulation of ‘md, Vd and V0 (200V/5OHz) 180.00 170.00 180.00 180.00 Tine (,,) 200.00 80 Chapter 4 Project Simulation 300.00 200.00 00.00 0.00 -100.00 -200.00 -300.00 100.00 190.00 200.00 0.00 0.02 0.04 0.00 0.00 0.10 Fig. 4.18 Half Load Simulation of V1 and J (200V/5OHz) V: Input Line Voltage (Volts) I0. Input Line Current (Amperes) 2. The wave form under half load situation (R=3000hmsIf =50Hz) / 160.00 170,00 lime (ms) 6.00 4.00 2.00 0.00 -2.00 -4.00 -6.00 160.00 3.00 -— 2.60 2.00 1.50 1.00 0.50 0.00 AL Frequency (MHz) 81 Chapter 4 Project Simulation .1,00 300.00 250.00 200.00 150.00 100.00 50.00 0.00 150.00 nd 4.00 3.00 2.00 .00 0.00 .t / I time (no) 160.00 170.00 180.00 180.00 200.00 400.00 105.00 104.00 403.00 402.00 401.00 150.00 160.00 170.00 180.00 190.00 200.00 Time (ms) Fig. 4.18[A] Half Load Simulation of ‘md, Vd and V0 (200V/5OHz) lind: Rectified DC Current (Amperes) Vd: Rectified DC Voltage (Volts) V0: APFC Output Voltage (Volts) 82 Chapter 4 Project Simulation 3. The wave form under one-third load situation (R=4500hms/f =50Hz) 200.00 200.00 100.00 E0 ____ -4.00 160.00 160.00 170.00 100.00 100.00 200.00 lime (mo) 2.00 1.00 too 0.00 0.00 0.00 0.02 0.04 0.06 0.08 0.10 Frequenoy(MHz) Fig. 4.19 One-third Load Simulation of Vim and ‘in (200V/5OHz) V0: Input Line Voltage (Volts) Ijfl; Input Line Current (Amperes) 83 Chapter 4 Project Simulation 4.00 3.00 2.00 1.00 0.00 -0.00 300.00 250,00 200.00 150.00 100.00 50.00 400.00 407.00 408.00 405.00 404.00 403.00 150.00 180.00 170.00 100.00 190.00 200.00 Time (ins) ird 0.00 150.00 *?7 \ P ‘_.\. V .r/. 18000 17000 10000 190.00 200.00 Fig. 4.19[AJ One-third Load Simulation of V0, ‘md and Vd (200V/5OHz) lime (ins) Ihsd: Rectified DC Current (Amperes) Vd: Rectified DC Voltage (Volts) V0: APFC Output Voltage (Volts) 84 Chapter 4 Project Simulation 4.7 The Simulation for 240V/6OHz Input Power The practical input line power often fluctuates to some extent and makes the voltage more or less than the rated voltage. In order to ensure this Boost APFC circuit work normally for the rated 230V/5OHz/6OHz input line power, its performance under the input line power of 240V/5OHz/6OHz should be simulated accordingly. The simulation wave forms are listed as following. 1. The wave form under full load situation (R=l500hms/f =60Hz) 400.80 20:: /\ / •200.00 .....................\......./ /40.0L... 10.00 .... .— ......_ .-.... . 5.00 . 150.00 100.00 170.00 100.00 100.00 200.00 li,o. (rro) 7.00 .. . 5.00 500 4.00 3.00 2.00 . . . 100 0.00 —...———- 0.00 002 0.04 0.00 0.10 Fr.qny(MH) Fig. 4.20 Full Load Simulation of V1 and (240V/6OHz) V1: Input Line Voltage (Volts) I: Input Line Current (Amperes) 85 Chapter 4 Project Simulation 8.00 4.00 2.00 0.00 402.00 398.00 396.00 384.00 382.00 150.00 160.00 170.00 180.00 100.00 Time (ms) 8.00 203,00 350.00 300.00 F 250,00 200.00 150.00 100.00 50.00 0.00 150.00 ñji’ /::E/2c*ñ1! V 180.00 170.00 180.00 190.00 200.00 Fig. 4.20[A] Full Load Simulation of V00 ‘md and V6 (240V/6OHz) lime (ms) lind: Rectified DC Current (Amperes) Vd: Rectified DC Voltage (Volts) V0: APFC Output Voltage (Volts) 86 400.00 —________________________________ ________________________ 000 ( / \\ _Z \/-200.00 -400.00 4.00 2.00 0.00 -2.00 -4.00 10.00 0.00 0.02 0.04 0.00 0.08 Fig. 4.21 Half Load Simulation of V1,and I (240V/6OHz) 0.10 Chapter 4 Project Simulation 2. The wave form under half load situation (R=3000hmsIf =60Hz) Fr 160.00 170.00 100.00 190,00 tim€ (mo) 3 50 3.00 2.50 2.00 1 50 1.00 0.50 0.00 200.00 Freq.ny (MHz) V1: Input Line Voltage (Volts) Ijfl: Input Line Current (Amperes) 87 Chapter 4 Project Simulation 400.00 405.00 404.00 403.00 402,00 401.00 200.00 4.00 3.00 2.00 1.00 0.00 -1.00 350.00 -___ _ : :::tN”:::±2 :! \/ \i / \/ 1:: / V V v V __ on— 150.00 160.00 170.00 100.00 180.00 200.00 Time (mo) Fig. 4.21[A] Half Load Simulation of V0, ‘md and Vd (240V/6OHz) ‘ind Rectified DC Current (Amperes) Vd: Rectified DC Voltage (Volts) V0: APFC Output Voltage (Volts) 160.00 160.00 170.00 180.00 100.00 Time (ms) 88 Chapter 4 Project Simulation 3. The wave form under one-third load situation (R=4500hmsIf =60Hz) 180.00 200.00 0.00 -200.00 410.00 -i.oo[. 1. 160.00 16000 17000 18000 190.00 200.00 1me (ms) 0.00 0.02 0.04 0.06 0.08 0.10 F rzq n (M Hz) Fig. 4.22 One-third Load Simulation of V1and ‘in (240V/6OHz) 7/ / 2.50 2.00 1.50 1.00 0.50 0.00 1. Vin: kiput Line Voltage (Volts) Input Line Current (Amperes) 89 Chapter 4 Project Simulation 406.00 105.00 404.00 403.00 402.00 401.00 200.00 2.50 2.00 1.50 1.00 0.50 0.00 350.00 300.00 250,00 200.00 150.00 100.00 50.00 0.00 160.00 160.00 170.00 180.00 190.00 200.00 lime (ms) Fig. 4.22[A] One-third Load Simulation of V0, ‘md and Vd (240V/6OHz) lind: Rectified DC Current (Amperes) Vd: Rectified DC Voltage (Volts) V0: APFC Output Voltage (Volts) 150.00 160.00 170.00 180.00 180.00 Time (ms) 3.00 T /\ :7 /\ P\fV____ “V 90 4.8 The Simulation for 240V/5OHz Input Power Chapter 4 Project Simulation For the same reason as before, the performance of this project circuit under the 240V/5OHz input power will be simulated to check whether it can still work well or not. The simulation waveforms under this situation are listed as following. 1. The wave form under full load situation (R=l500hms/f= 50Hz) Fig. 4.23 Full Load Simulation of V9,and ‘in (240V/5OHz) V1: Input Line Voltage (Volts) Input Line Current (Amperes) 91 400.00 200.00 0.00 -200.00 -400.00 ;/ ••- / \./ ::. -10.00 -____________ ______________________________________________________ ______________________ ______________________ 100.00 160.00 170.00 180.00 190.00 200.00 urn. (mn) 0.00 ——---—----— —________________________________________________________ 4.00 3.00 2.00 1.00 0.00 —‘ 0.00 F req mm en om (M Hz) 0.02 0.04 0.00 0.08 0.10 Chapter 4 Project Simulatioa 404.00 402.00 400.00 308.00 390.00 394.00 302.00 8.00 6.00 4.00 2.00 0.00 -2.00 350.00 —.-—-—— . :: 200.00 - ------ LL v V 150.00 160.00 170.00 180.00 100.00 200.00 time (ins) Fig. 4.23[A] Full Load Simulation of V0, ‘md and Vd (240V/SOHz) 1ind Rectified DC Current (Amperes) Vd: Rectified DC Voltage (Volts) V0: APFC Output Voltage (Volts) 100.00 180.00 170.00 18000 190.00 200.00 Tine (ms) r::: 92 Chapter 4 Project Simulation The wave form under half load situation (R=3000hms/f= 50Hz) 400.00 —,-—---——- ___________________ __________________ 200.00 ‘---‘-/ :“-; \ .\ -200.00 F \./ -400.00 4.00 2.00 0.00 -2.00 -4.00 0.00 0.02 0.04 0.00 0,08 0.10 Frequency (MHz) Fig. 4.24 Half Load Simulation of V and ‘in (240V/5OHz) 2. 150.00 180.00 170.00 180.00 190.00 Time(ms) 200.00 2.50 2.00 1.50 1.00 0.50 0.00 V: Input Line Voltage (Volts) I: Input Line Current (Amperes) 93 Chapter 4 Project Simulation 405.00 405.00 404.00 403.00 402.00 401.00 150.00 ird 4,00 3.00 2.00 1.00 0.00 -1.00 350.00 :: 200.00 : ‘tzz”” ----Iz--zzzzzz 150.00 160.00 170.00 180.00 100.00 200.00 Time (ins) Fig. 4.24[A] Half Load Simulation of V0, ‘md and Vd (240V/5OHz) lund: Rectified DC Current (Amperes) Vd: Rectified DC Voltage (Volts) V0: APFC Output Voltage (Volts) 150.00 170.00 180.00 100.00 200.00 Time (ins) 94 \____ ___ 3.00 2.00 1.00 0.00 -1.00 -2.00 -3.00 1.75 1.50 125 1.00 0.75 0.50 0.25 0.00 - -... - -.- .- 0.00 0.02 0.04 0.08 0.09 0.10 F,eq.oy (MHz) Fig. 4.25 One-third Load Simulation of V1and (240V/50Hz) V: Input Line Voltage (Volts) Input Line Current (Amperes) Chapter 4 Project Simulation 3. The wave form under one-third load situation (R=4500hms/f= 50Hz) 400.00 200.00 0.00 -2.00 -400.00 10.00 160.00 170.00 180,00 100.00 lime (ms) 200.00 95 Chapter 4 Project Simulation 408.00 407.08 406.00 406.00 404.00 403,00 2080] nd 360i10 :t::f:\::z7Th 200.00 ‘ /_ 150.00 160.00 170.00 100.00 190.00 200.00 Tn (rim) Fig. 4.25[A] One-third Load Simulation V0, ‘md and Vd (240V/S0Hz) [md: Rectified DC Current (Amperes) Vd: Rectified DC Voltage (Volts) V0: APFC Output Voltage (Volts) 150.00 160,00 170.00 100.08 190.00 Time (ins) 3.00 2.60 2.00 1.50 1.00 0.50 0.00 96 Chapter 4 Project Simulation In the end, the definition of these wave names will be listed again in the following so that it is convenient for others to check. V: Input Line Voltage (Volts) Ii. Input Line Current (Amperes) lind: Rectified DC Current (Amperes) V0: APFC Output Voltage (Volts) Vd: Rectified Half Sine Wave DC Voltage (Volts) All these results listed above suggest that this design is feasible and this circuit can work satisfactorily under the input line voltage range from 200Vrms to 23OVrms with line frequency of 60Hz or 50Hz. Next, experiments will be made to verify its performance and revise this project circuit further. 97 Chapter 5 Experimental Results Chapter 5 Experimental Results After the schematic design for this boost active power factor corrector in chapter 2 and careful revision for it by simulation in chapter 4, the final simulations under all cases are satisfactory. However, this does not imply that the project circuit is feasible and this project design is finished. If a final reasonable Boost APFC circuit is to be got, practical experiments must be made to verify the performance of this schematic circuit and revise it. The hardware implementation of this project is explained and all components for the whole circuit are chosen in chapter 3. The next step is to do experiments and adjust some component values so that the desired results can be got and finish this project design in the end. Due to the line frequency in our lab is 60Hz, I will make the project experiments for 60Hz only. Certainly, we can get the line frequency of 50Hz by electrical generator at first and make the 50Hz experiment to check the performance of the Boost APFC circuit. The simulations in chapter 4 suggest that this circuit performs well for 50Hz line frequency input power if it can work well for 60Hz line frequency because the difference between these two frequency values is small. Therefore, it will be enough to make this APFC circuit satisfy the project requirement for line frequency of 60Hz. It can be found this is another advantage for project simulation. 5.1 The Experimental Results for Current Sensing Resistor R of 0.1 Ohm and IGBT Gate Driving Resistor Rg of 150 Ohms The practical experiments are made to check whether the input voltage range and the load range of this designed project circuit can satisfy the requirement of the power factor corrector or not. The corresponding experimental results are as following. 98 Chapter 5 Experimental Results Fig. 5.1 Full Load Experimental Results of V1 and ‘in (7OVrmJ6OHZ) Vj (Cl Signal): Input Line Voltage (Volts) ‘in (C2 Signal): Input Line Current (Amperes) Here, the signal for Ci channel is input line voltage and the signal for C2 channel is input AC current. Another resistor (0.112) is used to measure the input current. It can be found that the input current wave is a sinusoidal wave and it tracks the input voltage wave form very well. This suggests that the input power factor will be nearly equal to unity. The disadvantage is that the input current includes harmonics. Measures should be taken to reduce it. This will be explained later. 1. The experimental results for full load situation (R= 1 500/f =60Hz/V=70V) Measure vIue P1 .freq(C1) 60.52243Hz I, P2:dut(C1) P3:mean(C1) P4:pkpk(C4) P5:- - - P6:- - - 0 0 99 Chapter 5 Experimental Results 2. The experimental results for full load situation (R=1500/f =6OHz/Vi=l47Vrms) •- lTLiltJ llh JJ1,1::[. - - il I I . :•J ii.. status Fig. 5.2 Full Load Experimental Results (l47VrmJ6OHz) V (Cl Signal): Input Line Voltage (Volts) (C2 Signal): Input Line Current (Amperes) V0: (C3 Signal): APFC Output Voltage (Volts) ... ‘iv: .1 Measure value i. P1 trsq(C1) P2:duu(C1) P3:mean(C1) P4:pkplqC4) 60.08027 Hz •1 201$ornMst 2W i. .3 [Ffj PS:- - - P6:- - - 0 0 rj Measure P1 :freq(C1) P2duty(C1) P3mean(C1) P4pkpk(C4) PS:- - - P6:- - - value 464.5 6Hz 0 0 statusa:.. 100 Chapter 5 Experimental Results Here, the signal for C1 channel is input line voltage; the signal for C2 channel is input current and it is measured with a resistor (ft 12); the signal for C3 channel is the output voltage for this active power factor corrector and it is measured with a voltage divider formed with two resistors (510k and lOk2). From these wave forms, it can be found that the input current can track the input voltage waveform and remain sinusoidal but with obvious harmonics. Certainly, high frequency switching current will produce harmonics, but the valid methods must be found to reduce it. Another characteristic for these waveforms is that the output voltage is not equal to 400 Volts. It can be found it is approximately equal to: V3 2 x 2.2 x = 229(V) (5-1) ‘inmax X 1.8 = 3.6(A) (5-2) = = 229x229 349.6(W) (5-3) R0 150 p = VinrwXIinmax = 147X3.6 374.2(W) (5-4) 1.414 1.414 Po34969 4% (55) Pin 374.2 It can be found that the efficiency for this APFC circuit under this situation is acceptable and this suggests that the input power factor is good. However, it can be found that the output power is less than 1kW and the maximum input voltage for this circuit to work normally is equal to rms 160 Volts. What is the reason for this unsatisfactory characteristic? How to solve this problem? This will be discussed in detail later. 3. The experimental results under three-quarters load situation (R=20001f= 60Hz/V=75VN1=15OVmis) After several experimental trial, it can be seen that the load range for this circuit to work normally under this situation (Rs=0.lO/Rg=l500) is full load (R=1500) to three quarters load (R=2000) and the input voltage range nearly remains the same. The output voltage nearly remains the same as before. The corresponding wave forms will be listed as following: 101 Chapter 5 Experimental Results Measure P1 :freq(C1) value 454.5 <Hz status Jt a 1 .L. 0 P3:msan(C1) P4:pkpk(C4) PS:- - - PS:- - - 0 0 Fig. 5.3 Three-quarters Load Experimental Results (75VrmJ6OHz) (Cl Signal): Input Line Voltage (Volts) ‘in (C2 Signal): Input Line Current (Amperes) V0: (C3 Signal): APFC Output Voltage (Volts) :. ‘ID. I.. ..... :..1{.; ... .. ..... H.. JLq. H Li . .ilH IiTl P1 :freq(C1) 60.1 4531 Hz P2:duly(C1) P3:mean(C1) P4:pkpk(C4) [% $bvittst I nfl status PS:- - - PS:- - - a . .,I.k .1 1._S .. L., — . . ..L ii .. P2duts’(Cl) 102 - zTh i. Lti1..H .i I i”t r JHL I 1 [P q111 Measure P1:freq(C1) P2:duty(C1) P3:mean(C1) P4:pkpk(C4) P5:--- PS:-- value 5995060 Hz 0 0 6 I.. .._. - ..1. _...L, J S — P1:freq(Cl) P2:duty(C1) P3:mean(C1) P4:pkpk(04) PS:--- PS:-- 454.5 kHZ 0 0 Fig. 5.3[A] Three-quarters Load Experimental Results (l5OVrmJ6OHz) (Cl Signal): Input Line Voltage (Volts) I (C2 Signal): Input Line Current (Amperes) V0: (C3 Signal): APFC Output Voltage (Volts) Chapter 5 Experimental Results tl1 I h M \ I j.. I -. 4- Measure status 103 Chapter 5 Experimental Results It can be seen that the phenomenon is the same as before. The input current tracks input voltage very well with sinusoidal waveform, but it has obvious harmonics. From this experimental wave form, it can be found that the output voltage nearly remains the same as the value under full load situation. Here, it can be taken the same value for it(V0=229Vots). The relevant values can be calculated as following: ‘inmax 0.2 X 1.5 ÷ 0.1 = 3.0(A) (5-6) = 229x229 262.2(W) (5-7) p = VinrmsXlinmax 150x3.o 318.2(W) (5-8) 1.414 1.414 = 82.4% (5-9) It can be found that the efficiency under three-quarters load situation is still acceptable. After many times trial, it can be seen that the input voltage range for the APFC circuit to work normally is about rms75Volts—l6OVolts. If the input voltage is more than rms 160 Volts, this circuit will not be able to work normally and the input current will become pulsed waveform. Here, the reason for this phenomenon will be explained. Because the power converter is a Boost converter, the output voltage must be always more than the input voltage for the converter to work normally; otherwise, the converter will not be able to work normally. When the input voltage is equal to rms 160 Volts, its maximum value is equal to: Vmmaxl.4rins226 Volts. The experimental results prove that this is always true for the boost converter. From the common knowledge of the boost converter, it is known that the output voltage is determined by the duty cycle D of the converter. The duty cycle D is controlled by the control circuit and the current sensing resistor in the main circuit together. From the measured results and calculated results, it can be found that the input power and output power are less than 1kW and output voltage is less than 400V, all these suggest that the duty cycle must be increased in order to increase the output voltage and output power. The fundamental measure is to reduce the value of current sensing resistor. This will increase the input current value and input power effectively. Certainly, the output power, the output voltage 104 Chapter 5 Experimental Results and the input working voltage will be increased. This will solve this question effectively. Generally speaking, there are two reasons for the obvious harmonics in the input current. The first one is because the output power and output voltage for this circuit is less than the specifications, but the circuit components values are designed for desired output power and output voltage. This means that the circuit does not work at the desired condition and this will produce the harmonics. The other reason is perhaps because of the value of gate driver resistance Rg is not appropriate. In the following, the answer will be found to solve this problem step by step. 5.2 The Experimental Results for Current Sensing Resistor R of 0.1 Ohm and IGBT Gate Driving Resistor Rg of Different Values Because the value of gate driving resistance Rg is important for the normal work of IGBT, it is useful to check the circuit performance under different values of Rg to ensure that the present value of Rg is appropriate; otherwise, the circuit will not be able to work normally even if the main circuit and the control circuit are all excellent combination. The experimental results for different values of Rg are listed as following. 1. The experimental results for full load situation (R= 1500[Rg=85Q/Vi 1 3OVrms) Measure P1 freq(C1) P2:duty(C1) P3 mean(C1) P4:pkpk(C4) value 59.921 0 Hz status Fig. 5.4 Full Load Experimental Results (130Vrms/Rg850) 1711111 :11 lii) P5--- P6:--- 0 0 105 Chapter 5 Experimental Results (Cl Signal): Input Line Voltage (Volts) ‘in (C2 Signal): Input Line Current (Amperes) Compared with Fig. 5.3, it can be found that the input current harmonic becomes more obvious. This suggests that it is not appropriate for this APFC circuit to choose the value of Rg lower than 150 Ohms. If a lower gate driving resistance for power switch IGBT is chosen, it can be found that the input current harmonics will become sharper and the input working voltage will be improved to some extent. 2. The experimental results for full load situation (Rl500IRg2700Nil5OVrms) In order to find an appropriate gate driving resistance value for the power switch IGBT, a higher value should be tried for Rg by experiment. Here, a value of 270 Ohms is chosen to make this experiment. The corresponding wave forms are as following. V1 (Cl Signal): Input Line Voltage (Volts) ‘in (C2 Signal): Input Line Current (Amperes) Measure P1 :freq(C1) P2:duty(C1) P3:mean(C1) P4:pkpk(C4) P5:- - - PS:- - - value 60.1 2506 Hz 0 0 status Fig. 5.5 Full Load Experimental Results (150VrmJRg=27O) 106 Chapter 5 Experimental Results P1:freq(C1) P2:duly(C1) P3:mean(C1) P4:pkpk(C4) P5:-- - PS:-- - 178.6kHz 0 0 Fig. 5.5[A] Full Load Experimental Results of V0 (150Vrms/Rg=27OC)) V1 (Cl Signal): Input Line Voltage (Volts) ‘in (C2 Signal): Input Line Current (Amperes) V0: (C3 Signal): APFC Output Voltage (Volts) It can be found that the input current harmonic is reduced a little for this case, however, the output voltage, input power and output power do not satisfy the specifications. L I... I .1,. .iI..j .. i... .1, ..I. 107 Chapter 5 Experimental Results 3. The experimental results under deficient load situation (R=1800/Rg=2700) I II ID —. Measure P1 :freq(C1) P3:mean(C1) P4pkpk(C4) P5:- - - PS:- - - value 59.881 67 Hz U 0 status Fig. 5.6 Deficient Load Experimental Results (R=18OCJV 96VrmsIRg27OC)) V (Cl Signal): Input Line Voltage (Volts) ‘in (C2 Signal): Input Line Current (Amperes) After several trials, it can be found the circuit working load range is: “R=150Q — 180Q” when gate driving resistance Rg is equal to 270 Ohms. Therefore, the load range is reduced a little for “Rg=27OQ” compared with the situation of “Rg=l5O2”. It can not solve the harmonics satisfactorily. Considering the waveforms and load range together, it can be found that it is appropriate to choose the gate driving resistance 150 Ohms for Rg for this 1 Kilowatts boost active power factor corrector. 5.3 The Experimental Results for Current Sensing Resistor R=O.O5f and Gate Driving Resistor Rg=lSOC) According to the project specification, measures should be taken to ensure this APFC circuit performs well for input voltage of “200Volts - 23OVolts” and reduce the input current harmonics as lower as possible. From the above discussion, it is known that P2:duty(C1) 108 Chapter 5 Experimental Results the main reason for these discomforts is because the input power is lower than the specified value. The current sensing resistance should be reduced so as to increase the input power and the output power up to the specified value and check whether the performance of this APFC circuit can satisfy the requirement or not. Certainly, this will need higher current level main power switch IGBT and input diode rectifier. The circuit performance for this situation (Rs0.O5Ohms) with current components is checked and the results are satisfactory. The input power and output power all reach the specifications and there is no input current harmonics. Certainly, the present IGBT and diode rectifier all fired when I test the circuit under full load situation and there is no time for me to record the wave forms. In the end, the half load situation (R0=3000) is chosen to make this experiment so as to record the wave forms of this circuit. The experimental results are as following: E P2duty(C1) P3:meari(C1) P4pkpk(C4) PU:- - - PU:- - - 0 0 Fig. 5.7 Half Load Experimental Results (22Vrms/300Q/Rg 150Q) V1 (Cl Signal): Input Line Voltage (Volts) ‘in (C2 Signal): Input Line Current (Amperes) From this experimental waveform, it can be seen that there is nearly no harmonics 1 1 P1 :freq(C1) 6.7690 kHz 109 Chapter 5 Experimental Results in the input current. The distortion of the input voltage is mainly because the diode rectifier and power switch IGBT fired. Therefore, there is no problem to get the satisfactory waveform if the higher current level diode rectifier and IGBT power switch are used in the experimental circuit. For the input power, it is equal to: p = VinmaxXInmax 30x3.8 = 570(W) (5-10)2 0.1x2 It can be found that it is correct for the half load situation of this project, so, this method can solve the input power problem effectively. There is no time to record the output voltage waveform before the bum-down of the diode rectifier and IGBT switch. However, the output voltage can be calculated approximately as following: p0 = (5-11) ..v=./PxRJO.9xP1 = /0.9 x 570 x 300 392.3(V) (5-12) Therefore, the output voltage can satisfy the project specification very well, too. For this case, it can be found that this circuit can work well from half load (R0=3000) to full load range (R0 = 1500). Therefore, the good choice for this project design is to choose the current sensing resistance value as “Rs=0.050” and the gate driving resistance value as “Rg= 1500”; then, this boost active power factor corrector can satisfy the project specification. Although the diode rectifier and IGBT switch fired shortly, a not very satisfactory waveform is recorded. This result proves that it is a satisfactory method to solve this question. If the higher current level diode rectifier and power switch IGBT are used to make the experiment, the satisfactory waveforms can be recorded. Since this is only to develop the APFC circuit, it will be enough to find the correct answer to the problem. There is no need to spend money to buy expensive components to record the satisfactory waveforms. They can be recorded conveniently when commercial product is built. From all the experimental results listed above, it can be seen that this Boost APFC 110 Chapter 5 Experimental Results circuit can satisfy the project specifications in the required input line voltage range and the wide load scope. Therefore, the final revised circuit is feasible for this project. This boost active power factor corrector can be used in North America (AC12OV/6OHz), Asia (AC22OV/5OHz) and Europe (AC23OV/6OHz) directly. Compared with the simulation for this Boost APFC in Chapter 4, it can be found they are nearly the same from half load to full load range. The main difference between the experiment and simulation is that the current sensing resistance must be reduced to O.O5Ohm; otherwise, this circuit can not provide 1Kw output power. The reason is that simulation can not include all factors of the practical circuit. There is a great deal of flexibility in the choice of current sensing resistance. This has to be solved by experiment. From this project design, it can be found that simulation is a very useful tool for practical design. A lot of element values can be determined by simulation directly; this will save a lot of time and money in project design. However, some component values have to be determined by experiment; this suggests that simulation can not replace experiment for the project design. A good engineer should combine the simulation and experiment effectively to solve the practical engineering problems. 111 Chapter 6 Conclusion and Future Work Chapter 6 Conclusion and Future Work 6.1 Conclusion In this thesis, the development of a Boost Active Power Factor Corrector has been considered. A number of issues regarding the implementation of APFC circuit have been investigated. A brief conclusion opens in this section to summarize the major conclusive remarks obtained in the early chapters. In chapter 2, a boost converter topology is presented as the main circuit of the active power factor corrector after theoretical analysis and comparison of several commonly used converters. After careful studies of several control methods, the average current control method is chosen to implement the control circuit for this Boost APFC project. Meanwhile, a theoretical calculation of the important component values in this active power factor corrector is described. The next chapter explains the method to choose important components for this boost APFC circuit in detail. Then, the basic knowledge of control chip UC3854 is introduced because the control circuit is formed with it. Therefore, its basic working theory and application requirement should be understood before it is used to build the whole control circuit. In chapter 4, a detailed simulation is given for this APFC circuit. In order to make this circuit multi-usable, the European Standards, Asian Standards and North American Standards are taken into account and make two sets of simulation (230V/5OHz/6OFIz; 220V/5011z/6OHz). Because the load maybe change in practical application, it is necessary to ensure that the PFC circuit can still work satisfactorily when the load changes in an allowable scope. The simulation is made for three different cases (full load, 112 Chapter 6 Conclusion and Future Work half load and one-third load) to verify that this circuit can perform well and satisfy the load change requirement. In chapter 5, experiments are made to check this project design for two sets of current sensing resistors (0. lOhms/0.O5Ohms) and several gate driving resistances. The final results are satisfactory. As for the 50Hz input power situation, no experiment was made to verify the performance of this boost active power factor corrector because there is only 60Hz line frequency power to use directly. From the simulations for these two situations, it can be inferred that the circuit will perform well for 50Hz line frequency input power, too. Certainly, the performance of this Boost APFC for 50Hz line frequency input power can be verified with an electrical generator which produces 50Hz line frequency input power at first. Although the greatest efforts have been made in components selection and schematic circuit design of this project, some uncertainty still exists in the practical implementation. This is mainly for the choice of suitable values for current sensing resistor Rs and gate driving resistor R8. These problems have been solved step by step and the experiment is finished in the end. The experience gained from this implementation will give me some guidelines to the future work of IGBT related converters and the UC3854 related controllers. 6.2 Future Work for This Project In order to make this boost active power factor corrector a commercial product, the next step is to build a PCB control circuit including the basic control chip UC3854 and relevant components to reduce the layout problem and improve the reliability of the product. Because the switching frequency of the boost converter is high (For this project, it is equal to 100 kHz), the switching loss will become more serious compared with other losses of the boost active power factor corrector. If we expect to improve the efficiency and switching frequency further, measures should be taken to reduce the switching loss greatly. An effective method to solve this question is to use Zero-Voltage-Switching technology [2], [3], [4]. In this way, the switching frequency of the power converter can 113 Chapter 6 Conclusion and Future Work be improved and the product volume can be reduced greatly without reducing the converter efficiency. The ZVS can be realized by adding a parallel snubber circuit across the main switch IGBT and revise the control circuit according to the real project situation. In this way, the voltage across the IGBT can be reduced to zero before its Turn-on” signal and make it realize “Turn-on” under zero voltage condition; thus, the switching loss will be reduced greatly and the efficiency will be improved [2], [3], [4]. The basic control chip UC3855 can be used to build the effective control circuit for this ZVS boost active power factor corrector. If there is a company interested in this ZVS PFC circuit, it can be improved in this way. 114 References References [1] Kuiyuan Wu and William G. Dunford, “The Application and Characteristic of Several PFC Methods,” CD-000655, IEEE ISlE 2008, Cambridge, UK [2] Kuiyuan Wu and William G. Dunford, “A New Topology to Widen ZVS-PWM Scope,” HD-003999, WEE IECON 2008, Florida, USA [3] Kuiyuan Wu and William G. Dunford, “Analysis of an Effective Topology to Enlarge ZVS Scope,” TPEL-Reg-2008-05-0234, WEE Transactions on Power Electronics, 2008 [4] Kuiyuan Wu and William G. Dunford, “An Unusual Full Bridge Converter to Realize ZVS in Large Load Scope,” Ref_i 82, Asian Power Electronics Journal, 2008 [Acceptedl [51 L. H. Dixon, “High Power Factor Switching Pre-regulator Design Optimization,” Unitrode Power Supply Design Seminar Manual SEM700, 1990 [61 5. Freeland, “Input-Current Shaping for Single-Phase Ac-Dc Power Converters,” Ph.D. Thesis, California Institute of Technology, 1988 [7] E. YANG, Y. JIANG, G.HUA and F C. LEE, “Isolated Boost Circuit for Power Factor Correction,” WEE Applied Power Electronics Conference, 1993 Record, pp. 196-203. [81 Michail A. Slonim, P.P. Biringer: “Harmonics of Cyclo Converter Voltage Wave Form (New Method of Analysis)”, IEEE Trans. md. Electron. Contr. Instrum. Vol. IECI-F27, NO.2, May, 1980 [91 Ding Dao Hong: “Power Electronic Technology”, Aeronautical Industry Press, 1992. [101 FYUAN,D.Y.CHEN,Y.WU and Y.CHEN, “A Procedure for Designing EMI Filters for Ac Line Applications,” IEEE Transactions on Power Electronics, Vol 11, No.1, pp.l’7O-l8l, January 1996 [ill Robert W. Erickson, Dragan Maksimovic, Fundamentals of Power Electronics, Springer Science + Business Media, Inc., 2001 [12] M.NAVE, “Power Line Filter Design for Switched Mode Power Supplies,” New York: Van Nostrand Reinhold, 1991. 115 References [131 Graham C. Goodwin, Stefan F Graebe and Mario E. Salgado, Control System Design, Prentice-Hall, Inc. 2001 [14] Application Note, Use Gate Charge to Design the Gate Drive Circuit for Power MOSFETs and IGBTs, International rectifier, see ttp://www.irf.comltechnical-info/appnotes/an-944.pdf [15] Application Note, How to Use IGBT Modules, Powerex mc, 1999 116 Appendix A Permeability versus DC Bias Curve Appendix A Permeability versus DC Bias Curve In order to be convenient to check this property of Kool Mi Cores for MAGNETICS company, this curve is appended as following: This figure is removed because of no copyright permission. Fig. 1 Permeability versus DC Bias Curve 117 Appendix B Permeability versus Frequency Curve Appendix B Permeability versus Frequency Curve Because the switching frequency is 100kHz, this curve of Kool M1i core is appended in the following so as to be convenient to check. This figure is removed because of no copyright permission. Fig. 2 Permeability versus Frequency Curve 118 Appendix C Normal Magnetization Curve Appendix C Normal Magnetization Curve In order to be convenient to check the normal magnetization characteristic of Kool Mp cores, this curve is appended as following: This figure is removed because of no copyright permission. Fig. 3 Normal Magnetization Curve 119
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Design and implementation of a boost active power factor corrector Wu, Kuiyuan 2008
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Title | Design and implementation of a boost active power factor corrector |
Creator |
Wu, Kuiyuan |
Publisher | University of British Columbia |
Date Issued | 2008 |
Description | The input current harmonics of the rectifier are very harmful. Not only do they reduce the power factor of the AC-DC converter and cause a lot of electrical energy loss, but also damage other devices and pollute the line power system. Measures should be taken to reduce these harmonics. The commonly used method is to design an effective PFC circuit for the AC-DC converter. In this thesis, a Boost APFC circuit will be discussed in detail. This thesis presents a solution to design an appropriate APFC circuit with one Kilowatts output power and make this APFC circuit work satisfactorily from full load to half load scope. In this thesis, a detailed design process will be described for this project, including topology choice, theoretical calculation of the main components values, the determination of the main components for this circuit, circuit simulation and experimental verification. In the end, a concise conclusion will be made and the future improvement for this project will be introduced. Several commonly used control methods for the Active Power Factor Corrector circuit will be compared and then a good method will be chosen for this project. The average current control method is finally decided to use for this circuit and the basic control chip UC3854 is used to build the control circuit for this project. The simulation and the final experimental results all verify that this is an appropriate choice for this project. According to the schematic design and the simulation revision, a test prototype is built to verify the performance. Several tests are implemented and the final experimental results indicate that this circuit design can satisfy the project specification and it is feasible for this project. |
Extent | 2685959 bytes |
Genre |
Thesis/Dissertation |
Type |
Text |
FileFormat | application/pdf |
Language | eng |
Date Available | 2009-03-06 |
Provider | Vancouver : University of British Columbia Library |
Rights | Attribution-NonCommercial-NoDerivatives 4.0 International |
DOI | 10.14288/1.0067038 |
URI | http://hdl.handle.net/2429/5631 |
Degree |
Master of Applied Science - MASc |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
GraduationDate | 2008-11 |
Campus |
UBCV |
Scholarly Level | Graduate |
Rights URI | http://creativecommons.org/licenses/by-nc-nd/4.0/ |
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