UBC Theses and Dissertations
Cascode voltage switch logic circuits Chu, Kan Man
Cascode voltage switch (CVS) logic is a CMOS circuit technique which has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation and logic flexibility. This thesis presents two new procedures for constructing differential CVS circuits to perform random logic functions. The first procedure makes use of a Karnaugh map and the second procedure is a tabular method based on the Quine-McCluskey approach. Both static and dynamic circuit techniques employing the CVS logic concept are discussed. Some wiring and layout methods based on theoretical graph models are presented to ensure the wirability of CVS circuits. An 8x8 NORA CVS multiplier has been designed using the 3μm CMOS technology of Northern Telecom. The chip measures 4mm by 4mm and simulations indicate that it can be run at a throughput rate of 50MHz.
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