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Networks on Chip : emerging interconnect infrastructures for MP-SoC platforms Pande, Partha Pratim

Abstract

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for System on Chip (SoC) design. The state of the art has reached a point where commercial designs are readily integrating in the range of 10-100 embedded functional/storage blocks in a single SoC. As a result of this enormous degree of integration, several industrial and academic research groups are striving to develop efficient communication architectures, in some cases optimized for specific applications. Global synchronization is becoming increasingly complex due to process variability and power dissipation, and cross-chip signaling can no longer be achieved in a single clock cycle. Thus, system design must incorporate networking and distributed computation paradigms with communication structures designed first and then functional blocks integrated into the communication backbone. The emerging Network on chip (NoC) design methodology is a step in this direction. The practical implementation and adoption of the NoC design paradigm is faced with various unsolved issues related to design methodologies, test strategies, and dedicated CAD tools. The focus of this research is on design aspects and architectural issues of this new paradigm. The contributions of this research are two fold. First is the performance evaluation of various NoC architectures in regard to data rates, latency, silicon area overhead, and energy dissipation and second is the quantification of the timing characteristics of NoC architectures. Through detailed circuit design and timing analysis, this research has established that different NoC architectures proposed to date are guaranteed to achieve the high-performance clock cycle requirements in a given CMOS technology, usually specified in normalized units of FO4 (fan out of 4) delays.

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