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A VLSI receiver architecture for high speed ATM computer networks

University of British Columbia

Network communication bandwidths are surpassing the computational power of host systems. This improvement in communications bandwidth creates a need to develop ded icated communications processors which service the network without serious degradation of throughput. Asynchronous Transfer Mode(ATM) is a new Broadband Integrated Services Digital Network(BISDN) protocol specified to operate over fibre lines at rates of 155 Mbps or 622 Mbps. As the high-speed ATM networking protocol gains widespread acceptance in the networking community, dedicated high-speed protocol processing hardware is required to process ATM’s small 53 byte cells. In ATM networks, the problem of reassembly of cells at network speeds on the receiver side, is of particular significance. The Adaptation Layer is responsible for cell reassembly. In this thesis, a VLSI architecture for ATM receiver adap tation layer processing is presented. A fine grained parallel architecture is employed in our receiver design. Improvements over other ATM receiver designs have been made in our de sign. Potential bottlenecks in existing designs have been identified and an effort is made to overcome these problems. Problems such as parallel CRC computation, fast Virtual Circuit Identifier (VCI) mapping, and effective memory architectures are resolved. The proposed design is shown to operate at high throughputs ranging from 264.46 Mbps to well over 622 Mbps for sustained network data. The design is modelled at two levels so that low level timing details can be determined and high level traffic behavior can be monitored.

Thesis/Dissertation

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2009-02-26

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http://hdl.handle.net/2429/5199

Electrical and Computer Engineering

University of British Columbia

UBCV

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