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Application of generalized power-delay metrics to supply and threshold selection in deep submicron CMOS Sengupta, Dipanjan
Abstract
Power consumption has become as important as performance in todays deep submicron designs. As a result, high-level techniques and models must be developed to evaluate design changes in terms of power (energy) and performance tradeoff early in the design process. Recently, designers have been using the energy-delay product as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more traditional power-delay product. As the industry moves to 90nm technology and encountered higher leakage currents, it is appropriate to revisit existing design metrics. In this thesis, a more general view of power and delay metrics for design optimization has been provided along with how these metrics can be used for design optimization. Supply (VDD) and threshold (VT) voltage scaling are two popular methodologies of power reduction. As such, the effect on power and frequency are analyzed and the feasible region of operation is identified in the VDD vs. VT plane. A fundamental relationship is established between the optimal operating points and the generalized design metrics. In addition, new power and delay models are developed for logic blocks that incorporate the effect of VDD and VT . The effect of optimization on power and delay with respect to process, temperature and voltage variation has also been investigated.
Item Metadata
Title |
Application of generalized power-delay metrics to supply and threshold selection in deep submicron CMOS
|
Creator | |
Publisher |
University of British Columbia
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Date Issued |
2005
|
Description |
Power consumption has become as important as performance in todays deep submicron
designs. As a result, high-level techniques and models must be developed to evaluate design
changes in terms of power (energy) and performance tradeoff early in the design process.
Recently, designers have been using the energy-delay product as a metric of goodness for
CMOS designs due to certain perceived shortcomings of the more traditional power-delay
product. As the industry moves to 90nm technology and encountered higher leakage currents, it
is appropriate to revisit existing design metrics. In this thesis, a more general view of power and
delay metrics for design optimization has been provided along with how these metrics can be
used for design optimization.
Supply (VDD) and threshold (VT) voltage scaling are two popular methodologies of power
reduction. As such, the effect on power and frequency are analyzed and the feasible region of
operation is identified in the VDD vs. VT plane. A fundamental relationship is established between
the optimal operating points and the generalized design metrics. In addition, new power and
delay models are developed for logic blocks that incorporate the effect of VDD and VT . The
effect of optimization on power and delay with respect to process, temperature and voltage
variation has also been investigated.
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Genre | |
Type | |
Language |
eng
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Date Available |
2009-12-15
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Provider |
Vancouver : University of British Columbia Library
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Rights |
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.
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DOI |
10.14288/1.0065598
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URI | |
Degree | |
Program | |
Affiliation | |
Degree Grantor |
University of British Columbia
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Graduation Date |
2005-11
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Campus | |
Scholarly Level |
Graduate
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Aggregated Source Repository |
DSpace
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Item Media
Item Citations and Data
Rights
For non-commercial purposes only, such as research, private study and education. Additional conditions apply, see Terms of Use https://open.library.ubc.ca/terms_of_use.